diff --git a/Makefile b/Makefile index 2830603..eb46c5b 100644 --- a/Makefile +++ b/Makefile @@ -152,12 +152,17 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex #MEMORY_SIZE=393216 #RAM_INIT_FILE=micropython/firmware.hex -FPGA_TARGET ?= ORANGE-CRAB +FPGA_TARGET ?= ORANGE-CRAB-0.21 # FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5 # with yosys, so make it smaller for now as a workaround. ICACHE_NUM_LINES=4 +clkgen=fpga/clk_gen_ecp5.vhd +toplevel=fpga/top-generic.vhdl +dmi_dtm=dmi_dtm_dummy.vhdl +LITEDRAM_GHDL_ARG= + # OrangeCrab with ECP85 (original v0.0 with UM5G-85 chip) ifeq ($(FPGA_TARGET), ORANGE-CRAB) RESET_LOW=true @@ -175,15 +180,18 @@ endif ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21) RESET_LOW=true CLK_INPUT=48000000 -CLK_FREQUENCY=40000000 -LPF=constraints/orange-crab.lpf +CLK_FREQUENCY=48000000 +LPF=constraints/orange-crab-0.2.lpf PACKAGE=CSFBGA285 -NEXTPNR_FLAGS=--85k --speed 8 --freq 40 +NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg DFU_VENDOR=1209 DFU_PRODUCT=5af0 ECP_FLASH_OFFSET=0x80000 +toplevel=fpga/top-orangecrab0.2.vhdl +litedram_target=orangecrab-85-0.2 +soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v endif # ECP5-EVN @@ -198,12 +206,17 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg endif +ifneq ($(litedram_target),) +soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \ + litedram/generated/$(litedram_target)/litedram-initmem.vhdl +soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v +LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true +endif + GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \ - -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) + -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \ + $(LITEDRAM_GHDL_ARG) -clkgen=fpga/clk_gen_ecp5.vhd -toplevel=fpga/top-generic.vhdl -dmi_dtm=dmi_dtm_dummy.vhdl ifeq ($(FPGA_TARGET), verilator) RESET_LOW=true @@ -216,10 +229,10 @@ fpga_files = fpga/soc_reset.vhdl \ fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \ nonrandom.vhdl -synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) +synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" + $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)" microwatt.v: $(synth_files) $(RAM_INIT_FILE) $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" diff --git a/constraints/orange-crab-0.2.lpf b/constraints/orange-crab-0.2.lpf new file mode 100644 index 0000000..dbee9a9 --- /dev/null +++ b/constraints/orange-crab-0.2.lpf @@ -0,0 +1,225 @@ +LOCATE COMP "ext_clk" SITE "A9"; +IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33; + +// LOCATE COMP "ext_rst_n" SITE "J2"; // io_13 +// IOBUF PORT "ext_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +// user_button as reset +LOCATE COMP "ext_rst_n" SITE "J17"; +IOBUF PORT "ext_rst_n" IO_TYPE=SSTL135_I; + +LOCATE COMP "usb_d_p" SITE "N1"; +LOCATE COMP "usb_d_n" SITE "M2"; +LOCATE COMP "usb_pullup" SITE "N2"; + +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; + +LOCATE COMP "led0_g" SITE "M3"; +LOCATE COMP "led0_r" SITE "K4"; +LOCATE COMP "led0_b" SITE "J3"; + +IOBUF PORT "led0_g" IO_TYPE=LVCMOS33; +IOBUF PORT "led0_g" IO_TYPE=LVCMOS33; +IOBUF PORT "led0_b" IO_TYPE=LVCMOS33; + +// discontinuous gpio numbers, match orangecrab litex platform +LOCATE COMP "pin_gpio_0" SITE "N17"; // tx +LOCATE COMP "pin_gpio_1" SITE "M18"; // rx +LOCATE COMP "pin_gpio_2" SITE "C10"; // sda +LOCATE COMP "pin_gpio_3" SITE "C9"; // scl +// +LOCATE COMP "pin_gpio_5" SITE "B10"; // io_5 +LOCATE COMP "pin_gpio_6" SITE "B9"; // ... +// +LOCATE COMP "pin_gpio_9" SITE "C8"; // +LOCATE COMP "pin_gpio_10" SITE "B8"; // +LOCATE COMP "pin_gpio_11" SITE "A8"; // +LOCATE COMP "pin_gpio_12" SITE "H2"; // +LOCATE COMP "pin_gpio_13" SITE "J2"; // io_13 +LOCATE COMP "pin_gpio_14" SITE "N15"; // miso +LOCATE COMP "pin_gpio_15" SITE "R17"; // sck +LOCATE COMP "pin_gpio_16" SITE "N16"; // mosi + +LOCATE COMP "pin_io_a0" SITE "L4"; +LOCATE COMP "pin_io_a1" SITE "N3"; +LOCATE COMP "pin_io_a2" SITE "N4"; +LOCATE COMP "pin_io_a3" SITE "H4"; +LOCATE COMP "pin_io_a4" SITE "G4"; +LOCATE COMP "pin_io_a5" SITE "T17"; + +IOBUF PORT "pin_gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_2" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_3" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_14" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_15" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_gpio_16" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a4" IO_TYPE=LVCMOS33; +IOBUF PORT "pin_io_a5" IO_TYPE=LVCMOS33; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +LOCATE COMP "ddram_a[1]" SITE "D2"; +LOCATE COMP "ddram_a[2]" SITE "D3"; +LOCATE COMP "ddram_a[3]" SITE "A3"; +LOCATE COMP "ddram_a[4]" SITE "A4"; +LOCATE COMP "ddram_a[5]" SITE "D4"; +LOCATE COMP "ddram_a[6]" SITE "C3"; +LOCATE COMP "ddram_a[7]" SITE "B2"; +LOCATE COMP "ddram_a[8]" SITE "B1"; +LOCATE COMP "ddram_a[9]" SITE "D1"; +LOCATE COMP "ddram_a[10]" SITE "A7"; +LOCATE COMP "ddram_a[11]" SITE "C2"; +LOCATE COMP "ddram_a[12]" SITE "B6"; +LOCATE COMP "ddram_a[13]" SITE "C1"; +LOCATE COMP "ddram_a[14]" SITE "A2"; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST; + +LOCATE COMP "ddram_ba[0]" SITE "D6"; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +LOCATE COMP "ddram_cas_n" SITE "D13"; +LOCATE COMP "ddram_cs_n" SITE "A12"; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +LOCATE COMP "ddram_ras_n" SITE "C12"; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; + +// from litex platform, termination disabled to reduce heat +LOCATE COMP "ddram_dq[0]" SITE "C17"; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF; + +LOCATE COMP "ddram_dqs_n[0]" SITE "A16"; +LOCATE COMP "ddram_dqs_n[1]" SITE "H17"; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF; + +LOCATE COMP "ddram_clk_p" SITE "J18"; +LOCATE COMP "ddram_clk_n" SITE "K18"; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I SLEWRATE=FAST; +IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL135D_I SLEWRATE=FAST; + +LOCATE COMP "ddram_cke" SITE "D18"; +LOCATE COMP "ddram_odt" SITE "C13"; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I SLEWRATE=FAST; + +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST; + +// We use USRMCLK instead for clk +// LOCATE COMP "spi_flash_clk" SITE "U16"; +// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_cs_n" SITE "U17"; +IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_mosi" SITE "U18"; +IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_miso" SITE "T18"; +IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_wp_n" SITE "R18"; +IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spi_flash_hold_n" SITE "N18"; +IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "sdcard_data[0]" SITE "J1"; +LOCATE COMP "sdcard_data[1]" SITE "K3"; +LOCATE COMP "sdcard_data[2]" SITE "L3"; +LOCATE COMP "sdcard_data[3]" SITE "M1"; +LOCATE COMP "sdcard_cmd" SITE "K2"; +LOCATE COMP "sdcard_clk" SITE "K1"; +LOCATE COMP "sdcard_cd" SITE "L1"; + +IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33; diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl new file mode 100644 index 0000000..f4097db --- /dev/null +++ b/fpga/top-orangecrab0.2.vhdl @@ -0,0 +1,511 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_INPUT : positive := 100000000; + CLK_FREQUENCY : positive := 100000000; + HAS_FPU : boolean := true; + HAS_BTC : boolean := false; + USE_LITEDRAM : boolean := true; + NO_BRAM : boolean := true; + SCLK_STARTUPE2 : boolean := false; + SPI_FLASH_OFFSET : integer := 4194304; + SPI_FLASH_DEF_CKDV : natural := 1; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 0; + UART_IS_16550 : boolean := true; + HAS_UART1 : boolean := false; + USE_LITESDCARD : boolean := true; + ICACHE_NUM_LINES : natural := 64; + NGPIO : natural := 0 + ); + port( + ext_clk : in std_ulogic; + ext_rst_n : in std_ulogic; + + -- UART0 signals: + pin_gpio_0 : out std_ulogic; + pin_gpio_1 : in std_ulogic; + + -- LEDs + led0_b : out std_ulogic; + led0_g : out std_ulogic; + led0_r : out std_ulogic; + + -- SPI + spi_flash_cs_n : out std_ulogic; + spi_flash_mosi : inout std_ulogic; + spi_flash_miso : inout std_ulogic; + spi_flash_wp_n : inout std_ulogic; + spi_flash_hold_n : inout std_ulogic; + + -- SD card wires + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(13 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + -- only the positive differential pin is instantiated + --ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + --ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + + ddram_gnd : out std_ulogic_vector(1 downto 0); + ddram_vccio : out std_ulogic_vector(5 downto 0) + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- External IOs from the SoC + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + signal wb_ext_is_dram_csr : std_ulogic; + signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_sdcard : std_ulogic; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- Status LED + signal led0_b_pwm : std_ulogic; + signal led0_r_pwm : std_ulogic; + signal led0_g_pwm : std_ulogic; + + -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise + signal pwm_counter : std_ulogic_vector(8 downto 0); + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- GPIO + signal gpio_in : std_ulogic_vector(NGPIO - 1 downto 0); + signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0); + signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; + + COMPONENT USRMCLK + PORT( + USRMCLKI : IN STD_ULOGIC; + USRMCLKTS : IN STD_ULOGIC + ); + END COMPONENT; + attribute syn_noprune: boolean ; + attribute syn_noprune of USRMCLK: component is true; + +begin + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + HAS_SPI_FLASH => true, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1, + HAS_SD_CARD => USE_LITESDCARD, + ICACHE_NUM_LINES => ICACHE_NUM_LINES, + HAS_SHORT_MULT => true, + NGPIO => NGPIO + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => pin_gpio_0, + uart0_rxd => pin_gpio_1, + + -- UART1 signals + --uart1_txd => uart_pmod_tx, + --uart1_rxd => uart_pmod_rx, + + -- SPI signals + spi_flash_sck => spi_sck, + spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- GPIO signals + gpio_in => gpio_in, + gpio_out => gpio_out, + gpio_dir => gpio_dir, + + -- External interrupts + ext_irq_sdcard => ext_irq_sdcard, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + + -- IO wishbone + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_sdcard => wb_ext_is_sdcard, + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out, + + alt_reset => core_alt_reset + ); + + -- SPI Flash + -- + spi_flash_cs_n <= spi_cs_n; + spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z'; + spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z'; + spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z'; + spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z'; + spi_sdat_i(0) <= spi_flash_mosi; + spi_sdat_i(1) <= spi_flash_miso; + spi_sdat_i(2) <= spi_flash_wp_n; + spi_sdat_i(3) <= spi_flash_hold_n; + + uclk: USRMCLK port map ( + USRMCLKI => spi_sck, + USRMCLKTS => '0' + ); + + nodram: if not USE_LITEDRAM generate + signal ddram_clk_dummy : std_ulogic; + begin + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => CLK_INPUT, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + led0_b_pwm <= '1'; + led0_r_pwm <= '1'; + led0_g_pwm <= '0'; + core_alt_reset <= '0'; + + end generate; + + has_dram: if USE_LITEDRAM generate + signal dram_init_done : std_ulogic; + signal dram_init_error : std_ulogic; + signal dram_sys_rst : std_ulogic; + signal rst_gen_rst : std_ulogic; + begin + + -- Eventually dig out the frequency from + -- litesdram generate.py sys_clk_freq + -- but for now, assert it's 48Mhz for orangecrab + assert CLK_FREQUENCY = 48000000; + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => 18, + SOC_RESET_BITS => 1 + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => rst_gen_rst + ); + + -- Generate SoC reset + soc_rst_gen: process(system_clk) + begin + if ext_rst_n = '0' then + soc_rst <= '1'; + elsif rising_edge(system_clk) then + soc_rst <= dram_sys_rst or not system_clk_locked; + end if; + end process; + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 14, + DRAM_DLINES => 16, + DRAM_PORT_WIDTH => 128, + NUM_LINES => 8, -- reduce from default of 64 to make smaller/timing + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk_in => ext_clk, + rst => pll_rst, + system_clk => system_clk, + system_reset => dram_sys_rst, + core_alt_reset => core_alt_reset, + pll_locked => system_clk_locked, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_ext_io_in, + wb_ctrl_out => wb_dram_ctrl_out, + wb_ctrl_is_csr => wb_ext_is_dram_csr, + wb_ctrl_is_init => wb_ext_is_dram_init, + + init_done => dram_init_done, + init_error => dram_init_error, + + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_clk_p => ddram_clk_p, + -- only the positive differential pin is instantiated + --ddram_dqs_n => ddram_dqs_n, + --ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + + ddram_reset_n => ddram_reset_n + ); + + ddram_gnd <= "00"; + -- for power consumption. + -- https://github.com/orangecrab-fpga/orangecrab-hardware/issues/19#issuecomment-683479378 + ddram_vccio <= "111111"; + + led0_b_pwm <= not dram_init_done; + led0_r_pwm <= dram_init_error; + led0_g_pwm <= dram_init_done and not dram_init_error; + + end generate; + + + -- SD card pmod + has_sdcard : if USE_LITESDCARD generate + component litesdcard_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + -- wishbone for accessing control registers + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + -- wishbone for SD card core to use for DMA + wb_dma_adr : out std_ulogic_vector(29 downto 0); + wb_dma_dat_w : out std_ulogic_vector(31 downto 0); + wb_dma_dat_r : in std_ulogic_vector(31 downto 0); + wb_dma_sel : out std_ulogic_vector(3 downto 0); + wb_dma_cyc : out std_ulogic; + wb_dma_stb : out std_ulogic; + wb_dma_ack : in std_ulogic; + wb_dma_we : out std_ulogic; + wb_dma_cti : out std_ulogic_vector(2 downto 0); + wb_dma_bte : out std_ulogic_vector(1 downto 0); + wb_dma_err : in std_ulogic; + -- connections to SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + irq : out std_ulogic + ); + end component; + + signal wb_sdcard_cyc : std_ulogic; + signal wb_sdcard_adr : std_ulogic_vector(29 downto 0); + + begin + litesdcard : litesdcard_core + port map ( + clk => system_clk, + rst => soc_rst, + wb_ctrl_adr => wb_sdcard_adr, + wb_ctrl_dat_w => wb_ext_io_in.dat, + wb_ctrl_dat_r => wb_sdcard_out.dat, + wb_ctrl_sel => wb_ext_io_in.sel, + wb_ctrl_cyc => wb_sdcard_cyc, + wb_ctrl_stb => wb_ext_io_in.stb, + wb_ctrl_ack => wb_sdcard_out.ack, + wb_ctrl_we => wb_ext_io_in.we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + wb_dma_adr => wb_sddma_nr.adr, + wb_dma_dat_w => wb_sddma_nr.dat, + wb_dma_dat_r => wb_sddma_ir.dat, + wb_dma_sel => wb_sddma_nr.sel, + wb_dma_cyc => wb_sddma_nr.cyc, + wb_dma_stb => wb_sddma_nr.stb, + wb_dma_ack => wb_sddma_ir.ack, + wb_dma_we => wb_sddma_nr.we, + wb_dma_cti => open, + wb_dma_bte => open, + wb_dma_err => '0', + sdcard_data => sdcard_data, + sdcard_cmd => sdcard_cmd, + sdcard_clk => sdcard_clk, + sdcard_cd => sdcard_cd, + irq => ext_irq_sdcard + ); + + -- Gate cyc with chip select from SoC + wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard; + + wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0); + + wb_sdcard_out.stall <= not wb_sdcard_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_sddma_out <= wb_sddma_nr; + if wb_sddma_stb_sent = '1' or + (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then + wb_sddma_out.stb <= '0'; + end if; + if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then + wb_sddma_stb_sent <= '0'; + elsif wb_sddma_in.stall = '0' then + wb_sddma_stb_sent <= wb_sddma_nr.stb; + end if; + wb_sddma_ir <= wb_sddma_in; + end if; + end process; + + end generate; + + -- Mux WB response on the IO bus + wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_dram_ctrl_out; + + leds_pwm : process(system_clk) + begin + if rising_edge(system_clk) then + pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1); + if pwm_counter(8 downto 4) = "00000" then + led0_b <= led0_b_pwm; + led0_r <= led0_r_pwm; + led0_g <= led0_g_pwm; + else + led0_b <= '0'; + led0_r <= '0'; + led0_g <= '0'; + end if; + end if; + end process; + +end architecture behaviour; diff --git a/litedram/gen-src/acorn-cle-215.yml b/litedram/gen-src/acorn-cle-215.yml index 0e3e9eb..034995c 100644 --- a/litedram/gen-src/acorn-cle-215.yml +++ b/litedram/gen-src/acorn-cle-215.yml @@ -31,6 +31,7 @@ "user_ports": { "native_0": { "type": "native", + "block_until_ready": False, }, }, } diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index 22a0190..217d3eb 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -31,6 +31,7 @@ "user_ports": { "native_0": { "type": "native", + "block_until_ready": False, }, }, } diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index 2808f2a..0710b6a 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -100,7 +100,7 @@ def generate_one(t): def main(): - targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'sim'] + targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2', 'sim'] for t in targets: generate_one(t) diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml index ac1deeb..5acfc58 100644 --- a/litedram/gen-src/genesys2.yml +++ b/litedram/gen-src/genesys2.yml @@ -31,6 +31,7 @@ "user_ports": { "native_0": { "type": "native", + "block_until_ready": False, }, }, } diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 3752104..0772c96 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -31,6 +31,7 @@ "user_ports": { "native_0": { "type": "native", + "block_until_ready": False, }, }, } diff --git a/litedram/gen-src/orangecrab-85-0.2.yml b/litedram/gen-src/orangecrab-85-0.2.yml new file mode 100644 index 0000000..78b696a --- /dev/null +++ b/litedram/gen-src/orangecrab-85-0.2.yml @@ -0,0 +1,39 @@ +# Matt Johnston 2021 +# Based on parameters from Greg Davill's Orangecrab-test-sw + +{ + "cpu": "None", # CPU type (ex vexriscv, serv, None) + "device": "LFE5U-85F-8MG285C", + "memtype": "DDR3", # DRAM type + + "sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "disabled", # Nominal termination. ("disabled" from orangecrab) + "rtt_wr": "60ohm", # Write termination. (Default) + "ron": "34ohm", # Output driver impedance. (Default) + + # Frequency ---------------------------------------------------------------- + "init_clk_freq": 24e6, + "input_clk_freq": 48e6, # Input clock frequency + "sys_clk_freq": 48e6, # System clock frequency (DDR_clk = 4 x sys_clk) + + # 0 if freq >64e6 else 100. https://github.com/enjoy-digital/litedram/issues/130 + "cmd_delay": 100, + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + "dm_swap": true, + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + "block_until_ready": False, + }, + }, +} diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index 662cc26..6f50dae 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -32,6 +32,7 @@ CPPFLAGS += -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(LXINC_DIR)/base -I$(LXSRC_DIR)/lib CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks +CFLAGS += -Werror ASFLAGS = $(CPPFLAGS) $(CFLAGS) LDFLAGS = -static -nostdlib -T $(OBJ)/$(PROGRAM).lds --gc-sections diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml index 22a0190..217d3eb 100644 --- a/litedram/gen-src/sim.yml +++ b/litedram/gen-src/sim.yml @@ -31,6 +31,7 @@ "user_ports": { "native_0": { "type": "native", + "block_until_ready": False, }, }, } diff --git a/litedram/gen-src/wukong-v2.yml b/litedram/gen-src/wukong-v2.yml index 814b906..be0f76f 100644 --- a/litedram/gen-src/wukong-v2.yml +++ b/litedram/gen-src/wukong-v2.yml @@ -31,6 +31,7 @@ "user_ports": { "native_0": { "type": "native", + "block_until_ready": False, }, }, } diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init index 5b1a383..1b6e88e 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.init +++ b/litedram/generated/acorn-cle-215/litedram_core.init @@ -518,7 +518,7 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842afc4 +7c0802a63842adc4 fbe1fff8fbc1fff0 f821ff51f8010010 f88100d83bc10020 @@ -527,96 +527,97 @@ f8c100e87c651b78 38c100d87fc3f378 f90100f8f8e100f0 f9410108f9210100 -600000004800245d +6000000048002159 7fc3f3787c7f1b78 -6000000048001e69 +6000000048001b7d 7fe3fb78382100b0 -0000000048002a54 +00000000480027d4 0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842af203c4c0001 +3842ad203c4c0001 7d8000267c0802a6 -9181000848002991 -48001e65f821fed1 +9181000848002711 +48001b79f821fed1 3c62ffff60000000 -4bffff3938637b10 +4bffff3938637a90 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff 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+62202c64256d2020 +007c203a64323025 +0000000000006425 +000000000000207c 203a747365622020 302562202c64256d 6000000000206432 -616c206574697257 -61632079636e6574 -6f6974617262696c -00000000000a3a6e -0000202d3a64256d -002064253a64256d 76656c2064616552 000a3a676e696c65 696c616974696e49 diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v index 41a3761..da66195 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.v +++ b/litedram/generated/acorn-cle-215/litedram_core.v @@ -1,9 +1,25 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:37 -//-------------------------------------------------------------------------------- -module litedram_core( - input wire clk, - input wire rst, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 08:32:13 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + input wire rst, output wire pll_locked, output wire [15:0] ddram_a, output wire [2:0] ddram_ba, @@ -12,9 +28,9 @@ module litedram_core( output wire ddram_we_n, output wire ddram_cs_n, output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, @@ -22,32 +38,38 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [25:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + input wire user_port_native_0_cmd_we, + input wire [25:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, + input wire user_port_native_0_rdata_ready, output wire [127:0] user_port_native_0_rdata_data ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_rst = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -55,7 +77,7 @@ wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; wire main_reset; -reg main_power_down = 1'd0; +reg main_power_down = 1'd0; wire main_locked; wire main_clkin; wire main_clkout0; @@ -66,48 +88,48 @@ wire main_clkout2; wire main_clkout_buf2; wire main_clkout3; wire main_clkout_buf3; -reg [3:0] main_reset_counter = 4'd15; -reg main_ic_reset = 1'd1; -reg main_a7ddrphy_rst_storage = 1'd0; -reg main_a7ddrphy_rst_re = 1'd0; -reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg main_a7ddrphy_wlevel_en_storage = 1'd0; -reg main_a7ddrphy_wlevel_en_re = 1'd0; -reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; wire main_a7ddrphy_wlevel_strobe_r; -reg main_a7ddrphy_wlevel_strobe_we = 1'd0; -reg main_a7ddrphy_wlevel_strobe_w = 1'd0; -reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; -reg main_a7ddrphy_dly_sel_re = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_rst_r; -reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; wire main_a7ddrphy_rdly_dq_inc_r; -reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_rst_r; -reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_r; -reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_rst_r; -reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_r; -reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; -reg main_a7ddrphy_rdphase_re = 1'd0; -reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; -reg main_a7ddrphy_wrphase_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; wire [15:0] main_a7ddrphy_dfi_p0_address; wire [2:0] main_a7ddrphy_dfi_p0_bank; wire main_a7ddrphy_dfi_p0_cas_n; @@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata; wire main_a7ddrphy_dfi_p0_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; wire main_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; wire main_a7ddrphy_dfi_p0_rddata_valid; wire [15:0] main_a7ddrphy_dfi_p1_address; wire [2:0] main_a7ddrphy_dfi_p1_bank; @@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata; wire main_a7ddrphy_dfi_p1_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; wire main_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; wire main_a7ddrphy_dfi_p1_rddata_valid; wire [15:0] main_a7ddrphy_dfi_p2_address; wire [2:0] main_a7ddrphy_dfi_p2_bank; @@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata; wire main_a7ddrphy_dfi_p2_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; wire main_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; wire main_a7ddrphy_dfi_p2_rddata_valid; wire [15:0] main_a7ddrphy_dfi_p3_address; wire [2:0] main_a7ddrphy_dfi_p3_bank; @@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata; wire main_a7ddrphy_dfi_p3_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; wire main_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; wire main_a7ddrphy_dfi_p3_rddata_valid; wire main_a7ddrphy_sd_clk_se_nodelay; -reg main_a7ddrphy_dqs_oe = 1'd0; +reg main_a7ddrphy_dqs_oe = 1'd0; wire main_a7ddrphy_dqs_preamble; wire main_a7ddrphy_dqs_postamble; wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_dqspattern0 = 1'd0; -reg main_a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; wire main_a7ddrphy_dqs_o_no_delay0; wire main_a7ddrphy_dqs_t0; -reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; wire main_a7ddrphy0; wire main_a7ddrphy_dqs_o_no_delay1; wire main_a7ddrphy_dqs_t1; -reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; wire main_a7ddrphy1; -reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; wire main_a7ddrphy_dq_oe; wire main_a7ddrphy_dq_oe_delay_tappeddelayline; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire main_a7ddrphy_dq_o_nodelay0; wire main_a7ddrphy_dq_i_nodelay0; wire main_a7ddrphy_dq_i_delayed0; wire main_a7ddrphy_dq_t0; -reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip03; -reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay1; wire main_a7ddrphy_dq_i_nodelay1; wire main_a7ddrphy_dq_i_delayed1; wire main_a7ddrphy_dq_t1; -reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip13; -reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay2; wire main_a7ddrphy_dq_i_nodelay2; wire main_a7ddrphy_dq_i_delayed2; wire main_a7ddrphy_dq_t2; -reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip21; -reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay3; wire main_a7ddrphy_dq_i_nodelay3; wire main_a7ddrphy_dq_i_delayed3; wire main_a7ddrphy_dq_t3; -reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip31; -reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay4; wire main_a7ddrphy_dq_i_nodelay4; wire main_a7ddrphy_dq_i_delayed4; wire main_a7ddrphy_dq_t4; -reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip41; -reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay5; wire main_a7ddrphy_dq_i_nodelay5; wire main_a7ddrphy_dq_i_delayed5; wire main_a7ddrphy_dq_t5; -reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip51; -reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay6; wire main_a7ddrphy_dq_i_nodelay6; wire main_a7ddrphy_dq_i_delayed6; wire main_a7ddrphy_dq_t6; -reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip61; -reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay7; wire main_a7ddrphy_dq_i_nodelay7; wire main_a7ddrphy_dq_i_delayed7; wire main_a7ddrphy_dq_t7; -reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip71; -reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay8; wire main_a7ddrphy_dq_i_nodelay8; wire main_a7ddrphy_dq_i_delayed8; wire main_a7ddrphy_dq_t8; -reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip81; -reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay9; wire main_a7ddrphy_dq_i_nodelay9; wire main_a7ddrphy_dq_i_delayed9; wire main_a7ddrphy_dq_t9; -reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip91; -reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay10; wire main_a7ddrphy_dq_i_nodelay10; wire main_a7ddrphy_dq_i_delayed10; wire main_a7ddrphy_dq_t10; -reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip101; -reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay11; wire main_a7ddrphy_dq_i_nodelay11; wire main_a7ddrphy_dq_i_delayed11; wire main_a7ddrphy_dq_t11; -reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip111; -reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay12; wire main_a7ddrphy_dq_i_nodelay12; wire main_a7ddrphy_dq_i_delayed12; wire main_a7ddrphy_dq_t12; -reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip121; -reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay13; wire main_a7ddrphy_dq_i_nodelay13; wire main_a7ddrphy_dq_i_delayed13; wire main_a7ddrphy_dq_t13; -reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip131; -reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay14; wire main_a7ddrphy_dq_i_nodelay14; wire main_a7ddrphy_dq_i_delayed14; wire main_a7ddrphy_dq_t14; -reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip141; -reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay15; wire main_a7ddrphy_dq_i_nodelay15; wire main_a7ddrphy_dq_i_delayed15; wire main_a7ddrphy_dq_t15; -reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip151; -reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [15:0] main_litedramcore_inti_p0_address; wire [2:0] main_litedramcore_inti_p0_bank; -reg main_litedramcore_inti_p0_cas_n = 1'd1; -reg main_litedramcore_inti_p0_cs_n = 1'd1; -reg main_litedramcore_inti_p0_ras_n = 1'd1; -reg main_litedramcore_inti_p0_we_n = 1'd1; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; wire main_litedramcore_inti_p0_cke; wire main_litedramcore_inti_p0_odt; wire main_litedramcore_inti_p0_reset_n; -reg main_litedramcore_inti_p0_act_n = 1'd1; +reg main_litedramcore_inti_p0_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p0_wrdata; wire main_litedramcore_inti_p0_wrdata_en; wire [3:0] main_litedramcore_inti_p0_wrdata_mask; wire main_litedramcore_inti_p0_rddata_en; -reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; -reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; wire [15:0] main_litedramcore_inti_p1_address; wire [2:0] main_litedramcore_inti_p1_bank; -reg main_litedramcore_inti_p1_cas_n = 1'd1; -reg main_litedramcore_inti_p1_cs_n = 1'd1; -reg main_litedramcore_inti_p1_ras_n = 1'd1; -reg main_litedramcore_inti_p1_we_n = 1'd1; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; wire main_litedramcore_inti_p1_cke; wire main_litedramcore_inti_p1_odt; wire main_litedramcore_inti_p1_reset_n; -reg main_litedramcore_inti_p1_act_n = 1'd1; +reg main_litedramcore_inti_p1_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p1_wrdata; wire main_litedramcore_inti_p1_wrdata_en; wire [3:0] main_litedramcore_inti_p1_wrdata_mask; wire main_litedramcore_inti_p1_rddata_en; -reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; -reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; wire [15:0] main_litedramcore_inti_p2_address; wire [2:0] main_litedramcore_inti_p2_bank; -reg main_litedramcore_inti_p2_cas_n = 1'd1; -reg main_litedramcore_inti_p2_cs_n = 1'd1; -reg main_litedramcore_inti_p2_ras_n = 1'd1; -reg main_litedramcore_inti_p2_we_n = 1'd1; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; wire main_litedramcore_inti_p2_cke; wire main_litedramcore_inti_p2_odt; wire main_litedramcore_inti_p2_reset_n; -reg main_litedramcore_inti_p2_act_n = 1'd1; +reg main_litedramcore_inti_p2_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p2_wrdata; wire main_litedramcore_inti_p2_wrdata_en; wire [3:0] main_litedramcore_inti_p2_wrdata_mask; wire main_litedramcore_inti_p2_rddata_en; -reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; -reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; wire [15:0] main_litedramcore_inti_p3_address; wire [2:0] main_litedramcore_inti_p3_bank; -reg main_litedramcore_inti_p3_cas_n = 1'd1; -reg main_litedramcore_inti_p3_cs_n = 1'd1; -reg main_litedramcore_inti_p3_ras_n = 1'd1; -reg main_litedramcore_inti_p3_we_n = 1'd1; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; wire main_litedramcore_inti_p3_cke; wire main_litedramcore_inti_p3_odt; wire main_litedramcore_inti_p3_reset_n; -reg main_litedramcore_inti_p3_act_n = 1'd1; +reg main_litedramcore_inti_p3_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p3_wrdata; wire main_litedramcore_inti_p3_wrdata_en; wire [3:0] main_litedramcore_inti_p3_wrdata_mask; wire main_litedramcore_inti_p3_rddata_en; -reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; -reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; wire [15:0] main_litedramcore_slave_p0_address; wire [2:0] main_litedramcore_slave_p0_bank; wire main_litedramcore_slave_p0_cas_n; @@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata; wire main_litedramcore_slave_p0_wrdata_en; wire [3:0] main_litedramcore_slave_p0_wrdata_mask; wire main_litedramcore_slave_p0_rddata_en; -reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; -reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; wire [15:0] main_litedramcore_slave_p1_address; wire [2:0] main_litedramcore_slave_p1_bank; wire main_litedramcore_slave_p1_cas_n; @@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata; wire main_litedramcore_slave_p1_wrdata_en; wire [3:0] main_litedramcore_slave_p1_wrdata_mask; wire main_litedramcore_slave_p1_rddata_en; -reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; -reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; wire [15:0] main_litedramcore_slave_p2_address; wire [2:0] main_litedramcore_slave_p2_bank; wire main_litedramcore_slave_p2_cas_n; @@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata; wire main_litedramcore_slave_p2_wrdata_en; wire [3:0] main_litedramcore_slave_p2_wrdata_mask; wire main_litedramcore_slave_p2_rddata_en; -reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; -reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; wire [15:0] main_litedramcore_slave_p3_address; wire [2:0] main_litedramcore_slave_p3_bank; wire main_litedramcore_slave_p3_cas_n; @@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata; wire main_litedramcore_slave_p3_wrdata_en; wire [3:0] main_litedramcore_slave_p3_wrdata_mask; wire main_litedramcore_slave_p3_rddata_en; -reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; -reg main_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [15:0] main_litedramcore_master_p0_address = 16'd0; -reg [2:0] main_litedramcore_master_p0_bank = 3'd0; -reg main_litedramcore_master_p0_cas_n = 1'd1; -reg main_litedramcore_master_p0_cs_n = 1'd1; -reg main_litedramcore_master_p0_ras_n = 1'd1; -reg main_litedramcore_master_p0_we_n = 1'd1; -reg main_litedramcore_master_p0_cke = 1'd0; -reg main_litedramcore_master_p0_odt = 1'd0; -reg main_litedramcore_master_p0_reset_n = 1'd0; -reg main_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; -reg main_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; -reg main_litedramcore_master_p0_rddata_en = 1'd0; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [15:0] main_litedramcore_master_p0_address = 16'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p0_rddata; wire main_litedramcore_master_p0_rddata_valid; -reg [15:0] main_litedramcore_master_p1_address = 16'd0; -reg [2:0] main_litedramcore_master_p1_bank = 3'd0; -reg main_litedramcore_master_p1_cas_n = 1'd1; -reg main_litedramcore_master_p1_cs_n = 1'd1; -reg main_litedramcore_master_p1_ras_n = 1'd1; -reg main_litedramcore_master_p1_we_n = 1'd1; -reg main_litedramcore_master_p1_cke = 1'd0; -reg main_litedramcore_master_p1_odt = 1'd0; -reg main_litedramcore_master_p1_reset_n = 1'd0; -reg main_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; -reg main_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; -reg main_litedramcore_master_p1_rddata_en = 1'd0; +reg [15:0] main_litedramcore_master_p1_address = 16'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p1_rddata; wire main_litedramcore_master_p1_rddata_valid; -reg [15:0] main_litedramcore_master_p2_address = 16'd0; -reg [2:0] main_litedramcore_master_p2_bank = 3'd0; -reg main_litedramcore_master_p2_cas_n = 1'd1; -reg main_litedramcore_master_p2_cs_n = 1'd1; -reg main_litedramcore_master_p2_ras_n = 1'd1; -reg main_litedramcore_master_p2_we_n = 1'd1; -reg main_litedramcore_master_p2_cke = 1'd0; -reg main_litedramcore_master_p2_odt = 1'd0; -reg main_litedramcore_master_p2_reset_n = 1'd0; -reg main_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; -reg main_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; -reg main_litedramcore_master_p2_rddata_en = 1'd0; +reg [15:0] main_litedramcore_master_p2_address = 16'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p2_rddata; wire main_litedramcore_master_p2_rddata_valid; -reg [15:0] main_litedramcore_master_p3_address = 16'd0; -reg [2:0] main_litedramcore_master_p3_bank = 3'd0; -reg main_litedramcore_master_p3_cas_n = 1'd1; -reg main_litedramcore_master_p3_cs_n = 1'd1; -reg main_litedramcore_master_p3_ras_n = 1'd1; -reg main_litedramcore_master_p3_we_n = 1'd1; -reg main_litedramcore_master_p3_cke = 1'd0; -reg main_litedramcore_master_p3_odt = 1'd0; -reg main_litedramcore_master_p3_reset_n = 1'd0; -reg main_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; -reg main_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; -reg main_litedramcore_master_p3_rddata_en = 1'd0; +reg [15:0] main_litedramcore_master_p3_address = 16'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p3_rddata; wire main_litedramcore_master_p3_rddata_valid; wire main_litedramcore_sel; wire main_litedramcore_cke; wire main_litedramcore_odt; wire main_litedramcore_reset_n; -reg [3:0] main_litedramcore_storage = 4'd1; -reg main_litedramcore_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; -reg main_litedramcore_phaseinjector0_command_re = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector0_command_issue_r; -reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0; -reg main_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector0_address_storage = 16'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; wire main_litedramcore_phaseinjector0_rddata_we; -reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; -reg main_litedramcore_phaseinjector1_command_re = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector1_command_issue_r; -reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0; -reg main_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector1_address_storage = 16'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; wire main_litedramcore_phaseinjector1_rddata_we; -reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; -reg main_litedramcore_phaseinjector2_command_re = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector2_command_issue_r; -reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0; -reg main_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector2_address_storage = 16'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; wire main_litedramcore_phaseinjector2_rddata_we; -reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; -reg main_litedramcore_phaseinjector3_command_re = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector3_command_issue_r; -reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0; -reg main_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [15:0] main_litedramcore_phaseinjector3_address_storage = 16'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; wire main_litedramcore_phaseinjector3_rddata_we; -reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; wire main_litedramcore_interface_bank0_valid; wire main_litedramcore_interface_bank0_ready; wire main_litedramcore_interface_bank0_we; @@ -706,131 +728,131 @@ wire [22:0] main_litedramcore_interface_bank7_addr; wire main_litedramcore_interface_bank7_lock; wire main_litedramcore_interface_bank7_wdata_ready; wire main_litedramcore_interface_bank7_rdata_valid; -reg [127:0] main_litedramcore_interface_wdata = 128'd0; -reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; wire [127:0] main_litedramcore_interface_rdata; -reg [15:0] main_litedramcore_dfi_p0_address = 16'd0; -reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; -reg main_litedramcore_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_dfi_p0_ras_n = 1'd1; -reg main_litedramcore_dfi_p0_we_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p0_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; wire main_litedramcore_dfi_p0_cke; wire main_litedramcore_dfi_p0_odt; wire main_litedramcore_dfi_p0_reset_n; -reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg main_litedramcore_dfi_p0_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p0_wrdata; -reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; -reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p0_rddata; wire main_litedramcore_dfi_p0_rddata_valid; -reg [15:0] main_litedramcore_dfi_p1_address = 16'd0; -reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; -reg main_litedramcore_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_dfi_p1_ras_n = 1'd1; -reg main_litedramcore_dfi_p1_we_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p1_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; wire main_litedramcore_dfi_p1_cke; wire main_litedramcore_dfi_p1_odt; wire main_litedramcore_dfi_p1_reset_n; -reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg main_litedramcore_dfi_p1_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p1_wrdata; -reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; -reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p1_rddata; wire main_litedramcore_dfi_p1_rddata_valid; -reg [15:0] main_litedramcore_dfi_p2_address = 16'd0; -reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; -reg main_litedramcore_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_dfi_p2_ras_n = 1'd1; -reg main_litedramcore_dfi_p2_we_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p2_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; wire main_litedramcore_dfi_p2_cke; wire main_litedramcore_dfi_p2_odt; wire main_litedramcore_dfi_p2_reset_n; -reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg main_litedramcore_dfi_p2_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p2_wrdata; -reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; -reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p2_rddata; wire main_litedramcore_dfi_p2_rddata_valid; -reg [15:0] main_litedramcore_dfi_p3_address = 16'd0; -reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; -reg main_litedramcore_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_dfi_p3_ras_n = 1'd1; -reg main_litedramcore_dfi_p3_we_n = 1'd1; +reg [15:0] main_litedramcore_dfi_p3_address = 16'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; wire main_litedramcore_dfi_p3_cke; wire main_litedramcore_dfi_p3_odt; wire main_litedramcore_dfi_p3_reset_n; -reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg main_litedramcore_dfi_p3_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p3_wrdata; -reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; -reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p3_rddata; wire main_litedramcore_dfi_p3_rddata_valid; -reg main_litedramcore_cmd_valid = 1'd0; -reg main_litedramcore_cmd_ready = 1'd0; -reg main_litedramcore_cmd_last = 1'd0; -reg [15:0] main_litedramcore_cmd_payload_a = 16'd0; -reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; -reg main_litedramcore_cmd_payload_cas = 1'd0; -reg main_litedramcore_cmd_payload_ras = 1'd0; -reg main_litedramcore_cmd_payload_we = 1'd0; -reg main_litedramcore_cmd_payload_is_read = 1'd0; -reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [15:0] main_litedramcore_cmd_payload_a = 16'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; wire main_litedramcore_wants_refresh; wire main_litedramcore_wants_zqcs; wire main_litedramcore_timer_wait; wire main_litedramcore_timer_done0; wire [9:0] main_litedramcore_timer_count0; wire main_litedramcore_timer_done1; -reg [9:0] main_litedramcore_timer_count1 = 10'd781; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; wire main_litedramcore_postponer_req_i; -reg main_litedramcore_postponer_req_o = 1'd0; -reg main_litedramcore_postponer_count = 1'd0; -reg main_litedramcore_sequencer_start0 = 1'd0; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; wire main_litedramcore_sequencer_done0; wire main_litedramcore_sequencer_start1; -reg main_litedramcore_sequencer_done1 = 1'd0; -reg [6:0] main_litedramcore_sequencer_counter = 7'd0; -reg main_litedramcore_sequencer_count = 1'd0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [6:0] main_litedramcore_sequencer_counter = 7'd0; +reg main_litedramcore_sequencer_count = 1'd0; wire main_litedramcore_zqcs_timer_wait; wire main_litedramcore_zqcs_timer_done0; wire [26:0] main_litedramcore_zqcs_timer_count0; wire main_litedramcore_zqcs_timer_done1; -reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg main_litedramcore_zqcs_executer_start = 1'd0; -reg main_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; wire main_litedramcore_bankmachine0_req_valid; wire main_litedramcore_bankmachine0_req_ready; wire main_litedramcore_bankmachine0_req_we; wire [22:0] main_litedramcore_bankmachine0_req_addr; wire main_litedramcore_bankmachine0_req_lock; -reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine0_refresh_req; -reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine0_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; -reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; @@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; @@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine0_row = 16'd0; -reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine0_row = 16'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; wire main_litedramcore_bankmachine0_row_hit; -reg main_litedramcore_bankmachine0_row_open = 1'd0; -reg main_litedramcore_bankmachine0_row_close = 1'd0; -reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; wire main_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; wire main_litedramcore_bankmachine1_req_valid; wire main_litedramcore_bankmachine1_req_ready; wire main_litedramcore_bankmachine1_req_we; wire [22:0] main_litedramcore_bankmachine1_req_addr; wire main_litedramcore_bankmachine1_req_lock; -reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine1_refresh_req; -reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine1_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; -reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; @@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; @@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine1_row = 16'd0; -reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine1_row = 16'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; wire main_litedramcore_bankmachine1_row_hit; -reg main_litedramcore_bankmachine1_row_open = 1'd0; -reg main_litedramcore_bankmachine1_row_close = 1'd0; -reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; wire main_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; wire main_litedramcore_bankmachine2_req_valid; wire main_litedramcore_bankmachine2_req_ready; wire main_litedramcore_bankmachine2_req_we; wire [22:0] main_litedramcore_bankmachine2_req_addr; wire main_litedramcore_bankmachine2_req_lock; -reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine2_refresh_req; -reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine2_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; -reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; @@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; @@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine2_row = 16'd0; -reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine2_row = 16'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; wire main_litedramcore_bankmachine2_row_hit; -reg main_litedramcore_bankmachine2_row_open = 1'd0; -reg main_litedramcore_bankmachine2_row_close = 1'd0; -reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; wire main_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; wire main_litedramcore_bankmachine3_req_valid; wire main_litedramcore_bankmachine3_req_ready; wire main_litedramcore_bankmachine3_req_we; wire [22:0] main_litedramcore_bankmachine3_req_addr; wire main_litedramcore_bankmachine3_req_lock; -reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine3_refresh_req; -reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine3_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; -reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; @@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; @@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine3_row = 16'd0; -reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine3_row = 16'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; wire main_litedramcore_bankmachine3_row_hit; -reg main_litedramcore_bankmachine3_row_open = 1'd0; -reg main_litedramcore_bankmachine3_row_close = 1'd0; -reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; wire main_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; wire main_litedramcore_bankmachine4_req_valid; wire main_litedramcore_bankmachine4_req_ready; wire main_litedramcore_bankmachine4_req_we; wire [22:0] main_litedramcore_bankmachine4_req_addr; wire main_litedramcore_bankmachine4_req_lock; -reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine4_refresh_req; -reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine4_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; -reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; @@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; @@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine4_row = 16'd0; -reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine4_row = 16'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; wire main_litedramcore_bankmachine4_row_hit; -reg main_litedramcore_bankmachine4_row_open = 1'd0; -reg main_litedramcore_bankmachine4_row_close = 1'd0; -reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; wire main_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; wire main_litedramcore_bankmachine5_req_valid; wire main_litedramcore_bankmachine5_req_ready; wire main_litedramcore_bankmachine5_req_we; wire [22:0] main_litedramcore_bankmachine5_req_addr; wire main_litedramcore_bankmachine5_req_lock; -reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine5_refresh_req; -reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine5_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; -reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; @@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; @@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine5_row = 16'd0; -reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine5_row = 16'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; wire main_litedramcore_bankmachine5_row_hit; -reg main_litedramcore_bankmachine5_row_open = 1'd0; -reg main_litedramcore_bankmachine5_row_close = 1'd0; -reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; wire main_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; wire main_litedramcore_bankmachine6_req_valid; wire main_litedramcore_bankmachine6_req_ready; wire main_litedramcore_bankmachine6_req_we; wire [22:0] main_litedramcore_bankmachine6_req_addr; wire main_litedramcore_bankmachine6_req_lock; -reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine6_refresh_req; -reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine6_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; -reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; @@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; @@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine6_row = 16'd0; -reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine6_row = 16'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; wire main_litedramcore_bankmachine6_row_hit; -reg main_litedramcore_bankmachine6_row_open = 1'd0; -reg main_litedramcore_bankmachine6_row_close = 1'd0; -reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; wire main_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; wire main_litedramcore_bankmachine7_req_valid; wire main_litedramcore_bankmachine7_req_ready; wire main_litedramcore_bankmachine7_req_we; wire [22:0] main_litedramcore_bankmachine7_req_addr; wire main_litedramcore_bankmachine7_req_lock; -reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine7_refresh_req; -reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [15:0] main_litedramcore_bankmachine7_cmd_payload_a = 16'd0; wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; -reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; @@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [25:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; @@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; wire [22:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] main_litedramcore_bankmachine7_row = 16'd0; -reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [22:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0; +reg [15:0] main_litedramcore_bankmachine7_row = 16'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; wire main_litedramcore_bankmachine7_row_hit; -reg main_litedramcore_bankmachine7_row_open = 1'd0; -reg main_litedramcore_bankmachine7_row_close = 1'd0; -reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; wire main_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; wire main_litedramcore_ras_allowed; wire main_litedramcore_cas_allowed; wire [1:0] main_litedramcore_rdcmdphase; wire [1:0] main_litedramcore_wrcmdphase; -reg main_litedramcore_choose_cmd_want_reads = 1'd0; -reg main_litedramcore_choose_cmd_want_writes = 1'd0; -reg main_litedramcore_choose_cmd_want_cmds = 1'd0; -reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; wire main_litedramcore_choose_cmd_cmd_valid; -reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; wire [15:0] main_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; -reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; wire main_litedramcore_choose_cmd_cmd_payload_is_read; wire main_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; wire [7:0] main_litedramcore_choose_cmd_request; -reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; wire main_litedramcore_choose_cmd_ce; -reg main_litedramcore_choose_req_want_reads = 1'd0; -reg main_litedramcore_choose_req_want_writes = 1'd0; -reg main_litedramcore_choose_req_want_cmds = 1'd0; -reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; wire main_litedramcore_choose_req_cmd_valid; -reg main_litedramcore_choose_req_cmd_ready = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; wire [15:0] main_litedramcore_choose_req_cmd_payload_a; wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; -reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; wire main_litedramcore_choose_req_cmd_payload_is_cmd; wire main_litedramcore_choose_req_cmd_payload_is_read; wire main_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; wire [7:0] main_litedramcore_choose_req_request; -reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; wire main_litedramcore_choose_req_ce; -reg [15:0] main_litedramcore_nop_a = 16'd0; -reg [2:0] main_litedramcore_nop_ba = 3'd0; -reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; -reg main_litedramcore_steerer0 = 1'd1; -reg main_litedramcore_steerer1 = 1'd1; -reg main_litedramcore_steerer2 = 1'd1; -reg main_litedramcore_steerer3 = 1'd1; -reg main_litedramcore_steerer4 = 1'd1; -reg main_litedramcore_steerer5 = 1'd1; -reg main_litedramcore_steerer6 = 1'd1; -reg main_litedramcore_steerer7 = 1'd1; +reg [15:0] main_litedramcore_nop_a = 16'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; wire main_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; -reg main_litedramcore_trrdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; wire main_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; wire [2:0] main_litedramcore_tfawcon_count; -reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; wire main_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; -reg main_litedramcore_tccdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; wire main_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; wire main_litedramcore_read_available; wire main_litedramcore_write_available; -reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en0 = 1'd0; wire main_litedramcore_max_time0; -reg [4:0] main_litedramcore_time0 = 5'd0; -reg main_litedramcore_en1 = 1'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; wire main_litedramcore_max_time1; -reg [3:0] main_litedramcore_time1 = 4'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; wire main_litedramcore_go_to_refresh; -reg main_init_done_storage = 1'd0; -reg main_init_done_re = 1'd0; -reg main_init_error_storage = 1'd0; -reg main_init_error_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; wire [29:0] main_wb_bus_adr; wire [31:0] main_wb_bus_dat_w; wire [31:0] main_wb_bus_dat_r; @@ -1570,6 +1592,7 @@ wire main_wb_bus_we; wire [2:0] main_wb_bus_cti; wire [1:0] main_wb_bus_bte; wire main_wb_bus_err; +wire main_user_enable; wire main_user_port_cmd_valid; wire main_user_port_cmd_ready; wire main_user_port_cmd_payload_we; @@ -1590,26 +1613,26 @@ wire builder_reset5; wire builder_reset6; wire builder_reset7; wire builder_pll_fb; -reg [1:0] builder_refresher_state = 2'd0; -reg [1:0] builder_refresher_next_state = 2'd0; -reg [3:0] builder_bankmachine0_state = 4'd0; -reg [3:0] builder_bankmachine0_next_state = 4'd0; -reg [3:0] builder_bankmachine1_state = 4'd0; -reg [3:0] builder_bankmachine1_next_state = 4'd0; -reg [3:0] builder_bankmachine2_state = 4'd0; -reg [3:0] builder_bankmachine2_next_state = 4'd0; -reg [3:0] builder_bankmachine3_state = 4'd0; -reg [3:0] builder_bankmachine3_next_state = 4'd0; -reg [3:0] builder_bankmachine4_state = 4'd0; -reg [3:0] builder_bankmachine4_next_state = 4'd0; -reg [3:0] builder_bankmachine5_state = 4'd0; -reg [3:0] builder_bankmachine5_next_state = 4'd0; -reg [3:0] builder_bankmachine6_state = 4'd0; -reg [3:0] builder_bankmachine6_next_state = 4'd0; -reg [3:0] builder_bankmachine7_state = 4'd0; -reg [3:0] builder_bankmachine7_next_state = 4'd0; -reg [3:0] builder_multiplexer_state = 4'd0; -reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; wire builder_roundrobin0_request; wire builder_roundrobin0_grant; wire builder_roundrobin0_ce; @@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce; wire builder_roundrobin7_request; wire builder_roundrobin7_grant; wire builder_roundrobin7_ce; -reg builder_locked0 = 1'd0; -reg builder_locked1 = 1'd0; -reg builder_locked2 = 1'd0; -reg builder_locked3 = 1'd0; -reg builder_locked4 = 1'd0; -reg builder_locked5 = 1'd0; -reg builder_locked6 = 1'd0; -reg builder_locked7 = 1'd0; -reg builder_new_master_wdata_ready0 = 1'd0; -reg builder_new_master_wdata_ready1 = 1'd0; -reg builder_new_master_rdata_valid0 = 1'd0; -reg builder_new_master_rdata_valid1 = 1'd0; -reg builder_new_master_rdata_valid2 = 1'd0; -reg builder_new_master_rdata_valid3 = 1'd0; -reg builder_new_master_rdata_valid4 = 1'd0; -reg builder_new_master_rdata_valid5 = 1'd0; -reg builder_new_master_rdata_valid6 = 1'd0; -reg builder_new_master_rdata_valid7 = 1'd0; -reg builder_new_master_rdata_valid8 = 1'd0; -reg [13:0] builder_litedramcore_adr = 14'd0; -reg builder_litedramcore_we = 1'd0; -reg [7:0] builder_litedramcore_dat_w = 8'd0; -wire [7:0] builder_litedramcore_dat_r; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [31:0] builder_litedramcore_dat_w = 32'd0; +wire [31:0] builder_litedramcore_dat_r; wire [29:0] builder_litedramcore_wishbone_adr; wire [31:0] builder_litedramcore_wishbone_dat_w; -reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; wire [3:0] builder_litedramcore_wishbone_sel; wire builder_litedramcore_wishbone_cyc; wire builder_litedramcore_wishbone_stb; -reg builder_litedramcore_wishbone_ack = 1'd0; +reg builder_litedramcore_wishbone_ack = 1'd0; wire builder_litedramcore_wishbone_we; wire [2:0] builder_litedramcore_wishbone_cti; wire [1:0] builder_litedramcore_wishbone_bte; -reg builder_litedramcore_wishbone_err = 1'd0; +reg builder_litedramcore_wishbone_err = 1'd0; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; -wire [7:0] builder_interface0_bank_bus_dat_w; -reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; -reg builder_csrbank0_init_done0_re = 1'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +reg builder_csrbank0_init_done0_re = 1'd0; wire builder_csrbank0_init_done0_r; -reg builder_csrbank0_init_done0_we = 1'd0; +reg builder_csrbank0_init_done0_we = 1'd0; wire builder_csrbank0_init_done0_w; -reg builder_csrbank0_init_error0_re = 1'd0; +reg builder_csrbank0_init_error0_re = 1'd0; wire builder_csrbank0_init_error0_r; -reg builder_csrbank0_init_error0_we = 1'd0; +reg builder_csrbank0_init_error0_we = 1'd0; wire builder_csrbank0_init_error0_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; -wire [7:0] builder_interface1_bank_bus_dat_w; -reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; -reg builder_csrbank1_rst0_re = 1'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +reg builder_csrbank1_rst0_re = 1'd0; wire builder_csrbank1_rst0_r; -reg builder_csrbank1_rst0_we = 1'd0; +reg builder_csrbank1_rst0_we = 1'd0; wire builder_csrbank1_rst0_w; -reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_r; -reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_w; -reg builder_csrbank1_wlevel_en0_re = 1'd0; +reg builder_csrbank1_wlevel_en0_re = 1'd0; wire builder_csrbank1_wlevel_en0_r; -reg builder_csrbank1_wlevel_en0_we = 1'd0; +reg builder_csrbank1_wlevel_en0_we = 1'd0; wire builder_csrbank1_wlevel_en0_w; -reg builder_csrbank1_dly_sel0_re = 1'd0; +reg builder_csrbank1_dly_sel0_re = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_r; -reg builder_csrbank1_dly_sel0_we = 1'd0; +reg builder_csrbank1_dly_sel0_we = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_w; -reg builder_csrbank1_rdphase0_re = 1'd0; +reg builder_csrbank1_rdphase0_re = 1'd0; wire [1:0] builder_csrbank1_rdphase0_r; -reg builder_csrbank1_rdphase0_we = 1'd0; +reg builder_csrbank1_rdphase0_we = 1'd0; wire [1:0] builder_csrbank1_rdphase0_w; -reg builder_csrbank1_wrphase0_re = 1'd0; +reg builder_csrbank1_wrphase0_re = 1'd0; wire [1:0] builder_csrbank1_wrphase0_r; -reg builder_csrbank1_wrphase0_we = 1'd0; +reg builder_csrbank1_wrphase0_we = 1'd0; wire [1:0] builder_csrbank1_wrphase0_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; -wire [7:0] builder_interface2_bank_bus_dat_w; -reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; -reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_r; -reg builder_csrbank2_dfii_control0_we = 1'd0; +reg builder_csrbank2_dfii_control0_we = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_w; -reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_r; -reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_w; -reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address1_r; -reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address1_w; -reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_r; -reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_w; -reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; -reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; -reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; -reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; -reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; -reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; -reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; -reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; -reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; -reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; -reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; -reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; -reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; -reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; -reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; -reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; -reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; -reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; -reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_r; -reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_w; -reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address1_r; -reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address1_w; -reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_r; -reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_w; -reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; -reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; -reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; -reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; -reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; -reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; -reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; -reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; -reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; -reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; -reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; -reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; -reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; -reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; -reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; -reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; -reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; -reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; -reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_r; -reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_w; -reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address1_r; -reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address1_w; -reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_r; -reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_w; -reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; -reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; -reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; -reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; -reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; -reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; -reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; -reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; -reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; -reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; -reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; -reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; -reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; -reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; -reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; -reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; -reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; -reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; -reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_r; -reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_w; -reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address1_r; -reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address1_w; -reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_r; -reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_w; -reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [15:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; -reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; -reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; -reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; -reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; -reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; -reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; -reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; -reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; -reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; -reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; -reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; -reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; -reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; -reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; -reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; -reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; -reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; wire builder_csrbank2_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; -wire [7:0] builder_csr_interconnect_dat_w; -wire [7:0] builder_csr_interconnect_dat_r; -reg [1:0] builder_state = 2'd0; -reg [1:0] builder_next_state = 2'd0; -reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; -reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; -reg builder_litedramcore_adr_next_value_ce1 = 1'd0; -reg builder_litedramcore_we_next_value2 = 1'd0; -reg builder_litedramcore_we_next_value_ce2 = 1'd0; -reg builder_rhs_array_muxed0 = 1'd0; -reg [15:0] builder_rhs_array_muxed1 = 16'd0; -reg [2:0] builder_rhs_array_muxed2 = 3'd0; -reg builder_rhs_array_muxed3 = 1'd0; -reg builder_rhs_array_muxed4 = 1'd0; -reg builder_rhs_array_muxed5 = 1'd0; -reg builder_t_array_muxed0 = 1'd0; -reg builder_t_array_muxed1 = 1'd0; -reg builder_t_array_muxed2 = 1'd0; -reg builder_rhs_array_muxed6 = 1'd0; -reg [15:0] builder_rhs_array_muxed7 = 16'd0; -reg [2:0] builder_rhs_array_muxed8 = 3'd0; -reg builder_rhs_array_muxed9 = 1'd0; -reg builder_rhs_array_muxed10 = 1'd0; -reg builder_rhs_array_muxed11 = 1'd0; -reg builder_t_array_muxed3 = 1'd0; -reg builder_t_array_muxed4 = 1'd0; -reg builder_t_array_muxed5 = 1'd0; -reg [22:0] builder_rhs_array_muxed12 = 23'd0; -reg builder_rhs_array_muxed13 = 1'd0; -reg builder_rhs_array_muxed14 = 1'd0; -reg [22:0] builder_rhs_array_muxed15 = 23'd0; -reg builder_rhs_array_muxed16 = 1'd0; -reg builder_rhs_array_muxed17 = 1'd0; -reg [22:0] builder_rhs_array_muxed18 = 23'd0; -reg builder_rhs_array_muxed19 = 1'd0; -reg builder_rhs_array_muxed20 = 1'd0; -reg [22:0] builder_rhs_array_muxed21 = 23'd0; -reg builder_rhs_array_muxed22 = 1'd0; -reg builder_rhs_array_muxed23 = 1'd0; -reg [22:0] builder_rhs_array_muxed24 = 23'd0; -reg builder_rhs_array_muxed25 = 1'd0; -reg builder_rhs_array_muxed26 = 1'd0; -reg [22:0] builder_rhs_array_muxed27 = 23'd0; -reg builder_rhs_array_muxed28 = 1'd0; -reg builder_rhs_array_muxed29 = 1'd0; -reg [22:0] builder_rhs_array_muxed30 = 23'd0; -reg builder_rhs_array_muxed31 = 1'd0; -reg builder_rhs_array_muxed32 = 1'd0; -reg [22:0] builder_rhs_array_muxed33 = 23'd0; -reg builder_rhs_array_muxed34 = 1'd0; -reg builder_rhs_array_muxed35 = 1'd0; -reg [2:0] builder_array_muxed0 = 3'd0; -reg [15:0] builder_array_muxed1 = 16'd0; -reg builder_array_muxed2 = 1'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg builder_array_muxed6 = 1'd0; -reg [2:0] builder_array_muxed7 = 3'd0; -reg [15:0] builder_array_muxed8 = 16'd0; -reg builder_array_muxed9 = 1'd0; -reg builder_array_muxed10 = 1'd0; -reg builder_array_muxed11 = 1'd0; -reg builder_array_muxed12 = 1'd0; -reg builder_array_muxed13 = 1'd0; -reg [2:0] builder_array_muxed14 = 3'd0; -reg [15:0] builder_array_muxed15 = 16'd0; -reg builder_array_muxed16 = 1'd0; -reg builder_array_muxed17 = 1'd0; -reg builder_array_muxed18 = 1'd0; -reg builder_array_muxed19 = 1'd0; -reg builder_array_muxed20 = 1'd0; -reg [2:0] builder_array_muxed21 = 3'd0; -reg [15:0] builder_array_muxed22 = 16'd0; -reg builder_array_muxed23 = 1'd0; -reg builder_array_muxed24 = 1'd0; -reg builder_array_muxed25 = 1'd0; -reg builder_array_muxed26 = 1'd0; -reg builder_array_muxed27 = 1'd0; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [15:0] builder_rhs_array_muxed1 = 16'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [15:0] builder_rhs_array_muxed7 = 16'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [22:0] builder_rhs_array_muxed12 = 23'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [22:0] builder_rhs_array_muxed15 = 23'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [22:0] builder_rhs_array_muxed18 = 23'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [22:0] builder_rhs_array_muxed21 = 23'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [22:0] builder_rhs_array_muxed24 = 23'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [22:0] builder_rhs_array_muxed27 = 23'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [22:0] builder_rhs_array_muxed30 = 23'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [22:0] builder_rhs_array_muxed33 = 23'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [15:0] builder_array_muxed1 = 16'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [15:0] builder_array_muxed8 = 16'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [15:0] builder_array_muxed15 = 16'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [15:0] builder_array_muxed22 = 16'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl1; @@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl3_expr; -// synthesis translate_off -reg dummy_s; -initial dummy_s <= 1'd0; -// synthesis translate_on +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + assign init_done = main_init_done_storage; assign init_error = main_init_error_storage; assign main_wb_bus_adr = wb_ctrl_adr; @@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; -assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; -assign main_reset = rst; +assign main_reset = (rst | main_rst); assign pll_locked = main_locked; assign main_clkin = clk; assign iodelay_clk = main_clkout_buf0; @@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2; assign sys4x_dqs_clk = main_clkout_buf3; assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); - -// synthesis translate_off -reg dummy_d; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p0_rddata <= 32'd0; main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; @@ -2081,14 +1989,7 @@ always @(*) begin main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; -// synthesis translate_off - dummy_d = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_1; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p1_rddata <= 32'd0; main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; @@ -2123,14 +2024,7 @@ always @(*) begin main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; -// synthesis translate_off - dummy_d_1 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_2; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p2_rddata <= 32'd0; main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; @@ -2165,14 +2059,7 @@ always @(*) begin main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; -// synthesis translate_off - dummy_d_2 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_3; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p3_rddata <= 32'd0; main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; @@ -2207,19 +2094,12 @@ always @(*) begin main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; -// synthesis translate_off - dummy_d_3 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; - -// synthesis translate_off -reg dummy_d_4; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqs_oe <= 1'd0; if (main_a7ddrphy_wlevel_en_storage) begin @@ -2227,16 +2107,9 @@ always @(*) begin end else begin main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; end -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqspattern_o0 <= 8'd0; main_a7ddrphy_dqspattern_o0 <= 7'd85; @@ -2252,14 +2125,7 @@ always @(*) begin main_a7ddrphy_dqspattern_o0 <= 1'd1; end end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip00 <= 8'd0; case (main_a7ddrphy_bitslip0_value0) @@ -2288,14 +2154,7 @@ always @(*) begin main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip10 <= 8'd0; case (main_a7ddrphy_bitslip1_value0) @@ -2324,14 +2183,7 @@ always @(*) begin main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip01 <= 8'd0; case (main_a7ddrphy_bitslip0_value1) @@ -2360,14 +2212,7 @@ always @(*) begin main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip11 <= 8'd0; case (main_a7ddrphy_bitslip1_value1) @@ -2396,14 +2241,7 @@ always @(*) begin main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip02 <= 8'd0; case (main_a7ddrphy_bitslip0_value2) @@ -2432,14 +2270,7 @@ always @(*) begin main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip04 <= 8'd0; case (main_a7ddrphy_bitslip0_value3) @@ -2468,14 +2299,7 @@ always @(*) begin main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip12 <= 8'd0; case (main_a7ddrphy_bitslip1_value2) @@ -2504,14 +2328,7 @@ always @(*) begin main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip14 <= 8'd0; case (main_a7ddrphy_bitslip1_value3) @@ -2540,14 +2357,7 @@ always @(*) begin main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip20 <= 8'd0; case (main_a7ddrphy_bitslip2_value0) @@ -2576,14 +2386,7 @@ always @(*) begin main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip22 <= 8'd0; case (main_a7ddrphy_bitslip2_value1) @@ -2612,14 +2415,7 @@ always @(*) begin main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip30 <= 8'd0; case (main_a7ddrphy_bitslip3_value0) @@ -2648,14 +2444,7 @@ always @(*) begin main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip32 <= 8'd0; case (main_a7ddrphy_bitslip3_value1) @@ -2684,14 +2473,7 @@ always @(*) begin main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_18; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip40 <= 8'd0; case (main_a7ddrphy_bitslip4_value0) @@ -2720,14 +2502,7 @@ always @(*) begin main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_18 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_19; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip42 <= 8'd0; case (main_a7ddrphy_bitslip4_value1) @@ -2756,14 +2531,7 @@ always @(*) begin main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_19 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_20; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip50 <= 8'd0; case (main_a7ddrphy_bitslip5_value0) @@ -2792,14 +2560,7 @@ always @(*) begin main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_20 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_21; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip52 <= 8'd0; case (main_a7ddrphy_bitslip5_value1) @@ -2828,14 +2589,7 @@ always @(*) begin main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_21 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip60 <= 8'd0; case (main_a7ddrphy_bitslip6_value0) @@ -2864,14 +2618,7 @@ always @(*) begin main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip62 <= 8'd0; case (main_a7ddrphy_bitslip6_value1) @@ -2900,14 +2647,7 @@ always @(*) begin main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip70 <= 8'd0; case (main_a7ddrphy_bitslip7_value0) @@ -2936,14 +2676,7 @@ always @(*) begin main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip72 <= 8'd0; case (main_a7ddrphy_bitslip7_value1) @@ -2972,14 +2705,7 @@ always @(*) begin main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_26; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip80 <= 8'd0; case (main_a7ddrphy_bitslip8_value0) @@ -3008,14 +2734,7 @@ always @(*) begin main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip82 <= 8'd0; case (main_a7ddrphy_bitslip8_value1) @@ -3044,14 +2763,7 @@ always @(*) begin main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip90 <= 8'd0; case (main_a7ddrphy_bitslip9_value0) @@ -3080,14 +2792,7 @@ always @(*) begin main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip92 <= 8'd0; case (main_a7ddrphy_bitslip9_value1) @@ -3116,14 +2821,7 @@ always @(*) begin main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip100 <= 8'd0; case (main_a7ddrphy_bitslip10_value0) @@ -3152,14 +2850,7 @@ always @(*) begin main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_30 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_31; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip102 <= 8'd0; case (main_a7ddrphy_bitslip10_value1) @@ -3188,14 +2879,7 @@ always @(*) begin main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_31 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_32; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip110 <= 8'd0; case (main_a7ddrphy_bitslip11_value0) @@ -3224,14 +2908,7 @@ always @(*) begin main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_32 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_33; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip112 <= 8'd0; case (main_a7ddrphy_bitslip11_value1) @@ -3260,14 +2937,7 @@ always @(*) begin main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_33 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_34; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip120 <= 8'd0; case (main_a7ddrphy_bitslip12_value0) @@ -3296,14 +2966,7 @@ always @(*) begin main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_34 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_35; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip122 <= 8'd0; case (main_a7ddrphy_bitslip12_value1) @@ -3332,14 +2995,7 @@ always @(*) begin main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_35 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_36; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip130 <= 8'd0; case (main_a7ddrphy_bitslip13_value0) @@ -3368,14 +3024,7 @@ always @(*) begin main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_36 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_37; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip132 <= 8'd0; case (main_a7ddrphy_bitslip13_value1) @@ -3404,14 +3053,7 @@ always @(*) begin main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_37 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_38; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip140 <= 8'd0; case (main_a7ddrphy_bitslip14_value0) @@ -3440,14 +3082,7 @@ always @(*) begin main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip142 <= 8'd0; case (main_a7ddrphy_bitslip14_value1) @@ -3476,14 +3111,7 @@ always @(*) begin main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_39 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_40; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip150 <= 8'd0; case (main_a7ddrphy_bitslip15_value0) @@ -3512,14 +3140,7 @@ always @(*) begin main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_40 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_41; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip152 <= 8'd0; case (main_a7ddrphy_bitslip15_value1) @@ -3548,9 +3169,6 @@ always @(*) begin main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_41 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; @@ -3680,10 +3298,21 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_ assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; - -// synthesis translate_off -reg dummy_d_42; -// synthesis translate_on +always @(*) begin + main_litedramcore_master_p2_wrdata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; + end else begin + main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; + end +end +always @(*) begin + main_litedramcore_inti_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; + end +end always @(*) begin main_litedramcore_master_p2_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3691,28 +3320,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end -// synthesis translate_off - dummy_d_42 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_43; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end -// synthesis translate_off - dummy_d_43 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_44; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -3720,14 +3335,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end -// synthesis translate_off - dummy_d_44 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_45; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3735,14 +3343,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end -// synthesis translate_off - dummy_d_45 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_46; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_address <= 16'd0; if (main_litedramcore_sel) begin @@ -3750,14 +3351,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end -// synthesis translate_off - dummy_d_46 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_47; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -3765,14 +3359,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end -// synthesis translate_off - dummy_d_47 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_48; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3780,14 +3367,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end -// synthesis translate_off - dummy_d_48 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_49; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3795,14 +3375,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end -// synthesis translate_off - dummy_d_49 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_50; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3810,28 +3383,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end -// synthesis translate_off - dummy_d_50 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_51; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end -// synthesis translate_off - dummy_d_51 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_52; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3839,28 +3398,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end -// synthesis translate_off - dummy_d_52 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_53; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_53 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_54; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -3868,14 +3413,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end -// synthesis translate_off - dummy_d_54 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_55; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -3883,14 +3421,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end -// synthesis translate_off - dummy_d_55 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_56; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -3898,14 +3429,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end -// synthesis translate_off - dummy_d_56 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_57; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3913,14 +3437,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end -// synthesis translate_off - dummy_d_57 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_58; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -3928,28 +3445,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end -// synthesis translate_off - dummy_d_58 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_59; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end -// synthesis translate_off - dummy_d_59 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_60; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3957,28 +3460,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end -// synthesis translate_off - dummy_d_60 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_61; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end -// synthesis translate_off - dummy_d_61 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_62; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -3986,14 +3475,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end -// synthesis translate_off - dummy_d_62 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_63; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4001,14 +3483,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; end -// synthesis translate_off - dummy_d_63 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_64; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_address <= 16'd0; if (main_litedramcore_sel) begin @@ -4016,14 +3491,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end -// synthesis translate_off - dummy_d_64 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_65; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4031,14 +3499,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end -// synthesis translate_off - dummy_d_65 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_66; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4046,14 +3507,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end -// synthesis translate_off - dummy_d_66 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_67; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4061,14 +3515,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end -// synthesis translate_off - dummy_d_67 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_68; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4076,57 +3523,29 @@ always @(*) begin end else begin main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end -// synthesis translate_off - dummy_d_68 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_69; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end -// synthesis translate_off - dummy_d_69 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_70; -// synthesis translate_on always @(*) begin - main_litedramcore_master_p0_we_n <= 1'd1; + main_litedramcore_slave_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin - main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; + main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin - main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end -// synthesis translate_off - dummy_d_70 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_71; -// synthesis translate_on always @(*) begin - main_litedramcore_slave_p0_rddata_valid <= 1'd0; + main_litedramcore_master_p0_we_n <= 1'd1; if (main_litedramcore_sel) begin - main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n; end else begin + main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end -// synthesis translate_off - dummy_d_71 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_72; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4134,14 +3553,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end -// synthesis translate_off - dummy_d_72 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_73; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4149,14 +3561,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end -// synthesis translate_off - dummy_d_73 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_74; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4164,14 +3569,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end -// synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4179,14 +3577,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end -// synthesis translate_off - dummy_d_75 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_76; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4194,28 +3585,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end -// synthesis translate_off - dummy_d_76 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_77; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end -// synthesis translate_off - dummy_d_77 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_78; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4223,28 +3600,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end -// synthesis translate_off - dummy_d_78 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_79; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end -// synthesis translate_off - dummy_d_79 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_80; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4252,14 +3615,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end -// synthesis translate_off - dummy_d_80 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_81; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4267,14 +3623,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end -// synthesis translate_off - dummy_d_81 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_82; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_address <= 16'd0; if (main_litedramcore_sel) begin @@ -4282,14 +3631,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end -// synthesis translate_off - dummy_d_82 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_83; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4297,14 +3639,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end -// synthesis translate_off - dummy_d_83 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_84; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4312,14 +3647,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end -// synthesis translate_off - dummy_d_84 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_85; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4327,14 +3655,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end -// synthesis translate_off - dummy_d_85 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_86; -// synthesis translate_on +always @(*) begin + main_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; + end else begin + end +end always @(*) begin main_litedramcore_master_p1_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4342,28 +3670,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end -// synthesis translate_off - dummy_d_86 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_87; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end -// synthesis translate_off - dummy_d_87 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_88; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4371,28 +3685,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end -// synthesis translate_off - dummy_d_88 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_89; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_89 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_90; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4400,14 +3700,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end -// synthesis translate_off - dummy_d_90 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_91; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4415,14 +3708,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end -// synthesis translate_off - dummy_d_91 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_92; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4430,14 +3716,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end -// synthesis translate_off - dummy_d_92 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_93; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4445,14 +3724,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end -// synthesis translate_off - dummy_d_93 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_94; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4460,28 +3732,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end -// synthesis translate_off - dummy_d_94 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_95; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end -// synthesis translate_off - dummy_d_95 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_96; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4489,28 +3747,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end -// synthesis translate_off - dummy_d_97 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_98; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4518,14 +3762,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end -// synthesis translate_off - dummy_d_98 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_99; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4533,14 +3770,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end -// synthesis translate_off - dummy_d_99 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_100; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_address <= 16'd0; if (main_litedramcore_sel) begin @@ -4548,14 +3778,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end -// synthesis translate_off - dummy_d_100 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_101; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4563,14 +3786,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end -// synthesis translate_off - dummy_d_101 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_102; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4578,14 +3794,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end -// synthesis translate_off - dummy_d_102 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_103; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4593,14 +3802,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end -// synthesis translate_off - dummy_d_103 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_104; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4608,28 +3810,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_104 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_105; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end -// synthesis translate_off - dummy_d_105 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_106; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4637,28 +3825,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end -// synthesis translate_off - dummy_d_106 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_107; -// synthesis translate_on -always @(*) begin - main_litedramcore_slave_p2_rddata_valid <= 1'd0; - if (main_litedramcore_sel) begin - main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; - end else begin - end -// synthesis translate_off - dummy_d_107 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_108; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4666,28 +3833,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end -// synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p3_rddata <= 32'd0; - if (main_litedramcore_sel) begin - end else begin - main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; - end -// synthesis translate_off - dummy_d_109 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_110; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4695,14 +3841,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end -// synthesis translate_off - dummy_d_110 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_111; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4710,14 +3849,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end -// synthesis translate_off - dummy_d_111 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_112; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4725,24 +3857,6 @@ always @(*) begin end else begin main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end -// synthesis translate_off - dummy_d_112 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_113; -// synthesis translate_on -always @(*) begin - main_litedramcore_master_p2_wrdata <= 32'd0; - if (main_litedramcore_sel) begin - main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata; - end else begin - main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; - end -// synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; @@ -4756,10 +3870,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); + end else begin + main_litedramcore_inti_p0_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p0_cs_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4767,14 +3885,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_114 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_115; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_ras_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4782,14 +3893,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_115 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_116; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_we_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4797,24 +3901,6 @@ always @(*) begin end else begin main_litedramcore_inti_p0_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_116 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_117; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p0_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); - end else begin - main_litedramcore_inti_p0_cas_n <= 1'd1; - end -// synthesis translate_off - dummy_d_117 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; @@ -4822,10 +3908,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_118; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); + end else begin + main_litedramcore_inti_p1_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p1_cs_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4833,14 +3923,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_118 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_119; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_ras_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4848,14 +3931,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_we_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4863,24 +3939,6 @@ always @(*) begin end else begin main_litedramcore_inti_p1_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p1_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); - end else begin - main_litedramcore_inti_p1_cas_n <= 1'd1; - end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; @@ -4888,10 +3946,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p2_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]); + end else begin + main_litedramcore_inti_p2_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p2_cs_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4899,14 +3961,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_ras_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4914,14 +3969,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_we_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4929,24 +3977,6 @@ always @(*) begin end else begin main_litedramcore_inti_p2_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_124 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_125; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p2_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]); - end else begin - main_litedramcore_inti_p2_cas_n <= 1'd1; - end -// synthesis translate_off - dummy_d_125 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; @@ -4954,10 +3984,14 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_126; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); + end else begin + main_litedramcore_inti_p3_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p3_cs_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4965,14 +3999,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_ras_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4980,14 +4007,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_we_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4995,24 +4015,6 @@ always @(*) begin end else begin main_litedramcore_inti_p3_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p3_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); - end else begin - main_litedramcore_inti_p3_cas_n <= 1'd1; - end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; @@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on always @(*) begin builder_refresher_next_state <= 2'd0; builder_refresher_next_state <= builder_refresher_state; @@ -5124,119 +4122,88 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_130 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_131; -// synthesis translate_on always @(*) begin - main_litedramcore_zqcs_executer_start <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin - main_litedramcore_zqcs_executer_start <= 1'd1; end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase -// synthesis translate_off - dummy_d_131 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_132; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_last <= 1'd0; + main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) 1'd1: begin end 2'd2: begin if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase -// synthesis translate_off - dummy_d_132 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_133; -// synthesis translate_on always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; + main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase -// synthesis translate_off - dummy_d_133 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_134; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) 1'd1: begin - main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_sequencer_done0) begin - if (main_litedramcore_wants_zqcs) begin - end else begin - main_litedramcore_cmd_valid <= 1'd0; - end - end end 2'd3: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase -// synthesis translate_off - dummy_d_134 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; @@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_135; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin @@ -5263,17 +4226,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_135 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_136; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin @@ -5281,9 +4237,6 @@ always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_136 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; @@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_137; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin @@ -5313,9 +4262,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); @@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on always @(*) begin builder_bankmachine0_next_state <= 4'd0; builder_bankmachine0_next_state <= builder_bankmachine0_state; @@ -5389,14 +4331,45 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_138 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_139; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (builder_bankmachine0_state) @@ -5422,14 +4395,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (builder_bankmachine0_state) @@ -5470,14 +4436,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_140 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_141; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) @@ -5503,14 +4462,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_141 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_142; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_close <= 1'd0; case (builder_bankmachine0_state) @@ -5536,14 +4488,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_142 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_143; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (builder_bankmachine0_state) @@ -5578,22 +4523,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_143 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_144; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -5606,44 +4550,19 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5659,14 +4578,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_145 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_146; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (builder_bankmachine0_state) @@ -5707,47 +4619,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_146 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_147; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine0_state) @@ -5777,14 +4649,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_148 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_149; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (builder_bankmachine0_state) @@ -5822,14 +4687,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_149 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_150; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (builder_bankmachine0_state) @@ -5867,14 +4725,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_150 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_151; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (builder_bankmachine0_state) @@ -5912,9 +4763,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_151 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; @@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_152; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin @@ -5941,17 +4785,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin @@ -5959,9 +4796,6 @@ always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; @@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin @@ -5991,9 +4821,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); @@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on always @(*) begin builder_bankmachine1_next_state <= 4'd0; builder_bankmachine1_next_state <= builder_bankmachine1_state; @@ -6067,14 +4890,45 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_155 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_156; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) @@ -6100,14 +4954,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_156 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_157; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_valid <= 1'd0; case (builder_bankmachine1_state) @@ -6148,14 +4995,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_open <= 1'd0; case (builder_bankmachine1_state) @@ -6181,14 +5021,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_158 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_159; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_close <= 1'd0; case (builder_bankmachine1_state) @@ -6214,14 +5047,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_159 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_160; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (builder_bankmachine1_state) @@ -6256,14 +5082,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_160 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_161; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (builder_bankmachine1_state) @@ -6292,14 +5111,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (builder_bankmachine1_state) @@ -6340,47 +5152,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_162 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_163; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_163 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_164; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine1_state) @@ -6410,14 +5182,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_164 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_165; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (builder_bankmachine1_state) @@ -6455,14 +5220,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_165 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_166; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (builder_bankmachine1_state) @@ -6500,22 +5258,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_166 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_167; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6528,31 +5282,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_167 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_168; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (builder_bankmachine1_state) @@ -6590,9 +5322,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_168 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; @@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_169; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin @@ -6619,17 +5344,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin @@ -6637,9 +5355,6 @@ always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; @@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin @@ -6669,9 +5380,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); @@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on always @(*) begin builder_bankmachine2_next_state <= 4'd0; builder_bankmachine2_next_state <= builder_bankmachine2_state; @@ -6745,14 +5449,45 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_172 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_173; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (builder_bankmachine2_state) @@ -6778,14 +5513,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) @@ -6826,22 +5554,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_174 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_175; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6854,31 +5578,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) @@ -6904,14 +5606,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) @@ -6937,14 +5632,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_177 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_178; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) @@ -6979,14 +5667,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_178 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_179; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (builder_bankmachine2_state) @@ -7015,14 +5696,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_179 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_180; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) @@ -7063,47 +5737,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_180 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_181; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_181 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_182; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) @@ -7133,14 +5767,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_182 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_183; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) @@ -7178,14 +5805,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_183 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_184; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) @@ -7223,14 +5843,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_184 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_185; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) @@ -7268,9 +5881,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_185 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; @@ -7286,10 +5896,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_186; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin @@ -7297,17 +5903,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin @@ -7315,9 +5914,6 @@ always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; @@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin @@ -7347,9 +5939,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); @@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on always @(*) begin builder_bankmachine3_next_state <= 4'd0; builder_bankmachine3_next_state <= builder_bankmachine3_state; @@ -7423,14 +6008,45 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_189 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_190; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (builder_bankmachine3_state) @@ -7456,14 +6072,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_190 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_191; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (builder_bankmachine3_state) @@ -7504,14 +6113,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_open <= 1'd0; case (builder_bankmachine3_state) @@ -7537,24 +6139,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_192 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_193; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine3_row_close <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7565,44 +6163,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_193 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_194; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_row_close <= 1'd0; + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin - main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7615,14 +6191,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_194 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_195; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (builder_bankmachine3_state) @@ -7657,14 +6226,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_195 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_196; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (builder_bankmachine3_state) @@ -7693,14 +6255,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (builder_bankmachine3_state) @@ -7741,47 +6296,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_197 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_198; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_198 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_199; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -7811,14 +6326,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_199 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_200; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (builder_bankmachine3_state) @@ -7856,14 +6364,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_200 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_201; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (builder_bankmachine3_state) @@ -7901,14 +6402,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_201 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_202; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (builder_bankmachine3_state) @@ -7946,9 +6440,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_202 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; @@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_203; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin @@ -7975,17 +6462,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin @@ -7993,9 +6473,6 @@ always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_204 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; @@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_205; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin @@ -8025,9 +6498,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); @@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on always @(*) begin builder_bankmachine4_next_state <= 4'd0; builder_bankmachine4_next_state <= builder_bankmachine4_state; @@ -8101,16 +6567,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_206 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_207; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin end @@ -8119,9 +6578,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine4_twtpcon_ready) begin - main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8132,29 +6588,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8168,41 +6629,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_208 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_209; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_open <= 1'd0; + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8215,27 +6657,23 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_209 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_210; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_close <= 1'd0; + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8246,24 +6684,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_210 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_211; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine4_row_open <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -8276,44 +6722,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_211 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_212; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine4_row_close <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8326,21 +6750,11 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_212 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_213; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8362,10 +6776,7 @@ always @(*) begin if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine4_row_opened) begin if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8374,24 +6785,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_213 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_214; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8407,18 +6814,14 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_214 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_215; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8441,8 +6844,8 @@ always @(*) begin if (main_litedramcore_bankmachine4_row_opened) begin if (main_litedramcore_bankmachine4_row_hit) begin if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin - main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -8452,14 +6855,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_215 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_216; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine4_state) @@ -8489,14 +6885,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_216 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_217; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (builder_bankmachine4_state) @@ -8534,14 +6923,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (builder_bankmachine4_state) @@ -8579,14 +6961,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_218 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_219; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (builder_bankmachine4_state) @@ -8624,9 +6999,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_219 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; @@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_220; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin @@ -8653,17 +7021,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_220 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_221; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin @@ -8671,9 +7032,6 @@ always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_221 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; @@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_222; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin @@ -8703,9 +7057,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); @@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on always @(*) begin builder_bankmachine5_next_state <= 4'd0; builder_bankmachine5_next_state <= builder_bankmachine5_state; @@ -8779,14 +7126,71 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (builder_bankmachine5_state) @@ -8812,14 +7216,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_224 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_225; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (builder_bankmachine5_state) @@ -8860,14 +7257,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_open <= 1'd0; case (builder_bankmachine5_state) @@ -8893,14 +7283,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_close <= 1'd0; case (builder_bankmachine5_state) @@ -8926,14 +7309,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_227 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_228; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (builder_bankmachine5_state) @@ -8968,14 +7344,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_228 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_229; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (builder_bankmachine5_state) @@ -9004,14 +7373,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_229 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_230; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (builder_bankmachine5_state) @@ -9052,47 +7414,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_230 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_231; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_231 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_232; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine5_state) @@ -9122,14 +7444,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_232 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_233; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (builder_bankmachine5_state) @@ -9167,14 +7482,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_233 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_234; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (builder_bankmachine5_state) @@ -9212,14 +7520,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_234 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_235; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (builder_bankmachine5_state) @@ -9257,54 +7558,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_235 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_236; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_236 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; @@ -9320,10 +7573,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; - -// synthesis translate_off -reg dummy_d_237; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin @@ -9331,17 +7580,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin @@ -9349,9 +7591,6 @@ always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_238 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; @@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_239; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin @@ -9381,9 +7616,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); @@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on always @(*) begin builder_bankmachine6_next_state <= 4'd0; builder_bankmachine6_next_state <= builder_bankmachine6_state; @@ -9457,16 +7685,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_240 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_241; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -9475,9 +7696,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine6_twtpcon_ready) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9488,16 +7706,50 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) @@ -9538,22 +7790,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_242 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_243; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -9566,31 +7814,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_243 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_244; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) @@ -9616,14 +7842,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_244 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_245; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) @@ -9649,14 +7868,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) @@ -9691,14 +7903,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_246 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_247; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (builder_bankmachine6_state) @@ -9727,14 +7932,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_247 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_248; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) @@ -9775,47 +7973,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_248 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_249; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_249 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_250; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) @@ -9845,14 +8003,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_250 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_251; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) @@ -9890,14 +8041,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_251 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_252; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) @@ -9935,14 +8079,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_252 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_253; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) @@ -9980,9 +8117,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_253 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; @@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]); assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_254; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_a <= 16'd0; if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin @@ -10009,17 +8139,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_254 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_255; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin @@ -10027,9 +8150,6 @@ always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_255 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; @@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_256; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin @@ -10059,9 +8175,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_256 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); @@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_257; -// synthesis translate_on always @(*) begin builder_bankmachine7_next_state <= 4'd0; builder_bankmachine7_next_state <= builder_bankmachine7_state; @@ -10135,14 +8244,45 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_257 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_258; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) @@ -10168,14 +8308,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_258 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_259; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) @@ -10216,14 +8349,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_259 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_260; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_open <= 1'd0; case (builder_bankmachine7_state) @@ -10249,14 +8375,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_260 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_261; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) @@ -10282,14 +8401,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_261 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_262; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) @@ -10324,22 +8436,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_262 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_263; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -10352,31 +8460,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_263 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_264; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) @@ -10405,14 +8491,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_264 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_265; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) @@ -10453,47 +8532,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_265 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_266; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_266 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_267; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) @@ -10523,14 +8562,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_267 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_268; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) @@ -10568,14 +8600,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_268 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_269; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) @@ -10613,14 +8638,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_269 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_270; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) @@ -10658,9 +8676,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_270 = dummy_s; -// synthesis translate_on end assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); @@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); - -// synthesis translate_off -reg dummy_d_271; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_valids <= 8'd0; main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); @@ -10706,9 +8717,6 @@ always @(*) begin main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_271 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; @@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_272; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end -// synthesis translate_off - dummy_d_272 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_273; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end -// synthesis translate_off - dummy_d_273 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_274; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end -// synthesis translate_off - dummy_d_274 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_275; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin @@ -10768,14 +8751,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_275 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_276; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin @@ -10784,14 +8760,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_276 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_277; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin @@ -10800,14 +8769,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_277 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_278; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin @@ -10816,14 +8778,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_278 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_279; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin @@ -10832,14 +8787,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_279 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_280; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin @@ -10848,14 +8796,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin @@ -10864,14 +8805,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin @@ -10880,15 +8814,8 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_282 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); - -// synthesis translate_off -reg dummy_d_283; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_valids <= 8'd0; main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); @@ -10899,9 +8826,6 @@ always @(*) begin main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); -// synthesis translate_off - dummy_d_283 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; @@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; - -// synthesis translate_off -reg dummy_d_284; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end -// synthesis translate_off - dummy_d_284 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_285; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end -// synthesis translate_off - dummy_d_285 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); assign main_litedramcore_dfi_p0_reset_n = 1'd1; @@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1; assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on always @(*) begin builder_multiplexer_next_state <= 4'd0; builder_multiplexer_next_state <= builder_multiplexer_state; @@ -11023,27 +8922,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel1 <= 2'd0; + main_litedramcore_steerer_sel0 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel1 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; end - if ((main_litedramcore_wrcmdphase == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_wrcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; end end 2'd2: begin + main_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -11062,36 +8955,23 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel1 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 2'd2; + main_litedramcore_steerer_sel0 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 2'd2; end - if ((main_litedramcore_rdcmdphase == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 1'd1; + if ((main_litedramcore_rdcmdphase == 1'd0)) begin + main_litedramcore_steerer_sel0 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel2 <= 2'd0; + main_litedramcore_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel2 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 2'd2; - end - if ((main_litedramcore_wrcmdphase == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 1'd1; - end end 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -11110,30 +8990,19 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel2 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 2'd2; - end - if ((main_litedramcore_rdcmdphase == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 1'd1; - end end endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_cmd_want_activates <= 1'd0; + main_litedramcore_steerer_sel1 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; end end 2'd2: begin @@ -11155,30 +9024,26 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel3 <= 2'd0; + main_litedramcore_steerer_sel2 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel3 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; end - if ((main_litedramcore_wrcmdphase == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_wrcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; end end 2'd2: begin @@ -11200,27 +9065,24 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel3 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 2'd2; + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; end - if ((main_litedramcore_rdcmdphase == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 1'd1; + if ((main_litedramcore_rdcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on always @(*) begin - main_litedramcore_en0 <= 1'd0; + main_litedramcore_choose_cmd_want_activates <= 1'd0; case (builder_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -11241,24 +9103,23 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end endcase -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + main_litedramcore_steerer_sel3 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end 2'd2: begin @@ -11280,22 +9141,18 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_want_reads <= 1'd0; + main_litedramcore_en0 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin end @@ -11318,22 +9175,18 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_want_writes <= 1'd0; + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -11354,25 +9207,17 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end endcase -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; + main_litedramcore_choose_req_want_reads <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end end 2'd2: begin end @@ -11393,26 +9238,15 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on always @(*) begin - main_litedramcore_en1 <= 1'd0; + main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_en1 <= 1'd1; + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -11435,28 +9269,18 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel0 <= 2'd0; + main_litedramcore_choose_req_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel0 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin - main_litedramcore_steerer_sel0 <= 2'd2; - end - if ((main_litedramcore_wrcmdphase == 1'd0)) begin - main_litedramcore_steerer_sel0 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end 2'd2: begin - main_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -11475,30 +9299,21 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel0 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin - main_litedramcore_steerer_sel0 <= 2'd2; - end - if ((main_litedramcore_rdcmdphase == 1'd0)) begin - main_litedramcore_steerer_sel0 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_ready <= 1'd0; + main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_en1 <= 1'd1; end 2'd2: begin - main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -11519,9 +9334,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); @@ -11566,41 +9378,27 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on always @(*) begin - main_litedramcore_interface_wdata <= 128'd0; + main_litedramcore_interface_wdata_we <= 16'd0; case ({builder_new_master_wdata_ready1}) 1'd1: begin - main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - main_litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on always @(*) begin - main_litedramcore_interface_wdata_we <= 16'd0; + main_litedramcore_interface_wdata <= 128'd0; case ({builder_new_master_wdata_ready1}) 1'd1: begin - main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - main_litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on end assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; assign builder_roundrobin0_grant = 1'd0; @@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0; assign builder_roundrobin5_grant = 1'd0; assign builder_roundrobin6_grant = 1'd0; assign builder_roundrobin7_grant = 1'd0; - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on always @(*) begin builder_next_state <= 2'd0; builder_next_state <= builder_state; @@ -11631,173 +9425,114 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value0 <= 8'd0; + builder_litedramcore_wishbone_dat_r <= 32'd0; case (builder_state) 1'd1: begin end 2'd2: begin + builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; end default: begin - builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + builder_litedramcore_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin end 2'd2: begin end default: begin - builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on always @(*) begin - builder_litedramcore_adr_next_value1 <= 14'd0; + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; - end + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on always @(*) begin - builder_litedramcore_adr_next_value_ce1 <= 1'd0; + builder_litedramcore_wishbone_ack <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; end default: begin - if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_adr_next_value_ce1 <= 1'd1; - end end endcase -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on always @(*) begin - builder_litedramcore_we_next_value2 <= 1'd0; + builder_litedramcore_adr_next_value1 <= 14'd0; case (builder_state) 1'd1: begin - builder_litedramcore_we_next_value2 <= 1'd0; + builder_litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; end end endcase -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on always @(*) begin - builder_litedramcore_we_next_value_ce2 <= 1'd0; + builder_litedramcore_adr_next_value_ce1 <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_we_next_value_ce2 <= 1'd1; + builder_litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_we_next_value_ce2 <= 1'd1; + builder_litedramcore_adr_next_value_ce1 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on always @(*) begin - builder_litedramcore_wishbone_dat_r <= 32'd0; + builder_litedramcore_we_next_value2 <= 1'd0; case (builder_state) 1'd1: begin + builder_litedramcore_we_next_value2 <= 1'd0; end 2'd2: begin - builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; end default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + end end endcase -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on always @(*) begin - builder_litedramcore_wishbone_ack <= 1'd0; + builder_litedramcore_we_next_value_ce2 <= 1'd0; case (builder_state) 1'd1: begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin - builder_litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_we_next_value_ce2 <= 1'd1; + end end endcase -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on end assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; @@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we; assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; assign main_wb_bus_err = builder_litedramcore_wishbone_err; -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_we <= 1'd0; + builder_csrbank0_init_done0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; + builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_done0_w = main_init_done_storage; assign builder_csrbank0_init_error0_w = main_init_error_storage; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_337 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_338; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_338 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_339; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_339 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_340; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_340 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; @@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; - -// synthesis translate_off -reg dummy_d_341; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_control0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_341 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_342; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_control0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_342 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_343; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_343 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_344; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_344 = dummy_s; -// synthesis translate_on end -assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_345; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_345 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_346; -// synthesis translate_on +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_346 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_347; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_347 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_348; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_348 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_349; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin builder_csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_349 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_350; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_350 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_351; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_351 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_352; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_352 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_353; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_353 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_354; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_354 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_355; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_355 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_356; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_357 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_358; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_358 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_359; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_359 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_360; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_360 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_361; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_361 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_362; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_362 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_363; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_363 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_364; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_364 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_365; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_365 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_366; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_366 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_367; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_367 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_368; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_368 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_369; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_369 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_370; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_370 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_371; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_371 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_372; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_372 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_373; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_373 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_374; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_374 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_375; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin builder_csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_375 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_376; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_376 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_377; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_377 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_378; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_378 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_379; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_379 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_380; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_380 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_381; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_381 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_382; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_382 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_383; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_383 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_384; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_384 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_385; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_385 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_386; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_386 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_387; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_387 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_388; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_388 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_389; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_389 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_390; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_390 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_391; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_391 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_392; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_392 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_393; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_393 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_394; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_394 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_395; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_395 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_396; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_396 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_397; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_397 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_398; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_398 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_399; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi2_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_399 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_400; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_400 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_401; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_401 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_402; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_402 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_403; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_403 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_404; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_404 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_405; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_405 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_406; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_406 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_407; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_407 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_408; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_408 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_409; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_409 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_410; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_410 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_411; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_411 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_412; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_412 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_413; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_413 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_414; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_414 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_415; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_416; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_416 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_417; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_417 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_418; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_418 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_419; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_419 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_420; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_420 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_421; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_421 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_422; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_422 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_423; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_423 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_424; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_424 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_425; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_425 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_426; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_426 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_427; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_427 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_428; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_428 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_429; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_429 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_430; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_430 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_431; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_431 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_432; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_432 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_433; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_433 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_434; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_434 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_435; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_435 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_436; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_436 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_437; -// synthesis translate_on +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_437 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_438; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_438 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_439; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_439 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_440; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_440 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_441; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_441 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_442; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_442 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_443; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_443 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_444; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_444 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_445; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_445 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_446; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_446 = dummy_s; -// synthesis translate_on end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; @@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; -assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[15:8]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0]; assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; -assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; -assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[15:8]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0]; assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; -assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; -assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[15:8]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0]; assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; -assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; -assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[15:8]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0]; assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; -assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_csr_interconnect_adr = builder_litedramcore_adr; assign builder_csr_interconnect_we = builder_litedramcore_we; assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; @@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); - -// synthesis translate_off -reg dummy_d_447; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13760,14 +10147,7 @@ always @(*) begin builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase -// synthesis translate_off - dummy_d_447 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_448; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed1 <= 16'd0; case (main_litedramcore_choose_cmd_grant) @@ -13796,14 +10176,7 @@ always @(*) begin builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_448 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_449; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed2 <= 3'd0; case (main_litedramcore_choose_cmd_grant) @@ -13832,14 +10205,7 @@ always @(*) begin builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_449 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_450; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed3 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13868,14 +10234,7 @@ always @(*) begin builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_450 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_451; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed4 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13904,14 +10263,7 @@ always @(*) begin builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_451 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_452; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed5 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13940,14 +10292,7 @@ always @(*) begin builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_452 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_453; -// synthesis translate_on always @(*) begin builder_t_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13976,14 +10321,7 @@ always @(*) begin builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_453 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_454; -// synthesis translate_on always @(*) begin builder_t_array_muxed1 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14012,14 +10350,7 @@ always @(*) begin builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_454 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_455; -// synthesis translate_on always @(*) begin builder_t_array_muxed2 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14048,14 +10379,7 @@ always @(*) begin builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_455 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_456; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed6 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14084,14 +10408,7 @@ always @(*) begin builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase -// synthesis translate_off - dummy_d_456 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_457; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed7 <= 16'd0; case (main_litedramcore_choose_req_grant) @@ -14120,14 +10437,7 @@ always @(*) begin builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_457 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_458; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed8 <= 3'd0; case (main_litedramcore_choose_req_grant) @@ -14156,14 +10466,7 @@ always @(*) begin builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_458 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_459; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed9 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14192,14 +10495,7 @@ always @(*) begin builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_459 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_460; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed10 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14228,14 +10524,7 @@ always @(*) begin builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_460 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_461; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed11 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14264,14 +10553,7 @@ always @(*) begin builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_461 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_462; -// synthesis translate_on always @(*) begin builder_t_array_muxed3 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14300,14 +10582,7 @@ always @(*) begin builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_462 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_463; -// synthesis translate_on always @(*) begin builder_t_array_muxed4 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14336,14 +10611,7 @@ always @(*) begin builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_463 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_464; -// synthesis translate_on always @(*) begin builder_t_array_muxed5 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14372,14 +10640,7 @@ always @(*) begin builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_464 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_465; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed12 <= 23'd0; case (builder_roundrobin0_grant) @@ -14387,14 +10648,7 @@ always @(*) begin builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_465 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_466; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed13 <= 1'd0; case (builder_roundrobin0_grant) @@ -14402,14 +10656,7 @@ always @(*) begin builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_466 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_467; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed14 <= 1'd0; case (builder_roundrobin0_grant) @@ -14417,14 +10664,7 @@ always @(*) begin builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_467 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_468; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed15 <= 23'd0; case (builder_roundrobin1_grant) @@ -14432,14 +10672,7 @@ always @(*) begin builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_468 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_469; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed16 <= 1'd0; case (builder_roundrobin1_grant) @@ -14447,14 +10680,7 @@ always @(*) begin builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_469 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_470; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed17 <= 1'd0; case (builder_roundrobin1_grant) @@ -14462,14 +10688,7 @@ always @(*) begin builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_470 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_471; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed18 <= 23'd0; case (builder_roundrobin2_grant) @@ -14477,14 +10696,7 @@ always @(*) begin builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_471 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_472; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed19 <= 1'd0; case (builder_roundrobin2_grant) @@ -14492,14 +10704,7 @@ always @(*) begin builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_472 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_473; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed20 <= 1'd0; case (builder_roundrobin2_grant) @@ -14507,14 +10712,7 @@ always @(*) begin builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_473 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_474; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed21 <= 23'd0; case (builder_roundrobin3_grant) @@ -14522,14 +10720,7 @@ always @(*) begin builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_474 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_475; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed22 <= 1'd0; case (builder_roundrobin3_grant) @@ -14537,14 +10728,7 @@ always @(*) begin builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_475 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_476; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed23 <= 1'd0; case (builder_roundrobin3_grant) @@ -14552,14 +10736,7 @@ always @(*) begin builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_476 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_477; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed24 <= 23'd0; case (builder_roundrobin4_grant) @@ -14567,14 +10744,7 @@ always @(*) begin builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_477 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_478; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed25 <= 1'd0; case (builder_roundrobin4_grant) @@ -14582,14 +10752,7 @@ always @(*) begin builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_478 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_479; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed26 <= 1'd0; case (builder_roundrobin4_grant) @@ -14597,14 +10760,7 @@ always @(*) begin builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_479 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_480; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed27 <= 23'd0; case (builder_roundrobin5_grant) @@ -14612,14 +10768,7 @@ always @(*) begin builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_480 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_481; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed28 <= 1'd0; case (builder_roundrobin5_grant) @@ -14627,14 +10776,7 @@ always @(*) begin builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_481 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_482; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed29 <= 1'd0; case (builder_roundrobin5_grant) @@ -14642,14 +10784,7 @@ always @(*) begin builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_482 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_483; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed30 <= 23'd0; case (builder_roundrobin6_grant) @@ -14657,14 +10792,7 @@ always @(*) begin builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_483 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_484; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed31 <= 1'd0; case (builder_roundrobin6_grant) @@ -14672,14 +10800,7 @@ always @(*) begin builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_484 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_485; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed32 <= 1'd0; case (builder_roundrobin6_grant) @@ -14687,14 +10808,7 @@ always @(*) begin builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_485 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_486; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed33 <= 23'd0; case (builder_roundrobin7_grant) @@ -14702,14 +10816,7 @@ always @(*) begin builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[25:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_486 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_487; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed34 <= 1'd0; case (builder_roundrobin7_grant) @@ -14717,14 +10824,7 @@ always @(*) begin builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_487 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_488; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed35 <= 1'd0; case (builder_roundrobin7_grant) @@ -14732,14 +10832,7 @@ always @(*) begin builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_488 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_489; -// synthesis translate_on always @(*) begin builder_array_muxed0 <= 3'd0; case (main_litedramcore_steerer_sel0) @@ -14756,14 +10849,7 @@ always @(*) begin builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_489 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_490; -// synthesis translate_on always @(*) begin builder_array_muxed1 <= 16'd0; case (main_litedramcore_steerer_sel0) @@ -14780,14 +10866,7 @@ always @(*) begin builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_490 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_491; -// synthesis translate_on always @(*) begin builder_array_muxed2 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14804,14 +10883,7 @@ always @(*) begin builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_491 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_492; -// synthesis translate_on always @(*) begin builder_array_muxed3 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14828,14 +10900,7 @@ always @(*) begin builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_492 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_493; -// synthesis translate_on always @(*) begin builder_array_muxed4 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14852,14 +10917,7 @@ always @(*) begin builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_493 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_494; -// synthesis translate_on always @(*) begin builder_array_muxed5 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14876,14 +10934,7 @@ always @(*) begin builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_494 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_495; -// synthesis translate_on always @(*) begin builder_array_muxed6 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14900,14 +10951,7 @@ always @(*) begin builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_495 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_496; -// synthesis translate_on always @(*) begin builder_array_muxed7 <= 3'd0; case (main_litedramcore_steerer_sel1) @@ -14924,14 +10968,7 @@ always @(*) begin builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_496 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_497; -// synthesis translate_on always @(*) begin builder_array_muxed8 <= 16'd0; case (main_litedramcore_steerer_sel1) @@ -14948,14 +10985,7 @@ always @(*) begin builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_497 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_498; -// synthesis translate_on always @(*) begin builder_array_muxed9 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14972,14 +11002,7 @@ always @(*) begin builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_498 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_499; -// synthesis translate_on always @(*) begin builder_array_muxed10 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14996,14 +11019,7 @@ always @(*) begin builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_499 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_500; -// synthesis translate_on always @(*) begin builder_array_muxed11 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15020,14 +11036,7 @@ always @(*) begin builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_500 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_501; -// synthesis translate_on always @(*) begin builder_array_muxed12 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15044,14 +11053,7 @@ always @(*) begin builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_501 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_502; -// synthesis translate_on always @(*) begin builder_array_muxed13 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15068,14 +11070,7 @@ always @(*) begin builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_502 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_503; -// synthesis translate_on always @(*) begin builder_array_muxed14 <= 3'd0; case (main_litedramcore_steerer_sel2) @@ -15092,14 +11087,7 @@ always @(*) begin builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_503 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_504; -// synthesis translate_on always @(*) begin builder_array_muxed15 <= 16'd0; case (main_litedramcore_steerer_sel2) @@ -15116,14 +11104,7 @@ always @(*) begin builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_504 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_505; -// synthesis translate_on always @(*) begin builder_array_muxed16 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15140,14 +11121,7 @@ always @(*) begin builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_505 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_506; -// synthesis translate_on always @(*) begin builder_array_muxed17 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15164,14 +11138,7 @@ always @(*) begin builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_506 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_507; -// synthesis translate_on always @(*) begin builder_array_muxed18 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15188,14 +11155,7 @@ always @(*) begin builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_507 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_508; -// synthesis translate_on always @(*) begin builder_array_muxed19 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15212,14 +11172,7 @@ always @(*) begin builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_508 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_509; -// synthesis translate_on always @(*) begin builder_array_muxed20 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15236,14 +11189,7 @@ always @(*) begin builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_509 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_510; -// synthesis translate_on always @(*) begin builder_array_muxed21 <= 3'd0; case (main_litedramcore_steerer_sel3) @@ -15260,14 +11206,7 @@ always @(*) begin builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_510 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_511; -// synthesis translate_on always @(*) begin builder_array_muxed22 <= 16'd0; case (main_litedramcore_steerer_sel3) @@ -15284,14 +11223,7 @@ always @(*) begin builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_511 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_512; -// synthesis translate_on always @(*) begin builder_array_muxed23 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15308,14 +11240,7 @@ always @(*) begin builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_512 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_513; -// synthesis translate_on always @(*) begin builder_array_muxed24 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15332,14 +11257,7 @@ always @(*) begin builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_513 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_514; -// synthesis translate_on always @(*) begin builder_array_muxed25 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15356,14 +11274,7 @@ always @(*) begin builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_514 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_515; -// synthesis translate_on always @(*) begin builder_array_muxed26 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15380,14 +11291,7 @@ always @(*) begin builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_515 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_516; -// synthesis translate_on always @(*) begin builder_array_muxed27 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15404,15 +11308,17 @@ always @(*) begin builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_516 = dummy_s; -// synthesis translate_on end assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge iodelay_clk) begin if ((main_reset_counter != 1'd0)) begin main_reset_counter <= (main_reset_counter - 1'd1); @@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end @@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; - if (builder_csrbank2_dfii_pi0_address1_re) begin - main_litedramcore_phaseinjector0_address_storage[15:8] <= builder_csrbank2_dfii_pi0_address1_r; - end if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; - if (builder_csrbank2_dfii_pi0_wrdata3_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; - end - if (builder_csrbank2_dfii_pi0_wrdata2_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; - end - if (builder_csrbank2_dfii_pi0_wrdata1_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; - end if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; - main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; - if (builder_csrbank2_dfii_pi1_address1_re) begin - main_litedramcore_phaseinjector1_address_storage[15:8] <= builder_csrbank2_dfii_pi1_address1_r; - end if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; - if (builder_csrbank2_dfii_pi1_wrdata3_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; - end - if (builder_csrbank2_dfii_pi1_wrdata2_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; - end - if (builder_csrbank2_dfii_pi1_wrdata1_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; - end if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; - main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; - if (builder_csrbank2_dfii_pi2_address1_re) begin - main_litedramcore_phaseinjector2_address_storage[15:8] <= builder_csrbank2_dfii_pi2_address1_r; - end if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; - if (builder_csrbank2_dfii_pi2_wrdata3_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; - end - if (builder_csrbank2_dfii_pi2_wrdata2_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; - end - if (builder_csrbank2_dfii_pi2_wrdata1_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; - end if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; - main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; - if (builder_csrbank2_dfii_pi3_address1_re) begin - main_litedramcore_phaseinjector3_address_storage[15:8] <= builder_csrbank2_dfii_pi3_address1_r; - end if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; - if (builder_csrbank2_dfii_pi3_wrdata3_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; - end - if (builder_csrbank2_dfii_pi3_wrdata2_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; - end - if (builder_csrbank2_dfii_pi3_wrdata1_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; - end if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; - main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin main_a7ddrphy_rst_storage <= 1'd0; main_a7ddrphy_rst_re <= 1'd0; @@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + BUFG BUFG( .I(main_clkout0), .O(main_clkout_buf0) @@ -19625,118 +15404,150 @@ IOBUF IOBUF_15( .O(main_a7ddrphy_dq_i_nodelay15) ); +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage[0:15]; -reg [25:0] memdat; +reg [25:0] storage_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_1[0:15]; -reg [25:0] memdat_1; +reg [25:0] storage_1_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_2[0:15]; -reg [25:0] memdat_2; +reg [25:0] storage_2_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_3[0:15]; -reg [25:0] memdat_3; +reg [25:0] storage_3_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_4[0:15]; -reg [25:0] memdat_4; +reg [25:0] storage_4_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_5[0:15]; -reg [25:0] memdat_5; +reg [25:0] storage_5_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_6[0:15]; -reg [25:0] memdat_6; +reg [25:0] storage_6_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 26-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 +// Port 1 | Read: Async | Write: ---- | reg [25:0] storage_7[0:15]; -reg [25:0] memdat_7; +reg [25:0] storage_7_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + FD FD( .C(main_clkin), .D(main_reset), @@ -19893,3 +15704,7 @@ PLLE2_ADV #( ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 08:32:13. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 5b1a383..1b6e88e 100644 --- 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-7c9e20507f65db78 -7d21e2144bfffed4 -38e0000a39000020 -9ac9002038c00001 -392000007f25cb78 -7fa3eb787c8af850 -e92100604bfffac1 -e92100609b690000 -f921006039290001 -7d21e2144bfffea0 -f901009038a0000a -38800000f9410088 -9ac900207f23cb78 -600000004bfff72d -7f63db78f8610080 -600000004bfff83d -7c291840e9210080 -7d2348514081004c -e9010090e9410088 -408200087d4af850 -e8c1006039200001 -7c2a38407ce83050 -38e0002040810024 -3929ffff2c290001 -e8e1006098e60000 -f8e1006038e70001 -e88100604082ffd4 -7fa3eb787f65db78 -7c84f8507c9e2050 -4bfffdfc4bfff989 -418200482807006c -4bfffdec3b400008 -3b40000228070068 -7c9823784082fde0 -4bfffdd43b400001 -554a063e3949ffd0 -4181fdc4280a0009 -7f81e214395c0001 -795c0020993c0020 -7c9823784bfffdb0 -993e00004bffffb8 -e92100607d455378 -f921006039290001 -000000004bfffae8 +4bfffe2c4bfff979 +392900019a490000 +7c29184039000001 +f921006040820034 +7ce9f0504bffffcc +7ce7fa147c634050 +2c2700007d4af850 +390000007c691a14 +40820008394a0001 +2c2a000139400001 +4082ffb4394affff +4082ffc071080001 +893900014bffff8c +4182004c2c09006c +4bfffdbc3b400008 +3b40000289390001 +4082fdac2c090068 +3b4000017cb92b78 +3928ffd04bfffda0 +280900095529063e +7b6900204181fd90 +7d214a143b7b0001 +4bfffd7c99090020 +4bffffb47cb92b78 +3bde0001993e0000 +fbc100607d054378 +000000004bfffa6c 0000128001000000 f9e1ff78f9c1ff70 fa21ff88fa01ff80 @@ -1938,9 +1858,8 @@ ebe1fff8e8010010 203a46464f204853 7479622078257830 00000000000a7365 -3536373832306564 +2d2d2d2d2d2d2d2d 0000000000000000 -0032363263623561 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1982,10 +1901,6 @@ ebe1fff8e8010010 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -62202c64256d2020 -007c203a64323025 -0000000000006425 -000000000000207c 203a7379616c6564 000000000000002d 203a7379616c6564 @@ -2001,15 +1916,13 @@ ebe1fff8e8010010 7764726168206f74 746e6f6320657261 0000000a2e6c6f72 +62202c64256d2020 +007c203a64323025 +0000000000006425 +000000000000207c 203a747365622020 302562202c64256d 6000000000206432 -616c206574697257 -61632079636e6574 -6f6974617262696c -00000000000a3a6e -0000202d3a64256d -002064253a64256d 76656c2064616552 000a3a676e696c65 696c616974696e49 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 525dde1..cad0120 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,9 +1,25 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:31 -//-------------------------------------------------------------------------------- -module litedram_core( - input wire clk, - input wire rst, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 08:32:09 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + input wire rst, output wire pll_locked, output wire [13:0] ddram_a, output wire [2:0] ddram_ba, @@ -12,9 +28,9 @@ module litedram_core( output wire ddram_we_n, output wire ddram_cs_n, output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, @@ -22,32 +38,38 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, + input wire user_port_native_0_rdata_ready, output wire [127:0] user_port_native_0_rdata_data ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_rst = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -55,7 +77,7 @@ wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; wire main_reset; -reg main_power_down = 1'd0; +reg main_power_down = 1'd0; wire main_locked; wire main_clkin; wire main_clkout0; @@ -66,48 +88,48 @@ wire main_clkout2; wire main_clkout_buf2; wire main_clkout3; wire main_clkout_buf3; -reg [3:0] main_reset_counter = 4'd15; -reg main_ic_reset = 1'd1; -reg main_a7ddrphy_rst_storage = 1'd0; -reg main_a7ddrphy_rst_re = 1'd0; -reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg main_a7ddrphy_wlevel_en_storage = 1'd0; -reg main_a7ddrphy_wlevel_en_re = 1'd0; -reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; wire main_a7ddrphy_wlevel_strobe_r; -reg main_a7ddrphy_wlevel_strobe_we = 1'd0; -reg main_a7ddrphy_wlevel_strobe_w = 1'd0; -reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; -reg main_a7ddrphy_dly_sel_re = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_rst_r; -reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; wire main_a7ddrphy_rdly_dq_inc_r; -reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_rst_r; -reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_r; -reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_rst_r; -reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_r; -reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; -reg main_a7ddrphy_rdphase_re = 1'd0; -reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; -reg main_a7ddrphy_wrphase_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; wire [13:0] main_a7ddrphy_dfi_p0_address; wire [2:0] main_a7ddrphy_dfi_p0_bank; wire main_a7ddrphy_dfi_p0_cas_n; @@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata; wire main_a7ddrphy_dfi_p0_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; wire main_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; wire main_a7ddrphy_dfi_p0_rddata_valid; wire [13:0] main_a7ddrphy_dfi_p1_address; wire [2:0] main_a7ddrphy_dfi_p1_bank; @@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata; wire main_a7ddrphy_dfi_p1_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; wire main_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; wire main_a7ddrphy_dfi_p1_rddata_valid; wire [13:0] main_a7ddrphy_dfi_p2_address; wire [2:0] main_a7ddrphy_dfi_p2_bank; @@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata; wire main_a7ddrphy_dfi_p2_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; wire main_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; wire main_a7ddrphy_dfi_p2_rddata_valid; wire [13:0] main_a7ddrphy_dfi_p3_address; wire [2:0] main_a7ddrphy_dfi_p3_bank; @@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata; wire main_a7ddrphy_dfi_p3_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; wire main_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; wire main_a7ddrphy_dfi_p3_rddata_valid; wire main_a7ddrphy_sd_clk_se_nodelay; -reg main_a7ddrphy_dqs_oe = 1'd0; +reg main_a7ddrphy_dqs_oe = 1'd0; wire main_a7ddrphy_dqs_preamble; wire main_a7ddrphy_dqs_postamble; wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_dqspattern0 = 1'd0; -reg main_a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; wire main_a7ddrphy_dqs_o_no_delay0; wire main_a7ddrphy_dqs_t0; -reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; wire main_a7ddrphy0; wire main_a7ddrphy_dqs_o_no_delay1; wire main_a7ddrphy_dqs_t1; -reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; wire main_a7ddrphy1; -reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; wire main_a7ddrphy_dq_oe; wire main_a7ddrphy_dq_oe_delay_tappeddelayline; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire main_a7ddrphy_dq_o_nodelay0; wire main_a7ddrphy_dq_i_nodelay0; wire main_a7ddrphy_dq_i_delayed0; wire main_a7ddrphy_dq_t0; -reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip03; -reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay1; wire main_a7ddrphy_dq_i_nodelay1; wire main_a7ddrphy_dq_i_delayed1; wire main_a7ddrphy_dq_t1; -reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip13; -reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay2; wire main_a7ddrphy_dq_i_nodelay2; wire main_a7ddrphy_dq_i_delayed2; wire main_a7ddrphy_dq_t2; -reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip21; -reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay3; wire main_a7ddrphy_dq_i_nodelay3; wire main_a7ddrphy_dq_i_delayed3; wire main_a7ddrphy_dq_t3; -reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip31; -reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay4; wire main_a7ddrphy_dq_i_nodelay4; wire main_a7ddrphy_dq_i_delayed4; wire main_a7ddrphy_dq_t4; -reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip41; -reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay5; wire main_a7ddrphy_dq_i_nodelay5; wire main_a7ddrphy_dq_i_delayed5; wire main_a7ddrphy_dq_t5; -reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip51; -reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay6; wire main_a7ddrphy_dq_i_nodelay6; wire main_a7ddrphy_dq_i_delayed6; wire main_a7ddrphy_dq_t6; -reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip61; -reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay7; wire main_a7ddrphy_dq_i_nodelay7; wire main_a7ddrphy_dq_i_delayed7; wire main_a7ddrphy_dq_t7; -reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip71; -reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay8; wire main_a7ddrphy_dq_i_nodelay8; wire main_a7ddrphy_dq_i_delayed8; wire main_a7ddrphy_dq_t8; -reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip81; -reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay9; wire main_a7ddrphy_dq_i_nodelay9; wire main_a7ddrphy_dq_i_delayed9; wire main_a7ddrphy_dq_t9; -reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip91; -reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay10; wire main_a7ddrphy_dq_i_nodelay10; wire main_a7ddrphy_dq_i_delayed10; wire main_a7ddrphy_dq_t10; -reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip101; -reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay11; wire main_a7ddrphy_dq_i_nodelay11; wire main_a7ddrphy_dq_i_delayed11; wire main_a7ddrphy_dq_t11; -reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip111; -reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay12; wire main_a7ddrphy_dq_i_nodelay12; wire main_a7ddrphy_dq_i_delayed12; wire main_a7ddrphy_dq_t12; -reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip121; -reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay13; wire main_a7ddrphy_dq_i_nodelay13; wire main_a7ddrphy_dq_i_delayed13; wire main_a7ddrphy_dq_t13; -reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip131; -reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay14; wire main_a7ddrphy_dq_i_nodelay14; wire main_a7ddrphy_dq_i_delayed14; wire main_a7ddrphy_dq_t14; -reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip141; -reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay15; wire main_a7ddrphy_dq_i_nodelay15; wire main_a7ddrphy_dq_i_delayed15; wire main_a7ddrphy_dq_t15; -reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip151; -reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [13:0] main_litedramcore_inti_p0_address; wire [2:0] main_litedramcore_inti_p0_bank; -reg main_litedramcore_inti_p0_cas_n = 1'd1; -reg main_litedramcore_inti_p0_cs_n = 1'd1; -reg main_litedramcore_inti_p0_ras_n = 1'd1; -reg main_litedramcore_inti_p0_we_n = 1'd1; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; wire main_litedramcore_inti_p0_cke; wire main_litedramcore_inti_p0_odt; wire main_litedramcore_inti_p0_reset_n; -reg main_litedramcore_inti_p0_act_n = 1'd1; +reg main_litedramcore_inti_p0_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p0_wrdata; wire main_litedramcore_inti_p0_wrdata_en; wire [3:0] main_litedramcore_inti_p0_wrdata_mask; wire main_litedramcore_inti_p0_rddata_en; -reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; -reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; wire [13:0] main_litedramcore_inti_p1_address; wire [2:0] main_litedramcore_inti_p1_bank; -reg main_litedramcore_inti_p1_cas_n = 1'd1; -reg main_litedramcore_inti_p1_cs_n = 1'd1; -reg main_litedramcore_inti_p1_ras_n = 1'd1; -reg main_litedramcore_inti_p1_we_n = 1'd1; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; wire main_litedramcore_inti_p1_cke; wire main_litedramcore_inti_p1_odt; wire main_litedramcore_inti_p1_reset_n; -reg main_litedramcore_inti_p1_act_n = 1'd1; +reg main_litedramcore_inti_p1_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p1_wrdata; wire main_litedramcore_inti_p1_wrdata_en; wire [3:0] main_litedramcore_inti_p1_wrdata_mask; wire main_litedramcore_inti_p1_rddata_en; -reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; -reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; wire [13:0] main_litedramcore_inti_p2_address; wire [2:0] main_litedramcore_inti_p2_bank; -reg main_litedramcore_inti_p2_cas_n = 1'd1; -reg main_litedramcore_inti_p2_cs_n = 1'd1; -reg main_litedramcore_inti_p2_ras_n = 1'd1; -reg main_litedramcore_inti_p2_we_n = 1'd1; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; wire main_litedramcore_inti_p2_cke; wire main_litedramcore_inti_p2_odt; wire main_litedramcore_inti_p2_reset_n; -reg main_litedramcore_inti_p2_act_n = 1'd1; +reg main_litedramcore_inti_p2_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p2_wrdata; wire main_litedramcore_inti_p2_wrdata_en; wire [3:0] main_litedramcore_inti_p2_wrdata_mask; wire main_litedramcore_inti_p2_rddata_en; -reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; -reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; wire [13:0] main_litedramcore_inti_p3_address; wire [2:0] main_litedramcore_inti_p3_bank; -reg main_litedramcore_inti_p3_cas_n = 1'd1; -reg main_litedramcore_inti_p3_cs_n = 1'd1; -reg main_litedramcore_inti_p3_ras_n = 1'd1; -reg main_litedramcore_inti_p3_we_n = 1'd1; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; wire main_litedramcore_inti_p3_cke; wire main_litedramcore_inti_p3_odt; wire main_litedramcore_inti_p3_reset_n; -reg main_litedramcore_inti_p3_act_n = 1'd1; +reg main_litedramcore_inti_p3_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p3_wrdata; wire main_litedramcore_inti_p3_wrdata_en; wire [3:0] main_litedramcore_inti_p3_wrdata_mask; wire main_litedramcore_inti_p3_rddata_en; -reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; -reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p0_address; wire [2:0] main_litedramcore_slave_p0_bank; wire main_litedramcore_slave_p0_cas_n; @@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata; wire main_litedramcore_slave_p0_wrdata_en; wire [3:0] main_litedramcore_slave_p0_wrdata_mask; wire main_litedramcore_slave_p0_rddata_en; -reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; -reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p1_address; wire [2:0] main_litedramcore_slave_p1_bank; wire main_litedramcore_slave_p1_cas_n; @@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata; wire main_litedramcore_slave_p1_wrdata_en; wire [3:0] main_litedramcore_slave_p1_wrdata_mask; wire main_litedramcore_slave_p1_rddata_en; -reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; -reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p2_address; wire [2:0] main_litedramcore_slave_p2_bank; wire main_litedramcore_slave_p2_cas_n; @@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata; wire main_litedramcore_slave_p2_wrdata_en; wire [3:0] main_litedramcore_slave_p2_wrdata_mask; wire main_litedramcore_slave_p2_rddata_en; -reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; -reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p3_address; wire [2:0] main_litedramcore_slave_p3_bank; wire main_litedramcore_slave_p3_cas_n; @@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata; wire main_litedramcore_slave_p3_wrdata_en; wire [3:0] main_litedramcore_slave_p3_wrdata_mask; wire main_litedramcore_slave_p3_rddata_en; -reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; -reg main_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] main_litedramcore_master_p0_address = 14'd0; -reg [2:0] main_litedramcore_master_p0_bank = 3'd0; -reg main_litedramcore_master_p0_cas_n = 1'd1; -reg main_litedramcore_master_p0_cs_n = 1'd1; -reg main_litedramcore_master_p0_ras_n = 1'd1; -reg main_litedramcore_master_p0_we_n = 1'd1; -reg main_litedramcore_master_p0_cke = 1'd0; -reg main_litedramcore_master_p0_odt = 1'd0; -reg main_litedramcore_master_p0_reset_n = 1'd0; -reg main_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; -reg main_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; -reg main_litedramcore_master_p0_rddata_en = 1'd0; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] main_litedramcore_master_p0_address = 14'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p0_rddata; wire main_litedramcore_master_p0_rddata_valid; -reg [13:0] main_litedramcore_master_p1_address = 14'd0; -reg [2:0] main_litedramcore_master_p1_bank = 3'd0; -reg main_litedramcore_master_p1_cas_n = 1'd1; -reg main_litedramcore_master_p1_cs_n = 1'd1; -reg main_litedramcore_master_p1_ras_n = 1'd1; -reg main_litedramcore_master_p1_we_n = 1'd1; -reg main_litedramcore_master_p1_cke = 1'd0; -reg main_litedramcore_master_p1_odt = 1'd0; -reg main_litedramcore_master_p1_reset_n = 1'd0; -reg main_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; -reg main_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; -reg main_litedramcore_master_p1_rddata_en = 1'd0; +reg [13:0] main_litedramcore_master_p1_address = 14'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p1_rddata; wire main_litedramcore_master_p1_rddata_valid; -reg [13:0] main_litedramcore_master_p2_address = 14'd0; -reg [2:0] main_litedramcore_master_p2_bank = 3'd0; -reg main_litedramcore_master_p2_cas_n = 1'd1; -reg main_litedramcore_master_p2_cs_n = 1'd1; -reg main_litedramcore_master_p2_ras_n = 1'd1; -reg main_litedramcore_master_p2_we_n = 1'd1; -reg main_litedramcore_master_p2_cke = 1'd0; -reg main_litedramcore_master_p2_odt = 1'd0; -reg main_litedramcore_master_p2_reset_n = 1'd0; -reg main_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; -reg main_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; -reg main_litedramcore_master_p2_rddata_en = 1'd0; +reg [13:0] main_litedramcore_master_p2_address = 14'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p2_rddata; wire main_litedramcore_master_p2_rddata_valid; -reg [13:0] main_litedramcore_master_p3_address = 14'd0; -reg [2:0] main_litedramcore_master_p3_bank = 3'd0; -reg main_litedramcore_master_p3_cas_n = 1'd1; -reg main_litedramcore_master_p3_cs_n = 1'd1; -reg main_litedramcore_master_p3_ras_n = 1'd1; -reg main_litedramcore_master_p3_we_n = 1'd1; -reg main_litedramcore_master_p3_cke = 1'd0; -reg main_litedramcore_master_p3_odt = 1'd0; -reg main_litedramcore_master_p3_reset_n = 1'd0; -reg main_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; -reg main_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; -reg main_litedramcore_master_p3_rddata_en = 1'd0; +reg [13:0] main_litedramcore_master_p3_address = 14'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p3_rddata; wire main_litedramcore_master_p3_rddata_valid; wire main_litedramcore_sel; wire main_litedramcore_cke; wire main_litedramcore_odt; wire main_litedramcore_reset_n; -reg [3:0] main_litedramcore_storage = 4'd1; -reg main_litedramcore_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; -reg main_litedramcore_phaseinjector0_command_re = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector0_command_issue_r; -reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; -reg main_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; wire main_litedramcore_phaseinjector0_rddata_we; -reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; -reg main_litedramcore_phaseinjector1_command_re = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector1_command_issue_r; -reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; -reg main_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; wire main_litedramcore_phaseinjector1_rddata_we; -reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; -reg main_litedramcore_phaseinjector2_command_re = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector2_command_issue_r; -reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; -reg main_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; wire main_litedramcore_phaseinjector2_rddata_we; -reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; -reg main_litedramcore_phaseinjector3_command_re = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector3_command_issue_r; -reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; -reg main_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; wire main_litedramcore_phaseinjector3_rddata_we; -reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; wire main_litedramcore_interface_bank0_valid; wire main_litedramcore_interface_bank0_ready; wire main_litedramcore_interface_bank0_we; @@ -706,131 +728,131 @@ wire [20:0] main_litedramcore_interface_bank7_addr; wire main_litedramcore_interface_bank7_lock; wire main_litedramcore_interface_bank7_wdata_ready; wire main_litedramcore_interface_bank7_rdata_valid; -reg [127:0] main_litedramcore_interface_wdata = 128'd0; -reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; wire [127:0] main_litedramcore_interface_rdata; -reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; -reg main_litedramcore_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_dfi_p0_ras_n = 1'd1; -reg main_litedramcore_dfi_p0_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; wire main_litedramcore_dfi_p0_cke; wire main_litedramcore_dfi_p0_odt; wire main_litedramcore_dfi_p0_reset_n; -reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg main_litedramcore_dfi_p0_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p0_wrdata; -reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; -reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p0_rddata; wire main_litedramcore_dfi_p0_rddata_valid; -reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; -reg main_litedramcore_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_dfi_p1_ras_n = 1'd1; -reg main_litedramcore_dfi_p1_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; wire main_litedramcore_dfi_p1_cke; wire main_litedramcore_dfi_p1_odt; wire main_litedramcore_dfi_p1_reset_n; -reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg main_litedramcore_dfi_p1_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p1_wrdata; -reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; -reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p1_rddata; wire main_litedramcore_dfi_p1_rddata_valid; -reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; -reg main_litedramcore_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_dfi_p2_ras_n = 1'd1; -reg main_litedramcore_dfi_p2_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; wire main_litedramcore_dfi_p2_cke; wire main_litedramcore_dfi_p2_odt; wire main_litedramcore_dfi_p2_reset_n; -reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg main_litedramcore_dfi_p2_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p2_wrdata; -reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; -reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p2_rddata; wire main_litedramcore_dfi_p2_rddata_valid; -reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; -reg main_litedramcore_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_dfi_p3_ras_n = 1'd1; -reg main_litedramcore_dfi_p3_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; wire main_litedramcore_dfi_p3_cke; wire main_litedramcore_dfi_p3_odt; wire main_litedramcore_dfi_p3_reset_n; -reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg main_litedramcore_dfi_p3_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p3_wrdata; -reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; -reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p3_rddata; wire main_litedramcore_dfi_p3_rddata_valid; -reg main_litedramcore_cmd_valid = 1'd0; -reg main_litedramcore_cmd_ready = 1'd0; -reg main_litedramcore_cmd_last = 1'd0; -reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; -reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; -reg main_litedramcore_cmd_payload_cas = 1'd0; -reg main_litedramcore_cmd_payload_ras = 1'd0; -reg main_litedramcore_cmd_payload_we = 1'd0; -reg main_litedramcore_cmd_payload_is_read = 1'd0; -reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; wire main_litedramcore_wants_refresh; wire main_litedramcore_wants_zqcs; wire main_litedramcore_timer_wait; wire main_litedramcore_timer_done0; wire [9:0] main_litedramcore_timer_count0; wire main_litedramcore_timer_done1; -reg [9:0] main_litedramcore_timer_count1 = 10'd781; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; wire main_litedramcore_postponer_req_i; -reg main_litedramcore_postponer_req_o = 1'd0; -reg main_litedramcore_postponer_count = 1'd0; -reg main_litedramcore_sequencer_start0 = 1'd0; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; wire main_litedramcore_sequencer_done0; wire main_litedramcore_sequencer_start1; -reg main_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] main_litedramcore_sequencer_counter = 6'd0; -reg main_litedramcore_sequencer_count = 1'd0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; wire main_litedramcore_zqcs_timer_wait; wire main_litedramcore_zqcs_timer_done0; wire [26:0] main_litedramcore_zqcs_timer_count0; wire main_litedramcore_zqcs_timer_done1; -reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg main_litedramcore_zqcs_executer_start = 1'd0; -reg main_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; wire main_litedramcore_bankmachine0_req_valid; wire main_litedramcore_bankmachine0_req_ready; wire main_litedramcore_bankmachine0_req_we; wire [20:0] main_litedramcore_bankmachine0_req_addr; wire main_litedramcore_bankmachine0_req_lock; -reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine0_refresh_req; -reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; -reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; @@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; @@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; -reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; wire main_litedramcore_bankmachine0_row_hit; -reg main_litedramcore_bankmachine0_row_open = 1'd0; -reg main_litedramcore_bankmachine0_row_close = 1'd0; -reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; wire main_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; wire main_litedramcore_bankmachine1_req_valid; wire main_litedramcore_bankmachine1_req_ready; wire main_litedramcore_bankmachine1_req_we; wire [20:0] main_litedramcore_bankmachine1_req_addr; wire main_litedramcore_bankmachine1_req_lock; -reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine1_refresh_req; -reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; -reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; @@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; @@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; -reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; wire main_litedramcore_bankmachine1_row_hit; -reg main_litedramcore_bankmachine1_row_open = 1'd0; -reg main_litedramcore_bankmachine1_row_close = 1'd0; -reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; wire main_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; wire main_litedramcore_bankmachine2_req_valid; wire main_litedramcore_bankmachine2_req_ready; wire main_litedramcore_bankmachine2_req_we; wire [20:0] main_litedramcore_bankmachine2_req_addr; wire main_litedramcore_bankmachine2_req_lock; -reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine2_refresh_req; -reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; -reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; @@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; @@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; -reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; wire main_litedramcore_bankmachine2_row_hit; -reg main_litedramcore_bankmachine2_row_open = 1'd0; -reg main_litedramcore_bankmachine2_row_close = 1'd0; -reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; wire main_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; wire main_litedramcore_bankmachine3_req_valid; wire main_litedramcore_bankmachine3_req_ready; wire main_litedramcore_bankmachine3_req_we; wire [20:0] main_litedramcore_bankmachine3_req_addr; wire main_litedramcore_bankmachine3_req_lock; -reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine3_refresh_req; -reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; -reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; @@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; @@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; -reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; wire main_litedramcore_bankmachine3_row_hit; -reg main_litedramcore_bankmachine3_row_open = 1'd0; -reg main_litedramcore_bankmachine3_row_close = 1'd0; -reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; wire main_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; wire main_litedramcore_bankmachine4_req_valid; wire main_litedramcore_bankmachine4_req_ready; wire main_litedramcore_bankmachine4_req_we; wire [20:0] main_litedramcore_bankmachine4_req_addr; wire main_litedramcore_bankmachine4_req_lock; -reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine4_refresh_req; -reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; -reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; @@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; @@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; -reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; wire main_litedramcore_bankmachine4_row_hit; -reg main_litedramcore_bankmachine4_row_open = 1'd0; -reg main_litedramcore_bankmachine4_row_close = 1'd0; -reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; wire main_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; wire main_litedramcore_bankmachine5_req_valid; wire main_litedramcore_bankmachine5_req_ready; wire main_litedramcore_bankmachine5_req_we; wire [20:0] main_litedramcore_bankmachine5_req_addr; wire main_litedramcore_bankmachine5_req_lock; -reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine5_refresh_req; -reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; -reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; @@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; @@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; -reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; wire main_litedramcore_bankmachine5_row_hit; -reg main_litedramcore_bankmachine5_row_open = 1'd0; -reg main_litedramcore_bankmachine5_row_close = 1'd0; -reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; wire main_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; wire main_litedramcore_bankmachine6_req_valid; wire main_litedramcore_bankmachine6_req_ready; wire main_litedramcore_bankmachine6_req_we; wire [20:0] main_litedramcore_bankmachine6_req_addr; wire main_litedramcore_bankmachine6_req_lock; -reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine6_refresh_req; -reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; -reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; @@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; @@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; -reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; wire main_litedramcore_bankmachine6_row_hit; -reg main_litedramcore_bankmachine6_row_open = 1'd0; -reg main_litedramcore_bankmachine6_row_close = 1'd0; -reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; wire main_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; wire main_litedramcore_bankmachine7_req_valid; wire main_litedramcore_bankmachine7_req_ready; wire main_litedramcore_bankmachine7_req_we; wire [20:0] main_litedramcore_bankmachine7_req_addr; wire main_litedramcore_bankmachine7_req_lock; -reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine7_refresh_req; -reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; -reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; @@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; @@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; -reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; wire main_litedramcore_bankmachine7_row_hit; -reg main_litedramcore_bankmachine7_row_open = 1'd0; -reg main_litedramcore_bankmachine7_row_close = 1'd0; -reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; wire main_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; wire main_litedramcore_ras_allowed; wire main_litedramcore_cas_allowed; wire [1:0] main_litedramcore_rdcmdphase; wire [1:0] main_litedramcore_wrcmdphase; -reg main_litedramcore_choose_cmd_want_reads = 1'd0; -reg main_litedramcore_choose_cmd_want_writes = 1'd0; -reg main_litedramcore_choose_cmd_want_cmds = 1'd0; -reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; wire main_litedramcore_choose_cmd_cmd_valid; -reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; -reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; wire main_litedramcore_choose_cmd_cmd_payload_is_read; wire main_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; wire [7:0] main_litedramcore_choose_cmd_request; -reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; wire main_litedramcore_choose_cmd_ce; -reg main_litedramcore_choose_req_want_reads = 1'd0; -reg main_litedramcore_choose_req_want_writes = 1'd0; -reg main_litedramcore_choose_req_want_cmds = 1'd0; -reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; wire main_litedramcore_choose_req_cmd_valid; -reg main_litedramcore_choose_req_cmd_ready = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; wire [13:0] main_litedramcore_choose_req_cmd_payload_a; wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; -reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; wire main_litedramcore_choose_req_cmd_payload_is_cmd; wire main_litedramcore_choose_req_cmd_payload_is_read; wire main_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; wire [7:0] main_litedramcore_choose_req_request; -reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; wire main_litedramcore_choose_req_ce; -reg [13:0] main_litedramcore_nop_a = 14'd0; -reg [2:0] main_litedramcore_nop_ba = 3'd0; -reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; -reg main_litedramcore_steerer0 = 1'd1; -reg main_litedramcore_steerer1 = 1'd1; -reg main_litedramcore_steerer2 = 1'd1; -reg main_litedramcore_steerer3 = 1'd1; -reg main_litedramcore_steerer4 = 1'd1; -reg main_litedramcore_steerer5 = 1'd1; -reg main_litedramcore_steerer6 = 1'd1; -reg main_litedramcore_steerer7 = 1'd1; +reg [13:0] main_litedramcore_nop_a = 14'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; wire main_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; -reg main_litedramcore_trrdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; wire main_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; wire [2:0] main_litedramcore_tfawcon_count; -reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; wire main_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; -reg main_litedramcore_tccdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; wire main_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; wire main_litedramcore_read_available; wire main_litedramcore_write_available; -reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en0 = 1'd0; wire main_litedramcore_max_time0; -reg [4:0] main_litedramcore_time0 = 5'd0; -reg main_litedramcore_en1 = 1'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; wire main_litedramcore_max_time1; -reg [3:0] main_litedramcore_time1 = 4'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; wire main_litedramcore_go_to_refresh; -reg main_init_done_storage = 1'd0; -reg main_init_done_re = 1'd0; -reg main_init_error_storage = 1'd0; -reg main_init_error_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; wire [29:0] main_wb_bus_adr; wire [31:0] main_wb_bus_dat_w; wire [31:0] main_wb_bus_dat_r; @@ -1570,6 +1592,7 @@ wire main_wb_bus_we; wire [2:0] main_wb_bus_cti; wire [1:0] main_wb_bus_bte; wire main_wb_bus_err; +wire main_user_enable; wire main_user_port_cmd_valid; wire main_user_port_cmd_ready; wire main_user_port_cmd_payload_we; @@ -1590,26 +1613,26 @@ wire builder_reset5; wire builder_reset6; wire builder_reset7; wire builder_pll_fb; -reg [1:0] builder_refresher_state = 2'd0; -reg [1:0] builder_refresher_next_state = 2'd0; -reg [3:0] builder_bankmachine0_state = 4'd0; -reg [3:0] builder_bankmachine0_next_state = 4'd0; -reg [3:0] builder_bankmachine1_state = 4'd0; -reg [3:0] builder_bankmachine1_next_state = 4'd0; -reg [3:0] builder_bankmachine2_state = 4'd0; -reg [3:0] builder_bankmachine2_next_state = 4'd0; -reg [3:0] builder_bankmachine3_state = 4'd0; -reg [3:0] builder_bankmachine3_next_state = 4'd0; -reg [3:0] builder_bankmachine4_state = 4'd0; -reg [3:0] builder_bankmachine4_next_state = 4'd0; -reg [3:0] builder_bankmachine5_state = 4'd0; -reg [3:0] builder_bankmachine5_next_state = 4'd0; -reg [3:0] builder_bankmachine6_state = 4'd0; -reg [3:0] builder_bankmachine6_next_state = 4'd0; -reg [3:0] builder_bankmachine7_state = 4'd0; -reg [3:0] builder_bankmachine7_next_state = 4'd0; -reg [3:0] builder_multiplexer_state = 4'd0; -reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; wire builder_roundrobin0_request; wire builder_roundrobin0_grant; wire builder_roundrobin0_ce; @@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce; wire builder_roundrobin7_request; wire builder_roundrobin7_grant; wire builder_roundrobin7_ce; -reg builder_locked0 = 1'd0; -reg builder_locked1 = 1'd0; -reg builder_locked2 = 1'd0; -reg builder_locked3 = 1'd0; -reg builder_locked4 = 1'd0; -reg builder_locked5 = 1'd0; -reg builder_locked6 = 1'd0; -reg builder_locked7 = 1'd0; -reg builder_new_master_wdata_ready0 = 1'd0; -reg builder_new_master_wdata_ready1 = 1'd0; -reg builder_new_master_rdata_valid0 = 1'd0; -reg builder_new_master_rdata_valid1 = 1'd0; -reg builder_new_master_rdata_valid2 = 1'd0; -reg builder_new_master_rdata_valid3 = 1'd0; -reg builder_new_master_rdata_valid4 = 1'd0; -reg builder_new_master_rdata_valid5 = 1'd0; -reg builder_new_master_rdata_valid6 = 1'd0; -reg builder_new_master_rdata_valid7 = 1'd0; -reg builder_new_master_rdata_valid8 = 1'd0; -reg [13:0] builder_litedramcore_adr = 14'd0; -reg builder_litedramcore_we = 1'd0; -reg [7:0] builder_litedramcore_dat_w = 8'd0; -wire [7:0] builder_litedramcore_dat_r; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [31:0] builder_litedramcore_dat_w = 32'd0; +wire [31:0] builder_litedramcore_dat_r; wire [29:0] builder_litedramcore_wishbone_adr; wire [31:0] builder_litedramcore_wishbone_dat_w; -reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; wire [3:0] builder_litedramcore_wishbone_sel; wire builder_litedramcore_wishbone_cyc; wire builder_litedramcore_wishbone_stb; -reg builder_litedramcore_wishbone_ack = 1'd0; +reg builder_litedramcore_wishbone_ack = 1'd0; wire builder_litedramcore_wishbone_we; wire [2:0] builder_litedramcore_wishbone_cti; wire [1:0] builder_litedramcore_wishbone_bte; -reg builder_litedramcore_wishbone_err = 1'd0; +reg builder_litedramcore_wishbone_err = 1'd0; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; -wire [7:0] builder_interface0_bank_bus_dat_w; -reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; -reg builder_csrbank0_init_done0_re = 1'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +reg builder_csrbank0_init_done0_re = 1'd0; wire builder_csrbank0_init_done0_r; -reg builder_csrbank0_init_done0_we = 1'd0; +reg builder_csrbank0_init_done0_we = 1'd0; wire builder_csrbank0_init_done0_w; -reg builder_csrbank0_init_error0_re = 1'd0; +reg builder_csrbank0_init_error0_re = 1'd0; wire builder_csrbank0_init_error0_r; -reg builder_csrbank0_init_error0_we = 1'd0; +reg builder_csrbank0_init_error0_we = 1'd0; wire builder_csrbank0_init_error0_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; -wire [7:0] builder_interface1_bank_bus_dat_w; -reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; -reg builder_csrbank1_rst0_re = 1'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +reg builder_csrbank1_rst0_re = 1'd0; wire builder_csrbank1_rst0_r; -reg builder_csrbank1_rst0_we = 1'd0; +reg builder_csrbank1_rst0_we = 1'd0; wire builder_csrbank1_rst0_w; -reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_r; -reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_w; -reg builder_csrbank1_wlevel_en0_re = 1'd0; +reg builder_csrbank1_wlevel_en0_re = 1'd0; wire builder_csrbank1_wlevel_en0_r; -reg builder_csrbank1_wlevel_en0_we = 1'd0; +reg builder_csrbank1_wlevel_en0_we = 1'd0; wire builder_csrbank1_wlevel_en0_w; -reg builder_csrbank1_dly_sel0_re = 1'd0; +reg builder_csrbank1_dly_sel0_re = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_r; -reg builder_csrbank1_dly_sel0_we = 1'd0; +reg builder_csrbank1_dly_sel0_we = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_w; -reg builder_csrbank1_rdphase0_re = 1'd0; +reg builder_csrbank1_rdphase0_re = 1'd0; wire [1:0] builder_csrbank1_rdphase0_r; -reg builder_csrbank1_rdphase0_we = 1'd0; +reg builder_csrbank1_rdphase0_we = 1'd0; wire [1:0] builder_csrbank1_rdphase0_w; -reg builder_csrbank1_wrphase0_re = 1'd0; +reg builder_csrbank1_wrphase0_re = 1'd0; wire [1:0] builder_csrbank1_wrphase0_r; -reg builder_csrbank1_wrphase0_we = 1'd0; +reg builder_csrbank1_wrphase0_we = 1'd0; wire [1:0] builder_csrbank1_wrphase0_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; -wire [7:0] builder_interface2_bank_bus_dat_w; -reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; -reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_r; -reg builder_csrbank2_dfii_control0_we = 1'd0; +reg builder_csrbank2_dfii_control0_we = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_w; -reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_r; -reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_w; -reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi0_address1_r; -reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi0_address1_w; -reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_r; -reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_w; -reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; -reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; -reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; -reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; -reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; -reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; -reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; -reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; -reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; -reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; -reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; -reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; -reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; -reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; -reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; -reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; -reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; -reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; -reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_r; -reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_w; -reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi1_address1_r; -reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi1_address1_w; -reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_r; -reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_w; -reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; -reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; -reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; -reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; -reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; -reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; -reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; -reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; -reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; -reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; -reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; -reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; -reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; -reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; -reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; -reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; -reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; -reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; -reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_r; -reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_w; -reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi2_address1_r; -reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi2_address1_w; -reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_r; -reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_w; -reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; -reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; -reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; -reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; -reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; -reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; -reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; -reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; -reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; -reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; -reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; -reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; -reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; -reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; -reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; -reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; -reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; -reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; -reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_r; -reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_w; -reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi3_address1_r; -reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi3_address1_w; -reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_r; -reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_w; -reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; -reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; -reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; -reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; -reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; -reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; -reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; -reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; -reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; -reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; -reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; -reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; -reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; -reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; -reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; -reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; -reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; -reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; wire builder_csrbank2_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; -wire [7:0] builder_csr_interconnect_dat_w; -wire [7:0] builder_csr_interconnect_dat_r; -reg [1:0] builder_state = 2'd0; -reg [1:0] builder_next_state = 2'd0; -reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; -reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; -reg builder_litedramcore_adr_next_value_ce1 = 1'd0; -reg builder_litedramcore_we_next_value2 = 1'd0; -reg builder_litedramcore_we_next_value_ce2 = 1'd0; -reg builder_rhs_array_muxed0 = 1'd0; -reg [13:0] builder_rhs_array_muxed1 = 14'd0; -reg [2:0] builder_rhs_array_muxed2 = 3'd0; -reg builder_rhs_array_muxed3 = 1'd0; -reg builder_rhs_array_muxed4 = 1'd0; -reg builder_rhs_array_muxed5 = 1'd0; -reg builder_t_array_muxed0 = 1'd0; -reg builder_t_array_muxed1 = 1'd0; -reg builder_t_array_muxed2 = 1'd0; -reg builder_rhs_array_muxed6 = 1'd0; -reg [13:0] builder_rhs_array_muxed7 = 14'd0; -reg [2:0] builder_rhs_array_muxed8 = 3'd0; -reg builder_rhs_array_muxed9 = 1'd0; -reg builder_rhs_array_muxed10 = 1'd0; -reg builder_rhs_array_muxed11 = 1'd0; -reg builder_t_array_muxed3 = 1'd0; -reg builder_t_array_muxed4 = 1'd0; -reg builder_t_array_muxed5 = 1'd0; -reg [20:0] builder_rhs_array_muxed12 = 21'd0; -reg builder_rhs_array_muxed13 = 1'd0; -reg builder_rhs_array_muxed14 = 1'd0; -reg [20:0] builder_rhs_array_muxed15 = 21'd0; -reg builder_rhs_array_muxed16 = 1'd0; -reg builder_rhs_array_muxed17 = 1'd0; -reg [20:0] builder_rhs_array_muxed18 = 21'd0; -reg builder_rhs_array_muxed19 = 1'd0; -reg builder_rhs_array_muxed20 = 1'd0; -reg [20:0] builder_rhs_array_muxed21 = 21'd0; -reg builder_rhs_array_muxed22 = 1'd0; -reg builder_rhs_array_muxed23 = 1'd0; -reg [20:0] builder_rhs_array_muxed24 = 21'd0; -reg builder_rhs_array_muxed25 = 1'd0; -reg builder_rhs_array_muxed26 = 1'd0; -reg [20:0] builder_rhs_array_muxed27 = 21'd0; -reg builder_rhs_array_muxed28 = 1'd0; -reg builder_rhs_array_muxed29 = 1'd0; -reg [20:0] builder_rhs_array_muxed30 = 21'd0; -reg builder_rhs_array_muxed31 = 1'd0; -reg builder_rhs_array_muxed32 = 1'd0; -reg [20:0] builder_rhs_array_muxed33 = 21'd0; -reg builder_rhs_array_muxed34 = 1'd0; -reg builder_rhs_array_muxed35 = 1'd0; -reg [2:0] builder_array_muxed0 = 3'd0; -reg [13:0] builder_array_muxed1 = 14'd0; -reg builder_array_muxed2 = 1'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg builder_array_muxed6 = 1'd0; -reg [2:0] builder_array_muxed7 = 3'd0; -reg [13:0] builder_array_muxed8 = 14'd0; -reg builder_array_muxed9 = 1'd0; -reg builder_array_muxed10 = 1'd0; -reg builder_array_muxed11 = 1'd0; -reg builder_array_muxed12 = 1'd0; -reg builder_array_muxed13 = 1'd0; -reg [2:0] builder_array_muxed14 = 3'd0; -reg [13:0] builder_array_muxed15 = 14'd0; -reg builder_array_muxed16 = 1'd0; -reg builder_array_muxed17 = 1'd0; -reg builder_array_muxed18 = 1'd0; -reg builder_array_muxed19 = 1'd0; -reg builder_array_muxed20 = 1'd0; -reg [2:0] builder_array_muxed21 = 3'd0; -reg [13:0] builder_array_muxed22 = 14'd0; -reg builder_array_muxed23 = 1'd0; -reg builder_array_muxed24 = 1'd0; -reg builder_array_muxed25 = 1'd0; -reg builder_array_muxed26 = 1'd0; -reg builder_array_muxed27 = 1'd0; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [13:0] builder_rhs_array_muxed1 = 14'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [13:0] builder_rhs_array_muxed7 = 14'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [20:0] builder_rhs_array_muxed12 = 21'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [20:0] builder_rhs_array_muxed15 = 21'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [20:0] builder_rhs_array_muxed18 = 21'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [20:0] builder_rhs_array_muxed21 = 21'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [20:0] builder_rhs_array_muxed24 = 21'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [20:0] builder_rhs_array_muxed27 = 21'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [20:0] builder_rhs_array_muxed30 = 21'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [20:0] builder_rhs_array_muxed33 = 21'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [13:0] builder_array_muxed1 = 14'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [13:0] builder_array_muxed8 = 14'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [13:0] builder_array_muxed15 = 14'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [13:0] builder_array_muxed22 = 14'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl1; @@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl3_expr; -// synthesis translate_off -reg dummy_s; -initial dummy_s <= 1'd0; -// synthesis translate_on +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + assign init_done = main_init_done_storage; assign init_error = main_init_error_storage; assign main_wb_bus_adr = wb_ctrl_adr; @@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; -assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; -assign main_reset = rst; +assign main_reset = (rst | main_rst); assign pll_locked = main_locked; assign main_clkin = clk; assign iodelay_clk = main_clkout_buf0; @@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2; assign sys4x_dqs_clk = main_clkout_buf3; assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); - -// synthesis translate_off -reg dummy_d; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p0_rddata <= 32'd0; main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; @@ -2081,14 +1989,7 @@ always @(*) begin main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; -// synthesis translate_off - dummy_d = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_1; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p1_rddata <= 32'd0; main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; @@ -2123,14 +2024,7 @@ always @(*) begin main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; -// synthesis translate_off - dummy_d_1 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_2; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p2_rddata <= 32'd0; main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; @@ -2165,14 +2059,7 @@ always @(*) begin main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; -// synthesis translate_off - dummy_d_2 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_3; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p3_rddata <= 32'd0; main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; @@ -2207,19 +2094,12 @@ always @(*) begin main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; -// synthesis translate_off - dummy_d_3 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; - -// synthesis translate_off -reg dummy_d_4; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqs_oe <= 1'd0; if (main_a7ddrphy_wlevel_en_storage) begin @@ -2227,16 +2107,9 @@ always @(*) begin end else begin main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; end -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqspattern_o0 <= 8'd0; main_a7ddrphy_dqspattern_o0 <= 7'd85; @@ -2252,14 +2125,7 @@ always @(*) begin main_a7ddrphy_dqspattern_o0 <= 1'd1; end end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip00 <= 8'd0; case (main_a7ddrphy_bitslip0_value0) @@ -2288,14 +2154,7 @@ always @(*) begin main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip10 <= 8'd0; case (main_a7ddrphy_bitslip1_value0) @@ -2324,14 +2183,7 @@ always @(*) begin main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip01 <= 8'd0; case (main_a7ddrphy_bitslip0_value1) @@ -2360,14 +2212,7 @@ always @(*) begin main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip11 <= 8'd0; case (main_a7ddrphy_bitslip1_value1) @@ -2396,14 +2241,7 @@ always @(*) begin main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip02 <= 8'd0; case (main_a7ddrphy_bitslip0_value2) @@ -2432,14 +2270,7 @@ always @(*) begin main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip04 <= 8'd0; case (main_a7ddrphy_bitslip0_value3) @@ -2468,14 +2299,7 @@ always @(*) begin main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip12 <= 8'd0; case (main_a7ddrphy_bitslip1_value2) @@ -2504,14 +2328,7 @@ always @(*) begin main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip14 <= 8'd0; case (main_a7ddrphy_bitslip1_value3) @@ -2540,14 +2357,7 @@ always @(*) begin main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip20 <= 8'd0; case (main_a7ddrphy_bitslip2_value0) @@ -2576,14 +2386,7 @@ always @(*) begin main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip22 <= 8'd0; case (main_a7ddrphy_bitslip2_value1) @@ -2612,14 +2415,7 @@ always @(*) begin main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip30 <= 8'd0; case (main_a7ddrphy_bitslip3_value0) @@ -2648,14 +2444,7 @@ always @(*) begin main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip32 <= 8'd0; case (main_a7ddrphy_bitslip3_value1) @@ -2684,14 +2473,7 @@ always @(*) begin main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_18; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip40 <= 8'd0; case (main_a7ddrphy_bitslip4_value0) @@ -2720,14 +2502,7 @@ always @(*) begin main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_18 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_19; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip42 <= 8'd0; case (main_a7ddrphy_bitslip4_value1) @@ -2756,14 +2531,7 @@ always @(*) begin main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_19 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_20; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip50 <= 8'd0; case (main_a7ddrphy_bitslip5_value0) @@ -2792,14 +2560,7 @@ always @(*) begin main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_20 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_21; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip52 <= 8'd0; case (main_a7ddrphy_bitslip5_value1) @@ -2828,14 +2589,7 @@ always @(*) begin main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_21 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip60 <= 8'd0; case (main_a7ddrphy_bitslip6_value0) @@ -2864,14 +2618,7 @@ always @(*) begin main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip62 <= 8'd0; case (main_a7ddrphy_bitslip6_value1) @@ -2900,14 +2647,7 @@ always @(*) begin main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip70 <= 8'd0; case (main_a7ddrphy_bitslip7_value0) @@ -2936,14 +2676,7 @@ always @(*) begin main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip72 <= 8'd0; case (main_a7ddrphy_bitslip7_value1) @@ -2972,14 +2705,7 @@ always @(*) begin main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_26; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip80 <= 8'd0; case (main_a7ddrphy_bitslip8_value0) @@ -3008,14 +2734,7 @@ always @(*) begin main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip82 <= 8'd0; case (main_a7ddrphy_bitslip8_value1) @@ -3044,14 +2763,7 @@ always @(*) begin main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip90 <= 8'd0; case (main_a7ddrphy_bitslip9_value0) @@ -3080,14 +2792,7 @@ always @(*) begin main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip92 <= 8'd0; case (main_a7ddrphy_bitslip9_value1) @@ -3116,14 +2821,7 @@ always @(*) begin main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip100 <= 8'd0; case (main_a7ddrphy_bitslip10_value0) @@ -3152,14 +2850,7 @@ always @(*) begin main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_30 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_31; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip102 <= 8'd0; case (main_a7ddrphy_bitslip10_value1) @@ -3188,14 +2879,7 @@ always @(*) begin main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_31 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_32; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip110 <= 8'd0; case (main_a7ddrphy_bitslip11_value0) @@ -3224,14 +2908,7 @@ always @(*) begin main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_32 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_33; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip112 <= 8'd0; case (main_a7ddrphy_bitslip11_value1) @@ -3260,14 +2937,7 @@ always @(*) begin main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_33 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_34; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip120 <= 8'd0; case (main_a7ddrphy_bitslip12_value0) @@ -3296,14 +2966,7 @@ always @(*) begin main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_34 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_35; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip122 <= 8'd0; case (main_a7ddrphy_bitslip12_value1) @@ -3332,14 +2995,7 @@ always @(*) begin main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_35 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_36; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip130 <= 8'd0; case (main_a7ddrphy_bitslip13_value0) @@ -3368,14 +3024,7 @@ always @(*) begin main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_36 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_37; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip132 <= 8'd0; case (main_a7ddrphy_bitslip13_value1) @@ -3404,14 +3053,7 @@ always @(*) begin main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_37 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_38; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip140 <= 8'd0; case (main_a7ddrphy_bitslip14_value0) @@ -3440,14 +3082,7 @@ always @(*) begin main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip142 <= 8'd0; case (main_a7ddrphy_bitslip14_value1) @@ -3476,14 +3111,7 @@ always @(*) begin main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_39 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_40; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip150 <= 8'd0; case (main_a7ddrphy_bitslip15_value0) @@ -3512,14 +3140,7 @@ always @(*) begin main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_40 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_41; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip152 <= 8'd0; case (main_a7ddrphy_bitslip15_value1) @@ -3548,9 +3169,6 @@ always @(*) begin main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_41 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; @@ -3680,10 +3298,14 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_ assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; - -// synthesis translate_off -reg dummy_d_42; -// synthesis translate_on +always @(*) begin + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; + end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; + end +end always @(*) begin main_litedramcore_master_p0_address <= 14'd0; if (main_litedramcore_sel) begin @@ -3691,14 +3313,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end -// synthesis translate_off - dummy_d_42 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_43; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -3706,14 +3321,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end -// synthesis translate_off - dummy_d_43 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_44; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3721,14 +3329,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end -// synthesis translate_off - dummy_d_44 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_45; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3736,14 +3337,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end -// synthesis translate_off - dummy_d_45 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_46; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3751,28 +3345,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end -// synthesis translate_off - dummy_d_46 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_47; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end -// synthesis translate_off - dummy_d_47 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_48; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3780,28 +3360,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end -// synthesis translate_off - dummy_d_48 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_49; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_49 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_50; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -3809,14 +3375,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end -// synthesis translate_off - dummy_d_50 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_51; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -3824,14 +3383,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end -// synthesis translate_off - dummy_d_51 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_52; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -3839,14 +3391,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end -// synthesis translate_off - dummy_d_52 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_53; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3854,14 +3399,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end -// synthesis translate_off - dummy_d_53 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_54; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -3869,28 +3407,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end -// synthesis translate_off - dummy_d_54 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_55; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end -// synthesis translate_off - dummy_d_55 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_56; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3898,28 +3422,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end -// synthesis translate_off - dummy_d_56 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_57; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end -// synthesis translate_off - dummy_d_57 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_58; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -3927,14 +3437,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end -// synthesis translate_off - dummy_d_58 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_59; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3942,14 +3445,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end -// synthesis translate_off - dummy_d_59 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_60; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_address <= 14'd0; if (main_litedramcore_sel) begin @@ -3957,14 +3453,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end -// synthesis translate_off - dummy_d_60 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_61; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -3972,14 +3461,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end -// synthesis translate_off - dummy_d_61 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_62; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3987,14 +3469,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end -// synthesis translate_off - dummy_d_62 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_63; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4002,14 +3477,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end -// synthesis translate_off - dummy_d_63 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_64; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4017,28 +3485,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end -// synthesis translate_off - dummy_d_64 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_65; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end -// synthesis translate_off - dummy_d_65 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_66; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4046,28 +3500,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end -// synthesis translate_off - dummy_d_66 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_67; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_67 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_68; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4075,14 +3515,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end -// synthesis translate_off - dummy_d_68 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_69; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4090,14 +3523,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end -// synthesis translate_off - dummy_d_69 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_70; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4105,14 +3531,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end -// synthesis translate_off - dummy_d_70 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_71; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4120,14 +3539,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end -// synthesis translate_off - dummy_d_71 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_72; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4135,28 +3547,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end -// synthesis translate_off - dummy_d_72 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_73; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end -// synthesis translate_off - dummy_d_73 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_74; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4164,28 +3562,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end -// synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end -// synthesis translate_off - dummy_d_75 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_76; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4193,14 +3577,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end -// synthesis translate_off - dummy_d_76 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_77; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4208,14 +3585,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end -// synthesis translate_off - dummy_d_77 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_78; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_address <= 14'd0; if (main_litedramcore_sel) begin @@ -4223,14 +3593,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end -// synthesis translate_off - dummy_d_78 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_79; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4238,14 +3601,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end -// synthesis translate_off - dummy_d_79 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_80; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4253,14 +3609,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end -// synthesis translate_off - dummy_d_80 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_81; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4268,14 +3617,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end -// synthesis translate_off - dummy_d_81 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_82; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4283,28 +3625,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_82 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_83; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end -// synthesis translate_off - dummy_d_83 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_84; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4312,28 +3640,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end -// synthesis translate_off - dummy_d_84 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_85; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_85 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_86; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4341,28 +3655,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end -// synthesis translate_off - dummy_d_86 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_87; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p0_rddata <= 32'd0; - if (main_litedramcore_sel) begin - end else begin - main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; - end -// synthesis translate_off - dummy_d_87 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_88; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4370,14 +3663,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end -// synthesis translate_off - dummy_d_88 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_89; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4385,14 +3671,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end -// synthesis translate_off - dummy_d_89 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_90; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4400,14 +3679,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end -// synthesis translate_off - dummy_d_90 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_91; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4415,28 +3687,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end -// synthesis translate_off - dummy_d_91 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_92; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end -// synthesis translate_off - dummy_d_92 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_93; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4444,28 +3702,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end -// synthesis translate_off - dummy_d_93 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_94; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p0_rddata_valid <= 1'd0; + main_litedramcore_inti_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin - main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end -// synthesis translate_off - dummy_d_94 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_95; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4473,28 +3717,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end -// synthesis translate_off - dummy_d_95 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_96; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_rddata_valid <= 1'd0; + main_litedramcore_inti_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin - main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; + main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4502,14 +3732,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end -// synthesis translate_off - dummy_d_97 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_98; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_address <= 14'd0; if (main_litedramcore_sel) begin @@ -4517,14 +3740,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end -// synthesis translate_off - dummy_d_98 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_99; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4532,14 +3748,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end -// synthesis translate_off - dummy_d_99 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_100; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + end +end always @(*) begin main_litedramcore_master_p3_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4547,14 +3763,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end -// synthesis translate_off - dummy_d_100 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_101; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4562,14 +3771,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end -// synthesis translate_off - dummy_d_101 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_102; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4577,28 +3779,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end -// synthesis translate_off - dummy_d_102 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_103; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end -// synthesis translate_off - dummy_d_103 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_104; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4606,28 +3794,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end -// synthesis translate_off - dummy_d_104 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_105; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_105 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_106; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4635,14 +3809,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end -// synthesis translate_off - dummy_d_106 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_107; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4650,14 +3817,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end -// synthesis translate_off - dummy_d_107 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_108; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4665,14 +3825,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end -// synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4680,14 +3833,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end -// synthesis translate_off - dummy_d_109 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_110; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4695,14 +3841,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end -// synthesis translate_off - dummy_d_110 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_111; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4710,14 +3849,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end -// synthesis translate_off - dummy_d_111 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_112; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4725,24 +3857,6 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end -// synthesis translate_off - dummy_d_112 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_113; -// synthesis translate_on -always @(*) begin - main_litedramcore_master_p3_rddata_en <= 1'd0; - if (main_litedramcore_sel) begin - main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; - end else begin - main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; - end -// synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; @@ -4756,10 +3870,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + end else begin + main_litedramcore_inti_p0_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p0_cas_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4767,14 +3885,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_114 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_115; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_cs_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4782,14 +3893,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_115 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_116; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_ras_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4797,24 +3901,6 @@ always @(*) begin end else begin main_litedramcore_inti_p0_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_116 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_117; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p0_we_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); - end else begin - main_litedramcore_inti_p0_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_117 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; @@ -4822,10 +3908,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_118; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); + end else begin + main_litedramcore_inti_p1_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p1_cas_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4833,14 +3923,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_118 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_119; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_cs_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4848,14 +3931,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_ras_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4863,24 +3939,6 @@ always @(*) begin end else begin main_litedramcore_inti_p1_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p1_we_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); - end else begin - main_litedramcore_inti_p1_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; @@ -4888,10 +3946,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); + end else begin + main_litedramcore_inti_p2_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4899,14 +3961,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_cs_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4914,14 +3969,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_ras_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4929,24 +3977,6 @@ always @(*) begin end else begin main_litedramcore_inti_p2_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_124 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_125; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p2_we_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); - end else begin - main_litedramcore_inti_p2_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_125 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; @@ -4954,10 +3984,14 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_126; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + end else begin + main_litedramcore_inti_p3_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p3_cas_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4965,14 +3999,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_cs_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4980,14 +4007,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_ras_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4995,24 +4015,6 @@ always @(*) begin end else begin main_litedramcore_inti_p3_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p3_we_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); - end else begin - main_litedramcore_inti_p3_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; @@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on always @(*) begin builder_refresher_next_state <= 2'd0; builder_refresher_next_state <= builder_refresher_state; @@ -5124,119 +4122,88 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_130 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_131; -// synthesis translate_on always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; + main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase -// synthesis translate_off - dummy_d_131 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_132; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) 1'd1: begin - main_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_sequencer_done0) begin - if (main_litedramcore_wants_zqcs) begin - end else begin - main_litedramcore_cmd_valid <= 1'd0; - end + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; end end + 2'd2: begin + end 2'd3: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase -// synthesis translate_off - dummy_d_132 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_133; -// synthesis translate_on always @(*) begin - main_litedramcore_zqcs_executer_start <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin - main_litedramcore_zqcs_executer_start <= 1'd1; end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase -// synthesis translate_off - dummy_d_133 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_134; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_last <= 1'd0; + main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) 1'd1: begin end 2'd2: begin if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase -// synthesis translate_off - dummy_d_134 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; @@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_135; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin @@ -5263,17 +4226,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_135 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_136; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin @@ -5281,9 +4237,6 @@ always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_136 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; @@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_137; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin @@ -5313,9 +4262,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); @@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on always @(*) begin builder_bankmachine0_next_state <= 4'd0; builder_bankmachine0_next_state <= builder_bankmachine0_state; @@ -5389,14 +4331,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_138 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_139; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) @@ -5422,14 +4398,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_close <= 1'd0; case (builder_bankmachine0_state) @@ -5455,14 +4424,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_140 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_141; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (builder_bankmachine0_state) @@ -5497,14 +4459,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_141 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_142; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (builder_bankmachine0_state) @@ -5533,14 +4488,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_142 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_143; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (builder_bankmachine0_state) @@ -5581,14 +4529,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_143 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_144; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine0_state) @@ -5614,14 +4555,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine0_state) @@ -5651,14 +4585,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_145 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_146; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (builder_bankmachine0_state) @@ -5696,16 +4623,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_146 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_147; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5730,8 +4650,8 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5741,16 +4661,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5775,7 +4688,7 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin end end else begin @@ -5786,16 +4699,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_148 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_149; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5820,8 +4726,8 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5831,14 +4737,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_149 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_150; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (builder_bankmachine0_state) @@ -5864,57 +4763,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_150 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_151; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_151 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; @@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_152; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin @@ -5941,17 +4785,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin @@ -5959,9 +4796,6 @@ always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; @@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin @@ -5991,9 +4821,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); @@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on always @(*) begin builder_bankmachine1_next_state <= 4'd0; builder_bankmachine1_next_state <= builder_bankmachine1_state; @@ -6067,14 +4890,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_155 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_156; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine1_row_open <= 1'd0; case (builder_bankmachine1_state) @@ -6100,14 +4957,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_156 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_157; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_close <= 1'd0; case (builder_bankmachine1_state) @@ -6133,14 +4983,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (builder_bankmachine1_state) @@ -6175,14 +5018,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_158 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_159; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (builder_bankmachine1_state) @@ -6211,14 +5047,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_159 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_160; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (builder_bankmachine1_state) @@ -6259,14 +5088,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_160 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_161; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) @@ -6292,14 +5114,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine1_state) @@ -6329,47 +5144,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_162 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_163; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_163 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_164; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (builder_bankmachine1_state) @@ -6407,14 +5182,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_164 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_165; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (builder_bankmachine1_state) @@ -6452,14 +5220,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_165 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_166; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (builder_bankmachine1_state) @@ -6497,14 +5258,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_166 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_167; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (builder_bankmachine1_state) @@ -6542,30 +5296,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_167 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_168; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6576,23 +5320,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_168 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; @@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_169; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin @@ -6619,17 +5344,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin @@ -6637,9 +5355,6 @@ always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; @@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin @@ -6669,9 +5380,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); @@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on always @(*) begin builder_bankmachine2_next_state <= 4'd0; builder_bankmachine2_next_state <= builder_bankmachine2_state; @@ -6745,22 +5449,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_172 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_173; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6778,10 +5481,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; - end + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6790,14 +5490,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) @@ -6823,14 +5516,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_174 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_175; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) @@ -6856,14 +5542,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) @@ -6898,14 +5577,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (builder_bankmachine2_state) @@ -6934,14 +5606,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_177 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_178; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) @@ -6982,14 +5647,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_178 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_179; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) @@ -7015,14 +5673,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_179 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_180; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) @@ -7052,14 +5703,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_180 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_181; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) @@ -7097,14 +5741,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_181 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_182; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) @@ -7142,14 +5779,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_182 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_183; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) @@ -7187,16 +5817,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_183 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_184; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -7205,9 +5828,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine2_twtpcon_ready) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7218,32 +5838,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_184 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_185; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7254,23 +5879,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_185 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; @@ -7286,10 +5896,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_186; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin @@ -7297,17 +5903,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin @@ -7315,9 +5914,6 @@ always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; @@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin @@ -7347,9 +5939,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); @@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on always @(*) begin builder_bankmachine3_next_state <= 4'd0; builder_bankmachine3_next_state <= builder_bankmachine3_state; @@ -7423,14 +6008,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_189 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_190; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_row_open <= 1'd0; case (builder_bankmachine3_state) @@ -7456,14 +6075,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_190 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_191; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_close <= 1'd0; case (builder_bankmachine3_state) @@ -7489,14 +6101,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (builder_bankmachine3_state) @@ -7531,14 +6136,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_192 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_193; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (builder_bankmachine3_state) @@ -7567,14 +6165,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_193 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_194; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (builder_bankmachine3_state) @@ -7615,22 +6206,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_194 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_195; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7643,31 +6230,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_195 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_196; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -7697,47 +6262,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_197 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_198; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (builder_bankmachine3_state) @@ -7775,14 +6300,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_198 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_199; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (builder_bankmachine3_state) @@ -7820,14 +6338,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_199 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_200; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (builder_bankmachine3_state) @@ -7865,16 +6376,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_200 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_201; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin end @@ -7883,9 +6387,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine3_twtpcon_ready) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7896,32 +6397,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_201 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_202; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7932,23 +6438,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_202 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; @@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_203; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin @@ -7975,17 +6462,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin @@ -7993,9 +6473,6 @@ always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_204 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; @@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_205; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin @@ -8025,9 +6498,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); @@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on always @(*) begin builder_bankmachine4_next_state <= 4'd0; builder_bankmachine4_next_state <= builder_bankmachine4_state; @@ -8101,24 +6567,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_206 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_207; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_open <= 1'd0; + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_row_open <= 1'd1; + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8132,29 +6594,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_close <= 1'd0; + main_litedramcore_bankmachine4_row_open <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8167,24 +6634,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_208 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_209; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine4_row_close <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8195,7 +6658,30 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine4_row_opened) begin @@ -8209,14 +6695,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_209 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_210; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (builder_bankmachine4_state) @@ -8245,14 +6724,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_210 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_211; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (builder_bankmachine4_state) @@ -8293,14 +6765,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_211 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_212; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine4_state) @@ -8326,14 +6791,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_212 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_213; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine4_state) @@ -8363,14 +6821,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_213 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_214; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (builder_bankmachine4_state) @@ -8408,14 +6859,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_214 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_215; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (builder_bankmachine4_state) @@ -8453,14 +6897,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_215 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_216; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (builder_bankmachine4_state) @@ -8498,14 +6935,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_216 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_217; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) @@ -8543,14 +6973,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (builder_bankmachine4_state) @@ -8576,57 +6999,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_218 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_219; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_219 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; @@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_220; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin @@ -8653,17 +7021,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_220 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_221; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin @@ -8671,9 +7032,6 @@ always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_221 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; @@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_222; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin @@ -8703,9 +7057,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); @@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on always @(*) begin builder_bankmachine5_next_state <= 4'd0; builder_bankmachine5_next_state <= builder_bankmachine5_state; @@ -8779,22 +7126,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8812,10 +7158,7 @@ always @(*) begin if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; - end + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -8824,14 +7167,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_224 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_225; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_open <= 1'd0; case (builder_bankmachine5_state) @@ -8857,14 +7193,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_close <= 1'd0; case (builder_bankmachine5_state) @@ -8890,14 +7219,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (builder_bankmachine5_state) @@ -8932,14 +7254,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_227 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_228; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (builder_bankmachine5_state) @@ -8968,14 +7283,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_228 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_229; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (builder_bankmachine5_state) @@ -9016,14 +7324,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_229 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_230; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -9049,14 +7350,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_230 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_231; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine5_state) @@ -9086,14 +7380,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_231 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_232; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (builder_bankmachine5_state) @@ -9131,14 +7418,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_232 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_233; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (builder_bankmachine5_state) @@ -9176,14 +7456,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_233 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_234; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (builder_bankmachine5_state) @@ -9221,16 +7494,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_234 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_235; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -9239,9 +7505,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine5_twtpcon_ready) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9252,32 +7515,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_235 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_236; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9288,23 +7556,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_236 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; @@ -9320,10 +7573,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; - -// synthesis translate_off -reg dummy_d_237; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin @@ -9331,17 +7580,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin @@ -9349,9 +7591,6 @@ always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_238 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; @@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_239; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin @@ -9381,9 +7616,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); @@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on always @(*) begin builder_bankmachine6_next_state <= 4'd0; builder_bankmachine6_next_state <= builder_bankmachine6_state; @@ -9457,24 +7685,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_240 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_241; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_row_open <= 1'd0; + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_open <= 1'd1; + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9488,29 +7712,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_row_close <= 1'd0; + main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9523,24 +7752,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_242 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_243; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9551,31 +7776,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_243 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_244; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) @@ -9610,14 +7813,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_244 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_245; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (builder_bankmachine6_state) @@ -9646,14 +7842,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) @@ -9694,14 +7883,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_246 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_247; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) @@ -9727,14 +7909,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_247 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_248; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) @@ -9764,14 +7939,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_248 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_249; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) @@ -9809,14 +7977,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_249 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_250; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) @@ -9854,14 +8015,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_250 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_251; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) @@ -9899,16 +8053,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_251 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_252; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -9917,9 +8064,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine6_twtpcon_ready) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9930,32 +8074,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_252 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_253; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9966,23 +8115,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_253 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; @@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_254; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin @@ -10009,17 +8139,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_254 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_255; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin @@ -10027,9 +8150,6 @@ always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_255 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; @@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_256; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin @@ -10059,9 +8175,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_256 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); @@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_257; -// synthesis translate_on always @(*) begin builder_bankmachine7_next_state <= 4'd0; builder_bankmachine7_next_state <= builder_bankmachine7_state; @@ -10135,14 +8244,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_257 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_258; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine7_row_open <= 1'd0; case (builder_bankmachine7_state) @@ -10168,14 +8311,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_258 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_259; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) @@ -10201,14 +8337,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_259 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_260; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) @@ -10243,14 +8372,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_260 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_261; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) @@ -10279,14 +8401,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_261 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_262; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) @@ -10327,14 +8442,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_262 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_263; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) @@ -10360,14 +8468,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_263 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_264; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) @@ -10397,16 +8498,9 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_264 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_265; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10432,7 +8526,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10442,16 +8536,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_265 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_266; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10476,8 +8563,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10487,16 +8574,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_266 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_267; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10521,7 +8601,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -10532,16 +8612,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_267 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_268; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10566,8 +8639,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -10577,14 +8650,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_268 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_269; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) @@ -10610,57 +8676,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_269 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_270; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_270 = dummy_s; -// synthesis translate_on end assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); @@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); - -// synthesis translate_off -reg dummy_d_271; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_valids <= 8'd0; main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); @@ -10706,9 +8717,6 @@ always @(*) begin main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_271 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; @@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_272; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end -// synthesis translate_off - dummy_d_272 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_273; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end -// synthesis translate_off - dummy_d_273 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_274; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end -// synthesis translate_off - dummy_d_274 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_275; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin @@ -10768,14 +8751,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_275 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_276; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin @@ -10784,14 +8760,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_276 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_277; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin @@ -10800,14 +8769,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_277 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_278; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin @@ -10816,14 +8778,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_278 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_279; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin @@ -10832,14 +8787,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_279 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_280; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin @@ -10848,14 +8796,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin @@ -10864,14 +8805,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin @@ -10880,15 +8814,8 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_282 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); - -// synthesis translate_off -reg dummy_d_283; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_valids <= 8'd0; main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); @@ -10899,9 +8826,6 @@ always @(*) begin main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); -// synthesis translate_off - dummy_d_283 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; @@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; - -// synthesis translate_off -reg dummy_d_284; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end -// synthesis translate_off - dummy_d_284 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_285; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end -// synthesis translate_off - dummy_d_285 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); assign main_litedramcore_dfi_p0_reset_n = 1'd1; @@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1; assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on always @(*) begin builder_multiplexer_next_state <= 4'd0; builder_multiplexer_next_state <= builder_multiplexer_state; @@ -11023,18 +8922,15 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on always @(*) begin - main_litedramcore_en0 <= 1'd0; + main_litedramcore_choose_cmd_want_activates <= 1'd0; case (builder_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -11055,24 +8951,23 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + main_litedramcore_steerer_sel3 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end 2'd2: begin @@ -11094,22 +8989,18 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_want_reads <= 1'd0; + main_litedramcore_en0 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin end @@ -11132,22 +9023,18 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_want_writes <= 1'd0; + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -11168,25 +9055,17 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end endcase -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; + main_litedramcore_choose_req_want_reads <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end end 2'd2: begin end @@ -11207,32 +9086,15 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel3 <= 2'd0; + main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel3 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 2'd2; - end - if ((main_litedramcore_wrcmdphase == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 1'd1; - end + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -11253,23 +9115,46 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel3 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 2'd2; + end + endcase +end +always @(*) begin + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end - if ((main_litedramcore_rdcmdphase == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on always @(*) begin main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) @@ -11297,14 +9182,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel0 <= 2'd0; case (builder_multiplexer_state) @@ -11346,14 +9224,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on always @(*) begin main_litedramcore_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -11381,14 +9252,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel1 <= 2'd0; case (builder_multiplexer_state) @@ -11429,14 +9293,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel2 <= 2'd0; case (builder_multiplexer_state) @@ -11477,51 +9334,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on -always @(*) begin - main_litedramcore_choose_cmd_want_activates <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; - end - end - endcase -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); @@ -11566,10 +9378,6 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on always @(*) begin main_litedramcore_interface_wdata <= 128'd0; case ({builder_new_master_wdata_ready1}) @@ -11580,14 +9388,7 @@ always @(*) begin main_litedramcore_interface_wdata <= 1'd0; end endcase -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on always @(*) begin main_litedramcore_interface_wdata_we <= 16'd0; case ({builder_new_master_wdata_ready1}) @@ -11598,9 +9399,6 @@ always @(*) begin main_litedramcore_interface_wdata_we <= 1'd0; end endcase -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on end assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; assign builder_roundrobin0_grant = 1'd0; @@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0; assign builder_roundrobin5_grant = 1'd0; assign builder_roundrobin6_grant = 1'd0; assign builder_roundrobin7_grant = 1'd0; - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on always @(*) begin builder_next_state <= 2'd0; builder_next_state <= builder_state; @@ -11631,16 +9425,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value0 <= 8'd0; + builder_litedramcore_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin end @@ -11650,14 +9437,7 @@ always @(*) begin builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on always @(*) begin builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; case (builder_state) @@ -11669,14 +9449,19 @@ always @(*) begin builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end always @(*) begin builder_litedramcore_adr_next_value1 <= 14'd0; case (builder_state) @@ -11691,14 +9476,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on always @(*) begin builder_litedramcore_adr_next_value_ce1 <= 1'd0; case (builder_state) @@ -11713,14 +9491,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on always @(*) begin builder_litedramcore_we_next_value2 <= 1'd0; case (builder_state) @@ -11735,14 +9506,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on always @(*) begin builder_litedramcore_we_next_value_ce2 <= 1'd0; case (builder_state) @@ -11757,14 +9521,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on always @(*) begin builder_litedramcore_wishbone_dat_r <= 32'd0; case (builder_state) @@ -11776,28 +9533,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on -always @(*) begin - builder_litedramcore_wishbone_ack <= 1'd0; - case (builder_state) - 1'd1: begin - end - 2'd2: begin - builder_litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on end assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; @@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we; assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; assign main_wb_bus_err = builder_litedramcore_wishbone_err; -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; + builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_we <= 1'd0; + builder_csrbank0_init_done0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_done0_w = main_init_done_storage; assign builder_csrbank0_init_error0_w = main_init_error_storage; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_337 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_338; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_338 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_339; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_339 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_340; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_340 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; @@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; - -// synthesis translate_off -reg dummy_d_341; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_control0_we <= 1'd0; + builder_csrbank2_dfii_control0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_341 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_342; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_control0_re <= 1'd0; + builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_342 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_343; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_343 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_344; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_344 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_345; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_345 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_346; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_346 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_347; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_347 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_348; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_348 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_349; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_349 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_350; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_350 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_351; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_351 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_352; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_352 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_353; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_353 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_354; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_354 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_355; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_355 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_356; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_357 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_358; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_358 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_359; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_359 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_360; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_360 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_361; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_361 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_362; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_362 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_363; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_363 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_364; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_364 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_365; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_365 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_366; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_366 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_367; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_367 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_368; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_368 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_369; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_369 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_370; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_370 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_371; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_371 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_372; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_372 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_373; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_373 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_374; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - builder_csrbank2_dfii_pi1_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_374 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_375; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_375 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_376; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_376 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_377; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_377 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_378; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_378 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_379; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_379 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_380; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_380 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_381; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_381 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_382; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_382 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_383; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_383 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_384; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_384 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_385; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_385 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_386; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_386 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_387; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_387 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_388; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_388 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_389; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_389 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_390; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_390 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_391; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_391 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_392; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_392 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_393; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_393 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_394; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_394 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_395; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_395 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_396; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_396 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_397; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_397 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_398; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_398 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_399; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_399 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_400; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi2_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_400 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_401; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin - builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_401 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_402; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_402 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_403; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_403 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_404; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_404 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_405; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_405 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_406; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_406 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_407; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_407 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_408; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_408 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_409; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_409 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_410; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_410 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_411; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_411 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_412; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_412 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_413; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_413 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_414; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_414 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_415; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_416; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_416 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_417; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_417 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_418; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_418 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_419; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_419 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_420; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_420 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_421; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_421 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_422; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_422 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_423; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_423 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_424; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_424 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_425; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_425 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_426; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_426 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_427; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_427 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_428; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_428 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_429; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_429 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_430; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_430 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_431; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_431 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_432; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_432 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_433; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_433 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_434; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_434 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_435; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_435 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_436; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_436 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_437; -// synthesis translate_on +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_437 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_438; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_438 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_439; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_439 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_440; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_440 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_441; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_441 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_442; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_442 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_443; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_443 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_444; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_444 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_445; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_445 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_446; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_446 = dummy_s; -// synthesis translate_on end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; @@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; -assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[13:8]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0]; assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; -assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; -assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[13:8]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0]; assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; -assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; -assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[13:8]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0]; assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; -assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; -assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[13:8]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0]; assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; -assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_csr_interconnect_adr = builder_litedramcore_adr; assign builder_csr_interconnect_we = builder_litedramcore_we; assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; @@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); - -// synthesis translate_off -reg dummy_d_447; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13760,14 +10147,7 @@ always @(*) begin builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase -// synthesis translate_off - dummy_d_447 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_448; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed1 <= 14'd0; case (main_litedramcore_choose_cmd_grant) @@ -13796,14 +10176,7 @@ always @(*) begin builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_448 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_449; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed2 <= 3'd0; case (main_litedramcore_choose_cmd_grant) @@ -13832,14 +10205,7 @@ always @(*) begin builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_449 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_450; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed3 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13868,14 +10234,7 @@ always @(*) begin builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_450 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_451; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed4 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13904,14 +10263,7 @@ always @(*) begin builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_451 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_452; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed5 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13940,14 +10292,7 @@ always @(*) begin builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_452 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_453; -// synthesis translate_on always @(*) begin builder_t_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13976,14 +10321,7 @@ always @(*) begin builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_453 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_454; -// synthesis translate_on always @(*) begin builder_t_array_muxed1 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14012,14 +10350,7 @@ always @(*) begin builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_454 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_455; -// synthesis translate_on always @(*) begin builder_t_array_muxed2 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14048,14 +10379,7 @@ always @(*) begin builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_455 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_456; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed6 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14084,14 +10408,7 @@ always @(*) begin builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase -// synthesis translate_off - dummy_d_456 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_457; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed7 <= 14'd0; case (main_litedramcore_choose_req_grant) @@ -14120,14 +10437,7 @@ always @(*) begin builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_457 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_458; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed8 <= 3'd0; case (main_litedramcore_choose_req_grant) @@ -14156,14 +10466,7 @@ always @(*) begin builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_458 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_459; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed9 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14192,14 +10495,7 @@ always @(*) begin builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_459 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_460; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed10 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14228,14 +10524,7 @@ always @(*) begin builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_460 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_461; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed11 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14264,14 +10553,7 @@ always @(*) begin builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_461 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_462; -// synthesis translate_on always @(*) begin builder_t_array_muxed3 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14300,14 +10582,7 @@ always @(*) begin builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_462 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_463; -// synthesis translate_on always @(*) begin builder_t_array_muxed4 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14336,14 +10611,7 @@ always @(*) begin builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_463 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_464; -// synthesis translate_on always @(*) begin builder_t_array_muxed5 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14372,14 +10640,7 @@ always @(*) begin builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_464 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_465; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed12 <= 21'd0; case (builder_roundrobin0_grant) @@ -14387,14 +10648,7 @@ always @(*) begin builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_465 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_466; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed13 <= 1'd0; case (builder_roundrobin0_grant) @@ -14402,14 +10656,7 @@ always @(*) begin builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_466 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_467; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed14 <= 1'd0; case (builder_roundrobin0_grant) @@ -14417,14 +10664,7 @@ always @(*) begin builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_467 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_468; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed15 <= 21'd0; case (builder_roundrobin1_grant) @@ -14432,14 +10672,7 @@ always @(*) begin builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_468 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_469; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed16 <= 1'd0; case (builder_roundrobin1_grant) @@ -14447,14 +10680,7 @@ always @(*) begin builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_469 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_470; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed17 <= 1'd0; case (builder_roundrobin1_grant) @@ -14462,14 +10688,7 @@ always @(*) begin builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_470 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_471; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed18 <= 21'd0; case (builder_roundrobin2_grant) @@ -14477,14 +10696,7 @@ always @(*) begin builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_471 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_472; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed19 <= 1'd0; case (builder_roundrobin2_grant) @@ -14492,14 +10704,7 @@ always @(*) begin builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_472 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_473; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed20 <= 1'd0; case (builder_roundrobin2_grant) @@ -14507,14 +10712,7 @@ always @(*) begin builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_473 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_474; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed21 <= 21'd0; case (builder_roundrobin3_grant) @@ -14522,14 +10720,7 @@ always @(*) begin builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_474 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_475; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed22 <= 1'd0; case (builder_roundrobin3_grant) @@ -14537,14 +10728,7 @@ always @(*) begin builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_475 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_476; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed23 <= 1'd0; case (builder_roundrobin3_grant) @@ -14552,14 +10736,7 @@ always @(*) begin builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_476 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_477; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed24 <= 21'd0; case (builder_roundrobin4_grant) @@ -14567,14 +10744,7 @@ always @(*) begin builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_477 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_478; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed25 <= 1'd0; case (builder_roundrobin4_grant) @@ -14582,14 +10752,7 @@ always @(*) begin builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_478 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_479; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed26 <= 1'd0; case (builder_roundrobin4_grant) @@ -14597,14 +10760,7 @@ always @(*) begin builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_479 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_480; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed27 <= 21'd0; case (builder_roundrobin5_grant) @@ -14612,14 +10768,7 @@ always @(*) begin builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_480 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_481; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed28 <= 1'd0; case (builder_roundrobin5_grant) @@ -14627,14 +10776,7 @@ always @(*) begin builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_481 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_482; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed29 <= 1'd0; case (builder_roundrobin5_grant) @@ -14642,14 +10784,7 @@ always @(*) begin builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_482 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_483; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed30 <= 21'd0; case (builder_roundrobin6_grant) @@ -14657,14 +10792,7 @@ always @(*) begin builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_483 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_484; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed31 <= 1'd0; case (builder_roundrobin6_grant) @@ -14672,14 +10800,7 @@ always @(*) begin builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_484 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_485; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed32 <= 1'd0; case (builder_roundrobin6_grant) @@ -14687,14 +10808,7 @@ always @(*) begin builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_485 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_486; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed33 <= 21'd0; case (builder_roundrobin7_grant) @@ -14702,14 +10816,7 @@ always @(*) begin builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_486 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_487; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed34 <= 1'd0; case (builder_roundrobin7_grant) @@ -14717,14 +10824,7 @@ always @(*) begin builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_487 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_488; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed35 <= 1'd0; case (builder_roundrobin7_grant) @@ -14732,14 +10832,7 @@ always @(*) begin builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_488 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_489; -// synthesis translate_on always @(*) begin builder_array_muxed0 <= 3'd0; case (main_litedramcore_steerer_sel0) @@ -14756,14 +10849,7 @@ always @(*) begin builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_489 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_490; -// synthesis translate_on always @(*) begin builder_array_muxed1 <= 14'd0; case (main_litedramcore_steerer_sel0) @@ -14780,14 +10866,7 @@ always @(*) begin builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_490 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_491; -// synthesis translate_on always @(*) begin builder_array_muxed2 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14804,14 +10883,7 @@ always @(*) begin builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_491 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_492; -// synthesis translate_on always @(*) begin builder_array_muxed3 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14828,14 +10900,7 @@ always @(*) begin builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_492 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_493; -// synthesis translate_on always @(*) begin builder_array_muxed4 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14852,14 +10917,7 @@ always @(*) begin builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_493 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_494; -// synthesis translate_on always @(*) begin builder_array_muxed5 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14876,14 +10934,7 @@ always @(*) begin builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_494 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_495; -// synthesis translate_on always @(*) begin builder_array_muxed6 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14900,14 +10951,7 @@ always @(*) begin builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_495 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_496; -// synthesis translate_on always @(*) begin builder_array_muxed7 <= 3'd0; case (main_litedramcore_steerer_sel1) @@ -14924,14 +10968,7 @@ always @(*) begin builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_496 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_497; -// synthesis translate_on always @(*) begin builder_array_muxed8 <= 14'd0; case (main_litedramcore_steerer_sel1) @@ -14948,14 +10985,7 @@ always @(*) begin builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_497 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_498; -// synthesis translate_on always @(*) begin builder_array_muxed9 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14972,14 +11002,7 @@ always @(*) begin builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_498 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_499; -// synthesis translate_on always @(*) begin builder_array_muxed10 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14996,14 +11019,7 @@ always @(*) begin builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_499 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_500; -// synthesis translate_on always @(*) begin builder_array_muxed11 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15020,14 +11036,7 @@ always @(*) begin builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_500 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_501; -// synthesis translate_on always @(*) begin builder_array_muxed12 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15044,14 +11053,7 @@ always @(*) begin builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_501 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_502; -// synthesis translate_on always @(*) begin builder_array_muxed13 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15068,14 +11070,7 @@ always @(*) begin builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_502 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_503; -// synthesis translate_on always @(*) begin builder_array_muxed14 <= 3'd0; case (main_litedramcore_steerer_sel2) @@ -15092,14 +11087,7 @@ always @(*) begin builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_503 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_504; -// synthesis translate_on always @(*) begin builder_array_muxed15 <= 14'd0; case (main_litedramcore_steerer_sel2) @@ -15116,14 +11104,7 @@ always @(*) begin builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_504 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_505; -// synthesis translate_on always @(*) begin builder_array_muxed16 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15140,14 +11121,7 @@ always @(*) begin builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_505 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_506; -// synthesis translate_on always @(*) begin builder_array_muxed17 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15164,14 +11138,7 @@ always @(*) begin builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_506 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_507; -// synthesis translate_on always @(*) begin builder_array_muxed18 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15188,14 +11155,7 @@ always @(*) begin builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_507 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_508; -// synthesis translate_on always @(*) begin builder_array_muxed19 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15212,14 +11172,7 @@ always @(*) begin builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_508 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_509; -// synthesis translate_on always @(*) begin builder_array_muxed20 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15236,14 +11189,7 @@ always @(*) begin builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_509 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_510; -// synthesis translate_on always @(*) begin builder_array_muxed21 <= 3'd0; case (main_litedramcore_steerer_sel3) @@ -15260,14 +11206,7 @@ always @(*) begin builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_510 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_511; -// synthesis translate_on always @(*) begin builder_array_muxed22 <= 14'd0; case (main_litedramcore_steerer_sel3) @@ -15284,14 +11223,7 @@ always @(*) begin builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_511 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_512; -// synthesis translate_on always @(*) begin builder_array_muxed23 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15308,14 +11240,7 @@ always @(*) begin builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_512 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_513; -// synthesis translate_on always @(*) begin builder_array_muxed24 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15332,14 +11257,7 @@ always @(*) begin builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_513 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_514; -// synthesis translate_on always @(*) begin builder_array_muxed25 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15356,14 +11274,7 @@ always @(*) begin builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_514 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_515; -// synthesis translate_on always @(*) begin builder_array_muxed26 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15380,14 +11291,7 @@ always @(*) begin builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_515 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_516; -// synthesis translate_on always @(*) begin builder_array_muxed27 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15404,15 +11308,17 @@ always @(*) begin builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_516 = dummy_s; -// synthesis translate_on end assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge iodelay_clk) begin if ((main_reset_counter != 1'd0)) begin main_reset_counter <= (main_reset_counter - 1'd1); @@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end @@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; - if (builder_csrbank2_dfii_pi0_address1_re) begin - main_litedramcore_phaseinjector0_address_storage[13:8] <= builder_csrbank2_dfii_pi0_address1_r; - end if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; - if (builder_csrbank2_dfii_pi0_wrdata3_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; - end - if (builder_csrbank2_dfii_pi0_wrdata2_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; - end - if (builder_csrbank2_dfii_pi0_wrdata1_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; - end if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; - main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; - if (builder_csrbank2_dfii_pi1_address1_re) begin - main_litedramcore_phaseinjector1_address_storage[13:8] <= builder_csrbank2_dfii_pi1_address1_r; - end if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; - if (builder_csrbank2_dfii_pi1_wrdata3_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; - end - if (builder_csrbank2_dfii_pi1_wrdata2_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; - end - if (builder_csrbank2_dfii_pi1_wrdata1_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; - end if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; - main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; - if (builder_csrbank2_dfii_pi2_address1_re) begin - main_litedramcore_phaseinjector2_address_storage[13:8] <= builder_csrbank2_dfii_pi2_address1_r; - end if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; - if (builder_csrbank2_dfii_pi2_wrdata3_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; - end - if (builder_csrbank2_dfii_pi2_wrdata2_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; - end - if (builder_csrbank2_dfii_pi2_wrdata1_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; - end if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; - main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; - if (builder_csrbank2_dfii_pi3_address1_re) begin - main_litedramcore_phaseinjector3_address_storage[13:8] <= builder_csrbank2_dfii_pi3_address1_r; - end if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; - if (builder_csrbank2_dfii_pi3_wrdata3_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; - end - if (builder_csrbank2_dfii_pi3_wrdata2_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; - end - if (builder_csrbank2_dfii_pi3_wrdata1_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; - end if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; - main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin main_a7ddrphy_rst_storage <= 1'd0; main_a7ddrphy_rst_re <= 1'd0; @@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + BUFG BUFG( .I(main_clkout0), .O(main_clkout_buf0) @@ -19581,118 +15360,150 @@ IOBUF IOBUF_15( .O(main_a7ddrphy_dq_i_nodelay15) ); +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage[0:15]; -reg [23:0] memdat; +reg [23:0] storage_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_1[0:15]; -reg [23:0] memdat_1; +reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_2[0:15]; -reg [23:0] memdat_2; +reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_3[0:15]; -reg [23:0] memdat_3; +reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_4[0:15]; -reg [23:0] memdat_4; +reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_5[0:15]; -reg [23:0] memdat_5; +reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_6[0:15]; -reg [23:0] memdat_6; +reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_7[0:15]; -reg [23:0] memdat_7; +reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + FD FD( .C(main_clkin), .D(main_reset), @@ -19849,3 +15660,7 @@ PLLE2_ADV #( ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 08:32:09. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init index 6b2631b..49b28a5 100644 --- a/litedram/generated/genesys2/litedram_core.init +++ b/litedram/generated/genesys2/litedram_core.init @@ -527,11 +527,11 @@ f8c100e87c651b78 38c100d87fc3f378 f90100f8f8e100f0 f9410108f9210100 -6000000048002fc5 +6000000048002f19 7fc3f3787c7f1b78 -60000000480029d1 +600000004800293d 7fe3fb78382100b0 -00000000480035bc +0000000048003594 0000028001000000 000000004e800020 0000000000000000 @@ -540,83 +540,84 @@ f9410108f9210100 0000000000000000 3842bc203c4c0001 7d8000267c0802a6 -91810008480034f9 -480029cdf821fed1 +91810008480034d1 +48002939f821fed1 3c62ffff60000000 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-//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:35 -//-------------------------------------------------------------------------------- -module litedram_core( - input wire clk, - input wire rst, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 08:32:12 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + input wire rst, output wire pll_locked, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, @@ -12,9 +28,9 @@ module litedram_core( output wire ddram_we_n, output wire ddram_cs_n, output wire [3:0] ddram_dm, - inout wire [31:0] ddram_dq, - inout wire [3:0] ddram_dqs_p, - inout wire [3:0] ddram_dqs_n, + inout wire [31:0] ddram_dq, + inout wire [3:0] ddram_dqs_p, + inout wire [3:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, @@ -22,32 +38,38 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, - input wire [31:0] user_port_native_0_wdata_we, - input wire [255:0] user_port_native_0_wdata_data, + input wire [31:0] user_port_native_0_wdata_we, + input wire [255:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, + input wire user_port_native_0_rdata_ready, output wire [255:0] user_port_native_0_rdata_data ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_rst = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -55,7 +77,7 @@ wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; wire main_reset; -reg main_power_down = 1'd0; +reg main_power_down = 1'd0; wire main_locked; wire main_clkin; wire main_clkout0; @@ -66,72 +88,72 @@ wire main_clkout2; wire main_clkout_buf2; wire main_clkout3; wire main_clkout_buf3; -reg [3:0] main_reset_counter = 4'd15; -reg main_ic_reset = 1'd1; -reg main_k7ddrphy_rst_storage = 1'd0; -reg main_k7ddrphy_rst_re = 1'd0; -reg [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8; -reg main_k7ddrphy_half_sys8x_taps_re = 1'd0; -reg main_k7ddrphy_wlevel_en_storage = 1'd0; -reg main_k7ddrphy_wlevel_en_re = 1'd0; -reg main_k7ddrphy_wlevel_strobe_re = 1'd0; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_k7ddrphy_rst_storage = 1'd0; +reg main_k7ddrphy_rst_re = 1'd0; +reg [4:0] main_k7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_k7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_k7ddrphy_wlevel_en_storage = 1'd0; +reg main_k7ddrphy_wlevel_en_re = 1'd0; +reg main_k7ddrphy_wlevel_strobe_re = 1'd0; wire main_k7ddrphy_wlevel_strobe_r; -reg main_k7ddrphy_wlevel_strobe_we = 1'd0; -reg main_k7ddrphy_wlevel_strobe_w = 1'd0; -reg main_k7ddrphy_cdly_rst_re = 1'd0; +reg main_k7ddrphy_wlevel_strobe_we = 1'd0; +reg main_k7ddrphy_wlevel_strobe_w = 1'd0; +reg main_k7ddrphy_cdly_rst_re = 1'd0; wire main_k7ddrphy_cdly_rst_r; -reg main_k7ddrphy_cdly_rst_we = 1'd0; -reg main_k7ddrphy_cdly_rst_w = 1'd0; -reg main_k7ddrphy_cdly_inc_re = 1'd0; +reg main_k7ddrphy_cdly_rst_we = 1'd0; +reg main_k7ddrphy_cdly_rst_w = 1'd0; +reg main_k7ddrphy_cdly_inc_re = 1'd0; wire main_k7ddrphy_cdly_inc_r; -reg main_k7ddrphy_cdly_inc_we = 1'd0; -reg main_k7ddrphy_cdly_inc_w = 1'd0; -reg [3:0] main_k7ddrphy_dly_sel_storage = 4'd0; -reg main_k7ddrphy_dly_sel_re = 1'd0; -reg main_k7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_k7ddrphy_cdly_inc_we = 1'd0; +reg main_k7ddrphy_cdly_inc_w = 1'd0; +reg [3:0] main_k7ddrphy_dly_sel_storage = 4'd0; +reg main_k7ddrphy_dly_sel_re = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_re = 1'd0; wire main_k7ddrphy_rdly_dq_rst_r; -reg main_k7ddrphy_rdly_dq_rst_we = 1'd0; -reg main_k7ddrphy_rdly_dq_rst_w = 1'd0; -reg main_k7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_k7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_re = 1'd0; wire main_k7ddrphy_rdly_dq_inc_r; -reg main_k7ddrphy_rdly_dq_inc_we = 1'd0; -reg main_k7ddrphy_rdly_dq_inc_w = 1'd0; -reg main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_k7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; wire main_k7ddrphy_rdly_dq_bitslip_rst_r; -reg main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg main_k7ddrphy_rdly_dq_bitslip_re = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_re = 1'd0; wire main_k7ddrphy_rdly_dq_bitslip_r; -reg main_k7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg main_k7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg main_k7ddrphy_wdly_dq_rst_re = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_k7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_re = 1'd0; wire main_k7ddrphy_wdly_dq_rst_r; -reg main_k7ddrphy_wdly_dq_rst_we = 1'd0; -reg main_k7ddrphy_wdly_dq_rst_w = 1'd0; -reg main_k7ddrphy_wdly_dq_inc_re = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dq_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_re = 1'd0; wire main_k7ddrphy_wdly_dq_inc_r; -reg main_k7ddrphy_wdly_dq_inc_we = 1'd0; -reg main_k7ddrphy_wdly_dq_inc_w = 1'd0; -reg main_k7ddrphy_wdly_dqs_rst_re = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_we = 1'd0; +reg main_k7ddrphy_wdly_dq_inc_w = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_re = 1'd0; wire main_k7ddrphy_wdly_dqs_rst_r; -reg main_k7ddrphy_wdly_dqs_rst_we = 1'd0; -reg main_k7ddrphy_wdly_dqs_rst_w = 1'd0; -reg main_k7ddrphy_wdly_dqs_inc_re = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dqs_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_re = 1'd0; wire main_k7ddrphy_wdly_dqs_inc_r; -reg main_k7ddrphy_wdly_dqs_inc_we = 1'd0; -reg main_k7ddrphy_wdly_dqs_inc_w = 1'd0; -reg main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_we = 1'd0; +reg main_k7ddrphy_wdly_dqs_inc_w = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; wire main_k7ddrphy_wdly_dq_bitslip_rst_r; -reg main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg main_k7ddrphy_wdly_dq_bitslip_re = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_re = 1'd0; wire main_k7ddrphy_wdly_dq_bitslip_r; -reg main_k7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg main_k7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] main_k7ddrphy_rdphase_storage = 2'd1; -reg main_k7ddrphy_rdphase_re = 1'd0; -reg [1:0] main_k7ddrphy_wrphase_storage = 2'd2; -reg main_k7ddrphy_wrphase_re = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_k7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_k7ddrphy_rdphase_storage = 2'd1; +reg main_k7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_k7ddrphy_wrphase_storage = 2'd2; +reg main_k7ddrphy_wrphase_re = 1'd0; wire [14:0] main_k7ddrphy_dfi_p0_address; wire [2:0] main_k7ddrphy_dfi_p0_bank; wire main_k7ddrphy_dfi_p0_cas_n; @@ -146,7 +168,7 @@ wire [63:0] main_k7ddrphy_dfi_p0_wrdata; wire main_k7ddrphy_dfi_p0_wrdata_en; wire [7:0] main_k7ddrphy_dfi_p0_wrdata_mask; wire main_k7ddrphy_dfi_p0_rddata_en; -reg [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0; +reg [63:0] main_k7ddrphy_dfi_p0_rddata = 64'd0; wire main_k7ddrphy_dfi_p0_rddata_valid; wire [14:0] main_k7ddrphy_dfi_p1_address; wire [2:0] main_k7ddrphy_dfi_p1_bank; @@ -162,7 +184,7 @@ wire [63:0] main_k7ddrphy_dfi_p1_wrdata; wire main_k7ddrphy_dfi_p1_wrdata_en; wire [7:0] main_k7ddrphy_dfi_p1_wrdata_mask; wire main_k7ddrphy_dfi_p1_rddata_en; -reg [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0; +reg [63:0] main_k7ddrphy_dfi_p1_rddata = 64'd0; wire main_k7ddrphy_dfi_p1_rddata_valid; wire [14:0] main_k7ddrphy_dfi_p2_address; wire [2:0] main_k7ddrphy_dfi_p2_bank; @@ -178,7 +200,7 @@ wire [63:0] main_k7ddrphy_dfi_p2_wrdata; wire main_k7ddrphy_dfi_p2_wrdata_en; wire [7:0] main_k7ddrphy_dfi_p2_wrdata_mask; wire main_k7ddrphy_dfi_p2_rddata_en; -reg [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0; +reg [63:0] main_k7ddrphy_dfi_p2_rddata = 64'd0; wire main_k7ddrphy_dfi_p2_rddata_valid; wire [14:0] main_k7ddrphy_dfi_p3_address; wire [2:0] main_k7ddrphy_dfi_p3_bank; @@ -194,7 +216,7 @@ wire [63:0] main_k7ddrphy_dfi_p3_wrdata; wire main_k7ddrphy_dfi_p3_wrdata_en; wire [7:0] main_k7ddrphy_dfi_p3_wrdata_mask; wire main_k7ddrphy_dfi_p3_rddata_en; -reg [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0; +reg [63:0] main_k7ddrphy_dfi_p3_rddata = 64'd0; wire main_k7ddrphy_dfi_p3_rddata_valid; wire main_k7ddrphy_sd_clk_se_nodelay; wire main_k7ddrphy_sd_clk_se_delayed; @@ -223,522 +245,522 @@ wire main_k7ddrphy_oq21; wire main_k7ddrphy_oq22; wire main_k7ddrphy_oq23; wire main_k7ddrphy_oq24; -reg main_k7ddrphy_dqs_oe = 1'd0; +reg main_k7ddrphy_dqs_oe = 1'd0; wire main_k7ddrphy_dqs_preamble; wire main_k7ddrphy_dqs_postamble; wire main_k7ddrphy_dqs_oe_delay_tappeddelayline; -reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg main_k7ddrphy_dqspattern0 = 1'd0; -reg main_k7ddrphy_dqspattern1 = 1'd0; -reg [7:0] main_k7ddrphy_dqspattern_o = 8'd0; +reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_dqspattern0 = 1'd0; +reg main_k7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_k7ddrphy_dqspattern_o = 8'd0; wire main_k7ddrphy_dqs_o_no_delay0; wire main_k7ddrphy_dqs_o_delayed0; wire main_k7ddrphy_dqs_t0; -reg [7:0] main_k7ddrphy_bitslip00 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r0 = 16'd0; wire main_k7ddrphy0; wire main_k7ddrphy_dqs_o_no_delay1; wire main_k7ddrphy_dqs_o_delayed1; wire main_k7ddrphy_dqs_t1; -reg [7:0] main_k7ddrphy_bitslip10 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r0 = 16'd0; wire main_k7ddrphy1; wire main_k7ddrphy_dqs_o_no_delay2; wire main_k7ddrphy_dqs_o_delayed2; wire main_k7ddrphy_dqs_t2; -reg [7:0] main_k7ddrphy_bitslip20 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r0 = 16'd0; wire main_k7ddrphy2; wire main_k7ddrphy_dqs_o_no_delay3; wire main_k7ddrphy_dqs_o_delayed3; wire main_k7ddrphy_dqs_t3; -reg [7:0] main_k7ddrphy_bitslip30 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r0 = 16'd0; wire main_k7ddrphy3; wire main_k7ddrphy_dm_o_nodelay0; -reg [7:0] main_k7ddrphy_bitslip01 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r1 = 16'd0; wire main_k7ddrphy_dm_o_nodelay1; -reg [7:0] main_k7ddrphy_bitslip11 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r1 = 16'd0; wire main_k7ddrphy_dm_o_nodelay2; -reg [7:0] main_k7ddrphy_bitslip21 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip21 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r1 = 16'd0; wire main_k7ddrphy_dm_o_nodelay3; -reg [7:0] main_k7ddrphy_bitslip31 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip31 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r1 = 16'd0; wire main_k7ddrphy_dq_oe; wire main_k7ddrphy_dq_oe_delay_tappeddelayline; -reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire main_k7ddrphy_dq_o_nodelay0; wire main_k7ddrphy_dq_o_delayed0; wire main_k7ddrphy_dq_i_nodelay0; wire main_k7ddrphy_dq_i_delayed0; wire main_k7ddrphy_dq_t0; -reg [7:0] main_k7ddrphy_bitslip02 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] main_k7ddrphy_bitslip03; -reg [7:0] main_k7ddrphy_bitslip04 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip0_r3 = 16'd0; wire main_k7ddrphy_dq_o_nodelay1; wire main_k7ddrphy_dq_o_delayed1; wire main_k7ddrphy_dq_i_nodelay1; wire main_k7ddrphy_dq_i_delayed1; wire main_k7ddrphy_dq_t1; -reg [7:0] main_k7ddrphy_bitslip12 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] main_k7ddrphy_bitslip13; -reg [7:0] main_k7ddrphy_bitslip14 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip1_r3 = 16'd0; wire main_k7ddrphy_dq_o_nodelay2; wire main_k7ddrphy_dq_o_delayed2; wire main_k7ddrphy_dq_i_nodelay2; wire main_k7ddrphy_dq_i_delayed2; wire main_k7ddrphy_dq_t2; -reg [7:0] main_k7ddrphy_bitslip22 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r2 = 16'd0; wire [7:0] main_k7ddrphy_bitslip23; -reg [7:0] main_k7ddrphy_bitslip24 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip24 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip2_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip2_r3 = 16'd0; wire main_k7ddrphy_dq_o_nodelay3; wire main_k7ddrphy_dq_o_delayed3; wire main_k7ddrphy_dq_i_nodelay3; wire main_k7ddrphy_dq_i_delayed3; wire main_k7ddrphy_dq_t3; -reg [7:0] main_k7ddrphy_bitslip32 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value2 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r2 = 16'd0; wire [7:0] main_k7ddrphy_bitslip33; -reg [7:0] main_k7ddrphy_bitslip34 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip34 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip3_value3 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip3_r3 = 16'd0; wire main_k7ddrphy_dq_o_nodelay4; wire main_k7ddrphy_dq_o_delayed4; wire main_k7ddrphy_dq_i_nodelay4; wire main_k7ddrphy_dq_i_delayed4; wire main_k7ddrphy_dq_t4; -reg [7:0] main_k7ddrphy_bitslip40 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip41; -reg [7:0] main_k7ddrphy_bitslip42 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip4_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay5; wire main_k7ddrphy_dq_o_delayed5; wire main_k7ddrphy_dq_i_nodelay5; wire main_k7ddrphy_dq_i_delayed5; wire main_k7ddrphy_dq_t5; -reg [7:0] main_k7ddrphy_bitslip50 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip51; -reg [7:0] main_k7ddrphy_bitslip52 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip5_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay6; wire main_k7ddrphy_dq_o_delayed6; wire main_k7ddrphy_dq_i_nodelay6; wire main_k7ddrphy_dq_i_delayed6; wire main_k7ddrphy_dq_t6; -reg [7:0] main_k7ddrphy_bitslip60 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip61; -reg [7:0] main_k7ddrphy_bitslip62 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip6_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay7; wire main_k7ddrphy_dq_o_delayed7; wire main_k7ddrphy_dq_i_nodelay7; wire main_k7ddrphy_dq_i_delayed7; wire main_k7ddrphy_dq_t7; -reg [7:0] main_k7ddrphy_bitslip70 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip71; -reg [7:0] main_k7ddrphy_bitslip72 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip7_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay8; wire main_k7ddrphy_dq_o_delayed8; wire main_k7ddrphy_dq_i_nodelay8; wire main_k7ddrphy_dq_i_delayed8; wire main_k7ddrphy_dq_t8; -reg [7:0] main_k7ddrphy_bitslip80 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip81; -reg [7:0] main_k7ddrphy_bitslip82 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip8_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay9; wire main_k7ddrphy_dq_o_delayed9; wire main_k7ddrphy_dq_i_nodelay9; wire main_k7ddrphy_dq_i_delayed9; wire main_k7ddrphy_dq_t9; -reg [7:0] main_k7ddrphy_bitslip90 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip91; -reg [7:0] main_k7ddrphy_bitslip92 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip9_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay10; wire main_k7ddrphy_dq_o_delayed10; wire main_k7ddrphy_dq_i_nodelay10; wire main_k7ddrphy_dq_i_delayed10; wire main_k7ddrphy_dq_t10; -reg [7:0] main_k7ddrphy_bitslip100 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip101; -reg [7:0] main_k7ddrphy_bitslip102 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip10_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay11; wire main_k7ddrphy_dq_o_delayed11; wire main_k7ddrphy_dq_i_nodelay11; wire main_k7ddrphy_dq_i_delayed11; wire main_k7ddrphy_dq_t11; -reg [7:0] main_k7ddrphy_bitslip110 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip111; -reg [7:0] main_k7ddrphy_bitslip112 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip11_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay12; wire main_k7ddrphy_dq_o_delayed12; wire main_k7ddrphy_dq_i_nodelay12; wire main_k7ddrphy_dq_i_delayed12; wire main_k7ddrphy_dq_t12; -reg [7:0] main_k7ddrphy_bitslip120 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip121; -reg [7:0] main_k7ddrphy_bitslip122 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip12_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay13; wire main_k7ddrphy_dq_o_delayed13; wire main_k7ddrphy_dq_i_nodelay13; wire main_k7ddrphy_dq_i_delayed13; wire main_k7ddrphy_dq_t13; -reg [7:0] main_k7ddrphy_bitslip130 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip131; -reg [7:0] main_k7ddrphy_bitslip132 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip13_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay14; wire main_k7ddrphy_dq_o_delayed14; wire main_k7ddrphy_dq_i_nodelay14; wire main_k7ddrphy_dq_i_delayed14; wire main_k7ddrphy_dq_t14; -reg [7:0] main_k7ddrphy_bitslip140 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip141; -reg [7:0] main_k7ddrphy_bitslip142 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip14_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay15; wire main_k7ddrphy_dq_o_delayed15; wire main_k7ddrphy_dq_i_nodelay15; wire main_k7ddrphy_dq_i_delayed15; wire main_k7ddrphy_dq_t15; -reg [7:0] main_k7ddrphy_bitslip150 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip151; -reg [7:0] main_k7ddrphy_bitslip152 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip15_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay16; wire main_k7ddrphy_dq_o_delayed16; wire main_k7ddrphy_dq_i_nodelay16; wire main_k7ddrphy_dq_i_delayed16; wire main_k7ddrphy_dq_t16; -reg [7:0] main_k7ddrphy_bitslip160 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip160 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip16_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip16_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip161; -reg [7:0] main_k7ddrphy_bitslip162 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip162 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip16_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip16_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay17; wire main_k7ddrphy_dq_o_delayed17; wire main_k7ddrphy_dq_i_nodelay17; wire main_k7ddrphy_dq_i_delayed17; wire main_k7ddrphy_dq_t17; -reg [7:0] main_k7ddrphy_bitslip170 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip170 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip17_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip17_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip171; -reg [7:0] main_k7ddrphy_bitslip172 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip172 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip17_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip17_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay18; wire main_k7ddrphy_dq_o_delayed18; wire main_k7ddrphy_dq_i_nodelay18; wire main_k7ddrphy_dq_i_delayed18; wire main_k7ddrphy_dq_t18; -reg [7:0] main_k7ddrphy_bitslip180 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip180 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip18_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip18_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip181; -reg [7:0] main_k7ddrphy_bitslip182 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip182 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip18_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip18_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay19; wire main_k7ddrphy_dq_o_delayed19; wire main_k7ddrphy_dq_i_nodelay19; wire main_k7ddrphy_dq_i_delayed19; wire main_k7ddrphy_dq_t19; -reg [7:0] main_k7ddrphy_bitslip190 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip190 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip19_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip19_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip191; -reg [7:0] main_k7ddrphy_bitslip192 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip192 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip19_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip19_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay20; wire main_k7ddrphy_dq_o_delayed20; wire main_k7ddrphy_dq_i_nodelay20; wire main_k7ddrphy_dq_i_delayed20; wire main_k7ddrphy_dq_t20; -reg [7:0] main_k7ddrphy_bitslip200 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip200 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip20_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip20_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip201; -reg [7:0] main_k7ddrphy_bitslip202 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip202 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip20_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip20_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay21; wire main_k7ddrphy_dq_o_delayed21; wire main_k7ddrphy_dq_i_nodelay21; wire main_k7ddrphy_dq_i_delayed21; wire main_k7ddrphy_dq_t21; -reg [7:0] main_k7ddrphy_bitslip210 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip210 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip21_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip21_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip211; -reg [7:0] main_k7ddrphy_bitslip212 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip212 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip21_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip21_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay22; wire main_k7ddrphy_dq_o_delayed22; wire main_k7ddrphy_dq_i_nodelay22; wire main_k7ddrphy_dq_i_delayed22; wire main_k7ddrphy_dq_t22; -reg [7:0] main_k7ddrphy_bitslip220 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip220 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip22_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip22_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip221; -reg [7:0] main_k7ddrphy_bitslip222 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip222 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip22_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip22_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay23; wire main_k7ddrphy_dq_o_delayed23; wire main_k7ddrphy_dq_i_nodelay23; wire main_k7ddrphy_dq_i_delayed23; wire main_k7ddrphy_dq_t23; -reg [7:0] main_k7ddrphy_bitslip230 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip230 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip23_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip23_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip231; -reg [7:0] main_k7ddrphy_bitslip232 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip232 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip23_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip23_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay24; wire main_k7ddrphy_dq_o_delayed24; wire main_k7ddrphy_dq_i_nodelay24; wire main_k7ddrphy_dq_i_delayed24; wire main_k7ddrphy_dq_t24; -reg [7:0] main_k7ddrphy_bitslip240 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip240 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip24_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip24_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip241; -reg [7:0] main_k7ddrphy_bitslip242 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip242 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip24_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip24_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay25; wire main_k7ddrphy_dq_o_delayed25; wire main_k7ddrphy_dq_i_nodelay25; wire main_k7ddrphy_dq_i_delayed25; wire main_k7ddrphy_dq_t25; -reg [7:0] main_k7ddrphy_bitslip250 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip250 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip25_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip25_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip251; -reg [7:0] main_k7ddrphy_bitslip252 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip252 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip25_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip25_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay26; wire main_k7ddrphy_dq_o_delayed26; wire main_k7ddrphy_dq_i_nodelay26; wire main_k7ddrphy_dq_i_delayed26; wire main_k7ddrphy_dq_t26; -reg [7:0] main_k7ddrphy_bitslip260 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip260 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip26_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip26_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip261; -reg [7:0] main_k7ddrphy_bitslip262 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip262 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip26_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip26_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay27; wire main_k7ddrphy_dq_o_delayed27; wire main_k7ddrphy_dq_i_nodelay27; wire main_k7ddrphy_dq_i_delayed27; wire main_k7ddrphy_dq_t27; -reg [7:0] main_k7ddrphy_bitslip270 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip270 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip27_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip27_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip271; -reg [7:0] main_k7ddrphy_bitslip272 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip272 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip27_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip27_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay28; wire main_k7ddrphy_dq_o_delayed28; wire main_k7ddrphy_dq_i_nodelay28; wire main_k7ddrphy_dq_i_delayed28; wire main_k7ddrphy_dq_t28; -reg [7:0] main_k7ddrphy_bitslip280 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip280 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip28_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip28_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip281; -reg [7:0] main_k7ddrphy_bitslip282 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip282 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip28_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip28_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay29; wire main_k7ddrphy_dq_o_delayed29; wire main_k7ddrphy_dq_i_nodelay29; wire main_k7ddrphy_dq_i_delayed29; wire main_k7ddrphy_dq_t29; -reg [7:0] main_k7ddrphy_bitslip290 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip290 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip29_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip29_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip291; -reg [7:0] main_k7ddrphy_bitslip292 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip292 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip29_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip29_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay30; wire main_k7ddrphy_dq_o_delayed30; wire main_k7ddrphy_dq_i_nodelay30; wire main_k7ddrphy_dq_i_delayed30; wire main_k7ddrphy_dq_t30; -reg [7:0] main_k7ddrphy_bitslip300 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip300 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip30_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip30_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip301; -reg [7:0] main_k7ddrphy_bitslip302 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip302 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip30_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip30_r1 = 16'd0; wire main_k7ddrphy_dq_o_nodelay31; wire main_k7ddrphy_dq_o_delayed31; wire main_k7ddrphy_dq_i_nodelay31; wire main_k7ddrphy_dq_i_delayed31; wire main_k7ddrphy_dq_t31; -reg [7:0] main_k7ddrphy_bitslip310 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0; +reg [7:0] main_k7ddrphy_bitslip310 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip31_value0 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip31_r0 = 16'd0; wire [7:0] main_k7ddrphy_bitslip311; -reg [7:0] main_k7ddrphy_bitslip312 = 8'd0; -reg [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7; -reg [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg [7:0] main_k7ddrphy_bitslip312 = 8'd0; +reg [2:0] main_k7ddrphy_bitslip31_value1 = 3'd7; +reg [15:0] main_k7ddrphy_bitslip31_r1 = 16'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [14:0] main_litedramcore_inti_p0_address; wire [2:0] main_litedramcore_inti_p0_bank; -reg main_litedramcore_inti_p0_cas_n = 1'd1; -reg main_litedramcore_inti_p0_cs_n = 1'd1; -reg main_litedramcore_inti_p0_ras_n = 1'd1; -reg main_litedramcore_inti_p0_we_n = 1'd1; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; wire main_litedramcore_inti_p0_cke; wire main_litedramcore_inti_p0_odt; wire main_litedramcore_inti_p0_reset_n; -reg main_litedramcore_inti_p0_act_n = 1'd1; +reg main_litedramcore_inti_p0_act_n = 1'd1; wire [63:0] main_litedramcore_inti_p0_wrdata; wire main_litedramcore_inti_p0_wrdata_en; wire [7:0] main_litedramcore_inti_p0_wrdata_mask; wire main_litedramcore_inti_p0_rddata_en; -reg [63:0] main_litedramcore_inti_p0_rddata = 64'd0; -reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_inti_p0_rddata = 64'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; wire [14:0] main_litedramcore_inti_p1_address; wire [2:0] main_litedramcore_inti_p1_bank; -reg main_litedramcore_inti_p1_cas_n = 1'd1; -reg main_litedramcore_inti_p1_cs_n = 1'd1; -reg main_litedramcore_inti_p1_ras_n = 1'd1; -reg main_litedramcore_inti_p1_we_n = 1'd1; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; wire main_litedramcore_inti_p1_cke; wire main_litedramcore_inti_p1_odt; wire main_litedramcore_inti_p1_reset_n; -reg main_litedramcore_inti_p1_act_n = 1'd1; +reg main_litedramcore_inti_p1_act_n = 1'd1; wire [63:0] main_litedramcore_inti_p1_wrdata; wire main_litedramcore_inti_p1_wrdata_en; wire [7:0] main_litedramcore_inti_p1_wrdata_mask; wire main_litedramcore_inti_p1_rddata_en; -reg [63:0] main_litedramcore_inti_p1_rddata = 64'd0; -reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_inti_p1_rddata = 64'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; wire [14:0] main_litedramcore_inti_p2_address; wire [2:0] main_litedramcore_inti_p2_bank; -reg main_litedramcore_inti_p2_cas_n = 1'd1; -reg main_litedramcore_inti_p2_cs_n = 1'd1; -reg main_litedramcore_inti_p2_ras_n = 1'd1; -reg main_litedramcore_inti_p2_we_n = 1'd1; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; wire main_litedramcore_inti_p2_cke; wire main_litedramcore_inti_p2_odt; wire main_litedramcore_inti_p2_reset_n; -reg main_litedramcore_inti_p2_act_n = 1'd1; +reg main_litedramcore_inti_p2_act_n = 1'd1; wire [63:0] main_litedramcore_inti_p2_wrdata; wire main_litedramcore_inti_p2_wrdata_en; wire [7:0] main_litedramcore_inti_p2_wrdata_mask; wire main_litedramcore_inti_p2_rddata_en; -reg [63:0] main_litedramcore_inti_p2_rddata = 64'd0; -reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_inti_p2_rddata = 64'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; wire [14:0] main_litedramcore_inti_p3_address; wire [2:0] main_litedramcore_inti_p3_bank; -reg main_litedramcore_inti_p3_cas_n = 1'd1; -reg main_litedramcore_inti_p3_cs_n = 1'd1; -reg main_litedramcore_inti_p3_ras_n = 1'd1; -reg main_litedramcore_inti_p3_we_n = 1'd1; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; wire main_litedramcore_inti_p3_cke; wire main_litedramcore_inti_p3_odt; wire main_litedramcore_inti_p3_reset_n; -reg main_litedramcore_inti_p3_act_n = 1'd1; +reg main_litedramcore_inti_p3_act_n = 1'd1; wire [63:0] main_litedramcore_inti_p3_wrdata; wire main_litedramcore_inti_p3_wrdata_en; wire [7:0] main_litedramcore_inti_p3_wrdata_mask; wire main_litedramcore_inti_p3_rddata_en; -reg [63:0] main_litedramcore_inti_p3_rddata = 64'd0; -reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_inti_p3_rddata = 64'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p0_address; wire [2:0] main_litedramcore_slave_p0_bank; wire main_litedramcore_slave_p0_cas_n; @@ -753,8 +775,8 @@ wire [63:0] main_litedramcore_slave_p0_wrdata; wire main_litedramcore_slave_p0_wrdata_en; wire [7:0] main_litedramcore_slave_p0_wrdata_mask; wire main_litedramcore_slave_p0_rddata_en; -reg [63:0] main_litedramcore_slave_p0_rddata = 64'd0; -reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_slave_p0_rddata = 64'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p1_address; wire [2:0] main_litedramcore_slave_p1_bank; wire main_litedramcore_slave_p1_cas_n; @@ -769,8 +791,8 @@ wire [63:0] main_litedramcore_slave_p1_wrdata; wire main_litedramcore_slave_p1_wrdata_en; wire [7:0] main_litedramcore_slave_p1_wrdata_mask; wire main_litedramcore_slave_p1_rddata_en; -reg [63:0] main_litedramcore_slave_p1_rddata = 64'd0; -reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_slave_p1_rddata = 64'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p2_address; wire [2:0] main_litedramcore_slave_p2_bank; wire main_litedramcore_slave_p2_cas_n; @@ -785,8 +807,8 @@ wire [63:0] main_litedramcore_slave_p2_wrdata; wire main_litedramcore_slave_p2_wrdata_en; wire [7:0] main_litedramcore_slave_p2_wrdata_mask; wire main_litedramcore_slave_p2_rddata_en; -reg [63:0] main_litedramcore_slave_p2_rddata = 64'd0; -reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +reg [63:0] main_litedramcore_slave_p2_rddata = 64'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p3_address; wire [2:0] main_litedramcore_slave_p3_bank; wire main_litedramcore_slave_p3_cas_n; @@ -801,138 +823,138 @@ wire [63:0] main_litedramcore_slave_p3_wrdata; wire main_litedramcore_slave_p3_wrdata_en; wire [7:0] main_litedramcore_slave_p3_wrdata_mask; wire main_litedramcore_slave_p3_rddata_en; -reg [63:0] main_litedramcore_slave_p3_rddata = 64'd0; -reg main_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] main_litedramcore_master_p0_address = 15'd0; -reg [2:0] main_litedramcore_master_p0_bank = 3'd0; -reg main_litedramcore_master_p0_cas_n = 1'd1; -reg main_litedramcore_master_p0_cs_n = 1'd1; -reg main_litedramcore_master_p0_ras_n = 1'd1; -reg main_litedramcore_master_p0_we_n = 1'd1; -reg main_litedramcore_master_p0_cke = 1'd0; -reg main_litedramcore_master_p0_odt = 1'd0; -reg main_litedramcore_master_p0_reset_n = 1'd0; -reg main_litedramcore_master_p0_act_n = 1'd1; -reg [63:0] main_litedramcore_master_p0_wrdata = 64'd0; -reg main_litedramcore_master_p0_wrdata_en = 1'd0; -reg [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0; -reg main_litedramcore_master_p0_rddata_en = 1'd0; +reg [63:0] main_litedramcore_slave_p3_rddata = 64'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] main_litedramcore_master_p0_address = 15'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p0_wrdata = 64'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p0_wrdata_mask = 8'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; wire [63:0] main_litedramcore_master_p0_rddata; wire main_litedramcore_master_p0_rddata_valid; -reg [14:0] main_litedramcore_master_p1_address = 15'd0; -reg [2:0] main_litedramcore_master_p1_bank = 3'd0; -reg main_litedramcore_master_p1_cas_n = 1'd1; -reg main_litedramcore_master_p1_cs_n = 1'd1; -reg main_litedramcore_master_p1_ras_n = 1'd1; -reg main_litedramcore_master_p1_we_n = 1'd1; -reg main_litedramcore_master_p1_cke = 1'd0; -reg main_litedramcore_master_p1_odt = 1'd0; -reg main_litedramcore_master_p1_reset_n = 1'd0; -reg main_litedramcore_master_p1_act_n = 1'd1; -reg [63:0] main_litedramcore_master_p1_wrdata = 64'd0; -reg main_litedramcore_master_p1_wrdata_en = 1'd0; -reg [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0; -reg main_litedramcore_master_p1_rddata_en = 1'd0; +reg [14:0] main_litedramcore_master_p1_address = 15'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p1_wrdata = 64'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p1_wrdata_mask = 8'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; wire [63:0] main_litedramcore_master_p1_rddata; wire main_litedramcore_master_p1_rddata_valid; -reg [14:0] main_litedramcore_master_p2_address = 15'd0; -reg [2:0] main_litedramcore_master_p2_bank = 3'd0; -reg main_litedramcore_master_p2_cas_n = 1'd1; -reg main_litedramcore_master_p2_cs_n = 1'd1; -reg main_litedramcore_master_p2_ras_n = 1'd1; -reg main_litedramcore_master_p2_we_n = 1'd1; -reg main_litedramcore_master_p2_cke = 1'd0; -reg main_litedramcore_master_p2_odt = 1'd0; -reg main_litedramcore_master_p2_reset_n = 1'd0; -reg main_litedramcore_master_p2_act_n = 1'd1; -reg [63:0] main_litedramcore_master_p2_wrdata = 64'd0; -reg main_litedramcore_master_p2_wrdata_en = 1'd0; -reg [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0; -reg main_litedramcore_master_p2_rddata_en = 1'd0; +reg [14:0] main_litedramcore_master_p2_address = 15'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p2_wrdata = 64'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p2_wrdata_mask = 8'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; wire [63:0] main_litedramcore_master_p2_rddata; wire main_litedramcore_master_p2_rddata_valid; -reg [14:0] main_litedramcore_master_p3_address = 15'd0; -reg [2:0] main_litedramcore_master_p3_bank = 3'd0; -reg main_litedramcore_master_p3_cas_n = 1'd1; -reg main_litedramcore_master_p3_cs_n = 1'd1; -reg main_litedramcore_master_p3_ras_n = 1'd1; -reg main_litedramcore_master_p3_we_n = 1'd1; -reg main_litedramcore_master_p3_cke = 1'd0; -reg main_litedramcore_master_p3_odt = 1'd0; -reg main_litedramcore_master_p3_reset_n = 1'd0; -reg main_litedramcore_master_p3_act_n = 1'd1; -reg [63:0] main_litedramcore_master_p3_wrdata = 64'd0; -reg main_litedramcore_master_p3_wrdata_en = 1'd0; -reg [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0; -reg main_litedramcore_master_p3_rddata_en = 1'd0; +reg [14:0] main_litedramcore_master_p3_address = 15'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [63:0] main_litedramcore_master_p3_wrdata = 64'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [7:0] main_litedramcore_master_p3_wrdata_mask = 8'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; wire [63:0] main_litedramcore_master_p3_rddata; wire main_litedramcore_master_p3_rddata_valid; wire main_litedramcore_sel; wire main_litedramcore_cke; wire main_litedramcore_odt; wire main_litedramcore_reset_n; -reg [3:0] main_litedramcore_storage = 4'd1; -reg main_litedramcore_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; -reg main_litedramcore_phaseinjector0_command_re = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector0_command_issue_r; -reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; -reg main_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0; -reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector0_rddata_status = 64'd0; wire main_litedramcore_phaseinjector0_rddata_we; -reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; -reg main_litedramcore_phaseinjector1_command_re = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector1_command_issue_r; -reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; -reg main_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0; -reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector1_rddata_status = 64'd0; wire main_litedramcore_phaseinjector1_rddata_we; -reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; -reg main_litedramcore_phaseinjector2_command_re = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector2_command_issue_r; -reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; -reg main_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0; -reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector2_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector2_rddata_status = 64'd0; wire main_litedramcore_phaseinjector2_rddata_we; -reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; -reg main_litedramcore_phaseinjector3_command_re = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector3_command_issue_r; -reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; -reg main_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0; -reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector3_wrdata_storage = 64'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [63:0] main_litedramcore_phaseinjector3_rddata_status = 64'd0; wire main_litedramcore_phaseinjector3_rddata_we; -reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; wire main_litedramcore_interface_bank0_valid; wire main_litedramcore_interface_bank0_ready; wire main_litedramcore_interface_bank0_we; @@ -989,131 +1011,131 @@ wire [21:0] main_litedramcore_interface_bank7_addr; wire main_litedramcore_interface_bank7_lock; wire main_litedramcore_interface_bank7_wdata_ready; wire main_litedramcore_interface_bank7_rdata_valid; -reg [255:0] main_litedramcore_interface_wdata = 256'd0; -reg [31:0] main_litedramcore_interface_wdata_we = 32'd0; +reg [255:0] main_litedramcore_interface_wdata = 256'd0; +reg [31:0] main_litedramcore_interface_wdata_we = 32'd0; wire [255:0] main_litedramcore_interface_rdata; -reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; -reg main_litedramcore_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_dfi_p0_ras_n = 1'd1; -reg main_litedramcore_dfi_p0_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; wire main_litedramcore_dfi_p0_cke; wire main_litedramcore_dfi_p0_odt; wire main_litedramcore_dfi_p0_reset_n; -reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg main_litedramcore_dfi_p0_act_n = 1'd1; wire [63:0] main_litedramcore_dfi_p0_wrdata; -reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; wire [7:0] main_litedramcore_dfi_p0_wrdata_mask; -reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; wire [63:0] main_litedramcore_dfi_p0_rddata; wire main_litedramcore_dfi_p0_rddata_valid; -reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; -reg main_litedramcore_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_dfi_p1_ras_n = 1'd1; -reg main_litedramcore_dfi_p1_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; wire main_litedramcore_dfi_p1_cke; wire main_litedramcore_dfi_p1_odt; wire main_litedramcore_dfi_p1_reset_n; -reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg main_litedramcore_dfi_p1_act_n = 1'd1; wire [63:0] main_litedramcore_dfi_p1_wrdata; -reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; wire [7:0] main_litedramcore_dfi_p1_wrdata_mask; -reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; wire [63:0] main_litedramcore_dfi_p1_rddata; wire main_litedramcore_dfi_p1_rddata_valid; -reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; -reg main_litedramcore_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_dfi_p2_ras_n = 1'd1; -reg main_litedramcore_dfi_p2_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; wire main_litedramcore_dfi_p2_cke; wire main_litedramcore_dfi_p2_odt; wire main_litedramcore_dfi_p2_reset_n; -reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg main_litedramcore_dfi_p2_act_n = 1'd1; wire [63:0] main_litedramcore_dfi_p2_wrdata; -reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; wire [7:0] main_litedramcore_dfi_p2_wrdata_mask; -reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; wire [63:0] main_litedramcore_dfi_p2_rddata; wire main_litedramcore_dfi_p2_rddata_valid; -reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; -reg main_litedramcore_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_dfi_p3_ras_n = 1'd1; -reg main_litedramcore_dfi_p3_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; wire main_litedramcore_dfi_p3_cke; wire main_litedramcore_dfi_p3_odt; wire main_litedramcore_dfi_p3_reset_n; -reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg main_litedramcore_dfi_p3_act_n = 1'd1; wire [63:0] main_litedramcore_dfi_p3_wrdata; -reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; wire [7:0] main_litedramcore_dfi_p3_wrdata_mask; -reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; wire [63:0] main_litedramcore_dfi_p3_rddata; wire main_litedramcore_dfi_p3_rddata_valid; -reg main_litedramcore_cmd_valid = 1'd0; -reg main_litedramcore_cmd_ready = 1'd0; -reg main_litedramcore_cmd_last = 1'd0; -reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; -reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; -reg main_litedramcore_cmd_payload_cas = 1'd0; -reg main_litedramcore_cmd_payload_ras = 1'd0; -reg main_litedramcore_cmd_payload_we = 1'd0; -reg main_litedramcore_cmd_payload_is_read = 1'd0; -reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; wire main_litedramcore_wants_refresh; wire main_litedramcore_wants_zqcs; wire main_litedramcore_timer_wait; wire main_litedramcore_timer_done0; wire [9:0] main_litedramcore_timer_count0; wire main_litedramcore_timer_done1; -reg [9:0] main_litedramcore_timer_count1 = 10'd781; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; wire main_litedramcore_postponer_req_i; -reg main_litedramcore_postponer_req_o = 1'd0; -reg main_litedramcore_postponer_count = 1'd0; -reg main_litedramcore_sequencer_start0 = 1'd0; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; wire main_litedramcore_sequencer_done0; wire main_litedramcore_sequencer_start1; -reg main_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] main_litedramcore_sequencer_counter = 6'd0; -reg main_litedramcore_sequencer_count = 1'd0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; wire main_litedramcore_zqcs_timer_wait; wire main_litedramcore_zqcs_timer_done0; wire [26:0] main_litedramcore_zqcs_timer_count0; wire main_litedramcore_zqcs_timer_done1; -reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg main_litedramcore_zqcs_executer_start = 1'd0; -reg main_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; wire main_litedramcore_bankmachine0_req_valid; wire main_litedramcore_bankmachine0_req_ready; wire main_litedramcore_bankmachine0_req_we; wire [21:0] main_litedramcore_bankmachine0_req_addr; wire main_litedramcore_bankmachine0_req_lock; -reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine0_refresh_req; -reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; -reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; @@ -1128,11 +1150,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; @@ -1153,51 +1175,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; -reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; wire main_litedramcore_bankmachine0_row_hit; -reg main_litedramcore_bankmachine0_row_open = 1'd0; -reg main_litedramcore_bankmachine0_row_close = 1'd0; -reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; wire main_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; wire main_litedramcore_bankmachine1_req_valid; wire main_litedramcore_bankmachine1_req_ready; wire main_litedramcore_bankmachine1_req_we; wire [21:0] main_litedramcore_bankmachine1_req_addr; wire main_litedramcore_bankmachine1_req_lock; -reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine1_refresh_req; -reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; -reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; @@ -1212,11 +1234,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; @@ -1237,51 +1259,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; -reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; wire main_litedramcore_bankmachine1_row_hit; -reg main_litedramcore_bankmachine1_row_open = 1'd0; -reg main_litedramcore_bankmachine1_row_close = 1'd0; -reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; wire main_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; wire main_litedramcore_bankmachine2_req_valid; wire main_litedramcore_bankmachine2_req_ready; wire main_litedramcore_bankmachine2_req_we; wire [21:0] main_litedramcore_bankmachine2_req_addr; wire main_litedramcore_bankmachine2_req_lock; -reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine2_refresh_req; -reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; -reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; @@ -1296,11 +1318,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; @@ -1321,51 +1343,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; -reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; wire main_litedramcore_bankmachine2_row_hit; -reg main_litedramcore_bankmachine2_row_open = 1'd0; -reg main_litedramcore_bankmachine2_row_close = 1'd0; -reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; wire main_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; wire main_litedramcore_bankmachine3_req_valid; wire main_litedramcore_bankmachine3_req_ready; wire main_litedramcore_bankmachine3_req_we; wire [21:0] main_litedramcore_bankmachine3_req_addr; wire main_litedramcore_bankmachine3_req_lock; -reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine3_refresh_req; -reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; -reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; @@ -1380,11 +1402,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; @@ -1405,51 +1427,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; -reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; wire main_litedramcore_bankmachine3_row_hit; -reg main_litedramcore_bankmachine3_row_open = 1'd0; -reg main_litedramcore_bankmachine3_row_close = 1'd0; -reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; wire main_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; wire main_litedramcore_bankmachine4_req_valid; wire main_litedramcore_bankmachine4_req_ready; wire main_litedramcore_bankmachine4_req_we; wire [21:0] main_litedramcore_bankmachine4_req_addr; wire main_litedramcore_bankmachine4_req_lock; -reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine4_refresh_req; -reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; -reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; @@ -1464,11 +1486,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; @@ -1489,51 +1511,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; -reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; wire main_litedramcore_bankmachine4_row_hit; -reg main_litedramcore_bankmachine4_row_open = 1'd0; -reg main_litedramcore_bankmachine4_row_close = 1'd0; -reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; wire main_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; wire main_litedramcore_bankmachine5_req_valid; wire main_litedramcore_bankmachine5_req_ready; wire main_litedramcore_bankmachine5_req_we; wire [21:0] main_litedramcore_bankmachine5_req_addr; wire main_litedramcore_bankmachine5_req_lock; -reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine5_refresh_req; -reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; -reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; @@ -1548,11 +1570,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; @@ -1573,51 +1595,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; -reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; wire main_litedramcore_bankmachine5_row_hit; -reg main_litedramcore_bankmachine5_row_open = 1'd0; -reg main_litedramcore_bankmachine5_row_close = 1'd0; -reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; wire main_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; wire main_litedramcore_bankmachine6_req_valid; wire main_litedramcore_bankmachine6_req_ready; wire main_litedramcore_bankmachine6_req_we; wire [21:0] main_litedramcore_bankmachine6_req_addr; wire main_litedramcore_bankmachine6_req_lock; -reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine6_refresh_req; -reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; -reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; @@ -1632,11 +1654,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; @@ -1657,51 +1679,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; -reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; wire main_litedramcore_bankmachine6_row_hit; -reg main_litedramcore_bankmachine6_row_open = 1'd0; -reg main_litedramcore_bankmachine6_row_close = 1'd0; -reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; wire main_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; wire main_litedramcore_bankmachine7_req_valid; wire main_litedramcore_bankmachine7_req_ready; wire main_litedramcore_bankmachine7_req_we; wire [21:0] main_litedramcore_bankmachine7_req_addr; wire main_litedramcore_bankmachine7_req_lock; -reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine7_refresh_req; -reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; -reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; @@ -1716,11 +1738,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; @@ -1741,107 +1763,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; -reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; wire main_litedramcore_bankmachine7_row_hit; -reg main_litedramcore_bankmachine7_row_open = 1'd0; -reg main_litedramcore_bankmachine7_row_close = 1'd0; -reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; wire main_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; wire main_litedramcore_ras_allowed; wire main_litedramcore_cas_allowed; wire [1:0] main_litedramcore_rdcmdphase; wire [1:0] main_litedramcore_wrcmdphase; -reg main_litedramcore_choose_cmd_want_reads = 1'd0; -reg main_litedramcore_choose_cmd_want_writes = 1'd0; -reg main_litedramcore_choose_cmd_want_cmds = 1'd0; -reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; wire main_litedramcore_choose_cmd_cmd_valid; -reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; -reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; wire main_litedramcore_choose_cmd_cmd_payload_is_read; wire main_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; wire [7:0] main_litedramcore_choose_cmd_request; -reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; wire main_litedramcore_choose_cmd_ce; -reg main_litedramcore_choose_req_want_reads = 1'd0; -reg main_litedramcore_choose_req_want_writes = 1'd0; -reg main_litedramcore_choose_req_want_cmds = 1'd0; -reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; wire main_litedramcore_choose_req_cmd_valid; -reg main_litedramcore_choose_req_cmd_ready = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; wire [14:0] main_litedramcore_choose_req_cmd_payload_a; wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; -reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; wire main_litedramcore_choose_req_cmd_payload_is_cmd; wire main_litedramcore_choose_req_cmd_payload_is_read; wire main_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; wire [7:0] main_litedramcore_choose_req_request; -reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; wire main_litedramcore_choose_req_ce; -reg [14:0] main_litedramcore_nop_a = 15'd0; -reg [2:0] main_litedramcore_nop_ba = 3'd0; -reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; -reg main_litedramcore_steerer0 = 1'd1; -reg main_litedramcore_steerer1 = 1'd1; -reg main_litedramcore_steerer2 = 1'd1; -reg main_litedramcore_steerer3 = 1'd1; -reg main_litedramcore_steerer4 = 1'd1; -reg main_litedramcore_steerer5 = 1'd1; -reg main_litedramcore_steerer6 = 1'd1; -reg main_litedramcore_steerer7 = 1'd1; +reg [14:0] main_litedramcore_nop_a = 15'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; wire main_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; -reg main_litedramcore_trrdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; wire main_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; wire [2:0] main_litedramcore_tfawcon_count; -reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; wire main_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; -reg main_litedramcore_tccdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; wire main_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; wire main_litedramcore_read_available; wire main_litedramcore_write_available; -reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en0 = 1'd0; wire main_litedramcore_max_time0; -reg [4:0] main_litedramcore_time0 = 5'd0; -reg main_litedramcore_en1 = 1'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; wire main_litedramcore_max_time1; -reg [3:0] main_litedramcore_time1 = 4'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; wire main_litedramcore_go_to_refresh; -reg main_init_done_storage = 1'd0; -reg main_init_done_re = 1'd0; -reg main_init_error_storage = 1'd0; -reg main_init_error_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; wire [29:0] main_wb_bus_adr; wire [31:0] main_wb_bus_dat_w; wire [31:0] main_wb_bus_dat_r; @@ -1853,6 +1875,7 @@ wire main_wb_bus_we; wire [2:0] main_wb_bus_cti; wire [1:0] main_wb_bus_bte; wire main_wb_bus_err; +wire main_user_enable; wire main_user_port_cmd_valid; wire main_user_port_cmd_ready; wire main_user_port_cmd_payload_we; @@ -1873,26 +1896,26 @@ wire builder_reset5; wire builder_reset6; wire builder_reset7; wire builder_pll_fb; -reg [1:0] builder_refresher_state = 2'd0; -reg [1:0] builder_refresher_next_state = 2'd0; -reg [3:0] builder_bankmachine0_state = 4'd0; -reg [3:0] builder_bankmachine0_next_state = 4'd0; -reg [3:0] builder_bankmachine1_state = 4'd0; -reg [3:0] builder_bankmachine1_next_state = 4'd0; -reg [3:0] builder_bankmachine2_state = 4'd0; -reg [3:0] builder_bankmachine2_next_state = 4'd0; -reg [3:0] builder_bankmachine3_state = 4'd0; -reg [3:0] builder_bankmachine3_next_state = 4'd0; -reg [3:0] builder_bankmachine4_state = 4'd0; -reg [3:0] builder_bankmachine4_next_state = 4'd0; -reg [3:0] builder_bankmachine5_state = 4'd0; -reg [3:0] builder_bankmachine5_next_state = 4'd0; -reg [3:0] builder_bankmachine6_state = 4'd0; -reg [3:0] builder_bankmachine6_next_state = 4'd0; -reg [3:0] builder_bankmachine7_state = 4'd0; -reg [3:0] builder_bankmachine7_next_state = 4'd0; -reg [3:0] builder_multiplexer_state = 4'd0; -reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; wire builder_roundrobin0_request; wire builder_roundrobin0_grant; wire builder_roundrobin0_ce; @@ -1917,493 +1940,285 @@ wire builder_roundrobin6_ce; wire builder_roundrobin7_request; wire builder_roundrobin7_grant; wire builder_roundrobin7_ce; -reg builder_locked0 = 1'd0; -reg builder_locked1 = 1'd0; -reg builder_locked2 = 1'd0; -reg builder_locked3 = 1'd0; -reg builder_locked4 = 1'd0; -reg builder_locked5 = 1'd0; -reg builder_locked6 = 1'd0; -reg builder_locked7 = 1'd0; -reg builder_new_master_wdata_ready0 = 1'd0; -reg builder_new_master_wdata_ready1 = 1'd0; -reg builder_new_master_rdata_valid0 = 1'd0; -reg builder_new_master_rdata_valid1 = 1'd0; -reg builder_new_master_rdata_valid2 = 1'd0; -reg builder_new_master_rdata_valid3 = 1'd0; -reg builder_new_master_rdata_valid4 = 1'd0; -reg builder_new_master_rdata_valid5 = 1'd0; -reg builder_new_master_rdata_valid6 = 1'd0; -reg builder_new_master_rdata_valid7 = 1'd0; -reg builder_new_master_rdata_valid8 = 1'd0; -reg [13:0] builder_litedramcore_adr = 14'd0; -reg builder_litedramcore_we = 1'd0; -reg [7:0] builder_litedramcore_dat_w = 8'd0; -wire [7:0] builder_litedramcore_dat_r; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [31:0] builder_litedramcore_dat_w = 32'd0; +wire [31:0] builder_litedramcore_dat_r; wire [29:0] builder_litedramcore_wishbone_adr; wire [31:0] builder_litedramcore_wishbone_dat_w; -reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; wire [3:0] builder_litedramcore_wishbone_sel; wire builder_litedramcore_wishbone_cyc; wire builder_litedramcore_wishbone_stb; -reg builder_litedramcore_wishbone_ack = 1'd0; +reg builder_litedramcore_wishbone_ack = 1'd0; wire builder_litedramcore_wishbone_we; wire [2:0] builder_litedramcore_wishbone_cti; wire [1:0] builder_litedramcore_wishbone_bte; -reg builder_litedramcore_wishbone_err = 1'd0; +reg builder_litedramcore_wishbone_err = 1'd0; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; -wire [7:0] builder_interface0_bank_bus_dat_w; -reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; -reg builder_csrbank0_init_done0_re = 1'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +reg builder_csrbank0_init_done0_re = 1'd0; wire builder_csrbank0_init_done0_r; -reg builder_csrbank0_init_done0_we = 1'd0; +reg builder_csrbank0_init_done0_we = 1'd0; wire builder_csrbank0_init_done0_w; -reg builder_csrbank0_init_error0_re = 1'd0; +reg builder_csrbank0_init_error0_re = 1'd0; wire builder_csrbank0_init_error0_r; -reg builder_csrbank0_init_error0_we = 1'd0; +reg builder_csrbank0_init_error0_we = 1'd0; wire builder_csrbank0_init_error0_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; -wire [7:0] builder_interface1_bank_bus_dat_w; -reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; -reg builder_csrbank1_rst0_re = 1'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +reg builder_csrbank1_rst0_re = 1'd0; wire builder_csrbank1_rst0_r; -reg builder_csrbank1_rst0_we = 1'd0; +reg builder_csrbank1_rst0_we = 1'd0; wire builder_csrbank1_rst0_w; -reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_r; -reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_w; -reg builder_csrbank1_wlevel_en0_re = 1'd0; +reg builder_csrbank1_wlevel_en0_re = 1'd0; wire builder_csrbank1_wlevel_en0_r; -reg builder_csrbank1_wlevel_en0_we = 1'd0; +reg builder_csrbank1_wlevel_en0_we = 1'd0; wire builder_csrbank1_wlevel_en0_w; -reg builder_csrbank1_dly_sel0_re = 1'd0; +reg builder_csrbank1_dly_sel0_re = 1'd0; wire [3:0] builder_csrbank1_dly_sel0_r; -reg builder_csrbank1_dly_sel0_we = 1'd0; +reg builder_csrbank1_dly_sel0_we = 1'd0; wire [3:0] builder_csrbank1_dly_sel0_w; -reg builder_csrbank1_rdphase0_re = 1'd0; +reg builder_csrbank1_rdphase0_re = 1'd0; wire [1:0] builder_csrbank1_rdphase0_r; -reg builder_csrbank1_rdphase0_we = 1'd0; +reg builder_csrbank1_rdphase0_we = 1'd0; wire [1:0] builder_csrbank1_rdphase0_w; -reg builder_csrbank1_wrphase0_re = 1'd0; +reg builder_csrbank1_wrphase0_re = 1'd0; wire [1:0] builder_csrbank1_wrphase0_r; -reg builder_csrbank1_wrphase0_we = 1'd0; +reg builder_csrbank1_wrphase0_we = 1'd0; wire [1:0] builder_csrbank1_wrphase0_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; -wire [7:0] builder_interface2_bank_bus_dat_w; -reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; -reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_r; -reg builder_csrbank2_dfii_control0_we = 1'd0; +reg builder_csrbank2_dfii_control0_we = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_w; -reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_r; -reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_w; -reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi0_address1_r; -reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi0_address1_w; -reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_r; -reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_w; -reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; -reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; -reg builder_csrbank2_dfii_pi0_wrdata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata7_r; -reg builder_csrbank2_dfii_pi0_wrdata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata7_w; -reg builder_csrbank2_dfii_pi0_wrdata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata6_r; -reg builder_csrbank2_dfii_pi0_wrdata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata6_w; -reg builder_csrbank2_dfii_pi0_wrdata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata5_r; -reg builder_csrbank2_dfii_pi0_wrdata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata5_w; -reg builder_csrbank2_dfii_pi0_wrdata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata4_r; -reg builder_csrbank2_dfii_pi0_wrdata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata4_w; -reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; -reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; -reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; -reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; -reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; -reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; -reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; -reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; -reg builder_csrbank2_dfii_pi0_rddata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata7_r; -reg builder_csrbank2_dfii_pi0_rddata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata7_w; -reg builder_csrbank2_dfii_pi0_rddata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata6_r; -reg builder_csrbank2_dfii_pi0_rddata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata6_w; -reg builder_csrbank2_dfii_pi0_rddata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata5_r; -reg builder_csrbank2_dfii_pi0_rddata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata5_w; -reg builder_csrbank2_dfii_pi0_rddata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata4_r; -reg builder_csrbank2_dfii_pi0_rddata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata4_w; -reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; -reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; -reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; -reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; -reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; -reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; -reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; -reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; -reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_r; +reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata1_w; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata1_r; +reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata1_w; +reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata0_r; +reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata0_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_r; -reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_w; -reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi1_address1_r; -reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi1_address1_w; -reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_r; -reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_w; -reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; -reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; -reg builder_csrbank2_dfii_pi1_wrdata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata7_r; -reg builder_csrbank2_dfii_pi1_wrdata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata7_w; -reg builder_csrbank2_dfii_pi1_wrdata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata6_r; -reg builder_csrbank2_dfii_pi1_wrdata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata6_w; -reg builder_csrbank2_dfii_pi1_wrdata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata5_r; -reg builder_csrbank2_dfii_pi1_wrdata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata5_w; -reg builder_csrbank2_dfii_pi1_wrdata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata4_r; -reg builder_csrbank2_dfii_pi1_wrdata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata4_w; -reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; -reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; -reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; -reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; -reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; -reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; -reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; -reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; -reg builder_csrbank2_dfii_pi1_rddata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata7_r; -reg builder_csrbank2_dfii_pi1_rddata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata7_w; -reg builder_csrbank2_dfii_pi1_rddata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata6_r; -reg builder_csrbank2_dfii_pi1_rddata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata6_w; -reg builder_csrbank2_dfii_pi1_rddata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata5_r; -reg builder_csrbank2_dfii_pi1_rddata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata5_w; -reg builder_csrbank2_dfii_pi1_rddata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata4_r; -reg builder_csrbank2_dfii_pi1_rddata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata4_w; -reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; -reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; -reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; -reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; -reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; -reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; -reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; -reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; -reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_r; +reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata1_w; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata1_r; +reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata1_w; +reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata0_r; +reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata0_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_r; -reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_w; -reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi2_address1_r; -reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi2_address1_w; -reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_r; -reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_w; -reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; -reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; -reg builder_csrbank2_dfii_pi2_wrdata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata7_r; -reg builder_csrbank2_dfii_pi2_wrdata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata7_w; -reg builder_csrbank2_dfii_pi2_wrdata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata6_r; -reg builder_csrbank2_dfii_pi2_wrdata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata6_w; -reg builder_csrbank2_dfii_pi2_wrdata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata5_r; -reg builder_csrbank2_dfii_pi2_wrdata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata5_w; -reg builder_csrbank2_dfii_pi2_wrdata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata4_r; -reg builder_csrbank2_dfii_pi2_wrdata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata4_w; -reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; -reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; -reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; -reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; -reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; -reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; -reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; -reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; -reg builder_csrbank2_dfii_pi2_rddata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata7_r; -reg builder_csrbank2_dfii_pi2_rddata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata7_w; -reg builder_csrbank2_dfii_pi2_rddata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata6_r; -reg builder_csrbank2_dfii_pi2_rddata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata6_w; -reg builder_csrbank2_dfii_pi2_rddata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata5_r; -reg builder_csrbank2_dfii_pi2_rddata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata5_w; -reg builder_csrbank2_dfii_pi2_rddata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata4_r; -reg builder_csrbank2_dfii_pi2_rddata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata4_w; -reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; -reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; -reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; -reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; -reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; -reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; -reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; -reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; -reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_r; +reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata1_w; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata1_r; +reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata1_w; +reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata0_r; +reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata0_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_r; -reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_w; -reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi3_address1_r; -reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi3_address1_w; -reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_r; -reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_w; -reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; -reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; -reg builder_csrbank2_dfii_pi3_wrdata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata7_r; -reg builder_csrbank2_dfii_pi3_wrdata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata7_w; -reg builder_csrbank2_dfii_pi3_wrdata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata6_r; -reg builder_csrbank2_dfii_pi3_wrdata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata6_w; -reg builder_csrbank2_dfii_pi3_wrdata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata5_r; -reg builder_csrbank2_dfii_pi3_wrdata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata5_w; -reg builder_csrbank2_dfii_pi3_wrdata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata4_r; -reg builder_csrbank2_dfii_pi3_wrdata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata4_w; -reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; -reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; -reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; -reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; -reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; -reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; -reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; -reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; -reg builder_csrbank2_dfii_pi3_rddata7_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata7_r; -reg builder_csrbank2_dfii_pi3_rddata7_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata7_w; -reg builder_csrbank2_dfii_pi3_rddata6_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata6_r; -reg builder_csrbank2_dfii_pi3_rddata6_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata6_w; -reg builder_csrbank2_dfii_pi3_rddata5_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata5_r; -reg builder_csrbank2_dfii_pi3_rddata5_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata5_w; -reg builder_csrbank2_dfii_pi3_rddata4_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata4_r; -reg builder_csrbank2_dfii_pi3_rddata4_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata4_w; -reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; -reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; -reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; -reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; -reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; -reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; -reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; -reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_r; +reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata1_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata1_r; +reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata1_w; +reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata0_r; +reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata0_w; wire builder_csrbank2_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; -wire [7:0] builder_csr_interconnect_dat_w; -wire [7:0] builder_csr_interconnect_dat_r; -reg [1:0] builder_state = 2'd0; -reg [1:0] builder_next_state = 2'd0; -reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; -reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; -reg builder_litedramcore_adr_next_value_ce1 = 1'd0; -reg builder_litedramcore_we_next_value2 = 1'd0; -reg builder_litedramcore_we_next_value_ce2 = 1'd0; -reg builder_rhs_array_muxed0 = 1'd0; -reg [14:0] builder_rhs_array_muxed1 = 15'd0; -reg [2:0] builder_rhs_array_muxed2 = 3'd0; -reg builder_rhs_array_muxed3 = 1'd0; -reg builder_rhs_array_muxed4 = 1'd0; -reg builder_rhs_array_muxed5 = 1'd0; -reg builder_t_array_muxed0 = 1'd0; -reg builder_t_array_muxed1 = 1'd0; -reg builder_t_array_muxed2 = 1'd0; -reg builder_rhs_array_muxed6 = 1'd0; -reg [14:0] builder_rhs_array_muxed7 = 15'd0; -reg [2:0] builder_rhs_array_muxed8 = 3'd0; -reg builder_rhs_array_muxed9 = 1'd0; -reg builder_rhs_array_muxed10 = 1'd0; -reg builder_rhs_array_muxed11 = 1'd0; -reg builder_t_array_muxed3 = 1'd0; -reg builder_t_array_muxed4 = 1'd0; -reg builder_t_array_muxed5 = 1'd0; -reg [21:0] builder_rhs_array_muxed12 = 22'd0; -reg builder_rhs_array_muxed13 = 1'd0; -reg builder_rhs_array_muxed14 = 1'd0; -reg [21:0] builder_rhs_array_muxed15 = 22'd0; -reg builder_rhs_array_muxed16 = 1'd0; -reg builder_rhs_array_muxed17 = 1'd0; -reg [21:0] builder_rhs_array_muxed18 = 22'd0; -reg builder_rhs_array_muxed19 = 1'd0; -reg builder_rhs_array_muxed20 = 1'd0; -reg [21:0] builder_rhs_array_muxed21 = 22'd0; -reg builder_rhs_array_muxed22 = 1'd0; -reg builder_rhs_array_muxed23 = 1'd0; -reg [21:0] builder_rhs_array_muxed24 = 22'd0; -reg builder_rhs_array_muxed25 = 1'd0; -reg builder_rhs_array_muxed26 = 1'd0; -reg [21:0] builder_rhs_array_muxed27 = 22'd0; -reg builder_rhs_array_muxed28 = 1'd0; -reg builder_rhs_array_muxed29 = 1'd0; -reg [21:0] builder_rhs_array_muxed30 = 22'd0; -reg builder_rhs_array_muxed31 = 1'd0; -reg builder_rhs_array_muxed32 = 1'd0; -reg [21:0] builder_rhs_array_muxed33 = 22'd0; -reg builder_rhs_array_muxed34 = 1'd0; -reg builder_rhs_array_muxed35 = 1'd0; -reg [2:0] builder_array_muxed0 = 3'd0; -reg [14:0] builder_array_muxed1 = 15'd0; -reg builder_array_muxed2 = 1'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg builder_array_muxed6 = 1'd0; -reg [2:0] builder_array_muxed7 = 3'd0; -reg [14:0] builder_array_muxed8 = 15'd0; -reg builder_array_muxed9 = 1'd0; -reg builder_array_muxed10 = 1'd0; -reg builder_array_muxed11 = 1'd0; -reg builder_array_muxed12 = 1'd0; -reg builder_array_muxed13 = 1'd0; -reg [2:0] builder_array_muxed14 = 3'd0; -reg [14:0] builder_array_muxed15 = 15'd0; -reg builder_array_muxed16 = 1'd0; -reg builder_array_muxed17 = 1'd0; -reg builder_array_muxed18 = 1'd0; -reg builder_array_muxed19 = 1'd0; -reg builder_array_muxed20 = 1'd0; -reg [2:0] builder_array_muxed21 = 3'd0; -reg [14:0] builder_array_muxed22 = 15'd0; -reg builder_array_muxed23 = 1'd0; -reg builder_array_muxed24 = 1'd0; -reg builder_array_muxed25 = 1'd0; -reg builder_array_muxed26 = 1'd0; -reg builder_array_muxed27 = 1'd0; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [14:0] builder_rhs_array_muxed1 = 15'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [14:0] builder_rhs_array_muxed7 = 15'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [21:0] builder_rhs_array_muxed12 = 22'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [21:0] builder_rhs_array_muxed15 = 22'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [21:0] builder_rhs_array_muxed18 = 22'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [21:0] builder_rhs_array_muxed21 = 22'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [21:0] builder_rhs_array_muxed24 = 22'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [21:0] builder_rhs_array_muxed27 = 22'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [21:0] builder_rhs_array_muxed30 = 22'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [21:0] builder_rhs_array_muxed33 = 22'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [14:0] builder_array_muxed1 = 15'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [14:0] builder_array_muxed8 = 15'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [14:0] builder_array_muxed15 = 15'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [14:0] builder_array_muxed22 = 15'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl1; @@ -2415,10 +2230,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl3_expr; -// synthesis translate_off -reg dummy_s; -initial dummy_s <= 1'd0; -// synthesis translate_on +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + assign init_done = main_init_done_storage; assign init_error = main_init_error_storage; assign main_wb_bus_adr = wb_ctrl_adr; @@ -2434,18 +2249,19 @@ assign main_wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; -assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; -assign main_reset = rst; +assign main_reset = (rst | main_rst); assign pll_locked = main_locked; assign main_clkin = clk; assign iodelay_clk = main_clkout_buf0; @@ -2454,10 +2270,6 @@ assign sys4x_clk = main_clkout_buf2; assign sys4x_dqs_clk = main_clkout_buf3; assign main_k7ddrphy_dqs_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dqs_oe) | main_k7ddrphy_dqs_postamble); assign main_k7ddrphy_dq_oe_delay_tappeddelayline = ((main_k7ddrphy_dqs_preamble | main_k7ddrphy_dq_oe) | main_k7ddrphy_dqs_postamble); - -// synthesis translate_off -reg dummy_d; -// synthesis translate_on always @(*) begin main_k7ddrphy_dfi_p0_rddata <= 64'd0; main_k7ddrphy_dfi_p0_rddata[0] <= main_k7ddrphy_bitslip04[0]; @@ -2524,14 +2336,7 @@ always @(*) begin main_k7ddrphy_dfi_p0_rddata[62] <= main_k7ddrphy_bitslip302[1]; main_k7ddrphy_dfi_p0_rddata[31] <= main_k7ddrphy_bitslip312[0]; main_k7ddrphy_dfi_p0_rddata[63] <= main_k7ddrphy_bitslip312[1]; -// synthesis translate_off - dummy_d = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_1; -// synthesis translate_on always @(*) begin main_k7ddrphy_dfi_p1_rddata <= 64'd0; main_k7ddrphy_dfi_p1_rddata[0] <= main_k7ddrphy_bitslip04[2]; @@ -2598,14 +2403,7 @@ always @(*) begin main_k7ddrphy_dfi_p1_rddata[62] <= main_k7ddrphy_bitslip302[3]; main_k7ddrphy_dfi_p1_rddata[31] <= main_k7ddrphy_bitslip312[2]; main_k7ddrphy_dfi_p1_rddata[63] <= main_k7ddrphy_bitslip312[3]; -// synthesis translate_off - dummy_d_1 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_2; -// synthesis translate_on always @(*) begin main_k7ddrphy_dfi_p2_rddata <= 64'd0; main_k7ddrphy_dfi_p2_rddata[0] <= main_k7ddrphy_bitslip04[4]; @@ -2672,14 +2470,7 @@ always @(*) begin main_k7ddrphy_dfi_p2_rddata[62] <= main_k7ddrphy_bitslip302[5]; main_k7ddrphy_dfi_p2_rddata[31] <= main_k7ddrphy_bitslip312[4]; main_k7ddrphy_dfi_p2_rddata[63] <= main_k7ddrphy_bitslip312[5]; -// synthesis translate_off - dummy_d_2 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_3; -// synthesis translate_on always @(*) begin main_k7ddrphy_dfi_p3_rddata <= 64'd0; main_k7ddrphy_dfi_p3_rddata[0] <= main_k7ddrphy_bitslip04[6]; @@ -2746,19 +2537,12 @@ always @(*) begin main_k7ddrphy_dfi_p3_rddata[62] <= main_k7ddrphy_bitslip302[7]; main_k7ddrphy_dfi_p3_rddata[31] <= main_k7ddrphy_bitslip312[6]; main_k7ddrphy_dfi_p3_rddata[63] <= main_k7ddrphy_bitslip312[7]; -// synthesis translate_off - dummy_d_3 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_dfi_p0_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); assign main_k7ddrphy_dfi_p1_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); assign main_k7ddrphy_dfi_p2_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); assign main_k7ddrphy_dfi_p3_rddata_valid = (main_k7ddrphy_rddata_en_tappeddelayline7 | main_k7ddrphy_wlevel_en_storage); assign main_k7ddrphy_dq_oe = main_k7ddrphy_wrdata_en_tappeddelayline1; - -// synthesis translate_off -reg dummy_d_4; -// synthesis translate_on always @(*) begin main_k7ddrphy_dqs_oe <= 1'd0; if (main_k7ddrphy_wlevel_en_storage) begin @@ -2766,16 +2550,9 @@ always @(*) begin end else begin main_k7ddrphy_dqs_oe <= main_k7ddrphy_dq_oe; end -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_dqs_preamble = (main_k7ddrphy_wrdata_en_tappeddelayline0 & (~main_k7ddrphy_wrdata_en_tappeddelayline1)); assign main_k7ddrphy_dqs_postamble = (main_k7ddrphy_wrdata_en_tappeddelayline2 & (~main_k7ddrphy_wrdata_en_tappeddelayline1)); - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on always @(*) begin main_k7ddrphy_dqspattern_o <= 8'd0; main_k7ddrphy_dqspattern_o <= 7'd85; @@ -2791,14 +2568,7 @@ always @(*) begin main_k7ddrphy_dqspattern_o <= 1'd1; end end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip00 <= 8'd0; case (main_k7ddrphy_bitslip0_value0) @@ -2827,14 +2597,7 @@ always @(*) begin main_k7ddrphy_bitslip00 <= main_k7ddrphy_bitslip0_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip10 <= 8'd0; case (main_k7ddrphy_bitslip1_value0) @@ -2863,14 +2626,7 @@ always @(*) begin main_k7ddrphy_bitslip10 <= main_k7ddrphy_bitslip1_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip20 <= 8'd0; case (main_k7ddrphy_bitslip2_value0) @@ -2899,14 +2655,7 @@ always @(*) begin main_k7ddrphy_bitslip20 <= main_k7ddrphy_bitslip2_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip30 <= 8'd0; case (main_k7ddrphy_bitslip3_value0) @@ -2935,14 +2684,7 @@ always @(*) begin main_k7ddrphy_bitslip30 <= main_k7ddrphy_bitslip3_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip01 <= 8'd0; case (main_k7ddrphy_bitslip0_value1) @@ -2971,14 +2713,7 @@ always @(*) begin main_k7ddrphy_bitslip01 <= main_k7ddrphy_bitslip0_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip11 <= 8'd0; case (main_k7ddrphy_bitslip1_value1) @@ -3007,14 +2742,7 @@ always @(*) begin main_k7ddrphy_bitslip11 <= main_k7ddrphy_bitslip1_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip21 <= 8'd0; case (main_k7ddrphy_bitslip2_value1) @@ -3043,14 +2771,7 @@ always @(*) begin main_k7ddrphy_bitslip21 <= main_k7ddrphy_bitslip2_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip31 <= 8'd0; case (main_k7ddrphy_bitslip3_value1) @@ -3079,14 +2800,7 @@ always @(*) begin main_k7ddrphy_bitslip31 <= main_k7ddrphy_bitslip3_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip02 <= 8'd0; case (main_k7ddrphy_bitslip0_value2) @@ -3115,14 +2829,7 @@ always @(*) begin main_k7ddrphy_bitslip02 <= main_k7ddrphy_bitslip0_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip04 <= 8'd0; case (main_k7ddrphy_bitslip0_value3) @@ -3151,14 +2858,7 @@ always @(*) begin main_k7ddrphy_bitslip04 <= main_k7ddrphy_bitslip0_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip12 <= 8'd0; case (main_k7ddrphy_bitslip1_value2) @@ -3187,14 +2887,7 @@ always @(*) begin main_k7ddrphy_bitslip12 <= main_k7ddrphy_bitslip1_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip14 <= 8'd0; case (main_k7ddrphy_bitslip1_value3) @@ -3223,14 +2916,7 @@ always @(*) begin main_k7ddrphy_bitslip14 <= main_k7ddrphy_bitslip1_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_18; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip22 <= 8'd0; case (main_k7ddrphy_bitslip2_value2) @@ -3259,14 +2945,7 @@ always @(*) begin main_k7ddrphy_bitslip22 <= main_k7ddrphy_bitslip2_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_18 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_19; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip24 <= 8'd0; case (main_k7ddrphy_bitslip2_value3) @@ -3295,14 +2974,7 @@ always @(*) begin main_k7ddrphy_bitslip24 <= main_k7ddrphy_bitslip2_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_19 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_20; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip32 <= 8'd0; case (main_k7ddrphy_bitslip3_value2) @@ -3331,14 +3003,7 @@ always @(*) begin main_k7ddrphy_bitslip32 <= main_k7ddrphy_bitslip3_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_20 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_21; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip34 <= 8'd0; case (main_k7ddrphy_bitslip3_value3) @@ -3367,14 +3032,7 @@ always @(*) begin main_k7ddrphy_bitslip34 <= main_k7ddrphy_bitslip3_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_21 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip40 <= 8'd0; case (main_k7ddrphy_bitslip4_value0) @@ -3403,14 +3061,7 @@ always @(*) begin main_k7ddrphy_bitslip40 <= main_k7ddrphy_bitslip4_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip42 <= 8'd0; case (main_k7ddrphy_bitslip4_value1) @@ -3439,14 +3090,7 @@ always @(*) begin main_k7ddrphy_bitslip42 <= main_k7ddrphy_bitslip4_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip50 <= 8'd0; case (main_k7ddrphy_bitslip5_value0) @@ -3475,14 +3119,7 @@ always @(*) begin main_k7ddrphy_bitslip50 <= main_k7ddrphy_bitslip5_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip52 <= 8'd0; case (main_k7ddrphy_bitslip5_value1) @@ -3511,14 +3148,7 @@ always @(*) begin main_k7ddrphy_bitslip52 <= main_k7ddrphy_bitslip5_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_26; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip60 <= 8'd0; case (main_k7ddrphy_bitslip6_value0) @@ -3547,14 +3177,7 @@ always @(*) begin main_k7ddrphy_bitslip60 <= main_k7ddrphy_bitslip6_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip62 <= 8'd0; case (main_k7ddrphy_bitslip6_value1) @@ -3583,14 +3206,7 @@ always @(*) begin main_k7ddrphy_bitslip62 <= main_k7ddrphy_bitslip6_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip70 <= 8'd0; case (main_k7ddrphy_bitslip7_value0) @@ -3619,14 +3235,7 @@ always @(*) begin main_k7ddrphy_bitslip70 <= main_k7ddrphy_bitslip7_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip72 <= 8'd0; case (main_k7ddrphy_bitslip7_value1) @@ -3655,14 +3264,7 @@ always @(*) begin main_k7ddrphy_bitslip72 <= main_k7ddrphy_bitslip7_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip80 <= 8'd0; case (main_k7ddrphy_bitslip8_value0) @@ -3691,14 +3293,7 @@ always @(*) begin main_k7ddrphy_bitslip80 <= main_k7ddrphy_bitslip8_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_30 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_31; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip82 <= 8'd0; case (main_k7ddrphy_bitslip8_value1) @@ -3727,14 +3322,7 @@ always @(*) begin main_k7ddrphy_bitslip82 <= main_k7ddrphy_bitslip8_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_31 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_32; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip90 <= 8'd0; case (main_k7ddrphy_bitslip9_value0) @@ -3763,14 +3351,7 @@ always @(*) begin main_k7ddrphy_bitslip90 <= main_k7ddrphy_bitslip9_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_32 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_33; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip92 <= 8'd0; case (main_k7ddrphy_bitslip9_value1) @@ -3799,14 +3380,7 @@ always @(*) begin main_k7ddrphy_bitslip92 <= main_k7ddrphy_bitslip9_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_33 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_34; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip100 <= 8'd0; case (main_k7ddrphy_bitslip10_value0) @@ -3835,14 +3409,7 @@ always @(*) begin main_k7ddrphy_bitslip100 <= main_k7ddrphy_bitslip10_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_34 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_35; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip102 <= 8'd0; case (main_k7ddrphy_bitslip10_value1) @@ -3871,14 +3438,7 @@ always @(*) begin main_k7ddrphy_bitslip102 <= main_k7ddrphy_bitslip10_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_35 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_36; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip110 <= 8'd0; case (main_k7ddrphy_bitslip11_value0) @@ -3907,14 +3467,7 @@ always @(*) begin main_k7ddrphy_bitslip110 <= main_k7ddrphy_bitslip11_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_36 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_37; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip112 <= 8'd0; case (main_k7ddrphy_bitslip11_value1) @@ -3943,14 +3496,7 @@ always @(*) begin main_k7ddrphy_bitslip112 <= main_k7ddrphy_bitslip11_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_37 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_38; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip120 <= 8'd0; case (main_k7ddrphy_bitslip12_value0) @@ -3979,14 +3525,7 @@ always @(*) begin main_k7ddrphy_bitslip120 <= main_k7ddrphy_bitslip12_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip122 <= 8'd0; case (main_k7ddrphy_bitslip12_value1) @@ -4015,14 +3554,7 @@ always @(*) begin main_k7ddrphy_bitslip122 <= main_k7ddrphy_bitslip12_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_39 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_40; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip130 <= 8'd0; case (main_k7ddrphy_bitslip13_value0) @@ -4051,14 +3583,7 @@ always @(*) begin main_k7ddrphy_bitslip130 <= main_k7ddrphy_bitslip13_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_40 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_41; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip132 <= 8'd0; case (main_k7ddrphy_bitslip13_value1) @@ -4087,14 +3612,7 @@ always @(*) begin main_k7ddrphy_bitslip132 <= main_k7ddrphy_bitslip13_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_41 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_42; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip140 <= 8'd0; case (main_k7ddrphy_bitslip14_value0) @@ -4123,14 +3641,7 @@ always @(*) begin main_k7ddrphy_bitslip140 <= main_k7ddrphy_bitslip14_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_42 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_43; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip142 <= 8'd0; case (main_k7ddrphy_bitslip14_value1) @@ -4159,14 +3670,7 @@ always @(*) begin main_k7ddrphy_bitslip142 <= main_k7ddrphy_bitslip14_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_43 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_44; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip150 <= 8'd0; case (main_k7ddrphy_bitslip15_value0) @@ -4195,14 +3699,7 @@ always @(*) begin main_k7ddrphy_bitslip150 <= main_k7ddrphy_bitslip15_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_44 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_45; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip152 <= 8'd0; case (main_k7ddrphy_bitslip15_value1) @@ -4231,14 +3728,7 @@ always @(*) begin main_k7ddrphy_bitslip152 <= main_k7ddrphy_bitslip15_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_45 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_46; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip160 <= 8'd0; case (main_k7ddrphy_bitslip16_value0) @@ -4267,14 +3757,7 @@ always @(*) begin main_k7ddrphy_bitslip160 <= main_k7ddrphy_bitslip16_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_46 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_47; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip162 <= 8'd0; case (main_k7ddrphy_bitslip16_value1) @@ -4303,14 +3786,7 @@ always @(*) begin main_k7ddrphy_bitslip162 <= main_k7ddrphy_bitslip16_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_47 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_48; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip170 <= 8'd0; case (main_k7ddrphy_bitslip17_value0) @@ -4339,14 +3815,7 @@ always @(*) begin main_k7ddrphy_bitslip170 <= main_k7ddrphy_bitslip17_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_48 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_49; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip172 <= 8'd0; case (main_k7ddrphy_bitslip17_value1) @@ -4375,14 +3844,7 @@ always @(*) begin main_k7ddrphy_bitslip172 <= main_k7ddrphy_bitslip17_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_49 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_50; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip180 <= 8'd0; case (main_k7ddrphy_bitslip18_value0) @@ -4411,14 +3873,7 @@ always @(*) begin main_k7ddrphy_bitslip180 <= main_k7ddrphy_bitslip18_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_50 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_51; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip182 <= 8'd0; case (main_k7ddrphy_bitslip18_value1) @@ -4447,14 +3902,7 @@ always @(*) begin main_k7ddrphy_bitslip182 <= main_k7ddrphy_bitslip18_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_51 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_52; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip190 <= 8'd0; case (main_k7ddrphy_bitslip19_value0) @@ -4483,14 +3931,7 @@ always @(*) begin main_k7ddrphy_bitslip190 <= main_k7ddrphy_bitslip19_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_52 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_53; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip192 <= 8'd0; case (main_k7ddrphy_bitslip19_value1) @@ -4519,14 +3960,7 @@ always @(*) begin main_k7ddrphy_bitslip192 <= main_k7ddrphy_bitslip19_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_53 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_54; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip200 <= 8'd0; case (main_k7ddrphy_bitslip20_value0) @@ -4555,14 +3989,7 @@ always @(*) begin main_k7ddrphy_bitslip200 <= main_k7ddrphy_bitslip20_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_54 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_55; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip202 <= 8'd0; case (main_k7ddrphy_bitslip20_value1) @@ -4591,14 +4018,7 @@ always @(*) begin main_k7ddrphy_bitslip202 <= main_k7ddrphy_bitslip20_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_55 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_56; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip210 <= 8'd0; case (main_k7ddrphy_bitslip21_value0) @@ -4627,14 +4047,7 @@ always @(*) begin main_k7ddrphy_bitslip210 <= main_k7ddrphy_bitslip21_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_56 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_57; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip212 <= 8'd0; case (main_k7ddrphy_bitslip21_value1) @@ -4663,14 +4076,7 @@ always @(*) begin main_k7ddrphy_bitslip212 <= main_k7ddrphy_bitslip21_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_57 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_58; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip220 <= 8'd0; case (main_k7ddrphy_bitslip22_value0) @@ -4699,14 +4105,7 @@ always @(*) begin main_k7ddrphy_bitslip220 <= main_k7ddrphy_bitslip22_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_58 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_59; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip222 <= 8'd0; case (main_k7ddrphy_bitslip22_value1) @@ -4735,14 +4134,7 @@ always @(*) begin main_k7ddrphy_bitslip222 <= main_k7ddrphy_bitslip22_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_59 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_60; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip230 <= 8'd0; case (main_k7ddrphy_bitslip23_value0) @@ -4771,14 +4163,7 @@ always @(*) begin main_k7ddrphy_bitslip230 <= main_k7ddrphy_bitslip23_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_60 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_61; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip232 <= 8'd0; case (main_k7ddrphy_bitslip23_value1) @@ -4807,14 +4192,7 @@ always @(*) begin main_k7ddrphy_bitslip232 <= main_k7ddrphy_bitslip23_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_61 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_62; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip240 <= 8'd0; case (main_k7ddrphy_bitslip24_value0) @@ -4843,14 +4221,7 @@ always @(*) begin main_k7ddrphy_bitslip240 <= main_k7ddrphy_bitslip24_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_62 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_63; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip242 <= 8'd0; case (main_k7ddrphy_bitslip24_value1) @@ -4879,14 +4250,7 @@ always @(*) begin main_k7ddrphy_bitslip242 <= main_k7ddrphy_bitslip24_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_63 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_64; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip250 <= 8'd0; case (main_k7ddrphy_bitslip25_value0) @@ -4915,14 +4279,7 @@ always @(*) begin main_k7ddrphy_bitslip250 <= main_k7ddrphy_bitslip25_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_64 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_65; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip252 <= 8'd0; case (main_k7ddrphy_bitslip25_value1) @@ -4951,14 +4308,7 @@ always @(*) begin main_k7ddrphy_bitslip252 <= main_k7ddrphy_bitslip25_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_65 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_66; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip260 <= 8'd0; case (main_k7ddrphy_bitslip26_value0) @@ -4987,14 +4337,7 @@ always @(*) begin main_k7ddrphy_bitslip260 <= main_k7ddrphy_bitslip26_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_66 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_67; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip262 <= 8'd0; case (main_k7ddrphy_bitslip26_value1) @@ -5023,14 +4366,7 @@ always @(*) begin main_k7ddrphy_bitslip262 <= main_k7ddrphy_bitslip26_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_67 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_68; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip270 <= 8'd0; case (main_k7ddrphy_bitslip27_value0) @@ -5059,14 +4395,7 @@ always @(*) begin main_k7ddrphy_bitslip270 <= main_k7ddrphy_bitslip27_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_68 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_69; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip272 <= 8'd0; case (main_k7ddrphy_bitslip27_value1) @@ -5095,14 +4424,7 @@ always @(*) begin main_k7ddrphy_bitslip272 <= main_k7ddrphy_bitslip27_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_69 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_70; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip280 <= 8'd0; case (main_k7ddrphy_bitslip28_value0) @@ -5131,14 +4453,7 @@ always @(*) begin main_k7ddrphy_bitslip280 <= main_k7ddrphy_bitslip28_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_70 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_71; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip282 <= 8'd0; case (main_k7ddrphy_bitslip28_value1) @@ -5167,14 +4482,7 @@ always @(*) begin main_k7ddrphy_bitslip282 <= main_k7ddrphy_bitslip28_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_71 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_72; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip290 <= 8'd0; case (main_k7ddrphy_bitslip29_value0) @@ -5203,14 +4511,7 @@ always @(*) begin main_k7ddrphy_bitslip290 <= main_k7ddrphy_bitslip29_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_72 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_73; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip292 <= 8'd0; case (main_k7ddrphy_bitslip29_value1) @@ -5239,14 +4540,7 @@ always @(*) begin main_k7ddrphy_bitslip292 <= main_k7ddrphy_bitslip29_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_73 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_74; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip300 <= 8'd0; case (main_k7ddrphy_bitslip30_value0) @@ -5275,14 +4569,7 @@ always @(*) begin main_k7ddrphy_bitslip300 <= main_k7ddrphy_bitslip30_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip302 <= 8'd0; case (main_k7ddrphy_bitslip30_value1) @@ -5311,14 +4598,7 @@ always @(*) begin main_k7ddrphy_bitslip302 <= main_k7ddrphy_bitslip30_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_75 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_76; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip310 <= 8'd0; case (main_k7ddrphy_bitslip31_value0) @@ -5347,14 +4627,7 @@ always @(*) begin main_k7ddrphy_bitslip310 <= main_k7ddrphy_bitslip31_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_76 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_77; -// synthesis translate_on always @(*) begin main_k7ddrphy_bitslip312 <= 8'd0; case (main_k7ddrphy_bitslip31_value1) @@ -5383,9 +4656,6 @@ always @(*) begin main_k7ddrphy_bitslip312 <= main_k7ddrphy_bitslip31_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_77 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; assign main_k7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; @@ -5515,10 +4785,14 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_ assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; - -// synthesis translate_off -reg dummy_d_78; -// synthesis translate_on +always @(*) begin + main_litedramcore_master_p0_wrdata_mask <= 8'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; + end else begin + main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; + end +end always @(*) begin main_litedramcore_master_p0_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -5526,14 +4800,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end -// synthesis translate_off - dummy_d_78 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_79; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_address <= 15'd0; if (main_litedramcore_sel) begin @@ -5541,14 +4808,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end -// synthesis translate_off - dummy_d_79 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_80; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -5556,14 +4816,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end -// synthesis translate_off - dummy_d_80 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_81; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5571,14 +4824,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end -// synthesis translate_off - dummy_d_81 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_82; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5586,14 +4832,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end -// synthesis translate_off - dummy_d_82 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_83; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5601,28 +4840,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end -// synthesis translate_off - dummy_d_83 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_84; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata <= 64'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end -// synthesis translate_off - dummy_d_84 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_85; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5630,28 +4855,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end -// synthesis translate_off - dummy_d_85 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_86; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_86 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_87; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -5659,14 +4870,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end -// synthesis translate_off - dummy_d_87 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_88; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -5674,14 +4878,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end -// synthesis translate_off - dummy_d_88 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_89; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -5689,14 +4886,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end -// synthesis translate_off - dummy_d_89 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_90; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5704,14 +4894,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end -// synthesis translate_off - dummy_d_90 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_91; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata <= 64'd0; if (main_litedramcore_sel) begin @@ -5719,28 +4902,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end -// synthesis translate_off - dummy_d_91 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_92; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata <= 64'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end -// synthesis translate_off - dummy_d_92 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_93; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -5748,28 +4917,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end -// synthesis translate_off - dummy_d_93 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_94; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end -// synthesis translate_off - dummy_d_94 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_95; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_mask <= 8'd0; if (main_litedramcore_sel) begin @@ -5777,14 +4932,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end -// synthesis translate_off - dummy_d_95 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_96; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -5792,14 +4940,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_address <= 15'd0; if (main_litedramcore_sel) begin @@ -5807,14 +4948,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end -// synthesis translate_off - dummy_d_97 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_98; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -5822,14 +4956,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end -// synthesis translate_off - dummy_d_98 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_99; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5837,14 +4964,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end -// synthesis translate_off - dummy_d_99 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_100; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5852,14 +4972,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end -// synthesis translate_off - dummy_d_100 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_101; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5867,28 +4980,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_101 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_102; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata <= 64'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end -// synthesis translate_off - dummy_d_102 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_103; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5896,28 +4995,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end -// synthesis translate_off - dummy_d_103 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_104; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_104 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_105; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -5925,14 +5010,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end -// synthesis translate_off - dummy_d_105 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_106; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -5940,14 +5018,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end -// synthesis translate_off - dummy_d_106 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_107; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -5955,14 +5026,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end -// synthesis translate_off - dummy_d_107 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_108; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -5970,14 +5034,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end -// synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata <= 64'd0; if (main_litedramcore_sel) begin @@ -5985,28 +5042,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end -// synthesis translate_off - dummy_d_109 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_110; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_rddata <= 64'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end -// synthesis translate_off - dummy_d_110 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_111; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -6014,28 +5057,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end -// synthesis translate_off - dummy_d_111 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_112; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end -// synthesis translate_off - dummy_d_112 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_113; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_mask <= 8'd0; if (main_litedramcore_sel) begin @@ -6043,14 +5072,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end -// synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -6058,14 +5080,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end -// synthesis translate_off - dummy_d_114 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_115; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_address <= 15'd0; if (main_litedramcore_sel) begin @@ -6073,14 +5088,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end -// synthesis translate_off - dummy_d_115 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_116; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -6088,14 +5096,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end -// synthesis translate_off - dummy_d_116 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_117; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6103,14 +5104,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end -// synthesis translate_off - dummy_d_117 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_118; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6118,14 +5112,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end -// synthesis translate_off - dummy_d_118 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_119; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6133,28 +5120,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata <= 64'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6162,28 +5135,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -6191,14 +5150,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -6206,14 +5158,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end -// synthesis translate_off - dummy_d_124 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_125; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -6221,14 +5166,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end -// synthesis translate_off - dummy_d_125 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_126; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6236,14 +5174,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata <= 64'd0; if (main_litedramcore_sel) begin @@ -6251,28 +5182,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end -// synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_rddata <= 64'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -6280,28 +5197,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end -// synthesis translate_off - dummy_d_130 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_131; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_mask <= 8'd0; if (main_litedramcore_sel) begin @@ -6309,28 +5212,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end -// synthesis translate_off - dummy_d_131 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_132; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p1_rddata <= 64'd0; - if (main_litedramcore_sel) begin - end else begin - main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; - end -// synthesis translate_off - dummy_d_132 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_133; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -6338,43 +5220,22 @@ always @(*) begin end else begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; end -// synthesis translate_off - dummy_d_133 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_134; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p1_rddata_valid <= 1'd0; + main_litedramcore_master_p0_address <= 15'd0; if (main_litedramcore_sel) begin + main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end else begin - main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; + main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end -// synthesis translate_off - dummy_d_134 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_135; -// synthesis translate_on always @(*) begin - main_litedramcore_master_p0_address <= 15'd0; + main_litedramcore_inti_p1_rddata <= 64'd0; if (main_litedramcore_sel) begin - main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address; end else begin - main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; + main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end -// synthesis translate_off - dummy_d_135 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_136; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -6382,14 +5243,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end -// synthesis translate_off - dummy_d_136 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_137; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6397,14 +5251,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6412,14 +5259,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end -// synthesis translate_off - dummy_d_138 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_139; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6427,28 +5267,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata <= 64'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end -// synthesis translate_off - dummy_d_140 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_141; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6456,28 +5282,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end -// synthesis translate_off - dummy_d_141 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_142; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_142 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_143; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -6485,14 +5297,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end -// synthesis translate_off - dummy_d_143 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_144; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p1_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; + end +end always @(*) begin main_litedramcore_master_p0_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -6500,14 +5312,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end -// synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -6515,14 +5320,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end -// synthesis translate_off - dummy_d_145 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_146; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -6530,14 +5328,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end -// synthesis translate_off - dummy_d_146 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_147; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata <= 64'd0; if (main_litedramcore_sel) begin @@ -6545,14 +5336,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -6560,24 +5344,6 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end -// synthesis translate_off - dummy_d_148 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_149; -// synthesis translate_on -always @(*) begin - main_litedramcore_master_p0_wrdata_mask <= 8'd0; - if (main_litedramcore_sel) begin - main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask; - end else begin - main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; - end -// synthesis translate_off - dummy_d_149 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; @@ -6591,10 +5357,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; - -// synthesis translate_off -reg dummy_d_150; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); + end else begin + main_litedramcore_inti_p0_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p0_we_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -6602,14 +5372,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_150 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_151; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_cas_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -6617,14 +5380,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_151 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_152; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_cs_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -6632,24 +5388,6 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p0_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); - end else begin - main_litedramcore_inti_p0_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; @@ -6657,10 +5395,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); + end else begin + main_litedramcore_inti_p1_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p1_we_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -6668,14 +5410,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_cas_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -6683,14 +5418,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_155 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_156; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_cs_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -6698,24 +5426,6 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_156 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_157; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p1_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); - end else begin - main_litedramcore_inti_p1_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; @@ -6723,10 +5433,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); + end else begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p2_we_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -6734,14 +5448,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_158 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_159; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -6749,14 +5456,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_159 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_160; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_cs_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -6764,24 +5464,6 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_160 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_161; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p2_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); - end else begin - main_litedramcore_inti_p2_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; @@ -6789,25 +5471,22 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_inti_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); + end else begin + main_litedramcore_inti_p3_ras_n <= 1'd1; + end +end +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); end else begin main_litedramcore_inti_p3_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_162 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_163; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_cas_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -6815,14 +5494,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_163 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_164; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_cs_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -6830,24 +5502,6 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_164 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_165; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p3_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); - end else begin - main_litedramcore_inti_p3_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_165 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; @@ -6924,10 +5578,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_166; -// synthesis translate_on always @(*) begin builder_refresher_next_state <= 2'd0; builder_refresher_next_state <= builder_refresher_state; @@ -6959,119 +5609,88 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_166 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_167; -// synthesis translate_on always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; + main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end end 2'd3: begin end default: begin end endcase -// synthesis translate_off - dummy_d_167 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_168; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) 1'd1: begin - main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin end else begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_cmd_last <= 1'd1; end end default: begin end endcase -// synthesis translate_off - dummy_d_168 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_169; -// synthesis translate_on always @(*) begin - main_litedramcore_zqcs_executer_start <= 1'd0; + main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - if (main_litedramcore_sequencer_done0) begin - if (main_litedramcore_wants_zqcs) begin - main_litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end end 2'd3: begin end default: begin end endcase -// synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_last <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin end else begin - main_litedramcore_cmd_last <= 1'd1; + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_last <= 1'd1; + main_litedramcore_cmd_valid <= 1'd0; end end default: begin end endcase -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; @@ -7087,10 +5706,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin @@ -7098,17 +5713,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin @@ -7116,9 +5724,6 @@ always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_172 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; @@ -7137,10 +5742,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_173; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin @@ -7148,9 +5749,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); @@ -7160,10 +5758,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on always @(*) begin builder_bankmachine0_next_state <= 4'd0; builder_bankmachine0_next_state <= builder_bankmachine0_state; @@ -7224,14 +5818,33 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_174 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_175; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (builder_bankmachine0_state) @@ -7272,14 +5885,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) @@ -7305,14 +5911,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_close <= 1'd0; case (builder_bankmachine0_state) @@ -7338,14 +5937,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_177 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_178; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (builder_bankmachine0_state) @@ -7380,14 +5972,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_178 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_179; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (builder_bankmachine0_state) @@ -7416,14 +6001,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_179 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_180; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (builder_bankmachine0_state) @@ -7464,14 +6042,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_180 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_181; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine0_state) @@ -7497,14 +6068,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_181 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_182; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine0_state) @@ -7534,14 +6098,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_182 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_183; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (builder_bankmachine0_state) @@ -7579,14 +6136,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_183 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_184; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (builder_bankmachine0_state) @@ -7624,14 +6174,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_184 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_185; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (builder_bankmachine0_state) @@ -7669,14 +6212,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_185 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_186; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (builder_bankmachine0_state) @@ -7714,42 +6250,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine0_twtpcon_ready) begin - main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; @@ -7765,10 +6265,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin @@ -7776,17 +6272,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin @@ -7794,9 +6283,6 @@ always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_189 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; @@ -7815,10 +6301,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_190; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin @@ -7826,9 +6308,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_190 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); @@ -7838,10 +6317,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_191; -// synthesis translate_on always @(*) begin builder_bankmachine1_next_state <= 4'd0; builder_bankmachine1_next_state <= builder_bankmachine1_state; @@ -7902,30 +6377,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7936,36 +6401,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_192 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_193; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -7983,10 +6435,7 @@ always @(*) begin if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine1_row_opened) begin if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; - end + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -7995,14 +6444,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_193 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_194; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_open <= 1'd0; case (builder_bankmachine1_state) @@ -8028,14 +6470,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_194 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_195; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_close <= 1'd0; case (builder_bankmachine1_state) @@ -8061,14 +6496,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_195 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_196; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (builder_bankmachine1_state) @@ -8103,14 +6531,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (builder_bankmachine1_state) @@ -8139,14 +6560,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_197 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_198; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (builder_bankmachine1_state) @@ -8187,14 +6601,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_198 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_199; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) @@ -8220,14 +6627,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_199 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_200; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine1_state) @@ -8257,14 +6657,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_200 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_201; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (builder_bankmachine1_state) @@ -8302,14 +6695,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_201 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_202; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (builder_bankmachine1_state) @@ -8347,14 +6733,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_202 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_203; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (builder_bankmachine1_state) @@ -8392,16 +6771,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end @@ -8410,9 +6782,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8423,11 +6792,23 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_204 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; @@ -8443,10 +6824,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_205; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin @@ -8454,17 +6831,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin @@ -8472,9 +6842,6 @@ always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_206 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; @@ -8493,10 +6860,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_207; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin @@ -8504,9 +6867,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); @@ -8516,10 +6876,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on always @(*) begin builder_bankmachine2_next_state <= 4'd0; builder_bankmachine2_next_state <= builder_bankmachine2_state; @@ -8580,14 +6936,33 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_208 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_209; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) @@ -8628,14 +7003,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_209 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_210; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) @@ -8661,14 +7029,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_210 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_211; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) @@ -8694,14 +7055,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_211 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_212; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) @@ -8736,73 +7090,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_212 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_213; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_213 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_214; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -8817,14 +7119,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_214 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_215; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) @@ -8865,14 +7160,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_215 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_216; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) @@ -8898,14 +7186,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_216 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_217; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) @@ -8935,14 +7216,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) @@ -8980,14 +7254,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_218 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_219; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) @@ -9025,14 +7292,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_219 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_220; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) @@ -9070,16 +7330,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_220 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_221; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -9088,9 +7341,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine2_twtpcon_ready) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9101,11 +7351,23 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_221 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; @@ -9121,10 +7383,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_222; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin @@ -9132,17 +7390,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin @@ -9150,9 +7401,6 @@ always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; @@ -9171,10 +7419,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin @@ -9182,9 +7426,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_224 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); @@ -9194,10 +7435,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_225; -// synthesis translate_on always @(*) begin builder_bankmachine3_next_state <= 4'd0; builder_bankmachine3_next_state <= builder_bankmachine3_state; @@ -9258,14 +7495,33 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (builder_bankmachine3_state) @@ -9306,14 +7562,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_open <= 1'd0; case (builder_bankmachine3_state) @@ -9339,14 +7588,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_227 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_228; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_close <= 1'd0; case (builder_bankmachine3_state) @@ -9372,14 +7614,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_228 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_229; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (builder_bankmachine3_state) @@ -9414,14 +7649,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_229 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_230; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (builder_bankmachine3_state) @@ -9450,14 +7678,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_230 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_231; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (builder_bankmachine3_state) @@ -9498,14 +7719,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_231 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_232; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) @@ -9531,14 +7745,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_232 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_233; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -9568,14 +7775,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_233 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_234; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (builder_bankmachine3_state) @@ -9613,14 +7813,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_234 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_235; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (builder_bankmachine3_state) @@ -9658,16 +7851,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_235 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_236; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin end @@ -9692,8 +7878,8 @@ always @(*) begin if (main_litedramcore_bankmachine3_row_opened) begin if (main_litedramcore_bankmachine3_row_hit) begin if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin - main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -9703,16 +7889,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_236 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_237; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin end @@ -9737,8 +7916,8 @@ always @(*) begin if (main_litedramcore_bankmachine3_row_opened) begin if (main_litedramcore_bankmachine3_row_hit) begin if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready; end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -9748,42 +7927,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine3_twtpcon_ready) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_238 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; @@ -9799,10 +7942,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_239; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin @@ -9810,17 +7949,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin @@ -9828,9 +7960,6 @@ always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_240 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; @@ -9849,10 +7978,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_241; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin @@ -9860,9 +7985,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); @@ -9872,10 +7994,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on always @(*) begin builder_bankmachine4_next_state <= 4'd0; builder_bankmachine4_next_state <= builder_bankmachine4_state; @@ -9936,30 +8054,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_242 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_243; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd0; + main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine4_twtpcon_ready) begin + main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9970,36 +8078,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_243 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_244; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -10017,10 +8112,7 @@ always @(*) begin if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine4_row_opened) begin if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; - end + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin @@ -10029,14 +8121,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_244 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_245; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_open <= 1'd0; case (builder_bankmachine4_state) @@ -10062,14 +8147,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_close <= 1'd0; case (builder_bankmachine4_state) @@ -10095,14 +8173,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_246 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_247; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (builder_bankmachine4_state) @@ -10137,14 +8208,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_247 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_248; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (builder_bankmachine4_state) @@ -10173,14 +8237,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_248 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_249; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (builder_bankmachine4_state) @@ -10221,14 +8278,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_249 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_250; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine4_state) @@ -10254,14 +8304,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_250 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_251; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine4_state) @@ -10291,14 +8334,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_251 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_252; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (builder_bankmachine4_state) @@ -10336,14 +8372,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_252 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_253; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (builder_bankmachine4_state) @@ -10381,14 +8410,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_253 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_254; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (builder_bankmachine4_state) @@ -10426,16 +8448,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_254 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_255; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin end @@ -10444,9 +8459,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine4_twtpcon_ready) begin - main_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -10457,11 +8469,23 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_255 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; @@ -10477,10 +8501,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_256; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin @@ -10488,17 +8508,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_256 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_257; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin @@ -10506,9 +8519,6 @@ always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_257 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; @@ -10527,10 +8537,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_258; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin @@ -10538,9 +8544,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_258 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); @@ -10550,10 +8553,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_259; -// synthesis translate_on always @(*) begin builder_bankmachine5_next_state <= 4'd0; builder_bankmachine5_next_state <= builder_bankmachine5_state; @@ -10614,14 +8613,33 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_259 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_260; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (builder_bankmachine5_state) @@ -10662,14 +8680,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_260 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_261; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_open <= 1'd0; case (builder_bankmachine5_state) @@ -10695,72 +8706,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_261 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_262; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine5_row_close <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_262 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_263; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine5_row_close <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; + main_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -10773,14 +8732,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_263 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_264; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (builder_bankmachine5_state) @@ -10815,14 +8767,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_264 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_265; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (builder_bankmachine5_state) @@ -10851,14 +8796,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_265 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_266; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (builder_bankmachine5_state) @@ -10899,14 +8837,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_266 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_267; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -10932,14 +8863,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_267 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_268; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine5_state) @@ -10969,14 +8893,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_268 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_269; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (builder_bankmachine5_state) @@ -11014,14 +8931,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_269 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_270; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (builder_bankmachine5_state) @@ -11059,14 +8969,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_270 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_271; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (builder_bankmachine5_state) @@ -11104,16 +9007,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_271 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_272; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -11122,9 +9018,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine5_twtpcon_ready) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -11135,11 +9028,23 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_272 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; @@ -11155,10 +9060,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; - -// synthesis translate_off -reg dummy_d_273; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin @@ -11166,17 +9067,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_273 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_274; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin @@ -11184,9 +9078,6 @@ always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_274 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; @@ -11205,10 +9096,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_275; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin @@ -11216,9 +9103,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_275 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); @@ -11228,10 +9112,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_276; -// synthesis translate_on always @(*) begin builder_bankmachine6_next_state <= 4'd0; builder_bankmachine6_next_state <= builder_bankmachine6_state; @@ -11292,14 +9172,33 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_276 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_277; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) @@ -11340,14 +9239,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_277 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_278; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) @@ -11373,14 +9265,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_278 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_279; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) @@ -11406,14 +9291,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_279 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_280; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) @@ -11448,14 +9326,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (builder_bankmachine6_state) @@ -11484,14 +9355,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) @@ -11532,14 +9396,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_282 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_283; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) @@ -11565,59 +9422,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_283 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_284; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_284 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_285; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) @@ -11647,14 +9452,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_285 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) @@ -11692,14 +9490,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) @@ -11737,14 +9528,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) @@ -11782,16 +9566,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -11800,9 +9577,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine6_twtpcon_ready) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -11813,11 +9587,23 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; @@ -11833,10 +9619,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin @@ -11844,17 +9626,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin @@ -11862,9 +9637,6 @@ always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; @@ -11883,10 +9655,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin @@ -11894,9 +9662,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); @@ -11906,10 +9671,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on always @(*) begin builder_bankmachine7_next_state <= 4'd0; builder_bankmachine7_next_state <= builder_bankmachine7_state; @@ -11970,14 +9731,33 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) @@ -12018,14 +9798,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_open <= 1'd0; case (builder_bankmachine7_state) @@ -12051,14 +9824,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) @@ -12084,14 +9850,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) @@ -12126,14 +9885,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) @@ -12162,14 +9914,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) @@ -12210,14 +9955,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) @@ -12243,14 +9981,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) @@ -12280,14 +10011,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) @@ -12325,14 +10049,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) @@ -12370,14 +10087,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) @@ -12415,14 +10125,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) @@ -12460,42 +10163,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine7_twtpcon_ready) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on end assign main_litedramcore_rdcmdphase = (main_k7ddrphy_rdphase_storage - 1'd1); assign main_litedramcore_wrcmdphase = (main_k7ddrphy_wrphase_storage - 1'd1); @@ -12527,10 +10194,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_valids <= 8'd0; main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); @@ -12541,9 +10204,6 @@ always @(*) begin main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; @@ -12552,49 +10212,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin @@ -12603,14 +10238,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin @@ -12619,14 +10247,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin @@ -12635,14 +10256,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin @@ -12651,14 +10265,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin @@ -12667,14 +10274,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin @@ -12683,14 +10283,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin @@ -12699,14 +10292,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin @@ -12715,15 +10301,8 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_valids <= 8'd0; main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); @@ -12734,9 +10313,6 @@ always @(*) begin main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; @@ -12745,44 +10321,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); assign main_litedramcore_dfi_p0_reset_n = 1'd1; @@ -12798,10 +10353,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1; assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on always @(*) begin builder_multiplexer_next_state <= 4'd0; builder_multiplexer_next_state <= builder_multiplexer_state; @@ -12858,14 +10409,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on +always @(*) begin + main_litedramcore_steerer_sel2 <= 2'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_steerer_sel2 <= 1'd0; + if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd2)) begin + main_litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end always @(*) begin main_litedramcore_choose_cmd_want_activates <= 1'd0; case (builder_multiplexer_state) @@ -12900,14 +10485,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel3 <= 2'd0; case (builder_multiplexer_state) @@ -12948,14 +10526,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on always @(*) begin main_litedramcore_en0 <= 1'd0; case (builder_multiplexer_state) @@ -12983,14 +10554,7 @@ always @(*) begin main_litedramcore_en0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -13025,14 +10589,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_want_reads <= 1'd0; case (builder_multiplexer_state) @@ -13060,14 +10617,7 @@ always @(*) begin main_litedramcore_choose_req_want_reads <= 1'd1; end endcase -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) @@ -13095,14 +10645,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -13139,14 +10682,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on always @(*) begin main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) @@ -13174,14 +10710,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel0 <= 2'd0; case (builder_multiplexer_state) @@ -13223,14 +10752,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on always @(*) begin main_litedramcore_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -13258,14 +10780,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel1 <= 2'd0; case (builder_multiplexer_state) @@ -13306,57 +10821,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on -always @(*) begin - main_litedramcore_steerer_sel2 <= 2'd0; - case (builder_multiplexer_state) - 1'd1: begin - main_litedramcore_steerer_sel2 <= 1'd0; - if ((main_k7ddrphy_wrphase_storage == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 2'd2; - end - if ((main_litedramcore_wrcmdphase == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - main_litedramcore_steerer_sel2 <= 1'd0; - if ((main_k7ddrphy_rdphase_storage == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 2'd2; - end - if ((main_litedramcore_rdcmdphase == 2'd2)) begin - main_litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); @@ -13401,41 +10865,27 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on always @(*) begin - main_litedramcore_interface_wdata_we <= 32'd0; + main_litedramcore_interface_wdata <= 256'd0; case ({builder_new_master_wdata_ready1}) 1'd1: begin - main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - main_litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on always @(*) begin - main_litedramcore_interface_wdata <= 256'd0; + main_litedramcore_interface_wdata_we <= 32'd0; case ({builder_new_master_wdata_ready1}) 1'd1: begin - main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - main_litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase -// synthesis translate_off - dummy_d_337 = dummy_s; -// synthesis translate_on end assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; assign builder_roundrobin0_grant = 1'd0; @@ -13446,10 +10896,6 @@ assign builder_roundrobin4_grant = 1'd0; assign builder_roundrobin5_grant = 1'd0; assign builder_roundrobin6_grant = 1'd0; assign builder_roundrobin7_grant = 1'd0; - -// synthesis translate_off -reg dummy_d_338; -// synthesis translate_on always @(*) begin builder_next_state <= 2'd0; builder_next_state <= builder_state; @@ -13466,173 +10912,114 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_338 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_339; -// synthesis translate_on always @(*) begin - builder_litedramcore_adr_next_value1 <= 14'd0; + builder_litedramcore_adr_next_value_ce1 <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_adr_next_value1 <= 1'd0; + builder_litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; + builder_litedramcore_adr_next_value_ce1 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_339 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_340; -// synthesis translate_on always @(*) begin - builder_litedramcore_adr_next_value_ce1 <= 1'd0; + builder_litedramcore_we_next_value2 <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_adr_next_value_ce1 <= 1'd1; + builder_litedramcore_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_adr_next_value_ce1 <= 1'd1; + builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); end end endcase -// synthesis translate_off - dummy_d_340 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_341; -// synthesis translate_on always @(*) begin - builder_litedramcore_we_next_value2 <= 1'd0; + builder_litedramcore_we_next_value_ce2 <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_we_next_value2 <= 1'd0; + builder_litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0)); + builder_litedramcore_we_next_value_ce2 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_341 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_342; -// synthesis translate_on always @(*) begin - builder_litedramcore_we_next_value_ce2 <= 1'd0; + builder_litedramcore_wishbone_ack <= 1'd0; case (builder_state) 1'd1: begin - builder_litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; end default: begin - if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin - builder_litedramcore_we_next_value_ce2 <= 1'd1; - end end endcase -// synthesis translate_off - dummy_d_342 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_343; -// synthesis translate_on always @(*) begin - builder_litedramcore_wishbone_dat_r <= 32'd0; + builder_litedramcore_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin end 2'd2: begin - builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; end default: begin + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_343 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_344; -// synthesis translate_on always @(*) begin - builder_litedramcore_wishbone_ack <= 1'd0; + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; case (builder_state) 1'd1: begin end 2'd2: begin - builder_litedramcore_wishbone_ack <= 1'd1; end default: begin + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_344 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_345; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value0 <= 8'd0; + builder_litedramcore_wishbone_dat_r <= 32'd0; case (builder_state) 1'd1: begin end 2'd2: begin + builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r; end default: begin - builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_345 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_346; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + builder_litedramcore_adr_next_value1 <= 14'd0; case (builder_state) 1'd1: begin + builder_litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; + if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin + builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr; + end end endcase -// synthesis translate_off - dummy_d_346 = dummy_s; -// synthesis translate_on end assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; @@ -13645,576 +11032,282 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we; assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; assign main_wb_bus_err = builder_litedramcore_wishbone_err; -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_347; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; + builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_347 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_348; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_we <= 1'd0; + builder_csrbank0_init_done0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_348 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_349; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_349 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_350; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_350 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_done0_w = main_init_done_storage; assign builder_csrbank0_init_error0_w = main_init_error_storage; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_351; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_351 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_352; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_352 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; - -// synthesis translate_off -reg dummy_d_353; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_353 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_354; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_354 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_355; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_355 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_356; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on always @(*) begin main_k7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_357 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_358; -// synthesis translate_on always @(*) begin main_k7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_358 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_359; -// synthesis translate_on always @(*) begin - main_k7ddrphy_cdly_rst_we <= 1'd0; + main_k7ddrphy_cdly_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_359 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_360; -// synthesis translate_on always @(*) begin - main_k7ddrphy_cdly_rst_re <= 1'd0; + main_k7ddrphy_cdly_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_k7ddrphy_cdly_rst_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_360 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_361; -// synthesis translate_on always @(*) begin - main_k7ddrphy_cdly_inc_we <= 1'd0; + main_k7ddrphy_cdly_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_361 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_362; -// synthesis translate_on always @(*) begin - main_k7ddrphy_cdly_inc_re <= 1'd0; + main_k7ddrphy_cdly_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_362 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0]; - -// synthesis translate_off -reg dummy_d_363; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_363 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_364; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_364 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_365; -// synthesis translate_on always @(*) begin main_k7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_365 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_366; -// synthesis translate_on always @(*) begin main_k7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_366 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_367; -// synthesis translate_on always @(*) begin - main_k7ddrphy_rdly_dq_inc_we <= 1'd0; + main_k7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_367 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_368; -// synthesis translate_on always @(*) begin - main_k7ddrphy_rdly_dq_inc_re <= 1'd0; + main_k7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_368 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_369; -// synthesis translate_on always @(*) begin - main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_369 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_370; -// synthesis translate_on always @(*) begin - main_k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_k7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_370 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_371; -// synthesis translate_on always @(*) begin - main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_371 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_372; -// synthesis translate_on always @(*) begin - main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_372 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_373; -// synthesis translate_on always @(*) begin main_k7ddrphy_wdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_373 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_374; -// synthesis translate_on always @(*) begin main_k7ddrphy_wdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_374 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_375; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dq_inc_re <= 1'd0; + main_k7ddrphy_wdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_375 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_376; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dq_inc_we <= 1'd0; + main_k7ddrphy_wdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_376 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_377; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dqs_rst_re <= 1'd0; + main_k7ddrphy_wdly_dqs_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_377 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_378; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dqs_rst_we <= 1'd0; + main_k7ddrphy_wdly_dqs_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dqs_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_378 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_379; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dqs_inc_re <= 1'd0; + main_k7ddrphy_wdly_dqs_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_379 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_380; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dqs_inc_we <= 1'd0; + main_k7ddrphy_wdly_dqs_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_380 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_381; -// synthesis translate_on always @(*) begin main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_381 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_382; -// synthesis translate_on always @(*) begin main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_382 = dummy_s; -// synthesis translate_on end assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_383; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_383 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_384; -// synthesis translate_on always @(*) begin - main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_384 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_385; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_385 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_386; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_386 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_387; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_387 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_388; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_388 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage; assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0]; @@ -14222,2301 +11315,435 @@ assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage; assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0]; assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0]; assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0]; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; - -// synthesis translate_off -reg dummy_d_389; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_control0_re <= 1'd0; + builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_389 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_390; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_control0_we <= 1'd0; + builder_csrbank2_dfii_control0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_390 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_391; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_391 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_392; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_392 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_393; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_393 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_394; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_394 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_395; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_395 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_396; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_396 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_397; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_397 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_398; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_398 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_399; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_399 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_400; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_400 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_401; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata7_re <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata7_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_401 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_402; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata7_we <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata7_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_402 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_403; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata6_we <= 1'd0; + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata6_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_403 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_404; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata6_re <= 1'd0; + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata6_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_404 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_405; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata5_re <= 1'd0; + builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata5_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_405 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_406; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata5_we <= 1'd0; + builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata5_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_406 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_407; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata4_re <= 1'd0; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi0_wrdata4_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_407 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_408; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata4_we <= 1'd0; + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi0_wrdata4_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_408 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_409; -// synthesis translate_on +assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_409 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_410; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_410 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_411; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_411 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_412; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_412 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_413; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_413 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_414; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_414 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_415; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_416; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_416 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_417; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata7_re <= 1'd0; + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank2_dfii_pi0_rddata7_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_417 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_418; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata7_we <= 1'd0; + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank2_dfii_pi0_rddata7_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_418 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_419; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata6_we <= 1'd0; + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi0_rddata6_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_419 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_420; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata6_re <= 1'd0; + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi0_rddata6_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_420 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_421; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata5_we <= 1'd0; + builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi0_rddata5_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_421 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_422; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata5_re <= 1'd0; + builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi0_rddata5_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_422 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_423; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata4_re <= 1'd0; + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi0_rddata4_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_423 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_424; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata4_we <= 1'd0; + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi0_rddata4_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_424 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_425; -// synthesis translate_on +assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_425 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_426; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_426 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_427; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_427 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_428; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; + builder_csrbank2_dfii_pi2_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_428 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_429; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_429 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_430; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_430 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_431; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_431 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_432; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_432 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_433; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_433 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_434; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_434 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_435; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_435 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_436; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_436 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_437; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_437 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_438; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_438 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_439; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_439 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_440; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_440 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_441; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_441 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_442; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_442 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_443; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata7_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin - builder_csrbank2_dfii_pi1_wrdata7_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_443 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_444; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata7_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin - builder_csrbank2_dfii_pi1_wrdata7_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_444 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_445; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata6_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - builder_csrbank2_dfii_pi1_wrdata6_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_445 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_446; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata6_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - builder_csrbank2_dfii_pi1_wrdata6_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_446 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_447; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata5_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi1_wrdata5_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_447 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_448; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata5_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi1_wrdata5_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_448 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_449; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata4_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin - builder_csrbank2_dfii_pi1_wrdata4_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_449 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_450; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata4_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin - builder_csrbank2_dfii_pi1_wrdata4_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_450 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_451; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_451 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_452; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_452 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_453; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_453 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_454; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_454 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_455; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_455 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_456; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_456 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_457; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_457 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_458; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_458 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_459; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata7_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi1_rddata7_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_459 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_460; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata7_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi1_rddata7_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_460 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_461; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata6_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi1_rddata6_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_461 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_462; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata6_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi1_rddata6_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_462 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_463; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata5_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi1_rddata5_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_463 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_464; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata5_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi1_rddata5_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_464 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_465; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata4_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi1_rddata4_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_465 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_466; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata4_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi1_rddata4_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_466 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_467; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_467 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_468; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_468 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_469; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_469 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_470; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_470 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_471; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_471 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_472; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_472 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_473; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_473 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_474; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_474 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_475; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_475 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_476; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_476 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_477; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_477 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_478; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_478 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_479; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_479 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_480; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_480 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_481; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_481 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_482; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_482 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_483; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_483 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_484; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_484 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_485; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata7_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi2_wrdata7_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_485 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_486; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata7_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi2_wrdata7_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_486 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_487; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata6_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi2_wrdata6_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_487 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_488; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata6_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi2_wrdata6_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_488 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_489; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata5_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi2_wrdata5_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_489 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_490; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata5_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi2_wrdata5_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_490 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_491; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata4_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi2_wrdata4_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_491 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_492; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata4_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi2_wrdata4_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_492 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_493; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_493 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_494; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_494 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_495; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_495 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_496; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_496 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_497; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_497 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_498; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_498 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_499; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd55))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_499 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_500; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd55))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_500 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_501; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata7_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd56))) begin - builder_csrbank2_dfii_pi2_rddata7_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_501 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_502; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata7_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd56))) begin - builder_csrbank2_dfii_pi2_rddata7_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_502 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_503; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata6_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin - builder_csrbank2_dfii_pi2_rddata6_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_503 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_504; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata6_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin - builder_csrbank2_dfii_pi2_rddata6_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_504 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_505; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata5_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd58))) begin - builder_csrbank2_dfii_pi2_rddata5_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_505 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_506; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata5_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd58))) begin - builder_csrbank2_dfii_pi2_rddata5_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_506 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_507; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata4_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin - builder_csrbank2_dfii_pi2_rddata4_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_507 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_508; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata4_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin - builder_csrbank2_dfii_pi2_rddata4_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_508 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_509; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd60))) begin - builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_509 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_510; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd60))) begin - builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_510 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_511; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin - builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_511 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_512; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin - builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_512 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_513; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd62))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_513 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_514; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd62))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_514 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_515; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_515 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_516; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_516 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_517; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd64))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_517 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_518; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd64))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_518 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_519; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd65))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_519 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_520; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd65))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_520 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_521; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin - builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_521 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_522; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi3_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin - builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_522 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_523; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_523 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_524; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_524 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_525; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd68))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_525 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_526; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd68))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_526 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_527; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata7_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd69))) begin - builder_csrbank2_dfii_pi3_wrdata7_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_527 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_528; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata7_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd69))) begin - builder_csrbank2_dfii_pi3_wrdata7_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_528 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_529; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata6_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin - builder_csrbank2_dfii_pi3_wrdata6_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_529 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_530; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata6_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin - builder_csrbank2_dfii_pi3_wrdata6_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_530 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_531; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata5_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin - builder_csrbank2_dfii_pi3_wrdata5_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_531 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_532; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata5_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin - builder_csrbank2_dfii_pi3_wrdata5_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_532 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_533; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata4_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd72))) begin - builder_csrbank2_dfii_pi3_wrdata4_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_533 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_534; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata4_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd72))) begin - builder_csrbank2_dfii_pi3_wrdata4_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_534 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_535; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd73))) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_535 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_536; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd73))) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_536 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_537; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_537 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_538; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_538 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_539; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_539 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_540; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_540 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_541; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd76))) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_541 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_542; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd76))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_542 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_rddata7_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_543; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata7_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd77))) begin - builder_csrbank2_dfii_pi3_rddata7_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_543 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_544; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata7_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd77))) begin - builder_csrbank2_dfii_pi3_rddata7_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_544 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_rddata6_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_545; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata6_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin - builder_csrbank2_dfii_pi3_rddata6_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_545 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_546; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata6_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin - builder_csrbank2_dfii_pi3_rddata6_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_546 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_rddata5_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_547; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata5_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd79))) begin - builder_csrbank2_dfii_pi3_rddata5_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_547 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_548; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata5_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd79))) begin - builder_csrbank2_dfii_pi3_rddata5_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_548 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_rddata4_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_549; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata4_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin - builder_csrbank2_dfii_pi3_rddata4_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_549 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_550; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata4_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin - builder_csrbank2_dfii_pi3_rddata4_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_550 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_551; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd81))) begin - builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_551 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_552; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd81))) begin - builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_552 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_553; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin - builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_553 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_554; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin - builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_554 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_555; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd83))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_555 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_556; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd83))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_556 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_557; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_557 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_558; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_558 = dummy_s; -// synthesis translate_on end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; @@ -16524,88 +11751,36 @@ assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; -assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[14:8]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0]; assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata7_w = main_litedramcore_phaseinjector0_wrdata_storage[63:56]; -assign builder_csrbank2_dfii_pi0_wrdata6_w = main_litedramcore_phaseinjector0_wrdata_storage[55:48]; -assign builder_csrbank2_dfii_pi0_wrdata5_w = main_litedramcore_phaseinjector0_wrdata_storage[47:40]; -assign builder_csrbank2_dfii_pi0_wrdata4_w = main_litedramcore_phaseinjector0_wrdata_storage[39:32]; -assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi0_rddata7_w = main_litedramcore_phaseinjector0_rddata_status[63:56]; -assign builder_csrbank2_dfii_pi0_rddata6_w = main_litedramcore_phaseinjector0_rddata_status[55:48]; -assign builder_csrbank2_dfii_pi0_rddata5_w = main_litedramcore_phaseinjector0_rddata_status[47:40]; -assign builder_csrbank2_dfii_pi0_rddata4_w = main_litedramcore_phaseinjector0_rddata_status[39:32]; -assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; +assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; -assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[14:8]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0]; assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata7_w = main_litedramcore_phaseinjector1_wrdata_storage[63:56]; -assign builder_csrbank2_dfii_pi1_wrdata6_w = main_litedramcore_phaseinjector1_wrdata_storage[55:48]; -assign builder_csrbank2_dfii_pi1_wrdata5_w = main_litedramcore_phaseinjector1_wrdata_storage[47:40]; -assign builder_csrbank2_dfii_pi1_wrdata4_w = main_litedramcore_phaseinjector1_wrdata_storage[39:32]; -assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi1_rddata7_w = main_litedramcore_phaseinjector1_rddata_status[63:56]; -assign builder_csrbank2_dfii_pi1_rddata6_w = main_litedramcore_phaseinjector1_rddata_status[55:48]; -assign builder_csrbank2_dfii_pi1_rddata5_w = main_litedramcore_phaseinjector1_rddata_status[47:40]; -assign builder_csrbank2_dfii_pi1_rddata4_w = main_litedramcore_phaseinjector1_rddata_status[39:32]; -assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; +assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; -assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[14:8]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0]; assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata7_w = main_litedramcore_phaseinjector2_wrdata_storage[63:56]; -assign builder_csrbank2_dfii_pi2_wrdata6_w = main_litedramcore_phaseinjector2_wrdata_storage[55:48]; -assign builder_csrbank2_dfii_pi2_wrdata5_w = main_litedramcore_phaseinjector2_wrdata_storage[47:40]; -assign builder_csrbank2_dfii_pi2_wrdata4_w = main_litedramcore_phaseinjector2_wrdata_storage[39:32]; -assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi2_rddata7_w = main_litedramcore_phaseinjector2_rddata_status[63:56]; -assign builder_csrbank2_dfii_pi2_rddata6_w = main_litedramcore_phaseinjector2_rddata_status[55:48]; -assign builder_csrbank2_dfii_pi2_rddata5_w = main_litedramcore_phaseinjector2_rddata_status[47:40]; -assign builder_csrbank2_dfii_pi2_rddata4_w = main_litedramcore_phaseinjector2_rddata_status[39:32]; -assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; +assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; -assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[14:8]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0]; assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata7_w = main_litedramcore_phaseinjector3_wrdata_storage[63:56]; -assign builder_csrbank2_dfii_pi3_wrdata6_w = main_litedramcore_phaseinjector3_wrdata_storage[55:48]; -assign builder_csrbank2_dfii_pi3_wrdata5_w = main_litedramcore_phaseinjector3_wrdata_storage[47:40]; -assign builder_csrbank2_dfii_pi3_wrdata4_w = main_litedramcore_phaseinjector3_wrdata_storage[39:32]; -assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi3_rddata7_w = main_litedramcore_phaseinjector3_rddata_status[63:56]; -assign builder_csrbank2_dfii_pi3_rddata6_w = main_litedramcore_phaseinjector3_rddata_status[55:48]; -assign builder_csrbank2_dfii_pi3_rddata5_w = main_litedramcore_phaseinjector3_rddata_status[47:40]; -assign builder_csrbank2_dfii_pi3_rddata4_w = main_litedramcore_phaseinjector3_rddata_status[39:32]; -assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; +assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32]; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32]; +assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; assign builder_csr_interconnect_adr = builder_litedramcore_adr; assign builder_csr_interconnect_we = builder_litedramcore_we; @@ -16621,10 +11796,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); - -// synthesis translate_off -reg dummy_d_559; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16653,14 +11824,7 @@ always @(*) begin builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase -// synthesis translate_off - dummy_d_559 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_560; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed1 <= 15'd0; case (main_litedramcore_choose_cmd_grant) @@ -16689,14 +11853,7 @@ always @(*) begin builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_560 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_561; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed2 <= 3'd0; case (main_litedramcore_choose_cmd_grant) @@ -16725,14 +11882,7 @@ always @(*) begin builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_561 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_562; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed3 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16761,14 +11911,7 @@ always @(*) begin builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_562 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_563; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed4 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16797,14 +11940,7 @@ always @(*) begin builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_563 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_564; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed5 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16833,14 +11969,7 @@ always @(*) begin builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_564 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_565; -// synthesis translate_on always @(*) begin builder_t_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16869,14 +11998,7 @@ always @(*) begin builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_565 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_566; -// synthesis translate_on always @(*) begin builder_t_array_muxed1 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16905,14 +12027,7 @@ always @(*) begin builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_566 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_567; -// synthesis translate_on always @(*) begin builder_t_array_muxed2 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -16941,14 +12056,7 @@ always @(*) begin builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_567 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_568; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed6 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -16977,14 +12085,7 @@ always @(*) begin builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase -// synthesis translate_off - dummy_d_568 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_569; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed7 <= 15'd0; case (main_litedramcore_choose_req_grant) @@ -17013,14 +12114,7 @@ always @(*) begin builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_569 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_570; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed8 <= 3'd0; case (main_litedramcore_choose_req_grant) @@ -17049,14 +12143,7 @@ always @(*) begin builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_570 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_571; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed9 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -17085,14 +12172,7 @@ always @(*) begin builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_571 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_572; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed10 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -17121,14 +12201,7 @@ always @(*) begin builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_572 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_573; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed11 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -17157,14 +12230,7 @@ always @(*) begin builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_573 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_574; -// synthesis translate_on always @(*) begin builder_t_array_muxed3 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -17193,14 +12259,7 @@ always @(*) begin builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_574 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_575; -// synthesis translate_on always @(*) begin builder_t_array_muxed4 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -17229,14 +12288,7 @@ always @(*) begin builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_575 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_576; -// synthesis translate_on always @(*) begin builder_t_array_muxed5 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -17265,14 +12317,7 @@ always @(*) begin builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_576 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_577; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed12 <= 22'd0; case (builder_roundrobin0_grant) @@ -17280,14 +12325,7 @@ always @(*) begin builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_577 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_578; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed13 <= 1'd0; case (builder_roundrobin0_grant) @@ -17295,14 +12333,7 @@ always @(*) begin builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_578 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_579; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed14 <= 1'd0; case (builder_roundrobin0_grant) @@ -17310,14 +12341,7 @@ always @(*) begin builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_579 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_580; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed15 <= 22'd0; case (builder_roundrobin1_grant) @@ -17325,14 +12349,7 @@ always @(*) begin builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_580 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_581; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed16 <= 1'd0; case (builder_roundrobin1_grant) @@ -17340,14 +12357,7 @@ always @(*) begin builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_581 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_582; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed17 <= 1'd0; case (builder_roundrobin1_grant) @@ -17355,14 +12365,7 @@ always @(*) begin builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_582 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_583; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed18 <= 22'd0; case (builder_roundrobin2_grant) @@ -17370,14 +12373,7 @@ always @(*) begin builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_583 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_584; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed19 <= 1'd0; case (builder_roundrobin2_grant) @@ -17385,14 +12381,7 @@ always @(*) begin builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_584 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_585; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed20 <= 1'd0; case (builder_roundrobin2_grant) @@ -17400,14 +12389,7 @@ always @(*) begin builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_585 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_586; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed21 <= 22'd0; case (builder_roundrobin3_grant) @@ -17415,14 +12397,7 @@ always @(*) begin builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_586 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_587; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed22 <= 1'd0; case (builder_roundrobin3_grant) @@ -17430,14 +12405,7 @@ always @(*) begin builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_587 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_588; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed23 <= 1'd0; case (builder_roundrobin3_grant) @@ -17445,14 +12413,7 @@ always @(*) begin builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_588 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_589; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed24 <= 22'd0; case (builder_roundrobin4_grant) @@ -17460,14 +12421,7 @@ always @(*) begin builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_589 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_590; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed25 <= 1'd0; case (builder_roundrobin4_grant) @@ -17475,14 +12429,7 @@ always @(*) begin builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_590 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_591; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed26 <= 1'd0; case (builder_roundrobin4_grant) @@ -17490,14 +12437,7 @@ always @(*) begin builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_591 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_592; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed27 <= 22'd0; case (builder_roundrobin5_grant) @@ -17505,14 +12445,7 @@ always @(*) begin builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_592 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_593; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed28 <= 1'd0; case (builder_roundrobin5_grant) @@ -17520,14 +12453,7 @@ always @(*) begin builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_593 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_594; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed29 <= 1'd0; case (builder_roundrobin5_grant) @@ -17535,14 +12461,7 @@ always @(*) begin builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_594 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_595; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed30 <= 22'd0; case (builder_roundrobin6_grant) @@ -17550,14 +12469,7 @@ always @(*) begin builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_595 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_596; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed31 <= 1'd0; case (builder_roundrobin6_grant) @@ -17565,14 +12477,7 @@ always @(*) begin builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_596 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_597; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed32 <= 1'd0; case (builder_roundrobin6_grant) @@ -17580,14 +12485,7 @@ always @(*) begin builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_597 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_598; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed33 <= 22'd0; case (builder_roundrobin7_grant) @@ -17595,14 +12493,7 @@ always @(*) begin builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_598 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_599; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed34 <= 1'd0; case (builder_roundrobin7_grant) @@ -17610,14 +12501,7 @@ always @(*) begin builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_599 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_600; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed35 <= 1'd0; case (builder_roundrobin7_grant) @@ -17625,14 +12509,7 @@ always @(*) begin builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_600 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_601; -// synthesis translate_on always @(*) begin builder_array_muxed0 <= 3'd0; case (main_litedramcore_steerer_sel0) @@ -17649,14 +12526,7 @@ always @(*) begin builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_601 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_602; -// synthesis translate_on always @(*) begin builder_array_muxed1 <= 15'd0; case (main_litedramcore_steerer_sel0) @@ -17673,14 +12543,7 @@ always @(*) begin builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_602 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_603; -// synthesis translate_on always @(*) begin builder_array_muxed2 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -17697,14 +12560,7 @@ always @(*) begin builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_603 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_604; -// synthesis translate_on always @(*) begin builder_array_muxed3 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -17721,14 +12577,7 @@ always @(*) begin builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_604 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_605; -// synthesis translate_on always @(*) begin builder_array_muxed4 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -17745,14 +12594,7 @@ always @(*) begin builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_605 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_606; -// synthesis translate_on always @(*) begin builder_array_muxed5 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -17769,14 +12611,7 @@ always @(*) begin builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_606 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_607; -// synthesis translate_on always @(*) begin builder_array_muxed6 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -17793,14 +12628,7 @@ always @(*) begin builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_607 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_608; -// synthesis translate_on always @(*) begin builder_array_muxed7 <= 3'd0; case (main_litedramcore_steerer_sel1) @@ -17817,14 +12645,7 @@ always @(*) begin builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_608 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_609; -// synthesis translate_on always @(*) begin builder_array_muxed8 <= 15'd0; case (main_litedramcore_steerer_sel1) @@ -17841,14 +12662,7 @@ always @(*) begin builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_609 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_610; -// synthesis translate_on always @(*) begin builder_array_muxed9 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -17865,14 +12679,7 @@ always @(*) begin builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_610 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_611; -// synthesis translate_on always @(*) begin builder_array_muxed10 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -17889,14 +12696,7 @@ always @(*) begin builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_611 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_612; -// synthesis translate_on always @(*) begin builder_array_muxed11 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -17913,14 +12713,7 @@ always @(*) begin builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_612 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_613; -// synthesis translate_on always @(*) begin builder_array_muxed12 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -17937,14 +12730,7 @@ always @(*) begin builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_613 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_614; -// synthesis translate_on always @(*) begin builder_array_muxed13 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -17961,14 +12747,7 @@ always @(*) begin builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_614 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_615; -// synthesis translate_on always @(*) begin builder_array_muxed14 <= 3'd0; case (main_litedramcore_steerer_sel2) @@ -17985,14 +12764,7 @@ always @(*) begin builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_615 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_616; -// synthesis translate_on always @(*) begin builder_array_muxed15 <= 15'd0; case (main_litedramcore_steerer_sel2) @@ -18009,14 +12781,7 @@ always @(*) begin builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_616 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_617; -// synthesis translate_on always @(*) begin builder_array_muxed16 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -18033,14 +12798,7 @@ always @(*) begin builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_617 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_618; -// synthesis translate_on always @(*) begin builder_array_muxed17 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -18057,14 +12815,7 @@ always @(*) begin builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_618 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_619; -// synthesis translate_on always @(*) begin builder_array_muxed18 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -18081,14 +12832,7 @@ always @(*) begin builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_619 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_620; -// synthesis translate_on always @(*) begin builder_array_muxed19 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -18105,14 +12849,7 @@ always @(*) begin builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_620 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_621; -// synthesis translate_on always @(*) begin builder_array_muxed20 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -18129,14 +12866,7 @@ always @(*) begin builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_621 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_622; -// synthesis translate_on always @(*) begin builder_array_muxed21 <= 3'd0; case (main_litedramcore_steerer_sel3) @@ -18153,14 +12883,7 @@ always @(*) begin builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_622 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_623; -// synthesis translate_on always @(*) begin builder_array_muxed22 <= 15'd0; case (main_litedramcore_steerer_sel3) @@ -18177,14 +12900,7 @@ always @(*) begin builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_623 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_624; -// synthesis translate_on always @(*) begin builder_array_muxed23 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -18201,14 +12917,7 @@ always @(*) begin builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_624 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_625; -// synthesis translate_on always @(*) begin builder_array_muxed24 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -18225,14 +12934,7 @@ always @(*) begin builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_625 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_626; -// synthesis translate_on always @(*) begin builder_array_muxed25 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -18249,14 +12951,7 @@ always @(*) begin builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_626 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_627; -// synthesis translate_on always @(*) begin builder_array_muxed26 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -18273,14 +12968,7 @@ always @(*) begin builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_627 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_628; -// synthesis translate_on always @(*) begin builder_array_muxed27 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -18297,15 +12985,17 @@ always @(*) begin builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_628 = dummy_s; -// synthesis translate_on end assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge iodelay_clk) begin if ((main_reset_counter != 1'd0)) begin main_reset_counter <= (main_reset_counter - 1'd1); @@ -20270,249 +14960,93 @@ always @(posedge sys_clk) begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; - end - 3'd4: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end - 3'd5: begin + 3'd4: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end - 3'd6: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata7_w; - end - 3'd7: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata6_w; - end - 4'd8: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata5_w; - end - 4'd9: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata4_w; - end - 4'd10: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; - end - 4'd11: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; - end - 4'd12: begin + 3'd5: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; end - 4'd13: begin + 3'd6: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end - 4'd14: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata7_w; - end - 4'd15: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata6_w; - end - 5'd16: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata5_w; - end - 5'd17: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata4_w; - end - 5'd18: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; - end - 5'd19: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; - end - 5'd20: begin + 3'd7: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; end - 5'd21: begin + 4'd8: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; end - 5'd22: begin + 4'd9: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end - 5'd23: begin + 4'd10: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end - 5'd24: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; - end - 5'd25: begin + 4'd11: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end - 5'd26: begin + 4'd12: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end - 5'd27: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata7_w; - end - 5'd28: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata6_w; - end - 5'd29: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata5_w; - end - 5'd30: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata4_w; - end - 5'd31: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; - end - 6'd32: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; - end - 6'd33: begin + 4'd13: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; end - 6'd34: begin + 4'd14: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end - 6'd35: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata7_w; - end - 6'd36: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata6_w; - end - 6'd37: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata5_w; - end - 6'd38: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata4_w; - end - 6'd39: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; - end - 6'd40: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; - end - 6'd41: begin + 4'd15: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; end - 6'd42: begin + 5'd16: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; end - 6'd43: begin + 5'd17: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end - 6'd44: begin + 5'd18: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end - 6'd45: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; - end - 6'd46: begin + 5'd19: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end - 6'd47: begin + 5'd20: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end - 6'd48: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata7_w; - end - 6'd49: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata6_w; - end - 6'd50: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata5_w; - end - 6'd51: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata4_w; - end - 6'd52: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; - end - 6'd53: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; - end - 6'd54: begin + 5'd21: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; end - 6'd55: begin + 5'd22: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end - 6'd56: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata7_w; - end - 6'd57: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata6_w; - end - 6'd58: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata5_w; - end - 6'd59: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata4_w; - end - 6'd60: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; - end - 6'd61: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; - end - 6'd62: begin + 5'd23: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; end - 6'd63: begin + 5'd24: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; end - 7'd64: begin + 5'd25: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end - 7'd65: begin + 5'd26: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end - 7'd66: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; - end - 7'd67: begin + 5'd27: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end - 7'd68: begin + 5'd28: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end - 7'd69: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata7_w; - end - 7'd70: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata6_w; - end - 7'd71: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata5_w; - end - 7'd72: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata4_w; - end - 7'd73: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; - end - 7'd74: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; - end - 7'd75: begin + 5'd29: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; end - 7'd76: begin + 5'd30: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end - 7'd77: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata7_w; - end - 7'd78: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata6_w; - end - 7'd79: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata5_w; - end - 7'd80: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata4_w; - end - 7'd81: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; - end - 7'd82: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; - end - 7'd83: begin + 5'd31: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; end - 7'd84: begin + 6'd32: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; end endcase @@ -20525,40 +15059,19 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; - if (builder_csrbank2_dfii_pi0_address1_re) begin - main_litedramcore_phaseinjector0_address_storage[14:8] <= builder_csrbank2_dfii_pi0_address1_r; - end if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; - if (builder_csrbank2_dfii_pi0_wrdata7_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi0_wrdata7_r; - end - if (builder_csrbank2_dfii_pi0_wrdata6_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi0_wrdata6_r; - end - if (builder_csrbank2_dfii_pi0_wrdata5_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi0_wrdata5_r; - end - if (builder_csrbank2_dfii_pi0_wrdata4_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi0_wrdata4_r; - end - if (builder_csrbank2_dfii_pi0_wrdata3_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; - end - if (builder_csrbank2_dfii_pi0_wrdata2_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; - end if (builder_csrbank2_dfii_pi0_wrdata1_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; + main_litedramcore_phaseinjector0_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi0_wrdata1_r; end if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; @@ -20566,40 +15079,19 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; - if (builder_csrbank2_dfii_pi1_address1_re) begin - main_litedramcore_phaseinjector1_address_storage[14:8] <= builder_csrbank2_dfii_pi1_address1_r; - end if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; - if (builder_csrbank2_dfii_pi1_wrdata7_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi1_wrdata7_r; - end - if (builder_csrbank2_dfii_pi1_wrdata6_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi1_wrdata6_r; - end - if (builder_csrbank2_dfii_pi1_wrdata5_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi1_wrdata5_r; - end - if (builder_csrbank2_dfii_pi1_wrdata4_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi1_wrdata4_r; - end - if (builder_csrbank2_dfii_pi1_wrdata3_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; - end - if (builder_csrbank2_dfii_pi1_wrdata2_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; - end if (builder_csrbank2_dfii_pi1_wrdata1_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; + main_litedramcore_phaseinjector1_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi1_wrdata1_r; end if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; @@ -20607,40 +15099,19 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; - if (builder_csrbank2_dfii_pi2_address1_re) begin - main_litedramcore_phaseinjector2_address_storage[14:8] <= builder_csrbank2_dfii_pi2_address1_r; - end if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; - if (builder_csrbank2_dfii_pi2_wrdata7_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi2_wrdata7_r; - end - if (builder_csrbank2_dfii_pi2_wrdata6_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi2_wrdata6_r; - end - if (builder_csrbank2_dfii_pi2_wrdata5_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi2_wrdata5_r; - end - if (builder_csrbank2_dfii_pi2_wrdata4_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi2_wrdata4_r; - end - if (builder_csrbank2_dfii_pi2_wrdata3_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; - end - if (builder_csrbank2_dfii_pi2_wrdata2_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; - end if (builder_csrbank2_dfii_pi2_wrdata1_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; + main_litedramcore_phaseinjector2_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi2_wrdata1_r; end if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; @@ -20648,40 +15119,19 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; - if (builder_csrbank2_dfii_pi3_address1_re) begin - main_litedramcore_phaseinjector3_address_storage[14:8] <= builder_csrbank2_dfii_pi3_address1_r; - end if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; - if (builder_csrbank2_dfii_pi3_wrdata7_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[63:56] <= builder_csrbank2_dfii_pi3_wrdata7_r; - end - if (builder_csrbank2_dfii_pi3_wrdata6_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[55:48] <= builder_csrbank2_dfii_pi3_wrdata6_r; - end - if (builder_csrbank2_dfii_pi3_wrdata5_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[47:40] <= builder_csrbank2_dfii_pi3_wrdata5_r; - end - if (builder_csrbank2_dfii_pi3_wrdata4_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[39:32] <= builder_csrbank2_dfii_pi3_wrdata4_r; - end - if (builder_csrbank2_dfii_pi3_wrdata3_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; - end - if (builder_csrbank2_dfii_pi3_wrdata2_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; - end if (builder_csrbank2_dfii_pi3_wrdata1_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; + main_litedramcore_phaseinjector3_wrdata_storage[63:32] <= builder_csrbank2_dfii_pi3_wrdata1_r; end if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; @@ -21015,6 +15465,11 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + BUFG BUFG( .I(main_clkout0), .O(main_clkout_buf0) @@ -25524,118 +19979,150 @@ IOBUF IOBUF_31( .O(main_k7ddrphy_dq_i_nodelay31) ); +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage[0:15]; -reg [24:0] memdat; +reg [24:0] storage_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_1[0:15]; -reg [24:0] memdat_1; +reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_2[0:15]; -reg [24:0] memdat_2; +reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_3[0:15]; -reg [24:0] memdat_3; +reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_4[0:15]; -reg [24:0] memdat_4; +reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_5[0:15]; -reg [24:0] memdat_5; +reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_6[0:15]; -reg [24:0] memdat_6; +reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_7[0:15]; -reg [24:0] memdat_7; +reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + FD FD( .C(main_clkin), .D(main_reset), @@ -25792,3 +20279,7 @@ PLLE2_ADV #( ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 08:32:12. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 5b1a383..1b6e88e 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -518,7 +518,7 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842afc4 +7c0802a63842adc4 fbe1fff8fbc1fff0 f821ff51f8010010 f88100d83bc10020 @@ -527,96 +527,97 @@ f8c100e87c651b78 38c100d87fc3f378 f90100f8f8e100f0 f9410108f9210100 -600000004800245d +6000000048002159 7fc3f3787c7f1b78 -6000000048001e69 +6000000048001b7d 7fe3fb78382100b0 -0000000048002a54 +00000000480027d4 0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842af203c4c0001 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-4181fdc4280a0009 -7f81e214395c0001 -795c0020993c0020 -7c9823784bfffdb0 -993e00004bffffb8 -e92100607d455378 -f921006039290001 -000000004bfffae8 +4bfffe2c4bfff979 +392900019a490000 +7c29184039000001 +f921006040820034 +7ce9f0504bffffcc +7ce7fa147c634050 +2c2700007d4af850 +390000007c691a14 +40820008394a0001 +2c2a000139400001 +4082ffb4394affff +4082ffc071080001 +893900014bffff8c +4182004c2c09006c +4bfffdbc3b400008 +3b40000289390001 +4082fdac2c090068 +3b4000017cb92b78 +3928ffd04bfffda0 +280900095529063e +7b6900204181fd90 +7d214a143b7b0001 +4bfffd7c99090020 +4bffffb47cb92b78 +3bde0001993e0000 +fbc100607d054378 +000000004bfffa6c 0000128001000000 f9e1ff78f9c1ff70 fa21ff88fa01ff80 @@ -1938,9 +1858,8 @@ ebe1fff8e8010010 203a46464f204853 7479622078257830 00000000000a7365 -3536373832306564 +2d2d2d2d2d2d2d2d 0000000000000000 -0032363263623561 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1982,10 +1901,6 @@ ebe1fff8e8010010 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d -62202c64256d2020 -007c203a64323025 -0000000000006425 -000000000000207c 203a7379616c6564 000000000000002d 203a7379616c6564 @@ -2001,15 +1916,13 @@ ebe1fff8e8010010 7764726168206f74 746e6f6320657261 0000000a2e6c6f72 +62202c64256d2020 +007c203a64323025 +0000000000006425 +000000000000207c 203a747365622020 302562202c64256d 6000000000206432 -616c206574697257 -61632079636e6574 -6f6974617262696c -00000000000a3a6e -0000202d3a64256d -002064253a64256d 76656c2064616552 000a3a676e696c65 696c616974696e49 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 1a0ab93..e3f6682 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,9 +1,25 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:33 -//-------------------------------------------------------------------------------- -module litedram_core( - input wire clk, - input wire rst, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 08:32:10 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + input wire rst, output wire pll_locked, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, @@ -12,9 +28,9 @@ module litedram_core( output wire ddram_we_n, output wire ddram_cs_n, output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, @@ -22,32 +38,38 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, + input wire user_port_native_0_rdata_ready, output wire [127:0] user_port_native_0_rdata_data ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_rst = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -55,7 +77,7 @@ wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; wire main_reset; -reg main_power_down = 1'd0; +reg main_power_down = 1'd0; wire main_locked; wire main_clkin; wire main_clkout0; @@ -66,48 +88,48 @@ wire main_clkout2; wire main_clkout_buf2; wire main_clkout3; wire main_clkout_buf3; -reg [3:0] main_reset_counter = 4'd15; -reg main_ic_reset = 1'd1; -reg main_a7ddrphy_rst_storage = 1'd0; -reg main_a7ddrphy_rst_re = 1'd0; -reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg main_a7ddrphy_wlevel_en_storage = 1'd0; -reg main_a7ddrphy_wlevel_en_re = 1'd0; -reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; wire main_a7ddrphy_wlevel_strobe_r; -reg main_a7ddrphy_wlevel_strobe_we = 1'd0; -reg main_a7ddrphy_wlevel_strobe_w = 1'd0; -reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; -reg main_a7ddrphy_dly_sel_re = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_rst_r; -reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; wire main_a7ddrphy_rdly_dq_inc_r; -reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_rst_r; -reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_r; -reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_rst_r; -reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_r; -reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; -reg main_a7ddrphy_rdphase_re = 1'd0; -reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; -reg main_a7ddrphy_wrphase_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; wire [14:0] main_a7ddrphy_dfi_p0_address; wire [2:0] main_a7ddrphy_dfi_p0_bank; wire main_a7ddrphy_dfi_p0_cas_n; @@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata; wire main_a7ddrphy_dfi_p0_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; wire main_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; wire main_a7ddrphy_dfi_p0_rddata_valid; wire [14:0] main_a7ddrphy_dfi_p1_address; wire [2:0] main_a7ddrphy_dfi_p1_bank; @@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata; wire main_a7ddrphy_dfi_p1_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; wire main_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; wire main_a7ddrphy_dfi_p1_rddata_valid; wire [14:0] main_a7ddrphy_dfi_p2_address; wire [2:0] main_a7ddrphy_dfi_p2_bank; @@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata; wire main_a7ddrphy_dfi_p2_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; wire main_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; wire main_a7ddrphy_dfi_p2_rddata_valid; wire [14:0] main_a7ddrphy_dfi_p3_address; wire [2:0] main_a7ddrphy_dfi_p3_bank; @@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata; wire main_a7ddrphy_dfi_p3_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; wire main_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; wire main_a7ddrphy_dfi_p3_rddata_valid; wire main_a7ddrphy_sd_clk_se_nodelay; -reg main_a7ddrphy_dqs_oe = 1'd0; +reg main_a7ddrphy_dqs_oe = 1'd0; wire main_a7ddrphy_dqs_preamble; wire main_a7ddrphy_dqs_postamble; wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_dqspattern0 = 1'd0; -reg main_a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; wire main_a7ddrphy_dqs_o_no_delay0; wire main_a7ddrphy_dqs_t0; -reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; wire main_a7ddrphy0; wire main_a7ddrphy_dqs_o_no_delay1; wire main_a7ddrphy_dqs_t1; -reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; wire main_a7ddrphy1; -reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; wire main_a7ddrphy_dq_oe; wire main_a7ddrphy_dq_oe_delay_tappeddelayline; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire main_a7ddrphy_dq_o_nodelay0; wire main_a7ddrphy_dq_i_nodelay0; wire main_a7ddrphy_dq_i_delayed0; wire main_a7ddrphy_dq_t0; -reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip03; -reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay1; wire main_a7ddrphy_dq_i_nodelay1; wire main_a7ddrphy_dq_i_delayed1; wire main_a7ddrphy_dq_t1; -reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip13; -reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay2; wire main_a7ddrphy_dq_i_nodelay2; wire main_a7ddrphy_dq_i_delayed2; wire main_a7ddrphy_dq_t2; -reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip21; -reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay3; wire main_a7ddrphy_dq_i_nodelay3; wire main_a7ddrphy_dq_i_delayed3; wire main_a7ddrphy_dq_t3; -reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip31; -reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay4; wire main_a7ddrphy_dq_i_nodelay4; wire main_a7ddrphy_dq_i_delayed4; wire main_a7ddrphy_dq_t4; -reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip41; -reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay5; wire main_a7ddrphy_dq_i_nodelay5; wire main_a7ddrphy_dq_i_delayed5; wire main_a7ddrphy_dq_t5; -reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip51; -reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay6; wire main_a7ddrphy_dq_i_nodelay6; wire main_a7ddrphy_dq_i_delayed6; wire main_a7ddrphy_dq_t6; -reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip61; -reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay7; wire main_a7ddrphy_dq_i_nodelay7; wire main_a7ddrphy_dq_i_delayed7; wire main_a7ddrphy_dq_t7; -reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip71; -reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay8; wire main_a7ddrphy_dq_i_nodelay8; wire main_a7ddrphy_dq_i_delayed8; wire main_a7ddrphy_dq_t8; -reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip81; -reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay9; wire main_a7ddrphy_dq_i_nodelay9; wire main_a7ddrphy_dq_i_delayed9; wire main_a7ddrphy_dq_t9; -reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip91; -reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay10; wire main_a7ddrphy_dq_i_nodelay10; wire main_a7ddrphy_dq_i_delayed10; wire main_a7ddrphy_dq_t10; -reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip101; -reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay11; wire main_a7ddrphy_dq_i_nodelay11; wire main_a7ddrphy_dq_i_delayed11; wire main_a7ddrphy_dq_t11; -reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip111; -reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay12; wire main_a7ddrphy_dq_i_nodelay12; wire main_a7ddrphy_dq_i_delayed12; wire main_a7ddrphy_dq_t12; -reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip121; -reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay13; wire main_a7ddrphy_dq_i_nodelay13; wire main_a7ddrphy_dq_i_delayed13; wire main_a7ddrphy_dq_t13; -reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip131; -reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay14; wire main_a7ddrphy_dq_i_nodelay14; wire main_a7ddrphy_dq_i_delayed14; wire main_a7ddrphy_dq_t14; -reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip141; -reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay15; wire main_a7ddrphy_dq_i_nodelay15; wire main_a7ddrphy_dq_i_delayed15; wire main_a7ddrphy_dq_t15; -reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip151; -reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [14:0] main_litedramcore_inti_p0_address; wire [2:0] main_litedramcore_inti_p0_bank; -reg main_litedramcore_inti_p0_cas_n = 1'd1; -reg main_litedramcore_inti_p0_cs_n = 1'd1; -reg main_litedramcore_inti_p0_ras_n = 1'd1; -reg main_litedramcore_inti_p0_we_n = 1'd1; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; wire main_litedramcore_inti_p0_cke; wire main_litedramcore_inti_p0_odt; wire main_litedramcore_inti_p0_reset_n; -reg main_litedramcore_inti_p0_act_n = 1'd1; +reg main_litedramcore_inti_p0_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p0_wrdata; wire main_litedramcore_inti_p0_wrdata_en; wire [3:0] main_litedramcore_inti_p0_wrdata_mask; wire main_litedramcore_inti_p0_rddata_en; -reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; -reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; wire [14:0] main_litedramcore_inti_p1_address; wire [2:0] main_litedramcore_inti_p1_bank; -reg main_litedramcore_inti_p1_cas_n = 1'd1; -reg main_litedramcore_inti_p1_cs_n = 1'd1; -reg main_litedramcore_inti_p1_ras_n = 1'd1; -reg main_litedramcore_inti_p1_we_n = 1'd1; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; wire main_litedramcore_inti_p1_cke; wire main_litedramcore_inti_p1_odt; wire main_litedramcore_inti_p1_reset_n; -reg main_litedramcore_inti_p1_act_n = 1'd1; +reg main_litedramcore_inti_p1_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p1_wrdata; wire main_litedramcore_inti_p1_wrdata_en; wire [3:0] main_litedramcore_inti_p1_wrdata_mask; wire main_litedramcore_inti_p1_rddata_en; -reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; -reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; wire [14:0] main_litedramcore_inti_p2_address; wire [2:0] main_litedramcore_inti_p2_bank; -reg main_litedramcore_inti_p2_cas_n = 1'd1; -reg main_litedramcore_inti_p2_cs_n = 1'd1; -reg main_litedramcore_inti_p2_ras_n = 1'd1; -reg main_litedramcore_inti_p2_we_n = 1'd1; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; wire main_litedramcore_inti_p2_cke; wire main_litedramcore_inti_p2_odt; wire main_litedramcore_inti_p2_reset_n; -reg main_litedramcore_inti_p2_act_n = 1'd1; +reg main_litedramcore_inti_p2_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p2_wrdata; wire main_litedramcore_inti_p2_wrdata_en; wire [3:0] main_litedramcore_inti_p2_wrdata_mask; wire main_litedramcore_inti_p2_rddata_en; -reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; -reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; wire [14:0] main_litedramcore_inti_p3_address; wire [2:0] main_litedramcore_inti_p3_bank; -reg main_litedramcore_inti_p3_cas_n = 1'd1; -reg main_litedramcore_inti_p3_cs_n = 1'd1; -reg main_litedramcore_inti_p3_ras_n = 1'd1; -reg main_litedramcore_inti_p3_we_n = 1'd1; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; wire main_litedramcore_inti_p3_cke; wire main_litedramcore_inti_p3_odt; wire main_litedramcore_inti_p3_reset_n; -reg main_litedramcore_inti_p3_act_n = 1'd1; +reg main_litedramcore_inti_p3_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p3_wrdata; wire main_litedramcore_inti_p3_wrdata_en; wire [3:0] main_litedramcore_inti_p3_wrdata_mask; wire main_litedramcore_inti_p3_rddata_en; -reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; -reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p0_address; wire [2:0] main_litedramcore_slave_p0_bank; wire main_litedramcore_slave_p0_cas_n; @@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata; wire main_litedramcore_slave_p0_wrdata_en; wire [3:0] main_litedramcore_slave_p0_wrdata_mask; wire main_litedramcore_slave_p0_rddata_en; -reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; -reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p1_address; wire [2:0] main_litedramcore_slave_p1_bank; wire main_litedramcore_slave_p1_cas_n; @@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata; wire main_litedramcore_slave_p1_wrdata_en; wire [3:0] main_litedramcore_slave_p1_wrdata_mask; wire main_litedramcore_slave_p1_rddata_en; -reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; -reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p2_address; wire [2:0] main_litedramcore_slave_p2_bank; wire main_litedramcore_slave_p2_cas_n; @@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata; wire main_litedramcore_slave_p2_wrdata_en; wire [3:0] main_litedramcore_slave_p2_wrdata_mask; wire main_litedramcore_slave_p2_rddata_en; -reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; -reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; wire [14:0] main_litedramcore_slave_p3_address; wire [2:0] main_litedramcore_slave_p3_bank; wire main_litedramcore_slave_p3_cas_n; @@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata; wire main_litedramcore_slave_p3_wrdata_en; wire [3:0] main_litedramcore_slave_p3_wrdata_mask; wire main_litedramcore_slave_p3_rddata_en; -reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; -reg main_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] main_litedramcore_master_p0_address = 15'd0; -reg [2:0] main_litedramcore_master_p0_bank = 3'd0; -reg main_litedramcore_master_p0_cas_n = 1'd1; -reg main_litedramcore_master_p0_cs_n = 1'd1; -reg main_litedramcore_master_p0_ras_n = 1'd1; -reg main_litedramcore_master_p0_we_n = 1'd1; -reg main_litedramcore_master_p0_cke = 1'd0; -reg main_litedramcore_master_p0_odt = 1'd0; -reg main_litedramcore_master_p0_reset_n = 1'd0; -reg main_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; -reg main_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; -reg main_litedramcore_master_p0_rddata_en = 1'd0; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] main_litedramcore_master_p0_address = 15'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p0_rddata; wire main_litedramcore_master_p0_rddata_valid; -reg [14:0] main_litedramcore_master_p1_address = 15'd0; -reg [2:0] main_litedramcore_master_p1_bank = 3'd0; -reg main_litedramcore_master_p1_cas_n = 1'd1; -reg main_litedramcore_master_p1_cs_n = 1'd1; -reg main_litedramcore_master_p1_ras_n = 1'd1; -reg main_litedramcore_master_p1_we_n = 1'd1; -reg main_litedramcore_master_p1_cke = 1'd0; -reg main_litedramcore_master_p1_odt = 1'd0; -reg main_litedramcore_master_p1_reset_n = 1'd0; -reg main_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; -reg main_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; -reg main_litedramcore_master_p1_rddata_en = 1'd0; +reg [14:0] main_litedramcore_master_p1_address = 15'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p1_rddata; wire main_litedramcore_master_p1_rddata_valid; -reg [14:0] main_litedramcore_master_p2_address = 15'd0; -reg [2:0] main_litedramcore_master_p2_bank = 3'd0; -reg main_litedramcore_master_p2_cas_n = 1'd1; -reg main_litedramcore_master_p2_cs_n = 1'd1; -reg main_litedramcore_master_p2_ras_n = 1'd1; -reg main_litedramcore_master_p2_we_n = 1'd1; -reg main_litedramcore_master_p2_cke = 1'd0; -reg main_litedramcore_master_p2_odt = 1'd0; -reg main_litedramcore_master_p2_reset_n = 1'd0; -reg main_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; -reg main_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; -reg main_litedramcore_master_p2_rddata_en = 1'd0; +reg [14:0] main_litedramcore_master_p2_address = 15'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p2_rddata; wire main_litedramcore_master_p2_rddata_valid; -reg [14:0] main_litedramcore_master_p3_address = 15'd0; -reg [2:0] main_litedramcore_master_p3_bank = 3'd0; -reg main_litedramcore_master_p3_cas_n = 1'd1; -reg main_litedramcore_master_p3_cs_n = 1'd1; -reg main_litedramcore_master_p3_ras_n = 1'd1; -reg main_litedramcore_master_p3_we_n = 1'd1; -reg main_litedramcore_master_p3_cke = 1'd0; -reg main_litedramcore_master_p3_odt = 1'd0; -reg main_litedramcore_master_p3_reset_n = 1'd0; -reg main_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; -reg main_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; -reg main_litedramcore_master_p3_rddata_en = 1'd0; +reg [14:0] main_litedramcore_master_p3_address = 15'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p3_rddata; wire main_litedramcore_master_p3_rddata_valid; wire main_litedramcore_sel; wire main_litedramcore_cke; wire main_litedramcore_odt; wire main_litedramcore_reset_n; -reg [3:0] main_litedramcore_storage = 4'd1; -reg main_litedramcore_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; -reg main_litedramcore_phaseinjector0_command_re = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector0_command_issue_r; -reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; -reg main_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector0_address_storage = 15'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; wire main_litedramcore_phaseinjector0_rddata_we; -reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; -reg main_litedramcore_phaseinjector1_command_re = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector1_command_issue_r; -reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; -reg main_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector1_address_storage = 15'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; wire main_litedramcore_phaseinjector1_rddata_we; -reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; -reg main_litedramcore_phaseinjector2_command_re = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector2_command_issue_r; -reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; -reg main_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector2_address_storage = 15'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; wire main_litedramcore_phaseinjector2_rddata_we; -reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; -reg main_litedramcore_phaseinjector3_command_re = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector3_command_issue_r; -reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; -reg main_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] main_litedramcore_phaseinjector3_address_storage = 15'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; wire main_litedramcore_phaseinjector3_rddata_we; -reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; wire main_litedramcore_interface_bank0_valid; wire main_litedramcore_interface_bank0_ready; wire main_litedramcore_interface_bank0_we; @@ -706,131 +728,131 @@ wire [21:0] main_litedramcore_interface_bank7_addr; wire main_litedramcore_interface_bank7_lock; wire main_litedramcore_interface_bank7_wdata_ready; wire main_litedramcore_interface_bank7_rdata_valid; -reg [127:0] main_litedramcore_interface_wdata = 128'd0; -reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; wire [127:0] main_litedramcore_interface_rdata; -reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; -reg main_litedramcore_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_dfi_p0_ras_n = 1'd1; -reg main_litedramcore_dfi_p0_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p0_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; wire main_litedramcore_dfi_p0_cke; wire main_litedramcore_dfi_p0_odt; wire main_litedramcore_dfi_p0_reset_n; -reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg main_litedramcore_dfi_p0_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p0_wrdata; -reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; -reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p0_rddata; wire main_litedramcore_dfi_p0_rddata_valid; -reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; -reg main_litedramcore_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_dfi_p1_ras_n = 1'd1; -reg main_litedramcore_dfi_p1_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p1_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; wire main_litedramcore_dfi_p1_cke; wire main_litedramcore_dfi_p1_odt; wire main_litedramcore_dfi_p1_reset_n; -reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg main_litedramcore_dfi_p1_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p1_wrdata; -reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; -reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p1_rddata; wire main_litedramcore_dfi_p1_rddata_valid; -reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; -reg main_litedramcore_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_dfi_p2_ras_n = 1'd1; -reg main_litedramcore_dfi_p2_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p2_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; wire main_litedramcore_dfi_p2_cke; wire main_litedramcore_dfi_p2_odt; wire main_litedramcore_dfi_p2_reset_n; -reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg main_litedramcore_dfi_p2_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p2_wrdata; -reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; -reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p2_rddata; wire main_litedramcore_dfi_p2_rddata_valid; -reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; -reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; -reg main_litedramcore_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_dfi_p3_ras_n = 1'd1; -reg main_litedramcore_dfi_p3_we_n = 1'd1; +reg [14:0] main_litedramcore_dfi_p3_address = 15'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; wire main_litedramcore_dfi_p3_cke; wire main_litedramcore_dfi_p3_odt; wire main_litedramcore_dfi_p3_reset_n; -reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg main_litedramcore_dfi_p3_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p3_wrdata; -reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; -reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p3_rddata; wire main_litedramcore_dfi_p3_rddata_valid; -reg main_litedramcore_cmd_valid = 1'd0; -reg main_litedramcore_cmd_ready = 1'd0; -reg main_litedramcore_cmd_last = 1'd0; -reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; -reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; -reg main_litedramcore_cmd_payload_cas = 1'd0; -reg main_litedramcore_cmd_payload_ras = 1'd0; -reg main_litedramcore_cmd_payload_we = 1'd0; -reg main_litedramcore_cmd_payload_is_read = 1'd0; -reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [14:0] main_litedramcore_cmd_payload_a = 15'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; wire main_litedramcore_wants_refresh; wire main_litedramcore_wants_zqcs; wire main_litedramcore_timer_wait; wire main_litedramcore_timer_done0; wire [9:0] main_litedramcore_timer_count0; wire main_litedramcore_timer_done1; -reg [9:0] main_litedramcore_timer_count1 = 10'd781; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; wire main_litedramcore_postponer_req_i; -reg main_litedramcore_postponer_req_o = 1'd0; -reg main_litedramcore_postponer_count = 1'd0; -reg main_litedramcore_sequencer_start0 = 1'd0; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; wire main_litedramcore_sequencer_done0; wire main_litedramcore_sequencer_start1; -reg main_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] main_litedramcore_sequencer_counter = 6'd0; -reg main_litedramcore_sequencer_count = 1'd0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; wire main_litedramcore_zqcs_timer_wait; wire main_litedramcore_zqcs_timer_done0; wire [26:0] main_litedramcore_zqcs_timer_count0; wire main_litedramcore_zqcs_timer_done1; -reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg main_litedramcore_zqcs_executer_start = 1'd0; -reg main_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; wire main_litedramcore_bankmachine0_req_valid; wire main_litedramcore_bankmachine0_req_ready; wire main_litedramcore_bankmachine0_req_we; wire [21:0] main_litedramcore_bankmachine0_req_addr; wire main_litedramcore_bankmachine0_req_lock; -reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine0_refresh_req; -reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine0_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; -reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; @@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; @@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; -reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine0_row = 15'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; wire main_litedramcore_bankmachine0_row_hit; -reg main_litedramcore_bankmachine0_row_open = 1'd0; -reg main_litedramcore_bankmachine0_row_close = 1'd0; -reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; wire main_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; wire main_litedramcore_bankmachine1_req_valid; wire main_litedramcore_bankmachine1_req_ready; wire main_litedramcore_bankmachine1_req_we; wire [21:0] main_litedramcore_bankmachine1_req_addr; wire main_litedramcore_bankmachine1_req_lock; -reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine1_refresh_req; -reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine1_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; -reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; @@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; @@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; -reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine1_row = 15'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; wire main_litedramcore_bankmachine1_row_hit; -reg main_litedramcore_bankmachine1_row_open = 1'd0; -reg main_litedramcore_bankmachine1_row_close = 1'd0; -reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; wire main_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; wire main_litedramcore_bankmachine2_req_valid; wire main_litedramcore_bankmachine2_req_ready; wire main_litedramcore_bankmachine2_req_we; wire [21:0] main_litedramcore_bankmachine2_req_addr; wire main_litedramcore_bankmachine2_req_lock; -reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine2_refresh_req; -reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine2_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; -reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; @@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; @@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; -reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine2_row = 15'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; wire main_litedramcore_bankmachine2_row_hit; -reg main_litedramcore_bankmachine2_row_open = 1'd0; -reg main_litedramcore_bankmachine2_row_close = 1'd0; -reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; wire main_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; wire main_litedramcore_bankmachine3_req_valid; wire main_litedramcore_bankmachine3_req_ready; wire main_litedramcore_bankmachine3_req_we; wire [21:0] main_litedramcore_bankmachine3_req_addr; wire main_litedramcore_bankmachine3_req_lock; -reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine3_refresh_req; -reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine3_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; -reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; @@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; @@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; -reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine3_row = 15'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; wire main_litedramcore_bankmachine3_row_hit; -reg main_litedramcore_bankmachine3_row_open = 1'd0; -reg main_litedramcore_bankmachine3_row_close = 1'd0; -reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; wire main_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; wire main_litedramcore_bankmachine4_req_valid; wire main_litedramcore_bankmachine4_req_ready; wire main_litedramcore_bankmachine4_req_we; wire [21:0] main_litedramcore_bankmachine4_req_addr; wire main_litedramcore_bankmachine4_req_lock; -reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine4_refresh_req; -reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine4_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; -reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; @@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; @@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; -reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine4_row = 15'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; wire main_litedramcore_bankmachine4_row_hit; -reg main_litedramcore_bankmachine4_row_open = 1'd0; -reg main_litedramcore_bankmachine4_row_close = 1'd0; -reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; wire main_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; wire main_litedramcore_bankmachine5_req_valid; wire main_litedramcore_bankmachine5_req_ready; wire main_litedramcore_bankmachine5_req_we; wire [21:0] main_litedramcore_bankmachine5_req_addr; wire main_litedramcore_bankmachine5_req_lock; -reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine5_refresh_req; -reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine5_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; -reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; @@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; @@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; -reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine5_row = 15'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; wire main_litedramcore_bankmachine5_row_hit; -reg main_litedramcore_bankmachine5_row_open = 1'd0; -reg main_litedramcore_bankmachine5_row_close = 1'd0; -reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; wire main_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; wire main_litedramcore_bankmachine6_req_valid; wire main_litedramcore_bankmachine6_req_ready; wire main_litedramcore_bankmachine6_req_we; wire [21:0] main_litedramcore_bankmachine6_req_addr; wire main_litedramcore_bankmachine6_req_lock; -reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine6_refresh_req; -reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine6_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; -reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; @@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; @@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; -reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine6_row = 15'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; wire main_litedramcore_bankmachine6_row_hit; -reg main_litedramcore_bankmachine6_row_open = 1'd0; -reg main_litedramcore_bankmachine6_row_close = 1'd0; -reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; wire main_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; wire main_litedramcore_bankmachine7_req_valid; wire main_litedramcore_bankmachine7_req_ready; wire main_litedramcore_bankmachine7_req_we; wire [21:0] main_litedramcore_bankmachine7_req_addr; wire main_litedramcore_bankmachine7_req_lock; -reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine7_refresh_req; -reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] main_litedramcore_bankmachine7_cmd_payload_a = 15'd0; wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; -reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; @@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [24:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; @@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; wire [21:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; -reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] main_litedramcore_bankmachine7_row = 15'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; wire main_litedramcore_bankmachine7_row_hit; -reg main_litedramcore_bankmachine7_row_open = 1'd0; -reg main_litedramcore_bankmachine7_row_close = 1'd0; -reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; wire main_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; wire main_litedramcore_ras_allowed; wire main_litedramcore_cas_allowed; wire [1:0] main_litedramcore_rdcmdphase; wire [1:0] main_litedramcore_wrcmdphase; -reg main_litedramcore_choose_cmd_want_reads = 1'd0; -reg main_litedramcore_choose_cmd_want_writes = 1'd0; -reg main_litedramcore_choose_cmd_want_cmds = 1'd0; -reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; wire main_litedramcore_choose_cmd_cmd_valid; -reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; wire [14:0] main_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; -reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; wire main_litedramcore_choose_cmd_cmd_payload_is_read; wire main_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; wire [7:0] main_litedramcore_choose_cmd_request; -reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; wire main_litedramcore_choose_cmd_ce; -reg main_litedramcore_choose_req_want_reads = 1'd0; -reg main_litedramcore_choose_req_want_writes = 1'd0; -reg main_litedramcore_choose_req_want_cmds = 1'd0; -reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; wire main_litedramcore_choose_req_cmd_valid; -reg main_litedramcore_choose_req_cmd_ready = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; wire [14:0] main_litedramcore_choose_req_cmd_payload_a; wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; -reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; wire main_litedramcore_choose_req_cmd_payload_is_cmd; wire main_litedramcore_choose_req_cmd_payload_is_read; wire main_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; wire [7:0] main_litedramcore_choose_req_request; -reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; wire main_litedramcore_choose_req_ce; -reg [14:0] main_litedramcore_nop_a = 15'd0; -reg [2:0] main_litedramcore_nop_ba = 3'd0; -reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; -reg main_litedramcore_steerer0 = 1'd1; -reg main_litedramcore_steerer1 = 1'd1; -reg main_litedramcore_steerer2 = 1'd1; -reg main_litedramcore_steerer3 = 1'd1; -reg main_litedramcore_steerer4 = 1'd1; -reg main_litedramcore_steerer5 = 1'd1; -reg main_litedramcore_steerer6 = 1'd1; -reg main_litedramcore_steerer7 = 1'd1; +reg [14:0] main_litedramcore_nop_a = 15'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; wire main_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; -reg main_litedramcore_trrdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; wire main_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; wire [2:0] main_litedramcore_tfawcon_count; -reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; wire main_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; -reg main_litedramcore_tccdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; wire main_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; wire main_litedramcore_read_available; wire main_litedramcore_write_available; -reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en0 = 1'd0; wire main_litedramcore_max_time0; -reg [4:0] main_litedramcore_time0 = 5'd0; -reg main_litedramcore_en1 = 1'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; wire main_litedramcore_max_time1; -reg [3:0] main_litedramcore_time1 = 4'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; wire main_litedramcore_go_to_refresh; -reg main_init_done_storage = 1'd0; -reg main_init_done_re = 1'd0; -reg main_init_error_storage = 1'd0; -reg main_init_error_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; wire [29:0] main_wb_bus_adr; wire [31:0] main_wb_bus_dat_w; wire [31:0] main_wb_bus_dat_r; @@ -1570,6 +1592,7 @@ wire main_wb_bus_we; wire [2:0] main_wb_bus_cti; wire [1:0] main_wb_bus_bte; wire main_wb_bus_err; +wire main_user_enable; wire main_user_port_cmd_valid; wire main_user_port_cmd_ready; wire main_user_port_cmd_payload_we; @@ -1590,26 +1613,26 @@ wire builder_reset5; wire builder_reset6; wire builder_reset7; wire builder_pll_fb; -reg [1:0] builder_refresher_state = 2'd0; -reg [1:0] builder_refresher_next_state = 2'd0; -reg [3:0] builder_bankmachine0_state = 4'd0; -reg [3:0] builder_bankmachine0_next_state = 4'd0; -reg [3:0] builder_bankmachine1_state = 4'd0; -reg [3:0] builder_bankmachine1_next_state = 4'd0; -reg [3:0] builder_bankmachine2_state = 4'd0; -reg [3:0] builder_bankmachine2_next_state = 4'd0; -reg [3:0] builder_bankmachine3_state = 4'd0; -reg [3:0] builder_bankmachine3_next_state = 4'd0; -reg [3:0] builder_bankmachine4_state = 4'd0; -reg [3:0] builder_bankmachine4_next_state = 4'd0; -reg [3:0] builder_bankmachine5_state = 4'd0; -reg [3:0] builder_bankmachine5_next_state = 4'd0; -reg [3:0] builder_bankmachine6_state = 4'd0; -reg [3:0] builder_bankmachine6_next_state = 4'd0; -reg [3:0] builder_bankmachine7_state = 4'd0; -reg [3:0] builder_bankmachine7_next_state = 4'd0; -reg [3:0] builder_multiplexer_state = 4'd0; -reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; wire builder_roundrobin0_request; wire builder_roundrobin0_grant; wire builder_roundrobin0_ce; @@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce; wire builder_roundrobin7_request; wire builder_roundrobin7_grant; wire builder_roundrobin7_ce; -reg builder_locked0 = 1'd0; -reg builder_locked1 = 1'd0; -reg builder_locked2 = 1'd0; -reg builder_locked3 = 1'd0; -reg builder_locked4 = 1'd0; -reg builder_locked5 = 1'd0; -reg builder_locked6 = 1'd0; -reg builder_locked7 = 1'd0; -reg builder_new_master_wdata_ready0 = 1'd0; -reg builder_new_master_wdata_ready1 = 1'd0; -reg builder_new_master_rdata_valid0 = 1'd0; -reg builder_new_master_rdata_valid1 = 1'd0; -reg builder_new_master_rdata_valid2 = 1'd0; -reg builder_new_master_rdata_valid3 = 1'd0; -reg builder_new_master_rdata_valid4 = 1'd0; -reg builder_new_master_rdata_valid5 = 1'd0; -reg builder_new_master_rdata_valid6 = 1'd0; -reg builder_new_master_rdata_valid7 = 1'd0; -reg builder_new_master_rdata_valid8 = 1'd0; -reg [13:0] builder_litedramcore_adr = 14'd0; -reg builder_litedramcore_we = 1'd0; -reg [7:0] builder_litedramcore_dat_w = 8'd0; -wire [7:0] builder_litedramcore_dat_r; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [31:0] builder_litedramcore_dat_w = 32'd0; +wire [31:0] builder_litedramcore_dat_r; wire [29:0] builder_litedramcore_wishbone_adr; wire [31:0] builder_litedramcore_wishbone_dat_w; -reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; wire [3:0] builder_litedramcore_wishbone_sel; wire builder_litedramcore_wishbone_cyc; wire builder_litedramcore_wishbone_stb; -reg builder_litedramcore_wishbone_ack = 1'd0; +reg builder_litedramcore_wishbone_ack = 1'd0; wire builder_litedramcore_wishbone_we; wire [2:0] builder_litedramcore_wishbone_cti; wire [1:0] builder_litedramcore_wishbone_bte; -reg builder_litedramcore_wishbone_err = 1'd0; +reg builder_litedramcore_wishbone_err = 1'd0; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; -wire [7:0] builder_interface0_bank_bus_dat_w; -reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; -reg builder_csrbank0_init_done0_re = 1'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +reg builder_csrbank0_init_done0_re = 1'd0; wire builder_csrbank0_init_done0_r; -reg builder_csrbank0_init_done0_we = 1'd0; +reg builder_csrbank0_init_done0_we = 1'd0; wire builder_csrbank0_init_done0_w; -reg builder_csrbank0_init_error0_re = 1'd0; +reg builder_csrbank0_init_error0_re = 1'd0; wire builder_csrbank0_init_error0_r; -reg builder_csrbank0_init_error0_we = 1'd0; +reg builder_csrbank0_init_error0_we = 1'd0; wire builder_csrbank0_init_error0_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; -wire [7:0] builder_interface1_bank_bus_dat_w; -reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; -reg builder_csrbank1_rst0_re = 1'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +reg builder_csrbank1_rst0_re = 1'd0; wire builder_csrbank1_rst0_r; -reg builder_csrbank1_rst0_we = 1'd0; +reg builder_csrbank1_rst0_we = 1'd0; wire builder_csrbank1_rst0_w; -reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_r; -reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_w; -reg builder_csrbank1_wlevel_en0_re = 1'd0; +reg builder_csrbank1_wlevel_en0_re = 1'd0; wire builder_csrbank1_wlevel_en0_r; -reg builder_csrbank1_wlevel_en0_we = 1'd0; +reg builder_csrbank1_wlevel_en0_we = 1'd0; wire builder_csrbank1_wlevel_en0_w; -reg builder_csrbank1_dly_sel0_re = 1'd0; +reg builder_csrbank1_dly_sel0_re = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_r; -reg builder_csrbank1_dly_sel0_we = 1'd0; +reg builder_csrbank1_dly_sel0_we = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_w; -reg builder_csrbank1_rdphase0_re = 1'd0; +reg builder_csrbank1_rdphase0_re = 1'd0; wire [1:0] builder_csrbank1_rdphase0_r; -reg builder_csrbank1_rdphase0_we = 1'd0; +reg builder_csrbank1_rdphase0_we = 1'd0; wire [1:0] builder_csrbank1_rdphase0_w; -reg builder_csrbank1_wrphase0_re = 1'd0; +reg builder_csrbank1_wrphase0_re = 1'd0; wire [1:0] builder_csrbank1_wrphase0_r; -reg builder_csrbank1_wrphase0_we = 1'd0; +reg builder_csrbank1_wrphase0_we = 1'd0; wire [1:0] builder_csrbank1_wrphase0_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; -wire [7:0] builder_interface2_bank_bus_dat_w; -reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; -reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_r; -reg builder_csrbank2_dfii_control0_we = 1'd0; +reg builder_csrbank2_dfii_control0_we = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_w; -reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_r; -reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_w; -reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi0_address1_r; -reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi0_address1_w; -reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_r; -reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_w; -reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; -reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; -reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; -reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; -reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; -reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; -reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; -reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; -reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; -reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; -reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; -reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; -reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; -reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; -reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; -reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; -reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; -reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; -reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_r; -reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_w; -reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi1_address1_r; -reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi1_address1_w; -reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_r; -reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_w; -reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; -reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; -reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; -reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; -reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; -reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; -reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; -reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; -reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; -reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; -reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; -reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; -reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; -reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; -reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; -reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; -reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; -reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; -reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_r; -reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_w; -reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi2_address1_r; -reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi2_address1_w; -reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_r; -reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_w; -reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; -reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; -reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; -reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; -reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; -reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; -reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; -reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; -reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; -reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; -reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; -reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; -reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; -reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; -reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; -reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; -reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; -reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; -reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_r; -reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_w; -reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi3_address1_r; -reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; -wire [6:0] builder_csrbank2_dfii_pi3_address1_w; -reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_r; -reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_w; -reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [14:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; -reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; -reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; -reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; -reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; -reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; -reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; -reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; -reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; -reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; -reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; -reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; -reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; -reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; -reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; -reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; -reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; -reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; wire builder_csrbank2_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; -wire [7:0] builder_csr_interconnect_dat_w; -wire [7:0] builder_csr_interconnect_dat_r; -reg [1:0] builder_state = 2'd0; -reg [1:0] builder_next_state = 2'd0; -reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; -reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; -reg builder_litedramcore_adr_next_value_ce1 = 1'd0; -reg builder_litedramcore_we_next_value2 = 1'd0; -reg builder_litedramcore_we_next_value_ce2 = 1'd0; -reg builder_rhs_array_muxed0 = 1'd0; -reg [14:0] builder_rhs_array_muxed1 = 15'd0; -reg [2:0] builder_rhs_array_muxed2 = 3'd0; -reg builder_rhs_array_muxed3 = 1'd0; -reg builder_rhs_array_muxed4 = 1'd0; -reg builder_rhs_array_muxed5 = 1'd0; -reg builder_t_array_muxed0 = 1'd0; -reg builder_t_array_muxed1 = 1'd0; -reg builder_t_array_muxed2 = 1'd0; -reg builder_rhs_array_muxed6 = 1'd0; -reg [14:0] builder_rhs_array_muxed7 = 15'd0; -reg [2:0] builder_rhs_array_muxed8 = 3'd0; -reg builder_rhs_array_muxed9 = 1'd0; -reg builder_rhs_array_muxed10 = 1'd0; -reg builder_rhs_array_muxed11 = 1'd0; -reg builder_t_array_muxed3 = 1'd0; -reg builder_t_array_muxed4 = 1'd0; -reg builder_t_array_muxed5 = 1'd0; -reg [21:0] builder_rhs_array_muxed12 = 22'd0; -reg builder_rhs_array_muxed13 = 1'd0; -reg builder_rhs_array_muxed14 = 1'd0; -reg [21:0] builder_rhs_array_muxed15 = 22'd0; -reg builder_rhs_array_muxed16 = 1'd0; -reg builder_rhs_array_muxed17 = 1'd0; -reg [21:0] builder_rhs_array_muxed18 = 22'd0; -reg builder_rhs_array_muxed19 = 1'd0; -reg builder_rhs_array_muxed20 = 1'd0; -reg [21:0] builder_rhs_array_muxed21 = 22'd0; -reg builder_rhs_array_muxed22 = 1'd0; -reg builder_rhs_array_muxed23 = 1'd0; -reg [21:0] builder_rhs_array_muxed24 = 22'd0; -reg builder_rhs_array_muxed25 = 1'd0; -reg builder_rhs_array_muxed26 = 1'd0; -reg [21:0] builder_rhs_array_muxed27 = 22'd0; -reg builder_rhs_array_muxed28 = 1'd0; -reg builder_rhs_array_muxed29 = 1'd0; -reg [21:0] builder_rhs_array_muxed30 = 22'd0; -reg builder_rhs_array_muxed31 = 1'd0; -reg builder_rhs_array_muxed32 = 1'd0; -reg [21:0] builder_rhs_array_muxed33 = 22'd0; -reg builder_rhs_array_muxed34 = 1'd0; -reg builder_rhs_array_muxed35 = 1'd0; -reg [2:0] builder_array_muxed0 = 3'd0; -reg [14:0] builder_array_muxed1 = 15'd0; -reg builder_array_muxed2 = 1'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg builder_array_muxed6 = 1'd0; -reg [2:0] builder_array_muxed7 = 3'd0; -reg [14:0] builder_array_muxed8 = 15'd0; -reg builder_array_muxed9 = 1'd0; -reg builder_array_muxed10 = 1'd0; -reg builder_array_muxed11 = 1'd0; -reg builder_array_muxed12 = 1'd0; -reg builder_array_muxed13 = 1'd0; -reg [2:0] builder_array_muxed14 = 3'd0; -reg [14:0] builder_array_muxed15 = 15'd0; -reg builder_array_muxed16 = 1'd0; -reg builder_array_muxed17 = 1'd0; -reg builder_array_muxed18 = 1'd0; -reg builder_array_muxed19 = 1'd0; -reg builder_array_muxed20 = 1'd0; -reg [2:0] builder_array_muxed21 = 3'd0; -reg [14:0] builder_array_muxed22 = 15'd0; -reg builder_array_muxed23 = 1'd0; -reg builder_array_muxed24 = 1'd0; -reg builder_array_muxed25 = 1'd0; -reg builder_array_muxed26 = 1'd0; -reg builder_array_muxed27 = 1'd0; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [14:0] builder_rhs_array_muxed1 = 15'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [14:0] builder_rhs_array_muxed7 = 15'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [21:0] builder_rhs_array_muxed12 = 22'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [21:0] builder_rhs_array_muxed15 = 22'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [21:0] builder_rhs_array_muxed18 = 22'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [21:0] builder_rhs_array_muxed21 = 22'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [21:0] builder_rhs_array_muxed24 = 22'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [21:0] builder_rhs_array_muxed27 = 22'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [21:0] builder_rhs_array_muxed30 = 22'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [21:0] builder_rhs_array_muxed33 = 22'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [14:0] builder_array_muxed1 = 15'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [14:0] builder_array_muxed8 = 15'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [14:0] builder_array_muxed15 = 15'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [14:0] builder_array_muxed22 = 15'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl1; @@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl3_expr; -// synthesis translate_off -reg dummy_s; -initial dummy_s <= 1'd0; -// synthesis translate_on +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + assign init_done = main_init_done_storage; assign init_error = main_init_error_storage; assign main_wb_bus_adr = wb_ctrl_adr; @@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; -assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; -assign main_reset = rst; +assign main_reset = (rst | main_rst); assign pll_locked = main_locked; assign main_clkin = clk; assign iodelay_clk = main_clkout_buf0; @@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2; assign sys4x_dqs_clk = main_clkout_buf3; assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); - -// synthesis translate_off -reg dummy_d; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p0_rddata <= 32'd0; main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; @@ -2081,14 +1989,7 @@ always @(*) begin main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; -// synthesis translate_off - dummy_d = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_1; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p1_rddata <= 32'd0; main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; @@ -2123,14 +2024,7 @@ always @(*) begin main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; -// synthesis translate_off - dummy_d_1 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_2; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p2_rddata <= 32'd0; main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; @@ -2165,14 +2059,7 @@ always @(*) begin main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; -// synthesis translate_off - dummy_d_2 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_3; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p3_rddata <= 32'd0; main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; @@ -2207,19 +2094,12 @@ always @(*) begin main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; -// synthesis translate_off - dummy_d_3 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; - -// synthesis translate_off -reg dummy_d_4; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqs_oe <= 1'd0; if (main_a7ddrphy_wlevel_en_storage) begin @@ -2227,16 +2107,9 @@ always @(*) begin end else begin main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; end -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqspattern_o0 <= 8'd0; main_a7ddrphy_dqspattern_o0 <= 7'd85; @@ -2252,14 +2125,7 @@ always @(*) begin main_a7ddrphy_dqspattern_o0 <= 1'd1; end end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip00 <= 8'd0; case (main_a7ddrphy_bitslip0_value0) @@ -2288,14 +2154,7 @@ always @(*) begin main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip10 <= 8'd0; case (main_a7ddrphy_bitslip1_value0) @@ -2324,14 +2183,7 @@ always @(*) begin main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip01 <= 8'd0; case (main_a7ddrphy_bitslip0_value1) @@ -2360,14 +2212,7 @@ always @(*) begin main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip11 <= 8'd0; case (main_a7ddrphy_bitslip1_value1) @@ -2396,14 +2241,7 @@ always @(*) begin main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip02 <= 8'd0; case (main_a7ddrphy_bitslip0_value2) @@ -2432,14 +2270,7 @@ always @(*) begin main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip04 <= 8'd0; case (main_a7ddrphy_bitslip0_value3) @@ -2468,14 +2299,7 @@ always @(*) begin main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip12 <= 8'd0; case (main_a7ddrphy_bitslip1_value2) @@ -2504,14 +2328,7 @@ always @(*) begin main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip14 <= 8'd0; case (main_a7ddrphy_bitslip1_value3) @@ -2540,14 +2357,7 @@ always @(*) begin main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip20 <= 8'd0; case (main_a7ddrphy_bitslip2_value0) @@ -2576,14 +2386,7 @@ always @(*) begin main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip22 <= 8'd0; case (main_a7ddrphy_bitslip2_value1) @@ -2612,14 +2415,7 @@ always @(*) begin main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip30 <= 8'd0; case (main_a7ddrphy_bitslip3_value0) @@ -2648,14 +2444,7 @@ always @(*) begin main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip32 <= 8'd0; case (main_a7ddrphy_bitslip3_value1) @@ -2684,14 +2473,7 @@ always @(*) begin main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_18; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip40 <= 8'd0; case (main_a7ddrphy_bitslip4_value0) @@ -2720,14 +2502,7 @@ always @(*) begin main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_18 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_19; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip42 <= 8'd0; case (main_a7ddrphy_bitslip4_value1) @@ -2756,14 +2531,7 @@ always @(*) begin main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_19 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_20; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip50 <= 8'd0; case (main_a7ddrphy_bitslip5_value0) @@ -2792,14 +2560,7 @@ always @(*) begin main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_20 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_21; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip52 <= 8'd0; case (main_a7ddrphy_bitslip5_value1) @@ -2828,14 +2589,7 @@ always @(*) begin main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_21 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip60 <= 8'd0; case (main_a7ddrphy_bitslip6_value0) @@ -2864,14 +2618,7 @@ always @(*) begin main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip62 <= 8'd0; case (main_a7ddrphy_bitslip6_value1) @@ -2900,14 +2647,7 @@ always @(*) begin main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip70 <= 8'd0; case (main_a7ddrphy_bitslip7_value0) @@ -2936,14 +2676,7 @@ always @(*) begin main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip72 <= 8'd0; case (main_a7ddrphy_bitslip7_value1) @@ -2972,14 +2705,7 @@ always @(*) begin main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_26; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip80 <= 8'd0; case (main_a7ddrphy_bitslip8_value0) @@ -3008,14 +2734,7 @@ always @(*) begin main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip82 <= 8'd0; case (main_a7ddrphy_bitslip8_value1) @@ -3044,14 +2763,7 @@ always @(*) begin main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip90 <= 8'd0; case (main_a7ddrphy_bitslip9_value0) @@ -3080,14 +2792,7 @@ always @(*) begin main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip92 <= 8'd0; case (main_a7ddrphy_bitslip9_value1) @@ -3116,14 +2821,7 @@ always @(*) begin main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip100 <= 8'd0; case (main_a7ddrphy_bitslip10_value0) @@ -3152,14 +2850,7 @@ always @(*) begin main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_30 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_31; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip102 <= 8'd0; case (main_a7ddrphy_bitslip10_value1) @@ -3188,14 +2879,7 @@ always @(*) begin main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_31 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_32; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip110 <= 8'd0; case (main_a7ddrphy_bitslip11_value0) @@ -3224,14 +2908,7 @@ always @(*) begin main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_32 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_33; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip112 <= 8'd0; case (main_a7ddrphy_bitslip11_value1) @@ -3260,14 +2937,7 @@ always @(*) begin main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_33 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_34; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip120 <= 8'd0; case (main_a7ddrphy_bitslip12_value0) @@ -3296,14 +2966,7 @@ always @(*) begin main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_34 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_35; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip122 <= 8'd0; case (main_a7ddrphy_bitslip12_value1) @@ -3332,14 +2995,7 @@ always @(*) begin main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_35 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_36; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip130 <= 8'd0; case (main_a7ddrphy_bitslip13_value0) @@ -3368,14 +3024,7 @@ always @(*) begin main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_36 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_37; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip132 <= 8'd0; case (main_a7ddrphy_bitslip13_value1) @@ -3404,14 +3053,7 @@ always @(*) begin main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_37 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_38; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip140 <= 8'd0; case (main_a7ddrphy_bitslip14_value0) @@ -3440,14 +3082,7 @@ always @(*) begin main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip142 <= 8'd0; case (main_a7ddrphy_bitslip14_value1) @@ -3476,14 +3111,7 @@ always @(*) begin main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_39 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_40; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip150 <= 8'd0; case (main_a7ddrphy_bitslip15_value0) @@ -3512,14 +3140,7 @@ always @(*) begin main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_40 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_41; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip152 <= 8'd0; case (main_a7ddrphy_bitslip15_value1) @@ -3548,9 +3169,6 @@ always @(*) begin main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_41 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; @@ -3680,10 +3298,29 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_ assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; - -// synthesis translate_off -reg dummy_d_42; -// synthesis translate_on +always @(*) begin + main_litedramcore_master_p3_cs_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; + end else begin + main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; + end +end +always @(*) begin + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; + end else begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; + end +end +always @(*) begin + main_litedramcore_slave_p3_rddata <= 32'd0; + if (main_litedramcore_sel) begin + main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; + end else begin + end +end always @(*) begin main_litedramcore_master_p3_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3691,28 +3328,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end -// synthesis translate_off - dummy_d_42 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_43; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_43 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_44; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -3720,14 +3343,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end -// synthesis translate_off - dummy_d_44 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_45; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -3735,14 +3351,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end -// synthesis translate_off - dummy_d_45 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_46; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -3750,14 +3359,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end -// synthesis translate_off - dummy_d_46 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_47; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3765,14 +3367,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end -// synthesis translate_off - dummy_d_47 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_48; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -3780,28 +3375,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end -// synthesis translate_off - dummy_d_48 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_49; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end -// synthesis translate_off - dummy_d_49 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_50; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3809,28 +3390,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end -// synthesis translate_off - dummy_d_50 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_51; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end -// synthesis translate_off - dummy_d_51 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_52; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -3838,14 +3405,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end -// synthesis translate_off - dummy_d_52 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_53; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3853,14 +3413,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; end -// synthesis translate_off - dummy_d_53 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_54; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_address <= 15'd0; if (main_litedramcore_sel) begin @@ -3868,14 +3421,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end -// synthesis translate_off - dummy_d_54 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_55; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -3883,14 +3429,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end -// synthesis translate_off - dummy_d_55 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_56; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3898,14 +3437,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end -// synthesis translate_off - dummy_d_56 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_57; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3913,43 +3445,22 @@ always @(*) begin end else begin main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end -// synthesis translate_off - dummy_d_57 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_58; -// synthesis translate_on always @(*) begin - main_litedramcore_slave_p0_rddata <= 32'd0; + main_litedramcore_master_p0_ras_n <= 1'd1; if (main_litedramcore_sel) begin - main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; + main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; end else begin + main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end -// synthesis translate_off - dummy_d_58 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_59; -// synthesis translate_on always @(*) begin - main_litedramcore_master_p0_ras_n <= 1'd1; + main_litedramcore_slave_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin - main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n; + main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin - main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end -// synthesis translate_off - dummy_d_59 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_60; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3957,28 +3468,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end -// synthesis translate_off - dummy_d_60 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_61; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_61 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_62; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -3986,14 +3483,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end -// synthesis translate_off - dummy_d_62 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_63; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4001,14 +3491,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end -// synthesis translate_off - dummy_d_63 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_64; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4016,14 +3499,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end -// synthesis translate_off - dummy_d_64 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_65; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4031,14 +3507,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end -// synthesis translate_off - dummy_d_65 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_66; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4046,28 +3515,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end -// synthesis translate_off - dummy_d_66 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_67; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end -// synthesis translate_off - dummy_d_67 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_68; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4075,28 +3530,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end -// synthesis translate_off - dummy_d_68 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_69; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end -// synthesis translate_off - dummy_d_69 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_70; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4104,14 +3545,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end -// synthesis translate_off - dummy_d_70 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_71; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4119,14 +3553,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end -// synthesis translate_off - dummy_d_71 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_72; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_address <= 15'd0; if (main_litedramcore_sel) begin @@ -4134,14 +3561,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end -// synthesis translate_off - dummy_d_72 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_73; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4149,14 +3569,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end -// synthesis translate_off - dummy_d_73 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_74; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4164,14 +3577,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end -// synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4179,14 +3585,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end -// synthesis translate_off - dummy_d_75 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_76; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4194,28 +3593,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end -// synthesis translate_off - dummy_d_76 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_77; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end -// synthesis translate_off - dummy_d_77 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_78; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4223,28 +3608,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end -// synthesis translate_off - dummy_d_78 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_79; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_79 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_80; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4252,14 +3623,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end -// synthesis translate_off - dummy_d_80 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_81; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4267,14 +3631,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end -// synthesis translate_off - dummy_d_81 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_82; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4282,14 +3639,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end -// synthesis translate_off - dummy_d_82 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_83; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4297,14 +3647,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end -// synthesis translate_off - dummy_d_83 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_84; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4312,28 +3655,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end -// synthesis translate_off - dummy_d_84 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_85; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end -// synthesis translate_off - dummy_d_85 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_86; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4341,28 +3670,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end -// synthesis translate_off - dummy_d_86 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_87; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end -// synthesis translate_off - dummy_d_87 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_88; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4370,14 +3685,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end -// synthesis translate_off - dummy_d_88 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_89; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4385,14 +3693,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end -// synthesis translate_off - dummy_d_89 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_90; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_address <= 15'd0; if (main_litedramcore_sel) begin @@ -4400,14 +3701,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end -// synthesis translate_off - dummy_d_90 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_91; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4415,14 +3709,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end -// synthesis translate_off - dummy_d_91 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_92; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4430,14 +3717,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end -// synthesis translate_off - dummy_d_92 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_93; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4445,14 +3725,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end -// synthesis translate_off - dummy_d_93 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_94; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4460,28 +3733,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_94 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_95; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end -// synthesis translate_off - dummy_d_95 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_96; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4489,28 +3748,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_97 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_98; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4518,14 +3763,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end -// synthesis translate_off - dummy_d_98 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_99; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4533,14 +3771,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end -// synthesis translate_off - dummy_d_99 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_100; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4548,14 +3779,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end -// synthesis translate_off - dummy_d_100 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_101; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4563,14 +3787,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end -// synthesis translate_off - dummy_d_101 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_102; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4578,28 +3795,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end -// synthesis translate_off - dummy_d_102 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_103; -// synthesis translate_on always @(*) begin - main_litedramcore_slave_p3_rddata <= 32'd0; + main_litedramcore_inti_p3_rddata <= 32'd0; if (main_litedramcore_sel) begin - main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin + main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end -// synthesis translate_off - dummy_d_103 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_104; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4607,28 +3810,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end -// synthesis translate_off - dummy_d_104 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_105; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_rddata <= 32'd0; + main_litedramcore_inti_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin - main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end -// synthesis translate_off - dummy_d_105 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_106; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4636,28 +3825,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end -// synthesis translate_off - dummy_d_106 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_107; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p3_rddata_valid <= 1'd0; - if (main_litedramcore_sel) begin - end else begin - main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; - end -// synthesis translate_off - dummy_d_107 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_108; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4665,14 +3833,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end -// synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_address <= 15'd0; if (main_litedramcore_sel) begin @@ -4680,14 +3841,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end -// synthesis translate_off - dummy_d_109 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_110; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4695,14 +3849,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end -// synthesis translate_off - dummy_d_110 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_111; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4710,39 +3857,6 @@ always @(*) begin end else begin main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end -// synthesis translate_off - dummy_d_111 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_112; -// synthesis translate_on -always @(*) begin - main_litedramcore_master_p3_cs_n <= 1'd1; - if (main_litedramcore_sel) begin - main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n; - end else begin - main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; - end -// synthesis translate_off - dummy_d_112 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_113; -// synthesis translate_on -always @(*) begin - main_litedramcore_master_p3_ras_n <= 1'd1; - if (main_litedramcore_sel) begin - main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; - end else begin - main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; - end -// synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; @@ -4756,65 +3870,37 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p0_we_n <= 1'd1; + main_litedramcore_inti_p0_cs_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}}; end else begin - main_litedramcore_inti_p0_we_n <= 1'd1; + main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_114 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_115; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p0_cas_n <= 1'd1; + main_litedramcore_inti_p0_ras_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); + main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); end else begin - main_litedramcore_inti_p0_cas_n <= 1'd1; + main_litedramcore_inti_p0_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_115 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_116; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p0_cs_n <= 1'd1; + main_litedramcore_inti_p0_we_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}}; + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); end else begin - main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; + main_litedramcore_inti_p0_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_116 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_117; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p0_ras_n <= 1'd1; + main_litedramcore_inti_p0_cas_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]); + main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]); end else begin - main_litedramcore_inti_p0_ras_n <= 1'd1; + main_litedramcore_inti_p0_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_117 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; @@ -4822,65 +3908,37 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_118; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p1_we_n <= 1'd1; + main_litedramcore_inti_p1_cs_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); + main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}}; end else begin - main_litedramcore_inti_p1_we_n <= 1'd1; + main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_118 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_119; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p1_cas_n <= 1'd1; + main_litedramcore_inti_p1_ras_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); + main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); end else begin - main_litedramcore_inti_p1_cas_n <= 1'd1; + main_litedramcore_inti_p1_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p1_cs_n <= 1'd1; + main_litedramcore_inti_p1_we_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}}; + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); end else begin - main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; + main_litedramcore_inti_p1_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p1_ras_n <= 1'd1; + main_litedramcore_inti_p1_cas_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]); + main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]); end else begin - main_litedramcore_inti_p1_ras_n <= 1'd1; + main_litedramcore_inti_p1_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; @@ -4888,10 +3946,22 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; + end +end +always @(*) begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); + end else begin + main_litedramcore_inti_p2_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p2_we_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4899,14 +3969,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4914,39 +3977,6 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p2_cs_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}}; - end else begin - main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; - end -// synthesis translate_off - dummy_d_124 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_125; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p2_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]); - end else begin - main_litedramcore_inti_p2_ras_n <= 1'd1; - end -// synthesis translate_off - dummy_d_125 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; @@ -4954,65 +3984,37 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_126; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_inti_p3_cs_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}}; end else begin - main_litedramcore_inti_p3_we_n <= 1'd1; + main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_cas_n <= 1'd1; + main_litedramcore_inti_p3_ras_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); + main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); end else begin - main_litedramcore_inti_p3_cas_n <= 1'd1; + main_litedramcore_inti_p3_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_cs_n <= 1'd1; + main_litedramcore_inti_p3_we_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}}; + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); end else begin - main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; + main_litedramcore_inti_p3_we_n <= 1'd1; end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_ras_n <= 1'd1; + main_litedramcore_inti_p3_cas_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]); + main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]); end else begin - main_litedramcore_inti_p3_ras_n <= 1'd1; + main_litedramcore_inti_p3_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; @@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on always @(*) begin builder_refresher_next_state <= 2'd0; builder_refresher_next_state <= builder_refresher_state; @@ -5124,14 +4122,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_130 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_131; -// synthesis translate_on always @(*) begin main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) @@ -5147,14 +4138,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_131 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_132; -// synthesis translate_on always @(*) begin main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) @@ -5179,14 +4163,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_132 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_133; -// synthesis translate_on always @(*) begin main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) @@ -5205,14 +4182,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_133 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_134; -// synthesis translate_on always @(*) begin main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) @@ -5234,9 +4204,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_134 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; @@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_135; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin @@ -5263,17 +4226,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_135 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_136; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin @@ -5281,9 +4237,6 @@ always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_136 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; @@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_137; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin @@ -5313,9 +4262,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); @@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on always @(*) begin builder_bankmachine0_next_state <= 4'd0; builder_bankmachine0_next_state <= builder_bankmachine0_state; @@ -5389,14 +4331,71 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_138 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_139; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (builder_bankmachine0_state) @@ -5437,14 +4436,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine0_state) @@ -5470,14 +4462,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_140 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_141; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine0_state) @@ -5507,14 +4492,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_141 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_142; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (builder_bankmachine0_state) @@ -5552,14 +4530,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_142 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_143; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (builder_bankmachine0_state) @@ -5597,14 +4568,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_143 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_144; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (builder_bankmachine0_state) @@ -5642,14 +4606,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (builder_bankmachine0_state) @@ -5687,14 +4644,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_145 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_146; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (builder_bankmachine0_state) @@ -5720,14 +4670,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_146 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_147; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (builder_bankmachine0_state) @@ -5768,14 +4711,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) @@ -5801,14 +4737,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_148 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_149; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_close <= 1'd0; case (builder_bankmachine0_state) @@ -5834,87 +4763,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_149 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_150; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_150 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_151; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_151 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; @@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_152; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin @@ -5941,17 +4785,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin @@ -5959,9 +4796,6 @@ always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; @@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin @@ -5991,9 +4821,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); @@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on always @(*) begin builder_bankmachine1_next_state <= 4'd0; builder_bankmachine1_next_state <= builder_bankmachine1_state; @@ -6067,21 +4890,11 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_155 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_156; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6103,10 +4916,7 @@ always @(*) begin if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine1_row_opened) begin if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6115,64 +4925,23 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_156 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_157; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin - main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6185,18 +4954,14 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_158 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_159; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6219,8 +4984,8 @@ always @(*) begin if (main_litedramcore_bankmachine1_row_opened) begin if (main_litedramcore_bankmachine1_row_hit) begin if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin - main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6230,22 +4995,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_159 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_160; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -6258,33 +5019,41 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end + 3'd4: begin + main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase -// synthesis translate_off - dummy_d_160 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_161; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end @@ -6309,8 +5078,8 @@ always @(*) begin if (main_litedramcore_bankmachine1_row_opened) begin if (main_litedramcore_bankmachine1_row_hit) begin if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; end else begin + main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6320,16 +5089,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end @@ -6354,8 +5116,8 @@ always @(*) begin if (main_litedramcore_bankmachine1_row_opened) begin if (main_litedramcore_bankmachine1_row_hit) begin if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin - main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -6365,16 +5127,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_162 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_163; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end @@ -6383,9 +5138,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6396,30 +5148,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_163 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_164; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6437,7 +5191,10 @@ always @(*) begin if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine1_row_opened) begin if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -6446,27 +5203,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_164 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_165; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_row_open <= 1'd0; + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_row_open <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6479,27 +5229,23 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_165 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_166; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_row_close <= 1'd0; + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -6510,24 +5256,32 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_166 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_167; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine1_row_open <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin end @@ -6540,44 +5294,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_167 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_168; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine1_row_close <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -6590,9 +5322,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_168 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; @@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_169; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin @@ -6619,17 +5344,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin @@ -6637,9 +5355,6 @@ always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; @@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin @@ -6669,9 +5380,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); @@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on always @(*) begin builder_bankmachine2_next_state <= 4'd0; builder_bankmachine2_next_state <= builder_bankmachine2_state; @@ -6745,14 +5449,71 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_172 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_173; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) @@ -6793,14 +5554,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) @@ -6826,14 +5580,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_174 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_175; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) @@ -6863,14 +5610,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) @@ -6908,14 +5648,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) @@ -6953,14 +5686,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_177 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_178; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) @@ -6998,14 +5724,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_178 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_179; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (builder_bankmachine2_state) @@ -7043,14 +5762,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_179 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_180; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (builder_bankmachine2_state) @@ -7076,14 +5788,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_180 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_181; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) @@ -7124,14 +5829,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_181 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_182; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) @@ -7157,14 +5855,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_182 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_183; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) @@ -7190,106 +5881,21 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_183 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_184; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_184 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_185; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_185 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; -assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we; -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; -assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); -assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); -assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); -assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_186; -// synthesis translate_on +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; +assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid); +assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin main_litedramcore_bankmachine3_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin @@ -7297,17 +5903,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin @@ -7315,9 +5914,6 @@ always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; @@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin @@ -7347,9 +5939,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); @@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on always @(*) begin builder_bankmachine3_next_state <= 4'd0; builder_bankmachine3_next_state <= builder_bankmachine3_state; @@ -7423,14 +6008,71 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_189 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_190; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (builder_bankmachine3_state) @@ -7471,14 +6113,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_190 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_191; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) @@ -7504,14 +6139,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -7541,14 +6169,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_192 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_193; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (builder_bankmachine3_state) @@ -7586,14 +6207,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_193 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_194; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (builder_bankmachine3_state) @@ -7631,14 +6245,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_194 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_195; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (builder_bankmachine3_state) @@ -7676,14 +6283,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_195 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_196; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (builder_bankmachine3_state) @@ -7721,14 +6321,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (builder_bankmachine3_state) @@ -7754,14 +6347,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_197 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_198; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (builder_bankmachine3_state) @@ -7802,14 +6388,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_198 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_199; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_open <= 1'd0; case (builder_bankmachine3_state) @@ -7835,14 +6414,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_199 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_200; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_close <= 1'd0; case (builder_bankmachine3_state) @@ -7868,87 +6440,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_200 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_201; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_201 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_202; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_202 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; @@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_203; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin @@ -7975,17 +6462,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin @@ -7993,9 +6473,6 @@ always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_204 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; @@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_205; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin @@ -8025,9 +6498,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); @@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on always @(*) begin builder_bankmachine4_next_state <= 4'd0; builder_bankmachine4_next_state <= builder_bankmachine4_state; @@ -8101,21 +6567,11 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_206 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_207; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8137,10 +6593,7 @@ always @(*) begin if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine4_row_opened) begin if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8149,24 +6602,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8182,31 +6631,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_208 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_209; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8217,20 +6655,84 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -// synthesis translate_off - dummy_d_209 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_210; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin end 2'd2: begin end @@ -8264,14 +6766,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_210 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_211; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (builder_bankmachine4_state) @@ -8309,14 +6804,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_211 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_212; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (builder_bankmachine4_state) @@ -8354,14 +6842,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_212 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_213; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) @@ -8399,14 +6880,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_213 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_214; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (builder_bankmachine4_state) @@ -8432,14 +6906,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_214 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_215; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (builder_bankmachine4_state) @@ -8480,14 +6947,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_215 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_216; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_open <= 1'd0; case (builder_bankmachine4_state) @@ -8513,14 +6973,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_216 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_217; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_close <= 1'd0; case (builder_bankmachine4_state) @@ -8546,87 +6999,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_218 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_219; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_219 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; @@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_220; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin @@ -8653,17 +7021,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_220 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_221; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin @@ -8671,9 +7032,6 @@ always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_221 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; @@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_222; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin @@ -8703,9 +7057,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); @@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on always @(*) begin builder_bankmachine5_next_state <= 4'd0; builder_bankmachine5_next_state <= builder_bankmachine5_state; @@ -8779,14 +7126,71 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (builder_bankmachine5_state) @@ -8827,14 +7231,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_224 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_225; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -8860,14 +7257,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine5_state) @@ -8897,14 +7287,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (builder_bankmachine5_state) @@ -8942,14 +7325,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_227 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_228; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (builder_bankmachine5_state) @@ -8987,14 +7363,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_228 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_229; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (builder_bankmachine5_state) @@ -9032,14 +7401,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_229 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_230; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (builder_bankmachine5_state) @@ -9077,14 +7439,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_230 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_231; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (builder_bankmachine5_state) @@ -9110,14 +7465,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_231 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_232; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (builder_bankmachine5_state) @@ -9158,14 +7506,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_232 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_233; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_open <= 1'd0; case (builder_bankmachine5_state) @@ -9191,14 +7532,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_233 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_234; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_close <= 1'd0; case (builder_bankmachine5_state) @@ -9224,106 +7558,21 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_234 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_235; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_235 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_236; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_236 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; -assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we; -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; -assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); -assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); -assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; - -// synthesis translate_off -reg dummy_d_237; -// synthesis translate_on +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; +assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid); +assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin main_litedramcore_bankmachine6_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin @@ -9331,17 +7580,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin @@ -9349,9 +7591,6 @@ always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_238 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; @@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_239; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin @@ -9381,9 +7616,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); @@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on always @(*) begin builder_bankmachine6_next_state <= 4'd0; builder_bankmachine6_next_state <= builder_bankmachine6_state; @@ -9457,14 +7685,71 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_240 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_241; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) @@ -9505,14 +7790,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) @@ -9538,14 +7816,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_242 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_243; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) @@ -9575,14 +7846,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_243 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_244; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) @@ -9620,14 +7884,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_244 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_245; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) @@ -9665,14 +7922,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) @@ -9710,14 +7960,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_246 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_247; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) @@ -9755,14 +7998,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_247 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_248; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (builder_bankmachine6_state) @@ -9788,14 +8024,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_248 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_249; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) @@ -9836,14 +8065,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_249 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_250; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) @@ -9869,14 +8091,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_250 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_251; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) @@ -9902,87 +8117,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_251 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_252; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_252 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_253; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_253 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; @@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_254; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_a <= 15'd0; if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin @@ -10009,17 +8139,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_254 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_255; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin @@ -10027,9 +8150,6 @@ always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_255 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; @@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_256; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin @@ -10059,9 +8175,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_256 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); @@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_257; -// synthesis translate_on always @(*) begin builder_bankmachine7_next_state <= 4'd0; builder_bankmachine7_next_state <= builder_bankmachine7_state; @@ -10135,21 +8244,11 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_257 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_258; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -10171,10 +8270,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10183,24 +8279,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_258 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_259; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -10216,31 +8308,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_259 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_260; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10251,23 +8332,87 @@ always @(*) begin 4'd8: begin end default: begin - end - endcase -// synthesis translate_off - dummy_d_260 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_261; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end 2'd3: begin end 3'd4: begin @@ -10298,14 +8443,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_261 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_262; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) @@ -10343,14 +8481,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_262 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_263; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) @@ -10388,14 +8519,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_263 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_264; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) @@ -10433,14 +8557,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_264 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_265; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) @@ -10466,14 +8583,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_265 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_266; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) @@ -10514,14 +8624,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_266 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_267; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_open <= 1'd0; case (builder_bankmachine7_state) @@ -10547,14 +8650,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_267 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_268; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) @@ -10580,87 +8676,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_268 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_269; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_269 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_270; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_270 = dummy_s; -// synthesis translate_on end assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); @@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); - -// synthesis translate_off -reg dummy_d_271; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_valids <= 8'd0; main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); @@ -10706,9 +8717,6 @@ always @(*) begin main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_271 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; @@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_272; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end -// synthesis translate_off - dummy_d_272 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_273; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end -// synthesis translate_off - dummy_d_273 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_274; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end -// synthesis translate_off - dummy_d_274 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_275; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin @@ -10768,14 +8751,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_275 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_276; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin @@ -10784,14 +8760,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_276 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_277; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin @@ -10800,14 +8769,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_277 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_278; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin @@ -10816,14 +8778,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_278 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_279; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin @@ -10832,14 +8787,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_279 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_280; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin @@ -10848,14 +8796,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin @@ -10864,14 +8805,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin @@ -10880,15 +8814,8 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_282 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); - -// synthesis translate_off -reg dummy_d_283; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_valids <= 8'd0; main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); @@ -10899,9 +8826,6 @@ always @(*) begin main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); -// synthesis translate_off - dummy_d_283 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; @@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; - -// synthesis translate_off -reg dummy_d_284; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end -// synthesis translate_off - dummy_d_284 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_285; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end -// synthesis translate_off - dummy_d_285 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); assign main_litedramcore_dfi_p0_reset_n = 1'd1; @@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1; assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on always @(*) begin builder_multiplexer_next_state <= 4'd0; builder_multiplexer_next_state <= builder_multiplexer_state; @@ -11023,14 +8922,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -11067,14 +8959,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on always @(*) begin main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) @@ -11102,14 +8987,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel0 <= 2'd0; case (builder_multiplexer_state) @@ -11151,27 +9029,14 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel1 <= 2'd0; + main_litedramcore_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel1 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 2'd2; - end - if ((main_litedramcore_wrcmdphase == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 1'd1; - end end 2'd2: begin + main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -11190,30 +9055,22 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel1 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 2'd2; - end - if ((main_litedramcore_rdcmdphase == 1'd1)) begin - main_litedramcore_steerer_sel1 <= 1'd1; - end end endcase -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_ready <= 1'd0; + main_litedramcore_steerer_sel1 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end end 2'd2: begin - main_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -11232,16 +9089,16 @@ always @(*) begin 4'd10: begin end default: begin + main_litedramcore_steerer_sel1 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 1'd1)) begin + main_litedramcore_steerer_sel1 <= 1'd1; + end end endcase -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel2 <= 2'd0; case (builder_multiplexer_state) @@ -11282,14 +9139,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_want_activates <= 1'd0; case (builder_multiplexer_state) @@ -11324,14 +9174,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel3 <= 2'd0; case (builder_multiplexer_state) @@ -11372,14 +9215,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on always @(*) begin main_litedramcore_en0 <= 1'd0; case (builder_multiplexer_state) @@ -11407,14 +9243,7 @@ always @(*) begin main_litedramcore_en0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -11449,14 +9278,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_want_reads <= 1'd0; case (builder_multiplexer_state) @@ -11484,14 +9306,7 @@ always @(*) begin main_litedramcore_choose_req_want_reads <= 1'd1; end endcase -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) @@ -11519,9 +9334,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); @@ -11566,10 +9378,6 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on always @(*) begin main_litedramcore_interface_wdata <= 128'd0; case ({builder_new_master_wdata_ready1}) @@ -11580,14 +9388,7 @@ always @(*) begin main_litedramcore_interface_wdata <= 1'd0; end endcase -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on always @(*) begin main_litedramcore_interface_wdata_we <= 16'd0; case ({builder_new_master_wdata_ready1}) @@ -11598,9 +9399,6 @@ always @(*) begin main_litedramcore_interface_wdata_we <= 1'd0; end endcase -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on end assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; assign builder_roundrobin0_grant = 1'd0; @@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0; assign builder_roundrobin5_grant = 1'd0; assign builder_roundrobin6_grant = 1'd0; assign builder_roundrobin7_grant = 1'd0; - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on always @(*) begin builder_next_state <= 2'd0; builder_next_state <= builder_state; @@ -11631,14 +9425,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on always @(*) begin builder_litedramcore_we_next_value_ce2 <= 1'd0; case (builder_state) @@ -11653,14 +9440,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on always @(*) begin builder_litedramcore_wishbone_dat_r <= 32'd0; case (builder_state) @@ -11672,71 +9452,43 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on always @(*) begin - builder_litedramcore_wishbone_ack <= 1'd0; + builder_litedramcore_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin end 2'd2: begin - builder_litedramcore_wishbone_ack <= 1'd1; end default: begin + builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value0 <= 8'd0; + builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; case (builder_state) 1'd1: begin end 2'd2: begin end default: begin - builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; + builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; + builder_litedramcore_wishbone_ack <= 1'd0; case (builder_state) 1'd1: begin end 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; end default: begin - builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on always @(*) begin builder_litedramcore_adr_next_value1 <= 14'd0; case (builder_state) @@ -11751,14 +9503,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on always @(*) begin builder_litedramcore_adr_next_value_ce1 <= 1'd0; case (builder_state) @@ -11773,14 +9518,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on always @(*) begin builder_litedramcore_we_next_value2 <= 1'd0; case (builder_state) @@ -11795,9 +9533,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on end assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; @@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we; assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; assign main_wb_bus_err = builder_litedramcore_wishbone_err; -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on -always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; - end -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on always @(*) begin builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on end -assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on +assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on +end +always @(*) begin + builder_csrbank0_init_error0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_init_done0_w = main_init_done_storage; assign builder_csrbank0_init_error0_w = main_init_error_storage; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_337 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_338; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_338 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_339; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_339 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_340; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_340 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; @@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; - -// synthesis translate_off -reg dummy_d_341; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_control0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_341 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_342; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_342 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_343; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_343 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_344; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin builder_csrbank2_dfii_pi0_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_344 = dummy_s; -// synthesis translate_on end -assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_345; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_345 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_346; -// synthesis translate_on +assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_346 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_347; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_347 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_348; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_348 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_349; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_349 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_350; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_350 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_351; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_351 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_352; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_352 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_353; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_353 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_354; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_354 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_355; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_355 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_356; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_357 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_358; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_358 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_359; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_359 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_360; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_360 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_361; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_361 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_362; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_362 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_363; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_363 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_364; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_364 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_365; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_365 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_366; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_366 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_367; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_367 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_368; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_368 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_369; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_369 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_370; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_370 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_371; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_371 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_372; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_372 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_373; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_373 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_374; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_374 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_375; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin builder_csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_375 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_376; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_376 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_377; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_377 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_378; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_378 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_379; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_379 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_380; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_380 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_381; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_381 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_382; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_382 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_383; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_383 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_384; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_384 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_385; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_385 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_386; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_386 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_387; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_387 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_388; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_388 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_389; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_389 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_390; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_390 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_391; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_391 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_392; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_392 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_393; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_393 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_394; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_394 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_395; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_395 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_396; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_396 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_397; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_397 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_398; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_398 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_399; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_399 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_400; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_400 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_401; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_401 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_402; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_402 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_403; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_403 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_404; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_404 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_405; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_405 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_406; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_406 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_407; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_407 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_408; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_408 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_409; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_409 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_410; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_410 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_411; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_411 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_412; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_412 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_413; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_413 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_414; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_414 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_415; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_416; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_416 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_417; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_417 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_418; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_418 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_419; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_419 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_420; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_420 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_421; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_421 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_422; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_422 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_423; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_423 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_424; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_424 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[6:0]; - -// synthesis translate_off -reg dummy_d_425; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_425 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_426; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_426 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_427; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_427 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_428; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_428 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_429; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_429 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_430; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_430 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_431; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_431 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_432; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_432 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_433; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_433 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_434; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_434 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_435; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_435 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_436; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_436 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_437; -// synthesis translate_on +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_437 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_438; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_438 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_439; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_439 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_440; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_440 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_441; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_441 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_442; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_442 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_443; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_443 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_444; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_444 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_445; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_445 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_446; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_446 = dummy_s; -// synthesis translate_on end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; @@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; -assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[14:8]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0]; assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; -assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; -assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[14:8]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0]; assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; -assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; -assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[14:8]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0]; assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; -assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; -assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[14:8]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0]; assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; -assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_csr_interconnect_adr = builder_litedramcore_adr; assign builder_csr_interconnect_we = builder_litedramcore_we; assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; @@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); - -// synthesis translate_off -reg dummy_d_447; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13760,14 +10147,7 @@ always @(*) begin builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase -// synthesis translate_off - dummy_d_447 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_448; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed1 <= 15'd0; case (main_litedramcore_choose_cmd_grant) @@ -13796,14 +10176,7 @@ always @(*) begin builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_448 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_449; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed2 <= 3'd0; case (main_litedramcore_choose_cmd_grant) @@ -13832,14 +10205,7 @@ always @(*) begin builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_449 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_450; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed3 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13868,14 +10234,7 @@ always @(*) begin builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_450 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_451; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed4 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13904,14 +10263,7 @@ always @(*) begin builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_451 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_452; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed5 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13940,14 +10292,7 @@ always @(*) begin builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_452 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_453; -// synthesis translate_on always @(*) begin builder_t_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13976,14 +10321,7 @@ always @(*) begin builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_453 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_454; -// synthesis translate_on always @(*) begin builder_t_array_muxed1 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14012,14 +10350,7 @@ always @(*) begin builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_454 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_455; -// synthesis translate_on always @(*) begin builder_t_array_muxed2 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14048,14 +10379,7 @@ always @(*) begin builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_455 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_456; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed6 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14084,14 +10408,7 @@ always @(*) begin builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase -// synthesis translate_off - dummy_d_456 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_457; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed7 <= 15'd0; case (main_litedramcore_choose_req_grant) @@ -14120,14 +10437,7 @@ always @(*) begin builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_457 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_458; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed8 <= 3'd0; case (main_litedramcore_choose_req_grant) @@ -14156,14 +10466,7 @@ always @(*) begin builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_458 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_459; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed9 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14192,14 +10495,7 @@ always @(*) begin builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_459 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_460; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed10 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14228,14 +10524,7 @@ always @(*) begin builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_460 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_461; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed11 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14264,14 +10553,7 @@ always @(*) begin builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_461 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_462; -// synthesis translate_on always @(*) begin builder_t_array_muxed3 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14300,14 +10582,7 @@ always @(*) begin builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_462 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_463; -// synthesis translate_on always @(*) begin builder_t_array_muxed4 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14336,14 +10611,7 @@ always @(*) begin builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_463 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_464; -// synthesis translate_on always @(*) begin builder_t_array_muxed5 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14372,14 +10640,7 @@ always @(*) begin builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_464 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_465; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed12 <= 22'd0; case (builder_roundrobin0_grant) @@ -14387,14 +10648,7 @@ always @(*) begin builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_465 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_466; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed13 <= 1'd0; case (builder_roundrobin0_grant) @@ -14402,14 +10656,7 @@ always @(*) begin builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_466 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_467; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed14 <= 1'd0; case (builder_roundrobin0_grant) @@ -14417,14 +10664,7 @@ always @(*) begin builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_467 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_468; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed15 <= 22'd0; case (builder_roundrobin1_grant) @@ -14432,14 +10672,7 @@ always @(*) begin builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_468 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_469; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed16 <= 1'd0; case (builder_roundrobin1_grant) @@ -14447,14 +10680,7 @@ always @(*) begin builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_469 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_470; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed17 <= 1'd0; case (builder_roundrobin1_grant) @@ -14462,14 +10688,7 @@ always @(*) begin builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_470 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_471; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed18 <= 22'd0; case (builder_roundrobin2_grant) @@ -14477,14 +10696,7 @@ always @(*) begin builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_471 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_472; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed19 <= 1'd0; case (builder_roundrobin2_grant) @@ -14492,14 +10704,7 @@ always @(*) begin builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_472 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_473; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed20 <= 1'd0; case (builder_roundrobin2_grant) @@ -14507,14 +10712,7 @@ always @(*) begin builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_473 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_474; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed21 <= 22'd0; case (builder_roundrobin3_grant) @@ -14522,14 +10720,7 @@ always @(*) begin builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_474 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_475; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed22 <= 1'd0; case (builder_roundrobin3_grant) @@ -14537,14 +10728,7 @@ always @(*) begin builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_475 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_476; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed23 <= 1'd0; case (builder_roundrobin3_grant) @@ -14552,14 +10736,7 @@ always @(*) begin builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_476 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_477; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed24 <= 22'd0; case (builder_roundrobin4_grant) @@ -14567,14 +10744,7 @@ always @(*) begin builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_477 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_478; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed25 <= 1'd0; case (builder_roundrobin4_grant) @@ -14582,14 +10752,7 @@ always @(*) begin builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_478 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_479; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed26 <= 1'd0; case (builder_roundrobin4_grant) @@ -14597,14 +10760,7 @@ always @(*) begin builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_479 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_480; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed27 <= 22'd0; case (builder_roundrobin5_grant) @@ -14612,14 +10768,7 @@ always @(*) begin builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_480 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_481; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed28 <= 1'd0; case (builder_roundrobin5_grant) @@ -14627,14 +10776,7 @@ always @(*) begin builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_481 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_482; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed29 <= 1'd0; case (builder_roundrobin5_grant) @@ -14642,14 +10784,7 @@ always @(*) begin builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_482 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_483; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed30 <= 22'd0; case (builder_roundrobin6_grant) @@ -14657,14 +10792,7 @@ always @(*) begin builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_483 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_484; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed31 <= 1'd0; case (builder_roundrobin6_grant) @@ -14672,14 +10800,7 @@ always @(*) begin builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_484 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_485; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed32 <= 1'd0; case (builder_roundrobin6_grant) @@ -14687,14 +10808,7 @@ always @(*) begin builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_485 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_486; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed33 <= 22'd0; case (builder_roundrobin7_grant) @@ -14702,14 +10816,7 @@ always @(*) begin builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[24:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_486 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_487; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed34 <= 1'd0; case (builder_roundrobin7_grant) @@ -14717,14 +10824,7 @@ always @(*) begin builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_487 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_488; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed35 <= 1'd0; case (builder_roundrobin7_grant) @@ -14732,14 +10832,7 @@ always @(*) begin builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_488 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_489; -// synthesis translate_on always @(*) begin builder_array_muxed0 <= 3'd0; case (main_litedramcore_steerer_sel0) @@ -14756,14 +10849,7 @@ always @(*) begin builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_489 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_490; -// synthesis translate_on always @(*) begin builder_array_muxed1 <= 15'd0; case (main_litedramcore_steerer_sel0) @@ -14780,14 +10866,7 @@ always @(*) begin builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_490 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_491; -// synthesis translate_on always @(*) begin builder_array_muxed2 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14804,14 +10883,7 @@ always @(*) begin builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_491 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_492; -// synthesis translate_on always @(*) begin builder_array_muxed3 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14828,14 +10900,7 @@ always @(*) begin builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_492 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_493; -// synthesis translate_on always @(*) begin builder_array_muxed4 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14852,14 +10917,7 @@ always @(*) begin builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_493 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_494; -// synthesis translate_on always @(*) begin builder_array_muxed5 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14876,14 +10934,7 @@ always @(*) begin builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_494 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_495; -// synthesis translate_on always @(*) begin builder_array_muxed6 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14900,14 +10951,7 @@ always @(*) begin builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_495 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_496; -// synthesis translate_on always @(*) begin builder_array_muxed7 <= 3'd0; case (main_litedramcore_steerer_sel1) @@ -14924,14 +10968,7 @@ always @(*) begin builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_496 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_497; -// synthesis translate_on always @(*) begin builder_array_muxed8 <= 15'd0; case (main_litedramcore_steerer_sel1) @@ -14948,14 +10985,7 @@ always @(*) begin builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_497 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_498; -// synthesis translate_on always @(*) begin builder_array_muxed9 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14972,14 +11002,7 @@ always @(*) begin builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_498 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_499; -// synthesis translate_on always @(*) begin builder_array_muxed10 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14996,14 +11019,7 @@ always @(*) begin builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_499 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_500; -// synthesis translate_on always @(*) begin builder_array_muxed11 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15020,14 +11036,7 @@ always @(*) begin builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_500 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_501; -// synthesis translate_on always @(*) begin builder_array_muxed12 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15044,14 +11053,7 @@ always @(*) begin builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_501 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_502; -// synthesis translate_on always @(*) begin builder_array_muxed13 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15068,14 +11070,7 @@ always @(*) begin builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_502 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_503; -// synthesis translate_on always @(*) begin builder_array_muxed14 <= 3'd0; case (main_litedramcore_steerer_sel2) @@ -15092,14 +11087,7 @@ always @(*) begin builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_503 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_504; -// synthesis translate_on always @(*) begin builder_array_muxed15 <= 15'd0; case (main_litedramcore_steerer_sel2) @@ -15116,14 +11104,7 @@ always @(*) begin builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_504 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_505; -// synthesis translate_on always @(*) begin builder_array_muxed16 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15140,14 +11121,7 @@ always @(*) begin builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_505 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_506; -// synthesis translate_on always @(*) begin builder_array_muxed17 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15164,14 +11138,7 @@ always @(*) begin builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_506 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_507; -// synthesis translate_on always @(*) begin builder_array_muxed18 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15188,14 +11155,7 @@ always @(*) begin builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_507 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_508; -// synthesis translate_on always @(*) begin builder_array_muxed19 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15212,14 +11172,7 @@ always @(*) begin builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_508 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_509; -// synthesis translate_on always @(*) begin builder_array_muxed20 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15236,14 +11189,7 @@ always @(*) begin builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_509 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_510; -// synthesis translate_on always @(*) begin builder_array_muxed21 <= 3'd0; case (main_litedramcore_steerer_sel3) @@ -15260,14 +11206,7 @@ always @(*) begin builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_510 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_511; -// synthesis translate_on always @(*) begin builder_array_muxed22 <= 15'd0; case (main_litedramcore_steerer_sel3) @@ -15284,14 +11223,7 @@ always @(*) begin builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_511 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_512; -// synthesis translate_on always @(*) begin builder_array_muxed23 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15308,14 +11240,7 @@ always @(*) begin builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_512 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_513; -// synthesis translate_on always @(*) begin builder_array_muxed24 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15332,14 +11257,7 @@ always @(*) begin builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_513 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_514; -// synthesis translate_on always @(*) begin builder_array_muxed25 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15356,14 +11274,7 @@ always @(*) begin builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_514 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_515; -// synthesis translate_on always @(*) begin builder_array_muxed26 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15380,14 +11291,7 @@ always @(*) begin builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_515 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_516; -// synthesis translate_on always @(*) begin builder_array_muxed27 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15404,15 +11308,17 @@ always @(*) begin builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_516 = dummy_s; -// synthesis translate_on end assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge iodelay_clk) begin if ((main_reset_counter != 1'd0)) begin main_reset_counter <= (main_reset_counter - 1'd1); @@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end @@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; - if (builder_csrbank2_dfii_pi0_address1_re) begin - main_litedramcore_phaseinjector0_address_storage[14:8] <= builder_csrbank2_dfii_pi0_address1_r; - end if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; - if (builder_csrbank2_dfii_pi0_wrdata3_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; - end - if (builder_csrbank2_dfii_pi0_wrdata2_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; - end - if (builder_csrbank2_dfii_pi0_wrdata1_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; - end if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; - main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; - if (builder_csrbank2_dfii_pi1_address1_re) begin - main_litedramcore_phaseinjector1_address_storage[14:8] <= builder_csrbank2_dfii_pi1_address1_r; - end if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; - if (builder_csrbank2_dfii_pi1_wrdata3_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; - end - if (builder_csrbank2_dfii_pi1_wrdata2_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; - end - if (builder_csrbank2_dfii_pi1_wrdata1_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; - end if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; - main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; - if (builder_csrbank2_dfii_pi2_address1_re) begin - main_litedramcore_phaseinjector2_address_storage[14:8] <= builder_csrbank2_dfii_pi2_address1_r; - end if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; - if (builder_csrbank2_dfii_pi2_wrdata3_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; - end - if (builder_csrbank2_dfii_pi2_wrdata2_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; - end - if (builder_csrbank2_dfii_pi2_wrdata1_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; - end if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; - main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; - if (builder_csrbank2_dfii_pi3_address1_re) begin - main_litedramcore_phaseinjector3_address_storage[14:8] <= builder_csrbank2_dfii_pi3_address1_r; - end if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; - if (builder_csrbank2_dfii_pi3_wrdata3_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; - end - if (builder_csrbank2_dfii_pi3_wrdata2_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; - end - if (builder_csrbank2_dfii_pi3_wrdata1_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; - end if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; - main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin main_a7ddrphy_rst_storage <= 1'd0; main_a7ddrphy_rst_re <= 1'd0; @@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + BUFG BUFG( .I(main_clkout0), .O(main_clkout_buf0) @@ -19603,118 +15382,150 @@ IOBUF IOBUF_15( .O(main_a7ddrphy_dq_i_nodelay15) ); +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage[0:15]; -reg [24:0] memdat; +reg [24:0] storage_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_1[0:15]; -reg [24:0] memdat_1; +reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_2[0:15]; -reg [24:0] memdat_2; +reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_3[0:15]; -reg [24:0] memdat_3; +reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_4[0:15]; -reg [24:0] memdat_4; +reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_5[0:15]; -reg [24:0] memdat_5; +reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_6[0:15]; -reg [24:0] memdat_6; +reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | reg [24:0] storage_7[0:15]; -reg [24:0] memdat_7; +reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + FD FD( .C(main_clkin), .D(main_reset), @@ -19871,3 +15682,7 @@ PLLE2_ADV #( ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 08:32:10. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/orangecrab-85-0.2/litedram-initmem.vhdl b/litedram/generated/orangecrab-85-0.2/litedram-initmem.vhdl new file mode 100644 index 0000000..231249e --- /dev/null +++ b/litedram/generated/orangecrab-85-0.2/litedram-initmem.vhdl @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; + +entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); + port ( + clk : in std_ulogic; + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out + ); +end entity dram_init_mem; + +architecture rtl of dram_init_mem is + + constant INIT_RAM_SIZE : integer := 24576; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); + constant INIT_RAM_FILE : string := "litedram_core.init"; + + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; + end function; + + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; +begin + + init_ram_0: process(clk) + variable adr : integer; + begin + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; + end process; + + wb_out.stall <= '0'; + +end architecture rtl; diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init new file mode 100644 index 0000000..54fd98a --- /dev/null +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init @@ -0,0 +1,1955 @@ +4800002408000048 +01006b69a600607d +a602487d05009f42 +a64b5a7d14004a39 +2402004ca64b7b7d +602100003c200000 +6421ff00782107c6 +3d80000060215f00 +798c07c6618c0000 +618c10e0658cff00 +4e8004217d8903a6 +4e8004207c6903a6 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 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a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v new file mode 100644 index 0000000..e0e68fd --- /dev/null +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v @@ -0,0 +1,13190 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : LFE5U-85F-8MG285C +// LiteX sha1 : -------- +// Date : 2022-01-14 09:35:04 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + input wire rst, + output wire pll_locked, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + input wire [15:0] ddram_dq, + input wire [1:0] ddram_dqs_p, + input wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + input wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg crg_rst = 1'd0; +wire init_clk; +wire init_rst; +wire por_clk; +wire sys_clk; +wire sys_rst; +wire sys2x_clk; +wire sys2x_rst; +wire sys2x_i_clk; +wire crg_stop; +wire crg_reset0; +reg [15:0] crg_por_count = 16'd65535; +wire crg_por_done; +wire crg_sys2x_clk_ecsout; +wire crg_reset1; +wire crg_locked; +reg crg_stdby = 1'd0; +wire crg_clkin; +wire crg_clkout0; +wire crg_clkout1; +wire ddrphy_pause0; +wire ddrphy_stop0; +wire ddrphy_delay0; +wire ddrphy_reset0; +wire ddrphy_new_lock; +reg ddrphy_update = 1'd0; +reg ddrphy_stop1 = 1'd0; +reg ddrphy_freeze = 1'd0; +reg ddrphy_pause1 = 1'd0; +reg ddrphy_reset1 = 1'd0; +wire ddrphy_lock0; +wire ddrphy_delay1; +wire ddrphy_lock1; +reg ddrphy_lock_d = 1'd0; +reg [6:0] ddrphy_counter = 7'd0; +reg [1:0] ddrphy_dly_sel_storage = 2'd0; +reg ddrphy_dly_sel_re = 1'd0; +reg ddrphy_rdly_dq_rst_re = 1'd0; +wire ddrphy_rdly_dq_rst_r; +reg ddrphy_rdly_dq_rst_we = 1'd0; +reg ddrphy_rdly_dq_rst_w = 1'd0; +reg ddrphy_rdly_dq_inc_re = 1'd0; +wire ddrphy_rdly_dq_inc_r; +reg ddrphy_rdly_dq_inc_we = 1'd0; +reg ddrphy_rdly_dq_inc_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_rst_r; +reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_r; +reg ddrphy_rdly_dq_bitslip_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_w = 1'd0; +reg ddrphy_burstdet_clr_re = 1'd0; +wire ddrphy_burstdet_clr_r; +reg ddrphy_burstdet_clr_we = 1'd0; +reg ddrphy_burstdet_clr_w = 1'd0; +reg [1:0] ddrphy_burstdet_seen_status = 2'd0; +wire ddrphy_burstdet_seen_we; +reg ddrphy_burstdet_seen_re = 1'd0; +wire [1:0] ddrphy_datavalid; +wire [14:0] ddrphy_dfi_p0_address; +wire [2:0] ddrphy_dfi_p0_bank; +wire ddrphy_dfi_p0_cas_n; +wire ddrphy_dfi_p0_cs_n; +wire ddrphy_dfi_p0_ras_n; +wire ddrphy_dfi_p0_we_n; +wire ddrphy_dfi_p0_cke; +wire ddrphy_dfi_p0_odt; +wire ddrphy_dfi_p0_reset_n; +wire ddrphy_dfi_p0_act_n; +wire [63:0] ddrphy_dfi_p0_wrdata; +wire ddrphy_dfi_p0_wrdata_en; +wire [7:0] ddrphy_dfi_p0_wrdata_mask; +wire ddrphy_dfi_p0_rddata_en; +reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; +wire ddrphy_dfi_p0_rddata_valid; +wire [14:0] ddrphy_dfi_p1_address; +wire [2:0] ddrphy_dfi_p1_bank; +wire ddrphy_dfi_p1_cas_n; +wire ddrphy_dfi_p1_cs_n; +wire ddrphy_dfi_p1_ras_n; +wire ddrphy_dfi_p1_we_n; +wire ddrphy_dfi_p1_cke; +wire ddrphy_dfi_p1_odt; +wire ddrphy_dfi_p1_reset_n; +wire ddrphy_dfi_p1_act_n; +wire [63:0] ddrphy_dfi_p1_wrdata; +wire ddrphy_dfi_p1_wrdata_en; +wire [7:0] ddrphy_dfi_p1_wrdata_mask; +wire ddrphy_dfi_p1_rddata_en; +reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; +wire ddrphy_dfi_p1_rddata_valid; +wire ddrphy_bl8_chunk; +wire ddrphy_pad_oddrx2f0; +wire ddrphy_pad_oddrx2f1; +wire ddrphy_pad_oddrx2f2; +wire ddrphy_pad_oddrx2f3; +wire ddrphy_pad_oddrx2f4; +wire ddrphy_pad_oddrx2f5; +wire ddrphy_pad_oddrx2f6; +wire ddrphy_pad_oddrx2f7; +wire ddrphy_pad_oddrx2f8; +wire ddrphy_pad_oddrx2f9; +wire ddrphy_pad_oddrx2f10; +wire ddrphy_pad_oddrx2f11; +wire ddrphy_pad_oddrx2f12; +wire ddrphy_pad_oddrx2f13; +wire ddrphy_pad_oddrx2f14; +wire ddrphy_pad_oddrx2f15; +wire ddrphy_pad_oddrx2f16; +wire ddrphy_pad_oddrx2f17; +wire ddrphy_pad_oddrx2f18; +wire ddrphy_pad_oddrx2f19; +wire ddrphy_pad_oddrx2f20; +wire ddrphy_pad_oddrx2f21; +wire ddrphy_pad_oddrx2f22; +wire ddrphy_pad_oddrx2f23; +wire ddrphy_pad_oddrx2f24; +wire ddrphy_pad_oddrx2f25; +wire ddrphy_dq_oe; +wire ddrphy_dqs_re; +wire ddrphy_dqs_oe; +wire ddrphy_dqs_postamble; +wire ddrphy_dqs_preamble; +wire ddrphy_dqs_i0; +wire ddrphy_dqsr900; +wire ddrphy_dqsw2700; +wire ddrphy_dqsw0; +wire [2:0] ddrphy_rdpntr0; +wire [2:0] ddrphy_wrpntr0; +reg [6:0] ddrphy_rdly0 = 7'd0; +wire ddrphy_burstdet0; +reg ddrphy_burstdet_d0 = 1'd0; +wire ddrphy_dqs0; +wire ddrphy_dqs_oe_n0; +reg [7:0] ddrphy_dm_o_data0 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; +wire ddrphy_dq_o0; +wire ddrphy_dq_i0; +wire ddrphy_dq_oe_n0; +wire ddrphy_dq_i_delayed0; +wire [7:0] ddrphy_dq_i_data0; +reg [7:0] ddrphy_dq_o_data0 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; +wire [3:0] ddrphy_bitslip0_i; +reg [3:0] ddrphy_bitslip0_o = 4'd0; +reg [1:0] ddrphy_bitslip0_value = 2'd0; +reg [7:0] ddrphy_bitslip0_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; +wire ddrphy_dq_o1; +wire ddrphy_dq_i1; +wire ddrphy_dq_oe_n1; +wire ddrphy_dq_i_delayed1; +wire [7:0] ddrphy_dq_i_data1; +reg [7:0] ddrphy_dq_o_data1 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; +wire [3:0] ddrphy_bitslip1_i; +reg [3:0] ddrphy_bitslip1_o = 4'd0; +reg [1:0] ddrphy_bitslip1_value = 2'd0; +reg [7:0] ddrphy_bitslip1_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; +wire ddrphy_dq_o2; +wire ddrphy_dq_i2; +wire ddrphy_dq_oe_n2; +wire ddrphy_dq_i_delayed2; +wire [7:0] ddrphy_dq_i_data2; +reg [7:0] ddrphy_dq_o_data2 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; +wire [3:0] ddrphy_bitslip2_i; +reg [3:0] ddrphy_bitslip2_o = 4'd0; +reg [1:0] ddrphy_bitslip2_value = 2'd0; +reg [7:0] ddrphy_bitslip2_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; +wire ddrphy_dq_o3; +wire ddrphy_dq_i3; +wire ddrphy_dq_oe_n3; +wire ddrphy_dq_i_delayed3; +wire [7:0] ddrphy_dq_i_data3; +reg [7:0] ddrphy_dq_o_data3 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; +wire [3:0] ddrphy_bitslip3_i; +reg [3:0] ddrphy_bitslip3_o = 4'd0; +reg [1:0] ddrphy_bitslip3_value = 2'd0; +reg [7:0] ddrphy_bitslip3_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; +wire ddrphy_dq_o4; +wire ddrphy_dq_i4; +wire ddrphy_dq_oe_n4; +wire ddrphy_dq_i_delayed4; +wire [7:0] ddrphy_dq_i_data4; +reg [7:0] ddrphy_dq_o_data4 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; +wire [3:0] ddrphy_bitslip4_i; +reg [3:0] ddrphy_bitslip4_o = 4'd0; +reg [1:0] ddrphy_bitslip4_value = 2'd0; +reg [7:0] ddrphy_bitslip4_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; +wire ddrphy_dq_o5; +wire ddrphy_dq_i5; +wire ddrphy_dq_oe_n5; +wire ddrphy_dq_i_delayed5; +wire [7:0] ddrphy_dq_i_data5; +reg [7:0] ddrphy_dq_o_data5 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; +wire [3:0] ddrphy_bitslip5_i; +reg [3:0] ddrphy_bitslip5_o = 4'd0; +reg [1:0] ddrphy_bitslip5_value = 2'd0; +reg [7:0] ddrphy_bitslip5_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; +wire ddrphy_dq_o6; +wire ddrphy_dq_i6; +wire ddrphy_dq_oe_n6; +wire ddrphy_dq_i_delayed6; +wire [7:0] ddrphy_dq_i_data6; +reg [7:0] ddrphy_dq_o_data6 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; +wire [3:0] ddrphy_bitslip6_i; +reg [3:0] ddrphy_bitslip6_o = 4'd0; +reg [1:0] ddrphy_bitslip6_value = 2'd0; +reg [7:0] ddrphy_bitslip6_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; +wire ddrphy_dq_o7; +wire ddrphy_dq_i7; +wire ddrphy_dq_oe_n7; +wire ddrphy_dq_i_delayed7; +wire [7:0] ddrphy_dq_i_data7; +reg [7:0] ddrphy_dq_o_data7 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; +wire [3:0] ddrphy_bitslip7_i; +reg [3:0] ddrphy_bitslip7_o = 4'd0; +reg [1:0] ddrphy_bitslip7_value = 2'd0; +reg [7:0] ddrphy_bitslip7_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; +wire ddrphy_dqs_i1; +wire ddrphy_dqsr901; +wire ddrphy_dqsw2701; +wire ddrphy_dqsw1; +wire [2:0] ddrphy_rdpntr1; +wire [2:0] ddrphy_wrpntr1; +reg [6:0] ddrphy_rdly1 = 7'd0; +wire ddrphy_burstdet1; +reg ddrphy_burstdet_d1 = 1'd0; +wire ddrphy_dqs1; +wire ddrphy_dqs_oe_n1; +reg [7:0] ddrphy_dm_o_data1 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; +wire ddrphy_dq_o8; +wire ddrphy_dq_i8; +wire ddrphy_dq_oe_n8; +wire ddrphy_dq_i_delayed8; +wire [7:0] ddrphy_dq_i_data8; +reg [7:0] ddrphy_dq_o_data8 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; +wire [3:0] ddrphy_bitslip8_i; +reg [3:0] ddrphy_bitslip8_o = 4'd0; +reg [1:0] ddrphy_bitslip8_value = 2'd0; +reg [7:0] ddrphy_bitslip8_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; +wire ddrphy_dq_o9; +wire ddrphy_dq_i9; +wire ddrphy_dq_oe_n9; +wire ddrphy_dq_i_delayed9; +wire [7:0] ddrphy_dq_i_data9; +reg [7:0] ddrphy_dq_o_data9 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; +wire [3:0] ddrphy_bitslip9_i; +reg [3:0] ddrphy_bitslip9_o = 4'd0; +reg [1:0] ddrphy_bitslip9_value = 2'd0; +reg [7:0] ddrphy_bitslip9_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; +wire ddrphy_dq_o10; +wire ddrphy_dq_i10; +wire ddrphy_dq_oe_n10; +wire ddrphy_dq_i_delayed10; +wire [7:0] ddrphy_dq_i_data10; +reg [7:0] ddrphy_dq_o_data10 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; +wire [3:0] ddrphy_bitslip10_i; +reg [3:0] ddrphy_bitslip10_o = 4'd0; +reg [1:0] ddrphy_bitslip10_value = 2'd0; +reg [7:0] ddrphy_bitslip10_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; +wire ddrphy_dq_o11; +wire ddrphy_dq_i11; +wire ddrphy_dq_oe_n11; +wire ddrphy_dq_i_delayed11; +wire [7:0] ddrphy_dq_i_data11; +reg [7:0] ddrphy_dq_o_data11 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; +wire [3:0] ddrphy_bitslip11_i; +reg [3:0] ddrphy_bitslip11_o = 4'd0; +reg [1:0] ddrphy_bitslip11_value = 2'd0; +reg [7:0] ddrphy_bitslip11_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; +wire ddrphy_dq_o12; +wire ddrphy_dq_i12; +wire ddrphy_dq_oe_n12; +wire ddrphy_dq_i_delayed12; +wire [7:0] ddrphy_dq_i_data12; +reg [7:0] ddrphy_dq_o_data12 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; +wire [3:0] ddrphy_bitslip12_i; +reg [3:0] ddrphy_bitslip12_o = 4'd0; +reg [1:0] ddrphy_bitslip12_value = 2'd0; +reg [7:0] ddrphy_bitslip12_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; +wire ddrphy_dq_o13; +wire ddrphy_dq_i13; +wire ddrphy_dq_oe_n13; +wire ddrphy_dq_i_delayed13; +wire [7:0] ddrphy_dq_i_data13; +reg [7:0] ddrphy_dq_o_data13 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; +wire [3:0] ddrphy_bitslip13_i; +reg [3:0] ddrphy_bitslip13_o = 4'd0; +reg [1:0] ddrphy_bitslip13_value = 2'd0; +reg [7:0] ddrphy_bitslip13_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; +wire ddrphy_dq_o14; +wire ddrphy_dq_i14; +wire ddrphy_dq_oe_n14; +wire ddrphy_dq_i_delayed14; +wire [7:0] ddrphy_dq_i_data14; +reg [7:0] ddrphy_dq_o_data14 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; +wire [3:0] ddrphy_bitslip14_i; +reg [3:0] ddrphy_bitslip14_o = 4'd0; +reg [1:0] ddrphy_bitslip14_value = 2'd0; +reg [7:0] ddrphy_bitslip14_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; +wire ddrphy_dq_o15; +wire ddrphy_dq_i15; +wire ddrphy_dq_oe_n15; +wire ddrphy_dq_i_delayed15; +wire [7:0] ddrphy_dq_i_data15; +reg [7:0] ddrphy_dq_o_data15 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; +wire [3:0] ddrphy_bitslip15_i; +reg [3:0] ddrphy_bitslip15_o = 4'd0; +reg [1:0] ddrphy_bitslip15_value = 2'd0; +reg [7:0] ddrphy_bitslip15_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; +reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; +wire [14:0] litedramcore_inti_p0_address; +wire [2:0] litedramcore_inti_p0_bank; +reg litedramcore_inti_p0_cas_n = 1'd1; +reg litedramcore_inti_p0_cs_n = 1'd1; +reg litedramcore_inti_p0_ras_n = 1'd1; +reg litedramcore_inti_p0_we_n = 1'd1; +wire litedramcore_inti_p0_cke; +wire litedramcore_inti_p0_odt; +wire litedramcore_inti_p0_reset_n; +reg litedramcore_inti_p0_act_n = 1'd1; +wire [63:0] litedramcore_inti_p0_wrdata; +wire litedramcore_inti_p0_wrdata_en; +wire [7:0] litedramcore_inti_p0_wrdata_mask; +wire litedramcore_inti_p0_rddata_en; +reg [63:0] litedramcore_inti_p0_rddata = 64'd0; +reg litedramcore_inti_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_inti_p1_address; +wire [2:0] litedramcore_inti_p1_bank; +reg litedramcore_inti_p1_cas_n = 1'd1; +reg litedramcore_inti_p1_cs_n = 1'd1; +reg litedramcore_inti_p1_ras_n = 1'd1; +reg litedramcore_inti_p1_we_n = 1'd1; +wire litedramcore_inti_p1_cke; +wire litedramcore_inti_p1_odt; +wire litedramcore_inti_p1_reset_n; +reg litedramcore_inti_p1_act_n = 1'd1; +wire [63:0] litedramcore_inti_p1_wrdata; +wire litedramcore_inti_p1_wrdata_en; +wire [7:0] litedramcore_inti_p1_wrdata_mask; +wire litedramcore_inti_p1_rddata_en; +reg [63:0] litedramcore_inti_p1_rddata = 64'd0; +reg litedramcore_inti_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [63:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [7:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [63:0] litedramcore_slave_p0_rddata = 64'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [63:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [7:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [63:0] litedramcore_slave_p1_rddata = 64'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [63:0] litedramcore_master_p0_wrdata = 64'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [63:0] litedramcore_master_p1_wrdata = 64'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [8:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [8:0] litedramcore_timer_count1 = 9'd374; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [6:0] litedramcore_sequencer_counter = 7'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [25:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [5:0] litedramcore_zqcs_executer_counter = 6'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire litedramcore_bankmachine0_cmd_buffer_sink_first; +wire litedramcore_bankmachine0_cmd_buffer_sink_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_source_ready; +reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0; +wire litedramcore_bankmachine0_trascon_valid; +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire litedramcore_bankmachine1_cmd_buffer_sink_first; +wire litedramcore_bankmachine1_cmd_buffer_sink_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_source_ready; +reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0; +wire litedramcore_bankmachine1_trascon_valid; +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire litedramcore_bankmachine2_cmd_buffer_sink_first; +wire litedramcore_bankmachine2_cmd_buffer_sink_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_source_ready; +reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0; +wire litedramcore_bankmachine2_trascon_valid; +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire litedramcore_bankmachine3_cmd_buffer_sink_first; +wire litedramcore_bankmachine3_cmd_buffer_sink_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_source_ready; +reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0; +wire litedramcore_bankmachine3_trascon_valid; +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire litedramcore_bankmachine4_cmd_buffer_sink_first; +wire litedramcore_bankmachine4_cmd_buffer_sink_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_source_ready; +reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0; +wire litedramcore_bankmachine4_trascon_valid; +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire litedramcore_bankmachine5_cmd_buffer_sink_first; +wire litedramcore_bankmachine5_cmd_buffer_sink_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_source_ready; +reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0; +wire litedramcore_bankmachine5_trascon_valid; +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire litedramcore_bankmachine6_cmd_buffer_sink_first; +wire litedramcore_bankmachine6_cmd_buffer_sink_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_source_ready; +reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0; +wire litedramcore_bankmachine6_trascon_valid; +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire litedramcore_bankmachine7_cmd_buffer_sink_first; +wire litedramcore_bankmachine7_cmd_buffer_sink_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_source_ready; +reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0; +wire litedramcore_bankmachine7_trascon_valid; +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +wire litedramcore_trrdcon_valid; +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +reg litedramcore_tfawcon_ready = 1'd1; +wire [1:0] litedramcore_tfawcon_count; +reg [2:0] litedramcore_tfawcon_window = 3'd0; +wire litedramcore_tccdcon_valid; +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +wire litedramecp5ddrphycrg_ecp5pll; +wire litedramecp5ddrphycrg_locked; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [2:0] litedramcore_bankmachine0_state = 3'd0; +reg [2:0] litedramcore_bankmachine0_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine1_state = 3'd0; +reg [2:0] litedramcore_bankmachine1_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine2_state = 3'd0; +reg [2:0] litedramcore_bankmachine2_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine3_state = 3'd0; +reg [2:0] litedramcore_bankmachine3_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine4_state = 3'd0; +reg [2:0] litedramcore_bankmachine4_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine5_state = 3'd0; +reg [2:0] litedramcore_bankmachine5_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine6_state = 3'd0; +reg [2:0] litedramcore_bankmachine6_next_state = 3'd0; +reg [2:0] litedramcore_bankmachine7_state = 3'd0; +reg [2:0] litedramcore_bankmachine7_next_state = 3'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_wdata_ready2 = 1'd0; +reg litedramcore_new_master_wdata_ready3 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg litedramcore_new_master_rdata_valid9 = 1'd0; +reg litedramcore_new_master_rdata_valid10 = 1'd0; +reg litedramcore_new_master_rdata_valid11 = 1'd0; +reg litedramcore_new_master_rdata_valid12 = 1'd0; +reg litedramcore_new_master_rdata_valid13 = 1'd0; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_burstdet_seen_re = 1'd0; +wire [1:0] csrbank1_burstdet_seen_r; +reg csrbank1_burstdet_seen_we = 1'd0; +wire [1:0] csrbank1_burstdet_seen_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_r; +reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_r; +reg csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_w; +reg csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_r; +reg csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_r; +reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_r; +reg csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_w; +reg csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_r; +reg csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +reg [1:0] state = 2'd0; +reg [1:0] next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [14:0] rhs_array_muxed1 = 15'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [14:0] rhs_array_muxed7 = 15'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [21:0] rhs_array_muxed12 = 22'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [21:0] rhs_array_muxed15 = 22'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [21:0] rhs_array_muxed18 = 22'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [21:0] rhs_array_muxed21 = 22'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [21:0] rhs_array_muxed24 = 22'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [21:0] rhs_array_muxed27 = 22'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [21:0] rhs_array_muxed30 = 22'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [21:0] rhs_array_muxed33 = 22'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [14:0] array_muxed1 = 15'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [14:0] array_muxed8 = 15'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +wire latticeecp5asyncresetsynchronizerimpl0_rst1; +wire latticeecp5asyncresetsynchronizerimpl0_expr; +wire latticeecp5asyncresetsynchronizerimpl1_rst1; +wire latticeecp5asyncresetsynchronizerimpl2_rst1; +wire latticeecp5asyncresetsynchronizerimpl3_rst1; +reg regs0 = 1'd0; +reg regs1 = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign crg_stop = ddrphy_stop0; +assign crg_reset0 = ddrphy_reset0; +assign init_done = init_done_storage; +assign init_error = init_error_storage; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign user_enable = 1'd1; +assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); +assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); +assign user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); +assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); +assign user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); +assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); +assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign por_clk = clk; +assign crg_por_done = (crg_por_count == 1'd0); +assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst); +assign pll_locked = crg_locked; +assign crg_clkin = clk; +assign sys2x_i_clk = crg_clkout0; +assign init_clk = crg_clkout1; +assign crg_locked = (litedramecp5ddrphycrg_locked & (~crg_reset1)); +always @(*) begin + ddrphy_dm_o_data0 <= 8'd0; + ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1]; + ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[3]; + ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[5]; + ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[7]; + ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1]; + ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[3]; + ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[5]; + ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[7]; +end +always @(*) begin + ddrphy_dq_o_data0 <= 8'd0; + ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0]; + ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[16]; + ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[32]; + ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[48]; + ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0]; + ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[16]; + ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[32]; + ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[48]; +end +assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0}; +always @(*) begin + ddrphy_dfi_p0_rddata <= 64'd0; + ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0]; + ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data0[1]; + ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[2]; + ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data0[3]; + ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0]; + ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data1[1]; + ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[2]; + ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data1[3]; + ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0]; + ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data2[1]; + ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[2]; + ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data2[3]; + ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0]; + ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data3[1]; + ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[2]; + ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data3[3]; + ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0]; + ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data4[1]; + ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[2]; + ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data4[3]; + ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0]; + ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data5[1]; + ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[2]; + ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data5[3]; + ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0]; + ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data6[1]; + ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[2]; + ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data6[3]; + ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0]; + ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data7[1]; + ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[2]; + ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data7[3]; + ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0]; + ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data8[1]; + ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[2]; + ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data8[3]; + ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0]; + ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data9[1]; + ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[2]; + ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data9[3]; + ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0]; + ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data10[1]; + ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[2]; + ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data10[3]; + ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0]; + ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data11[1]; + ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[2]; + ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data11[3]; + ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0]; + ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data12[1]; + ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[2]; + ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data12[3]; + ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0]; + ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data13[1]; + ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[2]; + ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data13[3]; + ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0]; + ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data14[1]; + ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[2]; + ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data14[3]; + ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0]; + ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data15[1]; + ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[2]; + ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data15[3]; +end +always @(*) begin + ddrphy_dfi_p1_rddata <= 64'd0; + ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4]; + ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data0[5]; + ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[6]; + ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data0[7]; + ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4]; + ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data1[5]; + ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[6]; + ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data1[7]; + ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4]; + ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data2[5]; + ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[6]; + ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data2[7]; + ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4]; + ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data3[5]; + ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[6]; + ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data3[7]; + ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4]; + ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data4[5]; + ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[6]; + ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data4[7]; + ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4]; + ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data5[5]; + ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[6]; + ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data5[7]; + ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4]; + ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data6[5]; + ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[6]; + ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data6[7]; + ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4]; + ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data7[5]; + ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[6]; + ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data7[7]; + ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4]; + ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data8[5]; + ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[6]; + ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data8[7]; + ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4]; + ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data9[5]; + ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[6]; + ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data9[7]; + ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4]; + ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data10[5]; + ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[6]; + ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data10[7]; + ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4]; + ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data11[5]; + ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[6]; + ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data11[7]; + ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4]; + ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data12[5]; + ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[6]; + ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data12[7]; + ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4]; + ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data13[5]; + ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[6]; + ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data13[7]; + ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4]; + ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data14[5]; + ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[6]; + ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data14[7]; + ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4]; + ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data15[5]; + ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[6]; + ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data15[7]; +end +always @(*) begin + ddrphy_dq_o_data1 <= 8'd0; + ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1]; + ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[17]; + ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[33]; + ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[49]; + ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1]; + ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[17]; + ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[33]; + ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[49]; +end +assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1}; +always @(*) begin + ddrphy_dq_o_data2 <= 8'd0; + ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2]; + ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[18]; + ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[34]; + ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[50]; + ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2]; + ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[18]; + ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[34]; + ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[50]; +end +assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2}; +always @(*) begin + ddrphy_dq_o_data3 <= 8'd0; + ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3]; + ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[19]; + ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[35]; + ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[51]; + ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3]; + ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[19]; + ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[35]; + ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[51]; +end +assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3}; +always @(*) begin + ddrphy_dq_o_data4 <= 8'd0; + ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4]; + ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[20]; + ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[36]; + ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[52]; + ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4]; + ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[20]; + ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[36]; + ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[52]; +end +assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4}; +always @(*) begin + ddrphy_dq_o_data5 <= 8'd0; + ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5]; + ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[21]; + ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[37]; + ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[53]; + ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5]; + ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[21]; + ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[37]; + ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[53]; +end +assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5}; +always @(*) begin + ddrphy_dq_o_data6 <= 8'd0; + ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6]; + ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[22]; + ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[38]; + ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[54]; + ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6]; + ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[22]; + ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[38]; + ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[54]; +end +assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6}; +always @(*) begin + ddrphy_dq_o_data7 <= 8'd0; + ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7]; + ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[23]; + ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[39]; + ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[55]; + ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7]; + ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[23]; + ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[39]; + ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[55]; +end +assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7}; +always @(*) begin + ddrphy_dm_o_data1 <= 8'd0; + ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0]; + ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[2]; + ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[4]; + ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[6]; + ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0]; + ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[2]; + ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[4]; + ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[6]; +end +always @(*) begin + ddrphy_dq_o_data8 <= 8'd0; + ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8]; + ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[24]; + ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[40]; + ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[56]; + ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8]; + ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[24]; + ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[40]; + ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[56]; +end +assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8}; +always @(*) begin + ddrphy_dq_o_data9 <= 8'd0; + ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9]; + ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[25]; + ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[41]; + ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[57]; + ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9]; + ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[25]; + ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[41]; + ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[57]; +end +assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9}; +always @(*) begin + ddrphy_dq_o_data10 <= 8'd0; + ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10]; + ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[26]; + ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[42]; + ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[58]; + ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10]; + ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[26]; + ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[42]; + ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[58]; +end +assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10}; +always @(*) begin + ddrphy_dq_o_data11 <= 8'd0; + ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11]; + ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[27]; + ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[43]; + ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[59]; + ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11]; + ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[27]; + ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[43]; + ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[59]; +end +assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11}; +always @(*) begin + ddrphy_dq_o_data12 <= 8'd0; + ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12]; + ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[28]; + ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[44]; + ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[60]; + ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12]; + ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[28]; + ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[44]; + ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[60]; +end +assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12}; +always @(*) begin + ddrphy_dq_o_data13 <= 8'd0; + ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13]; + ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[29]; + ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[45]; + ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[61]; + ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13]; + ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[29]; + ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[45]; + ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[61]; +end +assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13}; +always @(*) begin + ddrphy_dq_o_data14 <= 8'd0; + ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14]; + ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[30]; + ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[46]; + ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[62]; + ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14]; + ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[30]; + ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[46]; + ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[62]; +end +assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14}; +always @(*) begin + ddrphy_dq_o_data15 <= 8'd0; + ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15]; + ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[31]; + ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[47]; + ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[63]; + ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15]; + ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[31]; + ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[47]; + ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[63]; +end +assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15}; +assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12; +assign ddrphy_dfi_p1_rddata_valid = ddrphy_rddata_en_tappeddelayline12; +assign ddrphy_dqs_re = (ddrphy_rddata_en_tappeddelayline3 | ddrphy_rddata_en_tappeddelayline4); +assign ddrphy_dq_oe = (ddrphy_wrdata_en_tappeddelayline3 | ddrphy_wrdata_en_tappeddelayline4); +assign ddrphy_bl8_chunk = ddrphy_wrdata_en_tappeddelayline3; +assign ddrphy_dqs_oe = ddrphy_dq_oe; +assign ddrphy_dqs_preamble = (ddrphy_wrdata_en_tappeddelayline2 & (~ddrphy_wrdata_en_tappeddelayline3)); +assign ddrphy_dqs_postamble = (ddrphy_wrdata_en_tappeddelayline5 & (~ddrphy_wrdata_en_tappeddelayline4)); +assign ddrphy_new_lock = (ddrphy_lock1 & (~ddrphy_lock_d)); +assign ddrphy_pause0 = ddrphy_pause1; +assign ddrphy_stop0 = ddrphy_stop1; +assign ddrphy_delay0 = ddrphy_delay1; +assign ddrphy_reset0 = ddrphy_reset1; +always @(*) begin + ddrphy_bitslip0_o <= 4'd0; + case (ddrphy_bitslip0_value) + 1'd0: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip1_o <= 4'd0; + case (ddrphy_bitslip1_value) + 1'd0: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip2_o <= 4'd0; + case (ddrphy_bitslip2_value) + 1'd0: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip3_o <= 4'd0; + case (ddrphy_bitslip3_value) + 1'd0: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip4_o <= 4'd0; + case (ddrphy_bitslip4_value) + 1'd0: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip5_o <= 4'd0; + case (ddrphy_bitslip5_value) + 1'd0: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip6_o <= 4'd0; + case (ddrphy_bitslip6_value) + 1'd0: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip7_o <= 4'd0; + case (ddrphy_bitslip7_value) + 1'd0: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip8_o <= 4'd0; + case (ddrphy_bitslip8_value) + 1'd0: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip9_o <= 4'd0; + case (ddrphy_bitslip9_value) + 1'd0: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip10_o <= 4'd0; + case (ddrphy_bitslip10_value) + 1'd0: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip11_o <= 4'd0; + case (ddrphy_bitslip11_value) + 1'd0: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip12_o <= 4'd0; + case (ddrphy_bitslip12_value) + 1'd0: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip13_o <= 4'd0; + case (ddrphy_bitslip13_value) + 1'd0: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip14_o <= 4'd0; + case (ddrphy_bitslip14_value) + 1'd0: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip15_o <= 4'd0; + case (ddrphy_bitslip15_value) + 1'd0: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3]; + end + endcase +end +assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; +assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; +assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; +assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; +assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; +assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; +assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; +assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; +assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; +assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; +assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; +assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; +assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; +assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; +assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata; +assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid; +assign ddrphy_dfi_p1_address = litedramcore_master_p1_address; +assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; +assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; +assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; +assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; +assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; +assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; +assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; +assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; +assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; +assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; +assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; +assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; +assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; +assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata; +assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid; +assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; +assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; +assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; +assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; +assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; +assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; +assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; +assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; +assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; +assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; +assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; +assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; +assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; +assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; +assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; +assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; +assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; +assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; +assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; +assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; +assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; +assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; +assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; +assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; +assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; +assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; +assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; +assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; +assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; +assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; +assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; +assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; +always @(*) begin + litedramcore_slave_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 15'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_inti_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; + end +end +always @(*) begin + litedramcore_inti_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; + end +end +always @(*) begin + litedramcore_inti_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 64'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 15'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_inti_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; + end +end +always @(*) begin + litedramcore_inti_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; + end +end +always @(*) begin + litedramcore_inti_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 64'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + end +end +assign litedramcore_inti_p0_cke = litedramcore_cke; +assign litedramcore_inti_p1_cke = litedramcore_cke; +assign litedramcore_inti_p0_odt = litedramcore_odt; +assign litedramcore_inti_p1_odt = litedramcore_odt; +assign litedramcore_inti_p0_reset_n = litedramcore_reset_n; +assign litedramcore_inti_p1_reset_n = litedramcore_reset_n; +always @(*) begin + litedramcore_inti_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); + end else begin + litedramcore_inti_p0_ras_n <= 1'd1; + end +end +always @(*) begin + litedramcore_inti_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); + end else begin + litedramcore_inti_p0_we_n <= 1'd1; + end +end +always @(*) begin + litedramcore_inti_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); + end else begin + litedramcore_inti_p0_cas_n <= 1'd1; + end +end +always @(*) begin + litedramcore_inti_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + litedramcore_inti_p0_cs_n <= {1{1'd1}}; + end +end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); + end else begin + litedramcore_inti_p1_ras_n <= 1'd1; + end +end +always @(*) begin + litedramcore_inti_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); + end else begin + litedramcore_inti_p1_we_n <= 1'd1; + end +end +always @(*) begin + litedramcore_inti_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); + end else begin + litedramcore_inti_p1_cas_n <= 1'd1; + end +end +always @(*) begin + litedramcore_inti_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + litedramcore_inti_p1_cs_n <= {1{1'd1}}; + end +end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; +assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; +assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; +assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; +assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; +assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; +assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; +assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; +assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; +assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; +assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; +assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; +assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; +assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; +assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; +assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; +assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; +assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; +assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; +assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; +assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; +assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; +assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; +assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; +assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; +assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; +assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; +assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; +assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; +assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; +assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; +assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; +assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; +assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; +assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; +assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; +assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; +assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; +assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; +assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; +assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; +assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; +assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; +assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; +assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; +assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; +assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; +assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; +assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; +assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; +assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; +assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; +assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; +assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; +assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; +assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; +assign litedramcore_timer_wait = (~litedramcore_timer_done0); +assign litedramcore_postponer_req_i = litedramcore_timer_done0; +assign litedramcore_wants_refresh = litedramcore_postponer_req_o; +assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; +assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); +assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); +assign litedramcore_timer_done0 = litedramcore_timer_done1; +assign litedramcore_timer_count0 = litedramcore_timer_count1; +assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); +assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); +assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); +assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; +assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; +always @(*) begin + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); +assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +always @(*) begin + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine0_next_state <= 3'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); +assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +always @(*) begin + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine1_next_state <= 3'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); +assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +always @(*) begin + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine2_next_state <= 3'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); +assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +always @(*) begin + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine3_next_state <= 3'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); +assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +always @(*) begin + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine4_next_state <= 3'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); +assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +always @(*) begin + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine5_next_state <= 3'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); +assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +always @(*) begin + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine6_next_state <= 3'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); +assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); +assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +always @(*) begin + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); +always @(*) begin + litedramcore_bankmachine7_next_state <= 3'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); +assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); +assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; +assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); +assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); +assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); +assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); +assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); +assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; +assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); +assign litedramcore_interface_rdata = {litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; +assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +always @(*) begin + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); +end +assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; +assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +always @(*) begin + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end +end +always @(*) begin + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end +end +assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +always @(*) begin + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); +end +assign litedramcore_choose_req_request = litedramcore_choose_req_valids; +assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; +assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +always @(*) begin + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end +end +assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); +assign litedramcore_dfi_p0_reset_n = 1'd1; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; +assign litedramcore_dfi_p1_reset_n = 1'd1; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; +assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]); +always @(*) begin + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 4'd11; + end + 4'd11: begin + litedramcore_multiplexer_next_state <= 4'd12; + end + 4'd12: begin + litedramcore_multiplexer_next_state <= 4'd13; + end + 4'd13: begin + litedramcore_multiplexer_next_state <= 4'd14; + end + 4'd14: begin + litedramcore_multiplexer_next_state <= 4'd15; + end + 4'd15: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if (1'd1) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if (1'd1) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase +end +assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_array_muxed12; +assign litedramcore_interface_bank0_we = rhs_array_muxed13; +assign litedramcore_interface_bank0_valid = rhs_array_muxed14; +assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_array_muxed15; +assign litedramcore_interface_bank1_we = rhs_array_muxed16; +assign litedramcore_interface_bank1_valid = rhs_array_muxed17; +assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_array_muxed18; +assign litedramcore_interface_bank2_we = rhs_array_muxed19; +assign litedramcore_interface_bank2_valid = rhs_array_muxed20; +assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_array_muxed21; +assign litedramcore_interface_bank3_we = rhs_array_muxed22; +assign litedramcore_interface_bank3_valid = rhs_array_muxed23; +assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_array_muxed24; +assign litedramcore_interface_bank4_we = rhs_array_muxed25; +assign litedramcore_interface_bank4_valid = rhs_array_muxed26; +assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_array_muxed27; +assign litedramcore_interface_bank5_we = rhs_array_muxed28; +assign litedramcore_interface_bank5_valid = rhs_array_muxed29; +assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_array_muxed30; +assign litedramcore_interface_bank6_we = rhs_array_muxed31; +assign litedramcore_interface_bank6_valid = rhs_array_muxed32; +assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_array_muxed33; +assign litedramcore_interface_bank7_we = rhs_array_muxed34; +assign litedramcore_interface_bank7_valid = rhs_array_muxed35; +assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = litedramcore_new_master_wdata_ready3; +assign user_port_rdata_valid = litedramcore_new_master_rdata_valid13; +always @(*) begin + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase +end +assign user_port_rdata_payload_data = litedramcore_interface_rdata; +assign litedramcore_roundrobin0_grant = 1'd0; +assign litedramcore_roundrobin1_grant = 1'd0; +assign litedramcore_roundrobin2_grant = 1'd0; +assign litedramcore_roundrobin3_grant = 1'd0; +assign litedramcore_roundrobin4_grant = 1'd0; +assign litedramcore_roundrobin5_grant = 1'd0; +assign litedramcore_roundrobin6_grant = 1'd0; +assign litedramcore_roundrobin7_grant = 1'd0; +always @(*) begin + next_state <= 2'd0; + next_state <= state; + case (state) + 1'd1: begin + next_state <= 2'd2; + end + 2'd2: begin + next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +assign litedramcore_wishbone_adr = wb_bus_adr; +assign litedramcore_wishbone_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = wb_bus_sel; +assign litedramcore_wishbone_cyc = wb_bus_cyc; +assign litedramcore_wishbone_stb = wb_bus_stb; +assign wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = wb_bus_we; +assign litedramcore_wishbone_cti = wb_bus_cti; +assign litedramcore_wishbone_bte = wb_bus_bte; +assign wb_bus_err = litedramcore_wishbone_err; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end +end +always @(*) begin + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +always @(*) begin + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end +end +always @(*) begin + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end +end +assign csrbank0_init_done0_w = init_done_storage; +assign csrbank0_init_error0_w = init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end +end +always @(*) begin + ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end +end +assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end +end +always @(*) begin + ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end +end +assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + ddrphy_burstdet_clr_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_re <= interface1_bank_bus_we; + end +end +always @(*) begin + ddrphy_burstdet_clr_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank1_burstdet_seen_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_re <= interface1_bank_bus_we; + end +end +always @(*) begin + csrbank1_burstdet_seen_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0]; +assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0]; +assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end +end +assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; +always @(*) begin + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end +end +assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; +always @(*) begin + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + end +end +always @(*) begin + csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; + end +end +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + end +end +always @(*) begin + csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + end +end +assign litedramcore_sel = litedramcore_storage[0]; +assign litedramcore_cke = litedramcore_storage[1]; +assign litedramcore_odt = litedramcore_storage[2]; +assign litedramcore_reset_n = litedramcore_storage[3]; +assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; +assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; +assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32]; +assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_rddata_status[31:0]; +assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata0_we; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; +assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; +assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; +assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; +assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we; +assign csr_interconnect_adr = litedramcore_adr; +assign csr_interconnect_we = litedramcore_we; +assign csr_interconnect_dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = csr_interconnect_dat_r; +assign interface0_bank_bus_adr = csr_interconnect_adr; +assign interface1_bank_bus_adr = csr_interconnect_adr; +assign interface2_bank_bus_adr = csr_interconnect_adr; +assign interface0_bank_bus_we = csr_interconnect_we; +assign interface1_bank_bus_we = csr_interconnect_we; +assign interface2_bank_bus_we = csr_interconnect_we; +assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; +assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; +assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); +always @(*) begin + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 15'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 15'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 22'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 22'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 22'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 22'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed24 <= 22'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 22'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 22'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 22'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 15'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 15'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +assign ddrphy_lock1 = regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge init_clk) begin + ddrphy_lock_d <= ddrphy_lock1; + if ((ddrphy_counter == 4'd8)) begin + ddrphy_freeze <= 1'd1; + end + if ((ddrphy_counter == 5'd16)) begin + ddrphy_stop1 <= 1'd1; + end + if ((ddrphy_counter == 5'd24)) begin + ddrphy_reset1 <= 1'd1; + end + if ((ddrphy_counter == 6'd32)) begin + ddrphy_reset1 <= 1'd0; + end + if ((ddrphy_counter == 6'd40)) begin + ddrphy_stop1 <= 1'd0; + end + if ((ddrphy_counter == 6'd48)) begin + ddrphy_freeze <= 1'd0; + end + if ((ddrphy_counter == 6'd56)) begin + ddrphy_pause1 <= 1'd1; + end + if ((ddrphy_counter == 7'd64)) begin + ddrphy_update <= 1'd1; + end + if ((ddrphy_counter == 7'd72)) begin + ddrphy_update <= 1'd0; + end + if ((ddrphy_counter == 7'd80)) begin + ddrphy_pause1 <= 1'd0; + end + if ((ddrphy_counter == 7'd80)) begin + ddrphy_counter <= 1'd0; + end else begin + if ((ddrphy_counter != 1'd0)) begin + ddrphy_counter <= (ddrphy_counter + 1'd1); + end else begin + if (ddrphy_new_lock) begin + ddrphy_counter <= 1'd1; + end + end + end + if (init_rst) begin + ddrphy_update <= 1'd0; + ddrphy_stop1 <= 1'd0; + ddrphy_freeze <= 1'd0; + ddrphy_pause1 <= 1'd0; + ddrphy_reset1 <= 1'd0; + ddrphy_lock_d <= 1'd0; + ddrphy_counter <= 7'd0; + end + regs0 <= ddrphy_lock0; + regs1 <= regs0; +end + +always @(posedge por_clk) begin + if ((~crg_por_done)) begin + crg_por_count <= (crg_por_count - 1'd1); + end +end + +always @(posedge sys_clk) begin + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly0 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1); + end + ddrphy_burstdet_d0 <= ddrphy_burstdet0; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[0] <= 1'd0; + end + if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin + ddrphy_burstdet_seen_status[0] <= 1'd1; + end + ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4]; + end + endcase + ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o; + ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o; + ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o; + ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o; + ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o; + ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o; + ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o; + ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly1 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1); + end + ddrphy_burstdet_d1 <= ddrphy_burstdet1; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[1] <= 1'd0; + end + if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin + ddrphy_burstdet_seen_status[1] <= 1'd1; + end + ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4]; + end + endcase + ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o; + ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o; + ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o; + ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o; + ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o; + ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o; + ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o; + ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip0_value <= 1'd0; + end + ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip1_value <= 1'd0; + end + ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip2_value <= 1'd0; + end + ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip3_value <= 1'd0; + end + ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip4_value <= 1'd0; + end + ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip5_value <= 1'd0; + end + ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip6_value <= 1'd0; + end + ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip7_value <= 1'd0; + end + ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip8_value <= 1'd0; + end + ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip9_value <= 1'd0; + end + ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip10_value <= 1'd0; + end + ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip11_value <= 1'd0; + end + ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip12_value <= 1'd0; + end + ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip13_value <= 1'd0; + end + ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip14_value <= 1'd0; + end + ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip15_value <= 1'd0; + end + ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]}; + ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en); + ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0; + ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1; + ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2; + ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3; + ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4; + ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5; + ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6; + ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7; + ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8; + ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9; + ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10; + ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11; + ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en); + ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0; + ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1; + ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2; + ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3; + ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4; + ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5; + if (litedramcore_inti_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_inti_p0_rddata; + end + if (litedramcore_inti_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_inti_p1_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 9'd374; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd2)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 7'd106)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 7'd106)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 26'd47999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd2)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 6'd34)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 6'd34)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; + litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; + litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; + litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; + litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; + litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; + litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; + litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; + litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; + litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; + litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; + litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; + litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; + litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; + litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; + litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; + litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; + litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; + litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; + litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; + litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; + litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; + litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; + litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; + litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd6; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_wdata_ready2 <= litedramcore_new_master_wdata_ready1; + litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8; + litedramcore_new_master_rdata_valid10 <= litedramcore_new_master_rdata_valid9; + litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10; + litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11; + litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12; + state <= next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w; + end + endcase + end + if (csrbank1_dly_sel0_re) begin + ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; + end + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; + end + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; + if (sys_rst) begin + ddrphy_dly_sel_storage <= 2'd0; + ddrphy_dly_sel_re <= 1'd0; + ddrphy_burstdet_seen_status <= 2'd0; + ddrphy_burstdet_seen_re <= 1'd0; + ddrphy_rdly0 <= 7'd0; + ddrphy_burstdet_d0 <= 1'd0; + ddrphy_dm_o_data_d0 <= 8'd0; + ddrphy_dm_o_data_muxed0 <= 4'd0; + ddrphy_dq_o_data_d0 <= 8'd0; + ddrphy_dq_o_data_muxed0 <= 4'd0; + ddrphy_bitslip0_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d0 <= 4'd0; + ddrphy_dq_o_data_d1 <= 8'd0; + ddrphy_dq_o_data_muxed1 <= 4'd0; + ddrphy_bitslip1_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d1 <= 4'd0; + ddrphy_dq_o_data_d2 <= 8'd0; + ddrphy_dq_o_data_muxed2 <= 4'd0; + ddrphy_bitslip2_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d2 <= 4'd0; + ddrphy_dq_o_data_d3 <= 8'd0; + ddrphy_dq_o_data_muxed3 <= 4'd0; + ddrphy_bitslip3_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d3 <= 4'd0; + ddrphy_dq_o_data_d4 <= 8'd0; + ddrphy_dq_o_data_muxed4 <= 4'd0; + ddrphy_bitslip4_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d4 <= 4'd0; + ddrphy_dq_o_data_d5 <= 8'd0; + ddrphy_dq_o_data_muxed5 <= 4'd0; + ddrphy_bitslip5_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d5 <= 4'd0; + ddrphy_dq_o_data_d6 <= 8'd0; + ddrphy_dq_o_data_muxed6 <= 4'd0; + ddrphy_bitslip6_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d6 <= 4'd0; + ddrphy_dq_o_data_d7 <= 8'd0; + ddrphy_dq_o_data_muxed7 <= 4'd0; + ddrphy_bitslip7_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d7 <= 4'd0; + ddrphy_rdly1 <= 7'd0; + ddrphy_burstdet_d1 <= 1'd0; + ddrphy_dm_o_data_d1 <= 8'd0; + ddrphy_dm_o_data_muxed1 <= 4'd0; + ddrphy_dq_o_data_d8 <= 8'd0; + ddrphy_dq_o_data_muxed8 <= 4'd0; + ddrphy_bitslip8_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d8 <= 4'd0; + ddrphy_dq_o_data_d9 <= 8'd0; + ddrphy_dq_o_data_muxed9 <= 4'd0; + ddrphy_bitslip9_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d9 <= 4'd0; + ddrphy_dq_o_data_d10 <= 8'd0; + ddrphy_dq_o_data_muxed10 <= 4'd0; + ddrphy_bitslip10_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d10 <= 4'd0; + ddrphy_dq_o_data_d11 <= 8'd0; + ddrphy_dq_o_data_muxed11 <= 4'd0; + ddrphy_bitslip11_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d11 <= 4'd0; + ddrphy_dq_o_data_d12 <= 8'd0; + ddrphy_dq_o_data_muxed12 <= 4'd0; + ddrphy_bitslip12_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d12 <= 4'd0; + ddrphy_dq_o_data_d13 <= 8'd0; + ddrphy_dq_o_data_muxed13 <= 4'd0; + ddrphy_bitslip13_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d13 <= 4'd0; + ddrphy_dq_o_data_d14 <= 8'd0; + ddrphy_dq_o_data_muxed14 <= 4'd0; + ddrphy_bitslip14_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d14 <= 4'd0; + ddrphy_dq_o_data_d15 <= 8'd0; + ddrphy_dq_o_data_muxed15 <= 4'd0; + ddrphy_bitslip15_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d15 <= 4'd0; + ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + ddrphy_rddata_en_tappeddelayline8 <= 1'd0; + ddrphy_rddata_en_tappeddelayline9 <= 1'd0; + ddrphy_rddata_en_tappeddelayline10 <= 1'd0; + ddrphy_rddata_en_tappeddelayline11 <= 1'd0; + ddrphy_rddata_en_tappeddelayline12 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline3 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline4 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline5 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline6 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 64'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 64'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 15'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 9'd374; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 7'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 26'd47999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 6'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 2'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 2'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 2'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 2'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 2'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 2'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 2'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 2'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 2'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 2'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 2'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 2'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 2'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 2'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 2'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 2'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 3'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 3'd0; + litedramcore_bankmachine1_state <= 3'd0; + litedramcore_bankmachine2_state <= 3'd0; + litedramcore_bankmachine3_state <= 3'd0; + litedramcore_bankmachine4_state <= 3'd0; + litedramcore_bankmachine5_state <= 3'd0; + litedramcore_bankmachine6_state <= 3'd0; + litedramcore_bankmachine7_state <= 3'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_wdata_ready2 <= 1'd0; + litedramcore_new_master_wdata_ready3 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_new_master_rdata_valid9 <= 1'd0; + litedramcore_new_master_rdata_valid10 <= 1'd0; + litedramcore_new_master_rdata_valid11 <= 1'd0; + litedramcore_new_master_rdata_valid12 <= 1'd0; + litedramcore_new_master_rdata_valid13 <= 1'd0; + litedramcore_we <= 1'd0; + state <= 2'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +ECLKBRIDGECS ECLKBRIDGECS( + .CLK0(sys2x_i_clk), + .SEL(1'd0), + .ECSOUT(crg_sys2x_clk_ecsout) +); + +ECLKSYNCB ECLKSYNCB( + .ECLKI(crg_sys2x_clk_ecsout), + .STOP(crg_stop), + .ECLKO(sys2x_clk) +); + +CLKDIVF #( + .DIV("2.0") +) CLKDIVF ( + .ALIGNWD(1'd0), + .CLKI(sys2x_clk), + .RST(crg_reset0), + .CDIVX(sys_clk) +); + +DDRDLLA DDRDLLA( + .CLK(sys2x_clk), + .FREEZE(ddrphy_freeze), + .RST(init_rst), + .UDDCNTLN((~ddrphy_update)), + .DDRDEL(ddrphy_delay1), + .LOCK(ddrphy_lock0) +); + +ODDRX2F ODDRX2F( + .D0(1'd0), + .D1(1'd1), + .D2(1'd0), + .D3(1'd1), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f0) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG ( + .A(ddrphy_pad_oddrx2f0), + .Z(ddram_clk_p) +); + +ODDRX2F ODDRX2F_1( + .D0(ddrphy_dfi_p0_reset_n), + .D1(ddrphy_dfi_p0_reset_n), + .D2(ddrphy_dfi_p1_reset_n), + .D3(ddrphy_dfi_p1_reset_n), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f1) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_1 ( + .A(ddrphy_pad_oddrx2f1), + .Z(ddram_reset_n) +); + +ODDRX2F ODDRX2F_2( + .D0(ddrphy_dfi_p0_cs_n), + .D1(ddrphy_dfi_p0_cs_n), + .D2(ddrphy_dfi_p1_cs_n), + .D3(ddrphy_dfi_p1_cs_n), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f2) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_2 ( + .A(ddrphy_pad_oddrx2f2), + .Z(ddram_cs_n) +); + +ODDRX2F ODDRX2F_3( + .D0(ddrphy_dfi_p0_address[0]), + .D1(ddrphy_dfi_p0_address[0]), + .D2(ddrphy_dfi_p1_address[0]), + .D3(ddrphy_dfi_p1_address[0]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f3) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_3 ( + .A(ddrphy_pad_oddrx2f3), + .Z(ddram_a[0]) +); + +ODDRX2F ODDRX2F_4( + .D0(ddrphy_dfi_p0_address[1]), + .D1(ddrphy_dfi_p0_address[1]), + .D2(ddrphy_dfi_p1_address[1]), + .D3(ddrphy_dfi_p1_address[1]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f4) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_4 ( + .A(ddrphy_pad_oddrx2f4), + .Z(ddram_a[1]) +); + +ODDRX2F ODDRX2F_5( + .D0(ddrphy_dfi_p0_address[2]), + .D1(ddrphy_dfi_p0_address[2]), + .D2(ddrphy_dfi_p1_address[2]), + .D3(ddrphy_dfi_p1_address[2]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f5) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_5 ( + .A(ddrphy_pad_oddrx2f5), + .Z(ddram_a[2]) +); + +ODDRX2F ODDRX2F_6( + .D0(ddrphy_dfi_p0_address[3]), + .D1(ddrphy_dfi_p0_address[3]), + .D2(ddrphy_dfi_p1_address[3]), + .D3(ddrphy_dfi_p1_address[3]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f6) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_6 ( + .A(ddrphy_pad_oddrx2f6), + .Z(ddram_a[3]) +); + +ODDRX2F ODDRX2F_7( + .D0(ddrphy_dfi_p0_address[4]), + .D1(ddrphy_dfi_p0_address[4]), + .D2(ddrphy_dfi_p1_address[4]), + .D3(ddrphy_dfi_p1_address[4]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f7) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_7 ( + .A(ddrphy_pad_oddrx2f7), + .Z(ddram_a[4]) +); + +ODDRX2F ODDRX2F_8( + .D0(ddrphy_dfi_p0_address[5]), + .D1(ddrphy_dfi_p0_address[5]), + .D2(ddrphy_dfi_p1_address[5]), + .D3(ddrphy_dfi_p1_address[5]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f8) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_8 ( + .A(ddrphy_pad_oddrx2f8), + .Z(ddram_a[5]) +); + +ODDRX2F ODDRX2F_9( + .D0(ddrphy_dfi_p0_address[6]), + .D1(ddrphy_dfi_p0_address[6]), + .D2(ddrphy_dfi_p1_address[6]), + .D3(ddrphy_dfi_p1_address[6]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f9) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_9 ( + .A(ddrphy_pad_oddrx2f9), + .Z(ddram_a[6]) +); + +ODDRX2F ODDRX2F_10( + .D0(ddrphy_dfi_p0_address[7]), + .D1(ddrphy_dfi_p0_address[7]), + .D2(ddrphy_dfi_p1_address[7]), + .D3(ddrphy_dfi_p1_address[7]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f10) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_10 ( + .A(ddrphy_pad_oddrx2f10), + .Z(ddram_a[7]) +); + +ODDRX2F ODDRX2F_11( + .D0(ddrphy_dfi_p0_address[8]), + .D1(ddrphy_dfi_p0_address[8]), + .D2(ddrphy_dfi_p1_address[8]), + .D3(ddrphy_dfi_p1_address[8]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f11) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_11 ( + .A(ddrphy_pad_oddrx2f11), + .Z(ddram_a[8]) +); + +ODDRX2F ODDRX2F_12( + .D0(ddrphy_dfi_p0_address[9]), + .D1(ddrphy_dfi_p0_address[9]), + .D2(ddrphy_dfi_p1_address[9]), + .D3(ddrphy_dfi_p1_address[9]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f12) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_12 ( + .A(ddrphy_pad_oddrx2f12), + .Z(ddram_a[9]) +); + +ODDRX2F ODDRX2F_13( + .D0(ddrphy_dfi_p0_address[10]), + .D1(ddrphy_dfi_p0_address[10]), + .D2(ddrphy_dfi_p1_address[10]), + .D3(ddrphy_dfi_p1_address[10]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f13) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_13 ( + .A(ddrphy_pad_oddrx2f13), + .Z(ddram_a[10]) +); + +ODDRX2F ODDRX2F_14( + .D0(ddrphy_dfi_p0_address[11]), + .D1(ddrphy_dfi_p0_address[11]), + .D2(ddrphy_dfi_p1_address[11]), + .D3(ddrphy_dfi_p1_address[11]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f14) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_14 ( + .A(ddrphy_pad_oddrx2f14), + .Z(ddram_a[11]) +); + +ODDRX2F ODDRX2F_15( + .D0(ddrphy_dfi_p0_address[12]), + .D1(ddrphy_dfi_p0_address[12]), + .D2(ddrphy_dfi_p1_address[12]), + .D3(ddrphy_dfi_p1_address[12]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f15) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_15 ( + .A(ddrphy_pad_oddrx2f15), + .Z(ddram_a[12]) +); + +ODDRX2F ODDRX2F_16( + .D0(ddrphy_dfi_p0_address[13]), + .D1(ddrphy_dfi_p0_address[13]), + .D2(ddrphy_dfi_p1_address[13]), + .D3(ddrphy_dfi_p1_address[13]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f16) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_16 ( + .A(ddrphy_pad_oddrx2f16), + .Z(ddram_a[13]) +); + +ODDRX2F ODDRX2F_17( + .D0(ddrphy_dfi_p0_address[14]), + .D1(ddrphy_dfi_p0_address[14]), + .D2(ddrphy_dfi_p1_address[14]), + .D3(ddrphy_dfi_p1_address[14]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f17) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_17 ( + .A(ddrphy_pad_oddrx2f17), + .Z(ddram_a[14]) +); + +ODDRX2F ODDRX2F_18( + .D0(ddrphy_dfi_p0_bank[0]), + .D1(ddrphy_dfi_p0_bank[0]), + .D2(ddrphy_dfi_p1_bank[0]), + .D3(ddrphy_dfi_p1_bank[0]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f18) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_18 ( + .A(ddrphy_pad_oddrx2f18), + .Z(ddram_ba[0]) +); + +ODDRX2F ODDRX2F_19( + .D0(ddrphy_dfi_p0_bank[1]), + .D1(ddrphy_dfi_p0_bank[1]), + .D2(ddrphy_dfi_p1_bank[1]), + .D3(ddrphy_dfi_p1_bank[1]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f19) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_19 ( + .A(ddrphy_pad_oddrx2f19), + .Z(ddram_ba[1]) +); + +ODDRX2F ODDRX2F_20( + .D0(ddrphy_dfi_p0_bank[2]), + .D1(ddrphy_dfi_p0_bank[2]), + .D2(ddrphy_dfi_p1_bank[2]), + .D3(ddrphy_dfi_p1_bank[2]), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f20) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_20 ( + .A(ddrphy_pad_oddrx2f20), + .Z(ddram_ba[2]) +); + +ODDRX2F ODDRX2F_21( + .D0(ddrphy_dfi_p0_ras_n), + .D1(ddrphy_dfi_p0_ras_n), + .D2(ddrphy_dfi_p1_ras_n), + .D3(ddrphy_dfi_p1_ras_n), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f21) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_21 ( + .A(ddrphy_pad_oddrx2f21), + .Z(ddram_ras_n) +); + +ODDRX2F ODDRX2F_22( + .D0(ddrphy_dfi_p0_cas_n), + .D1(ddrphy_dfi_p0_cas_n), + .D2(ddrphy_dfi_p1_cas_n), + .D3(ddrphy_dfi_p1_cas_n), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f22) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_22 ( + .A(ddrphy_pad_oddrx2f22), + .Z(ddram_cas_n) +); + +ODDRX2F ODDRX2F_23( + .D0(ddrphy_dfi_p0_we_n), + .D1(ddrphy_dfi_p0_we_n), + .D2(ddrphy_dfi_p1_we_n), + .D3(ddrphy_dfi_p1_we_n), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f23) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_23 ( + .A(ddrphy_pad_oddrx2f23), + .Z(ddram_we_n) +); + +ODDRX2F ODDRX2F_24( + .D0(ddrphy_dfi_p0_cke), + .D1(ddrphy_dfi_p0_cke), + .D2(ddrphy_dfi_p1_cke), + .D3(ddrphy_dfi_p1_cke), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f24) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_24 ( + .A(ddrphy_pad_oddrx2f24), + .Z(ddram_cke) +); + +ODDRX2F ODDRX2F_25( + .D0(ddrphy_dfi_p0_odt), + .D1(ddrphy_dfi_p0_odt), + .D2(ddrphy_dfi_p1_odt), + .D3(ddrphy_dfi_p1_odt), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_pad_oddrx2f25) +); + +DELAYG #( + .DEL_VALUE(7'd100) +) DELAYG_25 ( + .A(ddrphy_pad_oddrx2f25), + .Z(ddram_odt) +); + +DQSBUFM #( + .DQS_LI_DEL_ADJ("MINUS"), + .DQS_LI_DEL_VAL(1'd1), + .DQS_LO_DEL_ADJ("MINUS"), + .DQS_LO_DEL_VAL(3'd4) +) DQSBUFM ( + .DDRDEL(ddrphy_delay0), + .DQSI(ddrphy_dqs_i0), + .ECLK(sys2x_clk), + .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[0])), + .RDDIRECTION(1'd1), + .RDLOADN(1'd0), + .RDMOVE(1'd0), + .READ0(ddrphy_dqs_re), + .READ1(ddrphy_dqs_re), + .READCLKSEL0(ddrphy_rdly0[0]), + .READCLKSEL1(ddrphy_rdly0[1]), + .READCLKSEL2(ddrphy_rdly0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRDIRECTION(1'd1), + .WRLOADN(1'd0), + .WRMOVE(1'd0), + .BURSTDET(ddrphy_burstdet0), + .DATAVALID(ddrphy_datavalid[0]), + .DQSR90(ddrphy_dqsr900), + .DQSW(ddrphy_dqsw0), + .DQSW270(ddrphy_dqsw2700), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]) +); + +ODDRX2DQSB ODDRX2DQSB( + .D0(1'd0), + .D1(1'd1), + .D2(1'd0), + .D3(1'd1), + .DQSW(ddrphy_dqsw0), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dqs0) +); + +TSHX2DQSA TSHX2DQSA( + .DQSW(ddrphy_dqsw0), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + .Q(ddrphy_dqs_oe_n0) +); + +ODDRX2DQA ODDRX2DQA( + .D0(ddrphy_dm_o_data_muxed0[0]), + .D1(ddrphy_dm_o_data_muxed0[1]), + .D2(ddrphy_dm_o_data_muxed0[2]), + .D3(ddrphy_dm_o_data_muxed0[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddram_dm[0]) +); + +ODDRX2DQA ODDRX2DQA_1( + .D0(ddrphy_dq_o_data_muxed0[0]), + .D1(ddrphy_dq_o_data_muxed0[1]), + .D2(ddrphy_dq_o_data_muxed0[2]), + .D3(ddrphy_dq_o_data_muxed0[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o0) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_26 ( + .A(ddrphy_dq_i0), + .Z(ddrphy_dq_i_delayed0) +); + +IDDRX2DQA IDDRX2DQA( + .D(ddrphy_dq_i_delayed0), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip0_i[0]), + .Q1(ddrphy_bitslip0_i[1]), + .Q2(ddrphy_bitslip0_i[2]), + .Q3(ddrphy_bitslip0_i[3]) +); + +TSHX2DQA TSHX2DQA( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n0) +); + +ODDRX2DQA ODDRX2DQA_2( + .D0(ddrphy_dq_o_data_muxed1[0]), + .D1(ddrphy_dq_o_data_muxed1[1]), + .D2(ddrphy_dq_o_data_muxed1[2]), + .D3(ddrphy_dq_o_data_muxed1[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o1) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_27 ( + .A(ddrphy_dq_i1), + .Z(ddrphy_dq_i_delayed1) +); + +IDDRX2DQA IDDRX2DQA_1( + .D(ddrphy_dq_i_delayed1), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip1_i[0]), + .Q1(ddrphy_bitslip1_i[1]), + .Q2(ddrphy_bitslip1_i[2]), + .Q3(ddrphy_bitslip1_i[3]) +); + +TSHX2DQA TSHX2DQA_1( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n1) +); + +ODDRX2DQA ODDRX2DQA_3( + .D0(ddrphy_dq_o_data_muxed2[0]), + .D1(ddrphy_dq_o_data_muxed2[1]), + .D2(ddrphy_dq_o_data_muxed2[2]), + .D3(ddrphy_dq_o_data_muxed2[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o2) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_28 ( + .A(ddrphy_dq_i2), + .Z(ddrphy_dq_i_delayed2) +); + +IDDRX2DQA IDDRX2DQA_2( + .D(ddrphy_dq_i_delayed2), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip2_i[0]), + .Q1(ddrphy_bitslip2_i[1]), + .Q2(ddrphy_bitslip2_i[2]), + .Q3(ddrphy_bitslip2_i[3]) +); + +TSHX2DQA TSHX2DQA_2( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n2) +); + +ODDRX2DQA ODDRX2DQA_4( + .D0(ddrphy_dq_o_data_muxed3[0]), + .D1(ddrphy_dq_o_data_muxed3[1]), + .D2(ddrphy_dq_o_data_muxed3[2]), + .D3(ddrphy_dq_o_data_muxed3[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o3) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_29 ( + .A(ddrphy_dq_i3), + .Z(ddrphy_dq_i_delayed3) +); + +IDDRX2DQA IDDRX2DQA_3( + .D(ddrphy_dq_i_delayed3), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip3_i[0]), + .Q1(ddrphy_bitslip3_i[1]), + .Q2(ddrphy_bitslip3_i[2]), + .Q3(ddrphy_bitslip3_i[3]) +); + +TSHX2DQA TSHX2DQA_3( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n3) +); + +ODDRX2DQA ODDRX2DQA_5( + .D0(ddrphy_dq_o_data_muxed4[0]), + .D1(ddrphy_dq_o_data_muxed4[1]), + .D2(ddrphy_dq_o_data_muxed4[2]), + .D3(ddrphy_dq_o_data_muxed4[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o4) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_30 ( + .A(ddrphy_dq_i4), + .Z(ddrphy_dq_i_delayed4) +); + +IDDRX2DQA IDDRX2DQA_4( + .D(ddrphy_dq_i_delayed4), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip4_i[0]), + .Q1(ddrphy_bitslip4_i[1]), + .Q2(ddrphy_bitslip4_i[2]), + .Q3(ddrphy_bitslip4_i[3]) +); + +TSHX2DQA TSHX2DQA_4( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n4) +); + +ODDRX2DQA ODDRX2DQA_6( + .D0(ddrphy_dq_o_data_muxed5[0]), + .D1(ddrphy_dq_o_data_muxed5[1]), + .D2(ddrphy_dq_o_data_muxed5[2]), + .D3(ddrphy_dq_o_data_muxed5[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o5) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_31 ( + .A(ddrphy_dq_i5), + .Z(ddrphy_dq_i_delayed5) +); + +IDDRX2DQA IDDRX2DQA_5( + .D(ddrphy_dq_i_delayed5), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip5_i[0]), + .Q1(ddrphy_bitslip5_i[1]), + .Q2(ddrphy_bitslip5_i[2]), + .Q3(ddrphy_bitslip5_i[3]) +); + +TSHX2DQA TSHX2DQA_5( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n5) +); + +ODDRX2DQA ODDRX2DQA_7( + .D0(ddrphy_dq_o_data_muxed6[0]), + .D1(ddrphy_dq_o_data_muxed6[1]), + .D2(ddrphy_dq_o_data_muxed6[2]), + .D3(ddrphy_dq_o_data_muxed6[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o6) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_32 ( + .A(ddrphy_dq_i6), + .Z(ddrphy_dq_i_delayed6) +); + +IDDRX2DQA IDDRX2DQA_6( + .D(ddrphy_dq_i_delayed6), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip6_i[0]), + .Q1(ddrphy_bitslip6_i[1]), + .Q2(ddrphy_bitslip6_i[2]), + .Q3(ddrphy_bitslip6_i[3]) +); + +TSHX2DQA TSHX2DQA_6( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n6) +); + +ODDRX2DQA ODDRX2DQA_8( + .D0(ddrphy_dq_o_data_muxed7[0]), + .D1(ddrphy_dq_o_data_muxed7[1]), + .D2(ddrphy_dq_o_data_muxed7[2]), + .D3(ddrphy_dq_o_data_muxed7[3]), + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o7) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_33 ( + .A(ddrphy_dq_i7), + .Z(ddrphy_dq_i_delayed7) +); + +IDDRX2DQA IDDRX2DQA_7( + .D(ddrphy_dq_i_delayed7), + .DQSR90(ddrphy_dqsr900), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr0[0]), + .RDPNTR1(ddrphy_rdpntr0[1]), + .RDPNTR2(ddrphy_rdpntr0[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr0[0]), + .WRPNTR1(ddrphy_wrpntr0[1]), + .WRPNTR2(ddrphy_wrpntr0[2]), + .Q0(ddrphy_bitslip7_i[0]), + .Q1(ddrphy_bitslip7_i[1]), + .Q2(ddrphy_bitslip7_i[2]), + .Q3(ddrphy_bitslip7_i[3]) +); + +TSHX2DQA TSHX2DQA_7( + .DQSW270(ddrphy_dqsw2700), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n7) +); + +DQSBUFM #( + .DQS_LI_DEL_ADJ("MINUS"), + .DQS_LI_DEL_VAL(1'd1), + .DQS_LO_DEL_ADJ("MINUS"), + .DQS_LO_DEL_VAL(3'd4) +) DQSBUFM_1 ( + .DDRDEL(ddrphy_delay0), + .DQSI(ddrphy_dqs_i1), + .ECLK(sys2x_clk), + .PAUSE((ddrphy_pause0 | ddrphy_dly_sel_storage[1])), + .RDDIRECTION(1'd1), + .RDLOADN(1'd0), + .RDMOVE(1'd0), + .READ0(ddrphy_dqs_re), + .READ1(ddrphy_dqs_re), + .READCLKSEL0(ddrphy_rdly1[0]), + .READCLKSEL1(ddrphy_rdly1[1]), + .READCLKSEL2(ddrphy_rdly1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRDIRECTION(1'd1), + .WRLOADN(1'd0), + .WRMOVE(1'd0), + .BURSTDET(ddrphy_burstdet1), + .DATAVALID(ddrphy_datavalid[1]), + .DQSR90(ddrphy_dqsr901), + .DQSW(ddrphy_dqsw1), + .DQSW270(ddrphy_dqsw2701), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]) +); + +ODDRX2DQSB ODDRX2DQSB_1( + .D0(1'd0), + .D1(1'd1), + .D2(1'd0), + .D3(1'd1), + .DQSW(ddrphy_dqsw1), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dqs1) +); + +TSHX2DQSA TSHX2DQSA_1( + .DQSW(ddrphy_dqsw1), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~(ddrphy_dqs_oe | ddrphy_dqs_postamble))), + .T1((~(ddrphy_dqs_oe | ddrphy_dqs_preamble))), + .Q(ddrphy_dqs_oe_n1) +); + +ODDRX2DQA ODDRX2DQA_9( + .D0(ddrphy_dm_o_data_muxed1[0]), + .D1(ddrphy_dm_o_data_muxed1[1]), + .D2(ddrphy_dm_o_data_muxed1[2]), + .D3(ddrphy_dm_o_data_muxed1[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddram_dm[1]) +); + +ODDRX2DQA ODDRX2DQA_10( + .D0(ddrphy_dq_o_data_muxed8[0]), + .D1(ddrphy_dq_o_data_muxed8[1]), + .D2(ddrphy_dq_o_data_muxed8[2]), + .D3(ddrphy_dq_o_data_muxed8[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o8) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_34 ( + .A(ddrphy_dq_i8), + .Z(ddrphy_dq_i_delayed8) +); + +IDDRX2DQA IDDRX2DQA_8( + .D(ddrphy_dq_i_delayed8), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip8_i[0]), + .Q1(ddrphy_bitslip8_i[1]), + .Q2(ddrphy_bitslip8_i[2]), + .Q3(ddrphy_bitslip8_i[3]) +); + +TSHX2DQA TSHX2DQA_8( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n8) +); + +ODDRX2DQA ODDRX2DQA_11( + .D0(ddrphy_dq_o_data_muxed9[0]), + .D1(ddrphy_dq_o_data_muxed9[1]), + .D2(ddrphy_dq_o_data_muxed9[2]), + .D3(ddrphy_dq_o_data_muxed9[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o9) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_35 ( + .A(ddrphy_dq_i9), + .Z(ddrphy_dq_i_delayed9) +); + +IDDRX2DQA IDDRX2DQA_9( + .D(ddrphy_dq_i_delayed9), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip9_i[0]), + .Q1(ddrphy_bitslip9_i[1]), + .Q2(ddrphy_bitslip9_i[2]), + .Q3(ddrphy_bitslip9_i[3]) +); + +TSHX2DQA TSHX2DQA_9( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n9) +); + +ODDRX2DQA ODDRX2DQA_12( + .D0(ddrphy_dq_o_data_muxed10[0]), + .D1(ddrphy_dq_o_data_muxed10[1]), + .D2(ddrphy_dq_o_data_muxed10[2]), + .D3(ddrphy_dq_o_data_muxed10[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o10) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_36 ( + .A(ddrphy_dq_i10), + .Z(ddrphy_dq_i_delayed10) +); + +IDDRX2DQA IDDRX2DQA_10( + .D(ddrphy_dq_i_delayed10), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip10_i[0]), + .Q1(ddrphy_bitslip10_i[1]), + .Q2(ddrphy_bitslip10_i[2]), + .Q3(ddrphy_bitslip10_i[3]) +); + +TSHX2DQA TSHX2DQA_10( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n10) +); + +ODDRX2DQA ODDRX2DQA_13( + .D0(ddrphy_dq_o_data_muxed11[0]), + .D1(ddrphy_dq_o_data_muxed11[1]), + .D2(ddrphy_dq_o_data_muxed11[2]), + .D3(ddrphy_dq_o_data_muxed11[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o11) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_37 ( + .A(ddrphy_dq_i11), + .Z(ddrphy_dq_i_delayed11) +); + +IDDRX2DQA IDDRX2DQA_11( + .D(ddrphy_dq_i_delayed11), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip11_i[0]), + .Q1(ddrphy_bitslip11_i[1]), + .Q2(ddrphy_bitslip11_i[2]), + .Q3(ddrphy_bitslip11_i[3]) +); + +TSHX2DQA TSHX2DQA_11( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n11) +); + +ODDRX2DQA ODDRX2DQA_14( + .D0(ddrphy_dq_o_data_muxed12[0]), + .D1(ddrphy_dq_o_data_muxed12[1]), + .D2(ddrphy_dq_o_data_muxed12[2]), + .D3(ddrphy_dq_o_data_muxed12[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o12) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_38 ( + .A(ddrphy_dq_i12), + .Z(ddrphy_dq_i_delayed12) +); + +IDDRX2DQA IDDRX2DQA_12( + .D(ddrphy_dq_i_delayed12), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip12_i[0]), + .Q1(ddrphy_bitslip12_i[1]), + .Q2(ddrphy_bitslip12_i[2]), + .Q3(ddrphy_bitslip12_i[3]) +); + +TSHX2DQA TSHX2DQA_12( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n12) +); + +ODDRX2DQA ODDRX2DQA_15( + .D0(ddrphy_dq_o_data_muxed13[0]), + .D1(ddrphy_dq_o_data_muxed13[1]), + .D2(ddrphy_dq_o_data_muxed13[2]), + .D3(ddrphy_dq_o_data_muxed13[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o13) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_39 ( + .A(ddrphy_dq_i13), + .Z(ddrphy_dq_i_delayed13) +); + +IDDRX2DQA IDDRX2DQA_13( + .D(ddrphy_dq_i_delayed13), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip13_i[0]), + .Q1(ddrphy_bitslip13_i[1]), + .Q2(ddrphy_bitslip13_i[2]), + .Q3(ddrphy_bitslip13_i[3]) +); + +TSHX2DQA TSHX2DQA_13( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n13) +); + +ODDRX2DQA ODDRX2DQA_16( + .D0(ddrphy_dq_o_data_muxed14[0]), + .D1(ddrphy_dq_o_data_muxed14[1]), + .D2(ddrphy_dq_o_data_muxed14[2]), + .D3(ddrphy_dq_o_data_muxed14[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o14) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_40 ( + .A(ddrphy_dq_i14), + .Z(ddrphy_dq_i_delayed14) +); + +IDDRX2DQA IDDRX2DQA_14( + .D(ddrphy_dq_i_delayed14), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip14_i[0]), + .Q1(ddrphy_bitslip14_i[1]), + .Q2(ddrphy_bitslip14_i[2]), + .Q3(ddrphy_bitslip14_i[3]) +); + +TSHX2DQA TSHX2DQA_14( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n14) +); + +ODDRX2DQA ODDRX2DQA_17( + .D0(ddrphy_dq_o_data_muxed15[0]), + .D1(ddrphy_dq_o_data_muxed15[1]), + .D2(ddrphy_dq_o_data_muxed15[2]), + .D3(ddrphy_dq_o_data_muxed15[3]), + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .Q(ddrphy_dq_o15) +); + +DELAYG #( + .DEL_MODE("DQS_ALIGNED_X2") +) DELAYG_41 ( + .A(ddrphy_dq_i15), + .Z(ddrphy_dq_i_delayed15) +); + +IDDRX2DQA IDDRX2DQA_15( + .D(ddrphy_dq_i_delayed15), + .DQSR90(ddrphy_dqsr901), + .ECLK(sys2x_clk), + .RDPNTR0(ddrphy_rdpntr1[0]), + .RDPNTR1(ddrphy_rdpntr1[1]), + .RDPNTR2(ddrphy_rdpntr1[2]), + .RST(sys_rst), + .SCLK(sys_clk), + .WRPNTR0(ddrphy_wrpntr1[0]), + .WRPNTR1(ddrphy_wrpntr1[1]), + .WRPNTR2(ddrphy_wrpntr1[2]), + .Q0(ddrphy_bitslip15_i[0]), + .Q1(ddrphy_bitslip15_i[1]), + .Q2(ddrphy_bitslip15_i[2]), + .Q3(ddrphy_bitslip15_i[3]) +); + +TSHX2DQA TSHX2DQA_15( + .DQSW270(ddrphy_dqsw2701), + .ECLK(sys2x_clk), + .RST(sys_rst), + .SCLK(sys_clk), + .T0((~ddrphy_dq_oe)), + .T1((~ddrphy_dq_oe)), + .Q(ddrphy_dq_oe_n15) +); + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage[0:15]; +reg [24:0] storage_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_1[0:15]; +reg [24:0] storage_1_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_2[0:15]; +reg [24:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_3[0:15]; +reg [24:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_4[0:15]; +reg [24:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_5[0:15]; +reg [24:0] storage_5_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_6[0:15]; +reg [24:0] storage_6_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 25-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 25 +// Port 1 | Read: Async | Write: ---- | +reg [24:0] storage_7[0:15]; +reg [24:0] storage_7_dat0; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + + +(* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) EHXPLLL #( + .CLKFB_DIV(4'd10), + .CLKI_DIV(1'd1), + .CLKOP_CPHASE(3'd4), + .CLKOP_DIV(3'd5), + .CLKOP_ENABLE("ENABLED"), + .CLKOP_FPHASE(1'd0), + .CLKOS2_CPHASE(1'd0), + .CLKOS2_DIV(1'd1), + .CLKOS2_ENABLE("ENABLED"), + .CLKOS2_FPHASE(1'd0), + .CLKOS_CPHASE(5'd19), + .CLKOS_DIV(5'd20), + .CLKOS_ENABLE("ENABLED"), + .CLKOS_FPHASE(1'd0), + .FEEDBK_PATH("INT_OS2") +) EHXPLLL ( + .CLKI(crg_clkin), + .RST(crg_reset1), + .STDBY(crg_stdby), + .CLKOP(crg_clkout0), + .CLKOS(crg_clkout1), + .CLKOS2(litedramecp5ddrphycrg_ecp5pll), + .LOCK(litedramecp5ddrphycrg_locked) +); + +FD1S3BX FD1S3BX( + .CK(sys2x_i_clk), + .D(1'd0), + .PD((~crg_locked)), + .Q(latticeecp5asyncresetsynchronizerimpl0_rst1) +); + +FD1S3BX FD1S3BX_1( + .CK(sys2x_i_clk), + .D(latticeecp5asyncresetsynchronizerimpl0_rst1), + .PD((~crg_locked)), + .Q(latticeecp5asyncresetsynchronizerimpl0_expr) +); + +FD1S3BX FD1S3BX_2( + .CK(init_clk), + .D(1'd0), + .PD((~crg_locked)), + .Q(latticeecp5asyncresetsynchronizerimpl1_rst1) +); + +FD1S3BX FD1S3BX_3( + .CK(init_clk), + .D(latticeecp5asyncresetsynchronizerimpl1_rst1), + .PD((~crg_locked)), + .Q(init_rst) +); + +FD1S3BX FD1S3BX_4( + .CK(sys_clk), + .D(1'd0), + .PD(((~crg_locked) | crg_reset0)), + .Q(latticeecp5asyncresetsynchronizerimpl2_rst1) +); + +FD1S3BX FD1S3BX_5( + .CK(sys_clk), + .D(latticeecp5asyncresetsynchronizerimpl2_rst1), + .PD(((~crg_locked) | crg_reset0)), + .Q(sys_rst) +); + +FD1S3BX FD1S3BX_6( + .CK(sys2x_clk), + .D(1'd0), + .PD(((~crg_locked) | crg_reset0)), + .Q(latticeecp5asyncresetsynchronizerimpl3_rst1) +); + +FD1S3BX FD1S3BX_7( + .CK(sys2x_clk), + .D(latticeecp5asyncresetsynchronizerimpl3_rst1), + .PD(((~crg_locked) | crg_reset0)), + .Q(sys2x_rst) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO ( + .B(ddram_dqs_p[0]), + .I(ddrphy_dqs0), + .T((~(~ddrphy_dqs_oe_n0))), + .O(ddrphy_dqs_i0) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_1 ( + .B(ddram_dq[0]), + .I(ddrphy_dq_o0), + .T((~(~ddrphy_dq_oe_n0))), + .O(ddrphy_dq_i0) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_2 ( + .B(ddram_dq[1]), + .I(ddrphy_dq_o1), + .T((~(~ddrphy_dq_oe_n1))), + .O(ddrphy_dq_i1) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_3 ( + .B(ddram_dq[2]), + .I(ddrphy_dq_o2), + .T((~(~ddrphy_dq_oe_n2))), + .O(ddrphy_dq_i2) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_4 ( + .B(ddram_dq[3]), + .I(ddrphy_dq_o3), + .T((~(~ddrphy_dq_oe_n3))), + .O(ddrphy_dq_i3) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_5 ( + .B(ddram_dq[4]), + .I(ddrphy_dq_o4), + .T((~(~ddrphy_dq_oe_n4))), + .O(ddrphy_dq_i4) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_6 ( + .B(ddram_dq[5]), + .I(ddrphy_dq_o5), + .T((~(~ddrphy_dq_oe_n5))), + .O(ddrphy_dq_i5) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_7 ( + .B(ddram_dq[6]), + .I(ddrphy_dq_o6), + .T((~(~ddrphy_dq_oe_n6))), + .O(ddrphy_dq_i6) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_8 ( + .B(ddram_dq[7]), + .I(ddrphy_dq_o7), + .T((~(~ddrphy_dq_oe_n7))), + .O(ddrphy_dq_i7) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_9 ( + .B(ddram_dqs_p[1]), + .I(ddrphy_dqs1), + .T((~(~ddrphy_dqs_oe_n1))), + .O(ddrphy_dqs_i1) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_10 ( + .B(ddram_dq[8]), + .I(ddrphy_dq_o8), + .T((~(~ddrphy_dq_oe_n8))), + .O(ddrphy_dq_i8) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_11 ( + .B(ddram_dq[9]), + .I(ddrphy_dq_o9), + .T((~(~ddrphy_dq_oe_n9))), + .O(ddrphy_dq_i9) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_12 ( + .B(ddram_dq[10]), + .I(ddrphy_dq_o10), + .T((~(~ddrphy_dq_oe_n10))), + .O(ddrphy_dq_i10) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_13 ( + .B(ddram_dq[11]), + .I(ddrphy_dq_o11), + .T((~(~ddrphy_dq_oe_n11))), + .O(ddrphy_dq_i11) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_14 ( + .B(ddram_dq[12]), + .I(ddrphy_dq_o12), + .T((~(~ddrphy_dq_oe_n12))), + .O(ddrphy_dq_i12) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_15 ( + .B(ddram_dq[13]), + .I(ddrphy_dq_o13), + .T((~(~ddrphy_dq_oe_n13))), + .O(ddrphy_dq_i13) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_16 ( + .B(ddram_dq[14]), + .I(ddrphy_dq_o14), + .T((~(~ddrphy_dq_oe_n14))), + .O(ddrphy_dq_i14) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_17 ( + .B(ddram_dq[15]), + .I(ddrphy_dq_o15), + .T((~(~ddrphy_dq_oe_n15))), + .O(ddrphy_dq_i15) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 09:35:05. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index 542287d..e0b2512 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -527,11 +527,11 @@ f8c100e87c651b78 38c100d87fc3f378 f90100f8f8e100f0 f9410108f9210100 -6000000048001871 +60000000480017fd 7fc3f3787c7f1b78 -600000004800127d +6000000048001221 7fe3fb78382100b0 -0000000048001e68 +0000000048001e78 0000028001000000 000000004e800020 0000000000000000 @@ -540,83 +540,84 @@ f9410108f9210100 0000000000000000 3842a3203c4c0001 7d8000267c0802a6 -9181000848001da5 -48001279f821fed1 +9181000848001db5 +4800121df821fed1 3c62ffff60000000 -4bffff3938637b28 +4bffff3938637b38 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b48 +63ff000838637b58 3c62ffff4bffff15 -38637b687bff0020 +38637b787bff0020 7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffee938637b80 +4bfffee938637b90 4e00000073e90002 3c62ffff41820010 -4bfffed138637b88 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-7d455378993e0000 -39290001e9210060 -4bfffae8f9210060 +4bfff9797c84f850 +9a4900004bfffe2c +3900000139290001 +408200347c291840 +4bffffccf9210060 +7c6340507ce9f050 +7d4af8507ce7fa14 +7c691a142c270000 +394a000139000000 +3940000140820008 +394affff2c2a0001 +710800014082ffb4 +4bffff8c4082ffc0 +2c09006c89390001 +3b4000084182004c +893900014bfffdbc +2c0900683b400002 +7cb92b784082fdac +4bfffda03b400001 +5529063e3928ffd0 +4181fd9028090009 +3b7b00017b690020 +990900207d214a14 +7cb92b784bfffd7c +993e00004bffffb4 +7d0543783bde0001 +4bfffa6cfbc10060 0100000000000000 f9c1ff7000001280 fa01ff80f9e1ff78 @@ -1557,9 +1559,8 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -3536373832306564 +2d2d2d2d2d2d2d2d 0000000000000000 -0032363263623561 4d4152446574694c 6620746c69756220 6567694d206d6f72 diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index 398d7ad..1d6e21d 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -1,41 +1,62 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:42 -//-------------------------------------------------------------------------------- -module litedram_core( - input wire sim_trace, - input wire clk, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 08:32:16 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire sim_trace, + input wire clk, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, + input wire user_port_native_0_rdata_ready, output wire [127:0] user_port_native_0_rdata_data ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + wire sys_clk; wire sys_rst; wire por_clk; -reg soc_int_rst = 1'd1; +reg soc_int_rst = 1'd1; wire [13:0] soc_ddrphy_dfi_p0_address; wire [2:0] soc_ddrphy_dfi_p0_bank; wire soc_ddrphy_dfi_p0_cas_n; @@ -100,328 +121,328 @@ wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; wire soc_ddrphy_dfi_p3_rddata_en; wire [31:0] soc_ddrphy_dfi_p3_rddata; wire soc_ddrphy_dfi_p3_rddata_valid; -reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel0_write = 1'd0; -reg soc_ddrphy_dfiphasemodel0_read = 1'd0; -reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel1_write = 1'd0; -reg soc_ddrphy_dfiphasemodel1_read = 1'd0; -reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel2_write = 1'd0; -reg soc_ddrphy_dfiphasemodel2_read = 1'd0; -reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel3_write = 1'd0; -reg soc_ddrphy_dfiphasemodel3_read = 1'd0; -reg soc_ddrphy_bankmodel0_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; -reg soc_ddrphy_bankmodel0_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel0_write = 1'd0; +reg soc_ddrphy_dfiphasemodel0_read = 1'd0; +reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel1_write = 1'd0; +reg soc_ddrphy_dfiphasemodel1_read = 1'd0; +reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel2_write = 1'd0; +reg soc_ddrphy_dfiphasemodel2_read = 1'd0; +reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel3_write = 1'd0; +reg soc_ddrphy_dfiphasemodel3_read = 1'd0; +reg soc_ddrphy_bankmodel0_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; +reg soc_ddrphy_bankmodel0_precharge = 1'd0; wire soc_ddrphy_bankmodel0_write; wire [9:0] soc_ddrphy_bankmodel0_write_col; wire [127:0] soc_ddrphy_bankmodel0_write_data; wire [15:0] soc_ddrphy_bankmodel0_write_mask; -reg soc_ddrphy_bankmodel0_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; -reg soc_ddrphy_bankmodel0_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel0_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; +reg soc_ddrphy_bankmodel0_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel0_wraddr; wire [20:0] soc_ddrphy_bankmodel0_rdaddr; -reg soc_ddrphy_bankmodel1_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; -reg soc_ddrphy_bankmodel1_precharge = 1'd0; +reg soc_ddrphy_bankmodel1_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; +reg soc_ddrphy_bankmodel1_precharge = 1'd0; wire soc_ddrphy_bankmodel1_write; wire [9:0] soc_ddrphy_bankmodel1_write_col; wire [127:0] soc_ddrphy_bankmodel1_write_data; wire [15:0] soc_ddrphy_bankmodel1_write_mask; -reg soc_ddrphy_bankmodel1_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; -reg soc_ddrphy_bankmodel1_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel1_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; +reg soc_ddrphy_bankmodel1_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel1_wraddr; wire [20:0] soc_ddrphy_bankmodel1_rdaddr; -reg soc_ddrphy_bankmodel2_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0; -reg soc_ddrphy_bankmodel2_precharge = 1'd0; +reg soc_ddrphy_bankmodel2_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0; +reg soc_ddrphy_bankmodel2_precharge = 1'd0; wire soc_ddrphy_bankmodel2_write; wire [9:0] soc_ddrphy_bankmodel2_write_col; wire [127:0] soc_ddrphy_bankmodel2_write_data; wire [15:0] soc_ddrphy_bankmodel2_write_mask; -reg soc_ddrphy_bankmodel2_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; -reg soc_ddrphy_bankmodel2_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel2_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; +reg soc_ddrphy_bankmodel2_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel2_wraddr; wire [20:0] soc_ddrphy_bankmodel2_rdaddr; -reg soc_ddrphy_bankmodel3_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0; -reg soc_ddrphy_bankmodel3_precharge = 1'd0; +reg soc_ddrphy_bankmodel3_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0; +reg soc_ddrphy_bankmodel3_precharge = 1'd0; wire soc_ddrphy_bankmodel3_write; wire [9:0] soc_ddrphy_bankmodel3_write_col; wire [127:0] soc_ddrphy_bankmodel3_write_data; wire [15:0] soc_ddrphy_bankmodel3_write_mask; -reg soc_ddrphy_bankmodel3_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; -reg soc_ddrphy_bankmodel3_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel3_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; +reg soc_ddrphy_bankmodel3_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel3_wraddr; wire [20:0] soc_ddrphy_bankmodel3_rdaddr; -reg soc_ddrphy_bankmodel4_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0; -reg soc_ddrphy_bankmodel4_precharge = 1'd0; +reg soc_ddrphy_bankmodel4_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0; +reg soc_ddrphy_bankmodel4_precharge = 1'd0; wire soc_ddrphy_bankmodel4_write; wire [9:0] soc_ddrphy_bankmodel4_write_col; wire [127:0] soc_ddrphy_bankmodel4_write_data; wire [15:0] soc_ddrphy_bankmodel4_write_mask; -reg soc_ddrphy_bankmodel4_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; -reg soc_ddrphy_bankmodel4_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel4_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; +reg soc_ddrphy_bankmodel4_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel4_wraddr; wire [20:0] soc_ddrphy_bankmodel4_rdaddr; -reg soc_ddrphy_bankmodel5_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0; -reg soc_ddrphy_bankmodel5_precharge = 1'd0; +reg soc_ddrphy_bankmodel5_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0; +reg soc_ddrphy_bankmodel5_precharge = 1'd0; wire soc_ddrphy_bankmodel5_write; wire [9:0] soc_ddrphy_bankmodel5_write_col; wire [127:0] soc_ddrphy_bankmodel5_write_data; wire [15:0] soc_ddrphy_bankmodel5_write_mask; -reg soc_ddrphy_bankmodel5_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; -reg soc_ddrphy_bankmodel5_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel5_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; +reg soc_ddrphy_bankmodel5_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel5_wraddr; wire [20:0] soc_ddrphy_bankmodel5_rdaddr; -reg soc_ddrphy_bankmodel6_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0; -reg soc_ddrphy_bankmodel6_precharge = 1'd0; +reg soc_ddrphy_bankmodel6_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0; +reg soc_ddrphy_bankmodel6_precharge = 1'd0; wire soc_ddrphy_bankmodel6_write; wire [9:0] soc_ddrphy_bankmodel6_write_col; wire [127:0] soc_ddrphy_bankmodel6_write_data; wire [15:0] soc_ddrphy_bankmodel6_write_mask; -reg soc_ddrphy_bankmodel6_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; -reg soc_ddrphy_bankmodel6_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel6_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; +reg soc_ddrphy_bankmodel6_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel6_wraddr; wire [20:0] soc_ddrphy_bankmodel6_rdaddr; -reg soc_ddrphy_bankmodel7_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0; -reg soc_ddrphy_bankmodel7_precharge = 1'd0; +reg soc_ddrphy_bankmodel7_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0; +reg soc_ddrphy_bankmodel7_precharge = 1'd0; wire soc_ddrphy_bankmodel7_write; wire [9:0] soc_ddrphy_bankmodel7_write_col; wire [127:0] soc_ddrphy_bankmodel7_write_data; wire [15:0] soc_ddrphy_bankmodel7_write_mask; -reg soc_ddrphy_bankmodel7_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; -reg soc_ddrphy_bankmodel7_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0; +reg soc_ddrphy_bankmodel7_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; +reg soc_ddrphy_bankmodel7_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; +reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; wire [20:0] soc_ddrphy_bankmodel7_wraddr; wire [20:0] soc_ddrphy_bankmodel7_rdaddr; -reg [3:0] soc_ddrphy_activates0 = 4'd0; -reg [3:0] soc_ddrphy_precharges0 = 4'd0; -reg soc_ddrphy_bank_write0 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; -reg [3:0] soc_ddrphy_writes0 = 4'd0; -reg soc_ddrphy_new_bank_write0 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; -reg [3:0] soc_ddrphy_reads0 = 4'd0; -reg [3:0] soc_ddrphy_activates1 = 4'd0; -reg [3:0] soc_ddrphy_precharges1 = 4'd0; -reg soc_ddrphy_bank_write1 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; -reg [3:0] soc_ddrphy_writes1 = 4'd0; -reg soc_ddrphy_new_bank_write1 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; -reg [3:0] soc_ddrphy_reads1 = 4'd0; -reg [3:0] soc_ddrphy_activates2 = 4'd0; -reg [3:0] soc_ddrphy_precharges2 = 4'd0; -reg soc_ddrphy_bank_write2 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; -reg [3:0] soc_ddrphy_writes2 = 4'd0; -reg soc_ddrphy_new_bank_write2 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; -reg [3:0] soc_ddrphy_reads2 = 4'd0; -reg [3:0] soc_ddrphy_activates3 = 4'd0; -reg [3:0] soc_ddrphy_precharges3 = 4'd0; -reg soc_ddrphy_bank_write3 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; -reg [3:0] soc_ddrphy_writes3 = 4'd0; -reg soc_ddrphy_new_bank_write3 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; -reg [3:0] soc_ddrphy_reads3 = 4'd0; -reg [3:0] soc_ddrphy_activates4 = 4'd0; -reg [3:0] soc_ddrphy_precharges4 = 4'd0; -reg soc_ddrphy_bank_write4 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; -reg [3:0] soc_ddrphy_writes4 = 4'd0; -reg soc_ddrphy_new_bank_write4 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; -reg [3:0] soc_ddrphy_reads4 = 4'd0; -reg [3:0] soc_ddrphy_activates5 = 4'd0; -reg [3:0] soc_ddrphy_precharges5 = 4'd0; -reg soc_ddrphy_bank_write5 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; -reg [3:0] soc_ddrphy_writes5 = 4'd0; -reg soc_ddrphy_new_bank_write5 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; -reg [3:0] soc_ddrphy_reads5 = 4'd0; -reg [3:0] soc_ddrphy_activates6 = 4'd0; -reg [3:0] soc_ddrphy_precharges6 = 4'd0; -reg soc_ddrphy_bank_write6 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; -reg [3:0] soc_ddrphy_writes6 = 4'd0; -reg soc_ddrphy_new_bank_write6 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; -reg [3:0] soc_ddrphy_reads6 = 4'd0; -reg [3:0] soc_ddrphy_activates7 = 4'd0; -reg [3:0] soc_ddrphy_precharges7 = 4'd0; -reg soc_ddrphy_bank_write7 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; -reg [3:0] soc_ddrphy_writes7 = 4'd0; -reg soc_ddrphy_new_bank_write7 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; -reg [3:0] soc_ddrphy_reads7 = 4'd0; +reg [3:0] soc_ddrphy_activates0 = 4'd0; +reg [3:0] soc_ddrphy_precharges0 = 4'd0; +reg soc_ddrphy_bank_write0 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; +reg [3:0] soc_ddrphy_writes0 = 4'd0; +reg soc_ddrphy_new_bank_write0 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; +reg [3:0] soc_ddrphy_reads0 = 4'd0; +reg [3:0] soc_ddrphy_activates1 = 4'd0; +reg [3:0] soc_ddrphy_precharges1 = 4'd0; +reg soc_ddrphy_bank_write1 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; +reg [3:0] soc_ddrphy_writes1 = 4'd0; +reg soc_ddrphy_new_bank_write1 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; +reg [3:0] soc_ddrphy_reads1 = 4'd0; +reg [3:0] soc_ddrphy_activates2 = 4'd0; +reg [3:0] soc_ddrphy_precharges2 = 4'd0; +reg soc_ddrphy_bank_write2 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; +reg [3:0] soc_ddrphy_writes2 = 4'd0; +reg soc_ddrphy_new_bank_write2 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; +reg [3:0] soc_ddrphy_reads2 = 4'd0; +reg [3:0] soc_ddrphy_activates3 = 4'd0; +reg [3:0] soc_ddrphy_precharges3 = 4'd0; +reg soc_ddrphy_bank_write3 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; +reg [3:0] soc_ddrphy_writes3 = 4'd0; +reg soc_ddrphy_new_bank_write3 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; +reg [3:0] soc_ddrphy_reads3 = 4'd0; +reg [3:0] soc_ddrphy_activates4 = 4'd0; +reg [3:0] soc_ddrphy_precharges4 = 4'd0; +reg soc_ddrphy_bank_write4 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; +reg [3:0] soc_ddrphy_writes4 = 4'd0; +reg soc_ddrphy_new_bank_write4 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; +reg [3:0] soc_ddrphy_reads4 = 4'd0; +reg [3:0] soc_ddrphy_activates5 = 4'd0; +reg [3:0] soc_ddrphy_precharges5 = 4'd0; +reg soc_ddrphy_bank_write5 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; +reg [3:0] soc_ddrphy_writes5 = 4'd0; +reg soc_ddrphy_new_bank_write5 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; +reg [3:0] soc_ddrphy_reads5 = 4'd0; +reg [3:0] soc_ddrphy_activates6 = 4'd0; +reg [3:0] soc_ddrphy_precharges6 = 4'd0; +reg soc_ddrphy_bank_write6 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; +reg [3:0] soc_ddrphy_writes6 = 4'd0; +reg soc_ddrphy_new_bank_write6 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; +reg [3:0] soc_ddrphy_reads6 = 4'd0; +reg [3:0] soc_ddrphy_activates7 = 4'd0; +reg [3:0] soc_ddrphy_precharges7 = 4'd0; +reg soc_ddrphy_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; +reg [3:0] soc_ddrphy_writes7 = 4'd0; +reg soc_ddrphy_new_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; +reg [3:0] soc_ddrphy_reads7 = 4'd0; wire soc_ddrphy_banks_read; wire [127:0] soc_ddrphy_banks_read_data; -reg soc_ddrphy_new_banks_read0 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; -reg soc_ddrphy_new_banks_read1 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; -reg soc_ddrphy_new_banks_read2 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; -reg soc_ddrphy_new_banks_read3 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; -reg soc_ddrphy_new_banks_read4 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; -reg soc_ddrphy_new_banks_read5 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; -reg soc_ddrphy_new_banks_read6 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; -reg soc_ddrphy_new_banks_read7 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; +reg soc_ddrphy_new_banks_read0 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; +reg soc_ddrphy_new_banks_read1 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; +reg soc_ddrphy_new_banks_read2 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; +reg soc_ddrphy_new_banks_read3 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; +reg soc_ddrphy_new_banks_read4 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; +reg soc_ddrphy_new_banks_read5 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; +reg soc_ddrphy_new_banks_read6 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; +reg soc_ddrphy_new_banks_read7 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; wire [13:0] soc_litedramcore_inti_p0_address; wire [2:0] soc_litedramcore_inti_p0_bank; -reg soc_litedramcore_inti_p0_cas_n = 1'd1; -reg soc_litedramcore_inti_p0_cs_n = 1'd1; -reg soc_litedramcore_inti_p0_ras_n = 1'd1; -reg soc_litedramcore_inti_p0_we_n = 1'd1; +reg soc_litedramcore_inti_p0_cas_n = 1'd1; +reg soc_litedramcore_inti_p0_cs_n = 1'd1; +reg soc_litedramcore_inti_p0_ras_n = 1'd1; +reg soc_litedramcore_inti_p0_we_n = 1'd1; wire soc_litedramcore_inti_p0_cke; wire soc_litedramcore_inti_p0_odt; wire soc_litedramcore_inti_p0_reset_n; -reg soc_litedramcore_inti_p0_act_n = 1'd1; +reg soc_litedramcore_inti_p0_act_n = 1'd1; wire [31:0] soc_litedramcore_inti_p0_wrdata; wire soc_litedramcore_inti_p0_wrdata_en; wire [3:0] soc_litedramcore_inti_p0_wrdata_mask; wire soc_litedramcore_inti_p0_rddata_en; -reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; -reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0; +reg soc_litedramcore_inti_p0_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_inti_p1_address; wire [2:0] soc_litedramcore_inti_p1_bank; -reg soc_litedramcore_inti_p1_cas_n = 1'd1; -reg soc_litedramcore_inti_p1_cs_n = 1'd1; -reg soc_litedramcore_inti_p1_ras_n = 1'd1; -reg soc_litedramcore_inti_p1_we_n = 1'd1; +reg soc_litedramcore_inti_p1_cas_n = 1'd1; +reg soc_litedramcore_inti_p1_cs_n = 1'd1; +reg soc_litedramcore_inti_p1_ras_n = 1'd1; +reg soc_litedramcore_inti_p1_we_n = 1'd1; wire soc_litedramcore_inti_p1_cke; wire soc_litedramcore_inti_p1_odt; wire soc_litedramcore_inti_p1_reset_n; -reg soc_litedramcore_inti_p1_act_n = 1'd1; +reg soc_litedramcore_inti_p1_act_n = 1'd1; wire [31:0] soc_litedramcore_inti_p1_wrdata; wire soc_litedramcore_inti_p1_wrdata_en; wire [3:0] soc_litedramcore_inti_p1_wrdata_mask; wire soc_litedramcore_inti_p1_rddata_en; -reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; -reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0; +reg soc_litedramcore_inti_p1_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_inti_p2_address; wire [2:0] soc_litedramcore_inti_p2_bank; -reg soc_litedramcore_inti_p2_cas_n = 1'd1; -reg soc_litedramcore_inti_p2_cs_n = 1'd1; -reg soc_litedramcore_inti_p2_ras_n = 1'd1; -reg soc_litedramcore_inti_p2_we_n = 1'd1; +reg soc_litedramcore_inti_p2_cas_n = 1'd1; +reg soc_litedramcore_inti_p2_cs_n = 1'd1; +reg soc_litedramcore_inti_p2_ras_n = 1'd1; +reg soc_litedramcore_inti_p2_we_n = 1'd1; wire soc_litedramcore_inti_p2_cke; wire soc_litedramcore_inti_p2_odt; wire soc_litedramcore_inti_p2_reset_n; -reg soc_litedramcore_inti_p2_act_n = 1'd1; +reg soc_litedramcore_inti_p2_act_n = 1'd1; wire [31:0] soc_litedramcore_inti_p2_wrdata; wire soc_litedramcore_inti_p2_wrdata_en; wire [3:0] soc_litedramcore_inti_p2_wrdata_mask; wire soc_litedramcore_inti_p2_rddata_en; -reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; -reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0; +reg soc_litedramcore_inti_p2_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_inti_p3_address; wire [2:0] soc_litedramcore_inti_p3_bank; -reg soc_litedramcore_inti_p3_cas_n = 1'd1; -reg soc_litedramcore_inti_p3_cs_n = 1'd1; -reg soc_litedramcore_inti_p3_ras_n = 1'd1; -reg soc_litedramcore_inti_p3_we_n = 1'd1; +reg soc_litedramcore_inti_p3_cas_n = 1'd1; +reg soc_litedramcore_inti_p3_cs_n = 1'd1; +reg soc_litedramcore_inti_p3_ras_n = 1'd1; +reg soc_litedramcore_inti_p3_we_n = 1'd1; wire soc_litedramcore_inti_p3_cke; wire soc_litedramcore_inti_p3_odt; wire soc_litedramcore_inti_p3_reset_n; -reg soc_litedramcore_inti_p3_act_n = 1'd1; +reg soc_litedramcore_inti_p3_act_n = 1'd1; wire [31:0] soc_litedramcore_inti_p3_wrdata; wire soc_litedramcore_inti_p3_wrdata_en; wire [3:0] soc_litedramcore_inti_p3_wrdata_mask; wire soc_litedramcore_inti_p3_rddata_en; -reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; -reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0; +reg soc_litedramcore_inti_p3_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_slave_p0_address; wire [2:0] soc_litedramcore_slave_p0_bank; wire soc_litedramcore_slave_p0_cas_n; @@ -436,8 +457,8 @@ wire [31:0] soc_litedramcore_slave_p0_wrdata; wire soc_litedramcore_slave_p0_wrdata_en; wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; wire soc_litedramcore_slave_p0_rddata_en; -reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_slave_p1_address; wire [2:0] soc_litedramcore_slave_p1_bank; wire soc_litedramcore_slave_p1_cas_n; @@ -452,8 +473,8 @@ wire [31:0] soc_litedramcore_slave_p1_wrdata; wire soc_litedramcore_slave_p1_wrdata_en; wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; wire soc_litedramcore_slave_p1_rddata_en; -reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_slave_p2_address; wire [2:0] soc_litedramcore_slave_p2_bank; wire soc_litedramcore_slave_p2_cas_n; @@ -468,8 +489,8 @@ wire [31:0] soc_litedramcore_slave_p2_wrdata; wire soc_litedramcore_slave_p2_wrdata_en; wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; wire soc_litedramcore_slave_p2_rddata_en; -reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; wire [13:0] soc_litedramcore_slave_p3_address; wire [2:0] soc_litedramcore_slave_p3_bank; wire soc_litedramcore_slave_p3_cas_n; @@ -484,138 +505,138 @@ wire [31:0] soc_litedramcore_slave_p3_wrdata; wire soc_litedramcore_slave_p3_wrdata_en; wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; wire soc_litedramcore_slave_p3_rddata_en; -reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_master_p0_address = 14'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; +reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_master_p0_address = 14'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; wire [31:0] soc_litedramcore_master_p0_rddata; wire soc_litedramcore_master_p0_rddata_valid; -reg [13:0] soc_litedramcore_master_p1_address = 14'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; +reg [13:0] soc_litedramcore_master_p1_address = 14'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; wire [31:0] soc_litedramcore_master_p1_rddata; wire soc_litedramcore_master_p1_rddata_valid; -reg [13:0] soc_litedramcore_master_p2_address = 14'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; +reg [13:0] soc_litedramcore_master_p2_address = 14'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; wire [31:0] soc_litedramcore_master_p2_rddata; wire soc_litedramcore_master_p2_rddata_valid; -reg [13:0] soc_litedramcore_master_p3_address = 14'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; +reg [13:0] soc_litedramcore_master_p3_address = 14'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] soc_litedramcore_master_p3_rddata; wire soc_litedramcore_master_p3_rddata_valid; wire soc_litedramcore_sel; wire soc_litedramcore_cke; wire soc_litedramcore_odt; wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector0_command_re = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; wire soc_litedramcore_phaseinjector0_command_issue_r; -reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; wire soc_litedramcore_phaseinjector0_rddata_we; -reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector1_command_re = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; wire soc_litedramcore_phaseinjector1_command_issue_r; -reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; wire soc_litedramcore_phaseinjector1_rddata_we; -reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector2_command_re = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; wire soc_litedramcore_phaseinjector2_command_issue_r; -reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; wire soc_litedramcore_phaseinjector2_rddata_we; -reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector3_command_re = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; wire soc_litedramcore_phaseinjector3_command_issue_r; -reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; +reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; wire soc_litedramcore_phaseinjector3_rddata_we; -reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; wire soc_litedramcore_interface_bank0_valid; wire soc_litedramcore_interface_bank0_ready; wire soc_litedramcore_interface_bank0_we; @@ -672,131 +693,131 @@ wire [20:0] soc_litedramcore_interface_bank7_addr; wire soc_litedramcore_interface_bank7_lock; wire soc_litedramcore_interface_bank7_wdata_ready; wire soc_litedramcore_interface_bank7_rdata_valid; -reg [127:0] soc_litedramcore_interface_wdata = 128'd0; -reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; +reg [127:0] soc_litedramcore_interface_wdata = 128'd0; +reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; wire [127:0] soc_litedramcore_interface_rdata; -reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; wire soc_litedramcore_dfi_p0_cke; wire soc_litedramcore_dfi_p0_odt; wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; wire [31:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; wire [31:0] soc_litedramcore_dfi_p0_rddata; wire soc_litedramcore_dfi_p0_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; wire soc_litedramcore_dfi_p1_cke; wire soc_litedramcore_dfi_p1_odt; wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; wire [31:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; wire [31:0] soc_litedramcore_dfi_p1_rddata; wire soc_litedramcore_dfi_p1_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; wire soc_litedramcore_dfi_p2_cke; wire soc_litedramcore_dfi_p2_odt; wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; wire [31:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; wire [31:0] soc_litedramcore_dfi_p2_rddata; wire soc_litedramcore_dfi_p2_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; +reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; wire soc_litedramcore_dfi_p3_cke; wire soc_litedramcore_dfi_p3_odt; wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; wire [31:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; wire [31:0] soc_litedramcore_dfi_p3_rddata; wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_last = 1'd0; +reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; wire soc_litedramcore_wants_refresh; wire soc_litedramcore_wants_zqcs; wire soc_litedramcore_timer_wait; wire soc_litedramcore_timer_done0; wire [9:0] soc_litedramcore_timer_count0; wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; +reg [9:0] soc_litedramcore_timer_count1 = 10'd781; wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; +reg soc_litedramcore_postponer_req_o = 1'd0; +reg soc_litedramcore_postponer_count = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; wire soc_litedramcore_sequencer_done0; wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; -reg soc_litedramcore_sequencer_count = 1'd0; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; +reg soc_litedramcore_sequencer_count = 1'd0; wire soc_litedramcore_zqcs_timer_wait; wire soc_litedramcore_zqcs_timer_done0; wire [26:0] soc_litedramcore_zqcs_timer_count0; wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; wire soc_litedramcore_bankmachine0_req_valid; wire soc_litedramcore_bankmachine0_req_ready; wire soc_litedramcore_bankmachine0_req_we; wire [20:0] soc_litedramcore_bankmachine0_req_addr; wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; -reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; @@ -811,11 +832,11 @@ wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; @@ -836,51 +857,51 @@ wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; -reg soc_litedramcore_bankmachine0_row_close = 1'd0; -reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_close = 1'd0; +reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine0_twtpcon_valid; -reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine0_trccon_valid; -reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; wire soc_litedramcore_bankmachine0_trascon_valid; -reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; wire soc_litedramcore_bankmachine1_req_valid; wire soc_litedramcore_bankmachine1_req_ready; wire soc_litedramcore_bankmachine1_req_we; wire [20:0] soc_litedramcore_bankmachine1_req_addr; wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; -reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; @@ -895,11 +916,11 @@ wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; @@ -920,51 +941,51 @@ wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; -reg soc_litedramcore_bankmachine1_row_close = 1'd0; -reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_close = 1'd0; +reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine1_twtpcon_valid; -reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine1_trccon_valid; -reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; wire soc_litedramcore_bankmachine1_trascon_valid; -reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; wire soc_litedramcore_bankmachine2_req_valid; wire soc_litedramcore_bankmachine2_req_ready; wire soc_litedramcore_bankmachine2_req_we; wire [20:0] soc_litedramcore_bankmachine2_req_addr; wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; -reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; @@ -979,11 +1000,11 @@ wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; @@ -1004,51 +1025,51 @@ wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; -reg soc_litedramcore_bankmachine2_row_close = 1'd0; -reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_close = 1'd0; +reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine2_twtpcon_valid; -reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine2_trccon_valid; -reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; wire soc_litedramcore_bankmachine2_trascon_valid; -reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; wire soc_litedramcore_bankmachine3_req_valid; wire soc_litedramcore_bankmachine3_req_ready; wire soc_litedramcore_bankmachine3_req_we; wire [20:0] soc_litedramcore_bankmachine3_req_addr; wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; -reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; @@ -1063,11 +1084,11 @@ wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; @@ -1088,51 +1109,51 @@ wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; -reg soc_litedramcore_bankmachine3_row_close = 1'd0; -reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_close = 1'd0; +reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine3_twtpcon_valid; -reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine3_trccon_valid; -reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; wire soc_litedramcore_bankmachine3_trascon_valid; -reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; wire soc_litedramcore_bankmachine4_req_valid; wire soc_litedramcore_bankmachine4_req_ready; wire soc_litedramcore_bankmachine4_req_we; wire [20:0] soc_litedramcore_bankmachine4_req_addr; wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; -reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; @@ -1147,11 +1168,11 @@ wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; @@ -1172,51 +1193,51 @@ wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; -reg soc_litedramcore_bankmachine4_row_close = 1'd0; -reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_close = 1'd0; +reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine4_twtpcon_valid; -reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine4_trccon_valid; -reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; wire soc_litedramcore_bankmachine4_trascon_valid; -reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; wire soc_litedramcore_bankmachine5_req_valid; wire soc_litedramcore_bankmachine5_req_ready; wire soc_litedramcore_bankmachine5_req_we; wire [20:0] soc_litedramcore_bankmachine5_req_addr; wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; -reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; @@ -1231,11 +1252,11 @@ wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; @@ -1256,51 +1277,51 @@ wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; -reg soc_litedramcore_bankmachine5_row_close = 1'd0; -reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_close = 1'd0; +reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine5_twtpcon_valid; -reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine5_trccon_valid; -reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; wire soc_litedramcore_bankmachine5_trascon_valid; -reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; wire soc_litedramcore_bankmachine6_req_valid; wire soc_litedramcore_bankmachine6_req_ready; wire soc_litedramcore_bankmachine6_req_we; wire [20:0] soc_litedramcore_bankmachine6_req_addr; wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; -reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; @@ -1315,11 +1336,11 @@ wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; @@ -1340,51 +1361,51 @@ wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; -reg soc_litedramcore_bankmachine6_row_close = 1'd0; -reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_close = 1'd0; +reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine6_twtpcon_valid; -reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine6_trccon_valid; -reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; wire soc_litedramcore_bankmachine6_trascon_valid; -reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; wire soc_litedramcore_bankmachine7_req_valid; wire soc_litedramcore_bankmachine7_req_ready; wire soc_litedramcore_bankmachine7_req_we; wire [20:0] soc_litedramcore_bankmachine7_req_addr; wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; -reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; @@ -1399,11 +1420,11 @@ wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; @@ -1424,105 +1445,105 @@ wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; -reg soc_litedramcore_bankmachine7_row_close = 1'd0; -reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_close = 1'd0; +reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire soc_litedramcore_bankmachine7_twtpcon_valid; -reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; wire soc_litedramcore_bankmachine7_trccon_valid; -reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; wire soc_litedramcore_bankmachine7_trascon_valid; -reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; +reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; wire soc_litedramcore_ras_allowed; wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; -reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; wire soc_litedramcore_choose_cmd_cmd_payload_is_read; wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; wire [7:0] soc_litedramcore_choose_cmd_request; -reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; +reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; wire [13:0] soc_litedramcore_choose_req_cmd_payload_a; wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; -reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; wire soc_litedramcore_choose_req_cmd_payload_is_cmd; wire soc_litedramcore_choose_req_cmd_payload_is_read; wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; wire [7:0] soc_litedramcore_choose_req_request; -reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; +reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; wire soc_litedramcore_choose_req_ce; -reg [13:0] soc_litedramcore_nop_a = 14'd0; -reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; -reg soc_litedramcore_steerer4 = 1'd1; -reg soc_litedramcore_steerer5 = 1'd1; -reg soc_litedramcore_steerer6 = 1'd1; -reg soc_litedramcore_steerer7 = 1'd1; +reg [13:0] soc_litedramcore_nop_a = 14'd0; +reg [2:0] soc_litedramcore_nop_ba = 3'd0; +reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; +reg soc_litedramcore_steerer0 = 1'd1; +reg soc_litedramcore_steerer1 = 1'd1; +reg soc_litedramcore_steerer2 = 1'd1; +reg soc_litedramcore_steerer3 = 1'd1; +reg soc_litedramcore_steerer4 = 1'd1; +reg soc_litedramcore_steerer5 = 1'd1; +reg soc_litedramcore_steerer6 = 1'd1; +reg soc_litedramcore_steerer7 = 1'd1; wire soc_litedramcore_trrdcon_valid; -reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; +reg soc_litedramcore_trrdcon_ready = 1'd0; +reg soc_litedramcore_trrdcon_count = 1'd0; wire soc_litedramcore_tfawcon_valid; -reg soc_litedramcore_tfawcon_ready = 1'd1; +reg soc_litedramcore_tfawcon_ready = 1'd1; wire [2:0] soc_litedramcore_tfawcon_count; -reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; +reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; wire soc_litedramcore_tccdcon_valid; -reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; +reg soc_litedramcore_tccdcon_ready = 1'd0; +reg soc_litedramcore_tccdcon_count = 1'd0; wire soc_litedramcore_twtrcon_valid; -reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +reg soc_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; wire soc_litedramcore_read_available; wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; +reg soc_litedramcore_en0 = 1'd0; wire soc_litedramcore_max_time0; -reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; +reg [4:0] soc_litedramcore_time0 = 5'd0; +reg soc_litedramcore_en1 = 1'd0; wire soc_litedramcore_max_time1; -reg [3:0] soc_litedramcore_time1 = 4'd0; +reg [3:0] soc_litedramcore_time1 = 4'd0; wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; wire [29:0] soc_wb_bus_adr; wire [31:0] soc_wb_bus_dat_w; wire [31:0] soc_wb_bus_dat_r; @@ -1534,6 +1555,7 @@ wire soc_wb_bus_we; wire [2:0] soc_wb_bus_cti; wire [1:0] soc_wb_bus_bte; wire soc_wb_bus_err; +wire soc_user_enable; wire soc_user_port_cmd_valid; wire soc_user_port_cmd_ready; wire soc_user_port_cmd_payload_we; @@ -1545,26 +1567,26 @@ wire [15:0] soc_user_port_wdata_payload_we; wire soc_user_port_rdata_valid; wire soc_user_port_rdata_ready; wire [127:0] soc_user_port_rdata_payload_data; -reg [1:0] refresher_state = 2'd0; -reg [1:0] refresher_next_state = 2'd0; -reg [3:0] bankmachine0_state = 4'd0; -reg [3:0] bankmachine0_next_state = 4'd0; -reg [3:0] bankmachine1_state = 4'd0; -reg [3:0] bankmachine1_next_state = 4'd0; -reg [3:0] bankmachine2_state = 4'd0; -reg [3:0] bankmachine2_next_state = 4'd0; -reg [3:0] bankmachine3_state = 4'd0; -reg [3:0] bankmachine3_next_state = 4'd0; -reg [3:0] bankmachine4_state = 4'd0; -reg [3:0] bankmachine4_next_state = 4'd0; -reg [3:0] bankmachine5_state = 4'd0; -reg [3:0] bankmachine5_next_state = 4'd0; -reg [3:0] bankmachine6_state = 4'd0; -reg [3:0] bankmachine6_next_state = 4'd0; -reg [3:0] bankmachine7_state = 4'd0; -reg [3:0] bankmachine7_next_state = 4'd0; -reg [3:0] multiplexer_state = 4'd0; -reg [3:0] multiplexer_next_state = 4'd0; +reg [1:0] refresher_state = 2'd0; +reg [1:0] refresher_next_state = 2'd0; +reg [3:0] bankmachine0_state = 4'd0; +reg [3:0] bankmachine0_next_state = 4'd0; +reg [3:0] bankmachine1_state = 4'd0; +reg [3:0] bankmachine1_next_state = 4'd0; +reg [3:0] bankmachine2_state = 4'd0; +reg [3:0] bankmachine2_next_state = 4'd0; +reg [3:0] bankmachine3_state = 4'd0; +reg [3:0] bankmachine3_next_state = 4'd0; +reg [3:0] bankmachine4_state = 4'd0; +reg [3:0] bankmachine4_next_state = 4'd0; +reg [3:0] bankmachine5_state = 4'd0; +reg [3:0] bankmachine5_next_state = 4'd0; +reg [3:0] bankmachine6_state = 4'd0; +reg [3:0] bankmachine6_next_state = 4'd0; +reg [3:0] bankmachine7_state = 4'd0; +reg [3:0] bankmachine7_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg [3:0] multiplexer_next_state = 4'd0; wire roundrobin0_request; wire roundrobin0_grant; wire roundrobin0_ce; @@ -1589,266 +1611,154 @@ wire roundrobin6_ce; wire roundrobin7_request; wire roundrobin7_grant; wire roundrobin7_ce; -reg locked0 = 1'd0; -reg locked1 = 1'd0; -reg locked2 = 1'd0; -reg locked3 = 1'd0; -reg locked4 = 1'd0; -reg locked5 = 1'd0; -reg locked6 = 1'd0; -reg locked7 = 1'd0; -reg new_master_wdata_ready0 = 1'd0; -reg new_master_wdata_ready1 = 1'd0; -reg new_master_rdata_valid0 = 1'd0; -reg new_master_rdata_valid1 = 1'd0; -reg new_master_rdata_valid2 = 1'd0; -reg new_master_rdata_valid3 = 1'd0; -reg new_master_rdata_valid4 = 1'd0; -reg new_master_rdata_valid5 = 1'd0; -reg new_master_rdata_valid6 = 1'd0; -reg new_master_rdata_valid7 = 1'd0; -reg new_master_rdata_valid8 = 1'd0; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [7:0] litedramcore_dat_w = 8'd0; -wire [7:0] litedramcore_dat_r; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; wire [29:0] litedramcore_wishbone_adr; wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; wire [3:0] litedramcore_wishbone_sel; wire litedramcore_wishbone_cyc; wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; +reg litedramcore_wishbone_ack = 1'd0; wire litedramcore_wishbone_we; wire [2:0] litedramcore_wishbone_cti; wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; +reg litedramcore_wishbone_err = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; -wire [7:0] interface0_bank_bus_dat_w; -reg [7:0] interface0_bank_bus_dat_r = 8'd0; -reg csrbank0_init_done0_re = 1'd0; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; +reg csrbank0_init_done0_we = 1'd0; wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; +reg csrbank0_init_error0_re = 1'd0; wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; +reg csrbank0_init_error0_we = 1'd0; wire csrbank0_init_error0_w; wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; -wire [7:0] interface1_bank_bus_dat_w; -reg [7:0] interface1_bank_bus_dat_r = 8'd0; -reg csrbank1_dfii_control0_re = 1'd0; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_dfii_control0_re = 1'd0; wire [3:0] csrbank1_dfii_control0_r; -reg csrbank1_dfii_control0_we = 1'd0; +reg csrbank1_dfii_control0_we = 1'd0; wire [3:0] csrbank1_dfii_control0_w; -reg csrbank1_dfii_pi0_command0_re = 1'd0; +reg csrbank1_dfii_pi0_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi0_command0_r; -reg csrbank1_dfii_pi0_command0_we = 1'd0; +reg csrbank1_dfii_pi0_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi0_command0_w; -reg csrbank1_dfii_pi0_address1_re = 1'd0; -wire [5:0] csrbank1_dfii_pi0_address1_r; -reg csrbank1_dfii_pi0_address1_we = 1'd0; -wire [5:0] csrbank1_dfii_pi0_address1_w; -reg csrbank1_dfii_pi0_address0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_address0_r; -reg csrbank1_dfii_pi0_address0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_address0_w; -reg csrbank1_dfii_pi0_baddress0_re = 1'd0; +reg csrbank1_dfii_pi0_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi0_address0_r; +reg csrbank1_dfii_pi0_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi0_address0_w; +reg csrbank1_dfii_pi0_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi0_baddress0_r; -reg csrbank1_dfii_pi0_baddress0_we = 1'd0; +reg csrbank1_dfii_pi0_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi0_baddress0_w; -reg csrbank1_dfii_pi0_wrdata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata3_r; -reg csrbank1_dfii_pi0_wrdata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata3_w; -reg csrbank1_dfii_pi0_wrdata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata2_r; -reg csrbank1_dfii_pi0_wrdata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata2_w; -reg csrbank1_dfii_pi0_wrdata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata1_r; -reg csrbank1_dfii_pi0_wrdata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata1_w; -reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata0_r; -reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_wrdata0_w; -reg csrbank1_dfii_pi0_rddata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata3_r; -reg csrbank1_dfii_pi0_rddata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata3_w; -reg csrbank1_dfii_pi0_rddata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata2_r; -reg csrbank1_dfii_pi0_rddata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata2_w; -reg csrbank1_dfii_pi0_rddata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata1_r; -reg csrbank1_dfii_pi0_rddata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata1_w; -reg csrbank1_dfii_pi0_rddata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata0_r; -reg csrbank1_dfii_pi0_rddata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi0_rddata0_w; -reg csrbank1_dfii_pi1_command0_re = 1'd0; +reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi0_wrdata0_r; +reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi0_wrdata0_w; +reg csrbank1_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi0_rddata_r; +reg csrbank1_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi0_rddata_w; +reg csrbank1_dfii_pi1_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi1_command0_r; -reg csrbank1_dfii_pi1_command0_we = 1'd0; +reg csrbank1_dfii_pi1_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi1_command0_w; -reg csrbank1_dfii_pi1_address1_re = 1'd0; -wire [5:0] csrbank1_dfii_pi1_address1_r; -reg csrbank1_dfii_pi1_address1_we = 1'd0; -wire [5:0] csrbank1_dfii_pi1_address1_w; -reg csrbank1_dfii_pi1_address0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_address0_r; -reg csrbank1_dfii_pi1_address0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_address0_w; -reg csrbank1_dfii_pi1_baddress0_re = 1'd0; +reg csrbank1_dfii_pi1_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi1_address0_r; +reg csrbank1_dfii_pi1_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi1_address0_w; +reg csrbank1_dfii_pi1_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi1_baddress0_r; -reg csrbank1_dfii_pi1_baddress0_we = 1'd0; +reg csrbank1_dfii_pi1_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi1_baddress0_w; -reg csrbank1_dfii_pi1_wrdata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata3_r; -reg csrbank1_dfii_pi1_wrdata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata3_w; -reg csrbank1_dfii_pi1_wrdata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata2_r; -reg csrbank1_dfii_pi1_wrdata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata2_w; -reg csrbank1_dfii_pi1_wrdata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata1_r; -reg csrbank1_dfii_pi1_wrdata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata1_w; -reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata0_r; -reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_wrdata0_w; -reg csrbank1_dfii_pi1_rddata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata3_r; -reg csrbank1_dfii_pi1_rddata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata3_w; -reg csrbank1_dfii_pi1_rddata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata2_r; -reg csrbank1_dfii_pi1_rddata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata2_w; -reg csrbank1_dfii_pi1_rddata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata1_r; -reg csrbank1_dfii_pi1_rddata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata1_w; -reg csrbank1_dfii_pi1_rddata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata0_r; -reg csrbank1_dfii_pi1_rddata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi1_rddata0_w; -reg csrbank1_dfii_pi2_command0_re = 1'd0; +reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi1_wrdata0_r; +reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi1_wrdata0_w; +reg csrbank1_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi1_rddata_r; +reg csrbank1_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi1_rddata_w; +reg csrbank1_dfii_pi2_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi2_command0_r; -reg csrbank1_dfii_pi2_command0_we = 1'd0; +reg csrbank1_dfii_pi2_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi2_command0_w; -reg csrbank1_dfii_pi2_address1_re = 1'd0; -wire [5:0] csrbank1_dfii_pi2_address1_r; -reg csrbank1_dfii_pi2_address1_we = 1'd0; -wire [5:0] csrbank1_dfii_pi2_address1_w; -reg csrbank1_dfii_pi2_address0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_address0_r; -reg csrbank1_dfii_pi2_address0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_address0_w; -reg csrbank1_dfii_pi2_baddress0_re = 1'd0; +reg csrbank1_dfii_pi2_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi2_address0_r; +reg csrbank1_dfii_pi2_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi2_address0_w; +reg csrbank1_dfii_pi2_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi2_baddress0_r; -reg csrbank1_dfii_pi2_baddress0_we = 1'd0; +reg csrbank1_dfii_pi2_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi2_baddress0_w; -reg csrbank1_dfii_pi2_wrdata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata3_r; -reg csrbank1_dfii_pi2_wrdata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata3_w; -reg csrbank1_dfii_pi2_wrdata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata2_r; -reg csrbank1_dfii_pi2_wrdata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata2_w; -reg csrbank1_dfii_pi2_wrdata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata1_r; -reg csrbank1_dfii_pi2_wrdata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata1_w; -reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata0_r; -reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_wrdata0_w; -reg csrbank1_dfii_pi2_rddata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata3_r; -reg csrbank1_dfii_pi2_rddata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata3_w; -reg csrbank1_dfii_pi2_rddata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata2_r; -reg csrbank1_dfii_pi2_rddata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata2_w; -reg csrbank1_dfii_pi2_rddata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata1_r; -reg csrbank1_dfii_pi2_rddata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata1_w; -reg csrbank1_dfii_pi2_rddata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata0_r; -reg csrbank1_dfii_pi2_rddata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi2_rddata0_w; -reg csrbank1_dfii_pi3_command0_re = 1'd0; +reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi2_wrdata0_r; +reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi2_wrdata0_w; +reg csrbank1_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi2_rddata_r; +reg csrbank1_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi2_rddata_w; +reg csrbank1_dfii_pi3_command0_re = 1'd0; wire [5:0] csrbank1_dfii_pi3_command0_r; -reg csrbank1_dfii_pi3_command0_we = 1'd0; +reg csrbank1_dfii_pi3_command0_we = 1'd0; wire [5:0] csrbank1_dfii_pi3_command0_w; -reg csrbank1_dfii_pi3_address1_re = 1'd0; -wire [5:0] csrbank1_dfii_pi3_address1_r; -reg csrbank1_dfii_pi3_address1_we = 1'd0; -wire [5:0] csrbank1_dfii_pi3_address1_w; -reg csrbank1_dfii_pi3_address0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_address0_r; -reg csrbank1_dfii_pi3_address0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_address0_w; -reg csrbank1_dfii_pi3_baddress0_re = 1'd0; +reg csrbank1_dfii_pi3_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi3_address0_r; +reg csrbank1_dfii_pi3_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi3_address0_w; +reg csrbank1_dfii_pi3_baddress0_re = 1'd0; wire [2:0] csrbank1_dfii_pi3_baddress0_r; -reg csrbank1_dfii_pi3_baddress0_we = 1'd0; +reg csrbank1_dfii_pi3_baddress0_we = 1'd0; wire [2:0] csrbank1_dfii_pi3_baddress0_w; -reg csrbank1_dfii_pi3_wrdata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata3_r; -reg csrbank1_dfii_pi3_wrdata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata3_w; -reg csrbank1_dfii_pi3_wrdata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata2_r; -reg csrbank1_dfii_pi3_wrdata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata2_w; -reg csrbank1_dfii_pi3_wrdata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata1_r; -reg csrbank1_dfii_pi3_wrdata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata1_w; -reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata0_r; -reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_wrdata0_w; -reg csrbank1_dfii_pi3_rddata3_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata3_r; -reg csrbank1_dfii_pi3_rddata3_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata3_w; -reg csrbank1_dfii_pi3_rddata2_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata2_r; -reg csrbank1_dfii_pi3_rddata2_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata2_w; -reg csrbank1_dfii_pi3_rddata1_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata1_r; -reg csrbank1_dfii_pi3_rddata1_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata1_w; -reg csrbank1_dfii_pi3_rddata0_re = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata0_r; -reg csrbank1_dfii_pi3_rddata0_we = 1'd0; -wire [7:0] csrbank1_dfii_pi3_rddata0_w; +reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi3_wrdata0_r; +reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi3_wrdata0_w; +reg csrbank1_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi3_rddata_r; +reg csrbank1_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi3_rddata_w; wire csrbank1_sel; wire [13:0] csr_interconnect_adr; wire csr_interconnect_we; -wire [7:0] csr_interconnect_dat_w; -wire [7:0] csr_interconnect_dat_r; -reg [1:0] state = 2'd0; -reg [1:0] next_state = 2'd0; -reg [7:0] litedramcore_dat_w_next_value0 = 8'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +reg [1:0] state = 2'd0; +reg [1:0] next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; wire [24:0] slice_proxy0; wire [24:0] slice_proxy1; wire [24:0] slice_proxy2; @@ -1865,76 +1775,80 @@ wire [24:0] slice_proxy12; wire [24:0] slice_proxy13; wire [24:0] slice_proxy14; wire [24:0] slice_proxy15; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ assign init_done = soc_init_done_storage; assign init_error = soc_init_error_storage; @@ -1951,123 +1865,124 @@ assign soc_wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = soc_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready; +assign soc_user_enable = 1'd1; +assign soc_user_port_cmd_valid = (user_port_native_0_cmd_valid & soc_user_enable); +assign user_port_native_0_cmd_ready = (soc_user_port_cmd_ready & soc_user_enable); assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we; assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready; +assign soc_user_port_wdata_valid = (user_port_native_0_wdata_valid & soc_user_enable); +assign user_port_native_0_wdata_ready = (soc_user_port_wdata_ready & soc_user_enable); assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we; assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid; -assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_valid = (soc_user_port_rdata_valid & soc_user_enable); +assign soc_user_port_rdata_ready = (user_port_native_0_rdata_ready & soc_user_enable); assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data; assign sys_clk = clk; assign por_clk = clk; assign sys_rst = soc_int_rst; always @(*) begin - soc_ddrphy_activates0 = 4'd0; - soc_ddrphy_activates0[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates0[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates0[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates0[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates0 <= 4'd0; + soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel0_activate = 1'd0; + soc_ddrphy_bankmodel0_activate_row <= 14'd0; case (soc_ddrphy_activates0) 1'd1: begin - soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel0_activate_row = 14'd0; + soc_ddrphy_bankmodel0_activate <= 1'd0; case (soc_ddrphy_activates0) 1'd1: begin - soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - soc_ddrphy_precharges0 = 4'd0; - soc_ddrphy_precharges0[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges0[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges0[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges0[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges0 <= 4'd0; + soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel0_precharge = 1'd0; + soc_ddrphy_bankmodel0_precharge <= 1'd0; case (soc_ddrphy_precharges0) 1'd1: begin - soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes0 = 4'd0; - soc_ddrphy_writes0[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes0[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes0[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes0[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes0 <= 4'd0; + soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write_col0 = 10'd0; + soc_ddrphy_bank_write0 <= 1'd0; case (soc_ddrphy_writes0) 1'd1: begin - soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - soc_ddrphy_bank_write0 = 1'd0; + soc_ddrphy_bank_write_col0 <= 10'd0; case (soc_ddrphy_writes0) 1'd1: begin - soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2076,149 +1991,149 @@ assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0; assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0; always @(*) begin - soc_ddrphy_reads0 = 4'd0; - soc_ddrphy_reads0[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads0[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads0[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads0[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads0 <= 4'd0; + soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel0_read = 1'd0; + soc_ddrphy_bankmodel0_read <= 1'd0; case (soc_ddrphy_reads0) 1'd1: begin - soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - soc_ddrphy_bankmodel0_read_col = 10'd0; + soc_ddrphy_bankmodel0_read_col <= 10'd0; case (soc_ddrphy_reads0) 1'd1: begin - soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_activates1 = 4'd0; - soc_ddrphy_activates1[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates1[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates1[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates1 <= 4'd0; + soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel1_activate_row = 14'd0; + soc_ddrphy_bankmodel1_activate <= 1'd0; case (soc_ddrphy_activates1) 1'd1: begin - soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - soc_ddrphy_bankmodel1_activate = 1'd0; + soc_ddrphy_bankmodel1_activate_row <= 14'd0; case (soc_ddrphy_activates1) 1'd1: begin - soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_precharges1 = 4'd0; - soc_ddrphy_precharges1[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges1[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges1[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges1[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges1 <= 4'd0; + soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel1_precharge = 1'd0; + soc_ddrphy_bankmodel1_precharge <= 1'd0; case (soc_ddrphy_precharges1) 1'd1: begin - soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes1 = 4'd0; - soc_ddrphy_writes1[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes1[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes1[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes1[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes1 <= 4'd0; + soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write1 = 1'd0; + soc_ddrphy_bank_write1 <= 1'd0; case (soc_ddrphy_writes1) 1'd1: begin - soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - soc_ddrphy_bank_write_col1 = 10'd0; + soc_ddrphy_bank_write_col1 <= 10'd0; case (soc_ddrphy_writes1) 1'd1: begin - soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2227,149 +2142,149 @@ assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1; assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1; always @(*) begin - soc_ddrphy_reads1 = 4'd0; - soc_ddrphy_reads1[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads1[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads1[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads1[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads1 <= 4'd0; + soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel1_read = 1'd0; + soc_ddrphy_bankmodel1_read_col <= 10'd0; case (soc_ddrphy_reads1) 1'd1: begin - soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel1_read_col = 10'd0; + soc_ddrphy_bankmodel1_read <= 1'd0; case (soc_ddrphy_reads1) 1'd1: begin - soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - soc_ddrphy_activates2 = 4'd0; - soc_ddrphy_activates2[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates2[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates2[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates2[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates2 <= 4'd0; + soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel2_activate = 1'd0; + soc_ddrphy_bankmodel2_activate <= 1'd0; case (soc_ddrphy_activates2) 1'd1: begin - soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - soc_ddrphy_bankmodel2_activate_row = 14'd0; + soc_ddrphy_bankmodel2_activate_row <= 14'd0; case (soc_ddrphy_activates2) 1'd1: begin - soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_precharges2 = 4'd0; - soc_ddrphy_precharges2[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges2[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges2[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges2[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges2 <= 4'd0; + soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel2_precharge = 1'd0; + soc_ddrphy_bankmodel2_precharge <= 1'd0; case (soc_ddrphy_precharges2) 1'd1: begin - soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes2 = 4'd0; - soc_ddrphy_writes2[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes2[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes2[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes2[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes2 <= 4'd0; + soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write2 = 1'd0; + soc_ddrphy_bank_write_col2 <= 10'd0; case (soc_ddrphy_writes2) 1'd1: begin - soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bank_write_col2 = 10'd0; + soc_ddrphy_bank_write2 <= 1'd0; case (soc_ddrphy_writes2) 1'd1: begin - soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end @@ -2378,149 +2293,149 @@ assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2; assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2; always @(*) begin - soc_ddrphy_reads2 = 4'd0; - soc_ddrphy_reads2[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads2[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads2[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads2[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads2 <= 4'd0; + soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel2_read_col = 10'd0; + soc_ddrphy_bankmodel2_read <= 1'd0; case (soc_ddrphy_reads2) 1'd1: begin - soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - soc_ddrphy_bankmodel2_read = 1'd0; + soc_ddrphy_bankmodel2_read_col <= 10'd0; case (soc_ddrphy_reads2) 1'd1: begin - soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_activates3 = 4'd0; - soc_ddrphy_activates3[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates3[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates3[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates3[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates3 <= 4'd0; + soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel3_activate = 1'd0; + soc_ddrphy_bankmodel3_activate_row <= 14'd0; case (soc_ddrphy_activates3) 1'd1: begin - soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel3_activate_row = 14'd0; + soc_ddrphy_bankmodel3_activate <= 1'd0; case (soc_ddrphy_activates3) 1'd1: begin - soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - soc_ddrphy_precharges3 = 4'd0; - soc_ddrphy_precharges3[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges3[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges3[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges3[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges3 <= 4'd0; + soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel3_precharge = 1'd0; + soc_ddrphy_bankmodel3_precharge <= 1'd0; case (soc_ddrphy_precharges3) 1'd1: begin - soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes3 = 4'd0; - soc_ddrphy_writes3[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes3[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes3[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes3[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes3 <= 4'd0; + soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write3 = 1'd0; + soc_ddrphy_bank_write3 <= 1'd0; case (soc_ddrphy_writes3) 1'd1: begin - soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - soc_ddrphy_bank_write_col3 = 10'd0; + soc_ddrphy_bank_write_col3 <= 10'd0; case (soc_ddrphy_writes3) 1'd1: begin - soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2529,149 +2444,149 @@ assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3; assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3; always @(*) begin - soc_ddrphy_reads3 = 4'd0; - soc_ddrphy_reads3[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads3[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads3[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads3[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads3 <= 4'd0; + soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel3_read = 1'd0; + soc_ddrphy_bankmodel3_read <= 1'd0; case (soc_ddrphy_reads3) 1'd1: begin - soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - soc_ddrphy_bankmodel3_read_col = 10'd0; + soc_ddrphy_bankmodel3_read_col <= 10'd0; case (soc_ddrphy_reads3) 1'd1: begin - soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_activates4 = 4'd0; - soc_ddrphy_activates4[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates4[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates4[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates4[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates4 <= 4'd0; + soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel4_activate_row = 14'd0; + soc_ddrphy_bankmodel4_activate <= 1'd0; case (soc_ddrphy_activates4) 1'd1: begin - soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4); end endcase end always @(*) begin - soc_ddrphy_bankmodel4_activate = 1'd0; + soc_ddrphy_bankmodel4_activate_row <= 14'd0; case (soc_ddrphy_activates4) 1'd1: begin - soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_precharges4 = 4'd0; - soc_ddrphy_precharges4[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges4[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges4[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges4[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges4 <= 4'd0; + soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel4_precharge = 1'd0; + soc_ddrphy_bankmodel4_precharge <= 1'd0; case (soc_ddrphy_precharges4) 1'd1: begin - soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes4 = 4'd0; - soc_ddrphy_writes4[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes4[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes4[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes4[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes4 <= 4'd0; + soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write_col4 = 10'd0; + soc_ddrphy_bank_write4 <= 1'd0; case (soc_ddrphy_writes4) 1'd1: begin - soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4); end endcase end always @(*) begin - soc_ddrphy_bank_write4 = 1'd0; + soc_ddrphy_bank_write_col4 <= 10'd0; case (soc_ddrphy_writes4) 1'd1: begin - soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2680,149 +2595,149 @@ assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4; assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4; always @(*) begin - soc_ddrphy_reads4 = 4'd0; - soc_ddrphy_reads4[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads4[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads4[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads4[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads4 <= 4'd0; + soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel4_read = 1'd0; + soc_ddrphy_bankmodel4_read <= 1'd0; case (soc_ddrphy_reads4) 1'd1: begin - soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p0_bank == 3'd4); + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4); end 2'd2: begin - soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p1_bank == 3'd4); + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4); end 3'd4: begin - soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p2_bank == 3'd4); + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4); end 4'd8: begin - soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p3_bank == 3'd4); + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4); end endcase end always @(*) begin - soc_ddrphy_bankmodel4_read_col = 10'd0; + soc_ddrphy_bankmodel4_read_col <= 10'd0; case (soc_ddrphy_reads4) 1'd1: begin - soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_activates5 = 4'd0; - soc_ddrphy_activates5[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates5[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates5[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates5[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates5 <= 4'd0; + soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel5_activate = 1'd0; + soc_ddrphy_bankmodel5_activate <= 1'd0; case (soc_ddrphy_activates5) 1'd1: begin - soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - soc_ddrphy_bankmodel5_activate_row = 14'd0; + soc_ddrphy_bankmodel5_activate_row <= 14'd0; case (soc_ddrphy_activates5) 1'd1: begin - soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_precharges5 = 4'd0; - soc_ddrphy_precharges5[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges5[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges5[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges5[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges5 <= 4'd0; + soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel5_precharge = 1'd0; + soc_ddrphy_bankmodel5_precharge <= 1'd0; case (soc_ddrphy_precharges5) 1'd1: begin - soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes5 = 4'd0; - soc_ddrphy_writes5[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes5[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes5[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes5[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes5 <= 4'd0; + soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write5 = 1'd0; + soc_ddrphy_bank_write5 <= 1'd0; case (soc_ddrphy_writes5) 1'd1: begin - soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - soc_ddrphy_bank_write_col5 = 10'd0; + soc_ddrphy_bank_write_col5 <= 10'd0; case (soc_ddrphy_writes5) 1'd1: begin - soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2831,149 +2746,149 @@ assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5; assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5; always @(*) begin - soc_ddrphy_reads5 = 4'd0; - soc_ddrphy_reads5[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads5[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads5[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads5 <= 4'd0; + soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel5_read = 1'd0; + soc_ddrphy_bankmodel5_read <= 1'd0; case (soc_ddrphy_reads5) 1'd1: begin - soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end always @(*) begin - soc_ddrphy_bankmodel5_read_col = 10'd0; + soc_ddrphy_bankmodel5_read_col <= 10'd0; case (soc_ddrphy_reads5) 1'd1: begin - soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_activates6 = 4'd0; - soc_ddrphy_activates6[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates6[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates6[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates6[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates6 <= 4'd0; + soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel6_activate = 1'd0; + soc_ddrphy_bankmodel6_activate <= 1'd0; case (soc_ddrphy_activates6) 1'd1: begin - soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - soc_ddrphy_bankmodel6_activate_row = 14'd0; + soc_ddrphy_bankmodel6_activate_row <= 14'd0; case (soc_ddrphy_activates6) 1'd1: begin - soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_precharges6 = 4'd0; - soc_ddrphy_precharges6[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges6[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges6[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges6[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges6 <= 4'd0; + soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel6_precharge = 1'd0; + soc_ddrphy_bankmodel6_precharge <= 1'd0; case (soc_ddrphy_precharges6) 1'd1: begin - soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes6 = 4'd0; - soc_ddrphy_writes6[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes6[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes6[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes6[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes6 <= 4'd0; + soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write6 = 1'd0; + soc_ddrphy_bank_write_col6 <= 10'd0; case (soc_ddrphy_writes6) 1'd1: begin - soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bank_write_col6 = 10'd0; + soc_ddrphy_bank_write6 <= 1'd0; case (soc_ddrphy_writes6) 1'd1: begin - soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end @@ -2982,149 +2897,149 @@ assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6; assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6; always @(*) begin - soc_ddrphy_reads6 = 4'd0; - soc_ddrphy_reads6[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads6[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads6[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads6[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads6 <= 4'd0; + soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel6_read = 1'd0; + soc_ddrphy_bankmodel6_read_col <= 10'd0; case (soc_ddrphy_reads6) 1'd1: begin - soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel6_read_col = 10'd0; + soc_ddrphy_bankmodel6_read <= 1'd0; case (soc_ddrphy_reads6) 1'd1: begin - soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - soc_ddrphy_activates7 = 4'd0; - soc_ddrphy_activates7[0] = soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates7[1] = soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates7[2] = soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate; + soc_ddrphy_activates7 <= 4'd0; + soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel7_activate = 1'd0; + soc_ddrphy_bankmodel7_activate <= 1'd0; case (soc_ddrphy_activates7) 1'd1: begin - soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - soc_ddrphy_bankmodel7_activate_row = 14'd0; + soc_ddrphy_bankmodel7_activate_row <= 14'd0; case (soc_ddrphy_activates7) 1'd1: begin - soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_precharges7 = 4'd0; - soc_ddrphy_precharges7[0] = soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges7[1] = soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges7[2] = soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges7[3] = soc_ddrphy_dfiphasemodel3_precharge; + soc_ddrphy_precharges7 <= 4'd0; + soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge; end always @(*) begin - soc_ddrphy_bankmodel7_precharge = 1'd0; + soc_ddrphy_bankmodel7_precharge <= 1'd0; case (soc_ddrphy_precharges7) 1'd1: begin - soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]); + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]); end 2'd2: begin - soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]); + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]); end 3'd4: begin - soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]); + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]); end 4'd8: begin - soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]); + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]); end endcase end always @(*) begin - soc_ddrphy_writes7 = 4'd0; - soc_ddrphy_writes7[0] = soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes7[1] = soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes7[2] = soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes7[3] = soc_ddrphy_dfiphasemodel3_write; + soc_ddrphy_writes7 <= 4'd0; + soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write7 = 1'd0; + soc_ddrphy_bank_write7 <= 1'd0; case (soc_ddrphy_writes7) 1'd1: begin - soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - soc_ddrphy_bank_write_col7 = 10'd0; + soc_ddrphy_bank_write_col7 <= 10'd0; case (soc_ddrphy_writes7) 1'd1: begin - soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -3133,43 +3048,43 @@ assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_dd assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7; assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7; always @(*) begin - soc_ddrphy_reads7 = 4'd0; - soc_ddrphy_reads7[0] = soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads7[1] = soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads7[2] = soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read; + soc_ddrphy_reads7 <= 4'd0; + soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel7_read_col = 10'd0; + soc_ddrphy_bankmodel7_read <= 1'd0; case (soc_ddrphy_reads7) 1'd1: begin - soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end always @(*) begin - soc_ddrphy_bankmodel7_read = 1'd0; + soc_ddrphy_bankmodel7_read_col <= 10'd0; case (soc_ddrphy_reads7) 1'd1: begin - soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address; end endcase end @@ -3184,418 +3099,418 @@ assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rd assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; always @(*) begin - soc_ddrphy_dfiphasemodel0_activate = 1'd0; + soc_ddrphy_dfiphasemodel0_precharge <= 1'd0; if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin - soc_ddrphy_dfiphasemodel0_activate = soc_ddrphy_dfi_p0_we_n; + soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel0_precharge = 1'd0; + soc_ddrphy_dfiphasemodel0_activate <= 1'd0; if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin - soc_ddrphy_dfiphasemodel0_precharge = (~soc_ddrphy_dfi_p0_we_n); + soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel0_read = 1'd0; + soc_ddrphy_dfiphasemodel0_write <= 1'd0; if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin - soc_ddrphy_dfiphasemodel0_read = soc_ddrphy_dfi_p0_we_n; + soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel0_write = 1'd0; + soc_ddrphy_dfiphasemodel0_read <= 1'd0; if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin - soc_ddrphy_dfiphasemodel0_write = (~soc_ddrphy_dfi_p0_we_n); + soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel1_activate = 1'd0; + soc_ddrphy_dfiphasemodel1_activate <= 1'd0; if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin - soc_ddrphy_dfiphasemodel1_activate = soc_ddrphy_dfi_p1_we_n; + soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel1_precharge = 1'd0; + soc_ddrphy_dfiphasemodel1_precharge <= 1'd0; if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin - soc_ddrphy_dfiphasemodel1_precharge = (~soc_ddrphy_dfi_p1_we_n); + soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel1_write = 1'd0; + soc_ddrphy_dfiphasemodel1_write <= 1'd0; if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin - soc_ddrphy_dfiphasemodel1_write = (~soc_ddrphy_dfi_p1_we_n); + soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel1_read = 1'd0; + soc_ddrphy_dfiphasemodel1_read <= 1'd0; if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin - soc_ddrphy_dfiphasemodel1_read = soc_ddrphy_dfi_p1_we_n; + soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel2_precharge = 1'd0; + soc_ddrphy_dfiphasemodel2_activate <= 1'd0; if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin - soc_ddrphy_dfiphasemodel2_precharge = (~soc_ddrphy_dfi_p2_we_n); + soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel2_activate = 1'd0; + soc_ddrphy_dfiphasemodel2_precharge <= 1'd0; if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin - soc_ddrphy_dfiphasemodel2_activate = soc_ddrphy_dfi_p2_we_n; + soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel2_write = 1'd0; + soc_ddrphy_dfiphasemodel2_read <= 1'd0; if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin - soc_ddrphy_dfiphasemodel2_write = (~soc_ddrphy_dfi_p2_we_n); + soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel2_read = 1'd0; + soc_ddrphy_dfiphasemodel2_write <= 1'd0; if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin - soc_ddrphy_dfiphasemodel2_read = soc_ddrphy_dfi_p2_we_n; + soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel3_activate = 1'd0; + soc_ddrphy_dfiphasemodel3_activate <= 1'd0; if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin - soc_ddrphy_dfiphasemodel3_activate = soc_ddrphy_dfi_p3_we_n; + soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel3_precharge = 1'd0; + soc_ddrphy_dfiphasemodel3_precharge <= 1'd0; if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin - soc_ddrphy_dfiphasemodel3_precharge = (~soc_ddrphy_dfi_p3_we_n); + soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel3_write = 1'd0; + soc_ddrphy_dfiphasemodel3_write <= 1'd0; if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin - soc_ddrphy_dfiphasemodel3_write = (~soc_ddrphy_dfi_p3_we_n); + soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel3_read = 1'd0; + soc_ddrphy_dfiphasemodel3_read <= 1'd0; if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin - soc_ddrphy_dfiphasemodel3_read = soc_ddrphy_dfi_p3_we_n; + soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n; end end assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; always @(*) begin - soc_ddrphy_bankmodel0_read_data = 128'd0; + soc_ddrphy_bankmodel0_read_data <= 128'd0; if (soc_ddrphy_bankmodel0_active) begin if (soc_ddrphy_bankmodel0_read) begin - soc_ddrphy_bankmodel0_read_data = soc_ddrphy_bankmodel0_read_port_dat_r; + soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r; end end end always @(*) begin - soc_ddrphy_bankmodel0_write_port_adr = 21'd0; + soc_ddrphy_bankmodel0_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel0_active) begin - soc_ddrphy_bankmodel0_write_port_adr = soc_ddrphy_bankmodel0_wraddr; + soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr; end end always @(*) begin - soc_ddrphy_bankmodel0_write_port_we = 16'd0; + soc_ddrphy_bankmodel0_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel0_active) begin if (4'd8) begin - soc_ddrphy_bankmodel0_write_port_we = ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask)); + soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask)); end else begin - soc_ddrphy_bankmodel0_write_port_we = soc_ddrphy_bankmodel0_write; + soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write; end end end always @(*) begin - soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel0_active) begin - soc_ddrphy_bankmodel0_write_port_dat_w = soc_ddrphy_bankmodel0_write_data; + soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data; end end always @(*) begin - soc_ddrphy_bankmodel0_read_port_adr = 21'd0; + soc_ddrphy_bankmodel0_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel0_active) begin if (soc_ddrphy_bankmodel0_read) begin - soc_ddrphy_bankmodel0_read_port_adr = soc_ddrphy_bankmodel0_rdaddr; + soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr; end end end assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; always @(*) begin - soc_ddrphy_bankmodel1_read_data = 128'd0; + soc_ddrphy_bankmodel1_read_data <= 128'd0; if (soc_ddrphy_bankmodel1_active) begin if (soc_ddrphy_bankmodel1_read) begin - soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r; + soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r; end end end always @(*) begin - soc_ddrphy_bankmodel1_write_port_adr = 21'd0; + soc_ddrphy_bankmodel1_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel1_active) begin - soc_ddrphy_bankmodel1_write_port_adr = soc_ddrphy_bankmodel1_wraddr; + soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr; end end always @(*) begin - soc_ddrphy_bankmodel1_write_port_we = 16'd0; + soc_ddrphy_bankmodel1_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel1_active) begin if (4'd8) begin - soc_ddrphy_bankmodel1_write_port_we = ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask)); + soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask)); end else begin - soc_ddrphy_bankmodel1_write_port_we = soc_ddrphy_bankmodel1_write; + soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write; end end end always @(*) begin - soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel1_active) begin - soc_ddrphy_bankmodel1_write_port_dat_w = soc_ddrphy_bankmodel1_write_data; + soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data; end end always @(*) begin - soc_ddrphy_bankmodel1_read_port_adr = 21'd0; + soc_ddrphy_bankmodel1_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel1_active) begin if (soc_ddrphy_bankmodel1_read) begin - soc_ddrphy_bankmodel1_read_port_adr = soc_ddrphy_bankmodel1_rdaddr; + soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr; end end end assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; always @(*) begin - soc_ddrphy_bankmodel2_write_port_adr = 21'd0; + soc_ddrphy_bankmodel2_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel2_active) begin - soc_ddrphy_bankmodel2_write_port_adr = soc_ddrphy_bankmodel2_wraddr; + soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr; end end always @(*) begin - soc_ddrphy_bankmodel2_write_port_we = 16'd0; + soc_ddrphy_bankmodel2_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel2_active) begin if (4'd8) begin - soc_ddrphy_bankmodel2_write_port_we = ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask)); + soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask)); end else begin - soc_ddrphy_bankmodel2_write_port_we = soc_ddrphy_bankmodel2_write; + soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write; end end end always @(*) begin - soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel2_active) begin - soc_ddrphy_bankmodel2_write_port_dat_w = soc_ddrphy_bankmodel2_write_data; + soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data; end end always @(*) begin - soc_ddrphy_bankmodel2_read_port_adr = 21'd0; + soc_ddrphy_bankmodel2_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel2_active) begin if (soc_ddrphy_bankmodel2_read) begin - soc_ddrphy_bankmodel2_read_port_adr = soc_ddrphy_bankmodel2_rdaddr; + soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr; end end end always @(*) begin - soc_ddrphy_bankmodel2_read_data = 128'd0; + soc_ddrphy_bankmodel2_read_data <= 128'd0; if (soc_ddrphy_bankmodel2_active) begin if (soc_ddrphy_bankmodel2_read) begin - soc_ddrphy_bankmodel2_read_data = soc_ddrphy_bankmodel2_read_port_dat_r; + soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r; end end end assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; always @(*) begin - soc_ddrphy_bankmodel3_write_port_we = 16'd0; + soc_ddrphy_bankmodel3_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr; + end +end +always @(*) begin + soc_ddrphy_bankmodel3_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel3_active) begin if (4'd8) begin - soc_ddrphy_bankmodel3_write_port_we = ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask)); + soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask)); end else begin - soc_ddrphy_bankmodel3_write_port_we = soc_ddrphy_bankmodel3_write; + soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write; end end end always @(*) begin - soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel3_active) begin - soc_ddrphy_bankmodel3_write_port_dat_w = soc_ddrphy_bankmodel3_write_data; + soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data; end end always @(*) begin - soc_ddrphy_bankmodel3_read_port_adr = 21'd0; + soc_ddrphy_bankmodel3_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel3_active) begin if (soc_ddrphy_bankmodel3_read) begin - soc_ddrphy_bankmodel3_read_port_adr = soc_ddrphy_bankmodel3_rdaddr; + soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr; end end end always @(*) begin - soc_ddrphy_bankmodel3_read_data = 128'd0; + soc_ddrphy_bankmodel3_read_data <= 128'd0; if (soc_ddrphy_bankmodel3_active) begin if (soc_ddrphy_bankmodel3_read) begin - soc_ddrphy_bankmodel3_read_data = soc_ddrphy_bankmodel3_read_port_dat_r; + soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r; end end end -always @(*) begin - soc_ddrphy_bankmodel3_write_port_adr = 21'd0; - if (soc_ddrphy_bankmodel3_active) begin - soc_ddrphy_bankmodel3_write_port_adr = soc_ddrphy_bankmodel3_wraddr; - end -end assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; always @(*) begin - soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel4_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel4_active) begin - soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); + end else begin + soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write; + end end end always @(*) begin - soc_ddrphy_bankmodel4_read_port_adr = 21'd0; + soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel4_active) begin - if (soc_ddrphy_bankmodel4_read) begin - soc_ddrphy_bankmodel4_read_port_adr = soc_ddrphy_bankmodel4_rdaddr; - end + soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data; end end always @(*) begin - soc_ddrphy_bankmodel4_read_data = 128'd0; + soc_ddrphy_bankmodel4_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel4_active) begin if (soc_ddrphy_bankmodel4_read) begin - soc_ddrphy_bankmodel4_read_data = soc_ddrphy_bankmodel4_read_port_dat_r; + soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr; end end end always @(*) begin - soc_ddrphy_bankmodel4_write_port_adr = 21'd0; + soc_ddrphy_bankmodel4_read_data <= 128'd0; if (soc_ddrphy_bankmodel4_active) begin - soc_ddrphy_bankmodel4_write_port_adr = soc_ddrphy_bankmodel4_wraddr; + if (soc_ddrphy_bankmodel4_read) begin + soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r; + end end end always @(*) begin - soc_ddrphy_bankmodel4_write_port_we = 16'd0; + soc_ddrphy_bankmodel4_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel4_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel4_write_port_we = ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); - end else begin - soc_ddrphy_bankmodel4_write_port_we = soc_ddrphy_bankmodel4_write; - end + soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr; end end assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin - soc_ddrphy_bankmodel5_read_data = 128'd0; + soc_ddrphy_bankmodel5_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel5_active) begin if (soc_ddrphy_bankmodel5_read) begin - soc_ddrphy_bankmodel5_read_data = soc_ddrphy_bankmodel5_read_port_dat_r; + soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr; end end end always @(*) begin - soc_ddrphy_bankmodel5_write_port_adr = 21'd0; + soc_ddrphy_bankmodel5_read_data <= 128'd0; if (soc_ddrphy_bankmodel5_active) begin - soc_ddrphy_bankmodel5_write_port_adr = soc_ddrphy_bankmodel5_wraddr; + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r; + end end end always @(*) begin - soc_ddrphy_bankmodel5_write_port_we = 16'd0; + soc_ddrphy_bankmodel5_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel5_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel5_write_port_we = ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask)); - end else begin - soc_ddrphy_bankmodel5_write_port_we = soc_ddrphy_bankmodel5_write; - end + soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr; end end always @(*) begin - soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel5_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel5_active) begin - soc_ddrphy_bankmodel5_write_port_dat_w = soc_ddrphy_bankmodel5_write_data; + if (4'd8) begin + soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask)); + end else begin + soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write; + end end end always @(*) begin - soc_ddrphy_bankmodel5_read_port_adr = 21'd0; + soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel5_active) begin - if (soc_ddrphy_bankmodel5_read) begin - soc_ddrphy_bankmodel5_read_port_adr = soc_ddrphy_bankmodel5_rdaddr; - end + soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data; end end assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; always @(*) begin - soc_ddrphy_bankmodel6_read_data = 128'd0; + soc_ddrphy_bankmodel6_read_data <= 128'd0; if (soc_ddrphy_bankmodel6_active) begin if (soc_ddrphy_bankmodel6_read) begin - soc_ddrphy_bankmodel6_read_data = soc_ddrphy_bankmodel6_read_port_dat_r; + soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r; end end end always @(*) begin - soc_ddrphy_bankmodel6_write_port_adr = 21'd0; + soc_ddrphy_bankmodel6_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel6_active) begin - soc_ddrphy_bankmodel6_write_port_adr = soc_ddrphy_bankmodel6_wraddr; + soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr; end end always @(*) begin - soc_ddrphy_bankmodel6_write_port_we = 16'd0; + soc_ddrphy_bankmodel6_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel6_active) begin if (4'd8) begin - soc_ddrphy_bankmodel6_write_port_we = ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask)); + soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask)); end else begin - soc_ddrphy_bankmodel6_write_port_we = soc_ddrphy_bankmodel6_write; + soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write; end end end always @(*) begin - soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel6_active) begin - soc_ddrphy_bankmodel6_write_port_dat_w = soc_ddrphy_bankmodel6_write_data; + soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data; end end always @(*) begin - soc_ddrphy_bankmodel6_read_port_adr = 21'd0; + soc_ddrphy_bankmodel6_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel6_active) begin if (soc_ddrphy_bankmodel6_read) begin - soc_ddrphy_bankmodel6_read_port_adr = soc_ddrphy_bankmodel6_rdaddr; + soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr; end end end assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; always @(*) begin - soc_ddrphy_bankmodel7_read_data = 128'd0; + soc_ddrphy_bankmodel7_read_data <= 128'd0; if (soc_ddrphy_bankmodel7_active) begin if (soc_ddrphy_bankmodel7_read) begin - soc_ddrphy_bankmodel7_read_data = soc_ddrphy_bankmodel7_read_port_dat_r; + soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r; end end end always @(*) begin - soc_ddrphy_bankmodel7_write_port_adr = 21'd0; + soc_ddrphy_bankmodel7_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel7_active) begin - soc_ddrphy_bankmodel7_write_port_adr = soc_ddrphy_bankmodel7_wraddr; + soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr; end end always @(*) begin - soc_ddrphy_bankmodel7_write_port_we = 16'd0; + soc_ddrphy_bankmodel7_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel7_active) begin if (4'd8) begin - soc_ddrphy_bankmodel7_write_port_we = ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask)); + soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask)); end else begin - soc_ddrphy_bankmodel7_write_port_we = soc_ddrphy_bankmodel7_write; + soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write; end end end always @(*) begin - soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; + soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0; if (soc_ddrphy_bankmodel7_active) begin - soc_ddrphy_bankmodel7_write_port_dat_w = soc_ddrphy_bankmodel7_write_data; + soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data; end end always @(*) begin - soc_ddrphy_bankmodel7_read_port_adr = 21'd0; + soc_ddrphy_bankmodel7_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel7_active) begin if (soc_ddrphy_bankmodel7_read) begin - soc_ddrphy_bankmodel7_read_port_adr = soc_ddrphy_bankmodel7_rdaddr; + soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr; end end end @@ -3728,563 +3643,563 @@ assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; always @(*) begin - soc_litedramcore_master_p0_we_n = 1'd1; + soc_litedramcore_master_p0_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_we_n = soc_litedramcore_slave_p0_we_n; + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; end else begin - soc_litedramcore_master_p0_we_n = soc_litedramcore_inti_p0_we_n; + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n; end end always @(*) begin - soc_litedramcore_slave_p0_rddata_valid = 1'd0; + soc_litedramcore_master_p0_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; end else begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n; end end always @(*) begin - soc_litedramcore_master_p0_cke = 1'd0; + soc_litedramcore_slave_p0_rddata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cke = soc_litedramcore_slave_p0_cke; + soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; end else begin - soc_litedramcore_master_p0_cke = soc_litedramcore_inti_p0_cke; end end always @(*) begin - soc_litedramcore_master_p0_odt = 1'd0; + soc_litedramcore_master_p0_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_odt = soc_litedramcore_slave_p0_odt; + soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; end else begin - soc_litedramcore_master_p0_odt = soc_litedramcore_inti_p0_odt; + soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n; end end always @(*) begin - soc_litedramcore_master_p0_reset_n = 1'd0; + soc_litedramcore_slave_p0_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_reset_n = soc_litedramcore_slave_p0_reset_n; + soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; end else begin - soc_litedramcore_master_p0_reset_n = soc_litedramcore_inti_p0_reset_n; end end always @(*) begin - soc_litedramcore_master_p0_act_n = 1'd1; + soc_litedramcore_master_p0_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_act_n = soc_litedramcore_slave_p0_act_n; + soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; end else begin - soc_litedramcore_master_p0_act_n = soc_litedramcore_inti_p0_act_n; + soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke; end end always @(*) begin - soc_litedramcore_master_p0_wrdata = 32'd0; + soc_litedramcore_master_p0_odt <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata = soc_litedramcore_slave_p0_wrdata; + soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; end else begin - soc_litedramcore_master_p0_wrdata = soc_litedramcore_inti_p0_wrdata; + soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt; end end always @(*) begin - soc_litedramcore_inti_p1_rddata = 32'd0; + soc_litedramcore_master_p0_reset_n <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; end else begin - soc_litedramcore_inti_p1_rddata = soc_litedramcore_master_p1_rddata; + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n; end end always @(*) begin - soc_litedramcore_master_p0_wrdata_en = 1'd0; + soc_litedramcore_master_p0_act_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_slave_p0_wrdata_en; + soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; end else begin - soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_inti_p0_wrdata_en; + soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n; end end always @(*) begin - soc_litedramcore_inti_p1_rddata_valid = 1'd0; + soc_litedramcore_master_p0_wrdata <= 32'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; end else begin - soc_litedramcore_inti_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata; end end always @(*) begin - soc_litedramcore_master_p0_wrdata_mask = 4'd0; + soc_litedramcore_inti_p1_rddata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_slave_p0_wrdata_mask; end else begin - soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_inti_p0_wrdata_mask; + soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata; end end always @(*) begin - soc_litedramcore_master_p0_rddata_en = 1'd0; + soc_litedramcore_master_p0_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_rddata_en = soc_litedramcore_slave_p0_rddata_en; + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; end else begin - soc_litedramcore_master_p0_rddata_en = soc_litedramcore_inti_p0_rddata_en; + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en; end end always @(*) begin - soc_litedramcore_master_p1_address = 14'd0; + soc_litedramcore_inti_p1_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_address = soc_litedramcore_slave_p1_address; end else begin - soc_litedramcore_master_p1_address = soc_litedramcore_inti_p1_address; + soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; end end always @(*) begin - soc_litedramcore_master_p1_bank = 3'd0; + soc_litedramcore_master_p0_wrdata_mask <= 4'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_bank = soc_litedramcore_slave_p1_bank; + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; end else begin - soc_litedramcore_master_p1_bank = soc_litedramcore_inti_p1_bank; + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask; end end always @(*) begin - soc_litedramcore_master_p1_cas_n = 1'd1; + soc_litedramcore_master_p0_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cas_n = soc_litedramcore_slave_p1_cas_n; + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; end else begin - soc_litedramcore_master_p1_cas_n = soc_litedramcore_inti_p1_cas_n; + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en; end end always @(*) begin - soc_litedramcore_master_p1_cs_n = 1'd1; + soc_litedramcore_master_p1_address <= 14'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cs_n = soc_litedramcore_slave_p1_cs_n; + soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; end else begin - soc_litedramcore_master_p1_cs_n = soc_litedramcore_inti_p1_cs_n; + soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address; end end always @(*) begin - soc_litedramcore_master_p1_ras_n = 1'd1; + soc_litedramcore_master_p1_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_ras_n = soc_litedramcore_slave_p1_ras_n; + soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; end else begin - soc_litedramcore_master_p1_ras_n = soc_litedramcore_inti_p1_ras_n; + soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank; end end always @(*) begin - soc_litedramcore_slave_p1_rddata = 32'd0; + soc_litedramcore_master_p1_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata = soc_litedramcore_master_p1_rddata; + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; end else begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n; end end always @(*) begin - soc_litedramcore_master_p1_we_n = 1'd1; + soc_litedramcore_master_p1_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_we_n = soc_litedramcore_slave_p1_we_n; + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; end else begin - soc_litedramcore_master_p1_we_n = soc_litedramcore_inti_p1_we_n; + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n; end end always @(*) begin - soc_litedramcore_slave_p1_rddata_valid = 1'd0; + soc_litedramcore_master_p1_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid; + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; end else begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n; end end always @(*) begin - soc_litedramcore_master_p1_cke = 1'd0; + soc_litedramcore_slave_p1_rddata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_cke = soc_litedramcore_slave_p1_cke; + soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; end else begin - soc_litedramcore_master_p1_cke = soc_litedramcore_inti_p1_cke; end end always @(*) begin - soc_litedramcore_master_p1_odt = 1'd0; + soc_litedramcore_master_p1_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_odt = soc_litedramcore_slave_p1_odt; + soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; end else begin - soc_litedramcore_master_p1_odt = soc_litedramcore_inti_p1_odt; + soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n; end end always @(*) begin - soc_litedramcore_master_p1_reset_n = 1'd0; + soc_litedramcore_slave_p1_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_reset_n = soc_litedramcore_slave_p1_reset_n; + soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; end else begin - soc_litedramcore_master_p1_reset_n = soc_litedramcore_inti_p1_reset_n; end end always @(*) begin - soc_litedramcore_master_p1_act_n = 1'd1; + soc_litedramcore_master_p1_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_act_n = soc_litedramcore_slave_p1_act_n; + soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; end else begin - soc_litedramcore_master_p1_act_n = soc_litedramcore_inti_p1_act_n; + soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke; end end always @(*) begin - soc_litedramcore_master_p1_wrdata = 32'd0; + soc_litedramcore_master_p1_odt <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata = soc_litedramcore_slave_p1_wrdata; + soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; end else begin - soc_litedramcore_master_p1_wrdata = soc_litedramcore_inti_p1_wrdata; + soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt; end end always @(*) begin - soc_litedramcore_inti_p2_rddata = 32'd0; + soc_litedramcore_master_p1_reset_n <= 1'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; end else begin - soc_litedramcore_inti_p2_rddata = soc_litedramcore_master_p2_rddata; + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n; end end always @(*) begin - soc_litedramcore_master_p1_wrdata_en = 1'd0; + soc_litedramcore_master_p1_act_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_slave_p1_wrdata_en; + soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; end else begin - soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_inti_p1_wrdata_en; + soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n; end end always @(*) begin - soc_litedramcore_inti_p2_rddata_valid = 1'd0; + soc_litedramcore_master_p1_wrdata <= 32'd0; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; end else begin - soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata; end end always @(*) begin - soc_litedramcore_master_p1_wrdata_mask = 4'd0; + soc_litedramcore_inti_p2_rddata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_inti_p1_wrdata_mask; + soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata; end end always @(*) begin - soc_litedramcore_master_p1_rddata_en = 1'd0; + soc_litedramcore_master_p1_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p1_rddata_en = soc_litedramcore_slave_p1_rddata_en; + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; end else begin - soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en; + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en; end end always @(*) begin - soc_litedramcore_master_p0_ras_n = 1'd1; + soc_litedramcore_inti_p2_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n; end else begin - soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n; + soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; end end always @(*) begin - soc_litedramcore_master_p2_address = 14'd0; + soc_litedramcore_master_p1_wrdata_mask <= 4'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_address = soc_litedramcore_slave_p2_address; + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; end else begin - soc_litedramcore_master_p2_address = soc_litedramcore_inti_p2_address; + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask; end end always @(*) begin - soc_litedramcore_master_p2_bank = 3'd0; + soc_litedramcore_master_p1_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_bank = soc_litedramcore_slave_p2_bank; + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; end else begin - soc_litedramcore_master_p2_bank = soc_litedramcore_inti_p2_bank; + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en; end end always @(*) begin - soc_litedramcore_master_p2_cas_n = 1'd1; + soc_litedramcore_master_p2_address <= 14'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cas_n = soc_litedramcore_slave_p2_cas_n; + soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; end else begin - soc_litedramcore_master_p2_cas_n = soc_litedramcore_inti_p2_cas_n; + soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address; end end always @(*) begin - soc_litedramcore_master_p2_cs_n = 1'd1; + soc_litedramcore_master_p2_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cs_n = soc_litedramcore_slave_p2_cs_n; + soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; end else begin - soc_litedramcore_master_p2_cs_n = soc_litedramcore_inti_p2_cs_n; + soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank; end end always @(*) begin - soc_litedramcore_master_p2_ras_n = 1'd1; + soc_litedramcore_master_p2_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_ras_n = soc_litedramcore_slave_p2_ras_n; + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; end else begin - soc_litedramcore_master_p2_ras_n = soc_litedramcore_inti_p2_ras_n; + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n; end end always @(*) begin - soc_litedramcore_slave_p2_rddata = 32'd0; + soc_litedramcore_master_p2_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata = soc_litedramcore_master_p2_rddata; + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; end else begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n; end end always @(*) begin - soc_litedramcore_master_p2_we_n = 1'd1; + soc_litedramcore_master_p2_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_we_n = soc_litedramcore_slave_p2_we_n; + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; end else begin - soc_litedramcore_master_p2_we_n = soc_litedramcore_inti_p2_we_n; + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n; end end always @(*) begin - soc_litedramcore_slave_p2_rddata_valid = 1'd0; + soc_litedramcore_slave_p2_rddata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid; + soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; end else begin end end always @(*) begin - soc_litedramcore_master_p2_cke = 1'd0; + soc_litedramcore_master_p2_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_cke = soc_litedramcore_slave_p2_cke; + soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; end else begin - soc_litedramcore_master_p2_cke = soc_litedramcore_inti_p2_cke; + soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n; end end always @(*) begin - soc_litedramcore_master_p2_odt = 1'd0; + soc_litedramcore_slave_p2_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_odt = soc_litedramcore_slave_p2_odt; + soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; end else begin - soc_litedramcore_master_p2_odt = soc_litedramcore_inti_p2_odt; end end always @(*) begin - soc_litedramcore_master_p2_reset_n = 1'd0; + soc_litedramcore_master_p2_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_reset_n = soc_litedramcore_slave_p2_reset_n; + soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; end else begin - soc_litedramcore_master_p2_reset_n = soc_litedramcore_inti_p2_reset_n; + soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke; end end always @(*) begin - soc_litedramcore_master_p2_act_n = 1'd1; + soc_litedramcore_master_p2_odt <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_act_n = soc_litedramcore_slave_p2_act_n; + soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; end else begin - soc_litedramcore_master_p2_act_n = soc_litedramcore_inti_p2_act_n; + soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt; end end always @(*) begin - soc_litedramcore_master_p2_wrdata = 32'd0; + soc_litedramcore_master_p2_reset_n <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata = soc_litedramcore_slave_p2_wrdata; + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; end else begin - soc_litedramcore_master_p2_wrdata = soc_litedramcore_inti_p2_wrdata; + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n; end end always @(*) begin - soc_litedramcore_inti_p3_rddata = 32'd0; + soc_litedramcore_master_p2_act_n <= 1'd1; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; end else begin - soc_litedramcore_inti_p3_rddata = soc_litedramcore_master_p3_rddata; + soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n; end end always @(*) begin - soc_litedramcore_master_p2_wrdata_en = 1'd0; + soc_litedramcore_master_p2_wrdata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_slave_p2_wrdata_en; + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; end else begin - soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_inti_p2_wrdata_en; + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata; end end always @(*) begin - soc_litedramcore_inti_p3_rddata_valid = 1'd0; + soc_litedramcore_inti_p3_rddata <= 32'd0; if (soc_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; + soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata; end end always @(*) begin - soc_litedramcore_master_p2_wrdata_mask = 4'd0; + soc_litedramcore_master_p2_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_slave_p2_wrdata_mask; + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; end else begin - soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_inti_p2_wrdata_mask; + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en; end end always @(*) begin - soc_litedramcore_master_p2_rddata_en = 1'd0; + soc_litedramcore_inti_p3_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p2_rddata_en = soc_litedramcore_slave_p2_rddata_en; end else begin - soc_litedramcore_master_p2_rddata_en = soc_litedramcore_inti_p2_rddata_en; + soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; end end always @(*) begin - soc_litedramcore_master_p3_address = 14'd0; + soc_litedramcore_master_p2_wrdata_mask <= 4'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_address = soc_litedramcore_slave_p3_address; + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; end else begin - soc_litedramcore_master_p3_address = soc_litedramcore_inti_p3_address; + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask; end end always @(*) begin - soc_litedramcore_master_p3_bank = 3'd0; + soc_litedramcore_master_p2_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_bank = soc_litedramcore_slave_p3_bank; + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; end else begin - soc_litedramcore_master_p3_bank = soc_litedramcore_inti_p3_bank; + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en; end end always @(*) begin - soc_litedramcore_master_p3_cas_n = 1'd1; + soc_litedramcore_master_p3_address <= 14'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cas_n = soc_litedramcore_slave_p3_cas_n; + soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; end else begin - soc_litedramcore_master_p3_cas_n = soc_litedramcore_inti_p3_cas_n; + soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address; end end always @(*) begin - soc_litedramcore_master_p3_cs_n = 1'd1; + soc_litedramcore_master_p3_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cs_n = soc_litedramcore_slave_p3_cs_n; + soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; end else begin - soc_litedramcore_master_p3_cs_n = soc_litedramcore_inti_p3_cs_n; + soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank; end end always @(*) begin - soc_litedramcore_master_p3_ras_n = 1'd1; + soc_litedramcore_master_p3_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_ras_n = soc_litedramcore_slave_p3_ras_n; + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; end else begin - soc_litedramcore_master_p3_ras_n = soc_litedramcore_inti_p3_ras_n; + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n; end end always @(*) begin - soc_litedramcore_slave_p3_rddata = 32'd0; + soc_litedramcore_master_p3_cs_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata = soc_litedramcore_master_p3_rddata; + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; end else begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n; end end always @(*) begin - soc_litedramcore_master_p3_we_n = 1'd1; + soc_litedramcore_master_p3_ras_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_we_n = soc_litedramcore_slave_p3_we_n; + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; end else begin - soc_litedramcore_master_p3_we_n = soc_litedramcore_inti_p3_we_n; + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n; end end always @(*) begin - soc_litedramcore_slave_p3_rddata_valid = 1'd0; + soc_litedramcore_slave_p3_rddata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid; + soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; end else begin end end always @(*) begin - soc_litedramcore_master_p3_cke = 1'd0; + soc_litedramcore_master_p3_we_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_cke = soc_litedramcore_slave_p3_cke; + soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; end else begin - soc_litedramcore_master_p3_cke = soc_litedramcore_inti_p3_cke; + soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n; end end always @(*) begin - soc_litedramcore_master_p3_odt = 1'd0; + soc_litedramcore_slave_p3_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_odt = soc_litedramcore_slave_p3_odt; + soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; end else begin - soc_litedramcore_master_p3_odt = soc_litedramcore_inti_p3_odt; end end always @(*) begin - soc_litedramcore_master_p3_reset_n = 1'd0; + soc_litedramcore_master_p3_cke <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_reset_n = soc_litedramcore_slave_p3_reset_n; + soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; end else begin - soc_litedramcore_master_p3_reset_n = soc_litedramcore_inti_p3_reset_n; + soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke; end end always @(*) begin - soc_litedramcore_master_p3_act_n = 1'd1; + soc_litedramcore_master_p3_odt <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_act_n = soc_litedramcore_slave_p3_act_n; + soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; end else begin - soc_litedramcore_master_p3_act_n = soc_litedramcore_inti_p3_act_n; + soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt; end end always @(*) begin - soc_litedramcore_master_p3_wrdata = 32'd0; + soc_litedramcore_master_p3_reset_n <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata = soc_litedramcore_slave_p3_wrdata; + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; end else begin - soc_litedramcore_master_p3_wrdata = soc_litedramcore_inti_p3_wrdata; + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n; end end always @(*) begin - soc_litedramcore_inti_p0_rddata = 32'd0; + soc_litedramcore_master_p3_act_n <= 1'd1; if (soc_litedramcore_sel) begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; end else begin - soc_litedramcore_inti_p0_rddata = soc_litedramcore_master_p0_rddata; + soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n; end end always @(*) begin - soc_litedramcore_master_p3_wrdata_en = 1'd0; + soc_litedramcore_master_p3_wrdata <= 32'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_slave_p3_wrdata_en; + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; end else begin - soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_inti_p3_wrdata_en; + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata; end end always @(*) begin - soc_litedramcore_inti_p0_rddata_valid = 1'd0; + soc_litedramcore_inti_p0_rddata <= 32'd0; if (soc_litedramcore_sel) begin end else begin - soc_litedramcore_inti_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid; + soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata; end end always @(*) begin - soc_litedramcore_master_p3_wrdata_mask = 4'd0; + soc_litedramcore_master_p3_wrdata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_slave_p3_wrdata_mask; + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; end else begin - soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_inti_p3_wrdata_mask; + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en; end end always @(*) begin - soc_litedramcore_master_p3_rddata_en = 1'd0; + soc_litedramcore_inti_p0_rddata_valid <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p3_rddata_en = soc_litedramcore_slave_p3_rddata_en; end else begin - soc_litedramcore_master_p3_rddata_en = soc_litedramcore_inti_p3_rddata_en; + soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; end end always @(*) begin - soc_litedramcore_master_p0_address = 14'd0; + soc_litedramcore_master_p3_wrdata_mask <= 4'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_address = soc_litedramcore_slave_p0_address; + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; end else begin - soc_litedramcore_master_p0_address = soc_litedramcore_inti_p0_address; + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask; end end always @(*) begin - soc_litedramcore_master_p0_bank = 3'd0; + soc_litedramcore_master_p3_rddata_en <= 1'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_bank = soc_litedramcore_slave_p0_bank; + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; end else begin - soc_litedramcore_master_p0_bank = soc_litedramcore_inti_p0_bank; + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en; end end always @(*) begin - soc_litedramcore_master_p0_cas_n = 1'd1; + soc_litedramcore_master_p0_address <= 14'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cas_n = soc_litedramcore_slave_p0_cas_n; + soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; end else begin - soc_litedramcore_master_p0_cas_n = soc_litedramcore_inti_p0_cas_n; + soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address; end end always @(*) begin - soc_litedramcore_master_p0_cs_n = 1'd1; + soc_litedramcore_master_p0_bank <= 3'd0; if (soc_litedramcore_sel) begin - soc_litedramcore_master_p0_cs_n = soc_litedramcore_slave_p0_cs_n; + soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; end else begin - soc_litedramcore_master_p0_cs_n = soc_litedramcore_inti_p0_cs_n; + soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank; end end always @(*) begin - soc_litedramcore_slave_p0_rddata = 32'd0; + soc_litedramcore_master_p0_cas_n <= 1'd1; if (soc_litedramcore_sel) begin - soc_litedramcore_slave_p0_rddata = soc_litedramcore_master_p0_rddata; + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; end else begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n; end end assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke; @@ -4300,35 +4215,35 @@ assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n; always @(*) begin - soc_litedramcore_inti_p0_we_n = 1'd1; + soc_litedramcore_inti_p0_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_we_n = (~soc_litedramcore_phaseinjector0_command_storage[1]); + soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; end else begin - soc_litedramcore_inti_p0_we_n = 1'd1; + soc_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end end always @(*) begin - soc_litedramcore_inti_p0_cas_n = 1'd1; + soc_litedramcore_inti_p0_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cas_n = (~soc_litedramcore_phaseinjector0_command_storage[2]); + soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]); end else begin - soc_litedramcore_inti_p0_cas_n = 1'd1; + soc_litedramcore_inti_p0_ras_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p0_cs_n = 1'd1; + soc_litedramcore_inti_p0_we_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_cs_n = {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}}; + soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]); end else begin - soc_litedramcore_inti_p0_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p0_we_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p0_ras_n = 1'd1; + soc_litedramcore_inti_p0_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_inti_p0_ras_n = (~soc_litedramcore_phaseinjector0_command_storage[3]); + soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]); end else begin - soc_litedramcore_inti_p0_ras_n = 1'd1; + soc_litedramcore_inti_p0_cas_n <= 1'd1; end end assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage; @@ -4338,35 +4253,35 @@ assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_com assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0; always @(*) begin - soc_litedramcore_inti_p1_we_n = 1'd1; + soc_litedramcore_inti_p1_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_we_n = (~soc_litedramcore_phaseinjector1_command_storage[1]); + soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; end else begin - soc_litedramcore_inti_p1_we_n = 1'd1; + soc_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end end always @(*) begin - soc_litedramcore_inti_p1_cas_n = 1'd1; + soc_litedramcore_inti_p1_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cas_n = (~soc_litedramcore_phaseinjector1_command_storage[2]); + soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]); end else begin - soc_litedramcore_inti_p1_cas_n = 1'd1; + soc_litedramcore_inti_p1_ras_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p1_cs_n = 1'd1; + soc_litedramcore_inti_p1_we_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_cs_n = {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}}; + soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]); end else begin - soc_litedramcore_inti_p1_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p1_we_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p1_ras_n = 1'd1; + soc_litedramcore_inti_p1_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_inti_p1_ras_n = (~soc_litedramcore_phaseinjector1_command_storage[3]); + soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]); end else begin - soc_litedramcore_inti_p1_ras_n = 1'd1; + soc_litedramcore_inti_p1_cas_n <= 1'd1; end end assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage; @@ -4376,35 +4291,35 @@ assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_com assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0; always @(*) begin - soc_litedramcore_inti_p2_we_n = 1'd1; + soc_litedramcore_inti_p2_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_we_n = (~soc_litedramcore_phaseinjector2_command_storage[1]); + soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; end else begin - soc_litedramcore_inti_p2_we_n = 1'd1; + soc_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end end always @(*) begin - soc_litedramcore_inti_p2_cas_n = 1'd1; + soc_litedramcore_inti_p2_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cas_n = (~soc_litedramcore_phaseinjector2_command_storage[2]); + soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]); end else begin - soc_litedramcore_inti_p2_cas_n = 1'd1; + soc_litedramcore_inti_p2_ras_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p2_cs_n = 1'd1; + soc_litedramcore_inti_p2_we_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_cs_n = {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}}; + soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]); end else begin - soc_litedramcore_inti_p2_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p2_we_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p2_ras_n = 1'd1; + soc_litedramcore_inti_p2_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_inti_p2_ras_n = (~soc_litedramcore_phaseinjector2_command_storage[3]); + soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]); end else begin - soc_litedramcore_inti_p2_ras_n = 1'd1; + soc_litedramcore_inti_p2_cas_n <= 1'd1; end end assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage; @@ -4414,35 +4329,35 @@ assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_com assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0; always @(*) begin - soc_litedramcore_inti_p3_we_n = 1'd1; + soc_litedramcore_inti_p3_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_we_n = (~soc_litedramcore_phaseinjector3_command_storage[1]); + soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; end else begin - soc_litedramcore_inti_p3_we_n = 1'd1; + soc_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end end always @(*) begin - soc_litedramcore_inti_p3_cas_n = 1'd1; + soc_litedramcore_inti_p3_ras_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cas_n = (~soc_litedramcore_phaseinjector3_command_storage[2]); + soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]); end else begin - soc_litedramcore_inti_p3_cas_n = 1'd1; + soc_litedramcore_inti_p3_ras_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p3_cs_n = 1'd1; + soc_litedramcore_inti_p3_we_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_cs_n = {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}}; + soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]); end else begin - soc_litedramcore_inti_p3_cs_n = {1{1'd1}}; + soc_litedramcore_inti_p3_we_n <= 1'd1; end end always @(*) begin - soc_litedramcore_inti_p3_ras_n = 1'd1; + soc_litedramcore_inti_p3_cas_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_inti_p3_ras_n = (~soc_litedramcore_phaseinjector3_command_storage[3]); + soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]); end else begin - soc_litedramcore_inti_p3_ras_n = 1'd1; + soc_litedramcore_inti_p3_cas_n <= 1'd1; end end assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage; @@ -4521,43 +4436,43 @@ assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 = assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; always @(*) begin - refresher_next_state = 2'd0; - refresher_next_state = refresher_state; + refresher_next_state <= 2'd0; + refresher_next_state <= refresher_state; case (refresher_state) 1'd1: begin if (soc_litedramcore_cmd_ready) begin - refresher_next_state = 2'd2; + refresher_next_state <= 2'd2; end end 2'd2: begin if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin - refresher_next_state = 2'd3; + refresher_next_state <= 2'd3; end else begin - refresher_next_state = 1'd0; + refresher_next_state <= 1'd0; end end end 2'd3: begin if (soc_litedramcore_zqcs_executer_done) begin - refresher_next_state = 1'd0; + refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin if (soc_litedramcore_wants_refresh) begin - refresher_next_state = 1'd1; + refresher_next_state <= 1'd1; end end end endcase end always @(*) begin - soc_litedramcore_sequencer_start0 = 1'd0; + soc_litedramcore_sequencer_start0 <= 1'd0; case (refresher_state) 1'd1: begin if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 = 1'd1; + soc_litedramcore_sequencer_start0 <= 1'd1; end end 2'd2: begin @@ -4569,24 +4484,24 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_cmd_valid = 1'd0; + soc_litedramcore_cmd_valid <= 1'd0; case (refresher_state) 1'd1: begin - soc_litedramcore_cmd_valid = 1'd1; + soc_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - soc_litedramcore_cmd_valid = 1'd1; + soc_litedramcore_cmd_valid <= 1'd1; if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin end else begin - soc_litedramcore_cmd_valid = 1'd0; + soc_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin - soc_litedramcore_cmd_valid = 1'd1; + soc_litedramcore_cmd_valid <= 1'd1; if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid = 1'd0; + soc_litedramcore_cmd_valid <= 1'd0; end end default: begin @@ -4594,14 +4509,14 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_zqcs_executer_start = 1'd0; + soc_litedramcore_zqcs_executer_start <= 1'd0; case (refresher_state) 1'd1: begin end 2'd2: begin if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start = 1'd1; + soc_litedramcore_zqcs_executer_start <= 1'd1; end else begin end end @@ -4613,7 +4528,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_cmd_last = 1'd0; + soc_litedramcore_cmd_last <= 1'd0; case (refresher_state) 1'd1: begin end @@ -4621,13 +4536,13 @@ always @(*) begin if (soc_litedramcore_sequencer_done0) begin if (soc_litedramcore_wants_zqcs) begin end else begin - soc_litedramcore_cmd_last = 1'd1; + soc_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last = 1'd1; + soc_litedramcore_cmd_last <= 1'd1; end end default: begin @@ -4649,21 +4564,21 @@ assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_c assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine0_cmd_payload_a = soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine0_cmd_payload_a = ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); always @(*) begin - soc_litedramcore_bankmachine0_auto_precharge = 1'd0; + soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine0_auto_precharge = (soc_litedramcore_bankmachine0_row_close == 1'd0); + soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); end end end @@ -4685,11 +4600,11 @@ assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; @@ -4701,60 +4616,60 @@ assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = ( assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); always @(*) begin - bankmachine0_next_state = 4'd0; - bankmachine0_next_state = bankmachine0_state; + bankmachine0_next_state <= 4'd0; + bankmachine0_next_state <= bankmachine0_state; case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin if (soc_litedramcore_bankmachine0_cmd_ready) begin - bankmachine0_next_state = 3'd5; + bankmachine0_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - bankmachine0_next_state = 3'd5; + bankmachine0_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine0_trccon_ready) begin if (soc_litedramcore_bankmachine0_cmd_ready) begin - bankmachine0_next_state = 3'd7; + bankmachine0_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - bankmachine0_next_state = 1'd0; + bankmachine0_next_state <= 1'd0; end end 3'd5: begin - bankmachine0_next_state = 3'd6; + bankmachine0_next_state <= 3'd6; end 3'd6: begin - bankmachine0_next_state = 2'd3; + bankmachine0_next_state <= 2'd3; end 3'd7: begin - bankmachine0_next_state = 4'd8; + bankmachine0_next_state <= 4'd8; end 4'd8: begin - bankmachine0_next_state = 1'd0; + bankmachine0_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine0_refresh_req) begin - bankmachine0_next_state = 3'd4; + bankmachine0_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - bankmachine0_next_state = 2'd2; + bankmachine0_next_state <= 2'd2; end end else begin - bankmachine0_next_state = 1'd1; + bankmachine0_next_state <= 1'd1; end end else begin - bankmachine0_next_state = 2'd3; + bankmachine0_next_state <= 2'd3; end end end @@ -4762,12 +4677,9 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1; - end end 2'd2: begin end @@ -4789,10 +4701,7 @@ always @(*) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1; - end else begin - end + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -4803,15 +4712,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -4829,22 +4741,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (bankmachine0_state) 1'd1: begin if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -4855,17 +4763,35 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -4878,34 +4804,26 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -4916,26 +4834,11 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4960,8 +4863,8 @@ always @(*) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready = soc_litedramcore_bankmachine0_cmd_ready; end else begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -4973,7 +4876,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4998,8 +4901,8 @@ always @(*) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine0_req_rdata_valid = soc_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5011,7 +4914,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -5020,9 +4923,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -5033,23 +4933,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid = 1'd0; + soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -5067,7 +4976,10 @@ always @(*) begin if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine0_row_opened) begin if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; + end end else begin end end else begin @@ -5078,18 +4990,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_row_open = 1'd0; + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5104,18 +5016,21 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_row_close = 1'd0; + soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin - soc_litedramcore_bankmachine0_row_close = 1'd1; + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine0_row_close = 1'd1; end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine0_row_close = 1'd1; end 3'd5: begin end @@ -5126,17 +5041,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine0_row_open <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -5149,37 +5079,22 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1; - end + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1; - end end 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5208,21 +5123,21 @@ assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_c assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine1_cmd_payload_a = soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine1_cmd_payload_a = ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); always @(*) begin - soc_litedramcore_bankmachine1_auto_precharge = 1'd0; + soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine1_auto_precharge = (soc_litedramcore_bankmachine1_row_close == 1'd0); + soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); end end end @@ -5244,11 +5159,11 @@ assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; @@ -5260,60 +5175,95 @@ assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = ( assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); always @(*) begin - bankmachine1_next_state = 4'd0; - bankmachine1_next_state = bankmachine1_state; + bankmachine1_next_state <= 4'd0; + bankmachine1_next_state <= bankmachine1_state; case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin if (soc_litedramcore_bankmachine1_cmd_ready) begin - bankmachine1_next_state = 3'd5; + bankmachine1_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - bankmachine1_next_state = 3'd5; + bankmachine1_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin if (soc_litedramcore_bankmachine1_cmd_ready) begin - bankmachine1_next_state = 3'd7; + bankmachine1_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - bankmachine1_next_state = 1'd0; + bankmachine1_next_state <= 1'd0; end end 3'd5: begin - bankmachine1_next_state = 3'd6; + bankmachine1_next_state <= 3'd6; end 3'd6: begin - bankmachine1_next_state = 2'd3; + bankmachine1_next_state <= 2'd3; end 3'd7: begin - bankmachine1_next_state = 4'd8; + bankmachine1_next_state <= 4'd8; end 4'd8: begin - bankmachine1_next_state = 1'd0; + bankmachine1_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine1_refresh_req) begin - bankmachine1_next_state = 3'd4; + bankmachine1_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - bankmachine1_next_state = 2'd2; + bankmachine1_next_state <= 2'd2; end end else begin - bankmachine1_next_state = 1'd1; + bankmachine1_next_state <= 1'd1; + end + end else begin + bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin end end else begin - bankmachine1_next_state = 2'd3; end end end @@ -5321,11 +5271,40 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -5349,7 +5328,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -5362,7 +5341,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5370,7 +5349,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -5388,22 +5367,22 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5418,7 +5397,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5444,7 +5423,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_row_hit) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5456,7 +5435,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5481,7 +5460,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -5494,7 +5473,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5519,7 +5498,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready = soc_litedramcore_bankmachine1_cmd_ready; + soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; end else begin end end else begin @@ -5532,7 +5511,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5558,7 +5537,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_row_hit) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine1_req_rdata_valid = soc_litedramcore_bankmachine1_cmd_ready; + soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5570,7 +5549,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5580,7 +5559,7 @@ always @(*) begin end 3'd4: begin if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt = 1'd1; + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -5596,18 +5575,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid = 1'd0; + soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5626,7 +5605,7 @@ always @(*) begin if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine1_row_opened) begin if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid = 1'd1; + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin @@ -5637,7 +5616,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_row_open = 1'd0; + soc_litedramcore_bankmachine1_row_open <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5645,7 +5624,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open = 1'd1; + soc_litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin @@ -5663,18 +5642,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine1_row_close = 1'd0; + soc_litedramcore_bankmachine1_row_close <= 1'd0; case (bankmachine1_state) 1'd1: begin - soc_litedramcore_bankmachine1_row_close = 1'd1; + soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine1_row_close = 1'd1; + soc_litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine1_row_close = 1'd1; + soc_litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end @@ -5688,100 +5667,36 @@ always @(*) begin end endcase end +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; +assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); +assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; - case (bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; - case (bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; -assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); -assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; - if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine2_cmd_payload_a = soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine2_cmd_payload_a = ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); -assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); -assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); -always @(*) begin - soc_litedramcore_bankmachine2_auto_precharge = 1'd0; - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine2_auto_precharge = (soc_litedramcore_bankmachine2_row_close == 1'd0); + soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); +assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); +always @(*) begin + soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); end end end @@ -5803,11 +5718,11 @@ assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; @@ -5819,60 +5734,60 @@ assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = ( assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); always @(*) begin - bankmachine2_next_state = 4'd0; - bankmachine2_next_state = bankmachine2_state; + bankmachine2_next_state <= 4'd0; + bankmachine2_next_state <= bankmachine2_state; case (bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin if (soc_litedramcore_bankmachine2_cmd_ready) begin - bankmachine2_next_state = 3'd5; + bankmachine2_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - bankmachine2_next_state = 3'd5; + bankmachine2_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine2_trccon_ready) begin if (soc_litedramcore_bankmachine2_cmd_ready) begin - bankmachine2_next_state = 3'd7; + bankmachine2_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - bankmachine2_next_state = 1'd0; + bankmachine2_next_state <= 1'd0; end end 3'd5: begin - bankmachine2_next_state = 3'd6; + bankmachine2_next_state <= 3'd6; end 3'd6: begin - bankmachine2_next_state = 2'd3; + bankmachine2_next_state <= 2'd3; end 3'd7: begin - bankmachine2_next_state = 4'd8; + bankmachine2_next_state <= 4'd8; end 4'd8: begin - bankmachine2_next_state = 1'd0; + bankmachine2_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine2_refresh_req) begin - bankmachine2_next_state = 3'd4; + bankmachine2_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - bankmachine2_next_state = 2'd2; + bankmachine2_next_state <= 2'd2; end end else begin - bankmachine2_next_state = 1'd1; + bankmachine2_next_state <= 1'd1; end end else begin - bankmachine2_next_state = 2'd3; + bankmachine2_next_state <= 2'd3; end end end @@ -5880,12 +5795,9 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1; - end end 2'd2: begin end @@ -5907,10 +5819,7 @@ always @(*) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1; - end else begin - end + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5921,15 +5830,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -5947,22 +5859,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (bankmachine2_state) 1'd1: begin if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -5973,17 +5881,35 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -5996,34 +5922,26 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6034,26 +5952,11 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6078,8 +5981,8 @@ always @(*) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready = soc_litedramcore_bankmachine2_cmd_ready; end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6091,7 +5994,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6116,8 +6019,8 @@ always @(*) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine2_req_rdata_valid = soc_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6129,7 +6032,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6138,9 +6041,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -6151,23 +6051,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid = 1'd0; + soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -6185,7 +6094,10 @@ always @(*) begin if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine2_row_opened) begin if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; + end end else begin end end else begin @@ -6196,18 +6108,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_row_open = 1'd0; + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6222,18 +6134,21 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine2_row_close = 1'd0; + soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin - soc_litedramcore_bankmachine2_row_close = 1'd1; + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine2_row_close = 1'd1; end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine2_row_close = 1'd1; end 3'd5: begin end @@ -6244,17 +6159,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin end @@ -6267,37 +6197,22 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1; - end + soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1; - end end 3'd4: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6326,21 +6241,21 @@ assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_c assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine3_cmd_payload_a = soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine3_cmd_payload_a = ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); always @(*) begin - soc_litedramcore_bankmachine3_auto_precharge = 1'd0; + soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine3_auto_precharge = (soc_litedramcore_bankmachine3_row_close == 1'd0); + soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); end end end @@ -6362,11 +6277,11 @@ assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; @@ -6378,60 +6293,95 @@ assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = ( assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); always @(*) begin - bankmachine3_next_state = 4'd0; - bankmachine3_next_state = bankmachine3_state; + bankmachine3_next_state <= 4'd0; + bankmachine3_next_state <= bankmachine3_state; case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin if (soc_litedramcore_bankmachine3_cmd_ready) begin - bankmachine3_next_state = 3'd5; + bankmachine3_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - bankmachine3_next_state = 3'd5; + bankmachine3_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin if (soc_litedramcore_bankmachine3_cmd_ready) begin - bankmachine3_next_state = 3'd7; + bankmachine3_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - bankmachine3_next_state = 1'd0; + bankmachine3_next_state <= 1'd0; end end 3'd5: begin - bankmachine3_next_state = 3'd6; + bankmachine3_next_state <= 3'd6; end 3'd6: begin - bankmachine3_next_state = 2'd3; + bankmachine3_next_state <= 2'd3; end 3'd7: begin - bankmachine3_next_state = 4'd8; + bankmachine3_next_state <= 4'd8; end 4'd8: begin - bankmachine3_next_state = 1'd0; + bankmachine3_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine3_refresh_req) begin - bankmachine3_next_state = 3'd4; + bankmachine3_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - bankmachine3_next_state = 2'd2; + bankmachine3_next_state <= 2'd2; end end else begin - bankmachine3_next_state = 1'd1; + bankmachine3_next_state <= 1'd1; + end + end else begin + bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin end end else begin - bankmachine3_next_state = 2'd3; end end end @@ -6439,11 +6389,40 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -6467,7 +6446,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -6480,7 +6459,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6488,7 +6467,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6506,22 +6485,22 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6536,7 +6515,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6562,7 +6541,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6574,7 +6553,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6599,7 +6578,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6612,7 +6591,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6637,7 +6616,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready = soc_litedramcore_bankmachine3_cmd_ready; + soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; end else begin end end else begin @@ -6650,7 +6629,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6676,7 +6655,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_row_hit) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine3_req_rdata_valid = soc_litedramcore_bankmachine3_cmd_ready; + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -6688,7 +6667,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6698,7 +6677,7 @@ always @(*) begin end 3'd4: begin if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt = 1'd1; + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -6714,18 +6693,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid = 1'd0; + soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -6744,7 +6723,7 @@ always @(*) begin if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine3_row_opened) begin if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid = 1'd1; + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin @@ -6755,7 +6734,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_row_open = 1'd0; + soc_litedramcore_bankmachine3_row_open <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -6763,7 +6742,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open = 1'd1; + soc_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -6781,18 +6760,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_row_close = 1'd0; + soc_litedramcore_bankmachine3_row_close <= 1'd0; case (bankmachine3_state) 1'd1: begin - soc_litedramcore_bankmachine3_row_close = 1'd1; + soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine3_row_close = 1'd1; + soc_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine3_row_close = 1'd1; + soc_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -6806,100 +6785,36 @@ always @(*) begin end endcase end +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; +assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); +assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; - case (bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; -assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); -assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine4_cmd_payload_a = soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine4_cmd_payload_a = ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); always @(*) begin - soc_litedramcore_bankmachine4_auto_precharge = 1'd0; + soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine4_auto_precharge = (soc_litedramcore_bankmachine4_row_close == 1'd0); + soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); end end end @@ -6921,11 +6836,11 @@ assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; @@ -6937,60 +6852,60 @@ assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = ( assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); always @(*) begin - bankmachine4_next_state = 4'd0; - bankmachine4_next_state = bankmachine4_state; + bankmachine4_next_state <= 4'd0; + bankmachine4_next_state <= bankmachine4_state; case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin if (soc_litedramcore_bankmachine4_cmd_ready) begin - bankmachine4_next_state = 3'd5; + bankmachine4_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - bankmachine4_next_state = 3'd5; + bankmachine4_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine4_trccon_ready) begin if (soc_litedramcore_bankmachine4_cmd_ready) begin - bankmachine4_next_state = 3'd7; + bankmachine4_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - bankmachine4_next_state = 1'd0; + bankmachine4_next_state <= 1'd0; end end 3'd5: begin - bankmachine4_next_state = 3'd6; + bankmachine4_next_state <= 3'd6; end 3'd6: begin - bankmachine4_next_state = 2'd3; + bankmachine4_next_state <= 2'd3; end 3'd7: begin - bankmachine4_next_state = 4'd8; + bankmachine4_next_state <= 4'd8; end 4'd8: begin - bankmachine4_next_state = 1'd0; + bankmachine4_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine4_refresh_req) begin - bankmachine4_next_state = 3'd4; + bankmachine4_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - bankmachine4_next_state = 2'd2; + bankmachine4_next_state <= 2'd2; end end else begin - bankmachine4_next_state = 1'd1; + bankmachine4_next_state <= 1'd1; end end else begin - bankmachine4_next_state = 2'd3; + bankmachine4_next_state <= 2'd3; end end end @@ -6998,12 +6913,9 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1; - end end 2'd2: begin end @@ -7025,10 +6937,7 @@ always @(*) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1; - end else begin - end + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -7039,15 +6948,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -7065,22 +6977,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (bankmachine4_state) 1'd1: begin if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -7091,17 +6999,35 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7114,34 +7040,26 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7152,26 +7070,11 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7196,8 +7099,8 @@ always @(*) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready = soc_litedramcore_bankmachine4_cmd_ready; end else begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7209,7 +7112,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7234,8 +7137,8 @@ always @(*) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine4_req_rdata_valid = soc_litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7247,7 +7150,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7256,9 +7159,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -7269,23 +7169,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid = 1'd0; + soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -7303,7 +7212,10 @@ always @(*) begin if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine4_row_opened) begin if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; + end end else begin end end else begin @@ -7314,18 +7226,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_row_open = 1'd0; + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7340,18 +7252,21 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine4_row_close = 1'd0; + soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin - soc_litedramcore_bankmachine4_row_close = 1'd1; + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine4_row_close = 1'd1; end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine4_row_close = 1'd1; end 3'd5: begin end @@ -7362,17 +7277,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine4_row_open <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin end @@ -7385,37 +7315,22 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1; - end + soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1; - end end 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7444,21 +7359,21 @@ assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_c assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine5_cmd_payload_a = soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine5_cmd_payload_a = ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); always @(*) begin - soc_litedramcore_bankmachine5_auto_precharge = 1'd0; + soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine5_auto_precharge = (soc_litedramcore_bankmachine5_row_close == 1'd0); + soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); end end end @@ -7480,11 +7395,11 @@ assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; @@ -7496,60 +7411,95 @@ assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = ( assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); always @(*) begin - bankmachine5_next_state = 4'd0; - bankmachine5_next_state = bankmachine5_state; + bankmachine5_next_state <= 4'd0; + bankmachine5_next_state <= bankmachine5_state; case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin if (soc_litedramcore_bankmachine5_cmd_ready) begin - bankmachine5_next_state = 3'd5; + bankmachine5_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - bankmachine5_next_state = 3'd5; + bankmachine5_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin if (soc_litedramcore_bankmachine5_cmd_ready) begin - bankmachine5_next_state = 3'd7; + bankmachine5_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - bankmachine5_next_state = 1'd0; + bankmachine5_next_state <= 1'd0; end end 3'd5: begin - bankmachine5_next_state = 3'd6; + bankmachine5_next_state <= 3'd6; end 3'd6: begin - bankmachine5_next_state = 2'd3; + bankmachine5_next_state <= 2'd3; end 3'd7: begin - bankmachine5_next_state = 4'd8; + bankmachine5_next_state <= 4'd8; end 4'd8: begin - bankmachine5_next_state = 1'd0; + bankmachine5_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine5_refresh_req) begin - bankmachine5_next_state = 3'd4; + bankmachine5_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - bankmachine5_next_state = 2'd2; + bankmachine5_next_state <= 2'd2; end end else begin - bankmachine5_next_state = 1'd1; + bankmachine5_next_state <= 1'd1; + end + end else begin + bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin end end else begin - bankmachine5_next_state = 2'd3; end end end @@ -7557,11 +7507,40 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -7585,7 +7564,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -7598,7 +7577,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7606,7 +7585,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7624,22 +7603,22 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7654,7 +7633,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7680,7 +7659,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_row_hit) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7692,7 +7671,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7717,7 +7696,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -7730,7 +7709,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7755,7 +7734,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready = soc_litedramcore_bankmachine5_cmd_ready; + soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -7768,7 +7747,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7794,7 +7773,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_row_hit) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine5_req_rdata_valid = soc_litedramcore_bankmachine5_cmd_ready; + soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -7806,7 +7785,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7816,7 +7795,7 @@ always @(*) begin end 3'd4: begin if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt = 1'd1; + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -7832,18 +7811,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid = 1'd0; + soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7862,7 +7841,7 @@ always @(*) begin if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine5_row_opened) begin if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid = 1'd1; + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -7873,7 +7852,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_row_open = 1'd0; + soc_litedramcore_bankmachine5_row_open <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -7881,7 +7860,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open = 1'd1; + soc_litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin @@ -7899,18 +7878,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine5_row_close = 1'd0; + soc_litedramcore_bankmachine5_row_close <= 1'd0; case (bankmachine5_state) 1'd1: begin - soc_litedramcore_bankmachine5_row_close = 1'd1; + soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine5_row_close = 1'd1; + soc_litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine5_row_close = 1'd1; + soc_litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end @@ -7924,100 +7903,36 @@ always @(*) begin end endcase end +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; +assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); +assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); +assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; - case (bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; - case (bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; -assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); -assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); -assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine6_cmd_payload_a = soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine6_cmd_payload_a = ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); always @(*) begin - soc_litedramcore_bankmachine6_auto_precharge = 1'd0; + soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine6_auto_precharge = (soc_litedramcore_bankmachine6_row_close == 1'd0); + soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); end end end @@ -8039,11 +7954,11 @@ assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; @@ -8055,60 +7970,60 @@ assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = ( assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); always @(*) begin - bankmachine6_next_state = 4'd0; - bankmachine6_next_state = bankmachine6_state; + bankmachine6_next_state <= 4'd0; + bankmachine6_next_state <= bankmachine6_state; case (bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin if (soc_litedramcore_bankmachine6_cmd_ready) begin - bankmachine6_next_state = 3'd5; + bankmachine6_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - bankmachine6_next_state = 3'd5; + bankmachine6_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin if (soc_litedramcore_bankmachine6_cmd_ready) begin - bankmachine6_next_state = 3'd7; + bankmachine6_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - bankmachine6_next_state = 1'd0; + bankmachine6_next_state <= 1'd0; end end 3'd5: begin - bankmachine6_next_state = 3'd6; + bankmachine6_next_state <= 3'd6; end 3'd6: begin - bankmachine6_next_state = 2'd3; + bankmachine6_next_state <= 2'd3; end 3'd7: begin - bankmachine6_next_state = 4'd8; + bankmachine6_next_state <= 4'd8; end 4'd8: begin - bankmachine6_next_state = 1'd0; + bankmachine6_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine6_refresh_req) begin - bankmachine6_next_state = 3'd4; + bankmachine6_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - bankmachine6_next_state = 2'd2; + bankmachine6_next_state <= 2'd2; end end else begin - bankmachine6_next_state = 1'd1; + bankmachine6_next_state <= 1'd1; end end else begin - bankmachine6_next_state = 2'd3; + bankmachine6_next_state <= 2'd3; end end end @@ -8116,12 +8031,9 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1; - end end 2'd2: begin end @@ -8143,10 +8055,7 @@ always @(*) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1; - end else begin - end + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8157,15 +8066,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8183,22 +8095,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; - end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; end 3'd5: begin end @@ -8209,17 +8117,35 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8232,34 +8158,26 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8270,26 +8188,11 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8314,8 +8217,8 @@ always @(*) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready = soc_litedramcore_bankmachine6_cmd_ready; end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8327,7 +8230,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8352,8 +8255,8 @@ always @(*) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin - soc_litedramcore_bankmachine6_req_rdata_valid = soc_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8365,7 +8268,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -8374,9 +8277,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt = 1'd1; - end end 3'd5: begin end @@ -8387,23 +8287,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid = 1'd0; + soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid = 1'd1; - end end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid = 1'd1; - end end 3'd4: begin end @@ -8421,7 +8330,10 @@ always @(*) begin if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid = 1'd1; + if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; + end end else begin end end else begin @@ -8432,18 +8344,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_row_open = 1'd0; + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open = 1'd1; - end end 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8458,18 +8370,21 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine6_row_close = 1'd0; + soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin - soc_litedramcore_bankmachine6_row_close = 1'd1; + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin - soc_litedramcore_bankmachine6_row_close = 1'd1; end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin - soc_litedramcore_bankmachine6_row_close = 1'd1; end 3'd5: begin end @@ -8480,17 +8395,32 @@ always @(*) begin 4'd8: begin end default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; + soc_litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -8503,37 +8433,22 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; + soc_litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1; - end + soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1; - end end 3'd4: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8562,21 +8477,21 @@ assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_c assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; + soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine7_cmd_payload_a = soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; end else begin - soc_litedramcore_bankmachine7_cmd_payload_a = ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end end assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); always @(*) begin - soc_litedramcore_bankmachine7_auto_precharge = 1'd0; + soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine7_auto_precharge = (soc_litedramcore_bankmachine7_row_close == 1'd0); + soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); end end end @@ -8598,11 +8513,11 @@ assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = so assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; always @(*) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); end else begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end end assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; @@ -8614,60 +8529,95 @@ assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = ( assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); always @(*) begin - bankmachine7_next_state = 4'd0; - bankmachine7_next_state = bankmachine7_state; + bankmachine7_next_state <= 4'd0; + bankmachine7_next_state <= bankmachine7_state; case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin if (soc_litedramcore_bankmachine7_cmd_ready) begin - bankmachine7_next_state = 3'd5; + bankmachine7_next_state <= 3'd5; end end end 2'd2: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - bankmachine7_next_state = 3'd5; + bankmachine7_next_state <= 3'd5; end end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin if (soc_litedramcore_bankmachine7_cmd_ready) begin - bankmachine7_next_state = 3'd7; + bankmachine7_next_state <= 3'd7; end end end 3'd4: begin if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - bankmachine7_next_state = 1'd0; + bankmachine7_next_state <= 1'd0; end end 3'd5: begin - bankmachine7_next_state = 3'd6; + bankmachine7_next_state <= 3'd6; end 3'd6: begin - bankmachine7_next_state = 2'd3; + bankmachine7_next_state <= 2'd3; end 3'd7: begin - bankmachine7_next_state = 4'd8; + bankmachine7_next_state <= 4'd8; end 4'd8: begin - bankmachine7_next_state = 1'd0; + bankmachine7_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine7_refresh_req) begin - bankmachine7_next_state = 3'd4; + bankmachine7_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - bankmachine7_next_state = 2'd2; + bankmachine7_next_state <= 2'd2; end end else begin - bankmachine7_next_state = 1'd1; + bankmachine7_next_state <= 1'd1; + end + end else begin + bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin end end else begin - bankmachine7_next_state = 2'd3; end end end @@ -8675,11 +8625,40 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin @@ -8703,7 +8682,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin @@ -8716,7 +8695,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8724,7 +8703,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8742,22 +8721,22 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8772,7 +8751,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8798,7 +8777,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_row_hit) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8810,7 +8789,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8835,7 +8814,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -8848,7 +8827,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; + soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8873,7 +8852,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready = soc_litedramcore_bankmachine7_cmd_ready; + soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -8886,7 +8865,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8912,7 +8891,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_row_hit) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - soc_litedramcore_bankmachine7_req_rdata_valid = soc_litedramcore_bankmachine7_cmd_ready; + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -8924,7 +8903,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8934,7 +8913,7 @@ always @(*) begin end 3'd4: begin if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt = 1'd1; + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin @@ -8950,18 +8929,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid = 1'd0; + soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8980,7 +8959,7 @@ always @(*) begin if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (soc_litedramcore_bankmachine7_row_opened) begin if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid = 1'd1; + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -8991,7 +8970,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_row_open = 1'd0; + soc_litedramcore_bankmachine7_row_open <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -8999,7 +8978,7 @@ always @(*) begin end 2'd3: begin if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open = 1'd1; + soc_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9017,82 +8996,18 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_row_close = 1'd0; + soc_litedramcore_bankmachine7_row_close <= 1'd0; case (bankmachine7_state) 1'd1: begin - soc_litedramcore_bankmachine7_row_close = 1'd1; + soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - soc_litedramcore_bankmachine7_row_close = 1'd1; + soc_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - soc_litedramcore_bankmachine7_row_close = 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; - case (bankmachine7_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1; - end - end - 3'd4: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9135,15 +9050,15 @@ assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); always @(*) begin - soc_litedramcore_choose_cmd_valids = 8'd0; - soc_litedramcore_choose_cmd_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids <= 8'd0; + soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); end assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -9153,106 +9068,106 @@ assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; + soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0; + soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end end always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; + soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1; + soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end end always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; + soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2; + soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; end end always @(*) begin - soc_litedramcore_bankmachine0_cmd_ready = 1'd0; + soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready = 1'd1; + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready = 1'd1; + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine1_cmd_ready = 1'd0; + soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready = 1'd1; + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready = 1'd1; + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine2_cmd_ready = 1'd0; + soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready = 1'd1; + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready = 1'd1; + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine3_cmd_ready = 1'd0; + soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready = 1'd1; + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready = 1'd1; + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine4_cmd_ready = 1'd0; + soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready = 1'd1; + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready = 1'd1; + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine5_cmd_ready = 1'd0; + soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready = 1'd1; + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready = 1'd1; + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine6_cmd_ready = 1'd0; + soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready = 1'd1; + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready = 1'd1; + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin - soc_litedramcore_bankmachine7_cmd_ready = 1'd0; + soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready = 1'd1; + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; end if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready = 1'd1; + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; end end assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - soc_litedramcore_choose_req_valids = 8'd0; - soc_litedramcore_choose_req_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids <= 8'd0; + soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); end assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -9262,21 +9177,21 @@ assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; + soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas = t_array_muxed3; + soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end end always @(*) begin - soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; + soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras = t_array_muxed4; + soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end end always @(*) begin - soc_litedramcore_choose_req_cmd_payload_we = 1'd0; + soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we = t_array_muxed5; + soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end end assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); @@ -9294,76 +9209,69 @@ assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); always @(*) begin - multiplexer_next_state = 4'd0; - multiplexer_next_state = multiplexer_state; + multiplexer_next_state <= 4'd0; + multiplexer_next_state <= multiplexer_state; case (multiplexer_state) 1'd1: begin if (soc_litedramcore_read_available) begin if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - multiplexer_next_state = 2'd3; + multiplexer_next_state <= 2'd3; end end if (soc_litedramcore_go_to_refresh) begin - multiplexer_next_state = 2'd2; + multiplexer_next_state <= 2'd2; end end 2'd2: begin if (soc_litedramcore_cmd_last) begin - multiplexer_next_state = 1'd0; + multiplexer_next_state <= 1'd0; end end 2'd3: begin if (soc_litedramcore_twtrcon_ready) begin - multiplexer_next_state = 1'd0; + multiplexer_next_state <= 1'd0; end end 3'd4: begin - multiplexer_next_state = 3'd5; + multiplexer_next_state <= 3'd5; end 3'd5: begin - multiplexer_next_state = 3'd6; + multiplexer_next_state <= 3'd6; end 3'd6: begin - multiplexer_next_state = 3'd7; + multiplexer_next_state <= 3'd7; end 3'd7: begin - multiplexer_next_state = 4'd8; + multiplexer_next_state <= 4'd8; end 4'd8: begin - multiplexer_next_state = 4'd9; + multiplexer_next_state <= 4'd9; end 4'd9: begin - multiplexer_next_state = 4'd10; + multiplexer_next_state <= 4'd10; end 4'd10: begin - multiplexer_next_state = 1'd1; + multiplexer_next_state <= 1'd1; end default: begin if (soc_litedramcore_write_available) begin if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - multiplexer_next_state = 3'd4; + multiplexer_next_state <= 3'd4; end end if (soc_litedramcore_go_to_refresh) begin - multiplexer_next_state = 2'd2; + multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin - soc_litedramcore_steerer_sel0 = 2'd0; + soc_litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel0 = 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel0 = 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel0 = 1'd1; - end + soc_litedramcore_en1 <= 1'd1; end 2'd2: begin - soc_litedramcore_steerer_sel0 = 2'd3; end 2'd3: begin end @@ -9382,29 +9290,23 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel0 = 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel0 = 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel0 = 1'd1; - end end endcase end always @(*) begin - soc_litedramcore_steerer_sel1 = 2'd0; + soc_litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel1 = 1'd0; + soc_litedramcore_steerer_sel0 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel1 = 2'd2; + soc_litedramcore_steerer_sel0 <= 2'd2; end if (1'd0) begin - soc_litedramcore_steerer_sel1 = 1'd1; + soc_litedramcore_steerer_sel0 <= 1'd1; end end 2'd2: begin + soc_litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -9423,26 +9325,26 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel1 = 1'd0; + soc_litedramcore_steerer_sel0 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel1 = 2'd2; + soc_litedramcore_steerer_sel0 <= 2'd2; end - if (1'd1) begin - soc_litedramcore_steerer_sel1 = 1'd1; + if (1'd0) begin + soc_litedramcore_steerer_sel0 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_steerer_sel2 = 2'd0; + soc_litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel2 = 1'd0; + soc_litedramcore_steerer_sel1 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel2 = 2'd2; + soc_litedramcore_steerer_sel1 <= 2'd2; end - if (1'd1) begin - soc_litedramcore_steerer_sel2 = 1'd1; + if (1'd0) begin + soc_litedramcore_steerer_sel1 <= 1'd1; end end 2'd2: begin @@ -9464,23 +9366,26 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel2 = 1'd0; - if (1'd1) begin - soc_litedramcore_steerer_sel2 = 2'd2; - end + soc_litedramcore_steerer_sel1 <= 1'd0; if (1'd0) begin - soc_litedramcore_steerer_sel2 = 1'd1; + soc_litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel1 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_choose_cmd_want_activates = 1'd0; + soc_litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin + soc_litedramcore_steerer_sel2 <= 1'd0; if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed; + soc_litedramcore_steerer_sel2 <= 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel2 <= 1'd1; end end 2'd2: begin @@ -9502,23 +9407,23 @@ always @(*) begin 4'd10: begin end default: begin + soc_litedramcore_steerer_sel2 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel2 <= 2'd2; + end if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed; + soc_litedramcore_steerer_sel2 <= 1'd1; end end endcase end always @(*) begin - soc_litedramcore_steerer_sel3 = 2'd0; + soc_litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer_sel3 = 1'd0; - if (1'd1) begin - soc_litedramcore_steerer_sel3 = 2'd2; - end if (1'd0) begin - soc_litedramcore_steerer_sel3 = 1'd1; + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; end end 2'd2: begin @@ -9540,20 +9445,24 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer_sel3 = 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel3 = 2'd2; - end if (1'd0) begin - soc_litedramcore_steerer_sel3 = 1'd1; + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; end end endcase end always @(*) begin - soc_litedramcore_en0 = 1'd0; + soc_litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + soc_litedramcore_steerer_sel3 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel3 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 <= 1'd1; + end end 2'd2: begin end @@ -9574,17 +9483,22 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_en0 = 1'd1; + soc_litedramcore_steerer_sel3 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel3 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 <= 1'd1; + end end endcase end always @(*) begin - soc_litedramcore_cmd_ready = 1'd0; + soc_litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - soc_litedramcore_cmd_ready = 1'd1; end 2'd3: begin end @@ -9603,19 +9517,17 @@ always @(*) begin 4'd10: begin end default: begin + soc_litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready = 1'd0; + soc_litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end end 2'd2: begin + soc_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -9634,17 +9546,17 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end end endcase end always @(*) begin - soc_litedramcore_choose_req_want_reads = 1'd0; + soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -9665,15 +9577,17 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_choose_req_want_reads = 1'd1; + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end end endcase end always @(*) begin - soc_litedramcore_choose_req_want_writes = 1'd0; + soc_litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_choose_req_want_writes = 1'd1; end 2'd2: begin end @@ -9694,14 +9608,15 @@ always @(*) begin 4'd10: begin end default: begin + soc_litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin - soc_litedramcore_en1 = 1'd0; + soc_litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_en1 = 1'd1; + soc_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -9726,13 +9641,13 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_choose_req_cmd_ready = 1'd0; + soc_litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed; + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; end end 2'd2: begin @@ -9755,9 +9670,9 @@ always @(*) begin end default: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); end else begin - soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed; + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; end end endcase @@ -9806,24 +9721,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & assign soc_user_port_wdata_ready = new_master_wdata_ready1; assign soc_user_port_rdata_valid = new_master_rdata_valid8; always @(*) begin - soc_litedramcore_interface_wdata = 128'd0; + soc_litedramcore_interface_wdata <= 128'd0; case ({new_master_wdata_ready1}) 1'd1: begin - soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data; + soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; end default: begin - soc_litedramcore_interface_wdata = 1'd0; + soc_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - soc_litedramcore_interface_wdata_we = 16'd0; + soc_litedramcore_interface_wdata_we <= 16'd0; case ({new_master_wdata_ready1}) 1'd1: begin - soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we; + soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; end default: begin - soc_litedramcore_interface_wdata_we = 1'd0; + soc_litedramcore_interface_wdata_we <= 1'd0; end endcase end @@ -9837,858 +9752,494 @@ assign roundrobin5_grant = 1'd0; assign roundrobin6_grant = 1'd0; assign roundrobin7_grant = 1'd0; always @(*) begin - next_state = 2'd0; - next_state = state; + next_state <= 2'd0; + next_state <= state; case (state) 1'd1: begin - next_state = 2'd2; + next_state <= 2'd2; end 2'd2: begin - next_state = 1'd0; + next_state <= 1'd0; end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - next_state = 1'd1; + next_state <= 1'd1; end end endcase end always @(*) begin - litedramcore_adr_next_value1 = 14'd0; + litedramcore_adr_next_value1 <= 14'd0; case (state) 1'd1: begin - litedramcore_adr_next_value1 = 1'd0; + litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 = litedramcore_wishbone_adr; + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; end end endcase end always @(*) begin - litedramcore_adr_next_value_ce1 = 1'd0; + litedramcore_adr_next_value_ce1 <= 1'd0; case (state) 1'd1: begin - litedramcore_adr_next_value_ce1 = 1'd1; + litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 = 1'd1; + litedramcore_adr_next_value_ce1 <= 1'd1; end end endcase end always @(*) begin - litedramcore_we_next_value2 = 1'd0; + litedramcore_wishbone_dat_r <= 32'd0; case (state) 1'd1: begin - litedramcore_we_next_value2 = 1'd0; end 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end end endcase end always @(*) begin - litedramcore_we_next_value_ce2 = 1'd0; + litedramcore_we_next_value2 <= 1'd0; case (state) 1'd1: begin - litedramcore_we_next_value_ce2 = 1'd1; + litedramcore_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 = 1'd1; + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase end always @(*) begin - litedramcore_wishbone_dat_r = 32'd0; - case (state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r = litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 = 8'd0; - case (state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 = litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 = 1'd0; + litedramcore_we_next_value_ce2 <= 1'd0; case (state) 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 = 1'd1; - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack = 1'd0; - case (state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack = 1'd1; - end - default: begin - end - endcase -end -assign litedramcore_wishbone_adr = soc_wb_bus_adr; -assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; -assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r; -assign litedramcore_wishbone_sel = soc_wb_bus_sel; -assign litedramcore_wishbone_cyc = soc_wb_bus_cyc; -assign litedramcore_wishbone_stb = soc_wb_bus_stb; -assign soc_wb_bus_ack = litedramcore_wishbone_ack; -assign litedramcore_wishbone_we = soc_wb_bus_we; -assign litedramcore_wishbone_cti = soc_wb_bus_cti; -assign litedramcore_wishbone_bte = soc_wb_bus_bte; -assign soc_wb_bus_err = litedramcore_wishbone_err; -assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd1); -assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -always @(*) begin - csrbank0_init_done0_we = 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we = (~interface0_bank_bus_we); - end -end -always @(*) begin - csrbank0_init_done0_re = 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re = interface0_bank_bus_we; - end -end -assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -always @(*) begin - csrbank0_init_error0_re = 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re = interface0_bank_bus_we; - end -end -always @(*) begin - csrbank0_init_error0_we = 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we = (~interface0_bank_bus_we); - end -end -assign csrbank0_init_done0_w = soc_init_done_storage; -assign csrbank0_init_error0_w = soc_init_error_storage; -assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0); -assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; -always @(*) begin - csrbank1_dfii_control0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_control0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; -always @(*) begin - csrbank1_dfii_pi0_command0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi0_command0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we; - end -end -assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_re = interface1_bank_bus_we; - end -end -always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0]; -always @(*) begin - csrbank1_dfii_pi0_address1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dfii_pi0_address1_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi0_address1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dfii_pi0_address1_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_address0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dfii_pi0_address0_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi0_address0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dfii_pi0_address0_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; -always @(*) begin - csrbank1_dfii_pi0_baddress0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_baddress0_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi0_baddress0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_baddress0_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_wrdata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi0_wrdata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_wrdata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - csrbank1_dfii_pi0_wrdata2_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi0_wrdata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - csrbank1_dfii_pi0_wrdata2_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_wrdata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - csrbank1_dfii_pi0_wrdata1_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi0_wrdata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - csrbank1_dfii_pi0_wrdata1_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_wrdata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi0_wrdata0_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi0_wrdata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi0_wrdata0_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_rddata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi0_rddata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_rddata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_dfii_pi0_rddata2_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi0_rddata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_dfii_pi0_rddata2_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_rddata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi0_rddata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi0_rddata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi0_rddata0_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi0_rddata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi0_rddata0_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; -always @(*) begin - csrbank1_dfii_pi1_command0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi1_command0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we; - end -end -assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; -always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - soc_litedramcore_phaseinjector1_command_issue_re = interface1_bank_bus_we; - end -end -always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - soc_litedramcore_phaseinjector1_command_issue_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0]; -always @(*) begin - csrbank1_dfii_pi1_address1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - csrbank1_dfii_pi1_address1_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi1_address1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - csrbank1_dfii_pi1_address1_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_address0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi1_address0_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi1_address0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi1_address0_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; -always @(*) begin - csrbank1_dfii_pi1_baddress0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi1_baddress0_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi1_baddress0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi1_baddress0_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_wrdata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin - csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi1_wrdata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin - csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_wrdata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin - csrbank1_dfii_pi1_wrdata2_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi1_wrdata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin - csrbank1_dfii_pi1_wrdata2_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_wrdata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi1_wrdata1_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi1_wrdata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi1_wrdata1_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_wrdata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi1_wrdata0_re = interface1_bank_bus_we; - end -end -always @(*) begin - csrbank1_dfii_pi1_wrdata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi1_wrdata0_we = (~interface1_bank_bus_we); - end -end -assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_rddata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin - csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we); - end -end -always @(*) begin - csrbank1_dfii_pi1_rddata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin - csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we; - end -end -assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0]; -always @(*) begin - csrbank1_dfii_pi1_rddata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin - csrbank1_dfii_pi1_rddata2_we = (~interface1_bank_bus_we); - end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase end always @(*) begin - csrbank1_dfii_pi1_rddata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin - csrbank1_dfii_pi1_rddata2_re = interface1_bank_bus_we; - end + litedramcore_wishbone_ack <= 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase end -assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - csrbank1_dfii_pi1_rddata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin - csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we; - end + litedramcore_dat_w_next_value0 <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase end always @(*) begin - csrbank1_dfii_pi1_rddata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin - csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we); - end + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase end -assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign litedramcore_wishbone_adr = soc_wb_bus_adr; +assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; +assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = soc_wb_bus_sel; +assign litedramcore_wishbone_cyc = soc_wb_bus_cyc; +assign litedramcore_wishbone_stb = soc_wb_bus_stb; +assign soc_wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = soc_wb_bus_we; +assign litedramcore_wishbone_cti = soc_wb_bus_cti; +assign litedramcore_wishbone_bte = soc_wb_bus_bte; +assign soc_wb_bus_err = litedramcore_wishbone_err; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank1_dfii_pi1_rddata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin - csrbank1_dfii_pi1_rddata0_re = interface1_bank_bus_we; + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi1_rddata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin - csrbank1_dfii_pi1_rddata0_we = (~interface1_bank_bus_we); + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); end end -assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank1_dfii_pi2_command0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin - csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we); + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_command0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin - csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we; + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; end end -assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; +assign csrbank0_init_done0_w = soc_init_done_storage; +assign csrbank0_init_error0_w = soc_init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; always @(*) begin - soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin - soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we; + csrbank1_dfii_control0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dfii_control0_we <= (~interface1_bank_bus_we); end end always @(*) begin - soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin - soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we); + csrbank1_dfii_control0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dfii_control0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi2_address1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin - csrbank1_dfii_pi2_address1_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi0_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_address1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin - csrbank1_dfii_pi2_address1_re = interface1_bank_bus_we; + csrbank1_dfii_pi0_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0]; +assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_dfii_pi2_address0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin - csrbank1_dfii_pi2_address0_re = interface1_bank_bus_we; + soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_address0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin - csrbank1_dfii_pi2_address0_we = (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; +assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi2_baddress0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin - csrbank1_dfii_pi2_baddress0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi0_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_baddress0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin - csrbank1_dfii_pi2_baddress0_re = interface1_bank_bus_we; + csrbank1_dfii_pi0_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi2_wrdata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin - csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we; + csrbank1_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_wrdata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin - csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_wrdata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin - csrbank1_dfii_pi2_wrdata2_re = interface1_bank_bus_we; + csrbank1_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_wrdata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin - csrbank1_dfii_pi2_wrdata2_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_wrdata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin - csrbank1_dfii_pi2_wrdata1_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi0_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_wrdata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin - csrbank1_dfii_pi2_wrdata1_re = interface1_bank_bus_we; + csrbank1_dfii_pi0_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi2_wrdata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin - csrbank1_dfii_pi2_wrdata0_re = interface1_bank_bus_we; + csrbank1_dfii_pi1_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_wrdata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin - csrbank1_dfii_pi2_wrdata0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi1_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0]; +assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_dfii_pi2_rddata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin - csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_rddata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin - csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we; + soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi2_rddata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin - csrbank1_dfii_pi2_rddata2_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi1_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_rddata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin - csrbank1_dfii_pi2_rddata2_re = interface1_bank_bus_we; + csrbank1_dfii_pi1_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi2_rddata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin - csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we; + csrbank1_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_rddata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin - csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_rddata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin - csrbank1_dfii_pi2_rddata0_re = interface1_bank_bus_we; + csrbank1_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi2_rddata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin - csrbank1_dfii_pi2_rddata0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_command0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin - csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi1_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_command0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin - csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we; + csrbank1_dfii_pi1_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we); end end -assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; +assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin - soc_litedramcore_phaseinjector3_command_issue_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi2_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we); end end always @(*) begin - soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin - soc_litedramcore_phaseinjector3_command_issue_re = interface1_bank_bus_we; + csrbank1_dfii_pi2_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0]; +assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_dfii_pi3_address1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin - csrbank1_dfii_pi3_address1_we = (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_address1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin - csrbank1_dfii_pi3_address1_re = interface1_bank_bus_we; + soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi3_address0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin - csrbank1_dfii_pi3_address0_re = interface1_bank_bus_we; + csrbank1_dfii_pi2_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi3_address0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin - csrbank1_dfii_pi3_address0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi2_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; +assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi3_baddress0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin - csrbank1_dfii_pi3_baddress0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_baddress0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin - csrbank1_dfii_pi3_baddress0_re = interface1_bank_bus_we; + csrbank1_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_wrdata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin - csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we; + csrbank1_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi3_wrdata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin - csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_wrdata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin - csrbank1_dfii_pi3_wrdata2_re = interface1_bank_bus_we; + csrbank1_dfii_pi2_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_wrdata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin - csrbank1_dfii_pi3_wrdata2_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi2_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi3_wrdata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin - csrbank1_dfii_pi3_wrdata1_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi3_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin + csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_wrdata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin - csrbank1_dfii_pi3_wrdata1_re = interface1_bank_bus_we; + csrbank1_dfii_pi3_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin + csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0]; +assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_dfii_pi3_wrdata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin - csrbank1_dfii_pi3_wrdata0_re = interface1_bank_bus_we; + soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin + soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_wrdata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin - csrbank1_dfii_pi3_wrdata0_we = (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin + soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi3_rddata3_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin - csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi3_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin + csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi3_rddata3_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin - csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we; + csrbank1_dfii_pi3_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin + csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi3_rddata2_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin - csrbank1_dfii_pi3_rddata2_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin + csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_rddata2_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin - csrbank1_dfii_pi3_rddata2_re = interface1_bank_bus_we; + csrbank1_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin + csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_rddata1_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin - csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we; + csrbank1_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin + csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_rddata1_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin - csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin + csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we); end end -assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0]; +assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_rddata0_re = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin - csrbank1_dfii_pi3_rddata0_re = interface1_bank_bus_we; + csrbank1_dfii_pi3_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin + csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we); end end always @(*) begin - csrbank1_dfii_pi3_rddata0_we = 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin - csrbank1_dfii_pi3_rddata0_we = (~interface1_bank_bus_we); + csrbank1_dfii_pi3_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin + csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we; end end assign soc_litedramcore_sel = soc_litedramcore_storage[0]; @@ -10697,57 +10248,29 @@ assign soc_litedramcore_odt = soc_litedramcore_storage[2]; assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0]; assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0]; -assign csrbank1_dfii_pi0_address1_w = soc_litedramcore_phaseinjector0_address_storage[13:8]; -assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[7:0]; +assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0]; assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank1_dfii_pi0_wrdata3_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign csrbank1_dfii_pi0_wrdata2_w = soc_litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign csrbank1_dfii_pi0_wrdata1_w = soc_litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign csrbank1_dfii_pi0_rddata3_w = soc_litedramcore_phaseinjector0_rddata_status[31:24]; -assign csrbank1_dfii_pi0_rddata2_w = soc_litedramcore_phaseinjector0_rddata_status[23:16]; -assign csrbank1_dfii_pi0_rddata1_w = soc_litedramcore_phaseinjector0_rddata_status[15:8]; -assign csrbank1_dfii_pi0_rddata0_w = soc_litedramcore_phaseinjector0_rddata_status[7:0]; -assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata0_we; +assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status[31:0]; +assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata_we; assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0]; -assign csrbank1_dfii_pi1_address1_w = soc_litedramcore_phaseinjector1_address_storage[13:8]; -assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[7:0]; +assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0]; assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank1_dfii_pi1_wrdata3_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign csrbank1_dfii_pi1_wrdata2_w = soc_litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign csrbank1_dfii_pi1_wrdata1_w = soc_litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign csrbank1_dfii_pi1_rddata3_w = soc_litedramcore_phaseinjector1_rddata_status[31:24]; -assign csrbank1_dfii_pi1_rddata2_w = soc_litedramcore_phaseinjector1_rddata_status[23:16]; -assign csrbank1_dfii_pi1_rddata1_w = soc_litedramcore_phaseinjector1_rddata_status[15:8]; -assign csrbank1_dfii_pi1_rddata0_w = soc_litedramcore_phaseinjector1_rddata_status[7:0]; -assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata0_we; +assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status[31:0]; +assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata_we; assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0]; -assign csrbank1_dfii_pi2_address1_w = soc_litedramcore_phaseinjector2_address_storage[13:8]; -assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[7:0]; +assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0]; assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank1_dfii_pi2_wrdata3_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign csrbank1_dfii_pi2_wrdata2_w = soc_litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign csrbank1_dfii_pi2_wrdata1_w = soc_litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign csrbank1_dfii_pi2_rddata3_w = soc_litedramcore_phaseinjector2_rddata_status[31:24]; -assign csrbank1_dfii_pi2_rddata2_w = soc_litedramcore_phaseinjector2_rddata_status[23:16]; -assign csrbank1_dfii_pi2_rddata1_w = soc_litedramcore_phaseinjector2_rddata_status[15:8]; -assign csrbank1_dfii_pi2_rddata0_w = soc_litedramcore_phaseinjector2_rddata_status[7:0]; -assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata0_we; +assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status[31:0]; +assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata_we; assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0]; -assign csrbank1_dfii_pi3_address1_w = soc_litedramcore_phaseinjector3_address_storage[13:8]; -assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[7:0]; +assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0]; assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank1_dfii_pi3_wrdata3_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign csrbank1_dfii_pi3_wrdata2_w = soc_litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign csrbank1_dfii_pi3_wrdata1_w = soc_litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign csrbank1_dfii_pi3_rddata3_w = soc_litedramcore_phaseinjector3_rddata_status[31:24]; -assign csrbank1_dfii_pi3_rddata2_w = soc_litedramcore_phaseinjector3_rddata_status[23:16]; -assign csrbank1_dfii_pi3_rddata1_w = soc_litedramcore_phaseinjector3_rddata_status[15:8]; -assign csrbank1_dfii_pi3_rddata0_w = soc_litedramcore_phaseinjector3_rddata_status[7:0]; -assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata0_we; +assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status[31:0]; +assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we; assign csr_interconnect_adr = litedramcore_adr; assign csr_interconnect_we = litedramcore_we; assign csr_interconnect_dat_w = litedramcore_dat_w; @@ -10776,1196 +10299,1201 @@ assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bank assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col); assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col); always @(*) begin - rhs_array_muxed0 = 1'd0; + rhs_array_muxed0 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[0]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; end 1'd1: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[1]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; end 2'd2: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[2]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; end 2'd3: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[3]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; end 3'd4: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[4]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; end 3'd5: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[5]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; end 3'd6: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[6]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; end default: begin - rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[7]; + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin - rhs_array_muxed1 = 14'd0; + rhs_array_muxed1 <= 14'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_a; + rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed2 = 3'd0; + rhs_array_muxed2 <= 3'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_ba; + rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed3 = 1'd0; + rhs_array_muxed3 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_is_read; + rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed4 = 1'd0; + rhs_array_muxed4 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_is_write; + rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed5 = 1'd0; + rhs_array_muxed5 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed0 = 1'd0; + t_array_muxed0 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed0 = soc_litedramcore_bankmachine0_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed0 = soc_litedramcore_bankmachine1_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed0 = soc_litedramcore_bankmachine2_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed0 = soc_litedramcore_bankmachine3_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed0 = soc_litedramcore_bankmachine4_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed0 = soc_litedramcore_bankmachine5_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed0 = soc_litedramcore_bankmachine6_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed0 = soc_litedramcore_bankmachine7_cmd_payload_cas; + t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed1 = 1'd0; + t_array_muxed1 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_ras; + t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed2 = 1'd0; + t_array_muxed2 <= 1'd0; case (soc_litedramcore_choose_cmd_grant) 1'd0: begin - t_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_we; + t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed6 = 1'd0; + rhs_array_muxed6 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[0]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; end 1'd1: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[1]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; end 2'd2: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[2]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; end 2'd3: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[3]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; end 3'd4: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[4]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; end 3'd5: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[5]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; end 3'd6: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[6]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; end default: begin - rhs_array_muxed6 = soc_litedramcore_choose_req_valids[7]; + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; end endcase end always @(*) begin - rhs_array_muxed7 = 14'd0; + rhs_array_muxed7 <= 14'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine0_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine1_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine2_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine3_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine4_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine5_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine6_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; end default: begin - rhs_array_muxed7 = soc_litedramcore_bankmachine7_cmd_payload_a; + rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin - rhs_array_muxed8 = 3'd0; + rhs_array_muxed8 <= 3'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine0_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine1_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine2_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine3_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine4_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine5_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine6_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; end default: begin - rhs_array_muxed8 = soc_litedramcore_bankmachine7_cmd_payload_ba; + rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin - rhs_array_muxed9 = 1'd0; + rhs_array_muxed9 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine0_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine1_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine2_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine3_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine4_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine5_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine6_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; end default: begin - rhs_array_muxed9 = soc_litedramcore_bankmachine7_cmd_payload_is_read; + rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin - rhs_array_muxed10 = 1'd0; + rhs_array_muxed10 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine0_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine1_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine2_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine3_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine4_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine5_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine6_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; end default: begin - rhs_array_muxed10 = soc_litedramcore_bankmachine7_cmd_payload_is_write; + rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin - rhs_array_muxed11 = 1'd0; + rhs_array_muxed11 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin - rhs_array_muxed11 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin - t_array_muxed3 = 1'd0; + t_array_muxed3 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin - t_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin - t_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin - t_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin - t_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin - t_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin - t_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; end default: begin - t_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_cas; + t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin - t_array_muxed4 = 1'd0; + t_array_muxed4 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin - t_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin - t_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin - t_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin - t_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin - t_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin - t_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; end default: begin - t_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_ras; + t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin - t_array_muxed5 = 1'd0; + t_array_muxed5 <= 1'd0; case (soc_litedramcore_choose_req_grant) 1'd0: begin - t_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin - t_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin - t_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin - t_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin - t_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin - t_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin - t_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; end default: begin - t_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_we; + t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed12 = 21'd0; + rhs_array_muxed12 <= 21'd0; case (roundrobin0_grant) default: begin - rhs_array_muxed12 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed13 = 1'd0; + rhs_array_muxed13 <= 1'd0; case (roundrobin0_grant) default: begin - rhs_array_muxed13 = soc_user_port_cmd_payload_we; + rhs_array_muxed13 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed14 = 1'd0; + rhs_array_muxed14 <= 1'd0; case (roundrobin0_grant) default: begin - rhs_array_muxed14 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed15 = 21'd0; + rhs_array_muxed15 <= 21'd0; case (roundrobin1_grant) default: begin - rhs_array_muxed15 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed16 = 1'd0; + rhs_array_muxed16 <= 1'd0; case (roundrobin1_grant) default: begin - rhs_array_muxed16 = soc_user_port_cmd_payload_we; + rhs_array_muxed16 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed17 = 1'd0; + rhs_array_muxed17 <= 1'd0; case (roundrobin1_grant) default: begin - rhs_array_muxed17 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed18 = 21'd0; + rhs_array_muxed18 <= 21'd0; case (roundrobin2_grant) default: begin - rhs_array_muxed18 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed19 = 1'd0; + rhs_array_muxed19 <= 1'd0; case (roundrobin2_grant) default: begin - rhs_array_muxed19 = soc_user_port_cmd_payload_we; + rhs_array_muxed19 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed20 = 1'd0; + rhs_array_muxed20 <= 1'd0; case (roundrobin2_grant) default: begin - rhs_array_muxed20 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed21 = 21'd0; + rhs_array_muxed21 <= 21'd0; case (roundrobin3_grant) default: begin - rhs_array_muxed21 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed22 = 1'd0; + rhs_array_muxed22 <= 1'd0; case (roundrobin3_grant) default: begin - rhs_array_muxed22 = soc_user_port_cmd_payload_we; + rhs_array_muxed22 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed23 = 1'd0; + rhs_array_muxed23 <= 1'd0; case (roundrobin3_grant) default: begin - rhs_array_muxed23 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed24 = 21'd0; + rhs_array_muxed24 <= 21'd0; case (roundrobin4_grant) default: begin - rhs_array_muxed24 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed25 = 1'd0; + rhs_array_muxed25 <= 1'd0; case (roundrobin4_grant) default: begin - rhs_array_muxed25 = soc_user_port_cmd_payload_we; + rhs_array_muxed25 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed26 = 1'd0; + rhs_array_muxed26 <= 1'd0; case (roundrobin4_grant) default: begin - rhs_array_muxed26 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed27 = 21'd0; + rhs_array_muxed27 <= 21'd0; case (roundrobin5_grant) default: begin - rhs_array_muxed27 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed28 = 1'd0; + rhs_array_muxed28 <= 1'd0; case (roundrobin5_grant) default: begin - rhs_array_muxed28 = soc_user_port_cmd_payload_we; + rhs_array_muxed28 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed29 = 1'd0; + rhs_array_muxed29 <= 1'd0; case (roundrobin5_grant) default: begin - rhs_array_muxed29 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed30 = 21'd0; + rhs_array_muxed30 <= 21'd0; case (roundrobin6_grant) default: begin - rhs_array_muxed30 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed31 = 1'd0; + rhs_array_muxed31 <= 1'd0; case (roundrobin6_grant) default: begin - rhs_array_muxed31 = soc_user_port_cmd_payload_we; + rhs_array_muxed31 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed32 = 1'd0; + rhs_array_muxed32 <= 1'd0; case (roundrobin6_grant) default: begin - rhs_array_muxed32 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - rhs_array_muxed33 = 21'd0; + rhs_array_muxed33 <= 21'd0; case (roundrobin7_grant) default: begin - rhs_array_muxed33 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin - rhs_array_muxed34 = 1'd0; + rhs_array_muxed34 <= 1'd0; case (roundrobin7_grant) default: begin - rhs_array_muxed34 = soc_user_port_cmd_payload_we; + rhs_array_muxed34 <= soc_user_port_cmd_payload_we; end endcase end always @(*) begin - rhs_array_muxed35 = 1'd0; + rhs_array_muxed35 <= 1'd0; case (roundrobin7_grant) default: begin - rhs_array_muxed35 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); end endcase end always @(*) begin - array_muxed0 = 3'd0; + array_muxed0 <= 3'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed0 = soc_litedramcore_nop_ba[2:0]; + array_muxed0 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed0 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed0 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed0 = soc_litedramcore_cmd_payload_ba[2:0]; + array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed1 = 14'd0; + array_muxed1 <= 14'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed1 = soc_litedramcore_nop_a; + array_muxed1 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed1 = soc_litedramcore_choose_cmd_cmd_payload_a; + array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed1 = soc_litedramcore_choose_req_cmd_payload_a; + array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed1 = soc_litedramcore_cmd_payload_a; + array_muxed1 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed2 = 1'd0; + array_muxed2 <= 1'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed2 = 1'd0; + array_muxed2 <= 1'd0; end 1'd1: begin - array_muxed2 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed2 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed2 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed3 = 1'd0; + array_muxed3 <= 1'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed3 = 1'd0; + array_muxed3 <= 1'd0; end 1'd1: begin - array_muxed3 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed3 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed3 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed4 = 1'd0; + array_muxed4 <= 1'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed4 = 1'd0; + array_muxed4 <= 1'd0; end 1'd1: begin - array_muxed4 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed4 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed4 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed5 = 1'd0; + array_muxed5 <= 1'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed5 = 1'd0; + array_muxed5 <= 1'd0; end 1'd1: begin - array_muxed5 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed5 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed5 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed6 = 1'd0; + array_muxed6 <= 1'd0; case (soc_litedramcore_steerer_sel0) 1'd0: begin - array_muxed6 = 1'd0; + array_muxed6 <= 1'd0; end 1'd1: begin - array_muxed6 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed6 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed6 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed7 = 3'd0; + array_muxed7 <= 3'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed7 = soc_litedramcore_nop_ba[2:0]; + array_muxed7 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed7 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed7 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed7 = soc_litedramcore_cmd_payload_ba[2:0]; + array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed8 = 14'd0; + array_muxed8 <= 14'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed8 = soc_litedramcore_nop_a; + array_muxed8 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed8 = soc_litedramcore_choose_cmd_cmd_payload_a; + array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed8 = soc_litedramcore_choose_req_cmd_payload_a; + array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed8 = soc_litedramcore_cmd_payload_a; + array_muxed8 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed9 = 1'd0; + array_muxed9 <= 1'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed9 = 1'd0; + array_muxed9 <= 1'd0; end 1'd1: begin - array_muxed9 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed9 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed9 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed10 = 1'd0; + array_muxed10 <= 1'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed10 = 1'd0; + array_muxed10 <= 1'd0; end 1'd1: begin - array_muxed10 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed10 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed10 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed11 = 1'd0; + array_muxed11 <= 1'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed11 = 1'd0; + array_muxed11 <= 1'd0; end 1'd1: begin - array_muxed11 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed11 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed11 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed12 = 1'd0; + array_muxed12 <= 1'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed12 = 1'd0; + array_muxed12 <= 1'd0; end 1'd1: begin - array_muxed12 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed12 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed12 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed13 = 1'd0; + array_muxed13 <= 1'd0; case (soc_litedramcore_steerer_sel1) 1'd0: begin - array_muxed13 = 1'd0; + array_muxed13 <= 1'd0; end 1'd1: begin - array_muxed13 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed13 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed13 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed14 = 3'd0; + array_muxed14 <= 3'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed14 = soc_litedramcore_nop_ba[2:0]; + array_muxed14 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed14 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed14 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed14 = soc_litedramcore_cmd_payload_ba[2:0]; + array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed15 = 14'd0; + array_muxed15 <= 14'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed15 = soc_litedramcore_nop_a; + array_muxed15 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed15 = soc_litedramcore_choose_cmd_cmd_payload_a; + array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed15 = soc_litedramcore_choose_req_cmd_payload_a; + array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed15 = soc_litedramcore_cmd_payload_a; + array_muxed15 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed16 = 1'd0; + array_muxed16 <= 1'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed16 = 1'd0; + array_muxed16 <= 1'd0; end 1'd1: begin - array_muxed16 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed16 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed16 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed17 = 1'd0; + array_muxed17 <= 1'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed17 = 1'd0; + array_muxed17 <= 1'd0; end 1'd1: begin - array_muxed17 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed17 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed17 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed18 = 1'd0; + array_muxed18 <= 1'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed18 = 1'd0; + array_muxed18 <= 1'd0; end 1'd1: begin - array_muxed18 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed18 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed18 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed19 = 1'd0; + array_muxed19 <= 1'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed19 = 1'd0; + array_muxed19 <= 1'd0; end 1'd1: begin - array_muxed19 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed19 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed19 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed20 = 1'd0; + array_muxed20 <= 1'd0; case (soc_litedramcore_steerer_sel2) 1'd0: begin - array_muxed20 = 1'd0; + array_muxed20 <= 1'd0; end 1'd1: begin - array_muxed20 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed20 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed20 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end always @(*) begin - array_muxed21 = 3'd0; + array_muxed21 <= 3'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed21 = soc_litedramcore_nop_ba[2:0]; + array_muxed21 <= soc_litedramcore_nop_ba[2:0]; end 1'd1: begin - array_muxed21 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin - array_muxed21 = soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin - array_muxed21 = soc_litedramcore_cmd_payload_ba[2:0]; + array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin - array_muxed22 = 14'd0; + array_muxed22 <= 14'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed22 = soc_litedramcore_nop_a; + array_muxed22 <= soc_litedramcore_nop_a; end 1'd1: begin - array_muxed22 = soc_litedramcore_choose_cmd_cmd_payload_a; + array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin - array_muxed22 = soc_litedramcore_choose_req_cmd_payload_a; + array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; end default: begin - array_muxed22 = soc_litedramcore_cmd_payload_a; + array_muxed22 <= soc_litedramcore_cmd_payload_a; end endcase end always @(*) begin - array_muxed23 = 1'd0; + array_muxed23 <= 1'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed23 = 1'd0; + array_muxed23 <= 1'd0; end 1'd1: begin - array_muxed23 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin - array_muxed23 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); end default: begin - array_muxed23 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); end endcase end always @(*) begin - array_muxed24 = 1'd0; + array_muxed24 <= 1'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed24 = 1'd0; + array_muxed24 <= 1'd0; end 1'd1: begin - array_muxed24 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin - array_muxed24 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); end default: begin - array_muxed24 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); end endcase end always @(*) begin - array_muxed25 = 1'd0; + array_muxed25 <= 1'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed25 = 1'd0; + array_muxed25 <= 1'd0; end 1'd1: begin - array_muxed25 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin - array_muxed25 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); end default: begin - array_muxed25 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); end endcase end always @(*) begin - array_muxed26 = 1'd0; + array_muxed26 <= 1'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed26 = 1'd0; + array_muxed26 <= 1'd0; end 1'd1: begin - array_muxed26 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin - array_muxed26 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); end default: begin - array_muxed26 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); end endcase end always @(*) begin - array_muxed27 = 1'd0; + array_muxed27 <= 1'd0; case (soc_litedramcore_steerer_sel3) 1'd0: begin - array_muxed27 = 1'd0; + array_muxed27 <= 1'd0; end 1'd1: begin - array_muxed27 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin - array_muxed27 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); end default: begin - array_muxed27 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); end endcase end + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge por_clk) begin soc_int_rst <= 1'd0; end @@ -13413,154 +12941,70 @@ always @(posedge sys_clk) begin interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; end 3'd4: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; end 3'd5: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; end 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w; end 3'd7: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; end 4'd8: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w; + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; end 4'd10: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; end 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; end 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w; end 4'd13: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; end 4'd14: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; end 5'd16: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; end 5'd17: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; end 5'd18: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w; end 5'd19: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w; - end - 5'd20: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w; - end - 5'd21: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w; - end - 5'd22: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; - end - 5'd23: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w; - end - 5'd24: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w; - end - 5'd25: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w; - end - 5'd26: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w; - end - 5'd27: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; - end - 5'd28: begin - interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w; - end - 5'd30: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; - end - 5'd31: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; - end - 6'd32: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w; - end - 6'd33: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w; - end - 6'd34: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w; - end - 6'd35: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; - end - 6'd36: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w; - end - 6'd37: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w; - end - 6'd38: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w; - end - 6'd39: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w; - end - 6'd40: begin interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; end - 6'd45: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w; - end - 6'd46: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w; - end - 6'd47: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; end - 6'd49: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w; - end - 6'd50: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w; - end - 6'd51: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w; - end - 6'd52: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w; + 5'd24: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w; end endcase end @@ -13572,118 +13016,70 @@ always @(posedge sys_clk) begin soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; end soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; - if (csrbank1_dfii_pi0_address1_re) begin - soc_litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r; - end if (csrbank1_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r; + soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; end soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; if (csrbank1_dfii_pi0_baddress0_re) begin soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; end soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; - if (csrbank1_dfii_pi0_wrdata3_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r; - end - if (csrbank1_dfii_pi0_wrdata2_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r; - end - if (csrbank1_dfii_pi0_wrdata1_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r; - end if (csrbank1_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r; + soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; end soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; - soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata0_re; + soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re; if (csrbank1_dfii_pi1_command0_re) begin soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; end soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; - if (csrbank1_dfii_pi1_address1_re) begin - soc_litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r; - end if (csrbank1_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r; + soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; end soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; if (csrbank1_dfii_pi1_baddress0_re) begin soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; end soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; - if (csrbank1_dfii_pi1_wrdata3_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r; - end - if (csrbank1_dfii_pi1_wrdata2_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r; - end - if (csrbank1_dfii_pi1_wrdata1_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r; - end if (csrbank1_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r; + soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; end soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; - soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata0_re; + soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re; if (csrbank1_dfii_pi2_command0_re) begin soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; end soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; - if (csrbank1_dfii_pi2_address1_re) begin - soc_litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r; - end if (csrbank1_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r; + soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; end soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; if (csrbank1_dfii_pi2_baddress0_re) begin soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; end soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; - if (csrbank1_dfii_pi2_wrdata3_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r; - end - if (csrbank1_dfii_pi2_wrdata2_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r; - end - if (csrbank1_dfii_pi2_wrdata1_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r; - end if (csrbank1_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r; + soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; end soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; - soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata0_re; + soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re; if (csrbank1_dfii_pi3_command0_re) begin soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; end soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; - if (csrbank1_dfii_pi3_address1_re) begin - soc_litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r; - end if (csrbank1_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r; + soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; end soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; if (csrbank1_dfii_pi3_baddress0_re) begin soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; end soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; - if (csrbank1_dfii_pi3_wrdata3_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r; - end - if (csrbank1_dfii_pi3_wrdata2_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r; - end - if (csrbank1_dfii_pi3_wrdata1_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r; - end if (csrbank1_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r; + soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; end soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; - soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata0_re; + soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re; if (sys_rst) begin soc_ddrphy_bankmodel0_active <= 1'd0; soc_ddrphy_bankmodel0_row <= 14'd0; @@ -13963,8 +13359,18 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory mem: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem[0:2097151]; -reg [20:0] memadr; +reg [20:0] mem_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel0_write_port_we[0]) mem[soc_ddrphy_bankmodel0_write_port_adr][7:0] <= soc_ddrphy_bankmodel0_write_port_dat_w[7:0]; @@ -13998,17 +13404,21 @@ always @(posedge sys_clk) begin mem[soc_ddrphy_bankmodel0_write_port_adr][119:112] <= soc_ddrphy_bankmodel0_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel0_write_port_we[15]) mem[soc_ddrphy_bankmodel0_write_port_adr][127:120] <= soc_ddrphy_bankmodel0_write_port_dat_w[127:120]; - memadr <= soc_ddrphy_bankmodel0_write_port_adr; + mem_adr0 <= soc_ddrphy_bankmodel0_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[memadr]; +assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[mem_adr0]; assign soc_ddrphy_bankmodel0_read_port_dat_r = mem[soc_ddrphy_bankmodel0_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_1: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_1[0:2097151]; -reg [20:0] memadr_1; +reg [20:0] mem_1_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel1_write_port_we[0]) mem_1[soc_ddrphy_bankmodel1_write_port_adr][7:0] <= soc_ddrphy_bankmodel1_write_port_dat_w[7:0]; @@ -14042,17 +13452,21 @@ always @(posedge sys_clk) begin mem_1[soc_ddrphy_bankmodel1_write_port_adr][119:112] <= soc_ddrphy_bankmodel1_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel1_write_port_we[15]) mem_1[soc_ddrphy_bankmodel1_write_port_adr][127:120] <= soc_ddrphy_bankmodel1_write_port_dat_w[127:120]; - memadr_1 <= soc_ddrphy_bankmodel1_write_port_adr; + mem_1_adr0 <= soc_ddrphy_bankmodel1_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1]; +assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[mem_1_adr0]; assign soc_ddrphy_bankmodel1_read_port_dat_r = mem_1[soc_ddrphy_bankmodel1_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_2: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_2[0:2097151]; -reg [20:0] memadr_2; +reg [20:0] mem_2_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel2_write_port_we[0]) mem_2[soc_ddrphy_bankmodel2_write_port_adr][7:0] <= soc_ddrphy_bankmodel2_write_port_dat_w[7:0]; @@ -14086,17 +13500,21 @@ always @(posedge sys_clk) begin mem_2[soc_ddrphy_bankmodel2_write_port_adr][119:112] <= soc_ddrphy_bankmodel2_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel2_write_port_we[15]) mem_2[soc_ddrphy_bankmodel2_write_port_adr][127:120] <= soc_ddrphy_bankmodel2_write_port_dat_w[127:120]; - memadr_2 <= soc_ddrphy_bankmodel2_write_port_adr; + mem_2_adr0 <= soc_ddrphy_bankmodel2_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2]; +assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[mem_2_adr0]; assign soc_ddrphy_bankmodel2_read_port_dat_r = mem_2[soc_ddrphy_bankmodel2_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_3: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_3[0:2097151]; -reg [20:0] memadr_3; +reg [20:0] mem_3_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel3_write_port_we[0]) mem_3[soc_ddrphy_bankmodel3_write_port_adr][7:0] <= soc_ddrphy_bankmodel3_write_port_dat_w[7:0]; @@ -14130,17 +13548,21 @@ always @(posedge sys_clk) begin mem_3[soc_ddrphy_bankmodel3_write_port_adr][119:112] <= soc_ddrphy_bankmodel3_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel3_write_port_we[15]) mem_3[soc_ddrphy_bankmodel3_write_port_adr][127:120] <= soc_ddrphy_bankmodel3_write_port_dat_w[127:120]; - memadr_3 <= soc_ddrphy_bankmodel3_write_port_adr; + mem_3_adr0 <= soc_ddrphy_bankmodel3_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3]; +assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[mem_3_adr0]; assign soc_ddrphy_bankmodel3_read_port_dat_r = mem_3[soc_ddrphy_bankmodel3_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_4: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_4[0:2097151]; -reg [20:0] memadr_4; +reg [20:0] mem_4_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel4_write_port_we[0]) mem_4[soc_ddrphy_bankmodel4_write_port_adr][7:0] <= soc_ddrphy_bankmodel4_write_port_dat_w[7:0]; @@ -14174,17 +13596,21 @@ always @(posedge sys_clk) begin mem_4[soc_ddrphy_bankmodel4_write_port_adr][119:112] <= soc_ddrphy_bankmodel4_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel4_write_port_we[15]) mem_4[soc_ddrphy_bankmodel4_write_port_adr][127:120] <= soc_ddrphy_bankmodel4_write_port_dat_w[127:120]; - memadr_4 <= soc_ddrphy_bankmodel4_write_port_adr; + mem_4_adr0 <= soc_ddrphy_bankmodel4_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4]; +assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[mem_4_adr0]; assign soc_ddrphy_bankmodel4_read_port_dat_r = mem_4[soc_ddrphy_bankmodel4_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_5: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_5[0:2097151]; -reg [20:0] memadr_5; +reg [20:0] mem_5_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel5_write_port_we[0]) mem_5[soc_ddrphy_bankmodel5_write_port_adr][7:0] <= soc_ddrphy_bankmodel5_write_port_dat_w[7:0]; @@ -14218,17 +13644,21 @@ always @(posedge sys_clk) begin mem_5[soc_ddrphy_bankmodel5_write_port_adr][119:112] <= soc_ddrphy_bankmodel5_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel5_write_port_we[15]) mem_5[soc_ddrphy_bankmodel5_write_port_adr][127:120] <= soc_ddrphy_bankmodel5_write_port_dat_w[127:120]; - memadr_5 <= soc_ddrphy_bankmodel5_write_port_adr; + mem_5_adr0 <= soc_ddrphy_bankmodel5_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5]; +assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[mem_5_adr0]; assign soc_ddrphy_bankmodel5_read_port_dat_r = mem_5[soc_ddrphy_bankmodel5_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_6: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_6[0:2097151]; -reg [20:0] memadr_6; +reg [20:0] mem_6_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel6_write_port_we[0]) mem_6[soc_ddrphy_bankmodel6_write_port_adr][7:0] <= soc_ddrphy_bankmodel6_write_port_dat_w[7:0]; @@ -14262,17 +13692,21 @@ always @(posedge sys_clk) begin mem_6[soc_ddrphy_bankmodel6_write_port_adr][119:112] <= soc_ddrphy_bankmodel6_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel6_write_port_we[15]) mem_6[soc_ddrphy_bankmodel6_write_port_adr][127:120] <= soc_ddrphy_bankmodel6_write_port_dat_w[127:120]; - memadr_6 <= soc_ddrphy_bankmodel6_write_port_adr; + mem_6_adr0 <= soc_ddrphy_bankmodel6_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6]; +assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[mem_6_adr0]; assign soc_ddrphy_bankmodel6_read_port_dat_r = mem_6[soc_ddrphy_bankmodel6_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory mem_7: 2097152-words x 128-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +// Port 1 | Read: Async | Write: ---- | reg [127:0] mem_7[0:2097151]; -reg [20:0] memadr_7; +reg [20:0] mem_7_adr0; always @(posedge sys_clk) begin if (soc_ddrphy_bankmodel7_write_port_we[0]) mem_7[soc_ddrphy_bankmodel7_write_port_adr][7:0] <= soc_ddrphy_bankmodel7_write_port_dat_w[7:0]; @@ -14306,125 +13740,160 @@ always @(posedge sys_clk) begin mem_7[soc_ddrphy_bankmodel7_write_port_adr][119:112] <= soc_ddrphy_bankmodel7_write_port_dat_w[119:112]; if (soc_ddrphy_bankmodel7_write_port_we[15]) mem_7[soc_ddrphy_bankmodel7_write_port_adr][127:120] <= soc_ddrphy_bankmodel7_write_port_dat_w[127:120]; - memadr_7 <= soc_ddrphy_bankmodel7_write_port_adr; + mem_7_adr0 <= soc_ddrphy_bankmodel7_write_port_adr; end - always @(posedge sys_clk) begin end - -assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7]; +assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[mem_7_adr0]; assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_port_adr]; + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage[0:15]; -reg [23:0] memdat; +reg [23:0] storage_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + storage_dat0 <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_1[0:15]; -reg [23:0] memdat_1; +reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_2[0:15]; -reg [23:0] memdat_2; +reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_3[0:15]; -reg [23:0] memdat_3; +reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_4[0:15]; -reg [23:0] memdat_4; +reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_5[0:15]; -reg [23:0] memdat_5; +reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_6[0:15]; -reg [23:0] memdat_6; +reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_7[0:15]; -reg [23:0] memdat_7; +reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 08:32:16. +//------------------------------------------------------------------------------ diff --git a/litedram/generated/wukong-v2/litedram-initmem.vhdl b/litedram/generated/wukong-v2/litedram-initmem.vhdl index 395602b..231249e 100644 --- a/litedram/generated/wukong-v2/litedram-initmem.vhdl +++ b/litedram/generated/wukong-v2/litedram-initmem.vhdl @@ -100,7 +100,7 @@ begin if rising_edge(clk) then oack <= '0'; if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0)))); if wb_in.we = '0' then obuf <= init_ram(adr); else diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init index 5b1a383..1b6e88e 100644 --- a/litedram/generated/wukong-v2/litedram_core.init +++ b/litedram/generated/wukong-v2/litedram_core.init @@ -518,7 +518,7 @@ a64b5a7d14004a39 4e80002060000000 0000000000000000 3c4c000100000000 -7c0802a63842afc4 +7c0802a63842adc4 fbe1fff8fbc1fff0 f821ff51f8010010 f88100d83bc10020 @@ -527,96 +527,97 @@ f8c100e87c651b78 38c100d87fc3f378 f90100f8f8e100f0 f9410108f9210100 -600000004800245d +6000000048002159 7fc3f3787c7f1b78 -6000000048001e69 +6000000048001b7d 7fe3fb78382100b0 -0000000048002a54 +00000000480027d4 0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842af203c4c0001 +3842ad203c4c0001 7d8000267c0802a6 -9181000848002991 -48001e65f821fed1 +9181000848002711 +48001b79f821fed1 3c62ffff60000000 -4bffff3938637b10 +4bffff3938637a90 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b30 +63ff000838637ab0 3c62ffff4bffff15 -38637b507bff0020 +38637ad07bff0020 7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffee938637b68 +4bfffee938637ae8 4e00000073e90002 3c62ffff41820010 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-0000202d3a64256d -002064253a64256d 76656c2064616552 000a3a676e696c65 696c616974696e49 diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v index 166195f..233a914 100644 --- a/litedram/generated/wukong-v2/litedram_core.v +++ b/litedram/generated/wukong-v2/litedram_core.v @@ -1,9 +1,25 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:40 -//-------------------------------------------------------------------------------- -module litedram_core( - input wire clk, - input wire rst, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litedram_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 08:32:15 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litedram_core ( + input wire clk, + input wire rst, output wire pll_locked, output wire [13:0] ddram_a, output wire [2:0] ddram_ba, @@ -12,9 +28,9 @@ module litedram_core( output wire ddram_we_n, output wire ddram_cs_n, output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, @@ -22,32 +38,38 @@ module litedram_core( output wire ddram_reset_n, output wire init_done, output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, - input wire user_port_native_0_cmd_valid, + input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, + input wire user_port_native_0_rdata_ready, output wire [127:0] user_port_native_0_rdata_data ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_rst = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; @@ -55,7 +77,7 @@ wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; wire main_reset; -reg main_power_down = 1'd0; +reg main_power_down = 1'd0; wire main_locked; wire main_clkin; wire main_clkout0; @@ -66,48 +88,48 @@ wire main_clkout2; wire main_clkout_buf2; wire main_clkout3; wire main_clkout_buf3; -reg [3:0] main_reset_counter = 4'd15; -reg main_ic_reset = 1'd1; -reg main_a7ddrphy_rst_storage = 1'd0; -reg main_a7ddrphy_rst_re = 1'd0; -reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; -reg main_a7ddrphy_wlevel_en_storage = 1'd0; -reg main_a7ddrphy_wlevel_en_re = 1'd0; -reg main_a7ddrphy_wlevel_strobe_re = 1'd0; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg main_a7ddrphy_rst_storage = 1'd0; +reg main_a7ddrphy_rst_re = 1'd0; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +reg main_a7ddrphy_wlevel_en_storage = 1'd0; +reg main_a7ddrphy_wlevel_en_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_re = 1'd0; wire main_a7ddrphy_wlevel_strobe_r; -reg main_a7ddrphy_wlevel_strobe_we = 1'd0; -reg main_a7ddrphy_wlevel_strobe_w = 1'd0; -reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; -reg main_a7ddrphy_dly_sel_re = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; +reg main_a7ddrphy_wlevel_strobe_we = 1'd0; +reg main_a7ddrphy_wlevel_strobe_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_rst_r; -reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_re = 1'd0; wire main_a7ddrphy_rdly_dq_inc_r; -reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; -reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_we = 1'd0; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_rst_r; -reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_rdly_dq_bitslip_r; -reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_rst_r; -reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0; wire main_a7ddrphy_wdly_dq_bitslip_r; -reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; -reg main_a7ddrphy_rdphase_re = 1'd0; -reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; -reg main_a7ddrphy_wrphase_re = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2; +reg main_a7ddrphy_rdphase_re = 1'd0; +reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3; +reg main_a7ddrphy_wrphase_re = 1'd0; wire [13:0] main_a7ddrphy_dfi_p0_address; wire [2:0] main_a7ddrphy_dfi_p0_bank; wire main_a7ddrphy_dfi_p0_cas_n; @@ -122,7 +144,7 @@ wire [31:0] main_a7ddrphy_dfi_p0_wrdata; wire main_a7ddrphy_dfi_p0_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; wire main_a7ddrphy_dfi_p0_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; wire main_a7ddrphy_dfi_p0_rddata_valid; wire [13:0] main_a7ddrphy_dfi_p1_address; wire [2:0] main_a7ddrphy_dfi_p1_bank; @@ -138,7 +160,7 @@ wire [31:0] main_a7ddrphy_dfi_p1_wrdata; wire main_a7ddrphy_dfi_p1_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; wire main_a7ddrphy_dfi_p1_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; wire main_a7ddrphy_dfi_p1_rddata_valid; wire [13:0] main_a7ddrphy_dfi_p2_address; wire [2:0] main_a7ddrphy_dfi_p2_bank; @@ -154,7 +176,7 @@ wire [31:0] main_a7ddrphy_dfi_p2_wrdata; wire main_a7ddrphy_dfi_p2_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; wire main_a7ddrphy_dfi_p2_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; wire main_a7ddrphy_dfi_p2_rddata_valid; wire [13:0] main_a7ddrphy_dfi_p3_address; wire [2:0] main_a7ddrphy_dfi_p3_bank; @@ -170,292 +192,292 @@ wire [31:0] main_a7ddrphy_dfi_p3_wrdata; wire main_a7ddrphy_dfi_p3_wrdata_en; wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; wire main_a7ddrphy_dfi_p3_rddata_en; -reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; wire main_a7ddrphy_dfi_p3_rddata_valid; wire main_a7ddrphy_sd_clk_se_nodelay; -reg main_a7ddrphy_dqs_oe = 1'd0; +reg main_a7ddrphy_dqs_oe = 1'd0; wire main_a7ddrphy_dqs_preamble; wire main_a7ddrphy_dqs_postamble; wire main_a7ddrphy_dqs_oe_delay_tappeddelayline; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_dqspattern0 = 1'd0; -reg main_a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dqspattern0 = 1'd0; +reg main_a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0; wire main_a7ddrphy_dqs_o_no_delay0; wire main_a7ddrphy_dqs_t0; -reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip00 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0; wire main_a7ddrphy0; wire main_a7ddrphy_dqs_o_no_delay1; wire main_a7ddrphy_dqs_t1; -reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip10 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0; wire main_a7ddrphy1; -reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip01 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip11 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0; wire main_a7ddrphy_dq_oe; wire main_a7ddrphy_dq_oe_delay_tappeddelayline; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire main_a7ddrphy_dq_o_nodelay0; wire main_a7ddrphy_dq_i_nodelay0; wire main_a7ddrphy_dq_i_delayed0; wire main_a7ddrphy_dq_t0; -reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip02 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip03; -reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip04 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay1; wire main_a7ddrphy_dq_i_nodelay1; wire main_a7ddrphy_dq_i_delayed1; wire main_a7ddrphy_dq_t1; -reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip12 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] main_a7ddrphy_bitslip13; -reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip14 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0; wire main_a7ddrphy_dq_o_nodelay2; wire main_a7ddrphy_dq_i_nodelay2; wire main_a7ddrphy_dq_i_delayed2; wire main_a7ddrphy_dq_t2; -reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip20 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip21; -reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip22 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay3; wire main_a7ddrphy_dq_i_nodelay3; wire main_a7ddrphy_dq_i_delayed3; wire main_a7ddrphy_dq_t3; -reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip30 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip31; -reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip32 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay4; wire main_a7ddrphy_dq_i_nodelay4; wire main_a7ddrphy_dq_i_delayed4; wire main_a7ddrphy_dq_t4; -reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip40 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip41; -reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip42 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay5; wire main_a7ddrphy_dq_i_nodelay5; wire main_a7ddrphy_dq_i_delayed5; wire main_a7ddrphy_dq_t5; -reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip50 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip51; -reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip52 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay6; wire main_a7ddrphy_dq_i_nodelay6; wire main_a7ddrphy_dq_i_delayed6; wire main_a7ddrphy_dq_t6; -reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip60 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip61; -reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip62 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay7; wire main_a7ddrphy_dq_i_nodelay7; wire main_a7ddrphy_dq_i_delayed7; wire main_a7ddrphy_dq_t7; -reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip70 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip71; -reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip72 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay8; wire main_a7ddrphy_dq_i_nodelay8; wire main_a7ddrphy_dq_i_delayed8; wire main_a7ddrphy_dq_t8; -reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip80 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip81; -reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip82 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay9; wire main_a7ddrphy_dq_i_nodelay9; wire main_a7ddrphy_dq_i_delayed9; wire main_a7ddrphy_dq_t9; -reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip90 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip91; -reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip92 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay10; wire main_a7ddrphy_dq_i_nodelay10; wire main_a7ddrphy_dq_i_delayed10; wire main_a7ddrphy_dq_t10; -reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip100 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip101; -reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip102 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay11; wire main_a7ddrphy_dq_i_nodelay11; wire main_a7ddrphy_dq_i_delayed11; wire main_a7ddrphy_dq_t11; -reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip110 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip111; -reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip112 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay12; wire main_a7ddrphy_dq_i_nodelay12; wire main_a7ddrphy_dq_i_delayed12; wire main_a7ddrphy_dq_t12; -reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip120 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip121; -reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip122 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay13; wire main_a7ddrphy_dq_i_nodelay13; wire main_a7ddrphy_dq_i_delayed13; wire main_a7ddrphy_dq_t13; -reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip130 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip131; -reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip132 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay14; wire main_a7ddrphy_dq_i_nodelay14; wire main_a7ddrphy_dq_i_delayed14; wire main_a7ddrphy_dq_t14; -reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip140 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip141; -reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip142 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0; wire main_a7ddrphy_dq_o_nodelay15; wire main_a7ddrphy_dq_i_nodelay15; wire main_a7ddrphy_dq_i_delayed15; wire main_a7ddrphy_dq_t15; -reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; +reg [7:0] main_a7ddrphy_bitslip150 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] main_a7ddrphy_bitslip151; -reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; -reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg [7:0] main_a7ddrphy_bitslip152 = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [13:0] main_litedramcore_inti_p0_address; wire [2:0] main_litedramcore_inti_p0_bank; -reg main_litedramcore_inti_p0_cas_n = 1'd1; -reg main_litedramcore_inti_p0_cs_n = 1'd1; -reg main_litedramcore_inti_p0_ras_n = 1'd1; -reg main_litedramcore_inti_p0_we_n = 1'd1; +reg main_litedramcore_inti_p0_cas_n = 1'd1; +reg main_litedramcore_inti_p0_cs_n = 1'd1; +reg main_litedramcore_inti_p0_ras_n = 1'd1; +reg main_litedramcore_inti_p0_we_n = 1'd1; wire main_litedramcore_inti_p0_cke; wire main_litedramcore_inti_p0_odt; wire main_litedramcore_inti_p0_reset_n; -reg main_litedramcore_inti_p0_act_n = 1'd1; +reg main_litedramcore_inti_p0_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p0_wrdata; wire main_litedramcore_inti_p0_wrdata_en; wire [3:0] main_litedramcore_inti_p0_wrdata_mask; wire main_litedramcore_inti_p0_rddata_en; -reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; -reg main_litedramcore_inti_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0; +reg main_litedramcore_inti_p0_rddata_valid = 1'd0; wire [13:0] main_litedramcore_inti_p1_address; wire [2:0] main_litedramcore_inti_p1_bank; -reg main_litedramcore_inti_p1_cas_n = 1'd1; -reg main_litedramcore_inti_p1_cs_n = 1'd1; -reg main_litedramcore_inti_p1_ras_n = 1'd1; -reg main_litedramcore_inti_p1_we_n = 1'd1; +reg main_litedramcore_inti_p1_cas_n = 1'd1; +reg main_litedramcore_inti_p1_cs_n = 1'd1; +reg main_litedramcore_inti_p1_ras_n = 1'd1; +reg main_litedramcore_inti_p1_we_n = 1'd1; wire main_litedramcore_inti_p1_cke; wire main_litedramcore_inti_p1_odt; wire main_litedramcore_inti_p1_reset_n; -reg main_litedramcore_inti_p1_act_n = 1'd1; +reg main_litedramcore_inti_p1_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p1_wrdata; wire main_litedramcore_inti_p1_wrdata_en; wire [3:0] main_litedramcore_inti_p1_wrdata_mask; wire main_litedramcore_inti_p1_rddata_en; -reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; -reg main_litedramcore_inti_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0; +reg main_litedramcore_inti_p1_rddata_valid = 1'd0; wire [13:0] main_litedramcore_inti_p2_address; wire [2:0] main_litedramcore_inti_p2_bank; -reg main_litedramcore_inti_p2_cas_n = 1'd1; -reg main_litedramcore_inti_p2_cs_n = 1'd1; -reg main_litedramcore_inti_p2_ras_n = 1'd1; -reg main_litedramcore_inti_p2_we_n = 1'd1; +reg main_litedramcore_inti_p2_cas_n = 1'd1; +reg main_litedramcore_inti_p2_cs_n = 1'd1; +reg main_litedramcore_inti_p2_ras_n = 1'd1; +reg main_litedramcore_inti_p2_we_n = 1'd1; wire main_litedramcore_inti_p2_cke; wire main_litedramcore_inti_p2_odt; wire main_litedramcore_inti_p2_reset_n; -reg main_litedramcore_inti_p2_act_n = 1'd1; +reg main_litedramcore_inti_p2_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p2_wrdata; wire main_litedramcore_inti_p2_wrdata_en; wire [3:0] main_litedramcore_inti_p2_wrdata_mask; wire main_litedramcore_inti_p2_rddata_en; -reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; -reg main_litedramcore_inti_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0; +reg main_litedramcore_inti_p2_rddata_valid = 1'd0; wire [13:0] main_litedramcore_inti_p3_address; wire [2:0] main_litedramcore_inti_p3_bank; -reg main_litedramcore_inti_p3_cas_n = 1'd1; -reg main_litedramcore_inti_p3_cs_n = 1'd1; -reg main_litedramcore_inti_p3_ras_n = 1'd1; -reg main_litedramcore_inti_p3_we_n = 1'd1; +reg main_litedramcore_inti_p3_cas_n = 1'd1; +reg main_litedramcore_inti_p3_cs_n = 1'd1; +reg main_litedramcore_inti_p3_ras_n = 1'd1; +reg main_litedramcore_inti_p3_we_n = 1'd1; wire main_litedramcore_inti_p3_cke; wire main_litedramcore_inti_p3_odt; wire main_litedramcore_inti_p3_reset_n; -reg main_litedramcore_inti_p3_act_n = 1'd1; +reg main_litedramcore_inti_p3_act_n = 1'd1; wire [31:0] main_litedramcore_inti_p3_wrdata; wire main_litedramcore_inti_p3_wrdata_en; wire [3:0] main_litedramcore_inti_p3_wrdata_mask; wire main_litedramcore_inti_p3_rddata_en; -reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; -reg main_litedramcore_inti_p3_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0; +reg main_litedramcore_inti_p3_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p0_address; wire [2:0] main_litedramcore_slave_p0_bank; wire main_litedramcore_slave_p0_cas_n; @@ -470,8 +492,8 @@ wire [31:0] main_litedramcore_slave_p0_wrdata; wire main_litedramcore_slave_p0_wrdata_en; wire [3:0] main_litedramcore_slave_p0_wrdata_mask; wire main_litedramcore_slave_p0_rddata_en; -reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; -reg main_litedramcore_slave_p0_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0; +reg main_litedramcore_slave_p0_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p1_address; wire [2:0] main_litedramcore_slave_p1_bank; wire main_litedramcore_slave_p1_cas_n; @@ -486,8 +508,8 @@ wire [31:0] main_litedramcore_slave_p1_wrdata; wire main_litedramcore_slave_p1_wrdata_en; wire [3:0] main_litedramcore_slave_p1_wrdata_mask; wire main_litedramcore_slave_p1_rddata_en; -reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; -reg main_litedramcore_slave_p1_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0; +reg main_litedramcore_slave_p1_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p2_address; wire [2:0] main_litedramcore_slave_p2_bank; wire main_litedramcore_slave_p2_cas_n; @@ -502,8 +524,8 @@ wire [31:0] main_litedramcore_slave_p2_wrdata; wire main_litedramcore_slave_p2_wrdata_en; wire [3:0] main_litedramcore_slave_p2_wrdata_mask; wire main_litedramcore_slave_p2_rddata_en; -reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; -reg main_litedramcore_slave_p2_rddata_valid = 1'd0; +reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0; +reg main_litedramcore_slave_p2_rddata_valid = 1'd0; wire [13:0] main_litedramcore_slave_p3_address; wire [2:0] main_litedramcore_slave_p3_bank; wire main_litedramcore_slave_p3_cas_n; @@ -518,138 +540,138 @@ wire [31:0] main_litedramcore_slave_p3_wrdata; wire main_litedramcore_slave_p3_wrdata_en; wire [3:0] main_litedramcore_slave_p3_wrdata_mask; wire main_litedramcore_slave_p3_rddata_en; -reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; -reg main_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] main_litedramcore_master_p0_address = 14'd0; -reg [2:0] main_litedramcore_master_p0_bank = 3'd0; -reg main_litedramcore_master_p0_cas_n = 1'd1; -reg main_litedramcore_master_p0_cs_n = 1'd1; -reg main_litedramcore_master_p0_ras_n = 1'd1; -reg main_litedramcore_master_p0_we_n = 1'd1; -reg main_litedramcore_master_p0_cke = 1'd0; -reg main_litedramcore_master_p0_odt = 1'd0; -reg main_litedramcore_master_p0_reset_n = 1'd0; -reg main_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; -reg main_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; -reg main_litedramcore_master_p0_rddata_en = 1'd0; +reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0; +reg main_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] main_litedramcore_master_p0_address = 14'd0; +reg [2:0] main_litedramcore_master_p0_bank = 3'd0; +reg main_litedramcore_master_p0_cas_n = 1'd1; +reg main_litedramcore_master_p0_cs_n = 1'd1; +reg main_litedramcore_master_p0_ras_n = 1'd1; +reg main_litedramcore_master_p0_we_n = 1'd1; +reg main_litedramcore_master_p0_cke = 1'd0; +reg main_litedramcore_master_p0_odt = 1'd0; +reg main_litedramcore_master_p0_reset_n = 1'd0; +reg main_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0; +reg main_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0; +reg main_litedramcore_master_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p0_rddata; wire main_litedramcore_master_p0_rddata_valid; -reg [13:0] main_litedramcore_master_p1_address = 14'd0; -reg [2:0] main_litedramcore_master_p1_bank = 3'd0; -reg main_litedramcore_master_p1_cas_n = 1'd1; -reg main_litedramcore_master_p1_cs_n = 1'd1; -reg main_litedramcore_master_p1_ras_n = 1'd1; -reg main_litedramcore_master_p1_we_n = 1'd1; -reg main_litedramcore_master_p1_cke = 1'd0; -reg main_litedramcore_master_p1_odt = 1'd0; -reg main_litedramcore_master_p1_reset_n = 1'd0; -reg main_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; -reg main_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; -reg main_litedramcore_master_p1_rddata_en = 1'd0; +reg [13:0] main_litedramcore_master_p1_address = 14'd0; +reg [2:0] main_litedramcore_master_p1_bank = 3'd0; +reg main_litedramcore_master_p1_cas_n = 1'd1; +reg main_litedramcore_master_p1_cs_n = 1'd1; +reg main_litedramcore_master_p1_ras_n = 1'd1; +reg main_litedramcore_master_p1_we_n = 1'd1; +reg main_litedramcore_master_p1_cke = 1'd0; +reg main_litedramcore_master_p1_odt = 1'd0; +reg main_litedramcore_master_p1_reset_n = 1'd0; +reg main_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0; +reg main_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0; +reg main_litedramcore_master_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p1_rddata; wire main_litedramcore_master_p1_rddata_valid; -reg [13:0] main_litedramcore_master_p2_address = 14'd0; -reg [2:0] main_litedramcore_master_p2_bank = 3'd0; -reg main_litedramcore_master_p2_cas_n = 1'd1; -reg main_litedramcore_master_p2_cs_n = 1'd1; -reg main_litedramcore_master_p2_ras_n = 1'd1; -reg main_litedramcore_master_p2_we_n = 1'd1; -reg main_litedramcore_master_p2_cke = 1'd0; -reg main_litedramcore_master_p2_odt = 1'd0; -reg main_litedramcore_master_p2_reset_n = 1'd0; -reg main_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; -reg main_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; -reg main_litedramcore_master_p2_rddata_en = 1'd0; +reg [13:0] main_litedramcore_master_p2_address = 14'd0; +reg [2:0] main_litedramcore_master_p2_bank = 3'd0; +reg main_litedramcore_master_p2_cas_n = 1'd1; +reg main_litedramcore_master_p2_cs_n = 1'd1; +reg main_litedramcore_master_p2_ras_n = 1'd1; +reg main_litedramcore_master_p2_we_n = 1'd1; +reg main_litedramcore_master_p2_cke = 1'd0; +reg main_litedramcore_master_p2_odt = 1'd0; +reg main_litedramcore_master_p2_reset_n = 1'd0; +reg main_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0; +reg main_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0; +reg main_litedramcore_master_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p2_rddata; wire main_litedramcore_master_p2_rddata_valid; -reg [13:0] main_litedramcore_master_p3_address = 14'd0; -reg [2:0] main_litedramcore_master_p3_bank = 3'd0; -reg main_litedramcore_master_p3_cas_n = 1'd1; -reg main_litedramcore_master_p3_cs_n = 1'd1; -reg main_litedramcore_master_p3_ras_n = 1'd1; -reg main_litedramcore_master_p3_we_n = 1'd1; -reg main_litedramcore_master_p3_cke = 1'd0; -reg main_litedramcore_master_p3_odt = 1'd0; -reg main_litedramcore_master_p3_reset_n = 1'd0; -reg main_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; -reg main_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; -reg main_litedramcore_master_p3_rddata_en = 1'd0; +reg [13:0] main_litedramcore_master_p3_address = 14'd0; +reg [2:0] main_litedramcore_master_p3_bank = 3'd0; +reg main_litedramcore_master_p3_cas_n = 1'd1; +reg main_litedramcore_master_p3_cs_n = 1'd1; +reg main_litedramcore_master_p3_ras_n = 1'd1; +reg main_litedramcore_master_p3_we_n = 1'd1; +reg main_litedramcore_master_p3_cke = 1'd0; +reg main_litedramcore_master_p3_odt = 1'd0; +reg main_litedramcore_master_p3_reset_n = 1'd0; +reg main_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0; +reg main_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0; +reg main_litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_master_p3_rddata; wire main_litedramcore_master_p3_rddata_valid; wire main_litedramcore_sel; wire main_litedramcore_cke; wire main_litedramcore_odt; wire main_litedramcore_reset_n; -reg [3:0] main_litedramcore_storage = 4'd1; -reg main_litedramcore_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; -reg main_litedramcore_phaseinjector0_command_re = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; +reg [3:0] main_litedramcore_storage = 4'd1; +reg main_litedramcore_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0; +reg main_litedramcore_phaseinjector0_command_re = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector0_command_issue_r; -reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; -reg main_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0; +reg main_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0; wire main_litedramcore_phaseinjector0_rddata_we; -reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; -reg main_litedramcore_phaseinjector1_command_re = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector0_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0; +reg main_litedramcore_phaseinjector1_command_re = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector1_command_issue_r; -reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; -reg main_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0; +reg main_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0; wire main_litedramcore_phaseinjector1_rddata_we; -reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; -reg main_litedramcore_phaseinjector2_command_re = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector1_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0; +reg main_litedramcore_phaseinjector2_command_re = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector2_command_issue_r; -reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; -reg main_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0; +reg main_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0; wire main_litedramcore_phaseinjector2_rddata_we; -reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; -reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; -reg main_litedramcore_phaseinjector3_command_re = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; +reg main_litedramcore_phaseinjector2_rddata_re = 1'd0; +reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0; +reg main_litedramcore_phaseinjector3_command_re = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0; wire main_litedramcore_phaseinjector3_command_issue_r; -reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; -reg main_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; +reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0; +reg main_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg main_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0; wire main_litedramcore_phaseinjector3_rddata_we; -reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; +reg main_litedramcore_phaseinjector3_rddata_re = 1'd0; wire main_litedramcore_interface_bank0_valid; wire main_litedramcore_interface_bank0_ready; wire main_litedramcore_interface_bank0_we; @@ -706,131 +728,131 @@ wire [20:0] main_litedramcore_interface_bank7_addr; wire main_litedramcore_interface_bank7_lock; wire main_litedramcore_interface_bank7_wdata_ready; wire main_litedramcore_interface_bank7_rdata_valid; -reg [127:0] main_litedramcore_interface_wdata = 128'd0; -reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; +reg [127:0] main_litedramcore_interface_wdata = 128'd0; +reg [15:0] main_litedramcore_interface_wdata_we = 16'd0; wire [127:0] main_litedramcore_interface_rdata; -reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; -reg main_litedramcore_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_dfi_p0_ras_n = 1'd1; -reg main_litedramcore_dfi_p0_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0; +reg main_litedramcore_dfi_p0_cas_n = 1'd1; +reg main_litedramcore_dfi_p0_cs_n = 1'd1; +reg main_litedramcore_dfi_p0_ras_n = 1'd1; +reg main_litedramcore_dfi_p0_we_n = 1'd1; wire main_litedramcore_dfi_p0_cke; wire main_litedramcore_dfi_p0_odt; wire main_litedramcore_dfi_p0_reset_n; -reg main_litedramcore_dfi_p0_act_n = 1'd1; +reg main_litedramcore_dfi_p0_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p0_wrdata; -reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p0_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p0_wrdata_mask; -reg main_litedramcore_dfi_p0_rddata_en = 1'd0; +reg main_litedramcore_dfi_p0_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p0_rddata; wire main_litedramcore_dfi_p0_rddata_valid; -reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; -reg main_litedramcore_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_dfi_p1_ras_n = 1'd1; -reg main_litedramcore_dfi_p1_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0; +reg main_litedramcore_dfi_p1_cas_n = 1'd1; +reg main_litedramcore_dfi_p1_cs_n = 1'd1; +reg main_litedramcore_dfi_p1_ras_n = 1'd1; +reg main_litedramcore_dfi_p1_we_n = 1'd1; wire main_litedramcore_dfi_p1_cke; wire main_litedramcore_dfi_p1_odt; wire main_litedramcore_dfi_p1_reset_n; -reg main_litedramcore_dfi_p1_act_n = 1'd1; +reg main_litedramcore_dfi_p1_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p1_wrdata; -reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p1_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p1_wrdata_mask; -reg main_litedramcore_dfi_p1_rddata_en = 1'd0; +reg main_litedramcore_dfi_p1_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p1_rddata; wire main_litedramcore_dfi_p1_rddata_valid; -reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; -reg main_litedramcore_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_dfi_p2_ras_n = 1'd1; -reg main_litedramcore_dfi_p2_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0; +reg main_litedramcore_dfi_p2_cas_n = 1'd1; +reg main_litedramcore_dfi_p2_cs_n = 1'd1; +reg main_litedramcore_dfi_p2_ras_n = 1'd1; +reg main_litedramcore_dfi_p2_we_n = 1'd1; wire main_litedramcore_dfi_p2_cke; wire main_litedramcore_dfi_p2_odt; wire main_litedramcore_dfi_p2_reset_n; -reg main_litedramcore_dfi_p2_act_n = 1'd1; +reg main_litedramcore_dfi_p2_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p2_wrdata; -reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p2_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p2_wrdata_mask; -reg main_litedramcore_dfi_p2_rddata_en = 1'd0; +reg main_litedramcore_dfi_p2_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p2_rddata; wire main_litedramcore_dfi_p2_rddata_valid; -reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; -reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; -reg main_litedramcore_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_dfi_p3_ras_n = 1'd1; -reg main_litedramcore_dfi_p3_we_n = 1'd1; +reg [13:0] main_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0; +reg main_litedramcore_dfi_p3_cas_n = 1'd1; +reg main_litedramcore_dfi_p3_cs_n = 1'd1; +reg main_litedramcore_dfi_p3_ras_n = 1'd1; +reg main_litedramcore_dfi_p3_we_n = 1'd1; wire main_litedramcore_dfi_p3_cke; wire main_litedramcore_dfi_p3_odt; wire main_litedramcore_dfi_p3_reset_n; -reg main_litedramcore_dfi_p3_act_n = 1'd1; +reg main_litedramcore_dfi_p3_act_n = 1'd1; wire [31:0] main_litedramcore_dfi_p3_wrdata; -reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; +reg main_litedramcore_dfi_p3_wrdata_en = 1'd0; wire [3:0] main_litedramcore_dfi_p3_wrdata_mask; -reg main_litedramcore_dfi_p3_rddata_en = 1'd0; +reg main_litedramcore_dfi_p3_rddata_en = 1'd0; wire [31:0] main_litedramcore_dfi_p3_rddata; wire main_litedramcore_dfi_p3_rddata_valid; -reg main_litedramcore_cmd_valid = 1'd0; -reg main_litedramcore_cmd_ready = 1'd0; -reg main_litedramcore_cmd_last = 1'd0; -reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; -reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; -reg main_litedramcore_cmd_payload_cas = 1'd0; -reg main_litedramcore_cmd_payload_ras = 1'd0; -reg main_litedramcore_cmd_payload_we = 1'd0; -reg main_litedramcore_cmd_payload_is_read = 1'd0; -reg main_litedramcore_cmd_payload_is_write = 1'd0; +reg main_litedramcore_cmd_valid = 1'd0; +reg main_litedramcore_cmd_ready = 1'd0; +reg main_litedramcore_cmd_last = 1'd0; +reg [13:0] main_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0; +reg main_litedramcore_cmd_payload_cas = 1'd0; +reg main_litedramcore_cmd_payload_ras = 1'd0; +reg main_litedramcore_cmd_payload_we = 1'd0; +reg main_litedramcore_cmd_payload_is_read = 1'd0; +reg main_litedramcore_cmd_payload_is_write = 1'd0; wire main_litedramcore_wants_refresh; wire main_litedramcore_wants_zqcs; wire main_litedramcore_timer_wait; wire main_litedramcore_timer_done0; wire [9:0] main_litedramcore_timer_count0; wire main_litedramcore_timer_done1; -reg [9:0] main_litedramcore_timer_count1 = 10'd781; +reg [9:0] main_litedramcore_timer_count1 = 10'd781; wire main_litedramcore_postponer_req_i; -reg main_litedramcore_postponer_req_o = 1'd0; -reg main_litedramcore_postponer_count = 1'd0; -reg main_litedramcore_sequencer_start0 = 1'd0; +reg main_litedramcore_postponer_req_o = 1'd0; +reg main_litedramcore_postponer_count = 1'd0; +reg main_litedramcore_sequencer_start0 = 1'd0; wire main_litedramcore_sequencer_done0; wire main_litedramcore_sequencer_start1; -reg main_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] main_litedramcore_sequencer_counter = 6'd0; -reg main_litedramcore_sequencer_count = 1'd0; +reg main_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] main_litedramcore_sequencer_counter = 6'd0; +reg main_litedramcore_sequencer_count = 1'd0; wire main_litedramcore_zqcs_timer_wait; wire main_litedramcore_zqcs_timer_done0; wire [26:0] main_litedramcore_zqcs_timer_count0; wire main_litedramcore_zqcs_timer_done1; -reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg main_litedramcore_zqcs_executer_start = 1'd0; -reg main_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; +reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg main_litedramcore_zqcs_executer_start = 1'd0; +reg main_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0; wire main_litedramcore_bankmachine0_req_valid; wire main_litedramcore_bankmachine0_req_ready; wire main_litedramcore_bankmachine0_req_we; wire [20:0] main_litedramcore_bankmachine0_req_addr; wire main_litedramcore_bankmachine0_req_lock; -reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine0_refresh_req; -reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba; -reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine0_auto_precharge = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; @@ -845,11 +867,11 @@ wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; @@ -870,51 +892,51 @@ wire main_litedramcore_bankmachine0_cmd_buffer_sink_first; wire main_litedramcore_bankmachine0_cmd_buffer_sink_last; wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; -reg main_litedramcore_bankmachine0_row_opened = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine0_row = 14'd0; +reg main_litedramcore_bankmachine0_row_opened = 1'd0; wire main_litedramcore_bankmachine0_row_hit; -reg main_litedramcore_bankmachine0_row_open = 1'd0; -reg main_litedramcore_bankmachine0_row_close = 1'd0; -reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine0_row_open = 1'd0; +reg main_litedramcore_bankmachine0_row_close = 1'd0; +reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0; wire main_litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0; wire main_litedramcore_bankmachine1_req_valid; wire main_litedramcore_bankmachine1_req_ready; wire main_litedramcore_bankmachine1_req_we; wire [20:0] main_litedramcore_bankmachine1_req_addr; wire main_litedramcore_bankmachine1_req_lock; -reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine1_refresh_req; -reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba; -reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine1_auto_precharge = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; @@ -929,11 +951,11 @@ wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; @@ -954,51 +976,51 @@ wire main_litedramcore_bankmachine1_cmd_buffer_sink_first; wire main_litedramcore_bankmachine1_cmd_buffer_sink_last; wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; -reg main_litedramcore_bankmachine1_row_opened = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine1_row = 14'd0; +reg main_litedramcore_bankmachine1_row_opened = 1'd0; wire main_litedramcore_bankmachine1_row_hit; -reg main_litedramcore_bankmachine1_row_open = 1'd0; -reg main_litedramcore_bankmachine1_row_close = 1'd0; -reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine1_row_open = 1'd0; +reg main_litedramcore_bankmachine1_row_close = 1'd0; +reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0; wire main_litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0; wire main_litedramcore_bankmachine2_req_valid; wire main_litedramcore_bankmachine2_req_ready; wire main_litedramcore_bankmachine2_req_we; wire [20:0] main_litedramcore_bankmachine2_req_addr; wire main_litedramcore_bankmachine2_req_lock; -reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine2_refresh_req; -reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba; -reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine2_auto_precharge = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; @@ -1013,11 +1035,11 @@ wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; @@ -1038,51 +1060,51 @@ wire main_litedramcore_bankmachine2_cmd_buffer_sink_first; wire main_litedramcore_bankmachine2_cmd_buffer_sink_last; wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; -reg main_litedramcore_bankmachine2_row_opened = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine2_row = 14'd0; +reg main_litedramcore_bankmachine2_row_opened = 1'd0; wire main_litedramcore_bankmachine2_row_hit; -reg main_litedramcore_bankmachine2_row_open = 1'd0; -reg main_litedramcore_bankmachine2_row_close = 1'd0; -reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine2_row_open = 1'd0; +reg main_litedramcore_bankmachine2_row_close = 1'd0; +reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0; wire main_litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0; wire main_litedramcore_bankmachine3_req_valid; wire main_litedramcore_bankmachine3_req_ready; wire main_litedramcore_bankmachine3_req_we; wire [20:0] main_litedramcore_bankmachine3_req_addr; wire main_litedramcore_bankmachine3_req_lock; -reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine3_refresh_req; -reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba; -reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine3_auto_precharge = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; @@ -1097,11 +1119,11 @@ wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; @@ -1122,51 +1144,51 @@ wire main_litedramcore_bankmachine3_cmd_buffer_sink_first; wire main_litedramcore_bankmachine3_cmd_buffer_sink_last; wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; -reg main_litedramcore_bankmachine3_row_opened = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine3_row = 14'd0; +reg main_litedramcore_bankmachine3_row_opened = 1'd0; wire main_litedramcore_bankmachine3_row_hit; -reg main_litedramcore_bankmachine3_row_open = 1'd0; -reg main_litedramcore_bankmachine3_row_close = 1'd0; -reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine3_row_open = 1'd0; +reg main_litedramcore_bankmachine3_row_close = 1'd0; +reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0; wire main_litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0; wire main_litedramcore_bankmachine4_req_valid; wire main_litedramcore_bankmachine4_req_ready; wire main_litedramcore_bankmachine4_req_we; wire [20:0] main_litedramcore_bankmachine4_req_addr; wire main_litedramcore_bankmachine4_req_lock; -reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine4_refresh_req; -reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba; -reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine4_auto_precharge = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; @@ -1181,11 +1203,11 @@ wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; @@ -1206,51 +1228,51 @@ wire main_litedramcore_bankmachine4_cmd_buffer_sink_first; wire main_litedramcore_bankmachine4_cmd_buffer_sink_last; wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; -reg main_litedramcore_bankmachine4_row_opened = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine4_row = 14'd0; +reg main_litedramcore_bankmachine4_row_opened = 1'd0; wire main_litedramcore_bankmachine4_row_hit; -reg main_litedramcore_bankmachine4_row_open = 1'd0; -reg main_litedramcore_bankmachine4_row_close = 1'd0; -reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine4_row_open = 1'd0; +reg main_litedramcore_bankmachine4_row_close = 1'd0; +reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0; wire main_litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0; wire main_litedramcore_bankmachine5_req_valid; wire main_litedramcore_bankmachine5_req_ready; wire main_litedramcore_bankmachine5_req_we; wire [20:0] main_litedramcore_bankmachine5_req_addr; wire main_litedramcore_bankmachine5_req_lock; -reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine5_refresh_req; -reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba; -reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine5_auto_precharge = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; @@ -1265,11 +1287,11 @@ wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; @@ -1290,51 +1312,51 @@ wire main_litedramcore_bankmachine5_cmd_buffer_sink_first; wire main_litedramcore_bankmachine5_cmd_buffer_sink_last; wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; -reg main_litedramcore_bankmachine5_row_opened = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine5_row = 14'd0; +reg main_litedramcore_bankmachine5_row_opened = 1'd0; wire main_litedramcore_bankmachine5_row_hit; -reg main_litedramcore_bankmachine5_row_open = 1'd0; -reg main_litedramcore_bankmachine5_row_close = 1'd0; -reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine5_row_open = 1'd0; +reg main_litedramcore_bankmachine5_row_close = 1'd0; +reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0; wire main_litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0; wire main_litedramcore_bankmachine6_req_valid; wire main_litedramcore_bankmachine6_req_ready; wire main_litedramcore_bankmachine6_req_we; wire [20:0] main_litedramcore_bankmachine6_req_addr; wire main_litedramcore_bankmachine6_req_lock; -reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine6_refresh_req; -reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba; -reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine6_auto_precharge = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; @@ -1349,11 +1371,11 @@ wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; @@ -1374,51 +1396,51 @@ wire main_litedramcore_bankmachine6_cmd_buffer_sink_first; wire main_litedramcore_bankmachine6_cmd_buffer_sink_last; wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; -reg main_litedramcore_bankmachine6_row_opened = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine6_row = 14'd0; +reg main_litedramcore_bankmachine6_row_opened = 1'd0; wire main_litedramcore_bankmachine6_row_hit; -reg main_litedramcore_bankmachine6_row_open = 1'd0; -reg main_litedramcore_bankmachine6_row_close = 1'd0; -reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine6_row_open = 1'd0; +reg main_litedramcore_bankmachine6_row_close = 1'd0; +reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0; wire main_litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0; wire main_litedramcore_bankmachine7_req_valid; wire main_litedramcore_bankmachine7_req_ready; wire main_litedramcore_bankmachine7_req_we; wire [20:0] main_litedramcore_bankmachine7_req_addr; wire main_litedramcore_bankmachine7_req_lock; -reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire main_litedramcore_bankmachine7_refresh_req; -reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg main_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0; wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba; -reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_litedramcore_bankmachine7_auto_precharge = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; @@ -1433,11 +1455,11 @@ wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; @@ -1458,107 +1480,107 @@ wire main_litedramcore_bankmachine7_cmd_buffer_sink_first; wire main_litedramcore_bankmachine7_cmd_buffer_sink_last; wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; wire main_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; -reg main_litedramcore_bankmachine7_row_opened = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] main_litedramcore_bankmachine7_row = 14'd0; +reg main_litedramcore_bankmachine7_row_opened = 1'd0; wire main_litedramcore_bankmachine7_row_hit; -reg main_litedramcore_bankmachine7_row_open = 1'd0; -reg main_litedramcore_bankmachine7_row_close = 1'd0; -reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +reg main_litedramcore_bankmachine7_row_open = 1'd0; +reg main_litedramcore_bankmachine7_row_close = 1'd0; +reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire main_litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0; wire main_litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0; wire main_litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0; wire main_litedramcore_ras_allowed; wire main_litedramcore_cas_allowed; wire [1:0] main_litedramcore_rdcmdphase; wire [1:0] main_litedramcore_wrcmdphase; -reg main_litedramcore_choose_cmd_want_reads = 1'd0; -reg main_litedramcore_choose_cmd_want_writes = 1'd0; -reg main_litedramcore_choose_cmd_want_cmds = 1'd0; -reg main_litedramcore_choose_cmd_want_activates = 1'd0; +reg main_litedramcore_choose_cmd_want_reads = 1'd0; +reg main_litedramcore_choose_cmd_want_writes = 1'd0; +reg main_litedramcore_choose_cmd_want_cmds = 1'd0; +reg main_litedramcore_choose_cmd_want_activates = 1'd0; wire main_litedramcore_choose_cmd_cmd_valid; -reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; +reg main_litedramcore_choose_cmd_cmd_ready = 1'd0; wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a; wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba; -reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire main_litedramcore_choose_cmd_cmd_payload_is_cmd; wire main_litedramcore_choose_cmd_cmd_payload_is_read; wire main_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; +reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0; wire [7:0] main_litedramcore_choose_cmd_request; -reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; +reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0; wire main_litedramcore_choose_cmd_ce; -reg main_litedramcore_choose_req_want_reads = 1'd0; -reg main_litedramcore_choose_req_want_writes = 1'd0; -reg main_litedramcore_choose_req_want_cmds = 1'd0; -reg main_litedramcore_choose_req_want_activates = 1'd0; +reg main_litedramcore_choose_req_want_reads = 1'd0; +reg main_litedramcore_choose_req_want_writes = 1'd0; +reg main_litedramcore_choose_req_want_cmds = 1'd0; +reg main_litedramcore_choose_req_want_activates = 1'd0; wire main_litedramcore_choose_req_cmd_valid; -reg main_litedramcore_choose_req_cmd_ready = 1'd0; +reg main_litedramcore_choose_req_cmd_ready = 1'd0; wire [13:0] main_litedramcore_choose_req_cmd_payload_a; wire [2:0] main_litedramcore_choose_req_cmd_payload_ba; -reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg main_litedramcore_choose_req_cmd_payload_we = 1'd0; wire main_litedramcore_choose_req_cmd_payload_is_cmd; wire main_litedramcore_choose_req_cmd_payload_is_read; wire main_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] main_litedramcore_choose_req_valids = 8'd0; +reg [7:0] main_litedramcore_choose_req_valids = 8'd0; wire [7:0] main_litedramcore_choose_req_request; -reg [2:0] main_litedramcore_choose_req_grant = 3'd0; +reg [2:0] main_litedramcore_choose_req_grant = 3'd0; wire main_litedramcore_choose_req_ce; -reg [13:0] main_litedramcore_nop_a = 14'd0; -reg [2:0] main_litedramcore_nop_ba = 3'd0; -reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; -reg main_litedramcore_steerer0 = 1'd1; -reg main_litedramcore_steerer1 = 1'd1; -reg main_litedramcore_steerer2 = 1'd1; -reg main_litedramcore_steerer3 = 1'd1; -reg main_litedramcore_steerer4 = 1'd1; -reg main_litedramcore_steerer5 = 1'd1; -reg main_litedramcore_steerer6 = 1'd1; -reg main_litedramcore_steerer7 = 1'd1; +reg [13:0] main_litedramcore_nop_a = 14'd0; +reg [2:0] main_litedramcore_nop_ba = 3'd0; +reg [1:0] main_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] main_litedramcore_steerer_sel3 = 2'd0; +reg main_litedramcore_steerer0 = 1'd1; +reg main_litedramcore_steerer1 = 1'd1; +reg main_litedramcore_steerer2 = 1'd1; +reg main_litedramcore_steerer3 = 1'd1; +reg main_litedramcore_steerer4 = 1'd1; +reg main_litedramcore_steerer5 = 1'd1; +reg main_litedramcore_steerer6 = 1'd1; +reg main_litedramcore_steerer7 = 1'd1; wire main_litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; -reg main_litedramcore_trrdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0; +reg main_litedramcore_trrdcon_count = 1'd0; wire main_litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; +(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1; wire [2:0] main_litedramcore_tfawcon_count; -reg [4:0] main_litedramcore_tfawcon_window = 5'd0; +reg [4:0] main_litedramcore_tfawcon_window = 5'd0; wire main_litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; -reg main_litedramcore_tccdcon_count = 1'd0; +(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0; +reg main_litedramcore_tccdcon_count = 1'd0; wire main_litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] main_litedramcore_twtrcon_count = 3'd0; +(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] main_litedramcore_twtrcon_count = 3'd0; wire main_litedramcore_read_available; wire main_litedramcore_write_available; -reg main_litedramcore_en0 = 1'd0; +reg main_litedramcore_en0 = 1'd0; wire main_litedramcore_max_time0; -reg [4:0] main_litedramcore_time0 = 5'd0; -reg main_litedramcore_en1 = 1'd0; +reg [4:0] main_litedramcore_time0 = 5'd0; +reg main_litedramcore_en1 = 1'd0; wire main_litedramcore_max_time1; -reg [3:0] main_litedramcore_time1 = 4'd0; +reg [3:0] main_litedramcore_time1 = 4'd0; wire main_litedramcore_go_to_refresh; -reg main_init_done_storage = 1'd0; -reg main_init_done_re = 1'd0; -reg main_init_error_storage = 1'd0; -reg main_init_error_re = 1'd0; +reg main_init_done_storage = 1'd0; +reg main_init_done_re = 1'd0; +reg main_init_error_storage = 1'd0; +reg main_init_error_re = 1'd0; wire [29:0] main_wb_bus_adr; wire [31:0] main_wb_bus_dat_w; wire [31:0] main_wb_bus_dat_r; @@ -1570,6 +1592,7 @@ wire main_wb_bus_we; wire [2:0] main_wb_bus_cti; wire [1:0] main_wb_bus_bte; wire main_wb_bus_err; +wire main_user_enable; wire main_user_port_cmd_valid; wire main_user_port_cmd_ready; wire main_user_port_cmd_payload_we; @@ -1590,26 +1613,26 @@ wire builder_reset5; wire builder_reset6; wire builder_reset7; wire builder_pll_fb; -reg [1:0] builder_refresher_state = 2'd0; -reg [1:0] builder_refresher_next_state = 2'd0; -reg [3:0] builder_bankmachine0_state = 4'd0; -reg [3:0] builder_bankmachine0_next_state = 4'd0; -reg [3:0] builder_bankmachine1_state = 4'd0; -reg [3:0] builder_bankmachine1_next_state = 4'd0; -reg [3:0] builder_bankmachine2_state = 4'd0; -reg [3:0] builder_bankmachine2_next_state = 4'd0; -reg [3:0] builder_bankmachine3_state = 4'd0; -reg [3:0] builder_bankmachine3_next_state = 4'd0; -reg [3:0] builder_bankmachine4_state = 4'd0; -reg [3:0] builder_bankmachine4_next_state = 4'd0; -reg [3:0] builder_bankmachine5_state = 4'd0; -reg [3:0] builder_bankmachine5_next_state = 4'd0; -reg [3:0] builder_bankmachine6_state = 4'd0; -reg [3:0] builder_bankmachine6_next_state = 4'd0; -reg [3:0] builder_bankmachine7_state = 4'd0; -reg [3:0] builder_bankmachine7_next_state = 4'd0; -reg [3:0] builder_multiplexer_state = 4'd0; -reg [3:0] builder_multiplexer_next_state = 4'd0; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [3:0] builder_bankmachine0_state = 4'd0; +reg [3:0] builder_bankmachine0_next_state = 4'd0; +reg [3:0] builder_bankmachine1_state = 4'd0; +reg [3:0] builder_bankmachine1_next_state = 4'd0; +reg [3:0] builder_bankmachine2_state = 4'd0; +reg [3:0] builder_bankmachine2_next_state = 4'd0; +reg [3:0] builder_bankmachine3_state = 4'd0; +reg [3:0] builder_bankmachine3_next_state = 4'd0; +reg [3:0] builder_bankmachine4_state = 4'd0; +reg [3:0] builder_bankmachine4_next_state = 4'd0; +reg [3:0] builder_bankmachine5_state = 4'd0; +reg [3:0] builder_bankmachine5_next_state = 4'd0; +reg [3:0] builder_bankmachine6_state = 4'd0; +reg [3:0] builder_bankmachine6_next_state = 4'd0; +reg [3:0] builder_bankmachine7_state = 4'd0; +reg [3:0] builder_bankmachine7_next_state = 4'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; wire builder_roundrobin0_request; wire builder_roundrobin0_grant; wire builder_roundrobin0_ce; @@ -1634,365 +1657,253 @@ wire builder_roundrobin6_ce; wire builder_roundrobin7_request; wire builder_roundrobin7_grant; wire builder_roundrobin7_ce; -reg builder_locked0 = 1'd0; -reg builder_locked1 = 1'd0; -reg builder_locked2 = 1'd0; -reg builder_locked3 = 1'd0; -reg builder_locked4 = 1'd0; -reg builder_locked5 = 1'd0; -reg builder_locked6 = 1'd0; -reg builder_locked7 = 1'd0; -reg builder_new_master_wdata_ready0 = 1'd0; -reg builder_new_master_wdata_ready1 = 1'd0; -reg builder_new_master_rdata_valid0 = 1'd0; -reg builder_new_master_rdata_valid1 = 1'd0; -reg builder_new_master_rdata_valid2 = 1'd0; -reg builder_new_master_rdata_valid3 = 1'd0; -reg builder_new_master_rdata_valid4 = 1'd0; -reg builder_new_master_rdata_valid5 = 1'd0; -reg builder_new_master_rdata_valid6 = 1'd0; -reg builder_new_master_rdata_valid7 = 1'd0; -reg builder_new_master_rdata_valid8 = 1'd0; -reg [13:0] builder_litedramcore_adr = 14'd0; -reg builder_litedramcore_we = 1'd0; -reg [7:0] builder_litedramcore_dat_w = 8'd0; -wire [7:0] builder_litedramcore_dat_r; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg [13:0] builder_litedramcore_adr = 14'd0; +reg builder_litedramcore_we = 1'd0; +reg [31:0] builder_litedramcore_dat_w = 32'd0; +wire [31:0] builder_litedramcore_dat_r; wire [29:0] builder_litedramcore_wishbone_adr; wire [31:0] builder_litedramcore_wishbone_dat_w; -reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; +reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0; wire [3:0] builder_litedramcore_wishbone_sel; wire builder_litedramcore_wishbone_cyc; wire builder_litedramcore_wishbone_stb; -reg builder_litedramcore_wishbone_ack = 1'd0; +reg builder_litedramcore_wishbone_ack = 1'd0; wire builder_litedramcore_wishbone_we; wire [2:0] builder_litedramcore_wishbone_cti; wire [1:0] builder_litedramcore_wishbone_bte; -reg builder_litedramcore_wishbone_err = 1'd0; +reg builder_litedramcore_wishbone_err = 1'd0; wire [13:0] builder_interface0_bank_bus_adr; wire builder_interface0_bank_bus_we; -wire [7:0] builder_interface0_bank_bus_dat_w; -reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0; -reg builder_csrbank0_init_done0_re = 1'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +reg builder_csrbank0_init_done0_re = 1'd0; wire builder_csrbank0_init_done0_r; -reg builder_csrbank0_init_done0_we = 1'd0; +reg builder_csrbank0_init_done0_we = 1'd0; wire builder_csrbank0_init_done0_w; -reg builder_csrbank0_init_error0_re = 1'd0; +reg builder_csrbank0_init_error0_re = 1'd0; wire builder_csrbank0_init_error0_r; -reg builder_csrbank0_init_error0_we = 1'd0; +reg builder_csrbank0_init_error0_we = 1'd0; wire builder_csrbank0_init_error0_w; wire builder_csrbank0_sel; wire [13:0] builder_interface1_bank_bus_adr; wire builder_interface1_bank_bus_we; -wire [7:0] builder_interface1_bank_bus_dat_w; -reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0; -reg builder_csrbank1_rst0_re = 1'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +reg builder_csrbank1_rst0_re = 1'd0; wire builder_csrbank1_rst0_r; -reg builder_csrbank1_rst0_we = 1'd0; +reg builder_csrbank1_rst0_we = 1'd0; wire builder_csrbank1_rst0_w; -reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_re = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_r; -reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; +reg builder_csrbank1_half_sys8x_taps0_we = 1'd0; wire [4:0] builder_csrbank1_half_sys8x_taps0_w; -reg builder_csrbank1_wlevel_en0_re = 1'd0; +reg builder_csrbank1_wlevel_en0_re = 1'd0; wire builder_csrbank1_wlevel_en0_r; -reg builder_csrbank1_wlevel_en0_we = 1'd0; +reg builder_csrbank1_wlevel_en0_we = 1'd0; wire builder_csrbank1_wlevel_en0_w; -reg builder_csrbank1_dly_sel0_re = 1'd0; +reg builder_csrbank1_dly_sel0_re = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_r; -reg builder_csrbank1_dly_sel0_we = 1'd0; +reg builder_csrbank1_dly_sel0_we = 1'd0; wire [1:0] builder_csrbank1_dly_sel0_w; -reg builder_csrbank1_rdphase0_re = 1'd0; +reg builder_csrbank1_rdphase0_re = 1'd0; wire [1:0] builder_csrbank1_rdphase0_r; -reg builder_csrbank1_rdphase0_we = 1'd0; +reg builder_csrbank1_rdphase0_we = 1'd0; wire [1:0] builder_csrbank1_rdphase0_w; -reg builder_csrbank1_wrphase0_re = 1'd0; +reg builder_csrbank1_wrphase0_re = 1'd0; wire [1:0] builder_csrbank1_wrphase0_r; -reg builder_csrbank1_wrphase0_we = 1'd0; +reg builder_csrbank1_wrphase0_we = 1'd0; wire [1:0] builder_csrbank1_wrphase0_w; wire builder_csrbank1_sel; wire [13:0] builder_interface2_bank_bus_adr; wire builder_interface2_bank_bus_we; -wire [7:0] builder_interface2_bank_bus_dat_w; -reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0; -reg builder_csrbank2_dfii_control0_re = 1'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +reg builder_csrbank2_dfii_control0_re = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_r; -reg builder_csrbank2_dfii_control0_we = 1'd0; +reg builder_csrbank2_dfii_control0_we = 1'd0; wire [3:0] builder_csrbank2_dfii_control0_w; -reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_r; -reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi0_command0_w; -reg builder_csrbank2_dfii_pi0_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi0_address1_r; -reg builder_csrbank2_dfii_pi0_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi0_address1_w; -reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_r; -reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_address0_w; -reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_r; +reg builder_csrbank2_dfii_pi0_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi0_address0_w; +reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r; -reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w; -reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r; -reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w; -reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r; -reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w; -reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r; -reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w; -reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r; -reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w; -reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r; -reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w; -reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r; -reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w; -reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r; -reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w; -reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r; -reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w; -reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_r; +reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_wrdata0_w; +reg builder_csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_r; +reg builder_csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi0_rddata_w; +reg builder_csrbank2_dfii_pi1_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_r; -reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi1_command0_w; -reg builder_csrbank2_dfii_pi1_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi1_address1_r; -reg builder_csrbank2_dfii_pi1_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi1_address1_w; -reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_r; -reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_address0_w; -reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_r; +reg builder_csrbank2_dfii_pi1_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi1_address0_w; +reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r; -reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w; -reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r; -reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w; -reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r; -reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w; -reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r; -reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w; -reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r; -reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w; -reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r; -reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w; -reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r; -reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w; -reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r; -reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w; -reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r; -reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w; -reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_r; +reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_wrdata0_w; +reg builder_csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_r; +reg builder_csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi1_rddata_w; +reg builder_csrbank2_dfii_pi2_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_r; -reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi2_command0_w; -reg builder_csrbank2_dfii_pi2_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi2_address1_r; -reg builder_csrbank2_dfii_pi2_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi2_address1_w; -reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_r; -reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_address0_w; -reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_r; +reg builder_csrbank2_dfii_pi2_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi2_address0_w; +reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r; -reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w; -reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r; -reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w; -reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r; -reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w; -reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r; -reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w; -reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r; -reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w; -reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r; -reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w; -reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r; -reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w; -reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r; -reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w; -reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r; -reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w; -reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; +reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_r; +reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_wrdata0_w; +reg builder_csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_r; +reg builder_csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi2_rddata_w; +reg builder_csrbank2_dfii_pi3_command0_re = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_r; -reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_command0_we = 1'd0; wire [5:0] builder_csrbank2_dfii_pi3_command0_w; -reg builder_csrbank2_dfii_pi3_address1_re = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi3_address1_r; -reg builder_csrbank2_dfii_pi3_address1_we = 1'd0; -wire [5:0] builder_csrbank2_dfii_pi3_address1_w; -reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_r; -reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_address0_w; -reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; +reg builder_csrbank2_dfii_pi3_address0_re = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_r; +reg builder_csrbank2_dfii_pi3_address0_we = 1'd0; +wire [13:0] builder_csrbank2_dfii_pi3_address0_w; +reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r; -reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; +reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0; wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w; -reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r; -reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w; -reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r; -reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w; -reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r; -reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w; -reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r; -reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w; -reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r; -reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w; -reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r; -reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w; -reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r; -reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w; -reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r; -reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w; +reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_r; +reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_wrdata0_w; +reg builder_csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_r; +reg builder_csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] builder_csrbank2_dfii_pi3_rddata_w; wire builder_csrbank2_sel; wire [13:0] builder_csr_interconnect_adr; wire builder_csr_interconnect_we; -wire [7:0] builder_csr_interconnect_dat_w; -wire [7:0] builder_csr_interconnect_dat_r; -reg [1:0] builder_state = 2'd0; -reg [1:0] builder_next_state = 2'd0; -reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0; -reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; -reg builder_litedramcore_adr_next_value_ce1 = 1'd0; -reg builder_litedramcore_we_next_value2 = 1'd0; -reg builder_litedramcore_we_next_value_ce2 = 1'd0; -reg builder_rhs_array_muxed0 = 1'd0; -reg [13:0] builder_rhs_array_muxed1 = 14'd0; -reg [2:0] builder_rhs_array_muxed2 = 3'd0; -reg builder_rhs_array_muxed3 = 1'd0; -reg builder_rhs_array_muxed4 = 1'd0; -reg builder_rhs_array_muxed5 = 1'd0; -reg builder_t_array_muxed0 = 1'd0; -reg builder_t_array_muxed1 = 1'd0; -reg builder_t_array_muxed2 = 1'd0; -reg builder_rhs_array_muxed6 = 1'd0; -reg [13:0] builder_rhs_array_muxed7 = 14'd0; -reg [2:0] builder_rhs_array_muxed8 = 3'd0; -reg builder_rhs_array_muxed9 = 1'd0; -reg builder_rhs_array_muxed10 = 1'd0; -reg builder_rhs_array_muxed11 = 1'd0; -reg builder_t_array_muxed3 = 1'd0; -reg builder_t_array_muxed4 = 1'd0; -reg builder_t_array_muxed5 = 1'd0; -reg [20:0] builder_rhs_array_muxed12 = 21'd0; -reg builder_rhs_array_muxed13 = 1'd0; -reg builder_rhs_array_muxed14 = 1'd0; -reg [20:0] builder_rhs_array_muxed15 = 21'd0; -reg builder_rhs_array_muxed16 = 1'd0; -reg builder_rhs_array_muxed17 = 1'd0; -reg [20:0] builder_rhs_array_muxed18 = 21'd0; -reg builder_rhs_array_muxed19 = 1'd0; -reg builder_rhs_array_muxed20 = 1'd0; -reg [20:0] builder_rhs_array_muxed21 = 21'd0; -reg builder_rhs_array_muxed22 = 1'd0; -reg builder_rhs_array_muxed23 = 1'd0; -reg [20:0] builder_rhs_array_muxed24 = 21'd0; -reg builder_rhs_array_muxed25 = 1'd0; -reg builder_rhs_array_muxed26 = 1'd0; -reg [20:0] builder_rhs_array_muxed27 = 21'd0; -reg builder_rhs_array_muxed28 = 1'd0; -reg builder_rhs_array_muxed29 = 1'd0; -reg [20:0] builder_rhs_array_muxed30 = 21'd0; -reg builder_rhs_array_muxed31 = 1'd0; -reg builder_rhs_array_muxed32 = 1'd0; -reg [20:0] builder_rhs_array_muxed33 = 21'd0; -reg builder_rhs_array_muxed34 = 1'd0; -reg builder_rhs_array_muxed35 = 1'd0; -reg [2:0] builder_array_muxed0 = 3'd0; -reg [13:0] builder_array_muxed1 = 14'd0; -reg builder_array_muxed2 = 1'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg builder_array_muxed6 = 1'd0; -reg [2:0] builder_array_muxed7 = 3'd0; -reg [13:0] builder_array_muxed8 = 14'd0; -reg builder_array_muxed9 = 1'd0; -reg builder_array_muxed10 = 1'd0; -reg builder_array_muxed11 = 1'd0; -reg builder_array_muxed12 = 1'd0; -reg builder_array_muxed13 = 1'd0; -reg [2:0] builder_array_muxed14 = 3'd0; -reg [13:0] builder_array_muxed15 = 14'd0; -reg builder_array_muxed16 = 1'd0; -reg builder_array_muxed17 = 1'd0; -reg builder_array_muxed18 = 1'd0; -reg builder_array_muxed19 = 1'd0; -reg builder_array_muxed20 = 1'd0; -reg [2:0] builder_array_muxed21 = 3'd0; -reg [13:0] builder_array_muxed22 = 14'd0; -reg builder_array_muxed23 = 1'd0; -reg builder_array_muxed24 = 1'd0; -reg builder_array_muxed25 = 1'd0; -reg builder_array_muxed26 = 1'd0; -reg builder_array_muxed27 = 1'd0; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg [1:0] builder_state = 2'd0; +reg [1:0] builder_next_state = 2'd0; +reg [31:0] builder_litedramcore_dat_w_next_value0 = 32'd0; +reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0; +reg builder_litedramcore_adr_next_value_ce1 = 1'd0; +reg builder_litedramcore_we_next_value2 = 1'd0; +reg builder_litedramcore_we_next_value_ce2 = 1'd0; +reg builder_rhs_array_muxed0 = 1'd0; +reg [13:0] builder_rhs_array_muxed1 = 14'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [13:0] builder_rhs_array_muxed7 = 14'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [20:0] builder_rhs_array_muxed12 = 21'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [20:0] builder_rhs_array_muxed15 = 21'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [20:0] builder_rhs_array_muxed18 = 21'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [20:0] builder_rhs_array_muxed21 = 21'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [20:0] builder_rhs_array_muxed24 = 21'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [20:0] builder_rhs_array_muxed27 = 21'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [20:0] builder_rhs_array_muxed30 = 21'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [20:0] builder_rhs_array_muxed33 = 21'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [13:0] builder_array_muxed1 = 14'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [13:0] builder_array_muxed8 = 14'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [13:0] builder_array_muxed15 = 14'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [13:0] builder_array_muxed22 = 14'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl1; @@ -2004,10 +1915,10 @@ wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire builder_xilinxasyncresetsynchronizerimpl3_expr; -// synthesis translate_off -reg dummy_s; -initial dummy_s <= 1'd0; -// synthesis translate_on +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + assign init_done = main_init_done_storage; assign init_error = main_init_error_storage; assign main_wb_bus_adr = wb_ctrl_adr; @@ -2023,18 +1934,19 @@ assign main_wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = main_wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; -assign main_user_port_cmd_valid = user_port_native_0_cmd_valid; -assign user_port_native_0_cmd_ready = main_user_port_cmd_ready; +assign main_user_enable = 1'd1; +assign main_user_port_cmd_valid = (user_port_native_0_cmd_valid & main_user_enable); +assign user_port_native_0_cmd_ready = (main_user_port_cmd_ready & main_user_enable); assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we; assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr; -assign main_user_port_wdata_valid = user_port_native_0_wdata_valid; -assign user_port_native_0_wdata_ready = main_user_port_wdata_ready; +assign main_user_port_wdata_valid = (user_port_native_0_wdata_valid & main_user_enable); +assign user_port_native_0_wdata_ready = (main_user_port_wdata_ready & main_user_enable); assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we; assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data; -assign user_port_native_0_rdata_valid = main_user_port_rdata_valid; -assign main_user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_valid = (main_user_port_rdata_valid & main_user_enable); +assign main_user_port_rdata_ready = (user_port_native_0_rdata_ready & main_user_enable); assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data; -assign main_reset = rst; +assign main_reset = (rst | main_rst); assign pll_locked = main_locked; assign main_clkin = clk; assign iodelay_clk = main_clkout_buf0; @@ -2043,10 +1955,6 @@ assign sys4x_clk = main_clkout_buf2; assign sys4x_dqs_clk = main_clkout_buf3; assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble); assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble); - -// synthesis translate_off -reg dummy_d; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p0_rddata <= 32'd0; main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0]; @@ -2081,14 +1989,7 @@ always @(*) begin main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1]; main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0]; main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1]; -// synthesis translate_off - dummy_d = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_1; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p1_rddata <= 32'd0; main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2]; @@ -2123,14 +2024,7 @@ always @(*) begin main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3]; main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2]; main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3]; -// synthesis translate_off - dummy_d_1 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_2; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p2_rddata <= 32'd0; main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4]; @@ -2165,14 +2059,7 @@ always @(*) begin main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5]; main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4]; main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5]; -// synthesis translate_off - dummy_d_2 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_3; -// synthesis translate_on always @(*) begin main_a7ddrphy_dfi_p3_rddata <= 32'd0; main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6]; @@ -2207,19 +2094,12 @@ always @(*) begin main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7]; main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6]; main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7]; -// synthesis translate_off - dummy_d_3 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage); assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1; - -// synthesis translate_off -reg dummy_d_4; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqs_oe <= 1'd0; if (main_a7ddrphy_wlevel_en_storage) begin @@ -2227,16 +2107,9 @@ always @(*) begin end else begin main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe; end -// synthesis translate_off - dummy_d_4 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1)); - -// synthesis translate_off -reg dummy_d_5; -// synthesis translate_on always @(*) begin main_a7ddrphy_dqspattern_o0 <= 8'd0; main_a7ddrphy_dqspattern_o0 <= 7'd85; @@ -2252,14 +2125,7 @@ always @(*) begin main_a7ddrphy_dqspattern_o0 <= 1'd1; end end -// synthesis translate_off - dummy_d_5 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_6; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip00 <= 8'd0; case (main_a7ddrphy_bitslip0_value0) @@ -2288,14 +2154,7 @@ always @(*) begin main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_6 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_7; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip10 <= 8'd0; case (main_a7ddrphy_bitslip1_value0) @@ -2324,14 +2183,7 @@ always @(*) begin main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_7 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_8; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip01 <= 8'd0; case (main_a7ddrphy_bitslip0_value1) @@ -2360,14 +2212,7 @@ always @(*) begin main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_8 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_9; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip11 <= 8'd0; case (main_a7ddrphy_bitslip1_value1) @@ -2396,14 +2241,7 @@ always @(*) begin main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_9 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_10; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip02 <= 8'd0; case (main_a7ddrphy_bitslip0_value2) @@ -2432,14 +2270,7 @@ always @(*) begin main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_10 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_11; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip04 <= 8'd0; case (main_a7ddrphy_bitslip0_value3) @@ -2468,14 +2299,7 @@ always @(*) begin main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_11 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_12; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip12 <= 8'd0; case (main_a7ddrphy_bitslip1_value2) @@ -2504,14 +2328,7 @@ always @(*) begin main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8]; end endcase -// synthesis translate_off - dummy_d_12 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_13; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip14 <= 8'd0; case (main_a7ddrphy_bitslip1_value3) @@ -2540,14 +2357,7 @@ always @(*) begin main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8]; end endcase -// synthesis translate_off - dummy_d_13 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_14; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip20 <= 8'd0; case (main_a7ddrphy_bitslip2_value0) @@ -2576,14 +2386,7 @@ always @(*) begin main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_14 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_15; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip22 <= 8'd0; case (main_a7ddrphy_bitslip2_value1) @@ -2612,14 +2415,7 @@ always @(*) begin main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_15 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_16; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip30 <= 8'd0; case (main_a7ddrphy_bitslip3_value0) @@ -2648,14 +2444,7 @@ always @(*) begin main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_16 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_17; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip32 <= 8'd0; case (main_a7ddrphy_bitslip3_value1) @@ -2684,14 +2473,7 @@ always @(*) begin main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_17 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_18; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip40 <= 8'd0; case (main_a7ddrphy_bitslip4_value0) @@ -2720,14 +2502,7 @@ always @(*) begin main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_18 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_19; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip42 <= 8'd0; case (main_a7ddrphy_bitslip4_value1) @@ -2756,14 +2531,7 @@ always @(*) begin main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_19 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_20; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip50 <= 8'd0; case (main_a7ddrphy_bitslip5_value0) @@ -2792,14 +2560,7 @@ always @(*) begin main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_20 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_21; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip52 <= 8'd0; case (main_a7ddrphy_bitslip5_value1) @@ -2828,14 +2589,7 @@ always @(*) begin main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_21 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_22; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip60 <= 8'd0; case (main_a7ddrphy_bitslip6_value0) @@ -2864,14 +2618,7 @@ always @(*) begin main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_22 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_23; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip62 <= 8'd0; case (main_a7ddrphy_bitslip6_value1) @@ -2900,14 +2647,7 @@ always @(*) begin main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_23 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_24; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip70 <= 8'd0; case (main_a7ddrphy_bitslip7_value0) @@ -2936,14 +2676,7 @@ always @(*) begin main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_24 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_25; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip72 <= 8'd0; case (main_a7ddrphy_bitslip7_value1) @@ -2972,14 +2705,7 @@ always @(*) begin main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_25 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_26; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip80 <= 8'd0; case (main_a7ddrphy_bitslip8_value0) @@ -3008,14 +2734,7 @@ always @(*) begin main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip82 <= 8'd0; case (main_a7ddrphy_bitslip8_value1) @@ -3044,14 +2763,7 @@ always @(*) begin main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip90 <= 8'd0; case (main_a7ddrphy_bitslip9_value0) @@ -3080,14 +2792,7 @@ always @(*) begin main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip92 <= 8'd0; case (main_a7ddrphy_bitslip9_value1) @@ -3116,14 +2821,7 @@ always @(*) begin main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip100 <= 8'd0; case (main_a7ddrphy_bitslip10_value0) @@ -3152,14 +2850,7 @@ always @(*) begin main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_30 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_31; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip102 <= 8'd0; case (main_a7ddrphy_bitslip10_value1) @@ -3188,14 +2879,7 @@ always @(*) begin main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_31 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_32; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip110 <= 8'd0; case (main_a7ddrphy_bitslip11_value0) @@ -3224,14 +2908,7 @@ always @(*) begin main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_32 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_33; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip112 <= 8'd0; case (main_a7ddrphy_bitslip11_value1) @@ -3260,14 +2937,7 @@ always @(*) begin main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_33 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_34; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip120 <= 8'd0; case (main_a7ddrphy_bitslip12_value0) @@ -3296,14 +2966,7 @@ always @(*) begin main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_34 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_35; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip122 <= 8'd0; case (main_a7ddrphy_bitslip12_value1) @@ -3332,14 +2995,7 @@ always @(*) begin main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_35 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_36; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip130 <= 8'd0; case (main_a7ddrphy_bitslip13_value0) @@ -3368,14 +3024,7 @@ always @(*) begin main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_36 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_37; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip132 <= 8'd0; case (main_a7ddrphy_bitslip13_value1) @@ -3404,14 +3053,7 @@ always @(*) begin main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_37 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_38; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip140 <= 8'd0; case (main_a7ddrphy_bitslip14_value0) @@ -3440,14 +3082,7 @@ always @(*) begin main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip142 <= 8'd0; case (main_a7ddrphy_bitslip14_value1) @@ -3476,14 +3111,7 @@ always @(*) begin main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_39 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_40; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip150 <= 8'd0; case (main_a7ddrphy_bitslip15_value0) @@ -3512,14 +3140,7 @@ always @(*) begin main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8]; end endcase -// synthesis translate_off - dummy_d_40 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_41; -// synthesis translate_on always @(*) begin main_a7ddrphy_bitslip152 <= 8'd0; case (main_a7ddrphy_bitslip15_value1) @@ -3548,9 +3169,6 @@ always @(*) begin main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8]; end endcase -// synthesis translate_off - dummy_d_41 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address; assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank; @@ -3680,10 +3298,14 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_ assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; - -// synthesis translate_off -reg dummy_d_42; -// synthesis translate_on +always @(*) begin + main_litedramcore_master_p3_rddata_en <= 1'd0; + if (main_litedramcore_sel) begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; + end else begin + main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; + end +end always @(*) begin main_litedramcore_master_p0_address <= 14'd0; if (main_litedramcore_sel) begin @@ -3691,14 +3313,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address; end -// synthesis translate_off - dummy_d_42 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_43; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -3706,14 +3321,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank; end -// synthesis translate_off - dummy_d_43 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_44; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3721,14 +3329,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n; end -// synthesis translate_off - dummy_d_44 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_45; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3736,14 +3337,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n; end -// synthesis translate_off - dummy_d_45 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_46; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3751,28 +3345,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n; end -// synthesis translate_off - dummy_d_46 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_47; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata; end else begin end -// synthesis translate_off - dummy_d_47 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_48; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3780,28 +3360,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n; end -// synthesis translate_off - dummy_d_48 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_49; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p0_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_49 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_50; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -3809,14 +3375,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke; end -// synthesis translate_off - dummy_d_50 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_51; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -3824,14 +3383,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt; end -// synthesis translate_off - dummy_d_51 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_52; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -3839,14 +3391,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n; end -// synthesis translate_off - dummy_d_52 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_53; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3854,14 +3399,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n; end -// synthesis translate_off - dummy_d_53 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_54; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -3869,28 +3407,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata; end -// synthesis translate_off - dummy_d_54 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_55; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata; end -// synthesis translate_off - dummy_d_55 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_56; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3898,28 +3422,14 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en; end -// synthesis translate_off - dummy_d_56 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_57; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end -// synthesis translate_off - dummy_d_57 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_58; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -3927,14 +3437,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask; end -// synthesis translate_off - dummy_d_58 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_59; -// synthesis translate_on always @(*) begin main_litedramcore_master_p0_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -3942,14 +3445,7 @@ always @(*) begin end else begin main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en; end -// synthesis translate_off - dummy_d_59 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_60; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_address <= 14'd0; if (main_litedramcore_sel) begin @@ -3957,14 +3453,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address; end -// synthesis translate_off - dummy_d_60 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_61; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -3972,14 +3461,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank; end -// synthesis translate_off - dummy_d_61 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_62; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -3987,14 +3469,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n; end -// synthesis translate_off - dummy_d_62 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_63; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4002,14 +3477,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n; end -// synthesis translate_off - dummy_d_63 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_64; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4017,28 +3485,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n; end -// synthesis translate_off - dummy_d_64 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_65; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata; end else begin end -// synthesis translate_off - dummy_d_65 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_66; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4046,28 +3500,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n; end -// synthesis translate_off - dummy_d_66 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_67; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p1_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_67 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_68; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4075,14 +3515,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke; end -// synthesis translate_off - dummy_d_68 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_69; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4090,14 +3523,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt; end -// synthesis translate_off - dummy_d_69 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_70; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4105,14 +3531,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n; end -// synthesis translate_off - dummy_d_70 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_71; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4120,14 +3539,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n; end -// synthesis translate_off - dummy_d_71 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_72; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4135,28 +3547,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata; end -// synthesis translate_off - dummy_d_72 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_73; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata; end -// synthesis translate_off - dummy_d_73 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_74; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4164,28 +3562,14 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en; end -// synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end -// synthesis translate_off - dummy_d_75 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_76; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4193,14 +3577,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask; end -// synthesis translate_off - dummy_d_76 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_77; -// synthesis translate_on always @(*) begin main_litedramcore_master_p1_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4208,14 +3585,7 @@ always @(*) begin end else begin main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en; end -// synthesis translate_off - dummy_d_77 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_78; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_address <= 14'd0; if (main_litedramcore_sel) begin @@ -4223,14 +3593,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address; end -// synthesis translate_off - dummy_d_78 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_79; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4238,14 +3601,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank; end -// synthesis translate_off - dummy_d_79 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_80; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4253,14 +3609,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n; end -// synthesis translate_off - dummy_d_80 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_81; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4268,14 +3617,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n; end -// synthesis translate_off - dummy_d_81 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_82; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4283,28 +3625,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_82 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_83; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata; end else begin end -// synthesis translate_off - dummy_d_83 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_84; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4312,28 +3640,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n; end -// synthesis translate_off - dummy_d_84 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_85; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p2_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_85 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_86; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4341,28 +3655,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke; end -// synthesis translate_off - dummy_d_86 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_87; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p0_rddata <= 32'd0; - if (main_litedramcore_sel) begin - end else begin - main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; - end -// synthesis translate_off - dummy_d_87 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_88; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4370,14 +3663,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt; end -// synthesis translate_off - dummy_d_88 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_89; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4385,14 +3671,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n; end -// synthesis translate_off - dummy_d_89 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_90; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4400,14 +3679,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n; end -// synthesis translate_off - dummy_d_90 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_91; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4415,28 +3687,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata; end -// synthesis translate_off - dummy_d_91 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_92; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata; end -// synthesis translate_off - dummy_d_92 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_93; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4444,28 +3702,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en; end -// synthesis translate_off - dummy_d_93 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_94; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p0_rddata_valid <= 1'd0; + main_litedramcore_inti_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin end else begin - main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end -// synthesis translate_off - dummy_d_94 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_95; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4473,28 +3717,14 @@ always @(*) begin end else begin main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask; end -// synthesis translate_off - dummy_d_95 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_96; -// synthesis translate_on always @(*) begin - main_litedramcore_inti_p3_rddata_valid <= 1'd0; + main_litedramcore_inti_p0_rddata <= 32'd0; if (main_litedramcore_sel) begin end else begin - main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; + main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on always @(*) begin main_litedramcore_master_p2_rddata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4502,14 +3732,7 @@ always @(*) begin end else begin main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en; end -// synthesis translate_off - dummy_d_97 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_98; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_address <= 14'd0; if (main_litedramcore_sel) begin @@ -4517,14 +3740,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address; end -// synthesis translate_off - dummy_d_98 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_99; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_bank <= 3'd0; if (main_litedramcore_sel) begin @@ -4532,14 +3748,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank; end -// synthesis translate_off - dummy_d_99 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_100; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p0_rddata_valid <= 1'd0; + if (main_litedramcore_sel) begin + end else begin + main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid; + end +end always @(*) begin main_litedramcore_master_p3_cas_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4547,14 +3763,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n; end -// synthesis translate_off - dummy_d_100 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_101; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cs_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4562,14 +3771,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n; end -// synthesis translate_off - dummy_d_101 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_102; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_ras_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4577,28 +3779,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n; end -// synthesis translate_off - dummy_d_102 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_103; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata <= 32'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata; end else begin end -// synthesis translate_off - dummy_d_103 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_104; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_we_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4606,28 +3794,14 @@ always @(*) begin end else begin main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n; end -// synthesis translate_off - dummy_d_104 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_105; -// synthesis translate_on always @(*) begin main_litedramcore_slave_p3_rddata_valid <= 1'd0; if (main_litedramcore_sel) begin main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid; end else begin end -// synthesis translate_off - dummy_d_105 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_106; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_cke <= 1'd0; if (main_litedramcore_sel) begin @@ -4635,14 +3809,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke; end -// synthesis translate_off - dummy_d_106 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_107; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4650,14 +3817,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt; end -// synthesis translate_off - dummy_d_107 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_108; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_reset_n <= 1'd0; if (main_litedramcore_sel) begin @@ -4665,14 +3825,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n; end -// synthesis translate_off - dummy_d_108 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_109; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_act_n <= 1'd1; if (main_litedramcore_sel) begin @@ -4680,14 +3833,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n; end -// synthesis translate_off - dummy_d_109 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_110; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata <= 32'd0; if (main_litedramcore_sel) begin @@ -4695,14 +3841,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata; end -// synthesis translate_off - dummy_d_110 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_111; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_en <= 1'd0; if (main_litedramcore_sel) begin @@ -4710,14 +3849,7 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en; end -// synthesis translate_off - dummy_d_111 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_112; -// synthesis translate_on always @(*) begin main_litedramcore_master_p3_wrdata_mask <= 4'd0; if (main_litedramcore_sel) begin @@ -4725,24 +3857,6 @@ always @(*) begin end else begin main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask; end -// synthesis translate_off - dummy_d_112 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_113; -// synthesis translate_on -always @(*) begin - main_litedramcore_master_p3_rddata_en <= 1'd0; - if (main_litedramcore_sel) begin - main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en; - end else begin - main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en; - end -// synthesis translate_off - dummy_d_113 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_cke = main_litedramcore_cke; assign main_litedramcore_inti_p1_cke = main_litedramcore_cke; @@ -4756,10 +3870,14 @@ assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n; - -// synthesis translate_off -reg dummy_d_114; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); + end else begin + main_litedramcore_inti_p0_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p0_cas_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4767,14 +3885,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_114 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_115; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_cs_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4782,14 +3893,7 @@ always @(*) begin end else begin main_litedramcore_inti_p0_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_115 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_116; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p0_ras_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4797,24 +3901,6 @@ always @(*) begin end else begin main_litedramcore_inti_p0_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_116 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_117; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p0_we_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]); - end else begin - main_litedramcore_inti_p0_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_117 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; @@ -4822,10 +3908,14 @@ assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_c assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]); assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_inti_p0_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_118; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); + end else begin + main_litedramcore_inti_p1_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p1_cas_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4833,14 +3923,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_118 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_119; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_cs_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4848,14 +3931,7 @@ always @(*) begin end else begin main_litedramcore_inti_p1_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_119 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_120; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p1_ras_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4863,24 +3939,6 @@ always @(*) begin end else begin main_litedramcore_inti_p1_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_120 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_121; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p1_we_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]); - end else begin - main_litedramcore_inti_p1_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_121 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; @@ -4888,10 +3946,14 @@ assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_c assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]); assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_inti_p1_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_122; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); + end else begin + main_litedramcore_inti_p2_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4899,14 +3961,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_122 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_123; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_cs_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4914,14 +3969,7 @@ always @(*) begin end else begin main_litedramcore_inti_p2_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p2_ras_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4929,24 +3977,6 @@ always @(*) begin end else begin main_litedramcore_inti_p2_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_124 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_125; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p2_we_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]); - end else begin - main_litedramcore_inti_p2_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_125 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; @@ -4954,10 +3984,14 @@ assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_c assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]); assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_inti_p2_wrdata_mask = 1'd0; - -// synthesis translate_off -reg dummy_d_126; -// synthesis translate_on +always @(*) begin + main_litedramcore_inti_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); + end else begin + main_litedramcore_inti_p3_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_inti_p3_cas_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4965,14 +3999,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cas_n <= 1'd1; end -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_cs_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4980,14 +4007,7 @@ always @(*) begin end else begin main_litedramcore_inti_p3_cs_n <= {1{1'd1}}; end -// synthesis translate_off - dummy_d_127 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_128; -// synthesis translate_on always @(*) begin main_litedramcore_inti_p3_ras_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4995,24 +4015,6 @@ always @(*) begin end else begin main_litedramcore_inti_p3_ras_n <= 1'd1; end -// synthesis translate_off - dummy_d_128 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_129; -// synthesis translate_on -always @(*) begin - main_litedramcore_inti_p3_we_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]); - end else begin - main_litedramcore_inti_p3_we_n <= 1'd1; - end -// synthesis translate_off - dummy_d_129 = dummy_s; -// synthesis translate_on end assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; @@ -5089,10 +4091,6 @@ assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0); assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1; assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1; - -// synthesis translate_off -reg dummy_d_130; -// synthesis translate_on always @(*) begin builder_refresher_next_state <= 2'd0; builder_refresher_next_state <= builder_refresher_state; @@ -5124,119 +4122,88 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_130 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_131; -// synthesis translate_on always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; + main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end end 2'd2: begin + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_last <= 1'd1; + end + end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase -// synthesis translate_off - dummy_d_131 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_132; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) 1'd1: begin - main_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_sequencer_done0) begin - if (main_litedramcore_wants_zqcs) begin - end else begin - main_litedramcore_cmd_valid <= 1'd0; - end + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; end end + 2'd2: begin + end 2'd3: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase -// synthesis translate_off - dummy_d_132 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_133; -// synthesis translate_on always @(*) begin - main_litedramcore_zqcs_executer_start <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) 1'd1: begin + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin - main_litedramcore_zqcs_executer_start <= 1'd1; end else begin + main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end endcase -// synthesis translate_off - dummy_d_133 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_134; -// synthesis translate_on always @(*) begin - main_litedramcore_cmd_last <= 1'd0; + main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) 1'd1: begin end 2'd2: begin if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase -// synthesis translate_off - dummy_d_134 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; @@ -5252,10 +4219,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid); assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; - -// synthesis translate_off -reg dummy_d_135; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin @@ -5263,17 +4226,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_135 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write); assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open); - -// synthesis translate_off -reg dummy_d_136; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin @@ -5281,9 +4237,6 @@ always @(*) begin main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_136 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; @@ -5302,10 +4255,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_137; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin @@ -5313,9 +4262,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_137 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); @@ -5325,10 +4271,6 @@ assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_138; -// synthesis translate_on always @(*) begin builder_bankmachine0_next_state <= 4'd0; builder_bankmachine0_next_state <= builder_bankmachine0_state; @@ -5389,14 +4331,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_138 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_139; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + main_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) @@ -5422,14 +4398,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_close <= 1'd0; case (builder_bankmachine0_state) @@ -5455,14 +4424,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_140 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_141; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (builder_bankmachine0_state) @@ -5497,14 +4459,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_141 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_142; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (builder_bankmachine0_state) @@ -5533,14 +4488,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_142 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_143; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (builder_bankmachine0_state) @@ -5581,14 +4529,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_143 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_144; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine0_state) @@ -5614,14 +4555,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_144 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_145; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine0_state) @@ -5651,14 +4585,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_145 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_146; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (builder_bankmachine0_state) @@ -5696,16 +4623,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_146 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_147; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5730,8 +4650,8 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin - main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5741,16 +4661,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5775,7 +4688,7 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin end end else begin @@ -5786,16 +4699,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_148 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_149; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5820,8 +4726,8 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5831,14 +4737,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_149 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_150; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (builder_bankmachine0_state) @@ -5864,57 +4763,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_150 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_151; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_151 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; @@ -5930,10 +4778,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid); assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; - -// synthesis translate_off -reg dummy_d_152; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin @@ -5941,17 +4785,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_152 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write); assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open); - -// synthesis translate_off -reg dummy_d_153; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin @@ -5959,9 +4796,6 @@ always @(*) begin main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_153 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; @@ -5980,10 +4814,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_154; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin @@ -5991,9 +4821,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_154 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); @@ -6003,10 +4830,6 @@ assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_155; -// synthesis translate_on always @(*) begin builder_bankmachine1_next_state <= 4'd0; builder_bankmachine1_next_state <= builder_bankmachine1_state; @@ -6067,14 +4890,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_155 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_156; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine1_row_open <= 1'd0; case (builder_bankmachine1_state) @@ -6100,14 +4957,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_156 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_157; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_close <= 1'd0; case (builder_bankmachine1_state) @@ -6133,14 +4983,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (builder_bankmachine1_state) @@ -6175,14 +5018,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_158 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_159; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (builder_bankmachine1_state) @@ -6211,14 +5047,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_159 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_160; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (builder_bankmachine1_state) @@ -6259,14 +5088,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_160 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_161; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) @@ -6292,14 +5114,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_161 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_162; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine1_state) @@ -6329,47 +5144,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_162 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_163; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_163 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_164; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (builder_bankmachine1_state) @@ -6407,14 +5182,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_164 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_165; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (builder_bankmachine1_state) @@ -6452,14 +5220,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_165 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_166; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (builder_bankmachine1_state) @@ -6497,14 +5258,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_166 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_167; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (builder_bankmachine1_state) @@ -6542,30 +5296,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_167 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_168; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6576,23 +5320,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_168 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; @@ -6608,10 +5337,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; - -// synthesis translate_off -reg dummy_d_169; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin @@ -6619,17 +5344,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_169 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); - -// synthesis translate_off -reg dummy_d_170; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin @@ -6637,9 +5355,6 @@ always @(*) begin main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_170 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; @@ -6658,10 +5373,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_171; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin @@ -6669,9 +5380,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_171 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); @@ -6681,10 +5389,6 @@ assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_172; -// synthesis translate_on always @(*) begin builder_bankmachine2_next_state <= 4'd0; builder_bankmachine2_next_state <= builder_bankmachine2_state; @@ -6745,22 +5449,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_172 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_173; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6778,10 +5481,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; - end + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6790,14 +5490,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) @@ -6823,14 +5516,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_174 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_175; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) @@ -6856,14 +5542,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_175 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_176; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) @@ -6898,14 +5577,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_176 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_177; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (builder_bankmachine2_state) @@ -6934,14 +5606,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_177 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_178; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) @@ -6982,14 +5647,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_178 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_179; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) @@ -7015,14 +5673,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_179 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_180; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) @@ -7052,14 +5703,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_180 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_181; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) @@ -7097,14 +5741,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_181 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_182; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) @@ -7142,14 +5779,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_182 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_183; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) @@ -7187,16 +5817,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_183 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_184; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -7205,9 +5828,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine2_twtpcon_ready) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7218,32 +5838,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_184 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_185; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7254,23 +5879,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_185 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid; assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; @@ -7286,10 +5896,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid); assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; - -// synthesis translate_off -reg dummy_d_186; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin @@ -7297,17 +5903,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_186 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write); assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open); - -// synthesis translate_off -reg dummy_d_187; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin @@ -7315,9 +5914,6 @@ always @(*) begin main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_187 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; @@ -7336,10 +5932,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_188; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin @@ -7347,9 +5939,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_188 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); @@ -7359,10 +5948,6 @@ assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_189; -// synthesis translate_on always @(*) begin builder_bankmachine3_next_state <= 4'd0; builder_bankmachine3_next_state <= builder_bankmachine3_state; @@ -7423,14 +6008,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_189 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_190; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_row_open <= 1'd0; case (builder_bankmachine3_state) @@ -7456,14 +6075,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_190 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_191; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_row_close <= 1'd0; case (builder_bankmachine3_state) @@ -7489,14 +6101,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (builder_bankmachine3_state) @@ -7531,14 +6136,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_192 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_193; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (builder_bankmachine3_state) @@ -7567,14 +6165,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_193 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_194; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (builder_bankmachine3_state) @@ -7615,22 +6206,18 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_194 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_195; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7643,31 +6230,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_195 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_196; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -7697,47 +6262,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_196 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_197; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_197 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_198; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (builder_bankmachine3_state) @@ -7775,14 +6300,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_198 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_199; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (builder_bankmachine3_state) @@ -7820,14 +6338,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_199 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_200; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (builder_bankmachine3_state) @@ -7865,16 +6376,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_200 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_201; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin end @@ -7883,9 +6387,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine3_twtpcon_ready) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7896,32 +6397,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_201 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_202; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7932,23 +6438,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_202 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; @@ -7964,10 +6455,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid); assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; - -// synthesis translate_off -reg dummy_d_203; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin @@ -7975,17 +6462,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_203 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write); assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open); - -// synthesis translate_off -reg dummy_d_204; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin @@ -7993,9 +6473,6 @@ always @(*) begin main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_204 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; @@ -8014,10 +6491,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_205; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin @@ -8025,9 +6498,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_205 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); @@ -8037,10 +6507,6 @@ assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_206; -// synthesis translate_on always @(*) begin builder_bankmachine4_next_state <= 4'd0; builder_bankmachine4_next_state <= builder_bankmachine4_state; @@ -8101,24 +6567,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_206 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_207; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_open <= 1'd0; + main_litedramcore_bankmachine4_cmd_valid <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_row_open <= 1'd1; + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8132,29 +6594,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + main_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_row_close <= 1'd0; + main_litedramcore_bankmachine4_row_open <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8167,24 +6634,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_208 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_209; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine4_row_close <= 1'd0; case (builder_bankmachine4_state) 1'd1: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -8195,7 +6658,30 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin end else begin if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine4_row_opened) begin @@ -8209,14 +6695,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_209 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_210; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (builder_bankmachine4_state) @@ -8245,14 +6724,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_210 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_211; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (builder_bankmachine4_state) @@ -8293,14 +6765,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_211 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_212; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine4_state) @@ -8326,14 +6791,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_212 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_213; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine4_state) @@ -8363,14 +6821,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_213 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_214; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (builder_bankmachine4_state) @@ -8408,14 +6859,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_214 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_215; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (builder_bankmachine4_state) @@ -8453,14 +6897,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_215 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_216; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (builder_bankmachine4_state) @@ -8498,14 +6935,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_216 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_217; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) @@ -8543,14 +6973,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (builder_bankmachine4_state) @@ -8576,57 +6999,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_218 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_219; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - main_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_219 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; @@ -8642,10 +7014,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid); assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; - -// synthesis translate_off -reg dummy_d_220; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin @@ -8653,17 +7021,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_220 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write); assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open); - -// synthesis translate_off -reg dummy_d_221; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin @@ -8671,9 +7032,6 @@ always @(*) begin main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_221 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; @@ -8692,10 +7050,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_222; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin @@ -8703,9 +7057,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_222 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); @@ -8715,10 +7066,6 @@ assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_223; -// synthesis translate_on always @(*) begin builder_bankmachine5_next_state <= 4'd0; builder_bankmachine5_next_state <= builder_bankmachine5_state; @@ -8779,22 +7126,21 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_223 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_224; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8812,10 +7158,7 @@ always @(*) begin if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; - end + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin @@ -8824,14 +7167,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_224 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_225; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_open <= 1'd0; case (builder_bankmachine5_state) @@ -8857,14 +7193,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_close <= 1'd0; case (builder_bankmachine5_state) @@ -8890,14 +7219,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_226 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_227; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (builder_bankmachine5_state) @@ -8932,14 +7254,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_227 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_228; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (builder_bankmachine5_state) @@ -8968,14 +7283,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_228 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_229; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (builder_bankmachine5_state) @@ -9016,14 +7324,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_229 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_230; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -9049,14 +7350,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_230 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_231; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine5_state) @@ -9086,14 +7380,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_231 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_232; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (builder_bankmachine5_state) @@ -9131,14 +7418,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_232 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_233; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (builder_bankmachine5_state) @@ -9176,14 +7456,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_233 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_234; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (builder_bankmachine5_state) @@ -9221,16 +7494,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_234 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_235; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -9239,9 +7505,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine5_twtpcon_ready) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9252,32 +7515,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_235 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_236; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9288,23 +7556,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_236 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; @@ -9320,10 +7573,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid); assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; - -// synthesis translate_off -reg dummy_d_237; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin @@ -9331,17 +7580,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_237 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write); assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open); - -// synthesis translate_off -reg dummy_d_238; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin @@ -9349,9 +7591,6 @@ always @(*) begin main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_238 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; @@ -9370,10 +7609,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_239; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin @@ -9381,9 +7616,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_239 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); @@ -9393,10 +7625,6 @@ assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_240; -// synthesis translate_on always @(*) begin builder_bankmachine6_next_state <= 4'd0; builder_bankmachine6_next_state <= builder_bankmachine6_state; @@ -9457,24 +7685,20 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_240 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_241; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_row_open <= 1'd0; + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_open <= 1'd1; + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9488,29 +7712,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_row_close <= 1'd0; + main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9523,24 +7752,20 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_242 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_243; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9551,31 +7776,9 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_243 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_244; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) @@ -9610,14 +7813,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_244 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_245; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (builder_bankmachine6_state) @@ -9646,14 +7842,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_245 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_246; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) @@ -9694,14 +7883,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_246 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_247; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) @@ -9727,14 +7909,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_247 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_248; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) @@ -9764,14 +7939,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_248 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_249; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) @@ -9809,14 +7977,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_249 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_250; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) @@ -9854,14 +8015,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_250 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_251; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) @@ -9899,16 +8053,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_251 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_252; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -9917,9 +8064,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine6_twtpcon_ready) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9930,32 +8074,37 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase -// synthesis translate_off - dummy_d_252 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_253; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9966,23 +8115,8 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase -// synthesis translate_off - dummy_d_253 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; @@ -9998,10 +8132,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramco assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid); assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; - -// synthesis translate_off -reg dummy_d_254; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin @@ -10009,17 +8139,10 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); end -// synthesis translate_off - dummy_d_254 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write); assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open); - -// synthesis translate_off -reg dummy_d_255; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin @@ -10027,9 +8150,6 @@ always @(*) begin main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0); end end -// synthesis translate_off - dummy_d_255 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; @@ -10048,10 +8168,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_li assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; - -// synthesis translate_off -reg dummy_d_256; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin @@ -10059,9 +8175,6 @@ always @(*) begin end else begin main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; end -// synthesis translate_off - dummy_d_256 = dummy_s; -// synthesis translate_on end assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); @@ -10071,10 +8184,6 @@ assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready); - -// synthesis translate_off -reg dummy_d_257; -// synthesis translate_on always @(*) begin builder_bankmachine7_next_state <= 4'd0; builder_bankmachine7_next_state <= builder_bankmachine7_state; @@ -10135,14 +8244,48 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_257 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_258; -// synthesis translate_on +always @(*) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end always @(*) begin main_litedramcore_bankmachine7_row_open <= 1'd0; case (builder_bankmachine7_state) @@ -10168,14 +8311,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_258 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_259; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) @@ -10201,14 +8337,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_259 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_260; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) @@ -10243,14 +8372,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_260 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_261; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) @@ -10279,14 +8401,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_261 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_262; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) @@ -10327,14 +8442,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_262 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_263; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) @@ -10360,14 +8468,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_263 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_264; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) @@ -10397,16 +8498,9 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_264 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_265; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10432,7 +8526,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin end else begin - main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10442,16 +8536,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_265 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_266; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10476,8 +8563,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10487,16 +8574,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_266 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_267; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10521,7 +8601,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin end end else begin @@ -10532,16 +8612,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_267 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_268; -// synthesis translate_on always @(*) begin - main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -10566,8 +8639,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -10577,14 +8650,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_268 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_269; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) @@ -10610,57 +8676,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_269 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_270; -// synthesis translate_on -always @(*) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -// synthesis translate_off - dummy_d_270 = dummy_s; -// synthesis translate_on end assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1); assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1); @@ -10692,10 +8707,6 @@ assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_ma assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we); - -// synthesis translate_off -reg dummy_d_271; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_valids <= 8'd0; main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); @@ -10706,9 +8717,6 @@ always @(*) begin main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes)))); -// synthesis translate_off - dummy_d_271 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids; assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0; @@ -10717,49 +8725,24 @@ assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; - -// synthesis translate_off -reg dummy_d_272; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; end -// synthesis translate_off - dummy_d_272 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_273; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; end -// synthesis translate_off - dummy_d_273 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_274; -// synthesis translate_on always @(*) begin main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_cmd_cmd_valid) begin main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; end -// synthesis translate_off - dummy_d_274 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_275; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin @@ -10768,14 +8751,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin main_litedramcore_bankmachine0_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_275 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_276; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin @@ -10784,14 +8760,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin main_litedramcore_bankmachine1_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_276 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_277; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin @@ -10800,14 +8769,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin main_litedramcore_bankmachine2_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_277 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_278; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin @@ -10816,14 +8778,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin main_litedramcore_bankmachine3_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_278 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_279; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin @@ -10832,14 +8787,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin main_litedramcore_bankmachine4_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_279 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_280; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin @@ -10848,14 +8796,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin main_litedramcore_bankmachine5_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_280 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_281; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin @@ -10864,14 +8805,7 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin main_litedramcore_bankmachine6_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_281 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_282; -// synthesis translate_on always @(*) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin @@ -10880,15 +8814,8 @@ always @(*) begin if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin main_litedramcore_bankmachine7_cmd_ready <= 1'd1; end -// synthesis translate_off - dummy_d_282 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid)); - -// synthesis translate_off -reg dummy_d_283; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_valids <= 8'd0; main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); @@ -10899,9 +8826,6 @@ always @(*) begin main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes)))); -// synthesis translate_off - dummy_d_283 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids; assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6; @@ -10910,44 +8834,23 @@ assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; - -// synthesis translate_off -reg dummy_d_284; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3; end -// synthesis translate_off - dummy_d_284 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_285; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4; end -// synthesis translate_off - dummy_d_285 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on always @(*) begin main_litedramcore_choose_req_cmd_payload_we <= 1'd0; if (main_litedramcore_choose_req_cmd_valid) begin main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5; end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on end assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); assign main_litedramcore_dfi_p0_reset_n = 1'd1; @@ -10963,10 +8866,6 @@ assign main_litedramcore_dfi_p3_reset_n = 1'd1; assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}}; assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}}; assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on always @(*) begin builder_multiplexer_next_state <= 4'd0; builder_multiplexer_next_state <= builder_multiplexer_state; @@ -11023,18 +8922,15 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on always @(*) begin - main_litedramcore_en0 <= 1'd0; + main_litedramcore_choose_cmd_want_activates <= 1'd0; case (builder_multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end 2'd2: begin end @@ -11055,24 +8951,23 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; + end end endcase -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_289; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + main_litedramcore_steerer_sel3 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_wrcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end 2'd2: begin @@ -11094,22 +8989,18 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + main_litedramcore_steerer_sel3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 2'd2; + end + if ((main_litedramcore_rdcmdphase == 2'd3)) begin + main_litedramcore_steerer_sel3 <= 1'd1; end end endcase -// synthesis translate_off - dummy_d_289 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_290; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_want_reads <= 1'd0; + main_litedramcore_en0 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin end @@ -11132,22 +9023,18 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_choose_req_want_reads <= 1'd1; + main_litedramcore_en0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_290 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_291; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_want_writes <= 1'd0; + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end 2'd2: begin end @@ -11168,25 +9055,17 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end end endcase -// synthesis translate_off - dummy_d_291 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_292; -// synthesis translate_on always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; + main_litedramcore_choose_req_want_reads <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end end 2'd2: begin end @@ -11207,32 +9086,15 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end + main_litedramcore_choose_req_want_reads <= 1'd1; end endcase -// synthesis translate_off - dummy_d_292 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_293; -// synthesis translate_on always @(*) begin - main_litedramcore_steerer_sel3 <= 2'd0; + main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer_sel3 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 2'd2; - end - if ((main_litedramcore_wrcmdphase == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 1'd1; - end + main_litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -11253,23 +9115,46 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer_sel3 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 2'd2; + end + endcase +end +always @(*) begin + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end - if ((main_litedramcore_rdcmdphase == 2'd3)) begin - main_litedramcore_steerer_sel3 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; end end endcase -// synthesis translate_off - dummy_d_293 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_294; -// synthesis translate_on always @(*) begin main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) @@ -11297,14 +9182,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_294 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_295; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel0 <= 2'd0; case (builder_multiplexer_state) @@ -11346,14 +9224,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_295 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_296; -// synthesis translate_on always @(*) begin main_litedramcore_cmd_ready <= 1'd0; case (builder_multiplexer_state) @@ -11381,14 +9252,7 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_296 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_297; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel1 <= 2'd0; case (builder_multiplexer_state) @@ -11429,14 +9293,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_297 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_298; -// synthesis translate_on always @(*) begin main_litedramcore_steerer_sel2 <= 2'd0; case (builder_multiplexer_state) @@ -11477,51 +9334,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_298 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_299; -// synthesis translate_on -always @(*) begin - main_litedramcore_choose_cmd_want_activates <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed; - end - end - endcase -// synthesis translate_off - dummy_d_299 = dummy_s; -// synthesis translate_on end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); @@ -11566,10 +9378,6 @@ assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35; assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready)); assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; - -// synthesis translate_off -reg dummy_d_300; -// synthesis translate_on always @(*) begin main_litedramcore_interface_wdata <= 128'd0; case ({builder_new_master_wdata_ready1}) @@ -11580,14 +9388,7 @@ always @(*) begin main_litedramcore_interface_wdata <= 1'd0; end endcase -// synthesis translate_off - dummy_d_300 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_301; -// synthesis translate_on always @(*) begin main_litedramcore_interface_wdata_we <= 16'd0; case ({builder_new_master_wdata_ready1}) @@ -11598,9 +9399,6 @@ always @(*) begin main_litedramcore_interface_wdata_we <= 1'd0; end endcase -// synthesis translate_off - dummy_d_301 = dummy_s; -// synthesis translate_on end assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata; assign builder_roundrobin0_grant = 1'd0; @@ -11611,10 +9409,6 @@ assign builder_roundrobin4_grant = 1'd0; assign builder_roundrobin5_grant = 1'd0; assign builder_roundrobin6_grant = 1'd0; assign builder_roundrobin7_grant = 1'd0; - -// synthesis translate_off -reg dummy_d_302; -// synthesis translate_on always @(*) begin builder_next_state <= 2'd0; builder_next_state <= builder_state; @@ -11631,16 +9425,9 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_302 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_303; -// synthesis translate_on always @(*) begin - builder_litedramcore_dat_w_next_value0 <= 8'd0; + builder_litedramcore_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin end @@ -11650,14 +9437,7 @@ always @(*) begin builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w; end endcase -// synthesis translate_off - dummy_d_303 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_304; -// synthesis translate_on always @(*) begin builder_litedramcore_dat_w_next_value_ce0 <= 1'd0; case (builder_state) @@ -11669,14 +9449,19 @@ always @(*) begin builder_litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase -// synthesis translate_off - dummy_d_304 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_305; -// synthesis translate_on +always @(*) begin + builder_litedramcore_wishbone_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end always @(*) begin builder_litedramcore_adr_next_value1 <= 14'd0; case (builder_state) @@ -11691,14 +9476,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_305 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_306; -// synthesis translate_on always @(*) begin builder_litedramcore_adr_next_value_ce1 <= 1'd0; case (builder_state) @@ -11713,14 +9491,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_306 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_307; -// synthesis translate_on always @(*) begin builder_litedramcore_we_next_value2 <= 1'd0; case (builder_state) @@ -11735,14 +9506,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_307 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_308; -// synthesis translate_on always @(*) begin builder_litedramcore_we_next_value_ce2 <= 1'd0; case (builder_state) @@ -11757,14 +9521,7 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_308 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_309; -// synthesis translate_on always @(*) begin builder_litedramcore_wishbone_dat_r <= 32'd0; case (builder_state) @@ -11776,28 +9533,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_309 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_310; -// synthesis translate_on -always @(*) begin - builder_litedramcore_wishbone_ack <= 1'd0; - case (builder_state) - 1'd1: begin - end - 2'd2: begin - builder_litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_310 = dummy_s; -// synthesis translate_on end assign builder_litedramcore_wishbone_adr = main_wb_bus_adr; assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w; @@ -11810,414 +9545,204 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we; assign builder_litedramcore_wishbone_cti = main_wb_bus_cti; assign builder_litedramcore_wishbone_bte = main_wb_bus_bte; assign main_wb_bus_err = builder_litedramcore_wishbone_err; -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_311; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; + builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_311 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_312; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_done0_we <= 1'd0; + builder_csrbank0_init_done0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_312 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_313; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); end -// synthesis translate_off - dummy_d_313 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_314; -// synthesis translate_on always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end -// synthesis translate_off - dummy_d_314 = dummy_s; -// synthesis translate_on end assign builder_csrbank0_init_done0_w = main_init_done_storage; assign builder_csrbank0_init_error0_w = main_init_error_storage; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_315; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_315 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_316; -// synthesis translate_on always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_316 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; - -// synthesis translate_off -reg dummy_d_317; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_317 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_318; -// synthesis translate_on always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_318 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_319; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_319 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_320; -// synthesis translate_on always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_320 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_321; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_321 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_322; -// synthesis translate_on always @(*) begin main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_322 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_323; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_323 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_324; -// synthesis translate_on always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_324 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_325; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_325 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_326; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_326 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_327; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_327 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_328; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_328 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_329; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_329 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_330; -// synthesis translate_on always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_330 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_331; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_331 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_332; -// synthesis translate_on always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_332 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_333; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_333 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_334; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_334 = dummy_s; -// synthesis translate_on end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_335; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_335 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_336; -// synthesis translate_on always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_336 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_337; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_337 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_338; -// synthesis translate_on always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_338 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; - -// synthesis translate_off -reg dummy_d_339; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); end -// synthesis translate_off - dummy_d_339 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_340; -// synthesis translate_on always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end -// synthesis translate_off - dummy_d_340 = dummy_s; -// synthesis translate_on end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; @@ -12225,1437 +9750,331 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; - -// synthesis translate_off -reg dummy_d_341; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_control0_we <= 1'd0; + builder_csrbank2_dfii_control0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_341 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_342; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_control0_re <= 1'd0; + builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_342 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_343; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_re <= 1'd0; + builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_343 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_344; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_command0_we <= 1'd0; + builder_csrbank2_dfii_pi0_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_344 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_345; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_345 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_346; -// synthesis translate_on always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_346 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_347; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address1_we <= 1'd0; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_347 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_348; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address1_re <= 1'd0; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_348 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_349; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_349 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_350; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_350 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_351; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_351 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_352; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_352 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_353; -// synthesis translate_on +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0; + builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_353 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_354; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0; + builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_354 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_355; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_355 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_356; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_356 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_357; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_357 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_358; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_358 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_359; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_359 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_360; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_360 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_361; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_361 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_362; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_362 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_363; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_363 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_364; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_364 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_365; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_365 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_366; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_366 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_367; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_367 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_368; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_368 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_369; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_369 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_370; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_370 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_371; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_371 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_372; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_372 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_373; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin + main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_373 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_374; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - builder_csrbank2_dfii_pi1_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_374 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_375; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_375 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_376; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_376 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_377; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_377 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_378; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_378 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_379; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_379 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_380; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_380 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_381; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_381 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_382; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_382 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_383; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_383 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_384; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_384 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_385; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_385 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_386; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_386 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_387; -// synthesis translate_on +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_387 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_388; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_388 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_389; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_389 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_390; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_390 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_391; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_391 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_392; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_392 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_393; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_393 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_394; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_394 = dummy_s; -// synthesis translate_on end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_395; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_395 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_396; -// synthesis translate_on always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_396 = dummy_s; -// synthesis translate_on end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_397; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_397 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_398; -// synthesis translate_on always @(*) begin main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_398 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_399; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_399 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_400; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi2_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin + main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_400 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_401; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin - builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_401 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_402; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_402 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_403; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_403 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_404; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_404 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_405; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_405 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_406; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_406 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_407; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_407 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_408; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin - builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_408 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_409; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_409 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_410; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_410 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_411; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_411 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_412; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_412 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_413; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_413 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_414; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin - builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_414 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_415; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_415 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_416; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin - builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_416 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_417; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_417 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_418; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin - builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_418 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_419; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_419 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_420; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin - builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_420 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_421; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_421 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_422; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_422 = dummy_s; -// synthesis translate_on -end -assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; - -// synthesis translate_off -reg dummy_d_423; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_423 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_424; -// synthesis translate_on -always @(*) begin - main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin - main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_424 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[5:0]; - -// synthesis translate_off -reg dummy_d_425; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we); - end -// synthesis translate_off - dummy_d_425 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_426; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin - builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_426 = dummy_s; -// synthesis translate_on -end -assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_427; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; - end -// synthesis translate_off - dummy_d_427 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_428; -// synthesis translate_on -always @(*) begin - builder_csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_428 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; - -// synthesis translate_off -reg dummy_d_429; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_429 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_430; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_430 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_431; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_431 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_432; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin - builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin + builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_432 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_433; -// synthesis translate_on +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_433 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_434; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin - builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin + builder_csrbank2_dfii_pi2_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_434 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_435; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_435 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_436; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin + builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_436 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_437; -// synthesis translate_on +assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_437 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_438; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin - builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_438 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_439; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_439 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_440; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin - builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin + builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_440 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_441; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_441 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_442; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin - builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_442 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_443; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_443 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_444; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin - builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin + builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_444 = dummy_s; -// synthesis translate_on end -assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0]; - -// synthesis translate_off -reg dummy_d_445; -// synthesis translate_on +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); end -// synthesis translate_off - dummy_d_445 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_446; -// synthesis translate_on always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin - builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin + builder_csrbank2_dfii_pi3_rddata_re <= builder_interface2_bank_bus_we; end -// synthesis translate_off - dummy_d_446 = dummy_s; -// synthesis translate_on end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; @@ -13663,57 +10082,29 @@ assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0]; -assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[13:8]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0]; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0]; assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0]; -assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0]; -assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[13:8]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0]; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0]; assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0]; -assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0]; -assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[13:8]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0]; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0]; assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0]; -assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0]; -assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[13:8]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0]; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0]; assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24]; -assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16]; -assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0]; -assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24]; -assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16]; -assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8]; -assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0]; -assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_csr_interconnect_adr = builder_litedramcore_adr; assign builder_csr_interconnect_we = builder_litedramcore_we; assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w; @@ -13728,10 +10119,6 @@ assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); - -// synthesis translate_off -reg dummy_d_447; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13760,14 +10147,7 @@ always @(*) begin builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7]; end endcase -// synthesis translate_off - dummy_d_447 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_448; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed1 <= 14'd0; case (main_litedramcore_choose_cmd_grant) @@ -13796,14 +10176,7 @@ always @(*) begin builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_448 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_449; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed2 <= 3'd0; case (main_litedramcore_choose_cmd_grant) @@ -13832,14 +10205,7 @@ always @(*) begin builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_449 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_450; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed3 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13868,14 +10234,7 @@ always @(*) begin builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_450 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_451; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed4 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13904,14 +10263,7 @@ always @(*) begin builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_451 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_452; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed5 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13940,14 +10292,7 @@ always @(*) begin builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_452 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_453; -// synthesis translate_on always @(*) begin builder_t_array_muxed0 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -13976,14 +10321,7 @@ always @(*) begin builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_453 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_454; -// synthesis translate_on always @(*) begin builder_t_array_muxed1 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14012,14 +10350,7 @@ always @(*) begin builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_454 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_455; -// synthesis translate_on always @(*) begin builder_t_array_muxed2 <= 1'd0; case (main_litedramcore_choose_cmd_grant) @@ -14048,14 +10379,7 @@ always @(*) begin builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_455 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_456; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed6 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14084,14 +10408,7 @@ always @(*) begin builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7]; end endcase -// synthesis translate_off - dummy_d_456 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_457; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed7 <= 14'd0; case (main_litedramcore_choose_req_grant) @@ -14120,14 +10437,7 @@ always @(*) begin builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_457 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_458; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed8 <= 3'd0; case (main_litedramcore_choose_req_grant) @@ -14156,14 +10466,7 @@ always @(*) begin builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba; end endcase -// synthesis translate_off - dummy_d_458 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_459; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed9 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14192,14 +10495,7 @@ always @(*) begin builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read; end endcase -// synthesis translate_off - dummy_d_459 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_460; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed10 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14228,14 +10524,7 @@ always @(*) begin builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write; end endcase -// synthesis translate_off - dummy_d_460 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_461; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed11 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14264,14 +10553,7 @@ always @(*) begin builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase -// synthesis translate_off - dummy_d_461 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_462; -// synthesis translate_on always @(*) begin builder_t_array_muxed3 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14300,14 +10582,7 @@ always @(*) begin builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas; end endcase -// synthesis translate_off - dummy_d_462 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_463; -// synthesis translate_on always @(*) begin builder_t_array_muxed4 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14336,14 +10611,7 @@ always @(*) begin builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras; end endcase -// synthesis translate_off - dummy_d_463 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_464; -// synthesis translate_on always @(*) begin builder_t_array_muxed5 <= 1'd0; case (main_litedramcore_choose_req_grant) @@ -14372,14 +10640,7 @@ always @(*) begin builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_464 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_465; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed12 <= 21'd0; case (builder_roundrobin0_grant) @@ -14387,14 +10648,7 @@ always @(*) begin builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_465 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_466; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed13 <= 1'd0; case (builder_roundrobin0_grant) @@ -14402,14 +10656,7 @@ always @(*) begin builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_466 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_467; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed14 <= 1'd0; case (builder_roundrobin0_grant) @@ -14417,14 +10664,7 @@ always @(*) begin builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_467 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_468; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed15 <= 21'd0; case (builder_roundrobin1_grant) @@ -14432,14 +10672,7 @@ always @(*) begin builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_468 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_469; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed16 <= 1'd0; case (builder_roundrobin1_grant) @@ -14447,14 +10680,7 @@ always @(*) begin builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_469 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_470; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed17 <= 1'd0; case (builder_roundrobin1_grant) @@ -14462,14 +10688,7 @@ always @(*) begin builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_470 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_471; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed18 <= 21'd0; case (builder_roundrobin2_grant) @@ -14477,14 +10696,7 @@ always @(*) begin builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_471 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_472; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed19 <= 1'd0; case (builder_roundrobin2_grant) @@ -14492,14 +10704,7 @@ always @(*) begin builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_472 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_473; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed20 <= 1'd0; case (builder_roundrobin2_grant) @@ -14507,14 +10712,7 @@ always @(*) begin builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_473 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_474; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed21 <= 21'd0; case (builder_roundrobin3_grant) @@ -14522,14 +10720,7 @@ always @(*) begin builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_474 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_475; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed22 <= 1'd0; case (builder_roundrobin3_grant) @@ -14537,14 +10728,7 @@ always @(*) begin builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_475 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_476; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed23 <= 1'd0; case (builder_roundrobin3_grant) @@ -14552,14 +10736,7 @@ always @(*) begin builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_476 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_477; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed24 <= 21'd0; case (builder_roundrobin4_grant) @@ -14567,14 +10744,7 @@ always @(*) begin builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_477 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_478; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed25 <= 1'd0; case (builder_roundrobin4_grant) @@ -14582,14 +10752,7 @@ always @(*) begin builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_478 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_479; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed26 <= 1'd0; case (builder_roundrobin4_grant) @@ -14597,14 +10760,7 @@ always @(*) begin builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_479 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_480; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed27 <= 21'd0; case (builder_roundrobin5_grant) @@ -14612,14 +10768,7 @@ always @(*) begin builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_480 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_481; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed28 <= 1'd0; case (builder_roundrobin5_grant) @@ -14627,14 +10776,7 @@ always @(*) begin builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_481 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_482; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed29 <= 1'd0; case (builder_roundrobin5_grant) @@ -14642,14 +10784,7 @@ always @(*) begin builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_482 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_483; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed30 <= 21'd0; case (builder_roundrobin6_grant) @@ -14657,14 +10792,7 @@ always @(*) begin builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_483 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_484; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed31 <= 1'd0; case (builder_roundrobin6_grant) @@ -14672,14 +10800,7 @@ always @(*) begin builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_484 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_485; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed32 <= 1'd0; case (builder_roundrobin6_grant) @@ -14687,14 +10808,7 @@ always @(*) begin builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_485 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_486; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed33 <= 21'd0; case (builder_roundrobin7_grant) @@ -14702,14 +10816,7 @@ always @(*) begin builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]}; end endcase -// synthesis translate_off - dummy_d_486 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_487; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed34 <= 1'd0; case (builder_roundrobin7_grant) @@ -14717,14 +10824,7 @@ always @(*) begin builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we; end endcase -// synthesis translate_off - dummy_d_487 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_488; -// synthesis translate_on always @(*) begin builder_rhs_array_muxed35 <= 1'd0; case (builder_roundrobin7_grant) @@ -14732,14 +10832,7 @@ always @(*) begin builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid); end endcase -// synthesis translate_off - dummy_d_488 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_489; -// synthesis translate_on always @(*) begin builder_array_muxed0 <= 3'd0; case (main_litedramcore_steerer_sel0) @@ -14756,14 +10849,7 @@ always @(*) begin builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_489 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_490; -// synthesis translate_on always @(*) begin builder_array_muxed1 <= 14'd0; case (main_litedramcore_steerer_sel0) @@ -14780,14 +10866,7 @@ always @(*) begin builder_array_muxed1 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_490 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_491; -// synthesis translate_on always @(*) begin builder_array_muxed2 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14804,14 +10883,7 @@ always @(*) begin builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_491 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_492; -// synthesis translate_on always @(*) begin builder_array_muxed3 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14828,14 +10900,7 @@ always @(*) begin builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_492 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_493; -// synthesis translate_on always @(*) begin builder_array_muxed4 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14852,14 +10917,7 @@ always @(*) begin builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_493 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_494; -// synthesis translate_on always @(*) begin builder_array_muxed5 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14876,14 +10934,7 @@ always @(*) begin builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_494 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_495; -// synthesis translate_on always @(*) begin builder_array_muxed6 <= 1'd0; case (main_litedramcore_steerer_sel0) @@ -14900,14 +10951,7 @@ always @(*) begin builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_495 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_496; -// synthesis translate_on always @(*) begin builder_array_muxed7 <= 3'd0; case (main_litedramcore_steerer_sel1) @@ -14924,14 +10968,7 @@ always @(*) begin builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_496 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_497; -// synthesis translate_on always @(*) begin builder_array_muxed8 <= 14'd0; case (main_litedramcore_steerer_sel1) @@ -14948,14 +10985,7 @@ always @(*) begin builder_array_muxed8 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_497 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_498; -// synthesis translate_on always @(*) begin builder_array_muxed9 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14972,14 +11002,7 @@ always @(*) begin builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_498 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_499; -// synthesis translate_on always @(*) begin builder_array_muxed10 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -14996,14 +11019,7 @@ always @(*) begin builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_499 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_500; -// synthesis translate_on always @(*) begin builder_array_muxed11 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15020,14 +11036,7 @@ always @(*) begin builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_500 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_501; -// synthesis translate_on always @(*) begin builder_array_muxed12 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15044,14 +11053,7 @@ always @(*) begin builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_501 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_502; -// synthesis translate_on always @(*) begin builder_array_muxed13 <= 1'd0; case (main_litedramcore_steerer_sel1) @@ -15068,14 +11070,7 @@ always @(*) begin builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_502 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_503; -// synthesis translate_on always @(*) begin builder_array_muxed14 <= 3'd0; case (main_litedramcore_steerer_sel2) @@ -15092,14 +11087,7 @@ always @(*) begin builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_503 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_504; -// synthesis translate_on always @(*) begin builder_array_muxed15 <= 14'd0; case (main_litedramcore_steerer_sel2) @@ -15116,14 +11104,7 @@ always @(*) begin builder_array_muxed15 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_504 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_505; -// synthesis translate_on always @(*) begin builder_array_muxed16 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15140,14 +11121,7 @@ always @(*) begin builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_505 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_506; -// synthesis translate_on always @(*) begin builder_array_muxed17 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15164,14 +11138,7 @@ always @(*) begin builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_506 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_507; -// synthesis translate_on always @(*) begin builder_array_muxed18 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15188,14 +11155,7 @@ always @(*) begin builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_507 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_508; -// synthesis translate_on always @(*) begin builder_array_muxed19 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15212,14 +11172,7 @@ always @(*) begin builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_508 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_509; -// synthesis translate_on always @(*) begin builder_array_muxed20 <= 1'd0; case (main_litedramcore_steerer_sel2) @@ -15236,14 +11189,7 @@ always @(*) begin builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_509 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_510; -// synthesis translate_on always @(*) begin builder_array_muxed21 <= 3'd0; case (main_litedramcore_steerer_sel3) @@ -15260,14 +11206,7 @@ always @(*) begin builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0]; end endcase -// synthesis translate_off - dummy_d_510 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_511; -// synthesis translate_on always @(*) begin builder_array_muxed22 <= 14'd0; case (main_litedramcore_steerer_sel3) @@ -15284,14 +11223,7 @@ always @(*) begin builder_array_muxed22 <= main_litedramcore_cmd_payload_a; end endcase -// synthesis translate_off - dummy_d_511 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_512; -// synthesis translate_on always @(*) begin builder_array_muxed23 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15308,14 +11240,7 @@ always @(*) begin builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas); end endcase -// synthesis translate_off - dummy_d_512 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_513; -// synthesis translate_on always @(*) begin builder_array_muxed24 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15332,14 +11257,7 @@ always @(*) begin builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras); end endcase -// synthesis translate_off - dummy_d_513 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_514; -// synthesis translate_on always @(*) begin builder_array_muxed25 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15356,14 +11274,7 @@ always @(*) begin builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we); end endcase -// synthesis translate_off - dummy_d_514 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_515; -// synthesis translate_on always @(*) begin builder_array_muxed26 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15380,14 +11291,7 @@ always @(*) begin builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read); end endcase -// synthesis translate_off - dummy_d_515 = dummy_s; -// synthesis translate_on end - -// synthesis translate_off -reg dummy_d_516; -// synthesis translate_on always @(*) begin builder_array_muxed27 <= 1'd0; case (main_litedramcore_steerer_sel3) @@ -15404,15 +11308,17 @@ always @(*) begin builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write); end endcase -// synthesis translate_off - dummy_d_516 = dummy_s; -// synthesis translate_on end assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge iodelay_clk) begin if ((main_reset_counter != 1'd0)) begin main_reset_counter <= (main_reset_counter - 1'd1); @@ -17108,154 +13014,70 @@ always @(posedge sys_clk) begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; end 3'd4: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata_w; end 3'd7: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; end 4'd8: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; end 4'd10: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata_w; end 4'd13: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; end 4'd14: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w; + builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; end 5'd16: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w; + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata_w; end 5'd19: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w; - end - 5'd20: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w; - end - 5'd21: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w; - end - 5'd22: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w; - end - 5'd23: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w; - end - 5'd24: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w; - end - 5'd25: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w; - end - 5'd26: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w; - end - 5'd27: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w; - end - 5'd28: begin - builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w; - end - 5'd29: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w; - end - 5'd30: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w; - end - 5'd31: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w; - end - 6'd32: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w; - end - 6'd33: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w; - end - 6'd34: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w; - end - 6'd35: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w; - end - 6'd36: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w; - end - 6'd37: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w; - end - 6'd38: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w; - end - 6'd39: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w; - end - 6'd40: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w; end - 6'd41: begin + 5'd20: begin builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w; end - 6'd42: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w; - end - 6'd43: begin + 5'd21: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w; end - 6'd44: begin + 5'd22: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w; end - 6'd45: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w; - end - 6'd46: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w; - end - 6'd47: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w; - end - 6'd48: begin + 5'd23: begin builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w; end - 6'd49: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w; - end - 6'd50: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w; - end - 6'd51: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w; - end - 6'd52: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w; + 5'd24: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata_w; end endcase end @@ -17267,118 +13089,70 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; - if (builder_csrbank2_dfii_pi0_address1_re) begin - main_litedramcore_phaseinjector0_address_storage[13:8] <= builder_csrbank2_dfii_pi0_address1_r; - end if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; - if (builder_csrbank2_dfii_pi0_wrdata3_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r; - end - if (builder_csrbank2_dfii_pi0_wrdata2_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r; - end - if (builder_csrbank2_dfii_pi0_wrdata1_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r; - end if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; - main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; + main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; - if (builder_csrbank2_dfii_pi1_address1_re) begin - main_litedramcore_phaseinjector1_address_storage[13:8] <= builder_csrbank2_dfii_pi1_address1_r; - end if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; - if (builder_csrbank2_dfii_pi1_wrdata3_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r; - end - if (builder_csrbank2_dfii_pi1_wrdata2_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r; - end - if (builder_csrbank2_dfii_pi1_wrdata1_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r; - end if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; - main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; + main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; - if (builder_csrbank2_dfii_pi2_address1_re) begin - main_litedramcore_phaseinjector2_address_storage[13:8] <= builder_csrbank2_dfii_pi2_address1_r; - end if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; - if (builder_csrbank2_dfii_pi2_wrdata3_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r; - end - if (builder_csrbank2_dfii_pi2_wrdata2_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r; - end - if (builder_csrbank2_dfii_pi2_wrdata1_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r; - end if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; - main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; + main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; - if (builder_csrbank2_dfii_pi3_address1_re) begin - main_litedramcore_phaseinjector3_address_storage[13:8] <= builder_csrbank2_dfii_pi3_address1_r; - end if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; - if (builder_csrbank2_dfii_pi3_wrdata3_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r; - end - if (builder_csrbank2_dfii_pi3_wrdata2_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r; - end - if (builder_csrbank2_dfii_pi3_wrdata1_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r; - end if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; - main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re; + main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin main_a7ddrphy_rst_storage <= 1'd0; main_a7ddrphy_rst_re <= 1'd0; @@ -17674,6 +13448,11 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + BUFG BUFG( .I(main_clkout0), .O(main_clkout_buf0) @@ -19581,118 +15360,150 @@ IOBUF IOBUF_15( .O(main_a7ddrphy_dq_i_nodelay15) ); +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage[0:15]; -reg [23:0] memdat; +reg [23:0] storage_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + storage_dat0 <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_1[0:15]; -reg [23:0] memdat_1; +reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + storage_1_dat0 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_2[0:15]; -reg [23:0] memdat_2; +reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + storage_2_dat0 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_3: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_3[0:15]; -reg [23:0] memdat_3; +reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + storage_3_dat0 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_4: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_4[0:15]; -reg [23:0] memdat_4; +reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + storage_4_dat0 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_5: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_5[0:15]; -reg [23:0] memdat_5; +reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + storage_5_dat0 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_6: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_6[0:15]; -reg [23:0] memdat_6; +reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + storage_6_dat0 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_7: 16-words x 24-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 24 +// Port 1 | Read: Async | Write: ---- | reg [23:0] storage_7[0:15]; -reg [23:0] memdat_7; +reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + storage_7_dat0 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + FD FD( .C(main_clkin), .D(main_reset), @@ -19849,3 +15660,7 @@ PLLE2_ADV #( ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 08:32:15. +//------------------------------------------------------------------------------ diff --git a/litesdcard/gen-src/generate.sh b/litesdcard/gen-src/generate.sh index 9f033fe..732df6b 100755 --- a/litesdcard/gen-src/generate.sh +++ b/litesdcard/gen-src/generate.sh @@ -1,6 +1,7 @@ #!/bin/bash -VENDORS="xilinx" +# vendor:sysclk +VENDORS="xilinx:100 lattice:48" ME=$(realpath $0) echo ME=$ME @@ -13,8 +14,10 @@ mkdir -p $BUILD_PATH GEN_PATH=$PARENT_PATH/generated mkdir -p $GEN_PATH -for i in $VENDORS +for i_clk in $VENDORS do + i=$(echo $i_clk | cut -d : -f 1) + clk=$(echo $i_clk | cut -d : -f 2) TARGET_BUILD_PATH=$BUILD_PATH/$i TARGET_GEN_PATH=$GEN_PATH/$i rm -rf $TARGET_BUILD_PATH @@ -22,8 +25,8 @@ do mkdir -p $TARGET_BUILD_PATH mkdir -p $TARGET_GEN_PATH - echo "Generating $i in $TARGET_BUILD_PATH" - (cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i) + echo "Generating $i in $TARGET_BUILD_PATH" + (cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i --clk-freq $clk) cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/ done diff --git a/litesdcard/generated/lattice/litesdcard_core.v b/litesdcard/generated/lattice/litesdcard_core.v new file mode 100644 index 0000000..d0d51cb --- /dev/null +++ b/litesdcard/generated/lattice/litesdcard_core.v @@ -0,0 +1,4288 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litesdcard_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 07:30:20 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litesdcard_core ( + input wire clk, + input wire rst, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire [29:0] wb_dma_adr, + output wire [31:0] wb_dma_dat_w, + input wire [31:0] wb_dma_dat_r, + output wire [3:0] wb_dma_sel, + output wire wb_dma_cyc, + output wire wb_dma_stb, + input wire wb_dma_ack, + output wire wb_dma_we, + output wire [2:0] wb_dma_cti, + output wire [1:0] wb_dma_bte, + input wire wb_dma_err, + inout wire [3:0] sdcard_data, + inout wire sdcard_cmd, + output wire sdcard_clk, + input wire sdcard_cd, + output wire irq +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire sys_clk; +wire sys_rst; +wire por_clk; +reg int_rst = 1'd1; +reg soc_rst = 1'd0; +wire cpu_rst; +reg [1:0] reset_storage = 2'd0; +reg reset_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg scratch_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg bus_errors_re = 1'd0; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +wire [29:0] wb_ctrl_adr_1; +wire [31:0] wb_ctrl_dat_w_1; +wire [31:0] wb_ctrl_dat_r_1; +wire [3:0] wb_ctrl_sel_1; +wire wb_ctrl_cyc_1; +wire wb_ctrl_stb_1; +wire wb_ctrl_ack_1; +wire wb_ctrl_we_1; +wire [2:0] wb_ctrl_cti_1; +wire [1:0] wb_ctrl_bte_1; +wire wb_ctrl_err_1; +wire [29:0] wb_dma_adr_1; +wire [31:0] wb_dma_dat_w_1; +wire [31:0] wb_dma_dat_r_1; +wire [3:0] wb_dma_sel_1; +wire wb_dma_cyc_1; +wire wb_dma_stb_1; +wire wb_dma_ack_1; +wire wb_dma_we_1; +wire [2:0] wb_dma_cti_1; +wire [1:0] wb_dma_bte_1; +wire wb_dma_err_1; +wire card_detect_status0; +wire card_detect_we; +reg card_detect_re = 1'd0; +reg [8:0] clocker_storage = 9'd256; +reg clocker_re = 1'd0; +wire clocker_stop; +wire clocker_ce; +wire clocker_clk_en; +wire clocker_clk0; +reg [8:0] clocker_clks = 9'd0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +reg init_initialize_re = 1'd0; +wire init_initialize_r; +reg init_initialize_we = 1'd0; +reg init_initialize_w = 1'd0; +wire init_pads_in_valid; +wire init_pads_in_payload_cmd_i; +wire [3:0] init_pads_in_payload_data_i; +wire init_pads_out_ready; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +reg [7:0] init_count = 8'd0; +wire cmdw_pads_in_valid; +wire cmdw_pads_in_payload_cmd_i; +wire [3:0] cmdw_pads_in_payload_data_i; +wire cmdw_pads_out_ready; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_last = 1'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg cmdw_done = 1'd0; +reg [7:0] cmdw_count = 8'd0; +wire cmdr_pads_in_pads_in_valid; +wire cmdr_pads_in_pads_in_ready; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +wire cmdr_pads_in_pads_in_payload_cmd_i; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] cmdr_pads_in_pads_in_payload_data_i; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +wire cmdr_pads_out_ready; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_sink_ready = 1'd0; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_source_valid = 1'd0; +reg cmdr_source_ready = 1'd0; +reg cmdr_source_last = 1'd0; +reg [7:0] cmdr_source_payload_data = 8'd0; +reg [2:0] cmdr_source_payload_status = 3'd0; +reg [31:0] cmdr_timeout = 32'd48; +reg [7:0] cmdr_count = 8'd0; +reg cmdr_busy = 1'd0; +wire cmdr_cmdr_pads_in_valid; +reg cmdr_cmdr_pads_in_ready = 1'd0; +wire cmdr_cmdr_pads_in_first; +wire cmdr_cmdr_pads_in_last; +wire cmdr_cmdr_pads_in_payload_clk; +wire cmdr_cmdr_pads_in_payload_cmd_i; +wire cmdr_cmdr_pads_in_payload_cmd_o; +wire cmdr_cmdr_pads_in_payload_cmd_oe; +wire [3:0] cmdr_cmdr_pads_in_payload_data_i; +wire [3:0] cmdr_cmdr_pads_in_payload_data_o; +wire cmdr_cmdr_pads_in_payload_data_oe; +wire cmdr_cmdr_pads_in_payload_data_i_ce; +wire cmdr_cmdr_source_source_valid0; +reg cmdr_cmdr_source_source_ready0 = 1'd0; +wire cmdr_cmdr_source_source_first0; +wire cmdr_cmdr_source_source_last0; +wire [7:0] cmdr_cmdr_source_source_payload_data0; +wire cmdr_cmdr_start; +reg cmdr_cmdr_run = 1'd0; +wire cmdr_cmdr_converter_sink_valid; +wire cmdr_cmdr_converter_sink_ready; +reg cmdr_cmdr_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_sink_last = 1'd0; +wire cmdr_cmdr_converter_sink_payload_data; +wire cmdr_cmdr_converter_source_valid; +wire cmdr_cmdr_converter_source_ready; +reg cmdr_cmdr_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_source_payload_valid_token_count = 4'd0; +reg [2:0] cmdr_cmdr_converter_demux = 3'd0; +wire cmdr_cmdr_converter_load_part; +reg cmdr_cmdr_converter_strobe_all = 1'd0; +wire cmdr_cmdr_source_source_valid1; +wire cmdr_cmdr_source_source_ready1; +wire cmdr_cmdr_source_source_first1; +wire cmdr_cmdr_source_source_last1; +wire [7:0] cmdr_cmdr_source_source_payload_data1; +wire cmdr_cmdr_buf_sink_valid; +wire cmdr_cmdr_buf_sink_ready; +wire cmdr_cmdr_buf_sink_first; +wire cmdr_cmdr_buf_sink_last; +wire [7:0] cmdr_cmdr_buf_sink_payload_data; +reg cmdr_cmdr_buf_source_valid = 1'd0; +wire cmdr_cmdr_buf_source_ready; +reg cmdr_cmdr_buf_source_first = 1'd0; +reg cmdr_cmdr_buf_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_source_payload_data = 8'd0; +reg cmdr_cmdr_reset = 1'd0; +wire dataw_pads_in_pads_in_valid; +reg dataw_pads_in_pads_in_ready = 1'd0; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; +wire dataw_pads_in_pads_in_payload_cmd_i; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] dataw_pads_in_pads_in_payload_data_i; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +wire dataw_pads_out_ready; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +reg dataw_sink_valid = 1'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_stop = 1'd0; +wire dataw_accepted0; +wire dataw_crc_error0; +wire dataw_write_error0; +reg [2:0] dataw_status = 3'd0; +wire dataw_we; +reg dataw_re = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg dataw_accepted1 = 1'd0; +reg dataw_crc_error1 = 1'd0; +reg dataw_write_error1 = 1'd0; +wire dataw_crc_pads_in_valid; +wire dataw_crc_pads_in_ready; +wire dataw_crc_pads_in_first; +wire dataw_crc_pads_in_last; +wire dataw_crc_pads_in_payload_clk; +wire dataw_crc_pads_in_payload_cmd_i; +wire dataw_crc_pads_in_payload_cmd_o; +wire dataw_crc_pads_in_payload_cmd_oe; +wire [3:0] dataw_crc_pads_in_payload_data_i; +wire [3:0] dataw_crc_pads_in_payload_data_o; +wire dataw_crc_pads_in_payload_data_oe; +wire dataw_crc_pads_in_payload_data_i_ce; +wire dataw_crc_source_source_valid0; +reg dataw_crc_source_source_ready0 = 1'd0; +wire dataw_crc_source_source_first0; +wire dataw_crc_source_source_last0; +wire [7:0] dataw_crc_source_source_payload_data0; +wire dataw_crc_start; +reg dataw_crc_run = 1'd0; +wire dataw_crc_converter_sink_valid; +wire dataw_crc_converter_sink_ready; +reg dataw_crc_converter_sink_first = 1'd0; +reg dataw_crc_converter_sink_last = 1'd0; +wire dataw_crc_converter_sink_payload_data; +wire dataw_crc_converter_source_valid; +wire dataw_crc_converter_source_ready; +reg dataw_crc_converter_source_first = 1'd0; +reg dataw_crc_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_source_payload_valid_token_count = 4'd0; +reg [2:0] dataw_crc_converter_demux = 3'd0; +wire dataw_crc_converter_load_part; +reg dataw_crc_converter_strobe_all = 1'd0; +wire dataw_crc_source_source_valid1; +wire dataw_crc_source_source_ready1; +wire dataw_crc_source_source_first1; +wire dataw_crc_source_source_last1; +wire [7:0] dataw_crc_source_source_payload_data1; +wire dataw_crc_buf_sink_valid; +wire dataw_crc_buf_sink_ready; +wire dataw_crc_buf_sink_first; +wire dataw_crc_buf_sink_last; +wire [7:0] dataw_crc_buf_sink_payload_data; +reg dataw_crc_buf_source_valid = 1'd0; +wire dataw_crc_buf_source_ready; +reg dataw_crc_buf_source_first = 1'd0; +reg dataw_crc_buf_source_last = 1'd0; +reg [7:0] dataw_crc_buf_source_payload_data = 8'd0; +reg dataw_crc_reset = 1'd0; +wire datar_pads_in_pads_in_valid; +wire datar_pads_in_pads_in_ready; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; +wire datar_pads_in_pads_in_payload_cmd_i; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] datar_pads_in_pads_in_payload_data_i; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +wire datar_pads_out_ready; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_source_valid = 1'd0; +reg datar_source_ready = 1'd0; +reg datar_source_first = 1'd0; +reg datar_source_last = 1'd0; +reg [7:0] datar_source_payload_data = 8'd0; +reg [2:0] datar_source_payload_status = 3'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd48; +reg [9:0] datar_count = 10'd0; +wire datar_datar_pads_in_valid; +reg datar_datar_pads_in_ready = 1'd0; +wire datar_datar_pads_in_first; +wire datar_datar_pads_in_last; +wire datar_datar_pads_in_payload_clk; +wire datar_datar_pads_in_payload_cmd_i; +wire datar_datar_pads_in_payload_cmd_o; +wire datar_datar_pads_in_payload_cmd_oe; +wire [3:0] datar_datar_pads_in_payload_data_i; +wire [3:0] datar_datar_pads_in_payload_data_o; +wire datar_datar_pads_in_payload_data_oe; +wire datar_datar_pads_in_payload_data_i_ce; +wire datar_datar_source_source_valid0; +reg datar_datar_source_source_ready0 = 1'd0; +wire datar_datar_source_source_first0; +wire datar_datar_source_source_last0; +wire [7:0] datar_datar_source_source_payload_data0; +wire datar_datar_start; +reg datar_datar_run = 1'd0; +wire datar_datar_converter_sink_valid; +wire datar_datar_converter_sink_ready; +reg datar_datar_converter_sink_first = 1'd0; +reg datar_datar_converter_sink_last = 1'd0; +wire [3:0] datar_datar_converter_sink_payload_data; +wire datar_datar_converter_source_valid; +wire datar_datar_converter_source_ready; +reg datar_datar_converter_source_first = 1'd0; +reg datar_datar_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_source_payload_valid_token_count = 2'd0; +reg datar_datar_converter_demux = 1'd0; +wire datar_datar_converter_load_part; +reg datar_datar_converter_strobe_all = 1'd0; +wire datar_datar_source_source_valid1; +wire datar_datar_source_source_ready1; +wire datar_datar_source_source_first1; +wire datar_datar_source_source_last1; +wire [7:0] datar_datar_source_source_payload_data1; +wire datar_datar_buf_sink_valid; +wire datar_datar_buf_sink_ready; +wire datar_datar_buf_sink_first; +wire datar_datar_buf_sink_last; +wire [7:0] datar_datar_buf_sink_payload_data; +reg datar_datar_buf_source_valid = 1'd0; +wire datar_datar_buf_source_ready; +reg datar_datar_buf_source_first = 1'd0; +reg datar_datar_buf_source_last = 1'd0; +reg [7:0] datar_datar_buf_source_payload_data = 8'd0; +reg datar_datar_reset = 1'd0; +wire sdpads_clk; +wire sdpads_cmd_i; +wire sdpads_cmd_o; +wire sdpads_cmd_oe; +wire [3:0] sdpads_data_i; +wire [3:0] sdpads_data_o; +wire sdpads_data_oe; +reg sdpads_data_i_ce = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +reg card_detect_irq = 1'd0; +reg card_detect_d = 1'd0; +wire sdcore_sink_sink_valid0; +wire sdcore_sink_sink_ready0; +wire sdcore_sink_sink_first0; +wire sdcore_sink_sink_last0; +wire [7:0] sdcore_sink_sink_payload_data0; +wire sdcore_source_source_valid0; +wire sdcore_source_source_ready0; +wire sdcore_source_source_first0; +wire sdcore_source_source_last0; +wire [7:0] sdcore_source_source_payload_data0; +reg [31:0] sdcore_cmd_argument_storage = 32'd0; +reg sdcore_cmd_argument_re = 1'd0; +wire [1:0] sdcore_csrfield_cmd_type; +wire [1:0] sdcore_csrfield_data_type; +wire [5:0] sdcore_csrfield_cmd; +reg [13:0] sdcore_cmd_command_storage = 14'd0; +reg sdcore_cmd_command_re = 1'd0; +reg sdcore_cmd_send_storage = 1'd0; +reg sdcore_cmd_send_re = 1'd0; +reg [127:0] sdcore_cmd_response_status = 128'd0; +wire sdcore_cmd_response_we; +reg sdcore_cmd_response_re = 1'd0; +wire sdcore_csrfield_done0; +wire sdcore_csrfield_error0; +wire sdcore_csrfield_timeout0; +wire sdcore_csrfield_crc0; +reg [3:0] sdcore_cmd_event_status = 4'd0; +wire sdcore_cmd_event_we; +reg sdcore_cmd_event_re = 1'd0; +wire sdcore_csrfield_done1; +wire sdcore_csrfield_error1; +wire sdcore_csrfield_timeout1; +wire sdcore_csrfield_crc1; +reg [3:0] sdcore_data_event_status = 4'd0; +wire sdcore_data_event_we; +reg sdcore_data_event_re = 1'd0; +reg [9:0] sdcore_block_length_storage = 10'd0; +reg sdcore_block_length_re = 1'd0; +reg [31:0] sdcore_block_count_storage = 32'd0; +reg sdcore_block_count_re = 1'd0; +wire sdcore_crc7_inserter_reset; +wire sdcore_crc7_inserter_enable; +wire [39:0] sdcore_crc7_inserter_din; +reg [6:0] sdcore_crc7_inserter_crc = 7'd0; +reg [6:0] sdcore_crc7_inserter_reg0 = 7'd0; +wire [6:0] sdcore_crc7_inserter_reg1; +wire [6:0] sdcore_crc7_inserter_reg2; +wire [6:0] sdcore_crc7_inserter_reg3; +wire [6:0] sdcore_crc7_inserter_reg4; +wire [6:0] sdcore_crc7_inserter_reg5; +wire [6:0] sdcore_crc7_inserter_reg6; +wire [6:0] sdcore_crc7_inserter_reg7; +wire [6:0] sdcore_crc7_inserter_reg8; +wire [6:0] sdcore_crc7_inserter_reg9; +wire [6:0] sdcore_crc7_inserter_reg10; +wire [6:0] sdcore_crc7_inserter_reg11; +wire [6:0] sdcore_crc7_inserter_reg12; +wire [6:0] sdcore_crc7_inserter_reg13; +wire [6:0] sdcore_crc7_inserter_reg14; +wire [6:0] sdcore_crc7_inserter_reg15; +wire [6:0] sdcore_crc7_inserter_reg16; +wire [6:0] sdcore_crc7_inserter_reg17; +wire [6:0] sdcore_crc7_inserter_reg18; +wire [6:0] sdcore_crc7_inserter_reg19; +wire [6:0] sdcore_crc7_inserter_reg20; +wire [6:0] sdcore_crc7_inserter_reg21; +wire [6:0] sdcore_crc7_inserter_reg22; +wire [6:0] sdcore_crc7_inserter_reg23; +wire [6:0] sdcore_crc7_inserter_reg24; +wire [6:0] sdcore_crc7_inserter_reg25; +wire [6:0] sdcore_crc7_inserter_reg26; +wire [6:0] sdcore_crc7_inserter_reg27; +wire [6:0] sdcore_crc7_inserter_reg28; +wire [6:0] sdcore_crc7_inserter_reg29; +wire [6:0] sdcore_crc7_inserter_reg30; +wire [6:0] sdcore_crc7_inserter_reg31; +wire [6:0] sdcore_crc7_inserter_reg32; +wire [6:0] sdcore_crc7_inserter_reg33; +wire [6:0] sdcore_crc7_inserter_reg34; +wire [6:0] sdcore_crc7_inserter_reg35; +wire [6:0] sdcore_crc7_inserter_reg36; +wire [6:0] sdcore_crc7_inserter_reg37; +wire [6:0] sdcore_crc7_inserter_reg38; +wire [6:0] sdcore_crc7_inserter_reg39; +wire [6:0] sdcore_crc7_inserter_reg40; +wire sdcore_crc16_inserter_sink_valid; +reg sdcore_crc16_inserter_sink_ready = 1'd0; +wire sdcore_crc16_inserter_sink_first; +wire sdcore_crc16_inserter_sink_last; +wire [7:0] sdcore_crc16_inserter_sink_payload_data; +reg sdcore_crc16_inserter_source_valid = 1'd0; +reg sdcore_crc16_inserter_source_ready = 1'd0; +reg sdcore_crc16_inserter_source_first = 1'd0; +reg sdcore_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcore_crc16_inserter_source_payload_data = 8'd0; +reg [2:0] sdcore_crc16_inserter_count = 3'd0; +wire sdcore_crc16_inserter_crc0_reset; +wire sdcore_crc16_inserter_crc0_enable; +reg [1:0] sdcore_crc16_inserter_crc0_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc0_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc0_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc0_reg1; +wire [15:0] sdcore_crc16_inserter_crc0_reg2; +wire sdcore_crc16_inserter_crc1_reset; +wire sdcore_crc16_inserter_crc1_enable; +reg [1:0] sdcore_crc16_inserter_crc1_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc1_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc1_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc1_reg1; +wire [15:0] sdcore_crc16_inserter_crc1_reg2; +wire sdcore_crc16_inserter_crc2_reset; +wire sdcore_crc16_inserter_crc2_enable; +reg [1:0] sdcore_crc16_inserter_crc2_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc2_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc2_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc2_reg1; +wire [15:0] sdcore_crc16_inserter_crc2_reg2; +wire sdcore_crc16_inserter_crc3_reset; +wire sdcore_crc16_inserter_crc3_enable; +reg [1:0] sdcore_crc16_inserter_crc3_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc3_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc3_reg0 = 16'd0; +wire [15:0] sdcore_crc16_inserter_crc3_reg1; +wire [15:0] sdcore_crc16_inserter_crc3_reg2; +reg sdcore_sink_sink_valid1 = 1'd0; +wire sdcore_sink_sink_ready1; +reg sdcore_sink_sink_first1 = 1'd0; +reg sdcore_sink_sink_last1 = 1'd0; +reg [7:0] sdcore_sink_sink_payload_data1 = 8'd0; +wire sdcore_source_source_valid1; +wire sdcore_source_source_ready1; +wire sdcore_source_source_first1; +wire sdcore_source_source_last1; +wire [7:0] sdcore_source_source_payload_data1; +wire sdcore_fifo_sink_valid; +wire sdcore_fifo_sink_ready; +wire sdcore_fifo_sink_first; +wire sdcore_fifo_sink_last; +wire [7:0] sdcore_fifo_sink_payload_data; +wire sdcore_fifo_source_valid; +wire sdcore_fifo_source_ready; +wire sdcore_fifo_source_first; +wire sdcore_fifo_source_last; +wire [7:0] sdcore_fifo_source_payload_data; +wire sdcore_fifo_syncfifo_we; +wire sdcore_fifo_syncfifo_writable; +wire sdcore_fifo_syncfifo_re; +wire sdcore_fifo_syncfifo_readable; +wire [9:0] sdcore_fifo_syncfifo_din; +wire [9:0] sdcore_fifo_syncfifo_dout; +reg [3:0] sdcore_fifo_level = 4'd0; +reg sdcore_fifo_replace = 1'd0; +reg [2:0] sdcore_fifo_produce = 3'd0; +reg [2:0] sdcore_fifo_consume = 3'd0; +reg [2:0] sdcore_fifo_wrport_adr = 3'd0; +wire [9:0] sdcore_fifo_wrport_dat_r; +wire sdcore_fifo_wrport_we; +wire [9:0] sdcore_fifo_wrport_dat_w; +wire sdcore_fifo_do_read; +wire [2:0] sdcore_fifo_rdport_adr; +wire [9:0] sdcore_fifo_rdport_dat_r; +wire [7:0] sdcore_fifo_fifo_in_payload_data; +wire sdcore_fifo_fifo_in_first; +wire sdcore_fifo_fifo_in_last; +wire [7:0] sdcore_fifo_fifo_out_payload_data; +wire sdcore_fifo_fifo_out_first; +wire sdcore_fifo_fifo_out_last; +wire sdcore_fifo_reset; +wire [1:0] sdcore_cmd_type; +reg [2:0] sdcore_cmd_count = 3'd0; +reg sdcore_cmd_done = 1'd0; +reg sdcore_cmd_error = 1'd0; +reg sdcore_cmd_timeout = 1'd0; +wire [1:0] sdcore_data_type; +reg [31:0] sdcore_data_count = 32'd0; +reg sdcore_data_done = 1'd0; +reg sdcore_data_error = 1'd0; +reg sdcore_data_timeout = 1'd0; +wire [5:0] sdcore_cmd; +wire [31:0] interface0_bus_adr; +wire [31:0] interface0_bus_dat_w; +wire [31:0] interface0_bus_dat_r; +wire [3:0] interface0_bus_sel; +wire interface0_bus_cyc; +wire interface0_bus_stb; +wire interface0_bus_ack; +wire interface0_bus_we; +reg [2:0] interface0_bus_cti = 3'd0; +reg [1:0] interface0_bus_bte = 2'd0; +wire interface0_bus_err; +wire sdblock2mem_sink_sink_valid0; +reg sdblock2mem_sink_sink_ready0 = 1'd0; +wire sdblock2mem_sink_sink_first; +wire sdblock2mem_sink_sink_last0; +wire [7:0] sdblock2mem_sink_sink_payload_data0; +reg sdblock2mem_irq = 1'd0; +reg sdblock2mem_fifo_sink_valid = 1'd0; +wire sdblock2mem_fifo_sink_ready; +reg sdblock2mem_fifo_sink_first = 1'd0; +reg sdblock2mem_fifo_sink_last = 1'd0; +reg [7:0] sdblock2mem_fifo_sink_payload_data = 8'd0; +wire sdblock2mem_fifo_source_valid; +wire sdblock2mem_fifo_source_ready; +wire sdblock2mem_fifo_source_first; +wire sdblock2mem_fifo_source_last; +wire [7:0] sdblock2mem_fifo_source_payload_data; +wire sdblock2mem_fifo_re; +reg sdblock2mem_fifo_readable = 1'd0; +wire sdblock2mem_fifo_syncfifo_we; +wire sdblock2mem_fifo_syncfifo_writable; +wire sdblock2mem_fifo_syncfifo_re; +wire sdblock2mem_fifo_syncfifo_readable; +wire [9:0] sdblock2mem_fifo_syncfifo_din; +wire [9:0] sdblock2mem_fifo_syncfifo_dout; +reg [9:0] sdblock2mem_fifo_level0 = 10'd0; +reg sdblock2mem_fifo_replace = 1'd0; +reg [8:0] sdblock2mem_fifo_produce = 9'd0; +reg [8:0] sdblock2mem_fifo_consume = 9'd0; +reg [8:0] sdblock2mem_fifo_wrport_adr = 9'd0; +wire [9:0] sdblock2mem_fifo_wrport_dat_r; +wire sdblock2mem_fifo_wrport_we; +wire [9:0] sdblock2mem_fifo_wrport_dat_w; +wire sdblock2mem_fifo_do_read; +wire [8:0] sdblock2mem_fifo_rdport_adr; +wire [9:0] sdblock2mem_fifo_rdport_dat_r; +wire sdblock2mem_fifo_rdport_re; +wire [9:0] sdblock2mem_fifo_level1; +wire [7:0] sdblock2mem_fifo_fifo_in_payload_data; +wire sdblock2mem_fifo_fifo_in_first; +wire sdblock2mem_fifo_fifo_in_last; +wire [7:0] sdblock2mem_fifo_fifo_out_payload_data; +wire sdblock2mem_fifo_fifo_out_first; +wire sdblock2mem_fifo_fifo_out_last; +wire sdblock2mem_converter_sink_valid; +wire sdblock2mem_converter_sink_ready; +wire sdblock2mem_converter_sink_first; +wire sdblock2mem_converter_sink_last; +wire [7:0] sdblock2mem_converter_sink_payload_data; +wire sdblock2mem_converter_source_valid; +wire sdblock2mem_converter_source_ready; +reg sdblock2mem_converter_source_first = 1'd0; +reg sdblock2mem_converter_source_last = 1'd0; +reg [31:0] sdblock2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdblock2mem_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] sdblock2mem_converter_demux = 2'd0; +wire sdblock2mem_converter_load_part; +reg sdblock2mem_converter_strobe_all = 1'd0; +wire sdblock2mem_source_source_valid; +wire sdblock2mem_source_source_ready; +wire sdblock2mem_source_source_first; +wire sdblock2mem_source_source_last; +wire [31:0] sdblock2mem_source_source_payload_data; +reg sdblock2mem_sink_sink_valid1 = 1'd0; +wire sdblock2mem_sink_sink_ready1; +reg sdblock2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdblock2mem_sink_sink_payload_address = 32'd0; +reg [31:0] sdblock2mem_sink_sink_payload_data1 = 32'd0; +wire sdblock2mem_wishbonedmawriter_sink_valid; +reg sdblock2mem_wishbonedmawriter_sink_ready = 1'd0; +wire sdblock2mem_wishbonedmawriter_sink_first; +wire sdblock2mem_wishbonedmawriter_sink_last; +wire [31:0] sdblock2mem_wishbonedmawriter_sink_payload_data; +reg [63:0] sdblock2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdblock2mem_wishbonedmawriter_base_re = 1'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdblock2mem_wishbonedmawriter_length_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_enable_storage = 1'd0; +reg sdblock2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_done_status = 1'd0; +wire sdblock2mem_wishbonedmawriter_done_we; +reg sdblock2mem_wishbonedmawriter_done_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_loop_storage = 1'd0; +reg sdblock2mem_wishbonedmawriter_loop_re = 1'd0; +wire [31:0] sdblock2mem_wishbonedmawriter_offset_status; +wire sdblock2mem_wishbonedmawriter_offset_we; +reg sdblock2mem_wishbonedmawriter_offset_re = 1'd0; +wire [31:0] sdblock2mem_wishbonedmawriter_base; +reg [31:0] sdblock2mem_wishbonedmawriter_offset = 32'd0; +wire [31:0] sdblock2mem_wishbonedmawriter_length; +wire sdblock2mem_wishbonedmawriter_reset; +wire sdblock2mem_start; +reg sdblock2mem_connect = 1'd0; +reg sdblock2mem_done_d = 1'd0; +reg [31:0] interface1_bus_adr = 32'd0; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire [31:0] interface1_bus_dat_r; +reg [3:0] interface1_bus_sel = 4'd0; +reg interface1_bus_cyc = 1'd0; +reg interface1_bus_stb = 1'd0; +wire interface1_bus_ack; +reg interface1_bus_we = 1'd0; +reg [2:0] interface1_bus_cti = 3'd0; +reg [1:0] interface1_bus_bte = 2'd0; +wire interface1_bus_err; +wire sdmem2block_source_source_valid0; +wire sdmem2block_source_source_ready0; +wire sdmem2block_source_source_first0; +reg sdmem2block_source_source_last0 = 1'd0; +wire [7:0] sdmem2block_source_source_payload_data0; +reg sdmem2block_irq = 1'd0; +reg sdmem2block_dma_sink_valid = 1'd0; +reg sdmem2block_dma_sink_ready = 1'd0; +reg sdmem2block_dma_sink_last = 1'd0; +reg [31:0] sdmem2block_dma_sink_payload_address = 32'd0; +reg sdmem2block_dma_source_valid = 1'd0; +wire sdmem2block_dma_source_ready; +reg sdmem2block_dma_source_first = 1'd0; +reg sdmem2block_dma_source_last = 1'd0; +reg [31:0] sdmem2block_dma_source_payload_data = 32'd0; +reg [31:0] sdmem2block_dma_data = 32'd0; +reg [63:0] sdmem2block_dma_base_storage = 64'd0; +reg sdmem2block_dma_base_re = 1'd0; +reg [31:0] sdmem2block_dma_length_storage = 32'd0; +reg sdmem2block_dma_length_re = 1'd0; +reg sdmem2block_dma_enable_storage = 1'd0; +reg sdmem2block_dma_enable_re = 1'd0; +reg sdmem2block_dma_done_status = 1'd0; +wire sdmem2block_dma_done_we; +reg sdmem2block_dma_done_re = 1'd0; +reg sdmem2block_dma_loop_storage = 1'd0; +reg sdmem2block_dma_loop_re = 1'd0; +wire [31:0] sdmem2block_dma_offset_status; +wire sdmem2block_dma_offset_we; +reg sdmem2block_dma_offset_re = 1'd0; +wire [31:0] sdmem2block_dma_base; +reg [31:0] sdmem2block_dma_offset = 32'd0; +wire [31:0] sdmem2block_dma_length; +wire sdmem2block_dma_reset; +wire sdmem2block_converter_sink_valid; +wire sdmem2block_converter_sink_ready; +wire sdmem2block_converter_sink_first; +wire sdmem2block_converter_sink_last; +wire [31:0] sdmem2block_converter_sink_payload_data; +wire sdmem2block_converter_source_valid; +wire sdmem2block_converter_source_ready; +wire sdmem2block_converter_source_first; +wire sdmem2block_converter_source_last; +reg [7:0] sdmem2block_converter_source_payload_data = 8'd0; +wire sdmem2block_converter_source_payload_valid_token_count; +reg [1:0] sdmem2block_converter_mux = 2'd0; +wire sdmem2block_converter_first; +wire sdmem2block_converter_last; +wire sdmem2block_source_source_valid1; +wire sdmem2block_source_source_ready1; +wire sdmem2block_source_source_first1; +wire sdmem2block_source_source_last1; +wire [7:0] sdmem2block_source_source_payload_data1; +wire sdmem2block_fifo_sink_valid; +wire sdmem2block_fifo_sink_ready; +wire sdmem2block_fifo_sink_first; +wire sdmem2block_fifo_sink_last; +wire [7:0] sdmem2block_fifo_sink_payload_data; +wire sdmem2block_fifo_source_valid; +wire sdmem2block_fifo_source_ready; +wire sdmem2block_fifo_source_first; +wire sdmem2block_fifo_source_last; +wire [7:0] sdmem2block_fifo_source_payload_data; +wire sdmem2block_fifo_re; +reg sdmem2block_fifo_readable = 1'd0; +wire sdmem2block_fifo_syncfifo_we; +wire sdmem2block_fifo_syncfifo_writable; +wire sdmem2block_fifo_syncfifo_re; +wire sdmem2block_fifo_syncfifo_readable; +wire [9:0] sdmem2block_fifo_syncfifo_din; +wire [9:0] sdmem2block_fifo_syncfifo_dout; +reg [9:0] sdmem2block_fifo_level0 = 10'd0; +reg sdmem2block_fifo_replace = 1'd0; +reg [8:0] sdmem2block_fifo_produce = 9'd0; +reg [8:0] sdmem2block_fifo_consume = 9'd0; +reg [8:0] sdmem2block_fifo_wrport_adr = 9'd0; +wire [9:0] sdmem2block_fifo_wrport_dat_r; +wire sdmem2block_fifo_wrport_we; +wire [9:0] sdmem2block_fifo_wrport_dat_w; +wire sdmem2block_fifo_do_read; +wire [8:0] sdmem2block_fifo_rdport_adr; +wire [9:0] sdmem2block_fifo_rdport_dat_r; +wire sdmem2block_fifo_rdport_re; +wire [9:0] sdmem2block_fifo_level1; +wire [7:0] sdmem2block_fifo_fifo_in_payload_data; +wire sdmem2block_fifo_fifo_in_first; +wire sdmem2block_fifo_fifo_in_last; +wire [7:0] sdmem2block_fifo_fifo_out_payload_data; +wire sdmem2block_fifo_fifo_out_first; +wire sdmem2block_fifo_fifo_out_last; +reg [8:0] sdmem2block_count = 9'd0; +reg sdmem2block_done_d = 1'd0; +wire sdirq_irq; +wire card_detect_status1; +reg card_detect_pending = 1'd0; +wire card_detect_trigger; +reg card_detect_clear = 1'd0; +wire block2mem_dma_status; +reg block2mem_dma_pending = 1'd0; +wire block2mem_dma_trigger; +reg block2mem_dma_clear = 1'd0; +wire mem2block_dma_status; +reg mem2block_dma_pending = 1'd0; +wire mem2block_dma_trigger; +reg mem2block_dma_clear = 1'd0; +wire cmd_done_status; +wire cmd_done_pending; +wire cmd_done_trigger; +reg cmd_done_clear = 1'd0; +wire eventmanager_card_detect0; +wire eventmanager_block2mem_dma0; +wire eventmanager_mem2block_dma0; +wire eventmanager_cmd_done0; +reg [3:0] eventmanager_status_status = 4'd0; +wire eventmanager_status_we; +reg eventmanager_status_re = 1'd0; +wire eventmanager_card_detect1; +wire eventmanager_block2mem_dma1; +wire eventmanager_mem2block_dma1; +wire eventmanager_cmd_done1; +reg [3:0] eventmanager_pending_status = 4'd0; +wire eventmanager_pending_we; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_r = 4'd0; +wire eventmanager_card_detect2; +wire eventmanager_block2mem_dma2; +wire eventmanager_mem2block_dma2; +wire eventmanager_cmd_done2; +reg [3:0] eventmanager_enable_storage = 4'd0; +reg eventmanager_enable_re = 1'd0; +reg subfragments_sdphyinit_state = 1'd0; +reg subfragments_sdphyinit_next_state = 1'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +reg [1:0] subfragments_sdphycmdw_state = 2'd0; +reg [1:0] subfragments_sdphycmdw_next_state = 2'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg [2:0] subfragments_sdphycmdr_state = 3'd0; +reg [2:0] subfragments_sdphycmdr_next_state = 3'd0; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg [2:0] subfragments_sdphydataw_state = 3'd0; +reg [2:0] subfragments_sdphydataw_next_state = 3'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +reg [2:0] subfragments_sdphydatar_state = 3'd0; +reg [2:0] subfragments_sdphydatar_next_state = 3'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg subfragments_sdcore_crc16inserter_state = 1'd0; +reg subfragments_sdcore_crc16inserter_next_state = 1'd0; +reg [2:0] sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value = 3'd0; +reg sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce = 1'd0; +reg [2:0] subfragments_sdcore_fsm_state = 3'd0; +reg [2:0] subfragments_sdcore_fsm_next_state = 3'd0; +reg sdcore_cmd_done_sdcore_fsm_next_value0 = 1'd0; +reg sdcore_cmd_done_sdcore_fsm_next_value_ce0 = 1'd0; +reg sdcore_data_done_sdcore_fsm_next_value1 = 1'd0; +reg sdcore_data_done_sdcore_fsm_next_value_ce1 = 1'd0; +reg [2:0] sdcore_cmd_count_sdcore_fsm_next_value2 = 3'd0; +reg sdcore_cmd_count_sdcore_fsm_next_value_ce2 = 1'd0; +reg [31:0] sdcore_data_count_sdcore_fsm_next_value3 = 32'd0; +reg sdcore_data_count_sdcore_fsm_next_value_ce3 = 1'd0; +reg sdcore_cmd_error_sdcore_fsm_next_value4 = 1'd0; +reg sdcore_cmd_error_sdcore_fsm_next_value_ce4 = 1'd0; +reg sdcore_cmd_timeout_sdcore_fsm_next_value5 = 1'd0; +reg sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 = 1'd0; +reg sdcore_data_error_sdcore_fsm_next_value6 = 1'd0; +reg sdcore_data_error_sdcore_fsm_next_value_ce6 = 1'd0; +reg sdcore_data_timeout_sdcore_fsm_next_value7 = 1'd0; +reg sdcore_data_timeout_sdcore_fsm_next_value_ce7 = 1'd0; +reg [127:0] sdcore_cmd_response_status_sdcore_fsm_next_value8 = 128'd0; +reg sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 = 1'd0; +reg [1:0] subfragments_state = 2'd0; +reg [1:0] subfragments_next_state = 2'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_offset_next_value = 32'd0; +reg sdblock2mem_wishbonedmawriter_offset_next_value_ce = 1'd0; +reg subfragments_sdmem2blockdma_fsm_state = 1'd0; +reg subfragments_sdmem2blockdma_fsm_next_state = 1'd0; +reg [31:0] sdmem2block_dma_data_sdmem2blockdma_fsm_next_value = 32'd0; +reg sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce = 1'd0; +reg [1:0] subfragments_sdmem2blockdma_resetinserter_state = 2'd0; +reg [1:0] subfragments_sdmem2blockdma_resetinserter_next_state = 2'd0; +reg [31:0] sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value = 32'd0; +reg sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce = 1'd0; +reg [13:0] litesdcardcore_litesdcardcore_adr = 14'd0; +reg litesdcardcore_litesdcardcore_we = 1'd0; +reg [31:0] litesdcardcore_litesdcardcore_dat_w = 32'd0; +wire [31:0] litesdcardcore_litesdcardcore_dat_r; +wire [29:0] litesdcardcore_litesdcardcore_wishbone_adr; +wire [31:0] litesdcardcore_litesdcardcore_wishbone_dat_w; +reg [31:0] litesdcardcore_litesdcardcore_wishbone_dat_r = 32'd0; +wire [3:0] litesdcardcore_litesdcardcore_wishbone_sel; +wire litesdcardcore_litesdcardcore_wishbone_cyc; +wire litesdcardcore_litesdcardcore_wishbone_stb; +reg litesdcardcore_litesdcardcore_wishbone_ack = 1'd0; +wire litesdcardcore_litesdcardcore_wishbone_we; +wire [2:0] litesdcardcore_litesdcardcore_wishbone_cti; +wire [1:0] litesdcardcore_litesdcardcore_wishbone_bte; +reg litesdcardcore_litesdcardcore_wishbone_err = 1'd0; +wire [29:0] litesdcardcore_shared_adr; +wire [31:0] litesdcardcore_shared_dat_w; +reg [31:0] litesdcardcore_shared_dat_r = 32'd0; +wire [3:0] litesdcardcore_shared_sel; +wire litesdcardcore_shared_cyc; +wire litesdcardcore_shared_stb; +reg litesdcardcore_shared_ack = 1'd0; +wire litesdcardcore_shared_we; +wire [2:0] litesdcardcore_shared_cti; +wire [1:0] litesdcardcore_shared_bte; +wire litesdcardcore_shared_err; +wire [1:0] litesdcardcore_request; +reg litesdcardcore_grant = 1'd0; +wire litesdcardcore_slave_sel; +reg litesdcardcore_slave_sel_r = 1'd0; +reg litesdcardcore_error = 1'd0; +wire litesdcardcore_wait; +wire litesdcardcore_done; +reg [19:0] litesdcardcore_count = 20'd1000000; +wire [13:0] litesdcardcore_interface0_bank_bus_adr; +wire litesdcardcore_interface0_bank_bus_we; +wire [31:0] litesdcardcore_interface0_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface0_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank0_reset0_re = 1'd0; +wire [1:0] litesdcardcore_csrbank0_reset0_r; +reg litesdcardcore_csrbank0_reset0_we = 1'd0; +wire [1:0] litesdcardcore_csrbank0_reset0_w; +reg litesdcardcore_csrbank0_scratch0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank0_scratch0_r; +reg litesdcardcore_csrbank0_scratch0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank0_scratch0_w; +reg litesdcardcore_csrbank0_bus_errors_re = 1'd0; +wire [31:0] litesdcardcore_csrbank0_bus_errors_r; +reg litesdcardcore_csrbank0_bus_errors_we = 1'd0; +wire [31:0] litesdcardcore_csrbank0_bus_errors_w; +wire litesdcardcore_csrbank0_sel; +wire [13:0] litesdcardcore_interface1_bank_bus_adr; +wire litesdcardcore_interface1_bank_bus_we; +wire [31:0] litesdcardcore_interface1_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface1_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank1_dma_base1_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base1_r; +reg litesdcardcore_csrbank1_dma_base1_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base1_w; +reg litesdcardcore_csrbank1_dma_base0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base0_r; +reg litesdcardcore_csrbank1_dma_base0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_base0_w; +reg litesdcardcore_csrbank1_dma_length0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_length0_r; +reg litesdcardcore_csrbank1_dma_length0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_length0_w; +reg litesdcardcore_csrbank1_dma_enable0_re = 1'd0; +wire litesdcardcore_csrbank1_dma_enable0_r; +reg litesdcardcore_csrbank1_dma_enable0_we = 1'd0; +wire litesdcardcore_csrbank1_dma_enable0_w; +reg litesdcardcore_csrbank1_dma_done_re = 1'd0; +wire litesdcardcore_csrbank1_dma_done_r; +reg litesdcardcore_csrbank1_dma_done_we = 1'd0; +wire litesdcardcore_csrbank1_dma_done_w; +reg litesdcardcore_csrbank1_dma_loop0_re = 1'd0; +wire litesdcardcore_csrbank1_dma_loop0_r; +reg litesdcardcore_csrbank1_dma_loop0_we = 1'd0; +wire litesdcardcore_csrbank1_dma_loop0_w; +reg litesdcardcore_csrbank1_dma_offset_re = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_offset_r; +reg litesdcardcore_csrbank1_dma_offset_we = 1'd0; +wire [31:0] litesdcardcore_csrbank1_dma_offset_w; +wire litesdcardcore_csrbank1_sel; +wire [13:0] litesdcardcore_interface2_bank_bus_adr; +wire litesdcardcore_interface2_bank_bus_we; +wire [31:0] litesdcardcore_interface2_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface2_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank2_cmd_argument0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_argument0_r; +reg litesdcardcore_csrbank2_cmd_argument0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_argument0_w; +reg litesdcardcore_csrbank2_cmd_command0_re = 1'd0; +wire [13:0] litesdcardcore_csrbank2_cmd_command0_r; +reg litesdcardcore_csrbank2_cmd_command0_we = 1'd0; +wire [13:0] litesdcardcore_csrbank2_cmd_command0_w; +reg litesdcardcore_csrbank2_cmd_send0_re = 1'd0; +wire litesdcardcore_csrbank2_cmd_send0_r; +reg litesdcardcore_csrbank2_cmd_send0_we = 1'd0; +wire litesdcardcore_csrbank2_cmd_send0_w; +reg litesdcardcore_csrbank2_cmd_response3_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response3_r; +reg litesdcardcore_csrbank2_cmd_response3_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response3_w; +reg litesdcardcore_csrbank2_cmd_response2_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response2_r; +reg litesdcardcore_csrbank2_cmd_response2_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response2_w; +reg litesdcardcore_csrbank2_cmd_response1_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response1_r; +reg litesdcardcore_csrbank2_cmd_response1_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response1_w; +reg litesdcardcore_csrbank2_cmd_response0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response0_r; +reg litesdcardcore_csrbank2_cmd_response0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_cmd_response0_w; +reg litesdcardcore_csrbank2_cmd_event_re = 1'd0; +wire [3:0] litesdcardcore_csrbank2_cmd_event_r; +reg litesdcardcore_csrbank2_cmd_event_we = 1'd0; +wire [3:0] litesdcardcore_csrbank2_cmd_event_w; +reg litesdcardcore_csrbank2_data_event_re = 1'd0; +wire [3:0] litesdcardcore_csrbank2_data_event_r; +reg litesdcardcore_csrbank2_data_event_we = 1'd0; +wire [3:0] litesdcardcore_csrbank2_data_event_w; +reg litesdcardcore_csrbank2_block_length0_re = 1'd0; +wire [9:0] litesdcardcore_csrbank2_block_length0_r; +reg litesdcardcore_csrbank2_block_length0_we = 1'd0; +wire [9:0] litesdcardcore_csrbank2_block_length0_w; +reg litesdcardcore_csrbank2_block_count0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank2_block_count0_r; +reg litesdcardcore_csrbank2_block_count0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank2_block_count0_w; +wire litesdcardcore_csrbank2_sel; +wire [13:0] litesdcardcore_interface3_bank_bus_adr; +wire litesdcardcore_interface3_bank_bus_we; +wire [31:0] litesdcardcore_interface3_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface3_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank3_status_re = 1'd0; +wire [3:0] litesdcardcore_csrbank3_status_r; +reg litesdcardcore_csrbank3_status_we = 1'd0; +wire [3:0] litesdcardcore_csrbank3_status_w; +reg litesdcardcore_csrbank3_pending_re = 1'd0; +wire [3:0] litesdcardcore_csrbank3_pending_r; +reg litesdcardcore_csrbank3_pending_we = 1'd0; +wire [3:0] litesdcardcore_csrbank3_pending_w; +reg litesdcardcore_csrbank3_enable0_re = 1'd0; +wire [3:0] litesdcardcore_csrbank3_enable0_r; +reg litesdcardcore_csrbank3_enable0_we = 1'd0; +wire [3:0] litesdcardcore_csrbank3_enable0_w; +wire litesdcardcore_csrbank3_sel; +wire [13:0] litesdcardcore_interface4_bank_bus_adr; +wire litesdcardcore_interface4_bank_bus_we; +wire [31:0] litesdcardcore_interface4_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface4_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank4_dma_base1_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base1_r; +reg litesdcardcore_csrbank4_dma_base1_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base1_w; +reg litesdcardcore_csrbank4_dma_base0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base0_r; +reg litesdcardcore_csrbank4_dma_base0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_base0_w; +reg litesdcardcore_csrbank4_dma_length0_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_length0_r; +reg litesdcardcore_csrbank4_dma_length0_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_length0_w; +reg litesdcardcore_csrbank4_dma_enable0_re = 1'd0; +wire litesdcardcore_csrbank4_dma_enable0_r; +reg litesdcardcore_csrbank4_dma_enable0_we = 1'd0; +wire litesdcardcore_csrbank4_dma_enable0_w; +reg litesdcardcore_csrbank4_dma_done_re = 1'd0; +wire litesdcardcore_csrbank4_dma_done_r; +reg litesdcardcore_csrbank4_dma_done_we = 1'd0; +wire litesdcardcore_csrbank4_dma_done_w; +reg litesdcardcore_csrbank4_dma_loop0_re = 1'd0; +wire litesdcardcore_csrbank4_dma_loop0_r; +reg litesdcardcore_csrbank4_dma_loop0_we = 1'd0; +wire litesdcardcore_csrbank4_dma_loop0_w; +reg litesdcardcore_csrbank4_dma_offset_re = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_offset_r; +reg litesdcardcore_csrbank4_dma_offset_we = 1'd0; +wire [31:0] litesdcardcore_csrbank4_dma_offset_w; +wire litesdcardcore_csrbank4_sel; +wire [13:0] litesdcardcore_interface5_bank_bus_adr; +wire litesdcardcore_interface5_bank_bus_we; +wire [31:0] litesdcardcore_interface5_bank_bus_dat_w; +reg [31:0] litesdcardcore_interface5_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank5_card_detect_re = 1'd0; +wire litesdcardcore_csrbank5_card_detect_r; +reg litesdcardcore_csrbank5_card_detect_we = 1'd0; +wire litesdcardcore_csrbank5_card_detect_w; +reg litesdcardcore_csrbank5_clocker_divider0_re = 1'd0; +wire [8:0] litesdcardcore_csrbank5_clocker_divider0_r; +reg litesdcardcore_csrbank5_clocker_divider0_we = 1'd0; +wire [8:0] litesdcardcore_csrbank5_clocker_divider0_w; +reg litesdcardcore_csrbank5_dataw_status_re = 1'd0; +wire [2:0] litesdcardcore_csrbank5_dataw_status_r; +reg litesdcardcore_csrbank5_dataw_status_we = 1'd0; +wire [2:0] litesdcardcore_csrbank5_dataw_status_w; +wire litesdcardcore_csrbank5_sel; +wire [13:0] litesdcardcore_csr_interconnect_adr; +wire litesdcardcore_csr_interconnect_we; +wire [31:0] litesdcardcore_csr_interconnect_dat_w; +wire [31:0] litesdcardcore_csr_interconnect_dat_r; +reg litesdcardcore_state = 1'd0; +reg litesdcardcore_next_state = 1'd0; +reg [31:0] array_muxed0 = 32'd0; +reg [31:0] array_muxed1 = 32'd0; +reg [3:0] array_muxed2 = 4'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg [2:0] array_muxed6 = 3'd0; +reg [1:0] array_muxed7 = 2'd0; +wire inferedsdrtristate0__o; +reg inferedsdrtristate0_oe = 1'd0; +wire inferedsdrtristate0__i; +wire sdrio_clk; +wire inferedsdrtristate1__o; +reg inferedsdrtristate1_oe = 1'd0; +wire inferedsdrtristate1__i; +wire sdrio_clk_1; +wire inferedsdrtristate2__o; +reg inferedsdrtristate2_oe = 1'd0; +wire inferedsdrtristate2__i; +wire sdrio_clk_2; +wire inferedsdrtristate3__o; +reg inferedsdrtristate3_oe = 1'd0; +wire inferedsdrtristate3__i; +wire sdrio_clk_3; +wire inferedsdrtristate4__o; +reg inferedsdrtristate4_oe = 1'd0; +wire inferedsdrtristate4__i; +wire sdrio_clk_4; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign wb_ctrl_adr_1 = wb_ctrl_adr; +assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; +assign wb_ctrl_sel_1 = wb_ctrl_sel; +assign wb_ctrl_cyc_1 = wb_ctrl_cyc; +assign wb_ctrl_stb_1 = wb_ctrl_stb; +assign wb_ctrl_ack = wb_ctrl_ack_1; +assign wb_ctrl_we_1 = wb_ctrl_we; +assign wb_ctrl_cti_1 = wb_ctrl_cti; +assign wb_ctrl_bte_1 = wb_ctrl_bte; +assign wb_ctrl_err = wb_ctrl_err_1; +assign wb_dma_adr = wb_dma_adr_1; +assign wb_dma_dat_w = wb_dma_dat_w_1; +assign wb_dma_dat_r_1 = wb_dma_dat_r; +assign wb_dma_sel = wb_dma_sel_1; +assign wb_dma_cyc = wb_dma_cyc_1; +assign wb_dma_stb = wb_dma_stb_1; +assign wb_dma_ack_1 = wb_dma_ack; +assign wb_dma_we = wb_dma_we_1; +assign wb_dma_cti = wb_dma_cti_1; +assign wb_dma_bte = wb_dma_bte_1; +assign wb_dma_err_1 = wb_dma_err; +assign sdblock2mem_sink_sink_valid0 = sdcore_source_source_valid0; +assign sdcore_source_source_ready0 = sdblock2mem_sink_sink_ready0; +assign sdblock2mem_sink_sink_first = sdcore_source_source_first0; +assign sdblock2mem_sink_sink_last0 = sdcore_source_source_last0; +assign sdblock2mem_sink_sink_payload_data0 = sdcore_source_source_payload_data0; +assign sdcore_sink_sink_valid0 = sdmem2block_source_source_valid0; +assign sdmem2block_source_source_ready0 = sdcore_sink_sink_ready0; +assign sdcore_sink_sink_first0 = sdmem2block_source_source_first0; +assign sdcore_sink_sink_last0 = sdmem2block_source_source_last0; +assign sdcore_sink_sink_payload_data0 = sdmem2block_source_source_payload_data0; +assign block2mem_dma_trigger = sdblock2mem_irq; +assign mem2block_dma_trigger = sdmem2block_irq; +assign card_detect_trigger = card_detect_irq; +assign cmd_done_trigger = sdcore_csrfield_done0; +assign irq = sdirq_irq; +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +assign bus_errors_status = bus_errors; +assign card_detect_status0 = sdcard_cd; +assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); +assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); +assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); +assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); +assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); +assign init_pads_out_ready = clocker_ce; +assign cmdw_pads_out_ready = clocker_ce; +assign cmdr_pads_out_ready = clocker_ce; +assign dataw_pads_out_ready = clocker_ce; +assign datar_pads_out_ready = clocker_ce; +assign clocker_clk_en = sdpads_clk; +assign init_pads_in_valid = sdpads_data_i_ce; +assign init_pads_in_payload_cmd_i = sdpads_cmd_i; +assign init_pads_in_payload_data_i = sdpads_data_i; +assign cmdw_pads_in_valid = sdpads_data_i_ce; +assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdw_pads_in_payload_data_i = sdpads_data_i; +assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; +assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; +assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; +assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign clocker_stop = (dataw_stop | datar_stop); +always @(*) begin + clocker_clk1 <= 1'd0; + case (clocker_storage) + 3'd4: begin + clocker_clk1 <= clocker_clks[1]; + end + 4'd8: begin + clocker_clk1 <= clocker_clks[2]; + end + 5'd16: begin + clocker_clk1 <= clocker_clks[3]; + end + 6'd32: begin + clocker_clk1 <= clocker_clks[4]; + end + 7'd64: begin + clocker_clk1 <= clocker_clks[5]; + end + 8'd128: begin + clocker_clk1 <= clocker_clks[6]; + end + 9'd256: begin + clocker_clk1 <= clocker_clks[7]; + end + default: begin + clocker_clk1 <= clocker_clks[0]; + end + endcase +end +assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); +always @(*) begin + clocker_ce_latched <= 1'd0; + if (clocker_clk_d) begin + clocker_ce_latched <= clocker_clk_en; + end else begin + clocker_ce_latched <= clocker_ce_delayed; + end +end +assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); +always @(*) begin + init_pads_out_payload_clk <= 1'd0; + init_pads_out_payload_cmd_o <= 1'd0; + init_pads_out_payload_cmd_oe <= 1'd0; + subfragments_sdphyinit_next_state <= 1'd0; + init_count_sdphyinit_next_value <= 8'd0; + init_pads_out_payload_data_o <= 4'd0; + init_count_sdphyinit_next_value_ce <= 1'd0; + init_pads_out_payload_data_oe <= 1'd0; + subfragments_sdphyinit_next_state <= subfragments_sdphyinit_state; + case (subfragments_sdphyinit_state) + 1'd1: begin + init_pads_out_payload_clk <= 1'd1; + init_pads_out_payload_cmd_oe <= 1'd1; + init_pads_out_payload_cmd_o <= 1'd1; + init_pads_out_payload_data_oe <= 1'd1; + init_pads_out_payload_data_o <= 4'd15; + if (init_pads_out_ready) begin + init_count_sdphyinit_next_value <= (init_count + 1'd1); + init_count_sdphyinit_next_value_ce <= 1'd1; + if ((init_count == 7'd79)) begin + subfragments_sdphyinit_next_state <= 1'd0; + end + end + end + default: begin + init_count_sdphyinit_next_value <= 1'd0; + init_count_sdphyinit_next_value_ce <= 1'd1; + if (init_initialize_re) begin + subfragments_sdphyinit_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + cmdw_done <= 1'd0; + subfragments_sdphycmdw_next_state <= 2'd0; + cmdw_pads_out_payload_clk <= 1'd0; + cmdw_count_sdphycmdw_next_value <= 8'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd0; + cmdw_pads_out_payload_cmd_o <= 1'd0; + cmdw_pads_out_payload_cmd_oe <= 1'd0; + cmdw_sink_ready <= 1'd0; + subfragments_sdphycmdw_next_state <= subfragments_sdphycmdw_state; + case (subfragments_sdphycmdw_state) + 1'd1: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + case (cmdw_count) + 1'd0: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; + end + 1'd1: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; + end + 2'd2: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; + end + 2'd3: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; + end + 3'd4: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; + end + 3'd5: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; + end + 3'd6: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; + end + 3'd7: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; + end + endcase + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin + subfragments_sdphycmdw_next_state <= 2'd2; + end else begin + cmdw_sink_ready <= 1'd1; + subfragments_sdphycmdw_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + cmdw_pads_out_payload_cmd_o <= 1'd1; + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + cmdw_sink_ready <= 1'd1; + subfragments_sdphycmdw_next_state <= 1'd0; + end + end + end + default: begin + cmdw_count_sdphycmdw_next_value <= 1'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin + subfragments_sdphycmdw_next_state <= 1'd1; + end else begin + cmdw_done <= 1'd1; + end + end + endcase +end +assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; +assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; +assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; +assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; +assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; +assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; +assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; +assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; +assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; +assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; +assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; +assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; +assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); +assign cmdr_cmdr_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); +assign cmdr_cmdr_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; +assign cmdr_cmdr_buf_sink_valid = cmdr_cmdr_source_source_valid1; +assign cmdr_cmdr_source_source_ready1 = cmdr_cmdr_buf_sink_ready; +assign cmdr_cmdr_buf_sink_first = cmdr_cmdr_source_source_first1; +assign cmdr_cmdr_buf_sink_last = cmdr_cmdr_source_source_last1; +assign cmdr_cmdr_buf_sink_payload_data = cmdr_cmdr_source_source_payload_data1; +assign cmdr_cmdr_source_source_valid0 = cmdr_cmdr_buf_source_valid; +assign cmdr_cmdr_buf_source_ready = cmdr_cmdr_source_source_ready0; +assign cmdr_cmdr_source_source_first0 = cmdr_cmdr_buf_source_first; +assign cmdr_cmdr_source_source_last0 = cmdr_cmdr_buf_source_last; +assign cmdr_cmdr_source_source_payload_data0 = cmdr_cmdr_buf_source_payload_data; +assign cmdr_cmdr_source_source_valid1 = cmdr_cmdr_converter_source_valid; +assign cmdr_cmdr_converter_source_ready = cmdr_cmdr_source_source_ready1; +assign cmdr_cmdr_source_source_first1 = cmdr_cmdr_converter_source_first; +assign cmdr_cmdr_source_source_last1 = cmdr_cmdr_converter_source_last; +assign cmdr_cmdr_source_source_payload_data1 = cmdr_cmdr_converter_source_payload_data; +assign cmdr_cmdr_converter_sink_ready = ((~cmdr_cmdr_converter_strobe_all) | cmdr_cmdr_converter_source_ready); +assign cmdr_cmdr_converter_source_valid = cmdr_cmdr_converter_strobe_all; +assign cmdr_cmdr_converter_load_part = (cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready); +assign cmdr_cmdr_buf_sink_ready = ((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready); +always @(*) begin + subfragments_sdphycmdr_next_state <= 3'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; + cmdr_pads_out_payload_clk <= 1'd0; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; + cmdr_pads_out_payload_cmd_o <= 1'd0; + cmdr_count_sdphycmdr_next_value1 <= 8'd0; + cmdr_pads_out_payload_cmd_oe <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; + cmdr_cmdr_source_source_ready0 <= 1'd0; + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; + cmdr_sink_ready <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; + cmdr_source_valid <= 1'd0; + cmdr_source_last <= 1'd0; + cmdr_source_payload_data <= 8'd0; + cmdr_source_payload_status <= 3'd0; + subfragments_sdphycmdr_next_state <= subfragments_sdphycmdr_state; + case (subfragments_sdphycmdr_state) + 1'd1: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + if (cmdr_cmdr_source_source_valid0) begin + subfragments_sdphycmdr_next_state <= 2'd2; + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + subfragments_sdphycmdr_next_state <= 3'd5; + end + end + 2'd2: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_source_valid <= cmdr_cmdr_source_source_valid0; + cmdr_source_payload_status <= 1'd0; + cmdr_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); + cmdr_source_payload_data <= cmdr_cmdr_source_source_payload_data0; + if ((cmdr_cmdr_source_source_valid0 & cmdr_source_ready)) begin + cmdr_cmdr_source_source_ready0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if (cmdr_source_last) begin + cmdr_sink_ready <= 1'd1; + if ((cmdr_sink_payload_cmd_type == 2'd3)) begin + cmdr_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 6'd48; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + subfragments_sdphycmdr_next_state <= 2'd3; + end else begin + if ((cmdr_sink_payload_data_type == 1'd0)) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + subfragments_sdphycmdr_next_state <= 3'd4; + end else begin + subfragments_sdphycmdr_next_state <= 1'd0; + end + end + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + subfragments_sdphycmdr_next_state <= 3'd5; + end + end + 2'd3: begin + cmdr_pads_out_payload_clk <= 1'd1; + if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + end + if ((~cmdr_busy)) begin + cmdr_source_valid <= 1'd1; + cmdr_source_last <= 1'd1; + cmdr_source_payload_status <= 1'd0; + if (cmdr_source_ready) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + subfragments_sdphycmdr_next_state <= 3'd4; + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + subfragments_sdphycmdr_next_state <= 3'd5; + end + end + 3'd4: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_pads_out_payload_cmd_oe <= 1'd1; + cmdr_pads_out_payload_cmd_o <= 1'd1; + if (cmdr_pads_out_ready) begin + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if ((cmdr_count == 3'd7)) begin + subfragments_sdphycmdr_next_state <= 1'd0; + end + end + end + 3'd5: begin + cmdr_sink_ready <= 1'd1; + cmdr_source_valid <= 1'd1; + cmdr_source_last <= 1'd1; + cmdr_source_payload_status <= 1'd1; + if (cmdr_source_ready) begin + subfragments_sdphycmdr_next_state <= 1'd0; + end + end + default: begin + cmdr_timeout_sdphycmdr_next_value0 <= 6'd48; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + cmdr_busy_sdphycmdr_next_value2 <= 1'd1; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + subfragments_sdphycmdr_next_state <= 1'd1; + end + end + endcase +end +assign dataw_accepted0 = dataw_accepted1; +assign dataw_crc_error0 = dataw_crc_error1; +assign dataw_write_error0 = dataw_write_error1; +assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; +assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; +assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; +assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; +assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; +assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; +assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; +assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; +assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; +assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; +assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; +assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; +assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); +assign dataw_crc_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); +assign dataw_crc_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; +assign dataw_crc_buf_sink_valid = dataw_crc_source_source_valid1; +assign dataw_crc_source_source_ready1 = dataw_crc_buf_sink_ready; +assign dataw_crc_buf_sink_first = dataw_crc_source_source_first1; +assign dataw_crc_buf_sink_last = dataw_crc_source_source_last1; +assign dataw_crc_buf_sink_payload_data = dataw_crc_source_source_payload_data1; +assign dataw_crc_source_source_valid0 = dataw_crc_buf_source_valid; +assign dataw_crc_buf_source_ready = dataw_crc_source_source_ready0; +assign dataw_crc_source_source_first0 = dataw_crc_buf_source_first; +assign dataw_crc_source_source_last0 = dataw_crc_buf_source_last; +assign dataw_crc_source_source_payload_data0 = dataw_crc_buf_source_payload_data; +assign dataw_crc_source_source_valid1 = dataw_crc_converter_source_valid; +assign dataw_crc_converter_source_ready = dataw_crc_source_source_ready1; +assign dataw_crc_source_source_first1 = dataw_crc_converter_source_first; +assign dataw_crc_source_source_last1 = dataw_crc_converter_source_last; +assign dataw_crc_source_source_payload_data1 = dataw_crc_converter_source_payload_data; +assign dataw_crc_converter_sink_ready = ((~dataw_crc_converter_strobe_all) | dataw_crc_converter_source_ready); +assign dataw_crc_converter_source_valid = dataw_crc_converter_strobe_all; +assign dataw_crc_converter_load_part = (dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready); +assign dataw_crc_buf_sink_ready = ((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready); +always @(*) begin + subfragments_sdphydataw_next_state <= 3'd0; + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; + dataw_pads_out_payload_clk <= 1'd0; + dataw_crc_reset <= 1'd0; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_pads_out_payload_cmd_o <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; + dataw_pads_out_payload_cmd_oe <= 1'd0; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_pads_out_payload_data_o <= 4'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; + dataw_pads_out_payload_data_oe <= 1'd0; + dataw_count_sdphydataw_next_value3 <= 8'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd0; + dataw_sink_ready <= 1'd0; + dataw_stop <= 1'd0; + subfragments_sdphydataw_next_state <= subfragments_sdphydataw_state; + case (subfragments_sdphydataw_state) + 1'd1: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_cmd_oe <= 1'd1; + dataw_pads_out_payload_cmd_o <= 1'd1; + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 3'd7)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + subfragments_sdphydataw_next_state <= 2'd2; + end + end + end + 2'd2: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 1'd0; + if (dataw_pads_out_ready) begin + subfragments_sdphydataw_next_state <= 2'd3; + end + end + 2'd3: begin + dataw_stop <= (~dataw_sink_valid); + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + case (dataw_count) + 1'd0: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; + end + 1'd1: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; + end + endcase + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 1'd1)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if (dataw_sink_last) begin + subfragments_sdphydataw_next_state <= 3'd4; + end else begin + dataw_sink_ready <= 1'd1; + end + end + end + end + 3'd4: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 4'd15; + if (dataw_pads_out_ready) begin + dataw_crc_reset <= 1'd1; + subfragments_sdphydataw_next_state <= 3'd5; + end + end + 3'd5: begin + dataw_pads_out_payload_clk <= 1'd1; + if (dataw_crc_source_source_valid0) begin + dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_source_payload_data0[7:5] == 2'd2); + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd5); + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_source_payload_data0[7:5] == 3'd6); + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + subfragments_sdphydataw_next_state <= 3'd6; + end + end + 3'd6: begin + dataw_pads_out_payload_clk <= 1'd1; + if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin + dataw_sink_ready <= 1'd1; + subfragments_sdphydataw_next_state <= 1'd0; + end + end + default: begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_sink_valid & dataw_pads_out_ready)) begin + subfragments_sdphydataw_next_state <= 1'd1; + end + end + endcase +end +assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; +assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; +assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; +assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; +assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; +assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; +assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; +assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; +assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; +assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; +assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; +assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; +assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); +assign datar_datar_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_buf_sink_valid = datar_datar_source_source_valid1; +assign datar_datar_source_source_ready1 = datar_datar_buf_sink_ready; +assign datar_datar_buf_sink_first = datar_datar_source_source_first1; +assign datar_datar_buf_sink_last = datar_datar_source_source_last1; +assign datar_datar_buf_sink_payload_data = datar_datar_source_source_payload_data1; +assign datar_datar_source_source_valid0 = datar_datar_buf_source_valid; +assign datar_datar_buf_source_ready = datar_datar_source_source_ready0; +assign datar_datar_source_source_first0 = datar_datar_buf_source_first; +assign datar_datar_source_source_last0 = datar_datar_buf_source_last; +assign datar_datar_source_source_payload_data0 = datar_datar_buf_source_payload_data; +assign datar_datar_source_source_valid1 = datar_datar_converter_source_valid; +assign datar_datar_converter_source_ready = datar_datar_source_source_ready1; +assign datar_datar_source_source_first1 = datar_datar_converter_source_first; +assign datar_datar_source_source_last1 = datar_datar_converter_source_last; +assign datar_datar_source_source_payload_data1 = datar_datar_converter_source_payload_data; +assign datar_datar_converter_sink_ready = ((~datar_datar_converter_strobe_all) | datar_datar_converter_source_ready); +assign datar_datar_converter_source_valid = datar_datar_converter_strobe_all; +assign datar_datar_converter_load_part = (datar_datar_converter_sink_valid & datar_datar_converter_sink_ready); +assign datar_datar_buf_sink_ready = ((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready); +always @(*) begin + datar_source_valid <= 1'd0; + datar_source_first <= 1'd0; + datar_source_last <= 1'd0; + datar_source_payload_data <= 8'd0; + datar_source_payload_status <= 3'd0; + datar_stop <= 1'd0; + subfragments_sdphydatar_next_state <= 3'd0; + datar_count_sdphydatar_next_value0 <= 10'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd0; + datar_timeout_sdphydatar_next_value1 <= 32'd0; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; + datar_pads_out_payload_clk <= 1'd0; + datar_datar_source_source_ready0 <= 1'd0; + datar_sink_ready <= 1'd0; + subfragments_sdphydatar_next_state <= subfragments_sdphydatar_state; + case (subfragments_sdphydatar_state) + 1'd1: begin + datar_pads_out_payload_clk <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if (datar_datar_source_source_valid0) begin + subfragments_sdphydatar_next_state <= 2'd2; + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + subfragments_sdphydatar_next_state <= 3'd4; + end + end + 2'd2: begin + datar_pads_out_payload_clk <= 1'd1; + datar_source_valid <= datar_datar_source_source_valid0; + datar_source_payload_status <= 1'd0; + datar_source_first <= (datar_count == 1'd0); + datar_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); + datar_source_payload_data <= datar_datar_source_source_payload_data0; + if (datar_source_valid) begin + if (datar_source_ready) begin + datar_datar_source_source_ready0 <= 1'd1; + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if (datar_source_last) begin + datar_sink_ready <= 1'd1; + if (datar_sink_last) begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + subfragments_sdphydatar_next_state <= 2'd3; + end else begin + subfragments_sdphydatar_next_state <= 1'd0; + end + end + end else begin + datar_stop <= 1'd1; + end + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + subfragments_sdphydatar_next_state <= 3'd4; + end + end + 2'd3: begin + datar_pads_out_payload_clk <= 1'd1; + if (datar_pads_out_ready) begin + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_count == 6'd39)) begin + subfragments_sdphydatar_next_state <= 1'd0; + end + end + end + 3'd4: begin + datar_source_valid <= 1'd1; + datar_source_payload_status <= 1'd1; + datar_source_last <= 1'd1; + if (datar_source_ready) begin + subfragments_sdphydatar_next_state <= 1'd0; + end + end + default: begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_sink_valid & datar_pads_out_ready)) begin + datar_pads_out_payload_clk <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= 32'd48; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd1; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + subfragments_sdphydatar_next_state <= 1'd1; + end + end + endcase +end +assign sdcore_crc16_inserter_sink_valid = sdcore_sink_sink_valid0; +assign sdcore_sink_sink_ready0 = sdcore_crc16_inserter_sink_ready; +assign sdcore_crc16_inserter_sink_first = sdcore_sink_sink_first0; +assign sdcore_crc16_inserter_sink_last = sdcore_sink_sink_last0; +assign sdcore_crc16_inserter_sink_payload_data = sdcore_sink_sink_payload_data0; +assign sdcore_source_source_valid0 = sdcore_source_source_valid1; +assign sdcore_source_source_ready1 = sdcore_source_source_ready0; +assign sdcore_source_source_first0 = sdcore_source_source_first1; +assign sdcore_source_source_last0 = sdcore_source_source_last1; +assign sdcore_source_source_payload_data0 = sdcore_source_source_payload_data1; +assign sdcore_cmd_type = sdcore_csrfield_cmd_type; +assign sdcore_data_type = sdcore_csrfield_data_type; +assign sdcore_cmd = sdcore_csrfield_cmd; +assign sdcore_csrfield_done0 = sdcore_cmd_done; +assign sdcore_csrfield_error0 = sdcore_cmd_error; +assign sdcore_csrfield_timeout0 = sdcore_cmd_timeout; +assign sdcore_csrfield_crc0 = 1'd0; +assign sdcore_csrfield_done1 = sdcore_data_done; +assign sdcore_csrfield_error1 = sdcore_data_error; +assign sdcore_csrfield_timeout1 = sdcore_data_timeout; +assign sdcore_csrfield_crc1 = 1'd0; +assign sdcore_crc7_inserter_din = {1'd0, 1'd1, sdcore_cmd, sdcore_cmd_argument_storage}; +assign sdcore_crc7_inserter_reset = 1'd1; +assign sdcore_crc7_inserter_enable = 1'd1; +assign sdcore_crc7_inserter_reg1 = {sdcore_crc7_inserter_reg0[5], sdcore_crc7_inserter_reg0[4], sdcore_crc7_inserter_reg0[3], (sdcore_crc7_inserter_reg0[2] ^ (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])), sdcore_crc7_inserter_reg0[1], sdcore_crc7_inserter_reg0[0], (sdcore_crc7_inserter_din[39] ^ sdcore_crc7_inserter_reg0[6])}; +assign sdcore_crc7_inserter_reg2 = {sdcore_crc7_inserter_reg1[5], sdcore_crc7_inserter_reg1[4], sdcore_crc7_inserter_reg1[3], (sdcore_crc7_inserter_reg1[2] ^ (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])), sdcore_crc7_inserter_reg1[1], sdcore_crc7_inserter_reg1[0], (sdcore_crc7_inserter_din[38] ^ sdcore_crc7_inserter_reg1[6])}; +assign sdcore_crc7_inserter_reg3 = {sdcore_crc7_inserter_reg2[5], sdcore_crc7_inserter_reg2[4], sdcore_crc7_inserter_reg2[3], (sdcore_crc7_inserter_reg2[2] ^ (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])), sdcore_crc7_inserter_reg2[1], sdcore_crc7_inserter_reg2[0], (sdcore_crc7_inserter_din[37] ^ sdcore_crc7_inserter_reg2[6])}; +assign sdcore_crc7_inserter_reg4 = {sdcore_crc7_inserter_reg3[5], sdcore_crc7_inserter_reg3[4], sdcore_crc7_inserter_reg3[3], (sdcore_crc7_inserter_reg3[2] ^ (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])), sdcore_crc7_inserter_reg3[1], sdcore_crc7_inserter_reg3[0], (sdcore_crc7_inserter_din[36] ^ sdcore_crc7_inserter_reg3[6])}; +assign sdcore_crc7_inserter_reg5 = {sdcore_crc7_inserter_reg4[5], sdcore_crc7_inserter_reg4[4], sdcore_crc7_inserter_reg4[3], (sdcore_crc7_inserter_reg4[2] ^ (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])), sdcore_crc7_inserter_reg4[1], sdcore_crc7_inserter_reg4[0], (sdcore_crc7_inserter_din[35] ^ sdcore_crc7_inserter_reg4[6])}; +assign sdcore_crc7_inserter_reg6 = {sdcore_crc7_inserter_reg5[5], sdcore_crc7_inserter_reg5[4], sdcore_crc7_inserter_reg5[3], (sdcore_crc7_inserter_reg5[2] ^ (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])), sdcore_crc7_inserter_reg5[1], sdcore_crc7_inserter_reg5[0], (sdcore_crc7_inserter_din[34] ^ sdcore_crc7_inserter_reg5[6])}; +assign sdcore_crc7_inserter_reg7 = {sdcore_crc7_inserter_reg6[5], sdcore_crc7_inserter_reg6[4], sdcore_crc7_inserter_reg6[3], (sdcore_crc7_inserter_reg6[2] ^ (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])), sdcore_crc7_inserter_reg6[1], sdcore_crc7_inserter_reg6[0], (sdcore_crc7_inserter_din[33] ^ sdcore_crc7_inserter_reg6[6])}; +assign sdcore_crc7_inserter_reg8 = {sdcore_crc7_inserter_reg7[5], sdcore_crc7_inserter_reg7[4], sdcore_crc7_inserter_reg7[3], (sdcore_crc7_inserter_reg7[2] ^ (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])), sdcore_crc7_inserter_reg7[1], sdcore_crc7_inserter_reg7[0], (sdcore_crc7_inserter_din[32] ^ sdcore_crc7_inserter_reg7[6])}; +assign sdcore_crc7_inserter_reg9 = {sdcore_crc7_inserter_reg8[5], sdcore_crc7_inserter_reg8[4], sdcore_crc7_inserter_reg8[3], (sdcore_crc7_inserter_reg8[2] ^ (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])), sdcore_crc7_inserter_reg8[1], sdcore_crc7_inserter_reg8[0], (sdcore_crc7_inserter_din[31] ^ sdcore_crc7_inserter_reg8[6])}; +assign sdcore_crc7_inserter_reg10 = {sdcore_crc7_inserter_reg9[5], sdcore_crc7_inserter_reg9[4], sdcore_crc7_inserter_reg9[3], (sdcore_crc7_inserter_reg9[2] ^ (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])), sdcore_crc7_inserter_reg9[1], sdcore_crc7_inserter_reg9[0], (sdcore_crc7_inserter_din[30] ^ sdcore_crc7_inserter_reg9[6])}; +assign sdcore_crc7_inserter_reg11 = {sdcore_crc7_inserter_reg10[5], sdcore_crc7_inserter_reg10[4], sdcore_crc7_inserter_reg10[3], (sdcore_crc7_inserter_reg10[2] ^ (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])), sdcore_crc7_inserter_reg10[1], sdcore_crc7_inserter_reg10[0], (sdcore_crc7_inserter_din[29] ^ sdcore_crc7_inserter_reg10[6])}; +assign sdcore_crc7_inserter_reg12 = {sdcore_crc7_inserter_reg11[5], sdcore_crc7_inserter_reg11[4], sdcore_crc7_inserter_reg11[3], (sdcore_crc7_inserter_reg11[2] ^ (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])), sdcore_crc7_inserter_reg11[1], sdcore_crc7_inserter_reg11[0], (sdcore_crc7_inserter_din[28] ^ sdcore_crc7_inserter_reg11[6])}; +assign sdcore_crc7_inserter_reg13 = {sdcore_crc7_inserter_reg12[5], sdcore_crc7_inserter_reg12[4], sdcore_crc7_inserter_reg12[3], (sdcore_crc7_inserter_reg12[2] ^ (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])), sdcore_crc7_inserter_reg12[1], sdcore_crc7_inserter_reg12[0], (sdcore_crc7_inserter_din[27] ^ sdcore_crc7_inserter_reg12[6])}; +assign sdcore_crc7_inserter_reg14 = {sdcore_crc7_inserter_reg13[5], sdcore_crc7_inserter_reg13[4], sdcore_crc7_inserter_reg13[3], (sdcore_crc7_inserter_reg13[2] ^ (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])), sdcore_crc7_inserter_reg13[1], sdcore_crc7_inserter_reg13[0], (sdcore_crc7_inserter_din[26] ^ sdcore_crc7_inserter_reg13[6])}; +assign sdcore_crc7_inserter_reg15 = {sdcore_crc7_inserter_reg14[5], sdcore_crc7_inserter_reg14[4], sdcore_crc7_inserter_reg14[3], (sdcore_crc7_inserter_reg14[2] ^ (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])), sdcore_crc7_inserter_reg14[1], sdcore_crc7_inserter_reg14[0], (sdcore_crc7_inserter_din[25] ^ sdcore_crc7_inserter_reg14[6])}; +assign sdcore_crc7_inserter_reg16 = {sdcore_crc7_inserter_reg15[5], sdcore_crc7_inserter_reg15[4], sdcore_crc7_inserter_reg15[3], (sdcore_crc7_inserter_reg15[2] ^ (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])), sdcore_crc7_inserter_reg15[1], sdcore_crc7_inserter_reg15[0], (sdcore_crc7_inserter_din[24] ^ sdcore_crc7_inserter_reg15[6])}; +assign sdcore_crc7_inserter_reg17 = {sdcore_crc7_inserter_reg16[5], sdcore_crc7_inserter_reg16[4], sdcore_crc7_inserter_reg16[3], (sdcore_crc7_inserter_reg16[2] ^ (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])), sdcore_crc7_inserter_reg16[1], sdcore_crc7_inserter_reg16[0], (sdcore_crc7_inserter_din[23] ^ sdcore_crc7_inserter_reg16[6])}; +assign sdcore_crc7_inserter_reg18 = {sdcore_crc7_inserter_reg17[5], sdcore_crc7_inserter_reg17[4], sdcore_crc7_inserter_reg17[3], (sdcore_crc7_inserter_reg17[2] ^ (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])), sdcore_crc7_inserter_reg17[1], sdcore_crc7_inserter_reg17[0], (sdcore_crc7_inserter_din[22] ^ sdcore_crc7_inserter_reg17[6])}; +assign sdcore_crc7_inserter_reg19 = {sdcore_crc7_inserter_reg18[5], sdcore_crc7_inserter_reg18[4], sdcore_crc7_inserter_reg18[3], (sdcore_crc7_inserter_reg18[2] ^ (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])), sdcore_crc7_inserter_reg18[1], sdcore_crc7_inserter_reg18[0], (sdcore_crc7_inserter_din[21] ^ sdcore_crc7_inserter_reg18[6])}; +assign sdcore_crc7_inserter_reg20 = {sdcore_crc7_inserter_reg19[5], sdcore_crc7_inserter_reg19[4], sdcore_crc7_inserter_reg19[3], (sdcore_crc7_inserter_reg19[2] ^ (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])), sdcore_crc7_inserter_reg19[1], sdcore_crc7_inserter_reg19[0], (sdcore_crc7_inserter_din[20] ^ sdcore_crc7_inserter_reg19[6])}; +assign sdcore_crc7_inserter_reg21 = {sdcore_crc7_inserter_reg20[5], sdcore_crc7_inserter_reg20[4], sdcore_crc7_inserter_reg20[3], (sdcore_crc7_inserter_reg20[2] ^ (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])), sdcore_crc7_inserter_reg20[1], sdcore_crc7_inserter_reg20[0], (sdcore_crc7_inserter_din[19] ^ sdcore_crc7_inserter_reg20[6])}; +assign sdcore_crc7_inserter_reg22 = {sdcore_crc7_inserter_reg21[5], sdcore_crc7_inserter_reg21[4], sdcore_crc7_inserter_reg21[3], (sdcore_crc7_inserter_reg21[2] ^ (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])), sdcore_crc7_inserter_reg21[1], sdcore_crc7_inserter_reg21[0], (sdcore_crc7_inserter_din[18] ^ sdcore_crc7_inserter_reg21[6])}; +assign sdcore_crc7_inserter_reg23 = {sdcore_crc7_inserter_reg22[5], sdcore_crc7_inserter_reg22[4], sdcore_crc7_inserter_reg22[3], (sdcore_crc7_inserter_reg22[2] ^ (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])), sdcore_crc7_inserter_reg22[1], sdcore_crc7_inserter_reg22[0], (sdcore_crc7_inserter_din[17] ^ sdcore_crc7_inserter_reg22[6])}; +assign sdcore_crc7_inserter_reg24 = {sdcore_crc7_inserter_reg23[5], sdcore_crc7_inserter_reg23[4], sdcore_crc7_inserter_reg23[3], (sdcore_crc7_inserter_reg23[2] ^ (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])), sdcore_crc7_inserter_reg23[1], sdcore_crc7_inserter_reg23[0], (sdcore_crc7_inserter_din[16] ^ sdcore_crc7_inserter_reg23[6])}; +assign sdcore_crc7_inserter_reg25 = {sdcore_crc7_inserter_reg24[5], sdcore_crc7_inserter_reg24[4], sdcore_crc7_inserter_reg24[3], (sdcore_crc7_inserter_reg24[2] ^ (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])), sdcore_crc7_inserter_reg24[1], sdcore_crc7_inserter_reg24[0], (sdcore_crc7_inserter_din[15] ^ sdcore_crc7_inserter_reg24[6])}; +assign sdcore_crc7_inserter_reg26 = {sdcore_crc7_inserter_reg25[5], sdcore_crc7_inserter_reg25[4], sdcore_crc7_inserter_reg25[3], (sdcore_crc7_inserter_reg25[2] ^ (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])), sdcore_crc7_inserter_reg25[1], sdcore_crc7_inserter_reg25[0], (sdcore_crc7_inserter_din[14] ^ sdcore_crc7_inserter_reg25[6])}; +assign sdcore_crc7_inserter_reg27 = {sdcore_crc7_inserter_reg26[5], sdcore_crc7_inserter_reg26[4], sdcore_crc7_inserter_reg26[3], (sdcore_crc7_inserter_reg26[2] ^ (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])), sdcore_crc7_inserter_reg26[1], sdcore_crc7_inserter_reg26[0], (sdcore_crc7_inserter_din[13] ^ sdcore_crc7_inserter_reg26[6])}; +assign sdcore_crc7_inserter_reg28 = {sdcore_crc7_inserter_reg27[5], sdcore_crc7_inserter_reg27[4], sdcore_crc7_inserter_reg27[3], (sdcore_crc7_inserter_reg27[2] ^ (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])), sdcore_crc7_inserter_reg27[1], sdcore_crc7_inserter_reg27[0], (sdcore_crc7_inserter_din[12] ^ sdcore_crc7_inserter_reg27[6])}; +assign sdcore_crc7_inserter_reg29 = {sdcore_crc7_inserter_reg28[5], sdcore_crc7_inserter_reg28[4], sdcore_crc7_inserter_reg28[3], (sdcore_crc7_inserter_reg28[2] ^ (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])), sdcore_crc7_inserter_reg28[1], sdcore_crc7_inserter_reg28[0], (sdcore_crc7_inserter_din[11] ^ sdcore_crc7_inserter_reg28[6])}; +assign sdcore_crc7_inserter_reg30 = {sdcore_crc7_inserter_reg29[5], sdcore_crc7_inserter_reg29[4], sdcore_crc7_inserter_reg29[3], (sdcore_crc7_inserter_reg29[2] ^ (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])), sdcore_crc7_inserter_reg29[1], sdcore_crc7_inserter_reg29[0], (sdcore_crc7_inserter_din[10] ^ sdcore_crc7_inserter_reg29[6])}; +assign sdcore_crc7_inserter_reg31 = {sdcore_crc7_inserter_reg30[5], sdcore_crc7_inserter_reg30[4], sdcore_crc7_inserter_reg30[3], (sdcore_crc7_inserter_reg30[2] ^ (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])), sdcore_crc7_inserter_reg30[1], sdcore_crc7_inserter_reg30[0], (sdcore_crc7_inserter_din[9] ^ sdcore_crc7_inserter_reg30[6])}; +assign sdcore_crc7_inserter_reg32 = {sdcore_crc7_inserter_reg31[5], sdcore_crc7_inserter_reg31[4], sdcore_crc7_inserter_reg31[3], (sdcore_crc7_inserter_reg31[2] ^ (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])), sdcore_crc7_inserter_reg31[1], sdcore_crc7_inserter_reg31[0], (sdcore_crc7_inserter_din[8] ^ sdcore_crc7_inserter_reg31[6])}; +assign sdcore_crc7_inserter_reg33 = {sdcore_crc7_inserter_reg32[5], sdcore_crc7_inserter_reg32[4], sdcore_crc7_inserter_reg32[3], (sdcore_crc7_inserter_reg32[2] ^ (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])), sdcore_crc7_inserter_reg32[1], sdcore_crc7_inserter_reg32[0], (sdcore_crc7_inserter_din[7] ^ sdcore_crc7_inserter_reg32[6])}; +assign sdcore_crc7_inserter_reg34 = {sdcore_crc7_inserter_reg33[5], sdcore_crc7_inserter_reg33[4], sdcore_crc7_inserter_reg33[3], (sdcore_crc7_inserter_reg33[2] ^ (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])), sdcore_crc7_inserter_reg33[1], sdcore_crc7_inserter_reg33[0], (sdcore_crc7_inserter_din[6] ^ sdcore_crc7_inserter_reg33[6])}; +assign sdcore_crc7_inserter_reg35 = {sdcore_crc7_inserter_reg34[5], sdcore_crc7_inserter_reg34[4], sdcore_crc7_inserter_reg34[3], (sdcore_crc7_inserter_reg34[2] ^ (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])), sdcore_crc7_inserter_reg34[1], sdcore_crc7_inserter_reg34[0], (sdcore_crc7_inserter_din[5] ^ sdcore_crc7_inserter_reg34[6])}; +assign sdcore_crc7_inserter_reg36 = {sdcore_crc7_inserter_reg35[5], sdcore_crc7_inserter_reg35[4], sdcore_crc7_inserter_reg35[3], (sdcore_crc7_inserter_reg35[2] ^ (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])), sdcore_crc7_inserter_reg35[1], sdcore_crc7_inserter_reg35[0], (sdcore_crc7_inserter_din[4] ^ sdcore_crc7_inserter_reg35[6])}; +assign sdcore_crc7_inserter_reg37 = {sdcore_crc7_inserter_reg36[5], sdcore_crc7_inserter_reg36[4], sdcore_crc7_inserter_reg36[3], (sdcore_crc7_inserter_reg36[2] ^ (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])), sdcore_crc7_inserter_reg36[1], sdcore_crc7_inserter_reg36[0], (sdcore_crc7_inserter_din[3] ^ sdcore_crc7_inserter_reg36[6])}; +assign sdcore_crc7_inserter_reg38 = {sdcore_crc7_inserter_reg37[5], sdcore_crc7_inserter_reg37[4], sdcore_crc7_inserter_reg37[3], (sdcore_crc7_inserter_reg37[2] ^ (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])), sdcore_crc7_inserter_reg37[1], sdcore_crc7_inserter_reg37[0], (sdcore_crc7_inserter_din[2] ^ sdcore_crc7_inserter_reg37[6])}; +assign sdcore_crc7_inserter_reg39 = {sdcore_crc7_inserter_reg38[5], sdcore_crc7_inserter_reg38[4], sdcore_crc7_inserter_reg38[3], (sdcore_crc7_inserter_reg38[2] ^ (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])), sdcore_crc7_inserter_reg38[1], sdcore_crc7_inserter_reg38[0], (sdcore_crc7_inserter_din[1] ^ sdcore_crc7_inserter_reg38[6])}; +assign sdcore_crc7_inserter_reg40 = {sdcore_crc7_inserter_reg39[5], sdcore_crc7_inserter_reg39[4], sdcore_crc7_inserter_reg39[3], (sdcore_crc7_inserter_reg39[2] ^ (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])), sdcore_crc7_inserter_reg39[1], sdcore_crc7_inserter_reg39[0], (sdcore_crc7_inserter_din[0] ^ sdcore_crc7_inserter_reg39[6])}; +always @(*) begin + sdcore_crc7_inserter_crc <= 7'd0; + if (sdcore_crc7_inserter_enable) begin + sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg40; + end else begin + sdcore_crc7_inserter_crc <= sdcore_crc7_inserter_reg0; + end +end +assign sdcore_crc16_inserter_crc0_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc0_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc0_din <= 2'd0; + sdcore_crc16_inserter_crc0_din[0] <= sdcore_crc16_inserter_sink_payload_data[0]; + sdcore_crc16_inserter_crc0_din[1] <= sdcore_crc16_inserter_sink_payload_data[4]; +end +assign sdcore_crc16_inserter_crc1_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc1_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc1_din <= 2'd0; + sdcore_crc16_inserter_crc1_din[0] <= sdcore_crc16_inserter_sink_payload_data[1]; + sdcore_crc16_inserter_crc1_din[1] <= sdcore_crc16_inserter_sink_payload_data[5]; +end +assign sdcore_crc16_inserter_crc2_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc2_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc2_din <= 2'd0; + sdcore_crc16_inserter_crc2_din[0] <= sdcore_crc16_inserter_sink_payload_data[2]; + sdcore_crc16_inserter_crc2_din[1] <= sdcore_crc16_inserter_sink_payload_data[6]; +end +assign sdcore_crc16_inserter_crc3_reset = ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready) & sdcore_crc16_inserter_source_last); +assign sdcore_crc16_inserter_crc3_enable = (sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready); +always @(*) begin + sdcore_crc16_inserter_crc3_din <= 2'd0; + sdcore_crc16_inserter_crc3_din[0] <= sdcore_crc16_inserter_sink_payload_data[3]; + sdcore_crc16_inserter_crc3_din[1] <= sdcore_crc16_inserter_sink_payload_data[7]; +end +assign sdcore_crc16_inserter_crc0_reg1 = {sdcore_crc16_inserter_crc0_reg0[14], sdcore_crc16_inserter_crc0_reg0[13], sdcore_crc16_inserter_crc0_reg0[12], (sdcore_crc16_inserter_crc0_reg0[11] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[10], sdcore_crc16_inserter_crc0_reg0[9], sdcore_crc16_inserter_crc0_reg0[8], sdcore_crc16_inserter_crc0_reg0[7], sdcore_crc16_inserter_crc0_reg0[6], sdcore_crc16_inserter_crc0_reg0[5], (sdcore_crc16_inserter_crc0_reg0[4] ^ (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])), sdcore_crc16_inserter_crc0_reg0[3], sdcore_crc16_inserter_crc0_reg0[2], sdcore_crc16_inserter_crc0_reg0[1], sdcore_crc16_inserter_crc0_reg0[0], (sdcore_crc16_inserter_crc0_din[1] ^ sdcore_crc16_inserter_crc0_reg0[15])}; +assign sdcore_crc16_inserter_crc0_reg2 = {sdcore_crc16_inserter_crc0_reg1[14], sdcore_crc16_inserter_crc0_reg1[13], sdcore_crc16_inserter_crc0_reg1[12], (sdcore_crc16_inserter_crc0_reg1[11] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[10], sdcore_crc16_inserter_crc0_reg1[9], sdcore_crc16_inserter_crc0_reg1[8], sdcore_crc16_inserter_crc0_reg1[7], sdcore_crc16_inserter_crc0_reg1[6], sdcore_crc16_inserter_crc0_reg1[5], (sdcore_crc16_inserter_crc0_reg1[4] ^ (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])), sdcore_crc16_inserter_crc0_reg1[3], sdcore_crc16_inserter_crc0_reg1[2], sdcore_crc16_inserter_crc0_reg1[1], sdcore_crc16_inserter_crc0_reg1[0], (sdcore_crc16_inserter_crc0_din[0] ^ sdcore_crc16_inserter_crc0_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc0_crc <= 16'd0; + if (sdcore_crc16_inserter_crc0_enable) begin + sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg2; + end else begin + sdcore_crc16_inserter_crc0_crc <= sdcore_crc16_inserter_crc0_reg0; + end +end +assign sdcore_crc16_inserter_crc1_reg1 = {sdcore_crc16_inserter_crc1_reg0[14], sdcore_crc16_inserter_crc1_reg0[13], sdcore_crc16_inserter_crc1_reg0[12], (sdcore_crc16_inserter_crc1_reg0[11] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[10], sdcore_crc16_inserter_crc1_reg0[9], sdcore_crc16_inserter_crc1_reg0[8], sdcore_crc16_inserter_crc1_reg0[7], sdcore_crc16_inserter_crc1_reg0[6], sdcore_crc16_inserter_crc1_reg0[5], (sdcore_crc16_inserter_crc1_reg0[4] ^ (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])), sdcore_crc16_inserter_crc1_reg0[3], sdcore_crc16_inserter_crc1_reg0[2], sdcore_crc16_inserter_crc1_reg0[1], sdcore_crc16_inserter_crc1_reg0[0], (sdcore_crc16_inserter_crc1_din[1] ^ sdcore_crc16_inserter_crc1_reg0[15])}; +assign sdcore_crc16_inserter_crc1_reg2 = {sdcore_crc16_inserter_crc1_reg1[14], sdcore_crc16_inserter_crc1_reg1[13], sdcore_crc16_inserter_crc1_reg1[12], (sdcore_crc16_inserter_crc1_reg1[11] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[10], sdcore_crc16_inserter_crc1_reg1[9], sdcore_crc16_inserter_crc1_reg1[8], sdcore_crc16_inserter_crc1_reg1[7], sdcore_crc16_inserter_crc1_reg1[6], sdcore_crc16_inserter_crc1_reg1[5], (sdcore_crc16_inserter_crc1_reg1[4] ^ (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])), sdcore_crc16_inserter_crc1_reg1[3], sdcore_crc16_inserter_crc1_reg1[2], sdcore_crc16_inserter_crc1_reg1[1], sdcore_crc16_inserter_crc1_reg1[0], (sdcore_crc16_inserter_crc1_din[0] ^ sdcore_crc16_inserter_crc1_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc1_crc <= 16'd0; + if (sdcore_crc16_inserter_crc1_enable) begin + sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg2; + end else begin + sdcore_crc16_inserter_crc1_crc <= sdcore_crc16_inserter_crc1_reg0; + end +end +assign sdcore_crc16_inserter_crc2_reg1 = {sdcore_crc16_inserter_crc2_reg0[14], sdcore_crc16_inserter_crc2_reg0[13], sdcore_crc16_inserter_crc2_reg0[12], (sdcore_crc16_inserter_crc2_reg0[11] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[10], sdcore_crc16_inserter_crc2_reg0[9], sdcore_crc16_inserter_crc2_reg0[8], sdcore_crc16_inserter_crc2_reg0[7], sdcore_crc16_inserter_crc2_reg0[6], sdcore_crc16_inserter_crc2_reg0[5], (sdcore_crc16_inserter_crc2_reg0[4] ^ (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])), sdcore_crc16_inserter_crc2_reg0[3], sdcore_crc16_inserter_crc2_reg0[2], sdcore_crc16_inserter_crc2_reg0[1], sdcore_crc16_inserter_crc2_reg0[0], (sdcore_crc16_inserter_crc2_din[1] ^ sdcore_crc16_inserter_crc2_reg0[15])}; +assign sdcore_crc16_inserter_crc2_reg2 = {sdcore_crc16_inserter_crc2_reg1[14], sdcore_crc16_inserter_crc2_reg1[13], sdcore_crc16_inserter_crc2_reg1[12], (sdcore_crc16_inserter_crc2_reg1[11] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[10], sdcore_crc16_inserter_crc2_reg1[9], sdcore_crc16_inserter_crc2_reg1[8], sdcore_crc16_inserter_crc2_reg1[7], sdcore_crc16_inserter_crc2_reg1[6], sdcore_crc16_inserter_crc2_reg1[5], (sdcore_crc16_inserter_crc2_reg1[4] ^ (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])), sdcore_crc16_inserter_crc2_reg1[3], sdcore_crc16_inserter_crc2_reg1[2], sdcore_crc16_inserter_crc2_reg1[1], sdcore_crc16_inserter_crc2_reg1[0], (sdcore_crc16_inserter_crc2_din[0] ^ sdcore_crc16_inserter_crc2_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc2_crc <= 16'd0; + if (sdcore_crc16_inserter_crc2_enable) begin + sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg2; + end else begin + sdcore_crc16_inserter_crc2_crc <= sdcore_crc16_inserter_crc2_reg0; + end +end +assign sdcore_crc16_inserter_crc3_reg1 = {sdcore_crc16_inserter_crc3_reg0[14], sdcore_crc16_inserter_crc3_reg0[13], sdcore_crc16_inserter_crc3_reg0[12], (sdcore_crc16_inserter_crc3_reg0[11] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[10], sdcore_crc16_inserter_crc3_reg0[9], sdcore_crc16_inserter_crc3_reg0[8], sdcore_crc16_inserter_crc3_reg0[7], sdcore_crc16_inserter_crc3_reg0[6], sdcore_crc16_inserter_crc3_reg0[5], (sdcore_crc16_inserter_crc3_reg0[4] ^ (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])), sdcore_crc16_inserter_crc3_reg0[3], sdcore_crc16_inserter_crc3_reg0[2], sdcore_crc16_inserter_crc3_reg0[1], sdcore_crc16_inserter_crc3_reg0[0], (sdcore_crc16_inserter_crc3_din[1] ^ sdcore_crc16_inserter_crc3_reg0[15])}; +assign sdcore_crc16_inserter_crc3_reg2 = {sdcore_crc16_inserter_crc3_reg1[14], sdcore_crc16_inserter_crc3_reg1[13], sdcore_crc16_inserter_crc3_reg1[12], (sdcore_crc16_inserter_crc3_reg1[11] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[10], sdcore_crc16_inserter_crc3_reg1[9], sdcore_crc16_inserter_crc3_reg1[8], sdcore_crc16_inserter_crc3_reg1[7], sdcore_crc16_inserter_crc3_reg1[6], sdcore_crc16_inserter_crc3_reg1[5], (sdcore_crc16_inserter_crc3_reg1[4] ^ (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])), sdcore_crc16_inserter_crc3_reg1[3], sdcore_crc16_inserter_crc3_reg1[2], sdcore_crc16_inserter_crc3_reg1[1], sdcore_crc16_inserter_crc3_reg1[0], (sdcore_crc16_inserter_crc3_din[0] ^ sdcore_crc16_inserter_crc3_reg1[15])}; +always @(*) begin + sdcore_crc16_inserter_crc3_crc <= 16'd0; + if (sdcore_crc16_inserter_crc3_enable) begin + sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg2; + end else begin + sdcore_crc16_inserter_crc3_crc <= sdcore_crc16_inserter_crc3_reg0; + end +end +always @(*) begin + sdcore_crc16_inserter_sink_ready <= 1'd0; + sdcore_crc16_inserter_source_valid <= 1'd0; + sdcore_crc16_inserter_source_first <= 1'd0; + sdcore_crc16_inserter_source_last <= 1'd0; + sdcore_crc16_inserter_source_payload_data <= 8'd0; + subfragments_sdcore_crc16inserter_next_state <= 1'd0; + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 3'd0; + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd0; + subfragments_sdcore_crc16inserter_next_state <= subfragments_sdcore_crc16inserter_state; + case (subfragments_sdcore_crc16inserter_state) + 1'd1: begin + sdcore_crc16_inserter_source_valid <= 1'd1; + sdcore_crc16_inserter_source_last <= (sdcore_crc16_inserter_count == 3'd7); + case (sdcore_crc16_inserter_count) + 1'd0: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[14]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[14]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[14]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[14]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[15]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[15]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[15]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[15]; + end + 1'd1: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[12]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[12]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[12]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[12]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[13]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[13]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[13]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[13]; + end + 2'd2: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[10]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[10]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[10]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[10]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[11]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[11]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[11]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[11]; + end + 2'd3: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[8]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[8]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[8]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[8]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[9]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[9]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[9]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[9]; + end + 3'd4: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[6]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[6]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[6]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[6]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[7]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[7]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[7]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[7]; + end + 3'd5: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[4]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[4]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[4]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[4]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[5]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[5]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[5]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[5]; + end + 3'd6: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[2]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[2]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[2]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[2]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[3]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[3]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[3]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[3]; + end + 3'd7: begin + sdcore_crc16_inserter_source_payload_data[0] <= sdcore_crc16_inserter_crc0_crc[0]; + sdcore_crc16_inserter_source_payload_data[1] <= sdcore_crc16_inserter_crc1_crc[0]; + sdcore_crc16_inserter_source_payload_data[2] <= sdcore_crc16_inserter_crc2_crc[0]; + sdcore_crc16_inserter_source_payload_data[3] <= sdcore_crc16_inserter_crc3_crc[0]; + sdcore_crc16_inserter_source_payload_data[4] <= sdcore_crc16_inserter_crc0_crc[1]; + sdcore_crc16_inserter_source_payload_data[5] <= sdcore_crc16_inserter_crc1_crc[1]; + sdcore_crc16_inserter_source_payload_data[6] <= sdcore_crc16_inserter_crc2_crc[1]; + sdcore_crc16_inserter_source_payload_data[7] <= sdcore_crc16_inserter_crc3_crc[1]; + end + endcase + if ((sdcore_crc16_inserter_source_valid & sdcore_crc16_inserter_source_ready)) begin + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= (sdcore_crc16_inserter_count + 1'd1); + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; + if (sdcore_crc16_inserter_source_last) begin + subfragments_sdcore_crc16inserter_next_state <= 1'd0; + end + end + end + default: begin + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value <= 1'd0; + sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce <= 1'd1; + sdcore_crc16_inserter_source_valid <= sdcore_crc16_inserter_sink_valid; + sdcore_crc16_inserter_sink_ready <= sdcore_crc16_inserter_source_ready; + sdcore_crc16_inserter_source_first <= sdcore_crc16_inserter_sink_first; + sdcore_crc16_inserter_source_payload_data <= sdcore_crc16_inserter_sink_payload_data; + sdcore_crc16_inserter_source_last <= 1'd0; + if ((sdcore_crc16_inserter_sink_valid & sdcore_crc16_inserter_sink_ready)) begin + if (sdcore_crc16_inserter_sink_last) begin + subfragments_sdcore_crc16inserter_next_state <= 1'd1; + end + end + end + endcase +end +assign sdcore_fifo_sink_valid = sdcore_sink_sink_valid1; +assign sdcore_sink_sink_ready1 = sdcore_fifo_sink_ready; +assign sdcore_fifo_sink_first = sdcore_sink_sink_first1; +assign sdcore_fifo_sink_last = sdcore_sink_sink_last1; +assign sdcore_fifo_sink_payload_data = sdcore_sink_sink_payload_data1; +assign sdcore_source_source_first1 = sdcore_fifo_source_first; +assign sdcore_source_source_last1 = sdcore_fifo_source_last; +assign sdcore_source_source_payload_data1 = sdcore_fifo_source_payload_data; +assign sdcore_source_source_valid1 = (sdcore_fifo_level >= 4'd8); +assign sdcore_fifo_source_ready = (sdcore_source_source_valid1 & sdcore_source_source_ready1); +assign sdcore_fifo_reset = ((sdcore_sink_sink_valid1 & sdcore_sink_sink_ready1) & sdcore_sink_sink_last1); +assign sdcore_fifo_syncfifo_din = {sdcore_fifo_fifo_in_last, sdcore_fifo_fifo_in_first, sdcore_fifo_fifo_in_payload_data}; +assign {sdcore_fifo_fifo_out_last, sdcore_fifo_fifo_out_first, sdcore_fifo_fifo_out_payload_data} = sdcore_fifo_syncfifo_dout; +assign sdcore_fifo_sink_ready = sdcore_fifo_syncfifo_writable; +assign sdcore_fifo_syncfifo_we = sdcore_fifo_sink_valid; +assign sdcore_fifo_fifo_in_first = sdcore_fifo_sink_first; +assign sdcore_fifo_fifo_in_last = sdcore_fifo_sink_last; +assign sdcore_fifo_fifo_in_payload_data = sdcore_fifo_sink_payload_data; +assign sdcore_fifo_source_valid = sdcore_fifo_syncfifo_readable; +assign sdcore_fifo_source_first = sdcore_fifo_fifo_out_first; +assign sdcore_fifo_source_last = sdcore_fifo_fifo_out_last; +assign sdcore_fifo_source_payload_data = sdcore_fifo_fifo_out_payload_data; +assign sdcore_fifo_syncfifo_re = sdcore_fifo_source_ready; +always @(*) begin + sdcore_fifo_wrport_adr <= 3'd0; + if (sdcore_fifo_replace) begin + sdcore_fifo_wrport_adr <= (sdcore_fifo_produce - 1'd1); + end else begin + sdcore_fifo_wrport_adr <= sdcore_fifo_produce; + end +end +assign sdcore_fifo_wrport_dat_w = sdcore_fifo_syncfifo_din; +assign sdcore_fifo_wrport_we = (sdcore_fifo_syncfifo_we & (sdcore_fifo_syncfifo_writable | sdcore_fifo_replace)); +assign sdcore_fifo_do_read = (sdcore_fifo_syncfifo_readable & sdcore_fifo_syncfifo_re); +assign sdcore_fifo_rdport_adr = sdcore_fifo_consume; +assign sdcore_fifo_syncfifo_dout = sdcore_fifo_rdport_dat_r; +assign sdcore_fifo_syncfifo_writable = (sdcore_fifo_level != 4'd8); +assign sdcore_fifo_syncfifo_readable = (sdcore_fifo_level != 1'd0); +always @(*) begin + sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; + sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd0; + sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; + sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd0; + sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; + sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd0; + sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; + sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd0; + cmdr_sink_valid <= 1'd0; + cmdr_sink_payload_cmd_type <= 2'd0; + cmdr_sink_payload_data_type <= 2'd0; + cmdr_sink_payload_length <= 8'd0; + cmdr_source_ready <= 1'd0; + dataw_sink_valid <= 1'd0; + sdcore_cmd_response_status_sdcore_fsm_next_value8 <= 128'd0; + sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd0; + dataw_sink_first <= 1'd0; + dataw_sink_last <= 1'd0; + dataw_sink_payload_data <= 8'd0; + cmdw_sink_valid <= 1'd0; + datar_sink_valid <= 1'd0; + cmdw_sink_last <= 1'd0; + datar_sink_last <= 1'd0; + cmdw_sink_payload_data <= 8'd0; + datar_sink_payload_block_length <= 10'd0; + cmdw_sink_payload_cmd_type <= 2'd0; + datar_source_ready <= 1'd0; + sdcore_crc16_inserter_source_ready <= 1'd0; + sdcore_sink_sink_valid1 <= 1'd0; + subfragments_sdcore_fsm_next_state <= 3'd0; + sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; + sdcore_sink_sink_first1 <= 1'd0; + sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd0; + sdcore_sink_sink_last1 <= 1'd0; + sdcore_sink_sink_payload_data1 <= 8'd0; + sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; + sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd0; + sdcore_cmd_count_sdcore_fsm_next_value2 <= 3'd0; + sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd0; + sdcore_data_count_sdcore_fsm_next_value3 <= 32'd0; + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd0; + subfragments_sdcore_fsm_next_state <= subfragments_sdcore_fsm_state; + case (subfragments_sdcore_fsm_state) + 1'd1: begin + cmdw_sink_valid <= 1'd1; + cmdw_sink_last <= (sdcore_cmd_count == 3'd5); + cmdw_sink_payload_cmd_type <= sdcore_cmd_type; + case (sdcore_cmd_count) + 1'd0: begin + cmdw_sink_payload_data <= {1'd0, 1'd1, sdcore_cmd}; + end + 1'd1: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[31:24]; + end + 2'd2: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[23:16]; + end + 2'd3: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[15:8]; + end + 3'd4: begin + cmdw_sink_payload_data <= sdcore_cmd_argument_storage[7:0]; + end + 3'd5: begin + cmdw_sink_payload_data <= {sdcore_crc7_inserter_crc, 1'd1}; + end + endcase + if (cmdw_sink_ready) begin + sdcore_cmd_count_sdcore_fsm_next_value2 <= (sdcore_cmd_count + 1'd1); + sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; + if (cmdw_sink_last) begin + if ((sdcore_cmd_type == 1'd0)) begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end else begin + subfragments_sdcore_fsm_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cmdr_sink_valid <= 1'd1; + cmdr_sink_payload_cmd_type <= sdcore_cmd_type; + cmdr_sink_payload_data_type <= sdcore_data_type; + if ((sdcore_cmd_type == 2'd2)) begin + cmdr_sink_payload_length <= 5'd18; + end else begin + cmdr_sink_payload_length <= 3'd6; + end + cmdr_source_ready <= 1'd1; + if (cmdr_source_valid) begin + if ((cmdr_source_payload_status == 1'd1)) begin + sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd1; + sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; + subfragments_sdcore_fsm_next_state <= 1'd0; + end else begin + if (cmdr_source_last) begin + if ((sdcore_data_type == 2'd2)) begin + subfragments_sdcore_fsm_next_state <= 2'd3; + end else begin + if ((sdcore_data_type == 1'd1)) begin + subfragments_sdcore_fsm_next_state <= 3'd4; + end else begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + end else begin + sdcore_cmd_response_status_sdcore_fsm_next_value8 <= {sdcore_cmd_response_status, cmdr_source_payload_data}; + sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 <= 1'd1; + end + end + end + end + 2'd3: begin + dataw_sink_valid <= sdcore_crc16_inserter_source_valid; + sdcore_crc16_inserter_source_ready <= dataw_sink_ready; + dataw_sink_first <= sdcore_crc16_inserter_source_first; + dataw_sink_last <= sdcore_crc16_inserter_source_last; + dataw_sink_payload_data <= sdcore_crc16_inserter_source_payload_data; + if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin + sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; + if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + datar_source_ready <= 1'd1; + if (datar_source_valid) begin + if ((datar_source_payload_status != 2'd2)) begin + sdcore_data_error_sdcore_fsm_next_value6 <= 1'd1; + sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; + end + end + end + 3'd4: begin + datar_sink_valid <= 1'd1; + datar_sink_payload_block_length <= sdcore_block_length_storage; + datar_sink_last <= (sdcore_data_count == (sdcore_block_count_storage - 1'd1)); + if (datar_source_valid) begin + if ((datar_source_payload_status == 1'd0)) begin + sdcore_sink_sink_valid1 <= datar_source_valid; + datar_source_ready <= sdcore_sink_sink_ready1; + sdcore_sink_sink_first1 <= datar_source_first; + sdcore_sink_sink_last1 <= datar_source_last; + sdcore_sink_sink_payload_data1 <= datar_source_payload_data; + if ((datar_source_last & datar_source_ready)) begin + sdcore_data_count_sdcore_fsm_next_value3 <= (sdcore_data_count + 1'd1); + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; + if ((sdcore_data_count == (sdcore_block_count_storage - 1'd1))) begin + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + end else begin + if ((datar_source_payload_status == 1'd1)) begin + sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd1; + sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; + datar_source_ready <= 1'd1; + subfragments_sdcore_fsm_next_state <= 1'd0; + end + end + end + end + default: begin + sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd1; + sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; + sdcore_data_done_sdcore_fsm_next_value1 <= 1'd1; + sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; + sdcore_cmd_count_sdcore_fsm_next_value2 <= 1'd0; + sdcore_cmd_count_sdcore_fsm_next_value_ce2 <= 1'd1; + sdcore_data_count_sdcore_fsm_next_value3 <= 1'd0; + sdcore_data_count_sdcore_fsm_next_value_ce3 <= 1'd1; + if (sdcore_cmd_send_re) begin + sdcore_cmd_done_sdcore_fsm_next_value0 <= 1'd0; + sdcore_cmd_done_sdcore_fsm_next_value_ce0 <= 1'd1; + sdcore_cmd_error_sdcore_fsm_next_value4 <= 1'd0; + sdcore_cmd_error_sdcore_fsm_next_value_ce4 <= 1'd1; + sdcore_cmd_timeout_sdcore_fsm_next_value5 <= 1'd0; + sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 <= 1'd1; + sdcore_data_done_sdcore_fsm_next_value1 <= 1'd0; + sdcore_data_done_sdcore_fsm_next_value_ce1 <= 1'd1; + sdcore_data_error_sdcore_fsm_next_value6 <= 1'd0; + sdcore_data_error_sdcore_fsm_next_value_ce6 <= 1'd1; + sdcore_data_timeout_sdcore_fsm_next_value7 <= 1'd0; + sdcore_data_timeout_sdcore_fsm_next_value_ce7 <= 1'd1; + subfragments_sdcore_fsm_next_state <= 1'd1; + end + end + endcase +end +assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first); +always @(*) begin + sdblock2mem_fifo_sink_first <= 1'd0; + sdblock2mem_fifo_sink_last <= 1'd0; + sdblock2mem_sink_sink_ready0 <= 1'd0; + sdblock2mem_fifo_sink_payload_data <= 8'd0; + sdblock2mem_fifo_sink_valid <= 1'd0; + if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin + sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0; + sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready; + sdblock2mem_fifo_sink_first <= sdblock2mem_sink_sink_first; + sdblock2mem_fifo_sink_last <= sdblock2mem_sink_sink_last0; + sdblock2mem_fifo_sink_payload_data <= sdblock2mem_sink_sink_payload_data0; + end else begin + sdblock2mem_sink_sink_ready0 <= 1'd1; + end +end +assign sdblock2mem_converter_sink_valid = sdblock2mem_fifo_source_valid; +assign sdblock2mem_fifo_source_ready = sdblock2mem_converter_sink_ready; +assign sdblock2mem_converter_sink_first = sdblock2mem_fifo_source_first; +assign sdblock2mem_converter_sink_last = sdblock2mem_fifo_source_last; +assign sdblock2mem_converter_sink_payload_data = sdblock2mem_fifo_source_payload_data; +assign sdblock2mem_wishbonedmawriter_sink_valid = sdblock2mem_source_source_valid; +assign sdblock2mem_source_source_ready = sdblock2mem_wishbonedmawriter_sink_ready; +assign sdblock2mem_wishbonedmawriter_sink_first = sdblock2mem_source_source_first; +assign sdblock2mem_wishbonedmawriter_sink_last = sdblock2mem_source_source_last; +assign sdblock2mem_wishbonedmawriter_sink_payload_data = sdblock2mem_source_source_payload_data; +assign sdblock2mem_fifo_syncfifo_din = {sdblock2mem_fifo_fifo_in_last, sdblock2mem_fifo_fifo_in_first, sdblock2mem_fifo_fifo_in_payload_data}; +assign {sdblock2mem_fifo_fifo_out_last, sdblock2mem_fifo_fifo_out_first, sdblock2mem_fifo_fifo_out_payload_data} = sdblock2mem_fifo_syncfifo_dout; +assign sdblock2mem_fifo_sink_ready = sdblock2mem_fifo_syncfifo_writable; +assign sdblock2mem_fifo_syncfifo_we = sdblock2mem_fifo_sink_valid; +assign sdblock2mem_fifo_fifo_in_first = sdblock2mem_fifo_sink_first; +assign sdblock2mem_fifo_fifo_in_last = sdblock2mem_fifo_sink_last; +assign sdblock2mem_fifo_fifo_in_payload_data = sdblock2mem_fifo_sink_payload_data; +assign sdblock2mem_fifo_source_valid = sdblock2mem_fifo_readable; +assign sdblock2mem_fifo_source_first = sdblock2mem_fifo_fifo_out_first; +assign sdblock2mem_fifo_source_last = sdblock2mem_fifo_fifo_out_last; +assign sdblock2mem_fifo_source_payload_data = sdblock2mem_fifo_fifo_out_payload_data; +assign sdblock2mem_fifo_re = sdblock2mem_fifo_source_ready; +assign sdblock2mem_fifo_syncfifo_re = (sdblock2mem_fifo_syncfifo_readable & ((~sdblock2mem_fifo_readable) | sdblock2mem_fifo_re)); +assign sdblock2mem_fifo_level1 = (sdblock2mem_fifo_level0 + sdblock2mem_fifo_readable); +always @(*) begin + sdblock2mem_fifo_wrport_adr <= 9'd0; + if (sdblock2mem_fifo_replace) begin + sdblock2mem_fifo_wrport_adr <= (sdblock2mem_fifo_produce - 1'd1); + end else begin + sdblock2mem_fifo_wrport_adr <= sdblock2mem_fifo_produce; + end +end +assign sdblock2mem_fifo_wrport_dat_w = sdblock2mem_fifo_syncfifo_din; +assign sdblock2mem_fifo_wrport_we = (sdblock2mem_fifo_syncfifo_we & (sdblock2mem_fifo_syncfifo_writable | sdblock2mem_fifo_replace)); +assign sdblock2mem_fifo_do_read = (sdblock2mem_fifo_syncfifo_readable & sdblock2mem_fifo_syncfifo_re); +assign sdblock2mem_fifo_rdport_adr = sdblock2mem_fifo_consume; +assign sdblock2mem_fifo_syncfifo_dout = sdblock2mem_fifo_rdport_dat_r; +assign sdblock2mem_fifo_rdport_re = sdblock2mem_fifo_do_read; +assign sdblock2mem_fifo_syncfifo_writable = (sdblock2mem_fifo_level0 != 10'd512); +assign sdblock2mem_fifo_syncfifo_readable = (sdblock2mem_fifo_level0 != 1'd0); +assign sdblock2mem_source_source_valid = sdblock2mem_converter_source_valid; +assign sdblock2mem_converter_source_ready = sdblock2mem_source_source_ready; +assign sdblock2mem_source_source_first = sdblock2mem_converter_source_first; +assign sdblock2mem_source_source_last = sdblock2mem_converter_source_last; +assign sdblock2mem_source_source_payload_data = sdblock2mem_converter_source_payload_data; +assign sdblock2mem_converter_sink_ready = ((~sdblock2mem_converter_strobe_all) | sdblock2mem_converter_source_ready); +assign sdblock2mem_converter_source_valid = sdblock2mem_converter_strobe_all; +assign sdblock2mem_converter_load_part = (sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready); +assign interface0_bus_stb = sdblock2mem_sink_sink_valid1; +assign interface0_bus_cyc = sdblock2mem_sink_sink_valid1; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sdblock2mem_sink_sink_payload_address; +assign interface0_bus_dat_w = {sdblock2mem_sink_sink_payload_data1[7:0], sdblock2mem_sink_sink_payload_data1[15:8], sdblock2mem_sink_sink_payload_data1[23:16], sdblock2mem_sink_sink_payload_data1[31:24]}; +assign sdblock2mem_sink_sink_ready1 = interface0_bus_ack; +assign sdblock2mem_wishbonedmawriter_base = sdblock2mem_wishbonedmawriter_base_storage[63:2]; +assign sdblock2mem_wishbonedmawriter_length = sdblock2mem_wishbonedmawriter_length_storage[31:2]; +assign sdblock2mem_wishbonedmawriter_offset_status = sdblock2mem_wishbonedmawriter_offset; +assign sdblock2mem_wishbonedmawriter_reset = (~sdblock2mem_wishbonedmawriter_enable_storage); +always @(*) begin + sdblock2mem_wishbonedmawriter_done_status <= 1'd0; + sdblock2mem_wishbonedmawriter_sink_ready <= 1'd0; + sdblock2mem_sink_sink_valid1 <= 1'd0; + subfragments_next_state <= 2'd0; + sdblock2mem_wishbonedmawriter_offset_next_value <= 32'd0; + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd0; + sdblock2mem_sink_sink_last1 <= 1'd0; + sdblock2mem_sink_sink_payload_address <= 32'd0; + sdblock2mem_sink_sink_payload_data1 <= 32'd0; + subfragments_next_state <= subfragments_state; + case (subfragments_state) + 1'd1: begin + sdblock2mem_sink_sink_valid1 <= sdblock2mem_wishbonedmawriter_sink_valid; + sdblock2mem_sink_sink_last1 <= (sdblock2mem_wishbonedmawriter_offset == (sdblock2mem_wishbonedmawriter_length - 1'd1)); + sdblock2mem_sink_sink_payload_address <= (sdblock2mem_wishbonedmawriter_base + sdblock2mem_wishbonedmawriter_offset); + sdblock2mem_sink_sink_payload_data1 <= sdblock2mem_wishbonedmawriter_sink_payload_data; + sdblock2mem_wishbonedmawriter_sink_ready <= sdblock2mem_sink_sink_ready1; + if ((sdblock2mem_wishbonedmawriter_sink_valid & sdblock2mem_wishbonedmawriter_sink_ready)) begin + sdblock2mem_wishbonedmawriter_offset_next_value <= (sdblock2mem_wishbonedmawriter_offset + 1'd1); + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; + if (sdblock2mem_sink_sink_last1) begin + if (sdblock2mem_wishbonedmawriter_loop_storage) begin + sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; + end else begin + subfragments_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdblock2mem_wishbonedmawriter_done_status <= 1'd1; + end + default: begin + sdblock2mem_wishbonedmawriter_sink_ready <= 1'd1; + sdblock2mem_wishbonedmawriter_offset_next_value <= 1'd0; + sdblock2mem_wishbonedmawriter_offset_next_value_ce <= 1'd1; + subfragments_next_state <= 1'd1; + end + endcase +end +assign sdmem2block_converter_sink_valid = sdmem2block_dma_source_valid; +assign sdmem2block_dma_source_ready = sdmem2block_converter_sink_ready; +assign sdmem2block_converter_sink_first = sdmem2block_dma_source_first; +assign sdmem2block_converter_sink_last = sdmem2block_dma_source_last; +assign sdmem2block_converter_sink_payload_data = sdmem2block_dma_source_payload_data; +assign sdmem2block_fifo_sink_valid = sdmem2block_source_source_valid1; +assign sdmem2block_source_source_ready1 = sdmem2block_fifo_sink_ready; +assign sdmem2block_fifo_sink_first = sdmem2block_source_source_first1; +assign sdmem2block_fifo_sink_last = sdmem2block_source_source_last1; +assign sdmem2block_fifo_sink_payload_data = sdmem2block_source_source_payload_data1; +assign sdmem2block_source_source_valid0 = sdmem2block_fifo_source_valid; +assign sdmem2block_fifo_source_ready = sdmem2block_source_source_ready0; +assign sdmem2block_source_source_first0 = sdmem2block_fifo_source_first; +assign sdmem2block_source_source_payload_data0 = sdmem2block_fifo_source_payload_data; +always @(*) begin + sdmem2block_source_source_last0 <= 1'd0; + sdmem2block_source_source_last0 <= sdmem2block_fifo_source_last; + if ((sdmem2block_count == 9'd511)) begin + sdmem2block_source_source_last0 <= 1'd1; + end +end +assign sdmem2block_dma_base = sdmem2block_dma_base_storage[63:2]; +assign sdmem2block_dma_length = sdmem2block_dma_length_storage[31:2]; +assign sdmem2block_dma_offset_status = sdmem2block_dma_offset; +assign sdmem2block_dma_reset = (~sdmem2block_dma_enable_storage); +always @(*) begin + interface1_bus_cyc <= 1'd0; + interface1_bus_stb <= 1'd0; + sdmem2block_dma_source_valid <= 1'd0; + interface1_bus_we <= 1'd0; + sdmem2block_dma_source_last <= 1'd0; + sdmem2block_dma_source_payload_data <= 32'd0; + subfragments_sdmem2blockdma_fsm_next_state <= 1'd0; + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= 32'd0; + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd0; + interface1_bus_adr <= 32'd0; + sdmem2block_dma_sink_ready <= 1'd0; + interface1_bus_sel <= 4'd0; + subfragments_sdmem2blockdma_fsm_next_state <= subfragments_sdmem2blockdma_fsm_state; + case (subfragments_sdmem2blockdma_fsm_state) + 1'd1: begin + sdmem2block_dma_source_valid <= 1'd1; + sdmem2block_dma_source_last <= sdmem2block_dma_sink_last; + sdmem2block_dma_source_payload_data <= sdmem2block_dma_data; + if (sdmem2block_dma_source_ready) begin + sdmem2block_dma_sink_ready <= 1'd1; + subfragments_sdmem2blockdma_fsm_next_state <= 1'd0; + end + end + default: begin + interface1_bus_stb <= sdmem2block_dma_sink_valid; + interface1_bus_cyc <= sdmem2block_dma_sink_valid; + interface1_bus_we <= 1'd0; + interface1_bus_sel <= 4'd15; + interface1_bus_adr <= sdmem2block_dma_sink_payload_address; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value <= {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; + sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce <= 1'd1; + subfragments_sdmem2blockdma_fsm_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0; + sdmem2block_dma_sink_last <= 1'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0; + sdmem2block_dma_sink_payload_address <= 32'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0; + sdmem2block_dma_sink_valid <= 1'd0; + sdmem2block_dma_done_status <= 1'd0; + subfragments_sdmem2blockdma_resetinserter_next_state <= subfragments_sdmem2blockdma_resetinserter_state; + case (subfragments_sdmem2blockdma_resetinserter_state) + 1'd1: begin + sdmem2block_dma_sink_valid <= 1'd1; + sdmem2block_dma_sink_last <= (sdmem2block_dma_offset == (sdmem2block_dma_length - 1'd1)); + sdmem2block_dma_sink_payload_address <= (sdmem2block_dma_base + sdmem2block_dma_offset); + if (sdmem2block_dma_sink_ready) begin + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= (sdmem2block_dma_offset + 1'd1); + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; + if (sdmem2block_dma_sink_last) begin + if (sdmem2block_dma_loop_storage) begin + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; + end else begin + subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdmem2block_dma_done_status <= 1'd1; + end + default: begin + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 1'd0; + sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd1; + subfragments_sdmem2blockdma_resetinserter_next_state <= 1'd1; + end + endcase +end +assign sdmem2block_source_source_valid1 = sdmem2block_converter_source_valid; +assign sdmem2block_converter_source_ready = sdmem2block_source_source_ready1; +assign sdmem2block_source_source_first1 = sdmem2block_converter_source_first; +assign sdmem2block_source_source_last1 = sdmem2block_converter_source_last; +assign sdmem2block_source_source_payload_data1 = sdmem2block_converter_source_payload_data; +assign sdmem2block_converter_first = (sdmem2block_converter_mux == 1'd0); +assign sdmem2block_converter_last = (sdmem2block_converter_mux == 2'd3); +assign sdmem2block_converter_source_valid = sdmem2block_converter_sink_valid; +assign sdmem2block_converter_source_first = (sdmem2block_converter_sink_first & sdmem2block_converter_first); +assign sdmem2block_converter_source_last = (sdmem2block_converter_sink_last & sdmem2block_converter_last); +assign sdmem2block_converter_sink_ready = (sdmem2block_converter_last & sdmem2block_converter_source_ready); +always @(*) begin + sdmem2block_converter_source_payload_data <= 8'd0; + case (sdmem2block_converter_mux) + 1'd0: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[31:24]; + end + 1'd1: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[23:16]; + end + 2'd2: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[15:8]; + end + default: begin + sdmem2block_converter_source_payload_data <= sdmem2block_converter_sink_payload_data[7:0]; + end + endcase +end +assign sdmem2block_converter_source_payload_valid_token_count = sdmem2block_converter_last; +assign sdmem2block_fifo_syncfifo_din = {sdmem2block_fifo_fifo_in_last, sdmem2block_fifo_fifo_in_first, sdmem2block_fifo_fifo_in_payload_data}; +assign {sdmem2block_fifo_fifo_out_last, sdmem2block_fifo_fifo_out_first, sdmem2block_fifo_fifo_out_payload_data} = sdmem2block_fifo_syncfifo_dout; +assign sdmem2block_fifo_sink_ready = sdmem2block_fifo_syncfifo_writable; +assign sdmem2block_fifo_syncfifo_we = sdmem2block_fifo_sink_valid; +assign sdmem2block_fifo_fifo_in_first = sdmem2block_fifo_sink_first; +assign sdmem2block_fifo_fifo_in_last = sdmem2block_fifo_sink_last; +assign sdmem2block_fifo_fifo_in_payload_data = sdmem2block_fifo_sink_payload_data; +assign sdmem2block_fifo_source_valid = sdmem2block_fifo_readable; +assign sdmem2block_fifo_source_first = sdmem2block_fifo_fifo_out_first; +assign sdmem2block_fifo_source_last = sdmem2block_fifo_fifo_out_last; +assign sdmem2block_fifo_source_payload_data = sdmem2block_fifo_fifo_out_payload_data; +assign sdmem2block_fifo_re = sdmem2block_fifo_source_ready; +assign sdmem2block_fifo_syncfifo_re = (sdmem2block_fifo_syncfifo_readable & ((~sdmem2block_fifo_readable) | sdmem2block_fifo_re)); +assign sdmem2block_fifo_level1 = (sdmem2block_fifo_level0 + sdmem2block_fifo_readable); +always @(*) begin + sdmem2block_fifo_wrport_adr <= 9'd0; + if (sdmem2block_fifo_replace) begin + sdmem2block_fifo_wrport_adr <= (sdmem2block_fifo_produce - 1'd1); + end else begin + sdmem2block_fifo_wrport_adr <= sdmem2block_fifo_produce; + end +end +assign sdmem2block_fifo_wrport_dat_w = sdmem2block_fifo_syncfifo_din; +assign sdmem2block_fifo_wrport_we = (sdmem2block_fifo_syncfifo_we & (sdmem2block_fifo_syncfifo_writable | sdmem2block_fifo_replace)); +assign sdmem2block_fifo_do_read = (sdmem2block_fifo_syncfifo_readable & sdmem2block_fifo_syncfifo_re); +assign sdmem2block_fifo_rdport_adr = sdmem2block_fifo_consume; +assign sdmem2block_fifo_syncfifo_dout = sdmem2block_fifo_rdport_dat_r; +assign sdmem2block_fifo_rdport_re = sdmem2block_fifo_do_read; +assign sdmem2block_fifo_syncfifo_writable = (sdmem2block_fifo_level0 != 10'd512); +assign sdmem2block_fifo_syncfifo_readable = (sdmem2block_fifo_level0 != 1'd0); +assign eventmanager_card_detect0 = card_detect_status1; +assign eventmanager_card_detect1 = card_detect_pending; +always @(*) begin + card_detect_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + card_detect_clear <= 1'd1; + end +end +assign eventmanager_block2mem_dma0 = block2mem_dma_status; +assign eventmanager_block2mem_dma1 = block2mem_dma_pending; +always @(*) begin + block2mem_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + block2mem_dma_clear <= 1'd1; + end +end +assign eventmanager_mem2block_dma0 = mem2block_dma_status; +assign eventmanager_mem2block_dma1 = mem2block_dma_pending; +always @(*) begin + mem2block_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin + mem2block_dma_clear <= 1'd1; + end +end +assign eventmanager_cmd_done0 = cmd_done_status; +assign eventmanager_cmd_done1 = cmd_done_pending; +always @(*) begin + cmd_done_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin + cmd_done_clear <= 1'd1; + end +end +assign sdirq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); +assign card_detect_status1 = 1'd0; +assign block2mem_dma_status = 1'd0; +assign mem2block_dma_status = 1'd0; +assign cmd_done_status = cmd_done_trigger; +assign cmd_done_pending = cmd_done_trigger; +always @(*) begin + litesdcardcore_litesdcardcore_wishbone_dat_r <= 32'd0; + litesdcardcore_next_state <= 1'd0; + litesdcardcore_litesdcardcore_adr <= 14'd0; + litesdcardcore_litesdcardcore_we <= 1'd0; + litesdcardcore_litesdcardcore_wishbone_ack <= 1'd0; + litesdcardcore_litesdcardcore_dat_w <= 32'd0; + litesdcardcore_next_state <= litesdcardcore_state; + case (litesdcardcore_state) + 1'd1: begin + litesdcardcore_litesdcardcore_wishbone_ack <= 1'd1; + litesdcardcore_litesdcardcore_wishbone_dat_r <= litesdcardcore_litesdcardcore_dat_r; + litesdcardcore_next_state <= 1'd0; + end + default: begin + litesdcardcore_litesdcardcore_dat_w <= litesdcardcore_litesdcardcore_wishbone_dat_w; + if ((litesdcardcore_litesdcardcore_wishbone_cyc & litesdcardcore_litesdcardcore_wishbone_stb)) begin + litesdcardcore_litesdcardcore_adr <= litesdcardcore_litesdcardcore_wishbone_adr; + litesdcardcore_litesdcardcore_we <= (litesdcardcore_litesdcardcore_wishbone_we & (litesdcardcore_litesdcardcore_wishbone_sel != 1'd0)); + litesdcardcore_next_state <= 1'd1; + end + end + endcase +end +assign litesdcardcore_litesdcardcore_wishbone_adr = wb_ctrl_adr_1; +assign litesdcardcore_litesdcardcore_wishbone_dat_w = wb_ctrl_dat_w_1; +assign wb_ctrl_dat_r_1 = litesdcardcore_litesdcardcore_wishbone_dat_r; +assign litesdcardcore_litesdcardcore_wishbone_sel = wb_ctrl_sel_1; +assign litesdcardcore_litesdcardcore_wishbone_cyc = wb_ctrl_cyc_1; +assign litesdcardcore_litesdcardcore_wishbone_stb = wb_ctrl_stb_1; +assign wb_ctrl_ack_1 = litesdcardcore_litesdcardcore_wishbone_ack; +assign litesdcardcore_litesdcardcore_wishbone_we = wb_ctrl_we_1; +assign litesdcardcore_litesdcardcore_wishbone_cti = wb_ctrl_cti_1; +assign litesdcardcore_litesdcardcore_wishbone_bte = wb_ctrl_bte_1; +assign wb_ctrl_err_1 = litesdcardcore_litesdcardcore_wishbone_err; +assign litesdcardcore_shared_adr = array_muxed0; +assign litesdcardcore_shared_dat_w = array_muxed1; +assign litesdcardcore_shared_sel = array_muxed2; +assign litesdcardcore_shared_cyc = array_muxed3; +assign litesdcardcore_shared_stb = array_muxed4; +assign litesdcardcore_shared_we = array_muxed5; +assign litesdcardcore_shared_cti = array_muxed6; +assign litesdcardcore_shared_bte = array_muxed7; +assign interface0_bus_dat_r = litesdcardcore_shared_dat_r; +assign interface1_bus_dat_r = litesdcardcore_shared_dat_r; +assign interface0_bus_ack = (litesdcardcore_shared_ack & (litesdcardcore_grant == 1'd0)); +assign interface1_bus_ack = (litesdcardcore_shared_ack & (litesdcardcore_grant == 1'd1)); +assign interface0_bus_err = (litesdcardcore_shared_err & (litesdcardcore_grant == 1'd0)); +assign interface1_bus_err = (litesdcardcore_shared_err & (litesdcardcore_grant == 1'd1)); +assign litesdcardcore_request = {interface1_bus_cyc, interface0_bus_cyc}; +assign litesdcardcore_slave_sel = 1'd1; +assign wb_dma_adr_1 = litesdcardcore_shared_adr; +assign wb_dma_dat_w_1 = litesdcardcore_shared_dat_w; +assign wb_dma_sel_1 = litesdcardcore_shared_sel; +assign wb_dma_stb_1 = litesdcardcore_shared_stb; +assign wb_dma_we_1 = litesdcardcore_shared_we; +assign wb_dma_cti_1 = litesdcardcore_shared_cti; +assign wb_dma_bte_1 = litesdcardcore_shared_bte; +assign wb_dma_cyc_1 = (litesdcardcore_shared_cyc & litesdcardcore_slave_sel); +assign litesdcardcore_shared_err = wb_dma_err_1; +assign litesdcardcore_wait = ((litesdcardcore_shared_stb & litesdcardcore_shared_cyc) & (~litesdcardcore_shared_ack)); +always @(*) begin + litesdcardcore_error <= 1'd0; + litesdcardcore_shared_ack <= 1'd0; + litesdcardcore_shared_dat_r <= 32'd0; + litesdcardcore_shared_ack <= wb_dma_ack_1; + litesdcardcore_shared_dat_r <= ({32{litesdcardcore_slave_sel_r}} & wb_dma_dat_r_1); + if (litesdcardcore_done) begin + litesdcardcore_shared_dat_r <= 32'd4294967295; + litesdcardcore_shared_ack <= 1'd1; + litesdcardcore_error <= 1'd1; + end +end +assign litesdcardcore_done = (litesdcardcore_count == 1'd0); +assign litesdcardcore_csrbank0_sel = (litesdcardcore_interface0_bank_bus_adr[13:9] == 1'd0); +assign litesdcardcore_csrbank0_reset0_r = litesdcardcore_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + litesdcardcore_csrbank0_reset0_re <= 1'd0; + litesdcardcore_csrbank0_reset0_we <= 1'd0; + if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank0_reset0_re <= litesdcardcore_interface0_bank_bus_we; + litesdcardcore_csrbank0_reset0_we <= (~litesdcardcore_interface0_bank_bus_we); + end +end +assign litesdcardcore_csrbank0_scratch0_r = litesdcardcore_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank0_scratch0_we <= 1'd0; + litesdcardcore_csrbank0_scratch0_re <= 1'd0; + if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank0_scratch0_re <= litesdcardcore_interface0_bank_bus_we; + litesdcardcore_csrbank0_scratch0_we <= (~litesdcardcore_interface0_bank_bus_we); + end +end +assign litesdcardcore_csrbank0_bus_errors_r = litesdcardcore_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank0_bus_errors_we <= 1'd0; + litesdcardcore_csrbank0_bus_errors_re <= 1'd0; + if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank0_bus_errors_re <= litesdcardcore_interface0_bank_bus_we; + litesdcardcore_csrbank0_bus_errors_we <= (~litesdcardcore_interface0_bank_bus_we); + end +end +always @(*) begin + soc_rst <= 1'd0; + if (reset_re) begin + soc_rst <= reset_storage[0]; + end +end +assign cpu_rst = reset_storage[1]; +assign litesdcardcore_csrbank0_reset0_w = reset_storage[1:0]; +assign litesdcardcore_csrbank0_scratch0_w = scratch_storage[31:0]; +assign litesdcardcore_csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = litesdcardcore_csrbank0_bus_errors_we; +assign litesdcardcore_csrbank1_sel = (litesdcardcore_interface1_bank_bus_adr[13:9] == 1'd1); +assign litesdcardcore_csrbank1_dma_base1_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_base1_we <= 1'd0; + litesdcardcore_csrbank1_dma_base1_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank1_dma_base1_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_base1_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_base0_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_base0_re <= 1'd0; + litesdcardcore_csrbank1_dma_base0_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank1_dma_base0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_base0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_length0_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_length0_re <= 1'd0; + litesdcardcore_csrbank1_dma_length0_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank1_dma_length0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_length0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_enable0_r = litesdcardcore_interface1_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank1_dma_enable0_we <= 1'd0; + litesdcardcore_csrbank1_dma_enable0_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank1_dma_enable0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_enable0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_done_r = litesdcardcore_interface1_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank1_dma_done_re <= 1'd0; + litesdcardcore_csrbank1_dma_done_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 3'd4))) begin + litesdcardcore_csrbank1_dma_done_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_done_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_loop0_r = litesdcardcore_interface1_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank1_dma_loop0_re <= 1'd0; + litesdcardcore_csrbank1_dma_loop0_we <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 3'd5))) begin + litesdcardcore_csrbank1_dma_loop0_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_loop0_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_offset_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank1_dma_offset_we <= 1'd0; + litesdcardcore_csrbank1_dma_offset_re <= 1'd0; + if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 3'd6))) begin + litesdcardcore_csrbank1_dma_offset_re <= litesdcardcore_interface1_bank_bus_we; + litesdcardcore_csrbank1_dma_offset_we <= (~litesdcardcore_interface1_bank_bus_we); + end +end +assign litesdcardcore_csrbank1_dma_base1_w = sdblock2mem_wishbonedmawriter_base_storage[63:32]; +assign litesdcardcore_csrbank1_dma_base0_w = sdblock2mem_wishbonedmawriter_base_storage[31:0]; +assign litesdcardcore_csrbank1_dma_length0_w = sdblock2mem_wishbonedmawriter_length_storage[31:0]; +assign litesdcardcore_csrbank1_dma_enable0_w = sdblock2mem_wishbonedmawriter_enable_storage; +assign litesdcardcore_csrbank1_dma_done_w = sdblock2mem_wishbonedmawriter_done_status; +assign sdblock2mem_wishbonedmawriter_done_we = litesdcardcore_csrbank1_dma_done_we; +assign litesdcardcore_csrbank1_dma_loop0_w = sdblock2mem_wishbonedmawriter_loop_storage; +assign litesdcardcore_csrbank1_dma_offset_w = sdblock2mem_wishbonedmawriter_offset_status[31:0]; +assign sdblock2mem_wishbonedmawriter_offset_we = litesdcardcore_csrbank1_dma_offset_we; +assign litesdcardcore_csrbank2_sel = (litesdcardcore_interface2_bank_bus_adr[13:9] == 2'd2); +assign litesdcardcore_csrbank2_cmd_argument0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_argument0_re <= 1'd0; + litesdcardcore_csrbank2_cmd_argument0_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank2_cmd_argument0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_argument0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_command0_r = litesdcardcore_interface2_bank_bus_dat_w[13:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_command0_re <= 1'd0; + litesdcardcore_csrbank2_cmd_command0_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank2_cmd_command0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_command0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_send0_r = litesdcardcore_interface2_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_send0_we <= 1'd0; + litesdcardcore_csrbank2_cmd_send0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank2_cmd_send0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_send0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response3_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response3_re <= 1'd0; + litesdcardcore_csrbank2_cmd_response3_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank2_cmd_response3_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response3_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response2_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response2_re <= 1'd0; + litesdcardcore_csrbank2_cmd_response2_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd4))) begin + litesdcardcore_csrbank2_cmd_response2_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response2_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response1_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response1_we <= 1'd0; + litesdcardcore_csrbank2_cmd_response1_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd5))) begin + litesdcardcore_csrbank2_cmd_response1_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response1_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_response0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_response0_we <= 1'd0; + litesdcardcore_csrbank2_cmd_response0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd6))) begin + litesdcardcore_csrbank2_cmd_response0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_response0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_event_r = litesdcardcore_interface2_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank2_cmd_event_re <= 1'd0; + litesdcardcore_csrbank2_cmd_event_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 3'd7))) begin + litesdcardcore_csrbank2_cmd_event_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_cmd_event_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_data_event_r = litesdcardcore_interface2_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank2_data_event_re <= 1'd0; + litesdcardcore_csrbank2_data_event_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd8))) begin + litesdcardcore_csrbank2_data_event_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_data_event_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_block_length0_r = litesdcardcore_interface2_bank_bus_dat_w[9:0]; +always @(*) begin + litesdcardcore_csrbank2_block_length0_we <= 1'd0; + litesdcardcore_csrbank2_block_length0_re <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd9))) begin + litesdcardcore_csrbank2_block_length0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_block_length0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_block_count0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank2_block_count0_re <= 1'd0; + litesdcardcore_csrbank2_block_count0_we <= 1'd0; + if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd10))) begin + litesdcardcore_csrbank2_block_count0_re <= litesdcardcore_interface2_bank_bus_we; + litesdcardcore_csrbank2_block_count0_we <= (~litesdcardcore_interface2_bank_bus_we); + end +end +assign litesdcardcore_csrbank2_cmd_argument0_w = sdcore_cmd_argument_storage[31:0]; +assign sdcore_csrfield_cmd_type = sdcore_cmd_command_storage[1:0]; +assign sdcore_csrfield_data_type = sdcore_cmd_command_storage[6:5]; +assign sdcore_csrfield_cmd = sdcore_cmd_command_storage[13:8]; +assign litesdcardcore_csrbank2_cmd_command0_w = sdcore_cmd_command_storage[13:0]; +assign litesdcardcore_csrbank2_cmd_send0_w = sdcore_cmd_send_storage; +assign litesdcardcore_csrbank2_cmd_response3_w = sdcore_cmd_response_status[127:96]; +assign litesdcardcore_csrbank2_cmd_response2_w = sdcore_cmd_response_status[95:64]; +assign litesdcardcore_csrbank2_cmd_response1_w = sdcore_cmd_response_status[63:32]; +assign litesdcardcore_csrbank2_cmd_response0_w = sdcore_cmd_response_status[31:0]; +assign sdcore_cmd_response_we = litesdcardcore_csrbank2_cmd_response0_we; +always @(*) begin + sdcore_cmd_event_status <= 4'd0; + sdcore_cmd_event_status[0] <= sdcore_csrfield_done0; + sdcore_cmd_event_status[1] <= sdcore_csrfield_error0; + sdcore_cmd_event_status[2] <= sdcore_csrfield_timeout0; + sdcore_cmd_event_status[3] <= sdcore_csrfield_crc0; +end +assign litesdcardcore_csrbank2_cmd_event_w = sdcore_cmd_event_status[3:0]; +assign sdcore_cmd_event_we = litesdcardcore_csrbank2_cmd_event_we; +always @(*) begin + sdcore_data_event_status <= 4'd0; + sdcore_data_event_status[0] <= sdcore_csrfield_done1; + sdcore_data_event_status[1] <= sdcore_csrfield_error1; + sdcore_data_event_status[2] <= sdcore_csrfield_timeout1; + sdcore_data_event_status[3] <= sdcore_csrfield_crc1; +end +assign litesdcardcore_csrbank2_data_event_w = sdcore_data_event_status[3:0]; +assign sdcore_data_event_we = litesdcardcore_csrbank2_data_event_we; +assign litesdcardcore_csrbank2_block_length0_w = sdcore_block_length_storage[9:0]; +assign litesdcardcore_csrbank2_block_count0_w = sdcore_block_count_storage[31:0]; +assign litesdcardcore_csrbank3_sel = (litesdcardcore_interface3_bank_bus_adr[13:9] == 2'd3); +assign litesdcardcore_csrbank3_status_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank3_status_we <= 1'd0; + litesdcardcore_csrbank3_status_re <= 1'd0; + if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank3_status_re <= litesdcardcore_interface3_bank_bus_we; + litesdcardcore_csrbank3_status_we <= (~litesdcardcore_interface3_bank_bus_we); + end +end +assign litesdcardcore_csrbank3_pending_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank3_pending_re <= 1'd0; + litesdcardcore_csrbank3_pending_we <= 1'd0; + if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank3_pending_re <= litesdcardcore_interface3_bank_bus_we; + litesdcardcore_csrbank3_pending_we <= (~litesdcardcore_interface3_bank_bus_we); + end +end +assign litesdcardcore_csrbank3_enable0_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; +always @(*) begin + litesdcardcore_csrbank3_enable0_we <= 1'd0; + litesdcardcore_csrbank3_enable0_re <= 1'd0; + if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank3_enable0_re <= litesdcardcore_interface3_bank_bus_we; + litesdcardcore_csrbank3_enable0_we <= (~litesdcardcore_interface3_bank_bus_we); + end +end +always @(*) begin + eventmanager_status_status <= 4'd0; + eventmanager_status_status[0] <= eventmanager_card_detect0; + eventmanager_status_status[1] <= eventmanager_block2mem_dma0; + eventmanager_status_status[2] <= eventmanager_mem2block_dma0; + eventmanager_status_status[3] <= eventmanager_cmd_done0; +end +assign litesdcardcore_csrbank3_status_w = eventmanager_status_status[3:0]; +assign eventmanager_status_we = litesdcardcore_csrbank3_status_we; +always @(*) begin + eventmanager_pending_status <= 4'd0; + eventmanager_pending_status[0] <= eventmanager_card_detect1; + eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; + eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; + eventmanager_pending_status[3] <= eventmanager_cmd_done1; +end +assign litesdcardcore_csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign eventmanager_pending_we = litesdcardcore_csrbank3_pending_we; +assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; +assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; +assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; +assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; +assign litesdcardcore_csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign litesdcardcore_csrbank4_sel = (litesdcardcore_interface4_bank_bus_adr[13:9] == 3'd4); +assign litesdcardcore_csrbank4_dma_base1_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_base1_re <= 1'd0; + litesdcardcore_csrbank4_dma_base1_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank4_dma_base1_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_base1_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_base0_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_base0_we <= 1'd0; + litesdcardcore_csrbank4_dma_base0_re <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank4_dma_base0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_base0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_length0_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_length0_re <= 1'd0; + litesdcardcore_csrbank4_dma_length0_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 2'd2))) begin + litesdcardcore_csrbank4_dma_length0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_length0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_enable0_r = litesdcardcore_interface4_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank4_dma_enable0_we <= 1'd0; + litesdcardcore_csrbank4_dma_enable0_re <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank4_dma_enable0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_enable0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_done_r = litesdcardcore_interface4_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank4_dma_done_we <= 1'd0; + litesdcardcore_csrbank4_dma_done_re <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd4))) begin + litesdcardcore_csrbank4_dma_done_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_done_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_loop0_r = litesdcardcore_interface4_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank4_dma_loop0_re <= 1'd0; + litesdcardcore_csrbank4_dma_loop0_we <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd5))) begin + litesdcardcore_csrbank4_dma_loop0_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_loop0_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_offset_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; +always @(*) begin + litesdcardcore_csrbank4_dma_offset_we <= 1'd0; + litesdcardcore_csrbank4_dma_offset_re <= 1'd0; + if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd6))) begin + litesdcardcore_csrbank4_dma_offset_re <= litesdcardcore_interface4_bank_bus_we; + litesdcardcore_csrbank4_dma_offset_we <= (~litesdcardcore_interface4_bank_bus_we); + end +end +assign litesdcardcore_csrbank4_dma_base1_w = sdmem2block_dma_base_storage[63:32]; +assign litesdcardcore_csrbank4_dma_base0_w = sdmem2block_dma_base_storage[31:0]; +assign litesdcardcore_csrbank4_dma_length0_w = sdmem2block_dma_length_storage[31:0]; +assign litesdcardcore_csrbank4_dma_enable0_w = sdmem2block_dma_enable_storage; +assign litesdcardcore_csrbank4_dma_done_w = sdmem2block_dma_done_status; +assign sdmem2block_dma_done_we = litesdcardcore_csrbank4_dma_done_we; +assign litesdcardcore_csrbank4_dma_loop0_w = sdmem2block_dma_loop_storage; +assign litesdcardcore_csrbank4_dma_offset_w = sdmem2block_dma_offset_status[31:0]; +assign sdmem2block_dma_offset_we = litesdcardcore_csrbank4_dma_offset_we; +assign litesdcardcore_csrbank5_sel = (litesdcardcore_interface5_bank_bus_adr[13:9] == 3'd5); +assign litesdcardcore_csrbank5_card_detect_r = litesdcardcore_interface5_bank_bus_dat_w[0]; +always @(*) begin + litesdcardcore_csrbank5_card_detect_we <= 1'd0; + litesdcardcore_csrbank5_card_detect_re <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 1'd0))) begin + litesdcardcore_csrbank5_card_detect_re <= litesdcardcore_interface5_bank_bus_we; + litesdcardcore_csrbank5_card_detect_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign litesdcardcore_csrbank5_clocker_divider0_r = litesdcardcore_interface5_bank_bus_dat_w[8:0]; +always @(*) begin + litesdcardcore_csrbank5_clocker_divider0_re <= 1'd0; + litesdcardcore_csrbank5_clocker_divider0_we <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 1'd1))) begin + litesdcardcore_csrbank5_clocker_divider0_re <= litesdcardcore_interface5_bank_bus_we; + litesdcardcore_csrbank5_clocker_divider0_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign init_initialize_r = litesdcardcore_interface5_bank_bus_dat_w[0]; +always @(*) begin + init_initialize_re <= 1'd0; + init_initialize_we <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 2'd2))) begin + init_initialize_re <= litesdcardcore_interface5_bank_bus_we; + init_initialize_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign litesdcardcore_csrbank5_dataw_status_r = litesdcardcore_interface5_bank_bus_dat_w[2:0]; +always @(*) begin + litesdcardcore_csrbank5_dataw_status_re <= 1'd0; + litesdcardcore_csrbank5_dataw_status_we <= 1'd0; + if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 2'd3))) begin + litesdcardcore_csrbank5_dataw_status_re <= litesdcardcore_interface5_bank_bus_we; + litesdcardcore_csrbank5_dataw_status_we <= (~litesdcardcore_interface5_bank_bus_we); + end +end +assign litesdcardcore_csrbank5_card_detect_w = card_detect_status0; +assign card_detect_we = litesdcardcore_csrbank5_card_detect_we; +assign litesdcardcore_csrbank5_clocker_divider0_w = clocker_storage[8:0]; +always @(*) begin + dataw_status <= 3'd0; + dataw_status[0] <= dataw_accepted0; + dataw_status[1] <= dataw_crc_error0; + dataw_status[2] <= dataw_write_error0; +end +assign litesdcardcore_csrbank5_dataw_status_w = dataw_status[2:0]; +assign dataw_we = litesdcardcore_csrbank5_dataw_status_we; +assign litesdcardcore_csr_interconnect_adr = litesdcardcore_litesdcardcore_adr; +assign litesdcardcore_csr_interconnect_we = litesdcardcore_litesdcardcore_we; +assign litesdcardcore_csr_interconnect_dat_w = litesdcardcore_litesdcardcore_dat_w; +assign litesdcardcore_litesdcardcore_dat_r = litesdcardcore_csr_interconnect_dat_r; +assign litesdcardcore_interface0_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface1_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface2_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface3_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface4_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface5_bank_bus_adr = litesdcardcore_csr_interconnect_adr; +assign litesdcardcore_interface0_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface1_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface2_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface3_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface4_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface5_bank_bus_we = litesdcardcore_csr_interconnect_we; +assign litesdcardcore_interface0_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface1_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface2_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface3_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface4_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_interface5_bank_bus_dat_w = litesdcardcore_csr_interconnect_dat_w; +assign litesdcardcore_csr_interconnect_dat_r = (((((litesdcardcore_interface0_bank_bus_dat_r | litesdcardcore_interface1_bank_bus_dat_r) | litesdcardcore_interface2_bank_bus_dat_r) | litesdcardcore_interface3_bank_bus_dat_r) | litesdcardcore_interface4_bank_bus_dat_r) | litesdcardcore_interface5_bank_bus_dat_r); +always @(*) begin + array_muxed0 <= 32'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed0 <= interface0_bus_adr; + end + default: begin + array_muxed0 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + array_muxed1 <= 32'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed1 <= interface0_bus_dat_w; + end + default: begin + array_muxed1 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + array_muxed2 <= 4'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed2 <= interface0_bus_sel; + end + default: begin + array_muxed2 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed3 <= interface0_bus_cyc; + end + default: begin + array_muxed3 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed4 <= interface0_bus_stb; + end + default: begin + array_muxed4 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed5 <= interface0_bus_we; + end + default: begin + array_muxed5 <= interface1_bus_we; + end + endcase +end +always @(*) begin + array_muxed6 <= 3'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed6 <= interface0_bus_cti; + end + default: begin + array_muxed6 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + array_muxed7 <= 2'd0; + case (litesdcardcore_grant) + 1'd0: begin + array_muxed7 <= interface0_bus_bte; + end + default: begin + array_muxed7 <= interface1_bus_bte; + end + endcase +end +assign sdrio_clk = sys_clk; +assign sdrio_clk_1 = sys_clk; +assign sdrio_clk_2 = sys_clk; +assign sdrio_clk_3 = sys_clk; +assign sdrio_clk_4 = sys_clk; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge por_clk) begin + int_rst <= rst; +end + +always @(posedge sdrio_clk) begin + inferedsdrtristate0_oe <= sdpads_cmd_oe; + inferedsdrtristate1_oe <= sdpads_data_oe; + inferedsdrtristate2_oe <= sdpads_data_oe; + inferedsdrtristate3_oe <= sdpads_data_oe; + inferedsdrtristate4_oe <= sdpads_data_oe; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + card_detect_d <= card_detect_status0; + card_detect_irq <= (card_detect_status0 ^ card_detect_d); + if ((~clocker_stop)) begin + clocker_clks <= (clocker_clks + 1'd1); + end + clocker_clk_d <= clocker_clk1; + if (clocker_clk_d) begin + clocker_ce_delayed <= clocker_clk_en; + end + subfragments_sdphyinit_state <= subfragments_sdphyinit_next_state; + if (init_count_sdphyinit_next_value_ce) begin + init_count <= init_count_sdphyinit_next_value; + end + subfragments_sdphycmdw_state <= subfragments_sdphycmdw_next_state; + if (cmdw_count_sdphycmdw_next_value_ce) begin + cmdw_count <= cmdw_count_sdphycmdw_next_value; + end + if (cmdr_cmdr_pads_in_valid) begin + cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); + end + if (cmdr_cmdr_converter_source_ready) begin + cmdr_cmdr_converter_strobe_all <= 1'd0; + end + if (cmdr_cmdr_converter_load_part) begin + if (((cmdr_cmdr_converter_demux == 3'd7) | cmdr_cmdr_converter_sink_last)) begin + cmdr_cmdr_converter_demux <= 1'd0; + cmdr_cmdr_converter_strobe_all <= 1'd1; + end else begin + cmdr_cmdr_converter_demux <= (cmdr_cmdr_converter_demux + 1'd1); + end + end + if ((cmdr_cmdr_converter_source_valid & cmdr_cmdr_converter_source_ready)) begin + if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin + cmdr_cmdr_converter_source_first <= cmdr_cmdr_converter_sink_first; + cmdr_cmdr_converter_source_last <= cmdr_cmdr_converter_sink_last; + end else begin + cmdr_cmdr_converter_source_first <= 1'd0; + cmdr_cmdr_converter_source_last <= 1'd0; + end + end else begin + if ((cmdr_cmdr_converter_sink_valid & cmdr_cmdr_converter_sink_ready)) begin + cmdr_cmdr_converter_source_first <= (cmdr_cmdr_converter_sink_first | cmdr_cmdr_converter_source_first); + cmdr_cmdr_converter_source_last <= (cmdr_cmdr_converter_sink_last | cmdr_cmdr_converter_source_last); + end + end + if (cmdr_cmdr_converter_load_part) begin + case (cmdr_cmdr_converter_demux) + 1'd0: begin + cmdr_cmdr_converter_source_payload_data[7] <= cmdr_cmdr_converter_sink_payload_data; + end + 1'd1: begin + cmdr_cmdr_converter_source_payload_data[6] <= cmdr_cmdr_converter_sink_payload_data; + end + 2'd2: begin + cmdr_cmdr_converter_source_payload_data[5] <= cmdr_cmdr_converter_sink_payload_data; + end + 2'd3: begin + cmdr_cmdr_converter_source_payload_data[4] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd4: begin + cmdr_cmdr_converter_source_payload_data[3] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd5: begin + cmdr_cmdr_converter_source_payload_data[2] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd6: begin + cmdr_cmdr_converter_source_payload_data[1] <= cmdr_cmdr_converter_sink_payload_data; + end + 3'd7: begin + cmdr_cmdr_converter_source_payload_data[0] <= cmdr_cmdr_converter_sink_payload_data; + end + endcase + end + if (cmdr_cmdr_converter_load_part) begin + cmdr_cmdr_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_demux + 1'd1); + end + if (((~cmdr_cmdr_buf_source_valid) | cmdr_cmdr_buf_source_ready)) begin + cmdr_cmdr_buf_source_valid <= cmdr_cmdr_buf_sink_valid; + cmdr_cmdr_buf_source_first <= cmdr_cmdr_buf_sink_first; + cmdr_cmdr_buf_source_last <= cmdr_cmdr_buf_sink_last; + cmdr_cmdr_buf_source_payload_data <= cmdr_cmdr_buf_sink_payload_data; + end + if (cmdr_cmdr_reset) begin + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_demux <= 3'd0; + cmdr_cmdr_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_source_valid <= 1'd0; + cmdr_cmdr_buf_source_payload_data <= 8'd0; + end + subfragments_sdphycmdr_state <= subfragments_sdphycmdr_next_state; + if (cmdr_timeout_sdphycmdr_next_value_ce0) begin + cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; + end + if (cmdr_count_sdphycmdr_next_value_ce1) begin + cmdr_count <= cmdr_count_sdphycmdr_next_value1; + end + if (cmdr_busy_sdphycmdr_next_value_ce2) begin + cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; + end + if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin + cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; + end + if (dataw_crc_pads_in_valid) begin + dataw_crc_run <= (dataw_crc_start | dataw_crc_run); + end + if (dataw_crc_converter_source_ready) begin + dataw_crc_converter_strobe_all <= 1'd0; + end + if (dataw_crc_converter_load_part) begin + if (((dataw_crc_converter_demux == 3'd7) | dataw_crc_converter_sink_last)) begin + dataw_crc_converter_demux <= 1'd0; + dataw_crc_converter_strobe_all <= 1'd1; + end else begin + dataw_crc_converter_demux <= (dataw_crc_converter_demux + 1'd1); + end + end + if ((dataw_crc_converter_source_valid & dataw_crc_converter_source_ready)) begin + if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin + dataw_crc_converter_source_first <= dataw_crc_converter_sink_first; + dataw_crc_converter_source_last <= dataw_crc_converter_sink_last; + end else begin + dataw_crc_converter_source_first <= 1'd0; + dataw_crc_converter_source_last <= 1'd0; + end + end else begin + if ((dataw_crc_converter_sink_valid & dataw_crc_converter_sink_ready)) begin + dataw_crc_converter_source_first <= (dataw_crc_converter_sink_first | dataw_crc_converter_source_first); + dataw_crc_converter_source_last <= (dataw_crc_converter_sink_last | dataw_crc_converter_source_last); + end + end + if (dataw_crc_converter_load_part) begin + case (dataw_crc_converter_demux) + 1'd0: begin + dataw_crc_converter_source_payload_data[7] <= dataw_crc_converter_sink_payload_data; + end + 1'd1: begin + dataw_crc_converter_source_payload_data[6] <= dataw_crc_converter_sink_payload_data; + end + 2'd2: begin + dataw_crc_converter_source_payload_data[5] <= dataw_crc_converter_sink_payload_data; + end + 2'd3: begin + dataw_crc_converter_source_payload_data[4] <= dataw_crc_converter_sink_payload_data; + end + 3'd4: begin + dataw_crc_converter_source_payload_data[3] <= dataw_crc_converter_sink_payload_data; + end + 3'd5: begin + dataw_crc_converter_source_payload_data[2] <= dataw_crc_converter_sink_payload_data; + end + 3'd6: begin + dataw_crc_converter_source_payload_data[1] <= dataw_crc_converter_sink_payload_data; + end + 3'd7: begin + dataw_crc_converter_source_payload_data[0] <= dataw_crc_converter_sink_payload_data; + end + endcase + end + if (dataw_crc_converter_load_part) begin + dataw_crc_converter_source_payload_valid_token_count <= (dataw_crc_converter_demux + 1'd1); + end + if (((~dataw_crc_buf_source_valid) | dataw_crc_buf_source_ready)) begin + dataw_crc_buf_source_valid <= dataw_crc_buf_sink_valid; + dataw_crc_buf_source_first <= dataw_crc_buf_sink_first; + dataw_crc_buf_source_last <= dataw_crc_buf_sink_last; + dataw_crc_buf_source_payload_data <= dataw_crc_buf_sink_payload_data; + end + if (dataw_crc_reset) begin + dataw_crc_run <= 1'd0; + dataw_crc_converter_source_payload_data <= 8'd0; + dataw_crc_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_demux <= 3'd0; + dataw_crc_converter_strobe_all <= 1'd0; + dataw_crc_buf_source_valid <= 1'd0; + dataw_crc_buf_source_payload_data <= 8'd0; + end + subfragments_sdphydataw_state <= subfragments_sdphydataw_next_state; + if (dataw_accepted1_sdphydataw_next_value_ce0) begin + dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; + end + if (dataw_crc_error1_sdphydataw_next_value_ce1) begin + dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; + end + if (dataw_write_error1_sdphydataw_next_value_ce2) begin + dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; + end + if (dataw_count_sdphydataw_next_value_ce3) begin + dataw_count <= dataw_count_sdphydataw_next_value3; + end + if (datar_datar_pads_in_valid) begin + datar_datar_run <= (datar_datar_start | datar_datar_run); + end + if (datar_datar_converter_source_ready) begin + datar_datar_converter_strobe_all <= 1'd0; + end + if (datar_datar_converter_load_part) begin + if (((datar_datar_converter_demux == 1'd1) | datar_datar_converter_sink_last)) begin + datar_datar_converter_demux <= 1'd0; + datar_datar_converter_strobe_all <= 1'd1; + end else begin + datar_datar_converter_demux <= (datar_datar_converter_demux + 1'd1); + end + end + if ((datar_datar_converter_source_valid & datar_datar_converter_source_ready)) begin + if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin + datar_datar_converter_source_first <= datar_datar_converter_sink_first; + datar_datar_converter_source_last <= datar_datar_converter_sink_last; + end else begin + datar_datar_converter_source_first <= 1'd0; + datar_datar_converter_source_last <= 1'd0; + end + end else begin + if ((datar_datar_converter_sink_valid & datar_datar_converter_sink_ready)) begin + datar_datar_converter_source_first <= (datar_datar_converter_sink_first | datar_datar_converter_source_first); + datar_datar_converter_source_last <= (datar_datar_converter_sink_last | datar_datar_converter_source_last); + end + end + if (datar_datar_converter_load_part) begin + case (datar_datar_converter_demux) + 1'd0: begin + datar_datar_converter_source_payload_data[7:4] <= datar_datar_converter_sink_payload_data; + end + 1'd1: begin + datar_datar_converter_source_payload_data[3:0] <= datar_datar_converter_sink_payload_data; + end + endcase + end + if (datar_datar_converter_load_part) begin + datar_datar_converter_source_payload_valid_token_count <= (datar_datar_converter_demux + 1'd1); + end + if (((~datar_datar_buf_source_valid) | datar_datar_buf_source_ready)) begin + datar_datar_buf_source_valid <= datar_datar_buf_sink_valid; + datar_datar_buf_source_first <= datar_datar_buf_sink_first; + datar_datar_buf_source_last <= datar_datar_buf_sink_last; + datar_datar_buf_source_payload_data <= datar_datar_buf_sink_payload_data; + end + if (datar_datar_reset) begin + datar_datar_run <= 1'd0; + datar_datar_converter_source_payload_data <= 8'd0; + datar_datar_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_demux <= 1'd0; + datar_datar_converter_strobe_all <= 1'd0; + datar_datar_buf_source_valid <= 1'd0; + datar_datar_buf_source_payload_data <= 8'd0; + end + subfragments_sdphydatar_state <= subfragments_sdphydatar_next_state; + if (datar_count_sdphydatar_next_value_ce0) begin + datar_count <= datar_count_sdphydatar_next_value0; + end + if (datar_timeout_sdphydatar_next_value_ce1) begin + datar_timeout <= datar_timeout_sdphydatar_next_value1; + end + if (datar_datar_reset_sdphydatar_next_value_ce2) begin + datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; + end + clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; + sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + if (sdcore_crc7_inserter_reset) begin + sdcore_crc7_inserter_reg0 <= 1'd0; + end else begin + if (sdcore_crc7_inserter_enable) begin + sdcore_crc7_inserter_reg0 <= sdcore_crc7_inserter_reg40; + end + end + if (sdcore_crc16_inserter_crc0_reset) begin + sdcore_crc16_inserter_crc0_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc0_enable) begin + sdcore_crc16_inserter_crc0_reg0 <= sdcore_crc16_inserter_crc0_reg2; + end + end + if (sdcore_crc16_inserter_crc1_reset) begin + sdcore_crc16_inserter_crc1_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc1_enable) begin + sdcore_crc16_inserter_crc1_reg0 <= sdcore_crc16_inserter_crc1_reg2; + end + end + if (sdcore_crc16_inserter_crc2_reset) begin + sdcore_crc16_inserter_crc2_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc2_enable) begin + sdcore_crc16_inserter_crc2_reg0 <= sdcore_crc16_inserter_crc2_reg2; + end + end + if (sdcore_crc16_inserter_crc3_reset) begin + sdcore_crc16_inserter_crc3_reg0 <= 1'd0; + end else begin + if (sdcore_crc16_inserter_crc3_enable) begin + sdcore_crc16_inserter_crc3_reg0 <= sdcore_crc16_inserter_crc3_reg2; + end + end + subfragments_sdcore_crc16inserter_state <= subfragments_sdcore_crc16inserter_next_state; + if (sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce) begin + sdcore_crc16_inserter_count <= sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value; + end + if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin + sdcore_fifo_produce <= (sdcore_fifo_produce + 1'd1); + end + if (sdcore_fifo_do_read) begin + sdcore_fifo_consume <= (sdcore_fifo_consume + 1'd1); + end + if (((sdcore_fifo_syncfifo_we & sdcore_fifo_syncfifo_writable) & (~sdcore_fifo_replace))) begin + if ((~sdcore_fifo_do_read)) begin + sdcore_fifo_level <= (sdcore_fifo_level + 1'd1); + end + end else begin + if (sdcore_fifo_do_read) begin + sdcore_fifo_level <= (sdcore_fifo_level - 1'd1); + end + end + if (sdcore_fifo_reset) begin + sdcore_fifo_level <= 4'd0; + sdcore_fifo_produce <= 3'd0; + sdcore_fifo_consume <= 3'd0; + end + subfragments_sdcore_fsm_state <= subfragments_sdcore_fsm_next_state; + if (sdcore_cmd_done_sdcore_fsm_next_value_ce0) begin + sdcore_cmd_done <= sdcore_cmd_done_sdcore_fsm_next_value0; + end + if (sdcore_data_done_sdcore_fsm_next_value_ce1) begin + sdcore_data_done <= sdcore_data_done_sdcore_fsm_next_value1; + end + if (sdcore_cmd_count_sdcore_fsm_next_value_ce2) begin + sdcore_cmd_count <= sdcore_cmd_count_sdcore_fsm_next_value2; + end + if (sdcore_data_count_sdcore_fsm_next_value_ce3) begin + sdcore_data_count <= sdcore_data_count_sdcore_fsm_next_value3; + end + if (sdcore_cmd_error_sdcore_fsm_next_value_ce4) begin + sdcore_cmd_error <= sdcore_cmd_error_sdcore_fsm_next_value4; + end + if (sdcore_cmd_timeout_sdcore_fsm_next_value_ce5) begin + sdcore_cmd_timeout <= sdcore_cmd_timeout_sdcore_fsm_next_value5; + end + if (sdcore_data_error_sdcore_fsm_next_value_ce6) begin + sdcore_data_error <= sdcore_data_error_sdcore_fsm_next_value6; + end + if (sdcore_data_timeout_sdcore_fsm_next_value_ce7) begin + sdcore_data_timeout <= sdcore_data_timeout_sdcore_fsm_next_value7; + end + if (sdcore_cmd_response_status_sdcore_fsm_next_value_ce8) begin + sdcore_cmd_response_status <= sdcore_cmd_response_status_sdcore_fsm_next_value8; + end + if ((~sdblock2mem_wishbonedmawriter_enable_storage)) begin + sdblock2mem_connect <= 1'd0; + end else begin + if (sdblock2mem_start) begin + sdblock2mem_connect <= 1'd1; + end + end + sdblock2mem_done_d <= sdblock2mem_wishbonedmawriter_done_status; + sdblock2mem_irq <= (sdblock2mem_wishbonedmawriter_done_status & (~sdblock2mem_done_d)); + if (sdblock2mem_fifo_syncfifo_re) begin + sdblock2mem_fifo_readable <= 1'd1; + end else begin + if (sdblock2mem_fifo_re) begin + sdblock2mem_fifo_readable <= 1'd0; + end + end + if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin + sdblock2mem_fifo_produce <= (sdblock2mem_fifo_produce + 1'd1); + end + if (sdblock2mem_fifo_do_read) begin + sdblock2mem_fifo_consume <= (sdblock2mem_fifo_consume + 1'd1); + end + if (((sdblock2mem_fifo_syncfifo_we & sdblock2mem_fifo_syncfifo_writable) & (~sdblock2mem_fifo_replace))) begin + if ((~sdblock2mem_fifo_do_read)) begin + sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 + 1'd1); + end + end else begin + if (sdblock2mem_fifo_do_read) begin + sdblock2mem_fifo_level0 <= (sdblock2mem_fifo_level0 - 1'd1); + end + end + if (sdblock2mem_converter_source_ready) begin + sdblock2mem_converter_strobe_all <= 1'd0; + end + if (sdblock2mem_converter_load_part) begin + if (((sdblock2mem_converter_demux == 2'd3) | sdblock2mem_converter_sink_last)) begin + sdblock2mem_converter_demux <= 1'd0; + sdblock2mem_converter_strobe_all <= 1'd1; + end else begin + sdblock2mem_converter_demux <= (sdblock2mem_converter_demux + 1'd1); + end + end + if ((sdblock2mem_converter_source_valid & sdblock2mem_converter_source_ready)) begin + if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin + sdblock2mem_converter_source_first <= sdblock2mem_converter_sink_first; + sdblock2mem_converter_source_last <= sdblock2mem_converter_sink_last; + end else begin + sdblock2mem_converter_source_first <= 1'd0; + sdblock2mem_converter_source_last <= 1'd0; + end + end else begin + if ((sdblock2mem_converter_sink_valid & sdblock2mem_converter_sink_ready)) begin + sdblock2mem_converter_source_first <= (sdblock2mem_converter_sink_first | sdblock2mem_converter_source_first); + sdblock2mem_converter_source_last <= (sdblock2mem_converter_sink_last | sdblock2mem_converter_source_last); + end + end + if (sdblock2mem_converter_load_part) begin + case (sdblock2mem_converter_demux) + 1'd0: begin + sdblock2mem_converter_source_payload_data[31:24] <= sdblock2mem_converter_sink_payload_data; + end + 1'd1: begin + sdblock2mem_converter_source_payload_data[23:16] <= sdblock2mem_converter_sink_payload_data; + end + 2'd2: begin + sdblock2mem_converter_source_payload_data[15:8] <= sdblock2mem_converter_sink_payload_data; + end + 2'd3: begin + sdblock2mem_converter_source_payload_data[7:0] <= sdblock2mem_converter_sink_payload_data; + end + endcase + end + if (sdblock2mem_converter_load_part) begin + sdblock2mem_converter_source_payload_valid_token_count <= (sdblock2mem_converter_demux + 1'd1); + end + subfragments_state <= subfragments_next_state; + if (sdblock2mem_wishbonedmawriter_offset_next_value_ce) begin + sdblock2mem_wishbonedmawriter_offset <= sdblock2mem_wishbonedmawriter_offset_next_value; + end + if (sdblock2mem_wishbonedmawriter_reset) begin + sdblock2mem_wishbonedmawriter_offset <= 32'd0; + subfragments_state <= 2'd0; + end + if ((sdmem2block_source_source_valid0 & sdmem2block_source_source_ready0)) begin + sdmem2block_count <= (sdmem2block_count + 1'd1); + if (sdmem2block_source_source_last0) begin + sdmem2block_count <= 1'd0; + end + end + sdmem2block_done_d <= sdmem2block_dma_done_status; + sdmem2block_irq <= (sdmem2block_dma_done_status & (~sdmem2block_done_d)); + subfragments_sdmem2blockdma_fsm_state <= subfragments_sdmem2blockdma_fsm_next_state; + if (sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce) begin + sdmem2block_dma_data <= sdmem2block_dma_data_sdmem2blockdma_fsm_next_value; + end + subfragments_sdmem2blockdma_resetinserter_state <= subfragments_sdmem2blockdma_resetinserter_next_state; + if (sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce) begin + sdmem2block_dma_offset <= sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value; + end + if (sdmem2block_dma_reset) begin + sdmem2block_dma_offset <= 32'd0; + subfragments_sdmem2blockdma_resetinserter_state <= 2'd0; + end + if ((sdmem2block_converter_source_valid & sdmem2block_converter_source_ready)) begin + if (sdmem2block_converter_last) begin + sdmem2block_converter_mux <= 1'd0; + end else begin + sdmem2block_converter_mux <= (sdmem2block_converter_mux + 1'd1); + end + end + if (sdmem2block_fifo_syncfifo_re) begin + sdmem2block_fifo_readable <= 1'd1; + end else begin + if (sdmem2block_fifo_re) begin + sdmem2block_fifo_readable <= 1'd0; + end + end + if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin + sdmem2block_fifo_produce <= (sdmem2block_fifo_produce + 1'd1); + end + if (sdmem2block_fifo_do_read) begin + sdmem2block_fifo_consume <= (sdmem2block_fifo_consume + 1'd1); + end + if (((sdmem2block_fifo_syncfifo_we & sdmem2block_fifo_syncfifo_writable) & (~sdmem2block_fifo_replace))) begin + if ((~sdmem2block_fifo_do_read)) begin + sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 + 1'd1); + end + end else begin + if (sdmem2block_fifo_do_read) begin + sdmem2block_fifo_level0 <= (sdmem2block_fifo_level0 - 1'd1); + end + end + if (card_detect_clear) begin + card_detect_pending <= 1'd0; + end + if (card_detect_trigger) begin + card_detect_pending <= 1'd1; + end + if (block2mem_dma_clear) begin + block2mem_dma_pending <= 1'd0; + end + if (block2mem_dma_trigger) begin + block2mem_dma_pending <= 1'd1; + end + if (mem2block_dma_clear) begin + mem2block_dma_pending <= 1'd0; + end + if (mem2block_dma_trigger) begin + mem2block_dma_pending <= 1'd1; + end + litesdcardcore_state <= litesdcardcore_next_state; + case (litesdcardcore_grant) + 1'd0: begin + if ((~litesdcardcore_request[0])) begin + if (litesdcardcore_request[1]) begin + litesdcardcore_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~litesdcardcore_request[1])) begin + if (litesdcardcore_request[0]) begin + litesdcardcore_grant <= 1'd0; + end + end + end + endcase + litesdcardcore_slave_sel_r <= litesdcardcore_slave_sel; + if (litesdcardcore_wait) begin + if ((~litesdcardcore_done)) begin + litesdcardcore_count <= (litesdcardcore_count - 1'd1); + end + end else begin + litesdcardcore_count <= 20'd1000000; + end + litesdcardcore_interface0_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank0_sel) begin + case (litesdcardcore_interface0_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface0_bank_bus_dat_r <= litesdcardcore_csrbank0_reset0_w; + end + 1'd1: begin + litesdcardcore_interface0_bank_bus_dat_r <= litesdcardcore_csrbank0_scratch0_w; + end + 2'd2: begin + litesdcardcore_interface0_bank_bus_dat_r <= litesdcardcore_csrbank0_bus_errors_w; + end + endcase + end + if (litesdcardcore_csrbank0_reset0_re) begin + reset_storage[1:0] <= litesdcardcore_csrbank0_reset0_r; + end + reset_re <= litesdcardcore_csrbank0_reset0_re; + if (litesdcardcore_csrbank0_scratch0_re) begin + scratch_storage[31:0] <= litesdcardcore_csrbank0_scratch0_r; + end + scratch_re <= litesdcardcore_csrbank0_scratch0_re; + bus_errors_re <= litesdcardcore_csrbank0_bus_errors_re; + litesdcardcore_interface1_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank1_sel) begin + case (litesdcardcore_interface1_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_base1_w; + end + 1'd1: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_base0_w; + end + 2'd2: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_length0_w; + end + 2'd3: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_enable0_w; + end + 3'd4: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_done_w; + end + 3'd5: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_loop0_w; + end + 3'd6: begin + litesdcardcore_interface1_bank_bus_dat_r <= litesdcardcore_csrbank1_dma_offset_w; + end + endcase + end + if (litesdcardcore_csrbank1_dma_base1_re) begin + sdblock2mem_wishbonedmawriter_base_storage[63:32] <= litesdcardcore_csrbank1_dma_base1_r; + end + if (litesdcardcore_csrbank1_dma_base0_re) begin + sdblock2mem_wishbonedmawriter_base_storage[31:0] <= litesdcardcore_csrbank1_dma_base0_r; + end + sdblock2mem_wishbonedmawriter_base_re <= litesdcardcore_csrbank1_dma_base0_re; + if (litesdcardcore_csrbank1_dma_length0_re) begin + sdblock2mem_wishbonedmawriter_length_storage[31:0] <= litesdcardcore_csrbank1_dma_length0_r; + end + sdblock2mem_wishbonedmawriter_length_re <= litesdcardcore_csrbank1_dma_length0_re; + if (litesdcardcore_csrbank1_dma_enable0_re) begin + sdblock2mem_wishbonedmawriter_enable_storage <= litesdcardcore_csrbank1_dma_enable0_r; + end + sdblock2mem_wishbonedmawriter_enable_re <= litesdcardcore_csrbank1_dma_enable0_re; + sdblock2mem_wishbonedmawriter_done_re <= litesdcardcore_csrbank1_dma_done_re; + if (litesdcardcore_csrbank1_dma_loop0_re) begin + sdblock2mem_wishbonedmawriter_loop_storage <= litesdcardcore_csrbank1_dma_loop0_r; + end + sdblock2mem_wishbonedmawriter_loop_re <= litesdcardcore_csrbank1_dma_loop0_re; + sdblock2mem_wishbonedmawriter_offset_re <= litesdcardcore_csrbank1_dma_offset_re; + litesdcardcore_interface2_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank2_sel) begin + case (litesdcardcore_interface2_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_argument0_w; + end + 1'd1: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_command0_w; + end + 2'd2: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_send0_w; + end + 2'd3: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response3_w; + end + 3'd4: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response2_w; + end + 3'd5: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response1_w; + end + 3'd6: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_response0_w; + end + 3'd7: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_cmd_event_w; + end + 4'd8: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_data_event_w; + end + 4'd9: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_block_length0_w; + end + 4'd10: begin + litesdcardcore_interface2_bank_bus_dat_r <= litesdcardcore_csrbank2_block_count0_w; + end + endcase + end + if (litesdcardcore_csrbank2_cmd_argument0_re) begin + sdcore_cmd_argument_storage[31:0] <= litesdcardcore_csrbank2_cmd_argument0_r; + end + sdcore_cmd_argument_re <= litesdcardcore_csrbank2_cmd_argument0_re; + if (litesdcardcore_csrbank2_cmd_command0_re) begin + sdcore_cmd_command_storage[13:0] <= litesdcardcore_csrbank2_cmd_command0_r; + end + sdcore_cmd_command_re <= litesdcardcore_csrbank2_cmd_command0_re; + if (litesdcardcore_csrbank2_cmd_send0_re) begin + sdcore_cmd_send_storage <= litesdcardcore_csrbank2_cmd_send0_r; + end + sdcore_cmd_send_re <= litesdcardcore_csrbank2_cmd_send0_re; + sdcore_cmd_response_re <= litesdcardcore_csrbank2_cmd_response0_re; + sdcore_cmd_event_re <= litesdcardcore_csrbank2_cmd_event_re; + sdcore_data_event_re <= litesdcardcore_csrbank2_data_event_re; + if (litesdcardcore_csrbank2_block_length0_re) begin + sdcore_block_length_storage[9:0] <= litesdcardcore_csrbank2_block_length0_r; + end + sdcore_block_length_re <= litesdcardcore_csrbank2_block_length0_re; + if (litesdcardcore_csrbank2_block_count0_re) begin + sdcore_block_count_storage[31:0] <= litesdcardcore_csrbank2_block_count0_r; + end + sdcore_block_count_re <= litesdcardcore_csrbank2_block_count0_re; + litesdcardcore_interface3_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank3_sel) begin + case (litesdcardcore_interface3_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface3_bank_bus_dat_r <= litesdcardcore_csrbank3_status_w; + end + 1'd1: begin + litesdcardcore_interface3_bank_bus_dat_r <= litesdcardcore_csrbank3_pending_w; + end + 2'd2: begin + litesdcardcore_interface3_bank_bus_dat_r <= litesdcardcore_csrbank3_enable0_w; + end + endcase + end + eventmanager_status_re <= litesdcardcore_csrbank3_status_re; + if (litesdcardcore_csrbank3_pending_re) begin + eventmanager_pending_r[3:0] <= litesdcardcore_csrbank3_pending_r; + end + eventmanager_pending_re <= litesdcardcore_csrbank3_pending_re; + if (litesdcardcore_csrbank3_enable0_re) begin + eventmanager_enable_storage[3:0] <= litesdcardcore_csrbank3_enable0_r; + end + eventmanager_enable_re <= litesdcardcore_csrbank3_enable0_re; + litesdcardcore_interface4_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank4_sel) begin + case (litesdcardcore_interface4_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_base1_w; + end + 1'd1: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_base0_w; + end + 2'd2: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_length0_w; + end + 2'd3: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_enable0_w; + end + 3'd4: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_done_w; + end + 3'd5: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_loop0_w; + end + 3'd6: begin + litesdcardcore_interface4_bank_bus_dat_r <= litesdcardcore_csrbank4_dma_offset_w; + end + endcase + end + if (litesdcardcore_csrbank4_dma_base1_re) begin + sdmem2block_dma_base_storage[63:32] <= litesdcardcore_csrbank4_dma_base1_r; + end + if (litesdcardcore_csrbank4_dma_base0_re) begin + sdmem2block_dma_base_storage[31:0] <= litesdcardcore_csrbank4_dma_base0_r; + end + sdmem2block_dma_base_re <= litesdcardcore_csrbank4_dma_base0_re; + if (litesdcardcore_csrbank4_dma_length0_re) begin + sdmem2block_dma_length_storage[31:0] <= litesdcardcore_csrbank4_dma_length0_r; + end + sdmem2block_dma_length_re <= litesdcardcore_csrbank4_dma_length0_re; + if (litesdcardcore_csrbank4_dma_enable0_re) begin + sdmem2block_dma_enable_storage <= litesdcardcore_csrbank4_dma_enable0_r; + end + sdmem2block_dma_enable_re <= litesdcardcore_csrbank4_dma_enable0_re; + sdmem2block_dma_done_re <= litesdcardcore_csrbank4_dma_done_re; + if (litesdcardcore_csrbank4_dma_loop0_re) begin + sdmem2block_dma_loop_storage <= litesdcardcore_csrbank4_dma_loop0_r; + end + sdmem2block_dma_loop_re <= litesdcardcore_csrbank4_dma_loop0_re; + sdmem2block_dma_offset_re <= litesdcardcore_csrbank4_dma_offset_re; + litesdcardcore_interface5_bank_bus_dat_r <= 1'd0; + if (litesdcardcore_csrbank5_sel) begin + case (litesdcardcore_interface5_bank_bus_adr[8:0]) + 1'd0: begin + litesdcardcore_interface5_bank_bus_dat_r <= litesdcardcore_csrbank5_card_detect_w; + end + 1'd1: begin + litesdcardcore_interface5_bank_bus_dat_r <= litesdcardcore_csrbank5_clocker_divider0_w; + end + 2'd2: begin + litesdcardcore_interface5_bank_bus_dat_r <= init_initialize_w; + end + 2'd3: begin + litesdcardcore_interface5_bank_bus_dat_r <= litesdcardcore_csrbank5_dataw_status_w; + end + endcase + end + card_detect_re <= litesdcardcore_csrbank5_card_detect_re; + if (litesdcardcore_csrbank5_clocker_divider0_re) begin + clocker_storage[8:0] <= litesdcardcore_csrbank5_clocker_divider0_r; + end + clocker_re <= litesdcardcore_csrbank5_clocker_divider0_re; + dataw_re <= litesdcardcore_csrbank5_dataw_status_re; + if (sys_rst) begin + reset_storage <= 2'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + card_detect_re <= 1'd0; + clocker_storage <= 9'd256; + clocker_re <= 1'd0; + clocker_clks <= 9'd0; + clocker_clk_d <= 1'd0; + clocker_ce_delayed <= 1'd0; + init_count <= 8'd0; + cmdw_count <= 8'd0; + cmdr_timeout <= 32'd48; + cmdr_count <= 8'd0; + cmdr_busy <= 1'd0; + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_demux <= 3'd0; + cmdr_cmdr_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_source_valid <= 1'd0; + cmdr_cmdr_buf_source_payload_data <= 8'd0; + cmdr_cmdr_reset <= 1'd0; + dataw_re <= 1'd0; + dataw_count <= 8'd0; + dataw_accepted1 <= 1'd0; + dataw_crc_error1 <= 1'd0; + dataw_write_error1 <= 1'd0; + dataw_crc_run <= 1'd0; + dataw_crc_converter_source_payload_data <= 8'd0; + dataw_crc_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_demux <= 3'd0; + dataw_crc_converter_strobe_all <= 1'd0; + dataw_crc_buf_source_valid <= 1'd0; + dataw_crc_buf_source_payload_data <= 8'd0; + datar_timeout <= 32'd48; + datar_count <= 10'd0; + datar_datar_run <= 1'd0; + datar_datar_converter_source_payload_data <= 8'd0; + datar_datar_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_demux <= 1'd0; + datar_datar_converter_strobe_all <= 1'd0; + datar_datar_buf_source_valid <= 1'd0; + datar_datar_buf_source_payload_data <= 8'd0; + datar_datar_reset <= 1'd0; + sdpads_data_i_ce <= 1'd0; + clocker_clk_delay <= 2'd0; + card_detect_irq <= 1'd0; + card_detect_d <= 1'd0; + sdcore_cmd_argument_storage <= 32'd0; + sdcore_cmd_argument_re <= 1'd0; + sdcore_cmd_command_storage <= 14'd0; + sdcore_cmd_command_re <= 1'd0; + sdcore_cmd_send_storage <= 1'd0; + sdcore_cmd_send_re <= 1'd0; + sdcore_cmd_response_status <= 128'd0; + sdcore_cmd_response_re <= 1'd0; + sdcore_cmd_event_re <= 1'd0; + sdcore_data_event_re <= 1'd0; + sdcore_block_length_storage <= 10'd0; + sdcore_block_length_re <= 1'd0; + sdcore_block_count_storage <= 32'd0; + sdcore_block_count_re <= 1'd0; + sdcore_crc7_inserter_reg0 <= 7'd0; + sdcore_crc16_inserter_count <= 3'd0; + sdcore_crc16_inserter_crc0_reg0 <= 16'd0; + sdcore_crc16_inserter_crc1_reg0 <= 16'd0; + sdcore_crc16_inserter_crc2_reg0 <= 16'd0; + sdcore_crc16_inserter_crc3_reg0 <= 16'd0; + sdcore_fifo_level <= 4'd0; + sdcore_fifo_produce <= 3'd0; + sdcore_fifo_consume <= 3'd0; + sdcore_cmd_count <= 3'd0; + sdcore_cmd_done <= 1'd0; + sdcore_cmd_error <= 1'd0; + sdcore_cmd_timeout <= 1'd0; + sdcore_data_count <= 32'd0; + sdcore_data_done <= 1'd0; + sdcore_data_error <= 1'd0; + sdcore_data_timeout <= 1'd0; + sdblock2mem_irq <= 1'd0; + sdblock2mem_fifo_readable <= 1'd0; + sdblock2mem_fifo_level0 <= 10'd0; + sdblock2mem_fifo_produce <= 9'd0; + sdblock2mem_fifo_consume <= 9'd0; + sdblock2mem_converter_source_payload_data <= 32'd0; + sdblock2mem_converter_source_payload_valid_token_count <= 3'd0; + sdblock2mem_converter_demux <= 2'd0; + sdblock2mem_converter_strobe_all <= 1'd0; + sdblock2mem_wishbonedmawriter_base_storage <= 64'd0; + sdblock2mem_wishbonedmawriter_base_re <= 1'd0; + sdblock2mem_wishbonedmawriter_length_storage <= 32'd0; + sdblock2mem_wishbonedmawriter_length_re <= 1'd0; + sdblock2mem_wishbonedmawriter_enable_storage <= 1'd0; + sdblock2mem_wishbonedmawriter_enable_re <= 1'd0; + sdblock2mem_wishbonedmawriter_done_re <= 1'd0; + sdblock2mem_wishbonedmawriter_loop_storage <= 1'd0; + sdblock2mem_wishbonedmawriter_loop_re <= 1'd0; + sdblock2mem_wishbonedmawriter_offset_re <= 1'd0; + sdblock2mem_wishbonedmawriter_offset <= 32'd0; + sdblock2mem_connect <= 1'd0; + sdblock2mem_done_d <= 1'd0; + sdmem2block_irq <= 1'd0; + sdmem2block_dma_data <= 32'd0; + sdmem2block_dma_base_storage <= 64'd0; + sdmem2block_dma_base_re <= 1'd0; + sdmem2block_dma_length_storage <= 32'd0; + sdmem2block_dma_length_re <= 1'd0; + sdmem2block_dma_enable_storage <= 1'd0; + sdmem2block_dma_enable_re <= 1'd0; + sdmem2block_dma_done_re <= 1'd0; + sdmem2block_dma_loop_storage <= 1'd0; + sdmem2block_dma_loop_re <= 1'd0; + sdmem2block_dma_offset_re <= 1'd0; + sdmem2block_dma_offset <= 32'd0; + sdmem2block_converter_mux <= 2'd0; + sdmem2block_fifo_readable <= 1'd0; + sdmem2block_fifo_level0 <= 10'd0; + sdmem2block_fifo_produce <= 9'd0; + sdmem2block_fifo_consume <= 9'd0; + sdmem2block_count <= 9'd0; + sdmem2block_done_d <= 1'd0; + card_detect_pending <= 1'd0; + block2mem_dma_pending <= 1'd0; + mem2block_dma_pending <= 1'd0; + eventmanager_status_re <= 1'd0; + eventmanager_pending_re <= 1'd0; + eventmanager_pending_r <= 4'd0; + eventmanager_enable_storage <= 4'd0; + eventmanager_enable_re <= 1'd0; + subfragments_sdphyinit_state <= 1'd0; + subfragments_sdphycmdw_state <= 2'd0; + subfragments_sdphycmdr_state <= 3'd0; + subfragments_sdphydataw_state <= 3'd0; + subfragments_sdphydatar_state <= 3'd0; + subfragments_sdcore_crc16inserter_state <= 1'd0; + subfragments_sdcore_fsm_state <= 3'd0; + subfragments_state <= 2'd0; + subfragments_sdmem2blockdma_fsm_state <= 1'd0; + subfragments_sdmem2blockdma_resetinserter_state <= 2'd0; + litesdcardcore_grant <= 1'd0; + litesdcardcore_slave_sel_r <= 1'd0; + litesdcardcore_count <= 20'd1000000; + litesdcardcore_state <= 1'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Async | Write: ---- | +reg [9:0] storage[0:7]; +reg [9:0] storage_dat0; +always @(posedge sys_clk) begin + if (sdcore_fifo_wrport_we) + storage[sdcore_fifo_wrport_adr] <= sdcore_fifo_wrport_dat_w; + storage_dat0 <= storage[sdcore_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcore_fifo_wrport_dat_r = storage_dat0; +assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:511]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (sdblock2mem_fifo_wrport_we) + storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[sdblock2mem_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdblock2mem_fifo_rdport_re) + storage_1_dat1 <= storage_1[sdblock2mem_fifo_rdport_adr]; +end +assign sdblock2mem_fifo_wrport_dat_r = storage_1_dat0; +assign sdblock2mem_fifo_rdport_dat_r = storage_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_2[0:511]; +reg [9:0] storage_2_dat0; +reg [9:0] storage_2_dat1; +always @(posedge sys_clk) begin + if (sdmem2block_fifo_wrport_we) + storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w; + storage_2_dat0 <= storage_2[sdmem2block_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdmem2block_fifo_rdport_re) + storage_2_dat1 <= storage_2[sdmem2block_fifo_rdport_adr]; +end +assign sdmem2block_fifo_wrport_dat_r = storage_2_dat0; +assign sdmem2block_fifo_rdport_dat_r = storage_2_dat1; + + +OFS1P3BX OFS1P3BX( + .D(clocker_clk0), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(sdcard_clk) +); + +assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; +assign inferedsdrtristate0__i = sdcard_cmd; + +assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; +assign inferedsdrtristate1__i = sdcard_data[0]; + +assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; +assign inferedsdrtristate2__i = sdcard_data[1]; + +assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; +assign inferedsdrtristate3__i = sdcard_data[2]; + +assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; +assign inferedsdrtristate4__i = sdcard_data[3]; + +OFS1P3BX OFS1P3BX_1( + .D(sdpads_cmd_o), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(inferedsdrtristate0__o) +); + +IFS1P3BX IFS1P3BX( + .D(inferedsdrtristate0__i), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(sdpads_cmd_i) +); + +OFS1P3BX OFS1P3BX_2( + .D(sdpads_data_o[0]), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(inferedsdrtristate1__o) +); + +IFS1P3BX IFS1P3BX_1( + .D(inferedsdrtristate1__i), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(sdpads_data_i[0]) +); + +OFS1P3BX OFS1P3BX_3( + .D(sdpads_data_o[1]), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(inferedsdrtristate2__o) +); + +IFS1P3BX IFS1P3BX_2( + .D(inferedsdrtristate2__i), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(sdpads_data_i[1]) +); + +OFS1P3BX OFS1P3BX_4( + .D(sdpads_data_o[2]), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(inferedsdrtristate3__o) +); + +IFS1P3BX IFS1P3BX_3( + .D(inferedsdrtristate3__i), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(sdpads_data_i[2]) +); + +OFS1P3BX OFS1P3BX_5( + .D(sdpads_data_o[3]), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(inferedsdrtristate4__o) +); + +IFS1P3BX IFS1P3BX_4( + .D(inferedsdrtristate4__i), + .PD(1'd0), + .SCLK(sys_clk), + .SP(1'd1), + .Q(sdpads_data_i[3]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 07:30:20. +//------------------------------------------------------------------------------ diff --git a/litesdcard/generated/xilinx/litesdcard_core.v b/litesdcard/generated/xilinx/litesdcard_core.v index de99c3e..2b880d2 100644 --- a/litesdcard/generated/xilinx/litesdcard_core.v +++ b/litesdcard/generated/xilinx/litesdcard_core.v @@ -1,53 +1,74 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-10 08:40:47 -//-------------------------------------------------------------------------------- -module litesdcard_core( - input wire clk, - input wire rst, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litesdcard_core.v +// Device : +// LiteX sha1 : -------- +// Date : 2022-01-14 07:30:19 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litesdcard_core ( + input wire clk, + input wire rst, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire [29:0] wb_dma_adr, output wire [31:0] wb_dma_dat_w, - input wire [31:0] wb_dma_dat_r, + input wire [31:0] wb_dma_dat_r, output wire [3:0] wb_dma_sel, output wire wb_dma_cyc, output wire wb_dma_stb, - input wire wb_dma_ack, + input wire wb_dma_ack, output wire wb_dma_we, output wire [2:0] wb_dma_cti, output wire [1:0] wb_dma_bte, - input wire wb_dma_err, - inout wire [3:0] sdcard_data, - inout wire sdcard_cmd, - output reg sdcard_clk, - input wire sdcard_cd, + input wire wb_dma_err, + inout wire [3:0] sdcard_data, + inout wire sdcard_cmd, + output reg sdcard_clk, + input wire sdcard_cd, output wire irq ); + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + wire sys_clk; wire sys_rst; wire por_clk; -reg int_rst = 1'd1; -reg soc_rst = 1'd0; +reg int_rst = 1'd1; +reg soc_rst = 1'd0; wire cpu_rst; -reg [1:0] reset_storage = 2'd0; -reg reset_re = 1'd0; -reg [31:0] scratch_storage = 32'd305419896; -reg scratch_re = 1'd0; +reg [1:0] reset_storage = 2'd0; +reg reset_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg scratch_re = 1'd0; wire [31:0] bus_errors_status; wire bus_errors_we; -reg bus_errors_re = 1'd0; -reg bus_error = 1'd0; -reg [31:0] bus_errors = 32'd0; +reg bus_errors_re = 1'd0; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; wire [29:0] wb_ctrl_adr_1; wire [31:0] wb_ctrl_dat_w_1; wire [31:0] wb_ctrl_dat_r_1; @@ -72,81 +93,81 @@ wire [1:0] wb_dma_bte_1; wire wb_dma_err_1; wire card_detect_status0; wire card_detect_we; -reg card_detect_re = 1'd0; -reg [8:0] clocker_storage = 9'd256; -reg clocker_re = 1'd0; +reg card_detect_re = 1'd0; +reg [8:0] clocker_storage = 9'd256; +reg clocker_re = 1'd0; wire clocker_stop; wire clocker_ce; wire clocker_clk_en; wire clocker_clk0; -reg [8:0] clocker_clks = 9'd0; -reg clocker_clk1 = 1'd0; -reg clocker_clk_d = 1'd0; -reg clocker_ce_delayed = 1'd0; -reg clocker_ce_latched = 1'd0; -reg init_initialize_re = 1'd0; +reg [8:0] clocker_clks = 9'd0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +reg init_initialize_re = 1'd0; wire init_initialize_r; -reg init_initialize_we = 1'd0; -reg init_initialize_w = 1'd0; +reg init_initialize_we = 1'd0; +reg init_initialize_w = 1'd0; wire init_pads_in_valid; wire init_pads_in_payload_cmd_i; wire [3:0] init_pads_in_payload_data_i; wire init_pads_out_ready; -reg init_pads_out_payload_clk = 1'd0; -reg init_pads_out_payload_cmd_o = 1'd0; -reg init_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] init_pads_out_payload_data_o = 4'd0; -reg init_pads_out_payload_data_oe = 1'd0; -reg [7:0] init_count = 8'd0; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +reg [7:0] init_count = 8'd0; wire cmdw_pads_in_valid; wire cmdw_pads_in_payload_cmd_i; wire [3:0] cmdw_pads_in_payload_data_i; wire cmdw_pads_out_ready; -reg cmdw_pads_out_payload_clk = 1'd0; -reg cmdw_pads_out_payload_cmd_o = 1'd0; -reg cmdw_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; -reg cmdw_pads_out_payload_data_oe = 1'd0; -reg cmdw_sink_valid = 1'd0; -reg cmdw_sink_ready = 1'd0; -reg cmdw_sink_last = 1'd0; -reg [7:0] cmdw_sink_payload_data = 8'd0; -reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; -reg cmdw_done = 1'd0; -reg [7:0] cmdw_count = 8'd0; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_last = 1'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg cmdw_done = 1'd0; +reg [7:0] cmdw_count = 8'd0; wire cmdr_pads_in_pads_in_valid; wire cmdr_pads_in_pads_in_ready; -reg cmdr_pads_in_pads_in_first = 1'd0; -reg cmdr_pads_in_pads_in_last = 1'd0; -reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; wire cmdr_pads_in_pads_in_payload_cmd_i; -reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; -reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; wire [3:0] cmdr_pads_in_pads_in_payload_data_i; -reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; -reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; -reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; wire cmdr_pads_out_ready; -reg cmdr_pads_out_payload_clk = 1'd0; -reg cmdr_pads_out_payload_cmd_o = 1'd0; -reg cmdr_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; -reg cmdr_pads_out_payload_data_oe = 1'd0; -reg cmdr_sink_valid = 1'd0; -reg cmdr_sink_ready = 1'd0; -reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; -reg [1:0] cmdr_sink_payload_data_type = 2'd0; -reg [7:0] cmdr_sink_payload_length = 8'd0; -reg cmdr_source_valid = 1'd0; -reg cmdr_source_ready = 1'd0; -reg cmdr_source_last = 1'd0; -reg [7:0] cmdr_source_payload_data = 8'd0; -reg [2:0] cmdr_source_payload_status = 3'd0; -reg [31:0] cmdr_timeout = 32'd100000000; -reg [7:0] cmdr_count = 8'd0; -reg cmdr_busy = 1'd0; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_sink_ready = 1'd0; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_source_valid = 1'd0; +reg cmdr_source_ready = 1'd0; +reg cmdr_source_last = 1'd0; +reg [7:0] cmdr_source_payload_data = 8'd0; +reg [2:0] cmdr_source_payload_status = 3'd0; +reg [31:0] cmdr_timeout = 32'd100; +reg [7:0] cmdr_count = 8'd0; +reg cmdr_busy = 1'd0; wire cmdr_cmdr_pads_in_valid; -reg cmdr_cmdr_pads_in_ready = 1'd0; +reg cmdr_cmdr_pads_in_ready = 1'd0; wire cmdr_cmdr_pads_in_first; wire cmdr_cmdr_pads_in_last; wire cmdr_cmdr_pads_in_payload_clk; @@ -158,26 +179,26 @@ wire [3:0] cmdr_cmdr_pads_in_payload_data_o; wire cmdr_cmdr_pads_in_payload_data_oe; wire cmdr_cmdr_pads_in_payload_data_i_ce; wire cmdr_cmdr_source_source_valid0; -reg cmdr_cmdr_source_source_ready0 = 1'd0; +reg cmdr_cmdr_source_source_ready0 = 1'd0; wire cmdr_cmdr_source_source_first0; wire cmdr_cmdr_source_source_last0; wire [7:0] cmdr_cmdr_source_source_payload_data0; wire cmdr_cmdr_start; -reg cmdr_cmdr_run = 1'd0; +reg cmdr_cmdr_run = 1'd0; wire cmdr_cmdr_converter_sink_valid; wire cmdr_cmdr_converter_sink_ready; -reg cmdr_cmdr_converter_sink_first = 1'd0; -reg cmdr_cmdr_converter_sink_last = 1'd0; +reg cmdr_cmdr_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_sink_last = 1'd0; wire cmdr_cmdr_converter_sink_payload_data; wire cmdr_cmdr_converter_source_valid; wire cmdr_cmdr_converter_source_ready; -reg cmdr_cmdr_converter_source_first = 1'd0; -reg cmdr_cmdr_converter_source_last = 1'd0; -reg [7:0] cmdr_cmdr_converter_source_payload_data = 8'd0; -reg [3:0] cmdr_cmdr_converter_source_payload_valid_token_count = 4'd0; -reg [2:0] cmdr_cmdr_converter_demux = 3'd0; +reg cmdr_cmdr_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_source_payload_valid_token_count = 4'd0; +reg [2:0] cmdr_cmdr_converter_demux = 3'd0; wire cmdr_cmdr_converter_load_part; -reg cmdr_cmdr_converter_strobe_all = 1'd0; +reg cmdr_cmdr_converter_strobe_all = 1'd0; wire cmdr_cmdr_source_source_valid1; wire cmdr_cmdr_source_source_ready1; wire cmdr_cmdr_source_source_first1; @@ -188,46 +209,46 @@ wire cmdr_cmdr_buf_sink_ready; wire cmdr_cmdr_buf_sink_first; wire cmdr_cmdr_buf_sink_last; wire [7:0] cmdr_cmdr_buf_sink_payload_data; -reg cmdr_cmdr_buf_source_valid = 1'd0; +reg cmdr_cmdr_buf_source_valid = 1'd0; wire cmdr_cmdr_buf_source_ready; -reg cmdr_cmdr_buf_source_first = 1'd0; -reg cmdr_cmdr_buf_source_last = 1'd0; -reg [7:0] cmdr_cmdr_buf_source_payload_data = 8'd0; -reg cmdr_cmdr_reset = 1'd0; +reg cmdr_cmdr_buf_source_first = 1'd0; +reg cmdr_cmdr_buf_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_source_payload_data = 8'd0; +reg cmdr_cmdr_reset = 1'd0; wire dataw_pads_in_pads_in_valid; -reg dataw_pads_in_pads_in_ready = 1'd0; -reg dataw_pads_in_pads_in_first = 1'd0; -reg dataw_pads_in_pads_in_last = 1'd0; -reg dataw_pads_in_pads_in_payload_clk = 1'd0; +reg dataw_pads_in_pads_in_ready = 1'd0; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; wire dataw_pads_in_pads_in_payload_cmd_i; -reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; -reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; wire [3:0] dataw_pads_in_pads_in_payload_data_i; -reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; -reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; -reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; wire dataw_pads_out_ready; -reg dataw_pads_out_payload_clk = 1'd0; -reg dataw_pads_out_payload_cmd_o = 1'd0; -reg dataw_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] dataw_pads_out_payload_data_o = 4'd0; -reg dataw_pads_out_payload_data_oe = 1'd0; -reg dataw_sink_valid = 1'd0; -reg dataw_sink_ready = 1'd0; -reg dataw_sink_first = 1'd0; -reg dataw_sink_last = 1'd0; -reg [7:0] dataw_sink_payload_data = 8'd0; -reg dataw_stop = 1'd0; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +reg dataw_sink_valid = 1'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_stop = 1'd0; wire dataw_accepted0; wire dataw_crc_error0; wire dataw_write_error0; -reg [2:0] dataw_status = 3'd0; +reg [2:0] dataw_status = 3'd0; wire dataw_we; -reg dataw_re = 1'd0; -reg [7:0] dataw_count = 8'd0; -reg dataw_accepted1 = 1'd0; -reg dataw_crc_error1 = 1'd0; -reg dataw_write_error1 = 1'd0; +reg dataw_re = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg dataw_accepted1 = 1'd0; +reg dataw_crc_error1 = 1'd0; +reg dataw_write_error1 = 1'd0; wire dataw_crc_pads_in_valid; wire dataw_crc_pads_in_ready; wire dataw_crc_pads_in_first; @@ -241,26 +262,26 @@ wire [3:0] dataw_crc_pads_in_payload_data_o; wire dataw_crc_pads_in_payload_data_oe; wire dataw_crc_pads_in_payload_data_i_ce; wire dataw_crc_source_source_valid0; -reg dataw_crc_source_source_ready0 = 1'd0; +reg dataw_crc_source_source_ready0 = 1'd0; wire dataw_crc_source_source_first0; wire dataw_crc_source_source_last0; wire [7:0] dataw_crc_source_source_payload_data0; wire dataw_crc_start; -reg dataw_crc_run = 1'd0; +reg dataw_crc_run = 1'd0; wire dataw_crc_converter_sink_valid; wire dataw_crc_converter_sink_ready; -reg dataw_crc_converter_sink_first = 1'd0; -reg dataw_crc_converter_sink_last = 1'd0; +reg dataw_crc_converter_sink_first = 1'd0; +reg dataw_crc_converter_sink_last = 1'd0; wire dataw_crc_converter_sink_payload_data; wire dataw_crc_converter_source_valid; wire dataw_crc_converter_source_ready; -reg dataw_crc_converter_source_first = 1'd0; -reg dataw_crc_converter_source_last = 1'd0; -reg [7:0] dataw_crc_converter_source_payload_data = 8'd0; -reg [3:0] dataw_crc_converter_source_payload_valid_token_count = 4'd0; -reg [2:0] dataw_crc_converter_demux = 3'd0; +reg dataw_crc_converter_source_first = 1'd0; +reg dataw_crc_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_source_payload_valid_token_count = 4'd0; +reg [2:0] dataw_crc_converter_demux = 3'd0; wire dataw_crc_converter_load_part; -reg dataw_crc_converter_strobe_all = 1'd0; +reg dataw_crc_converter_strobe_all = 1'd0; wire dataw_crc_source_source_valid1; wire dataw_crc_source_source_ready1; wire dataw_crc_source_source_first1; @@ -271,45 +292,45 @@ wire dataw_crc_buf_sink_ready; wire dataw_crc_buf_sink_first; wire dataw_crc_buf_sink_last; wire [7:0] dataw_crc_buf_sink_payload_data; -reg dataw_crc_buf_source_valid = 1'd0; +reg dataw_crc_buf_source_valid = 1'd0; wire dataw_crc_buf_source_ready; -reg dataw_crc_buf_source_first = 1'd0; -reg dataw_crc_buf_source_last = 1'd0; -reg [7:0] dataw_crc_buf_source_payload_data = 8'd0; -reg dataw_crc_reset = 1'd0; +reg dataw_crc_buf_source_first = 1'd0; +reg dataw_crc_buf_source_last = 1'd0; +reg [7:0] dataw_crc_buf_source_payload_data = 8'd0; +reg dataw_crc_reset = 1'd0; wire datar_pads_in_pads_in_valid; wire datar_pads_in_pads_in_ready; -reg datar_pads_in_pads_in_first = 1'd0; -reg datar_pads_in_pads_in_last = 1'd0; -reg datar_pads_in_pads_in_payload_clk = 1'd0; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; wire datar_pads_in_pads_in_payload_cmd_i; -reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; -reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; wire [3:0] datar_pads_in_pads_in_payload_data_i; -reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; -reg datar_pads_in_pads_in_payload_data_oe = 1'd0; -reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; wire datar_pads_out_ready; -reg datar_pads_out_payload_clk = 1'd0; -reg datar_pads_out_payload_cmd_o = 1'd0; -reg datar_pads_out_payload_cmd_oe = 1'd0; -reg [3:0] datar_pads_out_payload_data_o = 4'd0; -reg datar_pads_out_payload_data_oe = 1'd0; -reg datar_sink_valid = 1'd0; -reg datar_sink_ready = 1'd0; -reg datar_sink_last = 1'd0; -reg [9:0] datar_sink_payload_block_length = 10'd0; -reg datar_source_valid = 1'd0; -reg datar_source_ready = 1'd0; -reg datar_source_first = 1'd0; -reg datar_source_last = 1'd0; -reg [7:0] datar_source_payload_data = 8'd0; -reg [2:0] datar_source_payload_status = 3'd0; -reg datar_stop = 1'd0; -reg [31:0] datar_timeout = 32'd100000000; -reg [9:0] datar_count = 10'd0; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_source_valid = 1'd0; +reg datar_source_ready = 1'd0; +reg datar_source_first = 1'd0; +reg datar_source_last = 1'd0; +reg [7:0] datar_source_payload_data = 8'd0; +reg [2:0] datar_source_payload_status = 3'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd100; +reg [9:0] datar_count = 10'd0; wire datar_datar_pads_in_valid; -reg datar_datar_pads_in_ready = 1'd0; +reg datar_datar_pads_in_ready = 1'd0; wire datar_datar_pads_in_first; wire datar_datar_pads_in_last; wire datar_datar_pads_in_payload_clk; @@ -321,26 +342,26 @@ wire [3:0] datar_datar_pads_in_payload_data_o; wire datar_datar_pads_in_payload_data_oe; wire datar_datar_pads_in_payload_data_i_ce; wire datar_datar_source_source_valid0; -reg datar_datar_source_source_ready0 = 1'd0; +reg datar_datar_source_source_ready0 = 1'd0; wire datar_datar_source_source_first0; wire datar_datar_source_source_last0; wire [7:0] datar_datar_source_source_payload_data0; wire datar_datar_start; -reg datar_datar_run = 1'd0; +reg datar_datar_run = 1'd0; wire datar_datar_converter_sink_valid; wire datar_datar_converter_sink_ready; -reg datar_datar_converter_sink_first = 1'd0; -reg datar_datar_converter_sink_last = 1'd0; +reg datar_datar_converter_sink_first = 1'd0; +reg datar_datar_converter_sink_last = 1'd0; wire [3:0] datar_datar_converter_sink_payload_data; wire datar_datar_converter_source_valid; wire datar_datar_converter_source_ready; -reg datar_datar_converter_source_first = 1'd0; -reg datar_datar_converter_source_last = 1'd0; -reg [7:0] datar_datar_converter_source_payload_data = 8'd0; -reg [1:0] datar_datar_converter_source_payload_valid_token_count = 2'd0; -reg datar_datar_converter_demux = 1'd0; +reg datar_datar_converter_source_first = 1'd0; +reg datar_datar_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_source_payload_valid_token_count = 2'd0; +reg datar_datar_converter_demux = 1'd0; wire datar_datar_converter_load_part; -reg datar_datar_converter_strobe_all = 1'd0; +reg datar_datar_converter_strobe_all = 1'd0; wire datar_datar_source_source_valid1; wire datar_datar_source_source_ready1; wire datar_datar_source_source_first1; @@ -351,23 +372,23 @@ wire datar_datar_buf_sink_ready; wire datar_datar_buf_sink_first; wire datar_datar_buf_sink_last; wire [7:0] datar_datar_buf_sink_payload_data; -reg datar_datar_buf_source_valid = 1'd0; +reg datar_datar_buf_source_valid = 1'd0; wire datar_datar_buf_source_ready; -reg datar_datar_buf_source_first = 1'd0; -reg datar_datar_buf_source_last = 1'd0; -reg [7:0] datar_datar_buf_source_payload_data = 8'd0; -reg datar_datar_reset = 1'd0; +reg datar_datar_buf_source_first = 1'd0; +reg datar_datar_buf_source_last = 1'd0; +reg [7:0] datar_datar_buf_source_payload_data = 8'd0; +reg datar_datar_reset = 1'd0; wire sdpads_clk; -reg sdpads_cmd_i = 1'd0; +reg sdpads_cmd_i = 1'd0; wire sdpads_cmd_o; wire sdpads_cmd_oe; -reg [3:0] sdpads_data_i = 4'd0; +reg [3:0] sdpads_data_i = 4'd0; wire [3:0] sdpads_data_o; wire sdpads_data_oe; -reg sdpads_data_i_ce = 1'd0; -reg [1:0] clocker_clk_delay = 2'd0; -reg card_detect_irq = 1'd0; -reg card_detect_d = 1'd0; +reg sdpads_data_i_ce = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +reg card_detect_irq = 1'd0; +reg card_detect_d = 1'd0; wire sdcore_sink_sink_valid0; wire sdcore_sink_sink_ready0; wire sdcore_sink_sink_first0; @@ -378,41 +399,41 @@ wire sdcore_source_source_ready0; wire sdcore_source_source_first0; wire sdcore_source_source_last0; wire [7:0] sdcore_source_source_payload_data0; -reg [31:0] sdcore_cmd_argument_storage = 32'd0; -reg sdcore_cmd_argument_re = 1'd0; +reg [31:0] sdcore_cmd_argument_storage = 32'd0; +reg sdcore_cmd_argument_re = 1'd0; wire [1:0] sdcore_csrfield_cmd_type; wire [1:0] sdcore_csrfield_data_type; wire [5:0] sdcore_csrfield_cmd; -reg [13:0] sdcore_cmd_command_storage = 14'd0; -reg sdcore_cmd_command_re = 1'd0; -reg sdcore_cmd_send_storage = 1'd0; -reg sdcore_cmd_send_re = 1'd0; -reg [127:0] sdcore_cmd_response_status = 128'd0; +reg [13:0] sdcore_cmd_command_storage = 14'd0; +reg sdcore_cmd_command_re = 1'd0; +reg sdcore_cmd_send_storage = 1'd0; +reg sdcore_cmd_send_re = 1'd0; +reg [127:0] sdcore_cmd_response_status = 128'd0; wire sdcore_cmd_response_we; -reg sdcore_cmd_response_re = 1'd0; +reg sdcore_cmd_response_re = 1'd0; wire sdcore_csrfield_done0; wire sdcore_csrfield_error0; wire sdcore_csrfield_timeout0; wire sdcore_csrfield_crc0; -reg [3:0] sdcore_cmd_event_status = 4'd0; +reg [3:0] sdcore_cmd_event_status = 4'd0; wire sdcore_cmd_event_we; -reg sdcore_cmd_event_re = 1'd0; +reg sdcore_cmd_event_re = 1'd0; wire sdcore_csrfield_done1; wire sdcore_csrfield_error1; wire sdcore_csrfield_timeout1; wire sdcore_csrfield_crc1; -reg [3:0] sdcore_data_event_status = 4'd0; +reg [3:0] sdcore_data_event_status = 4'd0; wire sdcore_data_event_we; -reg sdcore_data_event_re = 1'd0; -reg [9:0] sdcore_block_length_storage = 10'd0; -reg sdcore_block_length_re = 1'd0; -reg [31:0] sdcore_block_count_storage = 32'd0; -reg sdcore_block_count_re = 1'd0; +reg sdcore_data_event_re = 1'd0; +reg [9:0] sdcore_block_length_storage = 10'd0; +reg sdcore_block_length_re = 1'd0; +reg [31:0] sdcore_block_count_storage = 32'd0; +reg sdcore_block_count_re = 1'd0; wire sdcore_crc7_inserter_reset; wire sdcore_crc7_inserter_enable; wire [39:0] sdcore_crc7_inserter_din; -reg [6:0] sdcore_crc7_inserter_crc = 7'd0; -reg [6:0] sdcore_crc7_inserter_reg0 = 7'd0; +reg [6:0] sdcore_crc7_inserter_crc = 7'd0; +reg [6:0] sdcore_crc7_inserter_reg0 = 7'd0; wire [6:0] sdcore_crc7_inserter_reg1; wire [6:0] sdcore_crc7_inserter_reg2; wire [6:0] sdcore_crc7_inserter_reg3; @@ -454,49 +475,49 @@ wire [6:0] sdcore_crc7_inserter_reg38; wire [6:0] sdcore_crc7_inserter_reg39; wire [6:0] sdcore_crc7_inserter_reg40; wire sdcore_crc16_inserter_sink_valid; -reg sdcore_crc16_inserter_sink_ready = 1'd0; +reg sdcore_crc16_inserter_sink_ready = 1'd0; wire sdcore_crc16_inserter_sink_first; wire sdcore_crc16_inserter_sink_last; wire [7:0] sdcore_crc16_inserter_sink_payload_data; -reg sdcore_crc16_inserter_source_valid = 1'd0; -reg sdcore_crc16_inserter_source_ready = 1'd0; -reg sdcore_crc16_inserter_source_first = 1'd0; -reg sdcore_crc16_inserter_source_last = 1'd0; -reg [7:0] sdcore_crc16_inserter_source_payload_data = 8'd0; -reg [2:0] sdcore_crc16_inserter_count = 3'd0; +reg sdcore_crc16_inserter_source_valid = 1'd0; +reg sdcore_crc16_inserter_source_ready = 1'd0; +reg sdcore_crc16_inserter_source_first = 1'd0; +reg sdcore_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcore_crc16_inserter_source_payload_data = 8'd0; +reg [2:0] sdcore_crc16_inserter_count = 3'd0; wire sdcore_crc16_inserter_crc0_reset; wire sdcore_crc16_inserter_crc0_enable; -reg [1:0] sdcore_crc16_inserter_crc0_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc0_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc0_reg0 = 16'd0; +reg [1:0] sdcore_crc16_inserter_crc0_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc0_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc0_reg0 = 16'd0; wire [15:0] sdcore_crc16_inserter_crc0_reg1; wire [15:0] sdcore_crc16_inserter_crc0_reg2; wire sdcore_crc16_inserter_crc1_reset; wire sdcore_crc16_inserter_crc1_enable; -reg [1:0] sdcore_crc16_inserter_crc1_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc1_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc1_reg0 = 16'd0; +reg [1:0] sdcore_crc16_inserter_crc1_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc1_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc1_reg0 = 16'd0; wire [15:0] sdcore_crc16_inserter_crc1_reg1; wire [15:0] sdcore_crc16_inserter_crc1_reg2; wire sdcore_crc16_inserter_crc2_reset; wire sdcore_crc16_inserter_crc2_enable; -reg [1:0] sdcore_crc16_inserter_crc2_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc2_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc2_reg0 = 16'd0; +reg [1:0] sdcore_crc16_inserter_crc2_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc2_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc2_reg0 = 16'd0; wire [15:0] sdcore_crc16_inserter_crc2_reg1; wire [15:0] sdcore_crc16_inserter_crc2_reg2; wire sdcore_crc16_inserter_crc3_reset; wire sdcore_crc16_inserter_crc3_enable; -reg [1:0] sdcore_crc16_inserter_crc3_din = 2'd0; -reg [15:0] sdcore_crc16_inserter_crc3_crc = 16'd0; -reg [15:0] sdcore_crc16_inserter_crc3_reg0 = 16'd0; +reg [1:0] sdcore_crc16_inserter_crc3_din = 2'd0; +reg [15:0] sdcore_crc16_inserter_crc3_crc = 16'd0; +reg [15:0] sdcore_crc16_inserter_crc3_reg0 = 16'd0; wire [15:0] sdcore_crc16_inserter_crc3_reg1; wire [15:0] sdcore_crc16_inserter_crc3_reg2; -reg sdcore_sink_sink_valid1 = 1'd0; +reg sdcore_sink_sink_valid1 = 1'd0; wire sdcore_sink_sink_ready1; -reg sdcore_sink_sink_first1 = 1'd0; -reg sdcore_sink_sink_last1 = 1'd0; -reg [7:0] sdcore_sink_sink_payload_data1 = 8'd0; +reg sdcore_sink_sink_first1 = 1'd0; +reg sdcore_sink_sink_last1 = 1'd0; +reg [7:0] sdcore_sink_sink_payload_data1 = 8'd0; wire sdcore_source_source_valid1; wire sdcore_source_source_ready1; wire sdcore_source_source_first1; @@ -518,11 +539,11 @@ wire sdcore_fifo_syncfifo_re; wire sdcore_fifo_syncfifo_readable; wire [9:0] sdcore_fifo_syncfifo_din; wire [9:0] sdcore_fifo_syncfifo_dout; -reg [3:0] sdcore_fifo_level = 4'd0; -reg sdcore_fifo_replace = 1'd0; -reg [2:0] sdcore_fifo_produce = 3'd0; -reg [2:0] sdcore_fifo_consume = 3'd0; -reg [2:0] sdcore_fifo_wrport_adr = 3'd0; +reg [3:0] sdcore_fifo_level = 4'd0; +reg sdcore_fifo_replace = 1'd0; +reg [2:0] sdcore_fifo_produce = 3'd0; +reg [2:0] sdcore_fifo_consume = 3'd0; +reg [2:0] sdcore_fifo_wrport_adr = 3'd0; wire [9:0] sdcore_fifo_wrport_dat_r; wire sdcore_fifo_wrport_we; wire [9:0] sdcore_fifo_wrport_dat_w; @@ -537,15 +558,15 @@ wire sdcore_fifo_fifo_out_first; wire sdcore_fifo_fifo_out_last; wire sdcore_fifo_reset; wire [1:0] sdcore_cmd_type; -reg [2:0] sdcore_cmd_count = 3'd0; -reg sdcore_cmd_done = 1'd0; -reg sdcore_cmd_error = 1'd0; -reg sdcore_cmd_timeout = 1'd0; +reg [2:0] sdcore_cmd_count = 3'd0; +reg sdcore_cmd_done = 1'd0; +reg sdcore_cmd_error = 1'd0; +reg sdcore_cmd_timeout = 1'd0; wire [1:0] sdcore_data_type; -reg [31:0] sdcore_data_count = 32'd0; -reg sdcore_data_done = 1'd0; -reg sdcore_data_error = 1'd0; -reg sdcore_data_timeout = 1'd0; +reg [31:0] sdcore_data_count = 32'd0; +reg sdcore_data_done = 1'd0; +reg sdcore_data_error = 1'd0; +reg sdcore_data_timeout = 1'd0; wire [5:0] sdcore_cmd; wire [31:0] interface0_bus_adr; wire [31:0] interface0_bus_dat_w; @@ -555,38 +576,38 @@ wire interface0_bus_cyc; wire interface0_bus_stb; wire interface0_bus_ack; wire interface0_bus_we; -reg [2:0] interface0_bus_cti = 3'd0; -reg [1:0] interface0_bus_bte = 2'd0; +reg [2:0] interface0_bus_cti = 3'd0; +reg [1:0] interface0_bus_bte = 2'd0; wire interface0_bus_err; wire sdblock2mem_sink_sink_valid0; -reg sdblock2mem_sink_sink_ready0 = 1'd0; +reg sdblock2mem_sink_sink_ready0 = 1'd0; wire sdblock2mem_sink_sink_first; wire sdblock2mem_sink_sink_last0; wire [7:0] sdblock2mem_sink_sink_payload_data0; -reg sdblock2mem_irq = 1'd0; -reg sdblock2mem_fifo_sink_valid = 1'd0; +reg sdblock2mem_irq = 1'd0; +reg sdblock2mem_fifo_sink_valid = 1'd0; wire sdblock2mem_fifo_sink_ready; -reg sdblock2mem_fifo_sink_first = 1'd0; -reg sdblock2mem_fifo_sink_last = 1'd0; -reg [7:0] sdblock2mem_fifo_sink_payload_data = 8'd0; +reg sdblock2mem_fifo_sink_first = 1'd0; +reg sdblock2mem_fifo_sink_last = 1'd0; +reg [7:0] sdblock2mem_fifo_sink_payload_data = 8'd0; wire sdblock2mem_fifo_source_valid; wire sdblock2mem_fifo_source_ready; wire sdblock2mem_fifo_source_first; wire sdblock2mem_fifo_source_last; wire [7:0] sdblock2mem_fifo_source_payload_data; wire sdblock2mem_fifo_re; -reg sdblock2mem_fifo_readable = 1'd0; +reg sdblock2mem_fifo_readable = 1'd0; wire sdblock2mem_fifo_syncfifo_we; wire sdblock2mem_fifo_syncfifo_writable; wire sdblock2mem_fifo_syncfifo_re; wire sdblock2mem_fifo_syncfifo_readable; wire [9:0] sdblock2mem_fifo_syncfifo_din; wire [9:0] sdblock2mem_fifo_syncfifo_dout; -reg [9:0] sdblock2mem_fifo_level0 = 10'd0; -reg sdblock2mem_fifo_replace = 1'd0; -reg [8:0] sdblock2mem_fifo_produce = 9'd0; -reg [8:0] sdblock2mem_fifo_consume = 9'd0; -reg [8:0] sdblock2mem_fifo_wrport_adr = 9'd0; +reg [9:0] sdblock2mem_fifo_level0 = 10'd0; +reg sdblock2mem_fifo_replace = 1'd0; +reg [8:0] sdblock2mem_fifo_produce = 9'd0; +reg [8:0] sdblock2mem_fifo_consume = 9'd0; +reg [8:0] sdblock2mem_fifo_wrport_adr = 9'd0; wire [9:0] sdblock2mem_fifo_wrport_dat_r; wire sdblock2mem_fifo_wrport_we; wire [9:0] sdblock2mem_fifo_wrport_dat_w; @@ -608,92 +629,92 @@ wire sdblock2mem_converter_sink_last; wire [7:0] sdblock2mem_converter_sink_payload_data; wire sdblock2mem_converter_source_valid; wire sdblock2mem_converter_source_ready; -reg sdblock2mem_converter_source_first = 1'd0; -reg sdblock2mem_converter_source_last = 1'd0; -reg [31:0] sdblock2mem_converter_source_payload_data = 32'd0; -reg [2:0] sdblock2mem_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] sdblock2mem_converter_demux = 2'd0; +reg sdblock2mem_converter_source_first = 1'd0; +reg sdblock2mem_converter_source_last = 1'd0; +reg [31:0] sdblock2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdblock2mem_converter_source_payload_valid_token_count = 3'd0; +reg [1:0] sdblock2mem_converter_demux = 2'd0; wire sdblock2mem_converter_load_part; -reg sdblock2mem_converter_strobe_all = 1'd0; +reg sdblock2mem_converter_strobe_all = 1'd0; wire sdblock2mem_source_source_valid; wire sdblock2mem_source_source_ready; wire sdblock2mem_source_source_first; wire sdblock2mem_source_source_last; wire [31:0] sdblock2mem_source_source_payload_data; -reg sdblock2mem_sink_sink_valid1 = 1'd0; +reg sdblock2mem_sink_sink_valid1 = 1'd0; wire sdblock2mem_sink_sink_ready1; -reg sdblock2mem_sink_sink_last1 = 1'd0; -reg [31:0] sdblock2mem_sink_sink_payload_address = 32'd0; -reg [31:0] sdblock2mem_sink_sink_payload_data1 = 32'd0; +reg sdblock2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdblock2mem_sink_sink_payload_address = 32'd0; +reg [31:0] sdblock2mem_sink_sink_payload_data1 = 32'd0; wire sdblock2mem_wishbonedmawriter_sink_valid; -reg sdblock2mem_wishbonedmawriter_sink_ready = 1'd0; +reg sdblock2mem_wishbonedmawriter_sink_ready = 1'd0; wire sdblock2mem_wishbonedmawriter_sink_first; wire sdblock2mem_wishbonedmawriter_sink_last; wire [31:0] sdblock2mem_wishbonedmawriter_sink_payload_data; -reg [63:0] sdblock2mem_wishbonedmawriter_base_storage = 64'd0; -reg sdblock2mem_wishbonedmawriter_base_re = 1'd0; -reg [31:0] sdblock2mem_wishbonedmawriter_length_storage = 32'd0; -reg sdblock2mem_wishbonedmawriter_length_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_enable_storage = 1'd0; -reg sdblock2mem_wishbonedmawriter_enable_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_done_status = 1'd0; +reg [63:0] sdblock2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdblock2mem_wishbonedmawriter_base_re = 1'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdblock2mem_wishbonedmawriter_length_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_enable_storage = 1'd0; +reg sdblock2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_done_status = 1'd0; wire sdblock2mem_wishbonedmawriter_done_we; -reg sdblock2mem_wishbonedmawriter_done_re = 1'd0; -reg sdblock2mem_wishbonedmawriter_loop_storage = 1'd0; -reg sdblock2mem_wishbonedmawriter_loop_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_done_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_loop_storage = 1'd0; +reg sdblock2mem_wishbonedmawriter_loop_re = 1'd0; wire [31:0] sdblock2mem_wishbonedmawriter_offset_status; wire sdblock2mem_wishbonedmawriter_offset_we; -reg sdblock2mem_wishbonedmawriter_offset_re = 1'd0; +reg sdblock2mem_wishbonedmawriter_offset_re = 1'd0; wire [31:0] sdblock2mem_wishbonedmawriter_base; -reg [31:0] sdblock2mem_wishbonedmawriter_offset = 32'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_offset = 32'd0; wire [31:0] sdblock2mem_wishbonedmawriter_length; wire sdblock2mem_wishbonedmawriter_reset; wire sdblock2mem_start; -reg sdblock2mem_connect = 1'd0; -reg sdblock2mem_done_d = 1'd0; -reg [31:0] interface1_bus_adr = 32'd0; -reg [31:0] interface1_bus_dat_w = 32'd0; +reg sdblock2mem_connect = 1'd0; +reg sdblock2mem_done_d = 1'd0; +reg [31:0] interface1_bus_adr = 32'd0; +reg [31:0] interface1_bus_dat_w = 32'd0; wire [31:0] interface1_bus_dat_r; -reg [3:0] interface1_bus_sel = 4'd0; -reg interface1_bus_cyc = 1'd0; -reg interface1_bus_stb = 1'd0; +reg [3:0] interface1_bus_sel = 4'd0; +reg interface1_bus_cyc = 1'd0; +reg interface1_bus_stb = 1'd0; wire interface1_bus_ack; -reg interface1_bus_we = 1'd0; -reg [2:0] interface1_bus_cti = 3'd0; -reg [1:0] interface1_bus_bte = 2'd0; +reg interface1_bus_we = 1'd0; +reg [2:0] interface1_bus_cti = 3'd0; +reg [1:0] interface1_bus_bte = 2'd0; wire interface1_bus_err; wire sdmem2block_source_source_valid0; wire sdmem2block_source_source_ready0; wire sdmem2block_source_source_first0; -reg sdmem2block_source_source_last0 = 1'd0; +reg sdmem2block_source_source_last0 = 1'd0; wire [7:0] sdmem2block_source_source_payload_data0; -reg sdmem2block_irq = 1'd0; -reg sdmem2block_dma_sink_valid = 1'd0; -reg sdmem2block_dma_sink_ready = 1'd0; -reg sdmem2block_dma_sink_last = 1'd0; -reg [31:0] sdmem2block_dma_sink_payload_address = 32'd0; -reg sdmem2block_dma_source_valid = 1'd0; +reg sdmem2block_irq = 1'd0; +reg sdmem2block_dma_sink_valid = 1'd0; +reg sdmem2block_dma_sink_ready = 1'd0; +reg sdmem2block_dma_sink_last = 1'd0; +reg [31:0] sdmem2block_dma_sink_payload_address = 32'd0; +reg sdmem2block_dma_source_valid = 1'd0; wire sdmem2block_dma_source_ready; -reg sdmem2block_dma_source_first = 1'd0; -reg sdmem2block_dma_source_last = 1'd0; -reg [31:0] sdmem2block_dma_source_payload_data = 32'd0; -reg [31:0] sdmem2block_dma_data = 32'd0; -reg [63:0] sdmem2block_dma_base_storage = 64'd0; -reg sdmem2block_dma_base_re = 1'd0; -reg [31:0] sdmem2block_dma_length_storage = 32'd0; -reg sdmem2block_dma_length_re = 1'd0; -reg sdmem2block_dma_enable_storage = 1'd0; -reg sdmem2block_dma_enable_re = 1'd0; -reg sdmem2block_dma_done_status = 1'd0; +reg sdmem2block_dma_source_first = 1'd0; +reg sdmem2block_dma_source_last = 1'd0; +reg [31:0] sdmem2block_dma_source_payload_data = 32'd0; +reg [31:0] sdmem2block_dma_data = 32'd0; +reg [63:0] sdmem2block_dma_base_storage = 64'd0; +reg sdmem2block_dma_base_re = 1'd0; +reg [31:0] sdmem2block_dma_length_storage = 32'd0; +reg sdmem2block_dma_length_re = 1'd0; +reg sdmem2block_dma_enable_storage = 1'd0; +reg sdmem2block_dma_enable_re = 1'd0; +reg sdmem2block_dma_done_status = 1'd0; wire sdmem2block_dma_done_we; -reg sdmem2block_dma_done_re = 1'd0; -reg sdmem2block_dma_loop_storage = 1'd0; -reg sdmem2block_dma_loop_re = 1'd0; +reg sdmem2block_dma_done_re = 1'd0; +reg sdmem2block_dma_loop_storage = 1'd0; +reg sdmem2block_dma_loop_re = 1'd0; wire [31:0] sdmem2block_dma_offset_status; wire sdmem2block_dma_offset_we; -reg sdmem2block_dma_offset_re = 1'd0; +reg sdmem2block_dma_offset_re = 1'd0; wire [31:0] sdmem2block_dma_base; -reg [31:0] sdmem2block_dma_offset = 32'd0; +reg [31:0] sdmem2block_dma_offset = 32'd0; wire [31:0] sdmem2block_dma_length; wire sdmem2block_dma_reset; wire sdmem2block_converter_sink_valid; @@ -705,9 +726,9 @@ wire sdmem2block_converter_source_valid; wire sdmem2block_converter_source_ready; wire sdmem2block_converter_source_first; wire sdmem2block_converter_source_last; -reg [7:0] sdmem2block_converter_source_payload_data = 8'd0; +reg [7:0] sdmem2block_converter_source_payload_data = 8'd0; wire sdmem2block_converter_source_payload_valid_token_count; -reg [1:0] sdmem2block_converter_mux = 2'd0; +reg [1:0] sdmem2block_converter_mux = 2'd0; wire sdmem2block_converter_first; wire sdmem2block_converter_last; wire sdmem2block_source_source_valid1; @@ -726,18 +747,18 @@ wire sdmem2block_fifo_source_first; wire sdmem2block_fifo_source_last; wire [7:0] sdmem2block_fifo_source_payload_data; wire sdmem2block_fifo_re; -reg sdmem2block_fifo_readable = 1'd0; +reg sdmem2block_fifo_readable = 1'd0; wire sdmem2block_fifo_syncfifo_we; wire sdmem2block_fifo_syncfifo_writable; wire sdmem2block_fifo_syncfifo_re; wire sdmem2block_fifo_syncfifo_readable; wire [9:0] sdmem2block_fifo_syncfifo_din; wire [9:0] sdmem2block_fifo_syncfifo_dout; -reg [9:0] sdmem2block_fifo_level0 = 10'd0; -reg sdmem2block_fifo_replace = 1'd0; -reg [8:0] sdmem2block_fifo_produce = 9'd0; -reg [8:0] sdmem2block_fifo_consume = 9'd0; -reg [8:0] sdmem2block_fifo_wrport_adr = 9'd0; +reg [9:0] sdmem2block_fifo_level0 = 10'd0; +reg sdmem2block_fifo_replace = 1'd0; +reg [8:0] sdmem2block_fifo_produce = 9'd0; +reg [8:0] sdmem2block_fifo_consume = 9'd0; +reg [8:0] sdmem2block_fifo_wrport_adr = 9'd0; wire [9:0] sdmem2block_fifo_wrport_dat_r; wire sdmem2block_fifo_wrport_we; wire [9:0] sdmem2block_fifo_wrport_dat_w; @@ -752,347 +773,347 @@ wire sdmem2block_fifo_fifo_in_last; wire [7:0] sdmem2block_fifo_fifo_out_payload_data; wire sdmem2block_fifo_fifo_out_first; wire sdmem2block_fifo_fifo_out_last; -reg [8:0] sdmem2block_count = 9'd0; -reg sdmem2block_done_d = 1'd0; +reg [8:0] sdmem2block_count = 9'd0; +reg sdmem2block_done_d = 1'd0; wire sdirq_irq; wire card_detect_status1; -reg card_detect_pending = 1'd0; +reg card_detect_pending = 1'd0; wire card_detect_trigger; -reg card_detect_clear = 1'd0; +reg card_detect_clear = 1'd0; wire block2mem_dma_status; -reg block2mem_dma_pending = 1'd0; +reg block2mem_dma_pending = 1'd0; wire block2mem_dma_trigger; -reg block2mem_dma_clear = 1'd0; +reg block2mem_dma_clear = 1'd0; wire mem2block_dma_status; -reg mem2block_dma_pending = 1'd0; +reg mem2block_dma_pending = 1'd0; wire mem2block_dma_trigger; -reg mem2block_dma_clear = 1'd0; +reg mem2block_dma_clear = 1'd0; wire cmd_done_status; wire cmd_done_pending; wire cmd_done_trigger; -reg cmd_done_clear = 1'd0; +reg cmd_done_clear = 1'd0; wire eventmanager_card_detect0; wire eventmanager_block2mem_dma0; wire eventmanager_mem2block_dma0; wire eventmanager_cmd_done0; -reg [3:0] eventmanager_status_status = 4'd0; +reg [3:0] eventmanager_status_status = 4'd0; wire eventmanager_status_we; -reg eventmanager_status_re = 1'd0; +reg eventmanager_status_re = 1'd0; wire eventmanager_card_detect1; wire eventmanager_block2mem_dma1; wire eventmanager_mem2block_dma1; wire eventmanager_cmd_done1; -reg [3:0] eventmanager_pending_status = 4'd0; +reg [3:0] eventmanager_pending_status = 4'd0; wire eventmanager_pending_we; -reg eventmanager_pending_re = 1'd0; -reg [3:0] eventmanager_pending_r = 4'd0; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_r = 4'd0; wire eventmanager_card_detect2; wire eventmanager_block2mem_dma2; wire eventmanager_mem2block_dma2; wire eventmanager_cmd_done2; -reg [3:0] eventmanager_enable_storage = 4'd0; -reg eventmanager_enable_re = 1'd0; -reg subfragments_sdphyinit_state = 1'd0; -reg subfragments_sdphyinit_next_state = 1'd0; -reg [7:0] init_count_sdphyinit_next_value = 8'd0; -reg init_count_sdphyinit_next_value_ce = 1'd0; -reg [1:0] subfragments_sdphycmdw_state = 2'd0; -reg [1:0] subfragments_sdphycmdw_next_state = 2'd0; -reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; -reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; -reg [2:0] subfragments_sdphycmdr_state = 3'd0; -reg [2:0] subfragments_sdphycmdr_next_state = 3'd0; -reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; -reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; -reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; -reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; -reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; -reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; -reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; -reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; -reg [2:0] subfragments_sdphydataw_state = 3'd0; -reg [2:0] subfragments_sdphydataw_next_state = 3'd0; -reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; -reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; -reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; -reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; -reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; -reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; -reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; -reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; -reg [2:0] subfragments_sdphydatar_state = 3'd0; -reg [2:0] subfragments_sdphydatar_next_state = 3'd0; -reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; -reg datar_count_sdphydatar_next_value_ce0 = 1'd0; -reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; -reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; -reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; -reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; -reg subfragments_sdcore_crc16inserter_state = 1'd0; -reg subfragments_sdcore_crc16inserter_next_state = 1'd0; -reg [2:0] sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value = 3'd0; -reg sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce = 1'd0; -reg [2:0] subfragments_sdcore_fsm_state = 3'd0; -reg [2:0] subfragments_sdcore_fsm_next_state = 3'd0; -reg sdcore_cmd_done_sdcore_fsm_next_value0 = 1'd0; -reg sdcore_cmd_done_sdcore_fsm_next_value_ce0 = 1'd0; -reg sdcore_data_done_sdcore_fsm_next_value1 = 1'd0; -reg sdcore_data_done_sdcore_fsm_next_value_ce1 = 1'd0; -reg [2:0] sdcore_cmd_count_sdcore_fsm_next_value2 = 3'd0; -reg sdcore_cmd_count_sdcore_fsm_next_value_ce2 = 1'd0; -reg [31:0] sdcore_data_count_sdcore_fsm_next_value3 = 32'd0; -reg sdcore_data_count_sdcore_fsm_next_value_ce3 = 1'd0; -reg sdcore_cmd_error_sdcore_fsm_next_value4 = 1'd0; -reg sdcore_cmd_error_sdcore_fsm_next_value_ce4 = 1'd0; -reg sdcore_cmd_timeout_sdcore_fsm_next_value5 = 1'd0; -reg sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 = 1'd0; -reg sdcore_data_error_sdcore_fsm_next_value6 = 1'd0; -reg sdcore_data_error_sdcore_fsm_next_value_ce6 = 1'd0; -reg sdcore_data_timeout_sdcore_fsm_next_value7 = 1'd0; -reg sdcore_data_timeout_sdcore_fsm_next_value_ce7 = 1'd0; -reg [127:0] sdcore_cmd_response_status_sdcore_fsm_next_value8 = 128'd0; -reg sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 = 1'd0; -reg [1:0] subfragments_state = 2'd0; -reg [1:0] subfragments_next_state = 2'd0; -reg [31:0] sdblock2mem_wishbonedmawriter_offset_next_value = 32'd0; -reg sdblock2mem_wishbonedmawriter_offset_next_value_ce = 1'd0; -reg subfragments_sdmem2blockdma_fsm_state = 1'd0; -reg subfragments_sdmem2blockdma_fsm_next_state = 1'd0; -reg [31:0] sdmem2block_dma_data_sdmem2blockdma_fsm_next_value = 32'd0; -reg sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce = 1'd0; -reg [1:0] subfragments_sdmem2blockdma_resetinserter_state = 2'd0; -reg [1:0] subfragments_sdmem2blockdma_resetinserter_next_state = 2'd0; -reg [31:0] sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value = 32'd0; -reg sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce = 1'd0; -reg [13:0] litesdcardcore_litesdcardcore_adr = 14'd0; -reg litesdcardcore_litesdcardcore_we = 1'd0; -reg [31:0] litesdcardcore_litesdcardcore_dat_w = 32'd0; +reg [3:0] eventmanager_enable_storage = 4'd0; +reg eventmanager_enable_re = 1'd0; +reg subfragments_sdphyinit_state = 1'd0; +reg subfragments_sdphyinit_next_state = 1'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +reg [1:0] subfragments_sdphycmdw_state = 2'd0; +reg [1:0] subfragments_sdphycmdw_next_state = 2'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg [2:0] subfragments_sdphycmdr_state = 3'd0; +reg [2:0] subfragments_sdphycmdr_next_state = 3'd0; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg [2:0] subfragments_sdphydataw_state = 3'd0; +reg [2:0] subfragments_sdphydataw_next_state = 3'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +reg [2:0] subfragments_sdphydatar_state = 3'd0; +reg [2:0] subfragments_sdphydatar_next_state = 3'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg subfragments_sdcore_crc16inserter_state = 1'd0; +reg subfragments_sdcore_crc16inserter_next_state = 1'd0; +reg [2:0] sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value = 3'd0; +reg sdcore_crc16_inserter_count_sdcore_crc16inserter_next_value_ce = 1'd0; +reg [2:0] subfragments_sdcore_fsm_state = 3'd0; +reg [2:0] subfragments_sdcore_fsm_next_state = 3'd0; +reg sdcore_cmd_done_sdcore_fsm_next_value0 = 1'd0; +reg sdcore_cmd_done_sdcore_fsm_next_value_ce0 = 1'd0; +reg sdcore_data_done_sdcore_fsm_next_value1 = 1'd0; +reg sdcore_data_done_sdcore_fsm_next_value_ce1 = 1'd0; +reg [2:0] sdcore_cmd_count_sdcore_fsm_next_value2 = 3'd0; +reg sdcore_cmd_count_sdcore_fsm_next_value_ce2 = 1'd0; +reg [31:0] sdcore_data_count_sdcore_fsm_next_value3 = 32'd0; +reg sdcore_data_count_sdcore_fsm_next_value_ce3 = 1'd0; +reg sdcore_cmd_error_sdcore_fsm_next_value4 = 1'd0; +reg sdcore_cmd_error_sdcore_fsm_next_value_ce4 = 1'd0; +reg sdcore_cmd_timeout_sdcore_fsm_next_value5 = 1'd0; +reg sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 = 1'd0; +reg sdcore_data_error_sdcore_fsm_next_value6 = 1'd0; +reg sdcore_data_error_sdcore_fsm_next_value_ce6 = 1'd0; +reg sdcore_data_timeout_sdcore_fsm_next_value7 = 1'd0; +reg sdcore_data_timeout_sdcore_fsm_next_value_ce7 = 1'd0; +reg [127:0] sdcore_cmd_response_status_sdcore_fsm_next_value8 = 128'd0; +reg sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 = 1'd0; +reg [1:0] subfragments_state = 2'd0; +reg [1:0] subfragments_next_state = 2'd0; +reg [31:0] sdblock2mem_wishbonedmawriter_offset_next_value = 32'd0; +reg sdblock2mem_wishbonedmawriter_offset_next_value_ce = 1'd0; +reg subfragments_sdmem2blockdma_fsm_state = 1'd0; +reg subfragments_sdmem2blockdma_fsm_next_state = 1'd0; +reg [31:0] sdmem2block_dma_data_sdmem2blockdma_fsm_next_value = 32'd0; +reg sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce = 1'd0; +reg [1:0] subfragments_sdmem2blockdma_resetinserter_state = 2'd0; +reg [1:0] subfragments_sdmem2blockdma_resetinserter_next_state = 2'd0; +reg [31:0] sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value = 32'd0; +reg sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce = 1'd0; +reg [13:0] litesdcardcore_litesdcardcore_adr = 14'd0; +reg litesdcardcore_litesdcardcore_we = 1'd0; +reg [31:0] litesdcardcore_litesdcardcore_dat_w = 32'd0; wire [31:0] litesdcardcore_litesdcardcore_dat_r; wire [29:0] litesdcardcore_litesdcardcore_wishbone_adr; wire [31:0] litesdcardcore_litesdcardcore_wishbone_dat_w; -reg [31:0] litesdcardcore_litesdcardcore_wishbone_dat_r = 32'd0; +reg [31:0] litesdcardcore_litesdcardcore_wishbone_dat_r = 32'd0; wire [3:0] litesdcardcore_litesdcardcore_wishbone_sel; wire litesdcardcore_litesdcardcore_wishbone_cyc; wire litesdcardcore_litesdcardcore_wishbone_stb; -reg litesdcardcore_litesdcardcore_wishbone_ack = 1'd0; +reg litesdcardcore_litesdcardcore_wishbone_ack = 1'd0; wire litesdcardcore_litesdcardcore_wishbone_we; wire [2:0] litesdcardcore_litesdcardcore_wishbone_cti; wire [1:0] litesdcardcore_litesdcardcore_wishbone_bte; -reg litesdcardcore_litesdcardcore_wishbone_err = 1'd0; +reg litesdcardcore_litesdcardcore_wishbone_err = 1'd0; wire [29:0] litesdcardcore_shared_adr; wire [31:0] litesdcardcore_shared_dat_w; -reg [31:0] litesdcardcore_shared_dat_r = 32'd0; +reg [31:0] litesdcardcore_shared_dat_r = 32'd0; wire [3:0] litesdcardcore_shared_sel; wire litesdcardcore_shared_cyc; wire litesdcardcore_shared_stb; -reg litesdcardcore_shared_ack = 1'd0; +reg litesdcardcore_shared_ack = 1'd0; wire litesdcardcore_shared_we; wire [2:0] litesdcardcore_shared_cti; wire [1:0] litesdcardcore_shared_bte; wire litesdcardcore_shared_err; wire [1:0] litesdcardcore_request; -reg litesdcardcore_grant = 1'd0; +reg litesdcardcore_grant = 1'd0; wire litesdcardcore_slave_sel; -reg litesdcardcore_slave_sel_r = 1'd0; -reg litesdcardcore_error = 1'd0; +reg litesdcardcore_slave_sel_r = 1'd0; +reg litesdcardcore_error = 1'd0; wire litesdcardcore_wait; wire litesdcardcore_done; -reg [19:0] litesdcardcore_count = 20'd1000000; +reg [19:0] litesdcardcore_count = 20'd1000000; wire [13:0] litesdcardcore_interface0_bank_bus_adr; wire litesdcardcore_interface0_bank_bus_we; wire [31:0] litesdcardcore_interface0_bank_bus_dat_w; -reg [31:0] litesdcardcore_interface0_bank_bus_dat_r = 32'd0; -reg litesdcardcore_csrbank0_reset0_re = 1'd0; +reg [31:0] litesdcardcore_interface0_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank0_reset0_re = 1'd0; wire [1:0] litesdcardcore_csrbank0_reset0_r; -reg litesdcardcore_csrbank0_reset0_we = 1'd0; +reg litesdcardcore_csrbank0_reset0_we = 1'd0; wire [1:0] litesdcardcore_csrbank0_reset0_w; -reg litesdcardcore_csrbank0_scratch0_re = 1'd0; +reg litesdcardcore_csrbank0_scratch0_re = 1'd0; wire [31:0] litesdcardcore_csrbank0_scratch0_r; -reg litesdcardcore_csrbank0_scratch0_we = 1'd0; +reg litesdcardcore_csrbank0_scratch0_we = 1'd0; wire [31:0] litesdcardcore_csrbank0_scratch0_w; -reg litesdcardcore_csrbank0_bus_errors_re = 1'd0; +reg litesdcardcore_csrbank0_bus_errors_re = 1'd0; wire [31:0] litesdcardcore_csrbank0_bus_errors_r; -reg litesdcardcore_csrbank0_bus_errors_we = 1'd0; +reg litesdcardcore_csrbank0_bus_errors_we = 1'd0; wire [31:0] litesdcardcore_csrbank0_bus_errors_w; wire litesdcardcore_csrbank0_sel; wire [13:0] litesdcardcore_interface1_bank_bus_adr; wire litesdcardcore_interface1_bank_bus_we; wire [31:0] litesdcardcore_interface1_bank_bus_dat_w; -reg [31:0] litesdcardcore_interface1_bank_bus_dat_r = 32'd0; -reg litesdcardcore_csrbank1_dma_base1_re = 1'd0; +reg [31:0] litesdcardcore_interface1_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank1_dma_base1_re = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_base1_r; -reg litesdcardcore_csrbank1_dma_base1_we = 1'd0; +reg litesdcardcore_csrbank1_dma_base1_we = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_base1_w; -reg litesdcardcore_csrbank1_dma_base0_re = 1'd0; +reg litesdcardcore_csrbank1_dma_base0_re = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_base0_r; -reg litesdcardcore_csrbank1_dma_base0_we = 1'd0; +reg litesdcardcore_csrbank1_dma_base0_we = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_base0_w; -reg litesdcardcore_csrbank1_dma_length0_re = 1'd0; +reg litesdcardcore_csrbank1_dma_length0_re = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_length0_r; -reg litesdcardcore_csrbank1_dma_length0_we = 1'd0; +reg litesdcardcore_csrbank1_dma_length0_we = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_length0_w; -reg litesdcardcore_csrbank1_dma_enable0_re = 1'd0; +reg litesdcardcore_csrbank1_dma_enable0_re = 1'd0; wire litesdcardcore_csrbank1_dma_enable0_r; -reg litesdcardcore_csrbank1_dma_enable0_we = 1'd0; +reg litesdcardcore_csrbank1_dma_enable0_we = 1'd0; wire litesdcardcore_csrbank1_dma_enable0_w; -reg litesdcardcore_csrbank1_dma_done_re = 1'd0; +reg litesdcardcore_csrbank1_dma_done_re = 1'd0; wire litesdcardcore_csrbank1_dma_done_r; -reg litesdcardcore_csrbank1_dma_done_we = 1'd0; +reg litesdcardcore_csrbank1_dma_done_we = 1'd0; wire litesdcardcore_csrbank1_dma_done_w; -reg litesdcardcore_csrbank1_dma_loop0_re = 1'd0; +reg litesdcardcore_csrbank1_dma_loop0_re = 1'd0; wire litesdcardcore_csrbank1_dma_loop0_r; -reg litesdcardcore_csrbank1_dma_loop0_we = 1'd0; +reg litesdcardcore_csrbank1_dma_loop0_we = 1'd0; wire litesdcardcore_csrbank1_dma_loop0_w; -reg litesdcardcore_csrbank1_dma_offset_re = 1'd0; +reg litesdcardcore_csrbank1_dma_offset_re = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_offset_r; -reg litesdcardcore_csrbank1_dma_offset_we = 1'd0; +reg litesdcardcore_csrbank1_dma_offset_we = 1'd0; wire [31:0] litesdcardcore_csrbank1_dma_offset_w; wire litesdcardcore_csrbank1_sel; wire [13:0] litesdcardcore_interface2_bank_bus_adr; wire litesdcardcore_interface2_bank_bus_we; wire [31:0] litesdcardcore_interface2_bank_bus_dat_w; -reg [31:0] litesdcardcore_interface2_bank_bus_dat_r = 32'd0; -reg litesdcardcore_csrbank2_cmd_argument0_re = 1'd0; +reg [31:0] litesdcardcore_interface2_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank2_cmd_argument0_re = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_argument0_r; -reg litesdcardcore_csrbank2_cmd_argument0_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_argument0_we = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_argument0_w; -reg litesdcardcore_csrbank2_cmd_command0_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_command0_re = 1'd0; wire [13:0] litesdcardcore_csrbank2_cmd_command0_r; -reg litesdcardcore_csrbank2_cmd_command0_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_command0_we = 1'd0; wire [13:0] litesdcardcore_csrbank2_cmd_command0_w; -reg litesdcardcore_csrbank2_cmd_send0_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_send0_re = 1'd0; wire litesdcardcore_csrbank2_cmd_send0_r; -reg litesdcardcore_csrbank2_cmd_send0_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_send0_we = 1'd0; wire litesdcardcore_csrbank2_cmd_send0_w; -reg litesdcardcore_csrbank2_cmd_response3_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_response3_re = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response3_r; -reg litesdcardcore_csrbank2_cmd_response3_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_response3_we = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response3_w; -reg litesdcardcore_csrbank2_cmd_response2_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_response2_re = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response2_r; -reg litesdcardcore_csrbank2_cmd_response2_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_response2_we = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response2_w; -reg litesdcardcore_csrbank2_cmd_response1_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_response1_re = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response1_r; -reg litesdcardcore_csrbank2_cmd_response1_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_response1_we = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response1_w; -reg litesdcardcore_csrbank2_cmd_response0_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_response0_re = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response0_r; -reg litesdcardcore_csrbank2_cmd_response0_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_response0_we = 1'd0; wire [31:0] litesdcardcore_csrbank2_cmd_response0_w; -reg litesdcardcore_csrbank2_cmd_event_re = 1'd0; +reg litesdcardcore_csrbank2_cmd_event_re = 1'd0; wire [3:0] litesdcardcore_csrbank2_cmd_event_r; -reg litesdcardcore_csrbank2_cmd_event_we = 1'd0; +reg litesdcardcore_csrbank2_cmd_event_we = 1'd0; wire [3:0] litesdcardcore_csrbank2_cmd_event_w; -reg litesdcardcore_csrbank2_data_event_re = 1'd0; +reg litesdcardcore_csrbank2_data_event_re = 1'd0; wire [3:0] litesdcardcore_csrbank2_data_event_r; -reg litesdcardcore_csrbank2_data_event_we = 1'd0; +reg litesdcardcore_csrbank2_data_event_we = 1'd0; wire [3:0] litesdcardcore_csrbank2_data_event_w; -reg litesdcardcore_csrbank2_block_length0_re = 1'd0; +reg litesdcardcore_csrbank2_block_length0_re = 1'd0; wire [9:0] litesdcardcore_csrbank2_block_length0_r; -reg litesdcardcore_csrbank2_block_length0_we = 1'd0; +reg litesdcardcore_csrbank2_block_length0_we = 1'd0; wire [9:0] litesdcardcore_csrbank2_block_length0_w; -reg litesdcardcore_csrbank2_block_count0_re = 1'd0; +reg litesdcardcore_csrbank2_block_count0_re = 1'd0; wire [31:0] litesdcardcore_csrbank2_block_count0_r; -reg litesdcardcore_csrbank2_block_count0_we = 1'd0; +reg litesdcardcore_csrbank2_block_count0_we = 1'd0; wire [31:0] litesdcardcore_csrbank2_block_count0_w; wire litesdcardcore_csrbank2_sel; wire [13:0] litesdcardcore_interface3_bank_bus_adr; wire litesdcardcore_interface3_bank_bus_we; wire [31:0] litesdcardcore_interface3_bank_bus_dat_w; -reg [31:0] litesdcardcore_interface3_bank_bus_dat_r = 32'd0; -reg litesdcardcore_csrbank3_status_re = 1'd0; +reg [31:0] litesdcardcore_interface3_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank3_status_re = 1'd0; wire [3:0] litesdcardcore_csrbank3_status_r; -reg litesdcardcore_csrbank3_status_we = 1'd0; +reg litesdcardcore_csrbank3_status_we = 1'd0; wire [3:0] litesdcardcore_csrbank3_status_w; -reg litesdcardcore_csrbank3_pending_re = 1'd0; +reg litesdcardcore_csrbank3_pending_re = 1'd0; wire [3:0] litesdcardcore_csrbank3_pending_r; -reg litesdcardcore_csrbank3_pending_we = 1'd0; +reg litesdcardcore_csrbank3_pending_we = 1'd0; wire [3:0] litesdcardcore_csrbank3_pending_w; -reg litesdcardcore_csrbank3_enable0_re = 1'd0; +reg litesdcardcore_csrbank3_enable0_re = 1'd0; wire [3:0] litesdcardcore_csrbank3_enable0_r; -reg litesdcardcore_csrbank3_enable0_we = 1'd0; +reg litesdcardcore_csrbank3_enable0_we = 1'd0; wire [3:0] litesdcardcore_csrbank3_enable0_w; wire litesdcardcore_csrbank3_sel; wire [13:0] litesdcardcore_interface4_bank_bus_adr; wire litesdcardcore_interface4_bank_bus_we; wire [31:0] litesdcardcore_interface4_bank_bus_dat_w; -reg [31:0] litesdcardcore_interface4_bank_bus_dat_r = 32'd0; -reg litesdcardcore_csrbank4_dma_base1_re = 1'd0; +reg [31:0] litesdcardcore_interface4_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank4_dma_base1_re = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_base1_r; -reg litesdcardcore_csrbank4_dma_base1_we = 1'd0; +reg litesdcardcore_csrbank4_dma_base1_we = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_base1_w; -reg litesdcardcore_csrbank4_dma_base0_re = 1'd0; +reg litesdcardcore_csrbank4_dma_base0_re = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_base0_r; -reg litesdcardcore_csrbank4_dma_base0_we = 1'd0; +reg litesdcardcore_csrbank4_dma_base0_we = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_base0_w; -reg litesdcardcore_csrbank4_dma_length0_re = 1'd0; +reg litesdcardcore_csrbank4_dma_length0_re = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_length0_r; -reg litesdcardcore_csrbank4_dma_length0_we = 1'd0; +reg litesdcardcore_csrbank4_dma_length0_we = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_length0_w; -reg litesdcardcore_csrbank4_dma_enable0_re = 1'd0; +reg litesdcardcore_csrbank4_dma_enable0_re = 1'd0; wire litesdcardcore_csrbank4_dma_enable0_r; -reg litesdcardcore_csrbank4_dma_enable0_we = 1'd0; +reg litesdcardcore_csrbank4_dma_enable0_we = 1'd0; wire litesdcardcore_csrbank4_dma_enable0_w; -reg litesdcardcore_csrbank4_dma_done_re = 1'd0; +reg litesdcardcore_csrbank4_dma_done_re = 1'd0; wire litesdcardcore_csrbank4_dma_done_r; -reg litesdcardcore_csrbank4_dma_done_we = 1'd0; +reg litesdcardcore_csrbank4_dma_done_we = 1'd0; wire litesdcardcore_csrbank4_dma_done_w; -reg litesdcardcore_csrbank4_dma_loop0_re = 1'd0; +reg litesdcardcore_csrbank4_dma_loop0_re = 1'd0; wire litesdcardcore_csrbank4_dma_loop0_r; -reg litesdcardcore_csrbank4_dma_loop0_we = 1'd0; +reg litesdcardcore_csrbank4_dma_loop0_we = 1'd0; wire litesdcardcore_csrbank4_dma_loop0_w; -reg litesdcardcore_csrbank4_dma_offset_re = 1'd0; +reg litesdcardcore_csrbank4_dma_offset_re = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_offset_r; -reg litesdcardcore_csrbank4_dma_offset_we = 1'd0; +reg litesdcardcore_csrbank4_dma_offset_we = 1'd0; wire [31:0] litesdcardcore_csrbank4_dma_offset_w; wire litesdcardcore_csrbank4_sel; wire [13:0] litesdcardcore_interface5_bank_bus_adr; wire litesdcardcore_interface5_bank_bus_we; wire [31:0] litesdcardcore_interface5_bank_bus_dat_w; -reg [31:0] litesdcardcore_interface5_bank_bus_dat_r = 32'd0; -reg litesdcardcore_csrbank5_card_detect_re = 1'd0; +reg [31:0] litesdcardcore_interface5_bank_bus_dat_r = 32'd0; +reg litesdcardcore_csrbank5_card_detect_re = 1'd0; wire litesdcardcore_csrbank5_card_detect_r; -reg litesdcardcore_csrbank5_card_detect_we = 1'd0; +reg litesdcardcore_csrbank5_card_detect_we = 1'd0; wire litesdcardcore_csrbank5_card_detect_w; -reg litesdcardcore_csrbank5_clocker_divider0_re = 1'd0; +reg litesdcardcore_csrbank5_clocker_divider0_re = 1'd0; wire [8:0] litesdcardcore_csrbank5_clocker_divider0_r; -reg litesdcardcore_csrbank5_clocker_divider0_we = 1'd0; +reg litesdcardcore_csrbank5_clocker_divider0_we = 1'd0; wire [8:0] litesdcardcore_csrbank5_clocker_divider0_w; -reg litesdcardcore_csrbank5_dataw_status_re = 1'd0; +reg litesdcardcore_csrbank5_dataw_status_re = 1'd0; wire [2:0] litesdcardcore_csrbank5_dataw_status_r; -reg litesdcardcore_csrbank5_dataw_status_we = 1'd0; +reg litesdcardcore_csrbank5_dataw_status_we = 1'd0; wire [2:0] litesdcardcore_csrbank5_dataw_status_w; wire litesdcardcore_csrbank5_sel; wire [13:0] litesdcardcore_csr_interconnect_adr; wire litesdcardcore_csr_interconnect_we; wire [31:0] litesdcardcore_csr_interconnect_dat_w; wire [31:0] litesdcardcore_csr_interconnect_dat_r; -reg litesdcardcore_state = 1'd0; -reg litesdcardcore_next_state = 1'd0; -reg [31:0] array_muxed0 = 32'd0; -reg [31:0] array_muxed1 = 32'd0; -reg [3:0] array_muxed2 = 4'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg [2:0] array_muxed6 = 3'd0; -reg [1:0] array_muxed7 = 2'd0; +reg litesdcardcore_state = 1'd0; +reg litesdcardcore_next_state = 1'd0; +reg [31:0] array_muxed0 = 32'd0; +reg [31:0] array_muxed1 = 32'd0; +reg [3:0] array_muxed2 = 4'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg [2:0] array_muxed6 = 3'd0; +reg [1:0] array_muxed7 = 2'd0; wire sdrio_clk; -reg xilinxsdrtristateimpl0__o = 1'd0; -reg xilinxsdrtristateimpl0_oe_n = 1'd0; +reg xilinxsdrtristateimpl0__o = 1'd0; +reg xilinxsdrtristateimpl0_oe_n = 1'd0; wire xilinxsdrtristateimpl0__i; -reg xilinxsdrtristateimpl1__o = 1'd0; -reg xilinxsdrtristateimpl1_oe_n = 1'd0; +reg xilinxsdrtristateimpl1__o = 1'd0; +reg xilinxsdrtristateimpl1_oe_n = 1'd0; wire xilinxsdrtristateimpl1__i; -reg xilinxsdrtristateimpl2__o = 1'd0; -reg xilinxsdrtristateimpl2_oe_n = 1'd0; +reg xilinxsdrtristateimpl2__o = 1'd0; +reg xilinxsdrtristateimpl2_oe_n = 1'd0; wire xilinxsdrtristateimpl2__i; -reg xilinxsdrtristateimpl3__o = 1'd0; -reg xilinxsdrtristateimpl3_oe_n = 1'd0; +reg xilinxsdrtristateimpl3__o = 1'd0; +reg xilinxsdrtristateimpl3_oe_n = 1'd0; wire xilinxsdrtristateimpl3__i; -reg xilinxsdrtristateimpl4__o = 1'd0; -reg xilinxsdrtristateimpl4_oe_n = 1'd0; +reg xilinxsdrtristateimpl4__o = 1'd0; +reg xilinxsdrtristateimpl4_oe_n = 1'd0; wire xilinxsdrtristateimpl4__i; wire sdrio_clk_1; wire sdrio_clk_2; @@ -1110,6 +1131,10 @@ wire sdrio_clk_13; wire sdrio_clk_14; wire sdrio_clk_15; +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + assign wb_ctrl_adr_1 = wb_ctrl_adr; assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; @@ -1411,7 +1436,7 @@ always @(*) begin cmdr_sink_ready <= 1'd1; if ((cmdr_sink_payload_cmd_type == 2'd3)) begin cmdr_source_valid <= 1'd0; - cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; + cmdr_timeout_sdphycmdr_next_value0 <= 7'd100; cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; subfragments_sdphycmdr_next_state <= 2'd3; end else begin @@ -1475,7 +1500,7 @@ always @(*) begin end end default: begin - cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000; + cmdr_timeout_sdphycmdr_next_value0 <= 7'd100; cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; cmdr_count_sdphycmdr_next_value1 <= 1'd0; cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; @@ -1762,7 +1787,7 @@ always @(*) begin datar_count_sdphydatar_next_value_ce0 <= 1'd1; if ((datar_sink_valid & datar_pads_out_ready)) begin datar_pads_out_payload_clk <= 1'd1; - datar_timeout_sdphydatar_next_value1 <= 32'd100000000; + datar_timeout_sdphydatar_next_value1 <= 32'd100; datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; datar_count_sdphydatar_next_value0 <= 1'd0; datar_count_sdphydatar_next_value_ce0 <= 1'd1; @@ -2262,11 +2287,11 @@ always @(*) begin end assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first); always @(*) begin + sdblock2mem_fifo_sink_first <= 1'd0; sdblock2mem_fifo_sink_last <= 1'd0; sdblock2mem_sink_sink_ready0 <= 1'd0; sdblock2mem_fifo_sink_payload_data <= 8'd0; sdblock2mem_fifo_sink_valid <= 1'd0; - sdblock2mem_fifo_sink_first <= 1'd0; if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0; sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready; @@ -2442,13 +2467,13 @@ always @(*) begin endcase end always @(*) begin + subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0; sdmem2block_dma_sink_last <= 1'd0; sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0; sdmem2block_dma_sink_payload_address <= 32'd0; sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0; - sdmem2block_dma_done_status <= 1'd0; sdmem2block_dma_sink_valid <= 1'd0; - subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0; + sdmem2block_dma_done_status <= 1'd0; subfragments_sdmem2blockdma_resetinserter_next_state <= subfragments_sdmem2blockdma_resetinserter_state; case (subfragments_sdmem2blockdma_resetinserter_state) 1'd1: begin @@ -2580,8 +2605,8 @@ always @(*) begin litesdcardcore_next_state <= 1'd0; litesdcardcore_litesdcardcore_adr <= 14'd0; litesdcardcore_litesdcardcore_we <= 1'd0; - litesdcardcore_litesdcardcore_dat_w <= 32'd0; litesdcardcore_litesdcardcore_wishbone_ack <= 1'd0; + litesdcardcore_litesdcardcore_dat_w <= 32'd0; litesdcardcore_next_state <= litesdcardcore_state; case (litesdcardcore_state) 1'd1: begin @@ -2638,8 +2663,8 @@ assign litesdcardcore_shared_err = wb_dma_err_1; assign litesdcardcore_wait = ((litesdcardcore_shared_stb & litesdcardcore_shared_cyc) & (~litesdcardcore_shared_ack)); always @(*) begin litesdcardcore_error <= 1'd0; - litesdcardcore_shared_dat_r <= 32'd0; litesdcardcore_shared_ack <= 1'd0; + litesdcardcore_shared_dat_r <= 32'd0; litesdcardcore_shared_ack <= wb_dma_ack_1; litesdcardcore_shared_dat_r <= ({32{litesdcardcore_slave_sel_r}} & wb_dma_dat_r_1); if (litesdcardcore_done) begin @@ -2661,8 +2686,8 @@ always @(*) begin end assign litesdcardcore_csrbank0_scratch0_r = litesdcardcore_interface0_bank_bus_dat_w[31:0]; always @(*) begin - litesdcardcore_csrbank0_scratch0_re <= 1'd0; litesdcardcore_csrbank0_scratch0_we <= 1'd0; + litesdcardcore_csrbank0_scratch0_re <= 1'd0; if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 1'd1))) begin litesdcardcore_csrbank0_scratch0_re <= litesdcardcore_interface0_bank_bus_we; litesdcardcore_csrbank0_scratch0_we <= (~litesdcardcore_interface0_bank_bus_we); @@ -2700,8 +2725,8 @@ always @(*) begin end assign litesdcardcore_csrbank1_dma_base0_r = litesdcardcore_interface1_bank_bus_dat_w[31:0]; always @(*) begin - litesdcardcore_csrbank1_dma_base0_we <= 1'd0; litesdcardcore_csrbank1_dma_base0_re <= 1'd0; + litesdcardcore_csrbank1_dma_base0_we <= 1'd0; if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 1'd1))) begin litesdcardcore_csrbank1_dma_base0_re <= litesdcardcore_interface1_bank_bus_we; litesdcardcore_csrbank1_dma_base0_we <= (~litesdcardcore_interface1_bank_bus_we); @@ -2764,8 +2789,8 @@ assign sdblock2mem_wishbonedmawriter_offset_we = litesdcardcore_csrbank1_dma_off assign litesdcardcore_csrbank2_sel = (litesdcardcore_interface2_bank_bus_adr[13:9] == 2'd2); assign litesdcardcore_csrbank2_cmd_argument0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; always @(*) begin - litesdcardcore_csrbank2_cmd_argument0_we <= 1'd0; litesdcardcore_csrbank2_cmd_argument0_re <= 1'd0; + litesdcardcore_csrbank2_cmd_argument0_we <= 1'd0; if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 1'd0))) begin litesdcardcore_csrbank2_cmd_argument0_re <= litesdcardcore_interface2_bank_bus_we; litesdcardcore_csrbank2_cmd_argument0_we <= (~litesdcardcore_interface2_bank_bus_we); @@ -2854,8 +2879,8 @@ always @(*) begin end assign litesdcardcore_csrbank2_block_count0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0]; always @(*) begin - litesdcardcore_csrbank2_block_count0_we <= 1'd0; litesdcardcore_csrbank2_block_count0_re <= 1'd0; + litesdcardcore_csrbank2_block_count0_we <= 1'd0; if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd10))) begin litesdcardcore_csrbank2_block_count0_re <= litesdcardcore_interface2_bank_bus_we; litesdcardcore_csrbank2_block_count0_we <= (~litesdcardcore_interface2_bank_bus_we); @@ -2913,8 +2938,8 @@ always @(*) begin end assign litesdcardcore_csrbank3_enable0_r = litesdcardcore_interface3_bank_bus_dat_w[3:0]; always @(*) begin - litesdcardcore_csrbank3_enable0_re <= 1'd0; litesdcardcore_csrbank3_enable0_we <= 1'd0; + litesdcardcore_csrbank3_enable0_re <= 1'd0; if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 2'd2))) begin litesdcardcore_csrbank3_enable0_re <= litesdcardcore_interface3_bank_bus_we; litesdcardcore_csrbank3_enable0_we <= (~litesdcardcore_interface3_bank_bus_we); @@ -2973,8 +2998,8 @@ always @(*) begin end assign litesdcardcore_csrbank4_dma_enable0_r = litesdcardcore_interface4_bank_bus_dat_w[0]; always @(*) begin - litesdcardcore_csrbank4_dma_enable0_re <= 1'd0; litesdcardcore_csrbank4_dma_enable0_we <= 1'd0; + litesdcardcore_csrbank4_dma_enable0_re <= 1'd0; if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 2'd3))) begin litesdcardcore_csrbank4_dma_enable0_re <= litesdcardcore_interface4_bank_bus_we; litesdcardcore_csrbank4_dma_enable0_we <= (~litesdcardcore_interface4_bank_bus_we); @@ -3000,8 +3025,8 @@ always @(*) begin end assign litesdcardcore_csrbank4_dma_offset_r = litesdcardcore_interface4_bank_bus_dat_w[31:0]; always @(*) begin - litesdcardcore_csrbank4_dma_offset_re <= 1'd0; litesdcardcore_csrbank4_dma_offset_we <= 1'd0; + litesdcardcore_csrbank4_dma_offset_re <= 1'd0; if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd6))) begin litesdcardcore_csrbank4_dma_offset_re <= litesdcardcore_interface4_bank_bus_we; litesdcardcore_csrbank4_dma_offset_we <= (~litesdcardcore_interface4_bank_bus_we); @@ -3028,8 +3053,8 @@ always @(*) begin end assign litesdcardcore_csrbank5_clocker_divider0_r = litesdcardcore_interface5_bank_bus_dat_w[8:0]; always @(*) begin - litesdcardcore_csrbank5_clocker_divider0_we <= 1'd0; litesdcardcore_csrbank5_clocker_divider0_re <= 1'd0; + litesdcardcore_csrbank5_clocker_divider0_we <= 1'd0; if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 1'd1))) begin litesdcardcore_csrbank5_clocker_divider0_re <= litesdcardcore_interface5_bank_bus_we; litesdcardcore_csrbank5_clocker_divider0_we <= (~litesdcardcore_interface5_bank_bus_we); @@ -3192,6 +3217,11 @@ assign sdrio_clk_13 = sys_clk; assign sdrio_clk_14 = sys_clk; assign sdrio_clk_15 = sys_clk; + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + always @(posedge por_clk) begin int_rst <= rst; end @@ -3981,7 +4011,7 @@ always @(posedge sys_clk) begin clocker_ce_delayed <= 1'd0; init_count <= 8'd0; cmdw_count <= 8'd0; - cmdr_timeout <= 32'd100000000; + cmdr_timeout <= 32'd100; cmdr_count <= 8'd0; cmdr_busy <= 1'd0; cmdr_cmdr_run <= 1'd0; @@ -4004,7 +4034,7 @@ always @(posedge sys_clk) begin dataw_crc_converter_strobe_all <= 1'd0; dataw_crc_buf_source_valid <= 1'd0; dataw_crc_buf_source_payload_data <= 8'd0; - datar_timeout <= 32'd100000000; + datar_timeout <= 32'd100; datar_count <= 10'd0; datar_datar_run <= 1'd0; datar_datar_converter_source_payload_data <= 8'd0; @@ -4116,53 +4146,70 @@ always @(posedge sys_clk) begin end end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Async | Write: ---- | reg [9:0] storage[0:7]; -reg [9:0] memdat; +reg [9:0] storage_dat0; always @(posedge sys_clk) begin if (sdcore_fifo_wrport_we) storage[sdcore_fifo_wrport_adr] <= sdcore_fifo_wrport_dat_w; - memdat <= storage[sdcore_fifo_wrport_adr]; + storage_dat0 <= storage[sdcore_fifo_wrport_adr]; end - always @(posedge sys_clk) begin end - -assign sdcore_fifo_wrport_dat_r = memdat; +assign sdcore_fifo_wrport_dat_r = storage_dat0; assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr]; + +//------------------------------------------------------------------------------ +// Memory storage_1: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | reg [9:0] storage_1[0:511]; -reg [9:0] memdat_1; -reg [9:0] memdat_2; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; always @(posedge sys_clk) begin if (sdblock2mem_fifo_wrport_we) storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w; - memdat_1 <= storage_1[sdblock2mem_fifo_wrport_adr]; + storage_1_dat0 <= storage_1[sdblock2mem_fifo_wrport_adr]; end - always @(posedge sys_clk) begin if (sdblock2mem_fifo_rdport_re) - memdat_2 <= storage_1[sdblock2mem_fifo_rdport_adr]; + storage_1_dat1 <= storage_1[sdblock2mem_fifo_rdport_adr]; end +assign sdblock2mem_fifo_wrport_dat_r = storage_1_dat0; +assign sdblock2mem_fifo_rdport_dat_r = storage_1_dat1; -assign sdblock2mem_fifo_wrport_dat_r = memdat_1; -assign sdblock2mem_fifo_rdport_dat_r = memdat_2; +//------------------------------------------------------------------------------ +// Memory storage_2: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | reg [9:0] storage_2[0:511]; -reg [9:0] memdat_3; -reg [9:0] memdat_4; +reg [9:0] storage_2_dat0; +reg [9:0] storage_2_dat1; always @(posedge sys_clk) begin if (sdmem2block_fifo_wrport_we) storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w; - memdat_3 <= storage_2[sdmem2block_fifo_wrport_adr]; + storage_2_dat0 <= storage_2[sdmem2block_fifo_wrport_adr]; end - always @(posedge sys_clk) begin if (sdmem2block_fifo_rdport_re) - memdat_4 <= storage_2[sdmem2block_fifo_rdport_adr]; + storage_2_dat1 <= storage_2[sdmem2block_fifo_rdport_adr]; end +assign sdmem2block_fifo_wrport_dat_r = storage_2_dat0; +assign sdmem2block_fifo_rdport_dat_r = storage_2_dat1; -assign sdmem2block_fifo_wrport_dat_r = memdat_3; -assign sdmem2block_fifo_rdport_dat_r = memdat_4; IOBUF IOBUF( .I(xilinxsdrtristateimpl0__o), @@ -4200,3 +4247,7 @@ IOBUF IOBUF_4( ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-01-14 07:30:20. +//------------------------------------------------------------------------------