diff --git a/core.vhdl b/core.vhdl
index 77af882..95dd89b 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -76,6 +76,7 @@ architecture behave of core is
     signal fetch2_stall_in : std_ulogic;
     signal decode1_stall_in : std_ulogic;
     signal decode2_stall_out : std_ulogic;
+    signal ex1_icache_inval: std_ulogic;
 
     signal flush: std_ulogic;
 
@@ -129,7 +130,7 @@ begin
             wishbone_in => wishbone_insn_in
             );
 
-    icache_rst <= rst or dbg_icache_rst;
+    icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 
     fetch2_0: entity work.fetch2
         port map (
@@ -204,6 +205,7 @@ begin
             e_in => decode2_to_execute1,
             f_out => execute1_to_fetch1,
             e_out => execute1_to_writeback,
+	    icache_inval => ex1_icache_inval,
             terminate_out => terminate
             );
 
diff --git a/decode1.vhdl b/decode1.vhdl
index afb1315..1a7bc0b 100644
--- a/decode1.vhdl
+++ b/decode1.vhdl
@@ -168,7 +168,7 @@ architecture behaviour of decode1 is
 		2#1110011010#  =>       (ALU,    OP_EXTS,      NONE,       NONE,        RS,   RA,   '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', RC,   '0', '0'), -- extsh
 		2#1111011010#  =>       (ALU,    OP_EXTS,      NONE,       NONE,        RS,   RA,   '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', RC,   '0', '0'), -- extsw
 		-- 2#110111101-# extswsli
-		2#1111010110#  =>       (ALU,    OP_NOP,       NONE,       NONE,        NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- icbi
+		2#1111010110#  =>       (ALU,    OP_ICBI,      NONE,       NONE,        NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- icbi
 		2#0000010110#  =>       (ALU,    OP_NOP,       NONE,       NONE,        NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- icbt
 		2#0000001111#  =>       (ALU,    OP_ISEL,      RA_OR_ZERO, RB,          NONE, RT,   '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- isel
 		2#0000101111#  =>       (ALU,    OP_ISEL,      RA_OR_ZERO, RB,          NONE, RT,   '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- isel
diff --git a/execute1.vhdl b/execute1.vhdl
index ec11678..f2277eb 100644
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -27,6 +27,7 @@ entity execute1 is
 
 	e_out : out Execute1ToWritebackType;
 
+	icache_inval : out std_ulogic;
 	terminate_out : out std_ulogic
 	);
 end entity execute1;
@@ -134,6 +135,7 @@ begin
 	ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 
 	terminate_out <= '0';
+	icache_inval <= '0';
 	f_out <= Execute1ToFetch1TypeInit;
 
 	-- Next insn adder used in a couple of places
@@ -353,6 +355,9 @@ begin
 		f_out.redirect <= '1';
 		f_out.redirect_nia <= next_nia;
 
+	    when OP_ICBI =>
+		icache_inval <= '1';
+
 	    when others =>
 		terminate_out <= '1';
 		report "illegal";