From 7437f699cab9701199ed9a50de20a9ea8ec0be23 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 8 Jan 2025 18:16:26 +1100 Subject: [PATCH] core: Implement the PIR SPR This reports the CPU core number, currently always 0, but this will be useful in future for distinguishing which CPU is which in a multiprocessor system. Signed-off-by: Paul Mackerras --- common.vhdl | 2 ++ core.vhdl | 2 ++ decode1.vhdl | 2 ++ execute1.vhdl | 5 ++++- soc.vhdl | 1 + 5 files changed, 11 insertions(+), 1 deletion(-) diff --git a/common.vhdl b/common.vhdl index c04bbe4..76eaec2 100644 --- a/common.vhdl +++ b/common.vhdl @@ -63,6 +63,7 @@ package common is constant SPR_UDSCR : spr_num_t := 3; constant SPR_DSCR : spr_num_t := 17; constant SPR_VRSAVE : spr_num_t := 256; + constant SPR_PIR : spr_num_t := 1023; -- PMU registers constant SPR_UPMC1 : spr_num_t := 771; @@ -172,6 +173,7 @@ package common is constant SPRSEL_HEIR : spr_selector := 4x"9"; constant SPRSEL_CTRL : spr_selector := 4x"a"; constant SPRSEL_DSCR : spr_selector := 4x"b"; + constant SPRSEL_PIR : spr_selector := 4x"c"; constant SPRSEL_XER : spr_selector := 4x"f"; -- FSCR and HFSCR bit numbers diff --git a/core.vhdl b/core.vhdl index bba1004..187e176 100644 --- a/core.vhdl +++ b/core.vhdl @@ -9,6 +9,7 @@ use work.wishbone_types.all; entity core is generic ( SIM : boolean := false; + CPU_INDEX : natural := 0; DISABLE_FLATTEN : boolean := false; EX1_BYPASS : boolean := true; HAS_FPU : boolean := true; @@ -364,6 +365,7 @@ begin execute1_0: entity work.execute1 generic map ( SIM => SIM, + CPU_INDEX => CPU_INDEX, EX1_BYPASS => EX1_BYPASS, HAS_FPU => HAS_FPU, LOG_LENGTH => LOG_LENGTH diff --git a/decode1.vhdl b/decode1.vhdl index 7b480a3..0ea9ed1 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -486,6 +486,8 @@ architecture behaviour of decode1 is i.sel := SPRSEL_DSCR; when SPR_DSCR => i.sel := SPRSEL_DSCR; + when SPR_PIR => + i.sel := SPRSEL_PIR; when others => i.valid := '0'; end case; diff --git a/execute1.vhdl b/execute1.vhdl index 84a6fbe..3b7ec2f 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -15,6 +15,7 @@ entity execute1 is SIM : boolean := false; EX1_BYPASS : boolean := true; HAS_FPU : boolean := true; + CPU_INDEX : natural; -- Non-zero to enable log data collection LOG_LENGTH : natural := 0 ); @@ -702,7 +703,8 @@ begin ex2 <= ex2in; ctrl <= ctrl_tmp; if valid_in = '1' then - report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) & + report "CPU " & natural'image(CPU_INDEX) & " execute " & to_hstring(e_in.nia) & + " op=" & insn_type_t'image(e_in.insn_type) & " wr=" & to_hstring(ex1in.e.write_reg) & " we=" & std_ulogic'image(ex1in.e.write_enable) & " tag=" & integer'image(ex1in.e.instr_tag.tag) & std_ulogic'image(ex1in.e.instr_tag.valid) & " 2nd=" & std_ulogic'image(e_in.second); @@ -1874,6 +1876,7 @@ begin ctrl.heir when SPRSEL_HEIR, assemble_ctrl(ctrl, ex1.msr(MSR_PR)) when SPRSEL_CTRL, 39x"0" & ctrl.dscr when SPRSEL_DSCR, + 56x"0" & std_ulogic_vector(to_unsigned(CPU_INDEX, 8)) when SPRSEL_PIR, assemble_xer(ex1.e.xerc, ctrl.xer_low) when others; stage2_stall <= l_in.l2stall or fp_in.f2stall; diff --git a/soc.vhdl b/soc.vhdl index 71474df..3e3b438 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -351,6 +351,7 @@ begin processor: entity work.core generic map( SIM => SIM, + CPU_INDEX => 0, HAS_FPU => HAS_FPU, HAS_BTC => HAS_BTC, DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,