diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc
index 309b12f..4db6aab 100644
--- a/fpga/arty_a7.xdc
+++ b/fpga/arty_a7.xdc
@@ -531,7 +531,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
 # Clock constraints
 ################################################################################
 
-create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
+create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
 
 create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }]
 
diff --git a/fpga/cmod_a7-35.xdc b/fpga/cmod_a7-35.xdc
index 4444e2a..8566b3f 100644
--- a/fpga/cmod_a7-35.xdc
+++ b/fpga/cmod_a7-35.xdc
@@ -1,6 +1,6 @@
 ## Clock signal 12 MHz
 set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
-create_clock -add -name sys_clk_pin -period 83.33 [get_ports {ext_clk}];
+create_clock -name sys_clk_pin -period 83.33 [get_ports {ext_clk}];
 
 set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
 set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd  }];
diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc
index 6a46627..4cedfd3 100644
--- a/fpga/nexys-video.xdc
+++ b/fpga/nexys-video.xdc
@@ -313,7 +313,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
 # Clock constraints
 ################################################################################
 
-create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
+create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
 
 ################################################################################
 # False path constraints (from LiteX as they relate to LiteDRAM)
diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc
index aa1af22..e661354 100644
--- a/fpga/nexys_a7.xdc
+++ b/fpga/nexys_a7.xdc
@@ -1,5 +1,5 @@
 set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk]
-create_clock -period 10.000 -name sys_clk_pin -add [get_ports ext_clk]
+create_clock -period 10.000 -name sys_clk_pin [get_ports ext_clk]
 
 set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]