From 79101041d6ea581cefdbabdf9fe96b1c4f76fcd5 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 17 Oct 2019 20:07:18 +1100 Subject: [PATCH] wishbone: Add stall signal Pipelined wishbone needs it Signed-off-by: Benjamin Herrenschmidt --- wishbone_types.vhdl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl index 12f0bc7..1b8a28b 100644 --- a/wishbone_types.vhdl +++ b/wishbone_types.vhdl @@ -21,9 +21,10 @@ package wishbone_types is constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0')); type wishbone_slave_out is record - dat : wishbone_data_type; - ack : std_ulogic; + dat : wishbone_data_type; + ack : std_ulogic; + stall : std_ulogic; end record; - constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0')); + constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0')); end package wishbone_types;