From 79a14c8e37ed072fb5c533e961d96b76443dd7e8 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Sep 2019 16:36:47 +1000 Subject: [PATCH] Add forwarding in the register file We need this for the upcoming pipelining patches. Signed-off-by: Anton Blanchard --- register_file.vhdl | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/register_file.vhdl b/register_file.vhdl index 9995374..bc6ef1c 100644 --- a/register_file.vhdl +++ b/register_file.vhdl @@ -51,17 +51,17 @@ begin d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg))); -- Forward any written data - --if w_in.write_enable = '1' then - --if d_in.read1_reg = w_in.write_reg then - --d_out.read1_data <= w_in.write_data; - --end if; - --if d_in.read2_reg = w_in.write_reg then - --d_out.read2_data <= w_in.write_data; - --end if; - --if d_in.read3_reg = w_in.write_reg then - --d_out.read3_data <= w_in.write_data; - --end if; - --end if; + if w_in.write_enable = '1' then + if d_in.read1_reg = w_in.write_reg then + d_out.read1_data <= w_in.write_data; + end if; + if d_in.read2_reg = w_in.write_reg then + d_out.read2_data <= w_in.write_data; + end if; + if d_in.read3_reg = w_in.write_reg then + d_out.read3_data <= w_in.write_data; + end if; + end if; end process register_read_0; -- debug