From 7a60c118ed6d8901012da13caff8aeded64f6cdc Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Fri, 29 Jul 2022 08:27:10 +1000 Subject: [PATCH] loadstore1: Simplify address generation in OP_FETCH_FAILED case Instead of having a multiplexer in loadstore1 in order to be able to put the instruction address into v.addr, we now set decode.input_reg_a to CIA in the decode table entry for OP_FETCH_FAILED. That means that the operand selection machinery in decode2 will supply the instruction address to loadstore1 on the lv.addr1 input and no special case is needed in loadstore1. This saves a few LUTs (~40 on the Artix-7). Signed-off-by: Paul Mackerras --- common.vhdl | 3 +-- decode1.vhdl | 2 +- execute1.vhdl | 1 - loadstore1.vhdl | 1 - 4 files changed, 2 insertions(+), 5 deletions(-) diff --git a/common.vhdl b/common.vhdl index f6cb939..685d0c3 100644 --- a/common.vhdl +++ b/common.vhdl @@ -476,7 +476,6 @@ package common is type Execute1ToLoadstore1Type is record valid : std_ulogic; op : insn_type_t; -- what ld/st or m[tf]spr or TLB op to do - nia : std_ulogic_vector(63 downto 0); insn : std_ulogic_vector(31 downto 0); instr_tag : instr_tag_t; addr1 : std_ulogic_vector(63 downto 0); @@ -504,7 +503,7 @@ package common is (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0', sign_extend => '0', update => '0', xerc => xerc_init, reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0', - nia => (others => '0'), insn => (others => '0'), + insn => (others => '0'), instr_tag => instr_tag_init, addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), write_reg => (others => '0'), diff --git a/decode1.vhdl b/decode1.vhdl index b2c6059..fda2ce2 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -527,7 +527,7 @@ architecture behaviour of decode1 is -- unit fac internal in1 in2 in3 out CR CR inv inv cry cry ldst BR sgn upd rsrv 32b sgn rc lk sgl rpt -- op in out A out in out len ext pipe constant nop_instr : decode_rom_t := (ALU, NONE, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE); - constant fetch_fail_inst: decode_rom_t := (LDST, NONE, OP_FETCH_FAILED, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE); + constant fetch_fail_inst: decode_rom_t := (LDST, NONE, OP_FETCH_FAILED, CIA, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE); function decode_ram_spr(sprn : spr_num_t) return ram_spr_info is variable ret : ram_spr_info; diff --git a/execute1.vhdl b/execute1.vhdl index fd20c01..0eb0b7f 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -1554,7 +1554,6 @@ begin -- Outputs to loadstore1 (async) lv.op := e_in.insn_type; - lv.nia := e_in.nia; lv.instr_tag := e_in.instr_tag; lv.addr1 := a_in; lv.addr2 := b_in; diff --git a/loadstore1.vhdl b/loadstore1.vhdl index 726f57a..7071582 100644 --- a/loadstore1.vhdl +++ b/loadstore1.vhdl @@ -497,7 +497,6 @@ begin when OP_FETCH_FAILED => -- send it to the MMU to do the radix walk v.instr_fault := '1'; - v.addr := l_in.nia; v.mmu_op := '1'; when others => end case;