From 82825a11badfbd65b18271ee3cd099248cd18de1 Mon Sep 17 00:00:00 2001
From: Paul Mackerras <paulus@ozlabs.org>
Date: Sat, 6 Dec 2025 17:55:11 +1100
Subject: [PATCH] FPU: Set result sign correctly for denorm +/- 0 case

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 fpu.vhdl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fpu.vhdl b/fpu.vhdl
index 554ca8c..106cee6 100644
--- a/fpu.vhdl
+++ b/fpu.vhdl
@@ -911,6 +911,7 @@ begin
                 -- result is +/- B
                 e.result_sel := AIN_B;
                 e.result_class := r.b.class;
+                -- r.result_sign is already correct
             else
                 e.result_class := ZERO;
             end if;
@@ -937,6 +938,7 @@ begin
             elsif r.is_addition = '1' then
                 -- fadd, result is A
                 e.result_sel := AIN_A;
+                e.rsgn_op := RSGN_SEL;
             else
                 -- other things, result is zero
                 e.result_class := ZERO;