From 9a63c098a5471e40ca0364a867d30204f0288bc4 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 23 Oct 2019 10:52:37 +1100 Subject: [PATCH] Move log2/ispow2 to a utils package (Out of icache and dcache) Signed-off-by: Benjamin Herrenschmidt --- Makefile | 5 +++-- dcache.vhdl | 21 +-------------------- icache.vhdl | 21 +-------------------- utils.vhdl | 35 +++++++++++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 42 deletions(-) create mode 100644 utils.vhdl diff --git a/Makefile b/Makefile index 3056c53..1c68ff4 100644 --- a/Makefile +++ b/Makefile @@ -35,10 +35,11 @@ helpers.o: cache_ram.o: plru.o: plru_tb.o: plru.o -icache.o: common.o wishbone_types.o plru.o cache_ram.o icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o -dcache.o: common.o wishbone_types.o plru.o cache_ram.o dcache_tb.o: common.o wishbone_types.o dcache.o simple_ram_behavioural.o +utils.o: +icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o +dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o insn_helpers.o: loadstore1.o: common.o helpers.o logical.o: decode_types.o diff --git a/dcache.vhdl b/dcache.vhdl index f12fd35..7d6e74c 100644 --- a/dcache.vhdl +++ b/dcache.vhdl @@ -16,6 +16,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; +use work.utils.all; use work.common.all; use work.helpers.all; use work.wishbone_types.all; @@ -44,26 +45,6 @@ entity dcache is end entity dcache; architecture rtl of dcache is - function log2(i : natural) return integer is - variable tmp : integer := i; - variable ret : integer := 0; - begin - while tmp > 1 loop - ret := ret + 1; - tmp := tmp / 2; - end loop; - return ret; - end function; - - function ispow2(i : integer) return boolean is - begin - if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then - return true; - else - return false; - end if; - end function; - -- BRAM organisation: We never access more than wishbone_data_bits at -- a time so to save resources we make the array only that wide, and -- use consecutive indices for to make a cache "line" diff --git a/icache.vhdl b/icache.vhdl index 70226a8..20d5724 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -21,6 +21,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; +use work.utils.all; use work.common.all; use work.wishbone_types.all; @@ -51,26 +52,6 @@ entity icache is end entity icache; architecture rtl of icache is - function log2(i : natural) return integer is - variable tmp : integer := i; - variable ret : integer := 0; - begin - while tmp > 1 loop - ret := ret + 1; - tmp := tmp / 2; - end loop; - return ret; - end function; - - function ispow2(i : integer) return boolean is - begin - if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then - return true; - else - return false; - end if; - end function; - -- BRAM organisation: We never access more than wishbone_data_bits at -- a time so to save resources we make the array only that wide, and -- use consecutive indices for to make a cache "line" diff --git a/utils.vhdl b/utils.vhdl new file mode 100644 index 0000000..7238641 --- /dev/null +++ b/utils.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package utils is + + function log2(i : natural) return integer; + function ispow2(i : integer) return boolean; + +end utils; + +package body utils is + + function log2(i : natural) return integer is + variable tmp : integer := i; + variable ret : integer := 0; + begin + while tmp > 1 loop + ret := ret + 1; + tmp := tmp / 2; + end loop; + return ret; + end function; + + function ispow2(i : integer) return boolean is + begin + if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then + return true; + else + return false; + end if; + end function; + +end utils; +