From 9b40b5a77b2ecd2d6a6317e624fc7b4aff7bb7c5 Mon Sep 17 00:00:00 2001
From: Paul Mackerras <paulus@ozlabs.org>
Date: Fri, 19 Jun 2020 17:13:06 +1000
Subject: [PATCH] logical: Only do output inversion for OP_AND, OP_OR and
 OP_XOR

It's not needed for the other ops (popcnt, parity, etc.) and the
logical unit shows up as a critical path from time to time.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 logical.vhdl | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/logical.vhdl b/logical.vhdl
index 5e6abfa..0f53544 100644
--- a/logical.vhdl
+++ b/logical.vhdl
@@ -87,12 +87,19 @@ begin
         end if;
 
         case op is
-            when OP_AND =>
-                tmp := rs and rb_adj;
-            when OP_OR =>
-                tmp := rs or rb_adj;
-	    when OP_XOR =>
-                tmp := rs xor rb_adj;
+            when OP_AND | OP_OR | OP_XOR =>
+                case op is
+                    when OP_AND =>
+                        tmp := rs and rb_adj;
+                    when OP_OR =>
+                        tmp := rs or rb_adj;
+                    when others =>
+                        tmp := rs xor rb_adj;
+                end case;
+                if invert_out = '1' then
+                    tmp := not tmp;
+                end if;
+
             when OP_POPCNT =>
                 tmp := popcnt;
             when OP_PRTY =>
@@ -115,9 +122,6 @@ begin
 		tmp(7 downto 0) := rs(7 downto 0);
         end case;
 
-        if invert_out = '1' then
-            tmp := not tmp;
-        end if;
         result <= tmp;
 
     end process;