diff --git a/dmi_dtm_xilinx.vhdl b/dmi_dtm_xilinx.vhdl
index 6e47c56..ed92e95 100644
--- a/dmi_dtm_xilinx.vhdl
+++ b/dmi_dtm_xilinx.vhdl
@@ -127,6 +127,11 @@ architecture behaviour of dmi_dtm is
     constant DMI_RSP_OK  : std_ulogic_vector(1 downto 0) := "00";
     constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
 
+    attribute ASYNC_REG : string;
+    attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
+    attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
+    attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
+    attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
 begin
 
     -- Implement the Xilinx bscan2 for series 7 devices (TODO: use PoC to
@@ -161,7 +166,6 @@ begin
 	    O => jtag_clk
 	    );
 
-
     -- dmi_req synchronization
     dmi_req_sync : process(sys_clk)
     begin