From a53ad600145f04348f8270c82dcb3979341c8368 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 7 Sep 2019 21:08:02 +1000 Subject: [PATCH] Rename a few reset signals clk -> ext_clk reset_n -> ext_rst reset -> rst Signed-off-by: Anton Blanchard --- fpga/arty_a7-35.xdc | 6 +++--- fpga/nexys-video.xdc | 6 +++--- fpga/nexys_a7.xdc | 6 +++--- fpga/toplevel.vhd | 22 +++++++++++----------- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/fpga/arty_a7-35.xdc b/fpga/arty_a7-35.xdc index f8280b9..30c3546 100644 --- a/fpga/arty_a7-35.xdc +++ b/fpga/arty_a7-35.xdc @@ -1,7 +1,7 @@ -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }]; +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }]; -set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { reset_n }]; +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]; set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }]; diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc index 2b71cc5..6fc09f3 100644 --- a/fpga/nexys-video.xdc +++ b/fpga/nexys-video.xdc @@ -1,7 +1,7 @@ -set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports clk] -create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ext_clk] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk] -set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports reset_n] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports ext_rst] set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart0_txd] set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc index b94f1bc..09a08d9 100644 --- a/fpga/nexys_a7.xdc +++ b/fpga/nexys_a7.xdc @@ -1,7 +1,7 @@ -set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk] -create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk] -set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst] set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd] set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] diff --git a/fpga/toplevel.vhd b/fpga/toplevel.vhd index ba41b31..9408823 100644 --- a/fpga/toplevel.vhd +++ b/fpga/toplevel.vhd @@ -16,8 +16,8 @@ entity toplevel is MEMORY_SIZE : positive := 524288; RAM_INIT_FILE : string := "firmware.hex"); port( - clk : in std_logic; - reset_n : in std_logic; + ext_clk : in std_logic; + ext_rst : in std_logic; -- UART0 signals: uart0_txd : out std_logic; @@ -28,7 +28,7 @@ end entity toplevel; architecture behaviour of toplevel is -- Reset signals: - signal reset : std_logic; + signal rst : std_logic; -- Internal clock signals: signal system_clk : std_logic; @@ -86,7 +86,7 @@ begin address_decoder: process(system_clk) begin if rising_edge(system_clk) then - if reset = '1' then + if rst = '1' then intercon_peripheral <= PERIPHERAL_NONE; intercon_busy <= false; else @@ -140,16 +140,16 @@ begin reset_controller: entity work.pp_soc_reset port map( clk => system_clk, - reset_n => reset_n, - reset_out => reset, + reset_n => ext_rst, + reset_out => rst, system_clk => system_clk, system_clk_locked => system_clk_locked ); clkgen: entity work.clock_generator port map( - clk => clk, - resetn => reset_n, + clk => ext_clk, + resetn => ext_rst, system_clk => system_clk, locked => system_clk_locked ); @@ -157,7 +157,7 @@ begin processor: entity work.core port map( clk => system_clk, - rst => reset, + rst => rst, wishbone_out => wishbone_proc_out, wishbone_in => wishbone_proc_in @@ -176,7 +176,7 @@ begin FIFO_DEPTH => 32 ) port map( clk => system_clk, - reset => reset, + reset => rst, txd => uart0_txd, rxd => uart0_rxd, wb_adr_in => uart0_adr_in, @@ -199,7 +199,7 @@ begin RAM_INIT_FILE => RAM_INIT_FILE ) port map( clk => system_clk, - reset => reset, + reset => rst, wb_adr_in => main_memory_adr_in, wb_dat_in => main_memory_dat_in, wb_dat_out => main_memory_dat_out,