From b0aa5340b82a59d345db50b02b598e8da8add88e Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 10 Aug 2022 11:33:10 +1000 Subject: [PATCH] execute1: Make it clear that divide logic is not included when HAS_FPU=true This adds a "not HAS_FPU" condition in a few places to make it obvious that logic to interface to the divide unit is not included when we have an FPU. Signed-off-by: Paul Mackerras --- execute1.vhdl | 88 ++++++++++++++++++++++++++------------------------- 1 file changed, 45 insertions(+), 43 deletions(-) diff --git a/execute1.vhdl b/execute1.vhdl index a8fd052..2d6af00 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -699,54 +699,56 @@ begin x_to_multiply.addend <= addend; -- Interface to divide unit - sign1 := '0'; - sign2 := '0'; - if e_in.is_signed = '1' then - if e_in.is_32bit = '1' then - sign1 := a_in(31); - sign2 := b_in(31); + if not HAS_FPU then + sign1 := '0'; + sign2 := '0'; + if e_in.is_signed = '1' then + if e_in.is_32bit = '1' then + sign1 := a_in(31); + sign2 := b_in(31); + else + sign1 := a_in(63); + sign2 := b_in(63); + end if; + end if; + -- take absolute values + if sign1 = '0' then + abs1 := signed(a_in); else - sign1 := a_in(63); - sign2 := b_in(63); + abs1 := - signed(a_in); end if; - end if; - -- take absolute values - if sign1 = '0' then - abs1 := signed(a_in); - else - abs1 := - signed(a_in); - end if; - if sign2 = '0' then - abs2 := signed(b_in); - else - abs2 := - signed(b_in); - end if; - - x_to_divider.is_signed <= e_in.is_signed; - x_to_divider.is_32bit <= e_in.is_32bit; - x_to_divider.is_extended <= '0'; - x_to_divider.is_modulus <= '0'; - if e_in.insn_type = OP_MOD then - x_to_divider.is_modulus <= '1'; - end if; - x_to_divider.flush <= flush_in; - x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus); - if e_in.is_32bit = '0' then - -- 64-bit forms - if e_in.insn_type = OP_DIVE then - x_to_divider.is_extended <= '1'; + if sign2 = '0' then + abs2 := signed(b_in); + else + abs2 := - signed(b_in); end if; - x_to_divider.dividend <= std_ulogic_vector(abs1); - x_to_divider.divisor <= std_ulogic_vector(abs2); - else - -- 32-bit forms + + x_to_divider.is_signed <= e_in.is_signed; + x_to_divider.is_32bit <= e_in.is_32bit; x_to_divider.is_extended <= '0'; - if e_in.insn_type = OP_DIVE then -- extended forms - x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000"; + x_to_divider.is_modulus <= '0'; + if e_in.insn_type = OP_MOD then + x_to_divider.is_modulus <= '1'; + end if; + x_to_divider.flush <= flush_in; + x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus); + if e_in.is_32bit = '0' then + -- 64-bit forms + if e_in.insn_type = OP_DIVE then + x_to_divider.is_extended <= '1'; + end if; + x_to_divider.dividend <= std_ulogic_vector(abs1); + x_to_divider.divisor <= std_ulogic_vector(abs2); else - x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0)); + -- 32-bit forms + x_to_divider.is_extended <= '0'; + if e_in.insn_type = OP_DIVE then -- extended forms + x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000"; + else + x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0)); + end if; + x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0)); end if; - x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0)); end if; -- signals to 32-bit multiplier @@ -1486,7 +1488,7 @@ begin end if; end if; - if ex1.div_in_progress = '1' then + if not HAS_FPU and ex1.div_in_progress = '1' then v.div_in_progress := not divider_to_x.valid; v.busy := not divider_to_x.valid; if divider_to_x.valid = '1' and ex1.oe = '1' then