From b0f7237b7f5cbdbf132085f5517d84f6cd19f3c6 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 3 Oct 2020 20:08:11 +1000 Subject: [PATCH] execute1: Fix bug in trace interrupt vs. ITLB miss If an instruction fetch results in an instruction TLB miss, an OP_FETCH_FAILED instruction is sent down the pipe. If the MSR[TE] field is set for instruction tracing, the core currently considers that executing the OP_FETCH_FAILED counts as having executed one instruction and so generates a trace interrupt on the next valid instruction, meaning that the trace interrupt happens before the desired instruction rather than after it. Fix this by not tracing OP_FETCH_FAILED instructions. Signed-off-by: Paul Mackerras --- execute1.vhdl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/execute1.vhdl b/execute1.vhdl index 29713b2..b6387b9 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -1124,6 +1124,10 @@ begin elsif HAS_FPU and e_in.unit = FPU then fv.valid := '1'; end if; + -- Handling an ITLB miss doesn't count as having executed an instruction + if e_in.insn_type = OP_FETCH_FAILED then + do_trace := '0'; + end if; elsif r.f.redirect = '1' then v.e.valid := '1';