From ab7105f43815ac6728845348b3496d90b1fa0dec Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 15 Feb 2025 16:33:23 +1100 Subject: [PATCH 1/3] liteeth: Update generated code Signed-off-by: Paul Mackerras --- liteeth/generated/arty/liteeth_core.v | 6222 ++++++++--------- liteeth/generated/ecpix-5/liteeth_core.v | 5977 ++++++++-------- liteeth/generated/nexys-video/liteeth_core.v | 6074 ++++++++-------- liteeth/generated/wukong-v2/liteeth_core.v | 6580 +++++++++--------- 4 files changed, 12285 insertions(+), 12568 deletions(-) diff --git a/liteeth/generated/arty/liteeth_core.v b/liteeth/generated/arty/liteeth_core.v index f363a2f..31df355 100644 --- a/liteeth/generated/arty/liteeth_core.v +++ b/liteeth/generated/arty/liteeth_core.v @@ -8,8 +8,8 @@ // // Filename : liteeth_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-05 17:38:49 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 16:17:45 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -88,7 +88,8 @@ MACCore │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) -│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── last_handler (LiteEthLastHandler) +│ │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) @@ -145,9 +146,11 @@ MACCore │ │ │ └─── ev (SharedIRQ) │ │ └─── sram_0* (SRAM) │ │ └─── sram_1* (SRAM) +│ │ └─── decoder_0* (Decoder) │ │ └─── sram_2* (SRAM) │ │ └─── sram_3* (SRAM) -│ │ └─── decoder_0* (Decoder) +│ │ └─── decoder_1* (Decoder) +│ └─── ev (SharedIRQ) └─── csr_bridge (Wishbone2CSR) │ └─── fsm (FSM) └─── csr_bankarray (CSRBankArray) @@ -189,1475 +192,1465 @@ MACCore // Signals //------------------------------------------------------------------------------ -wire [13:0] builder_adr; -wire [39:0] builder_complexslicelowerer_slice_proxy; -reg [19:0] builder_count = 20'd1000000; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_reset0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_scratch0_we = 1'd0; -wire builder_csrbank0_sel; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; -reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; -reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; -reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; -reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; -wire builder_csrbank1_sel; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_w; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire builder_csrbank2_sel; -wire [31:0] builder_dat_r; -wire [31:0] builder_dat_w; -wire builder_done; -reg builder_error = 1'd0; -wire builder_grant; -reg builder_interface0_ack = 1'd0; -wire [29:0] builder_interface0_adr; -wire [13:0] builder_interface0_bank_bus_adr; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface0_bank_bus_dat_w; -wire builder_interface0_bank_bus_we; -wire [1:0] builder_interface0_bte; -wire [2:0] builder_interface0_cti; -wire builder_interface0_cyc; -reg [31:0] builder_interface0_dat_r = 32'd0; -wire [31:0] builder_interface0_dat_w; -reg builder_interface0_err = 1'd0; -wire [3:0] builder_interface0_sel; -wire builder_interface0_stb; -wire builder_interface0_we; -reg [13:0] builder_interface1_adr = 14'd0; -wire [13:0] builder_interface1_bank_bus_adr; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface1_bank_bus_dat_w; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_dat_r; -reg [31:0] builder_interface1_dat_w = 32'd0; -reg builder_interface1_we = 1'd0; -wire [13:0] builder_interface2_bank_bus_adr; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface2_bank_bus_dat_w; -wire builder_interface2_bank_bus_we; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg builder_next_state = 1'd0; -wire builder_request; -wire builder_rst_meta0; -wire builder_rst_meta1; -reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; -reg [29:0] builder_self0 = 30'd0; -reg [31:0] builder_self1 = 32'd0; -reg [3:0] builder_self2 = 4'd0; -reg builder_self3 = 1'd0; -reg builder_self4 = 1'd0; -reg builder_self5 = 1'd0; -reg [2:0] builder_self6 = 3'd0; -reg [1:0] builder_self7 = 2'd0; -reg builder_shared_ack = 1'd0; -wire [29:0] builder_shared_adr; -wire [1:0] builder_shared_bte; -wire [2:0] builder_shared_cti; -wire builder_shared_cyc; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [31:0] builder_shared_dat_w; -wire builder_shared_err; -wire [3:0] builder_shared_sel; -wire builder_shared_stb; -wire builder_shared_we; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_state = 1'd0; -wire [31:0] builder_t_slice_proxy0; -wire [31:0] builder_t_slice_proxy1; -wire [31:0] builder_t_slice_proxy10; -wire [31:0] builder_t_slice_proxy11; -wire [31:0] builder_t_slice_proxy12; -wire [31:0] builder_t_slice_proxy13; -wire [31:0] builder_t_slice_proxy14; -wire [31:0] builder_t_slice_proxy15; -wire [31:0] builder_t_slice_proxy16; -wire [31:0] builder_t_slice_proxy17; -wire [31:0] builder_t_slice_proxy18; -wire [31:0] builder_t_slice_proxy19; -wire [31:0] builder_t_slice_proxy2; -wire [31:0] builder_t_slice_proxy20; -wire [31:0] builder_t_slice_proxy21; -wire [31:0] builder_t_slice_proxy22; -wire [31:0] builder_t_slice_proxy23; -wire [31:0] builder_t_slice_proxy24; -wire [31:0] builder_t_slice_proxy25; -wire [31:0] builder_t_slice_proxy26; -wire [31:0] builder_t_slice_proxy27; -wire [31:0] builder_t_slice_proxy28; -wire [31:0] builder_t_slice_proxy29; -wire [31:0] builder_t_slice_proxy3; -wire [31:0] builder_t_slice_proxy30; -wire [31:0] builder_t_slice_proxy31; -wire [31:0] builder_t_slice_proxy32; -wire [31:0] builder_t_slice_proxy33; -wire [31:0] builder_t_slice_proxy34; -wire [31:0] builder_t_slice_proxy35; -wire [31:0] builder_t_slice_proxy36; -wire [31:0] builder_t_slice_proxy37; -wire [31:0] builder_t_slice_proxy38; -wire [31:0] builder_t_slice_proxy39; -wire [31:0] builder_t_slice_proxy4; -wire [31:0] builder_t_slice_proxy40; -wire [31:0] builder_t_slice_proxy41; -wire [31:0] builder_t_slice_proxy42; -wire [31:0] builder_t_slice_proxy43; -wire [31:0] builder_t_slice_proxy44; -wire [31:0] builder_t_slice_proxy45; -wire [31:0] builder_t_slice_proxy46; -wire [31:0] builder_t_slice_proxy47; -wire [31:0] builder_t_slice_proxy48; -wire [31:0] builder_t_slice_proxy49; -wire [31:0] builder_t_slice_proxy5; -wire [31:0] builder_t_slice_proxy50; -wire [31:0] builder_t_slice_proxy51; -wire [31:0] builder_t_slice_proxy52; -wire [31:0] builder_t_slice_proxy53; -wire [31:0] builder_t_slice_proxy54; -wire [31:0] builder_t_slice_proxy55; -wire [31:0] builder_t_slice_proxy56; -wire [31:0] builder_t_slice_proxy57; -wire [31:0] builder_t_slice_proxy58; -wire [31:0] builder_t_slice_proxy59; -wire [31:0] builder_t_slice_proxy6; -wire [31:0] builder_t_slice_proxy60; -wire [31:0] builder_t_slice_proxy61; -wire [31:0] builder_t_slice_proxy62; -wire [31:0] builder_t_slice_proxy63; -wire [31:0] builder_t_slice_proxy7; -wire [31:0] builder_t_slice_proxy8; -wire [31:0] builder_t_slice_proxy9; -reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; -reg builder_txdatapath_liteethmacgap_next_state = 1'd0; -reg builder_txdatapath_liteethmacgap_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; -reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; -reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; -wire builder_wait; -wire builder_we; +wire [13:0] adr; +wire core_bufferizeendpoints_pipe_valid_sink_first; +wire core_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] core_bufferizeendpoints_pipe_valid_sink_payload_data; +wire core_bufferizeendpoints_pipe_valid_sink_payload_error; +wire core_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire core_bufferizeendpoints_pipe_valid_sink_ready; +wire core_bufferizeendpoints_pipe_valid_sink_valid; +reg core_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] core_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire core_bufferizeendpoints_pipe_valid_source_ready; +reg core_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire core_bufferizeendpoints_sink_sink_first; +wire core_bufferizeendpoints_sink_sink_last; +wire [7:0] core_bufferizeendpoints_sink_sink_payload_data; +wire core_bufferizeendpoints_sink_sink_payload_error; +wire core_bufferizeendpoints_sink_sink_payload_last_be; +wire core_bufferizeendpoints_sink_sink_ready; +wire core_bufferizeendpoints_sink_sink_valid; +wire core_bufferizeendpoints_source_source_first; +wire core_bufferizeendpoints_source_source_last; +wire [7:0] core_bufferizeendpoints_source_source_payload_data; +wire core_bufferizeendpoints_source_source_payload_error; +wire core_bufferizeendpoints_source_source_payload_last_be; +wire core_bufferizeendpoints_source_source_ready; +wire core_bufferizeendpoints_source_source_valid; +reg core_crc_errors_re = 1'd0; +reg [31:0] core_crc_errors_status = 32'd0; +wire core_crc_errors_we; +wire core_liteethmaccrc32checker_crc_be; +reg core_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] core_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] core_liteethmaccrc32checker_crc_data0; +wire [7:0] core_liteethmaccrc32checker_crc_data1; +reg core_liteethmaccrc32checker_crc_error0 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg core_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_value = 32'd0; +reg core_liteethmaccrc32checker_error = 1'd0; +wire core_liteethmaccrc32checker_fifo_full; +wire core_liteethmaccrc32checker_fifo_in; +wire core_liteethmaccrc32checker_fifo_out; +reg core_liteethmaccrc32checker_fifo_reset = 1'd0; +reg core_liteethmaccrc32checker_last_be = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_first; +wire core_liteethmaccrc32checker_sink_sink_last; +wire [7:0] core_liteethmaccrc32checker_sink_sink_payload_data; +wire core_liteethmaccrc32checker_sink_sink_payload_error; +wire core_liteethmaccrc32checker_sink_sink_payload_last_be; +reg core_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_valid; +wire core_liteethmaccrc32checker_source_source_first; +reg core_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] core_liteethmaccrc32checker_source_source_payload_data; +reg core_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg core_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire core_liteethmaccrc32checker_source_source_ready; +reg core_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire core_liteethmaccrc32checker_syncfifo_do_read; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] core_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] core_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg core_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_sink_first; +wire core_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_sink_ready; +reg core_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_first; +wire core_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_source_payload_data; +wire core_liteethmaccrc32checker_syncfifo_source_payload_error; +wire core_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg core_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] core_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire core_liteethmaccrc32checker_syncfifo_wrport_we; +reg core_preamble_errors_re = 1'd0; +reg [31:0] core_preamble_errors_status = 32'd0; +wire core_preamble_errors_we; +wire core_pulsesynchronizer0_i; +wire core_pulsesynchronizer0_o; +reg core_pulsesynchronizer0_toggle_i = 1'd0; +wire core_pulsesynchronizer0_toggle_o; +reg core_pulsesynchronizer0_toggle_o_r = 1'd0; +wire core_pulsesynchronizer1_i; +wire core_pulsesynchronizer1_o; +reg core_pulsesynchronizer1_toggle_i = 1'd0; +wire core_pulsesynchronizer1_toggle_o; +reg core_pulsesynchronizer1_toggle_o_r = 1'd0; +reg core_re = 1'd0; +wire [41:0] core_rx_cdc_cdc_asyncfifo_din; +wire [41:0] core_rx_cdc_cdc_asyncfifo_dout; +wire core_rx_cdc_cdc_asyncfifo_re; +wire core_rx_cdc_cdc_asyncfifo_readable; +wire core_rx_cdc_cdc_asyncfifo_we; +wire core_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_rx_cdc_cdc_consume_wdomain; +wire core_rx_cdc_cdc_fifo_in_first; +wire core_rx_cdc_cdc_fifo_in_last; +wire [31:0] core_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_last_be; +wire core_rx_cdc_cdc_fifo_out_first; +wire core_rx_cdc_cdc_fifo_out_last; +wire [31:0] core_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_last_be; +wire core_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] core_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] core_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_produce_rdomain; +wire [4:0] core_rx_cdc_cdc_rdport_adr; +wire [41:0] core_rx_cdc_cdc_rdport_dat_r; +wire core_rx_cdc_cdc_sink_first; +wire core_rx_cdc_cdc_sink_last; +wire [31:0] core_rx_cdc_cdc_sink_payload_data; +wire [3:0] core_rx_cdc_cdc_sink_payload_error; +wire [3:0] core_rx_cdc_cdc_sink_payload_last_be; +wire core_rx_cdc_cdc_sink_ready; +wire core_rx_cdc_cdc_sink_valid; +wire core_rx_cdc_cdc_source_first; +wire core_rx_cdc_cdc_source_last; +wire [31:0] core_rx_cdc_cdc_source_payload_data; +wire [3:0] core_rx_cdc_cdc_source_payload_error; +wire [3:0] core_rx_cdc_cdc_source_payload_last_be; +wire core_rx_cdc_cdc_source_ready; +wire core_rx_cdc_cdc_source_valid; +wire [4:0] core_rx_cdc_cdc_wrport_adr; +wire [41:0] core_rx_cdc_cdc_wrport_dat_r; +wire [41:0] core_rx_cdc_cdc_wrport_dat_w; +wire core_rx_cdc_cdc_wrport_we; +wire core_rx_cdc_sink_sink_first; +wire core_rx_cdc_sink_sink_last; +wire [31:0] core_rx_cdc_sink_sink_payload_data; +wire [3:0] core_rx_cdc_sink_sink_payload_error; +wire [3:0] core_rx_cdc_sink_sink_payload_last_be; +wire core_rx_cdc_sink_sink_ready; +wire core_rx_cdc_sink_sink_valid; +wire core_rx_cdc_source_source_first; +wire core_rx_cdc_source_source_last; +wire [31:0] core_rx_cdc_source_source_payload_data; +wire [3:0] core_rx_cdc_source_source_payload_error; +wire [3:0] core_rx_cdc_source_source_payload_last_be; +wire core_rx_cdc_source_source_ready; +wire core_rx_cdc_source_source_valid; +reg [1:0] core_rx_converter_converter_demux = 2'd0; +wire core_rx_converter_converter_load_part; +wire core_rx_converter_converter_sink_first; +wire core_rx_converter_converter_sink_last; +wire [9:0] core_rx_converter_converter_sink_payload_data; +wire core_rx_converter_converter_sink_ready; +wire core_rx_converter_converter_sink_valid; +reg core_rx_converter_converter_source_first = 1'd0; +reg core_rx_converter_converter_source_last = 1'd0; +reg [39:0] core_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] core_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire core_rx_converter_converter_source_ready; +wire core_rx_converter_converter_source_valid; +reg core_rx_converter_converter_strobe_all = 1'd0; +wire core_rx_converter_sink_first; +wire core_rx_converter_sink_last; +wire [7:0] core_rx_converter_sink_payload_data; +wire core_rx_converter_sink_payload_error; +wire core_rx_converter_sink_payload_last_be; +wire core_rx_converter_sink_ready; +wire core_rx_converter_sink_valid; +wire core_rx_converter_source_first; +wire core_rx_converter_source_last; +reg [31:0] core_rx_converter_source_payload_data = 32'd0; +reg [3:0] core_rx_converter_source_payload_error = 4'd0; +reg [3:0] core_rx_converter_source_payload_last_be = 4'd0; +wire core_rx_converter_source_ready; +wire core_rx_converter_source_source_first; +wire core_rx_converter_source_source_last; +wire [39:0] core_rx_converter_source_source_payload_data; +wire core_rx_converter_source_source_ready; +wire core_rx_converter_source_source_valid; +wire core_rx_converter_source_valid; +wire core_rx_last_be_sink_first; +wire core_rx_last_be_sink_last; +wire [7:0] core_rx_last_be_sink_payload_data; +wire core_rx_last_be_sink_payload_error; +wire core_rx_last_be_sink_payload_last_be; +wire core_rx_last_be_sink_ready; +wire core_rx_last_be_sink_valid; +wire core_rx_last_be_source_first; +wire core_rx_last_be_source_last; +wire [7:0] core_rx_last_be_source_payload_data; +wire core_rx_last_be_source_payload_error; +reg core_rx_last_be_source_payload_last_be = 1'd0; +wire core_rx_last_be_source_ready; +wire core_rx_last_be_source_valid; +wire core_rx_padding_sink_first; +wire core_rx_padding_sink_last; +wire [7:0] core_rx_padding_sink_payload_data; +wire core_rx_padding_sink_payload_error; +wire core_rx_padding_sink_payload_last_be; +wire core_rx_padding_sink_ready; +wire core_rx_padding_sink_valid; +wire core_rx_padding_source_first; +wire core_rx_padding_source_last; +wire [7:0] core_rx_padding_source_payload_data; +wire core_rx_padding_source_payload_error; +wire core_rx_padding_source_payload_last_be; +wire core_rx_padding_source_ready; +wire core_rx_padding_source_valid; +reg core_rx_preamble_error = 1'd0; +reg [63:0] core_rx_preamble_preamble = 64'd15372286728091293013; +wire core_rx_preamble_sink_first; +wire core_rx_preamble_sink_last; +wire [7:0] core_rx_preamble_sink_payload_data; +wire core_rx_preamble_sink_payload_error; +wire core_rx_preamble_sink_payload_last_be; +reg core_rx_preamble_sink_ready = 1'd0; +wire core_rx_preamble_sink_valid; +reg core_rx_preamble_source_first = 1'd0; +reg core_rx_preamble_source_last = 1'd0; +wire [7:0] core_rx_preamble_source_payload_data; +reg core_rx_preamble_source_payload_error = 1'd0; +wire core_rx_preamble_source_payload_last_be; +wire core_rx_preamble_source_ready; +reg core_rx_preamble_source_valid = 1'd0; +wire core_sink_first; +wire core_sink_last; +wire [31:0] core_sink_payload_data; +wire [3:0] core_sink_payload_error; +wire [3:0] core_sink_payload_last_be; +wire core_sink_ready; +wire core_sink_valid; +wire core_source_first; +wire core_source_last; +wire [31:0] core_source_payload_data; +wire [3:0] core_source_payload_error; +wire [3:0] core_source_payload_last_be; +wire core_source_ready; +wire core_source_valid; +reg core_status = 1'd1; +wire [41:0] core_tx_cdc_cdc_asyncfifo_din; +wire [41:0] core_tx_cdc_cdc_asyncfifo_dout; +wire core_tx_cdc_cdc_asyncfifo_re; +wire core_tx_cdc_cdc_asyncfifo_readable; +wire core_tx_cdc_cdc_asyncfifo_we; +wire core_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_tx_cdc_cdc_consume_wdomain; +wire core_tx_cdc_cdc_fifo_in_first; +wire core_tx_cdc_cdc_fifo_in_last; +wire [31:0] core_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_last_be; +wire core_tx_cdc_cdc_fifo_out_first; +wire core_tx_cdc_cdc_fifo_out_last; +wire [31:0] core_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_last_be; +wire core_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] core_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] core_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_produce_rdomain; +wire [4:0] core_tx_cdc_cdc_rdport_adr; +wire [41:0] core_tx_cdc_cdc_rdport_dat_r; +wire core_tx_cdc_cdc_sink_first; +wire core_tx_cdc_cdc_sink_last; +wire [31:0] core_tx_cdc_cdc_sink_payload_data; +wire [3:0] core_tx_cdc_cdc_sink_payload_error; +wire [3:0] core_tx_cdc_cdc_sink_payload_last_be; +wire core_tx_cdc_cdc_sink_ready; +wire core_tx_cdc_cdc_sink_valid; +wire core_tx_cdc_cdc_source_first; +wire core_tx_cdc_cdc_source_last; +wire [31:0] core_tx_cdc_cdc_source_payload_data; +wire [3:0] core_tx_cdc_cdc_source_payload_error; +wire [3:0] core_tx_cdc_cdc_source_payload_last_be; +wire core_tx_cdc_cdc_source_ready; +wire core_tx_cdc_cdc_source_valid; +wire [4:0] core_tx_cdc_cdc_wrport_adr; +wire [41:0] core_tx_cdc_cdc_wrport_dat_r; +wire [41:0] core_tx_cdc_cdc_wrport_dat_w; +wire core_tx_cdc_cdc_wrport_we; +wire core_tx_cdc_sink_sink_first; +wire core_tx_cdc_sink_sink_last; +wire [31:0] core_tx_cdc_sink_sink_payload_data; +wire [3:0] core_tx_cdc_sink_sink_payload_error; +wire [3:0] core_tx_cdc_sink_sink_payload_last_be; +wire core_tx_cdc_sink_sink_ready; +wire core_tx_cdc_sink_sink_valid; +wire core_tx_cdc_source_source_first; +wire core_tx_cdc_source_source_last; +wire [31:0] core_tx_cdc_source_source_payload_data; +wire [3:0] core_tx_cdc_source_source_payload_error; +wire [3:0] core_tx_cdc_source_source_payload_last_be; +wire core_tx_cdc_source_source_ready; +wire core_tx_cdc_source_source_valid; +wire core_tx_converter_converter_first; +wire core_tx_converter_converter_last; +reg [1:0] core_tx_converter_converter_mux = 2'd0; +wire core_tx_converter_converter_sink_first; +wire core_tx_converter_converter_sink_last; +reg [39:0] core_tx_converter_converter_sink_payload_data = 40'd0; +wire core_tx_converter_converter_sink_ready; +wire core_tx_converter_converter_sink_valid; +wire core_tx_converter_converter_source_first; +wire core_tx_converter_converter_source_last; +reg [9:0] core_tx_converter_converter_source_payload_data = 10'd0; +wire core_tx_converter_converter_source_payload_valid_token_count; +wire core_tx_converter_converter_source_ready; +wire core_tx_converter_converter_source_valid; +wire core_tx_converter_sink_first; +wire core_tx_converter_sink_last; +wire [31:0] core_tx_converter_sink_payload_data; +wire [3:0] core_tx_converter_sink_payload_error; +wire [3:0] core_tx_converter_sink_payload_last_be; +wire core_tx_converter_sink_ready; +wire core_tx_converter_sink_valid; +wire core_tx_converter_source_first; +wire core_tx_converter_source_last; +wire [7:0] core_tx_converter_source_payload_data; +wire core_tx_converter_source_payload_error; +wire core_tx_converter_source_payload_last_be; +wire core_tx_converter_source_ready; +wire core_tx_converter_source_source_first; +wire core_tx_converter_source_source_last; +wire [9:0] core_tx_converter_source_source_payload_data; +wire core_tx_converter_source_source_ready; +wire core_tx_converter_source_source_valid; +wire core_tx_converter_source_valid; +wire core_tx_crc_be; +reg core_tx_crc_ce = 1'd0; +reg [1:0] core_tx_crc_cnt = 2'd3; +wire core_tx_crc_cnt_done; +reg [31:0] core_tx_crc_crc_next = 32'd0; +reg [31:0] core_tx_crc_crc_packet = 32'd0; +reg [31:0] core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] core_tx_crc_crc_prev; +wire [7:0] core_tx_crc_data0; +wire [7:0] core_tx_crc_data1; +reg core_tx_crc_error = 1'd0; +reg core_tx_crc_is_ongoing0 = 1'd0; +reg core_tx_crc_is_ongoing1 = 1'd0; +reg core_tx_crc_last_be = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire core_tx_crc_pipe_valid_sink_first; +wire core_tx_crc_pipe_valid_sink_last; +wire [7:0] core_tx_crc_pipe_valid_sink_payload_data; +wire core_tx_crc_pipe_valid_sink_payload_error; +wire core_tx_crc_pipe_valid_sink_payload_last_be; +wire core_tx_crc_pipe_valid_sink_ready; +wire core_tx_crc_pipe_valid_sink_valid; +reg core_tx_crc_pipe_valid_source_first = 1'd0; +reg core_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] core_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg core_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg core_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire core_tx_crc_pipe_valid_source_ready; +reg core_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] core_tx_crc_reg = 32'd4294967295; +reg core_tx_crc_reset = 1'd0; +wire core_tx_crc_sink_first; +wire core_tx_crc_sink_last; +wire [7:0] core_tx_crc_sink_payload_data; +wire core_tx_crc_sink_payload_error; +wire core_tx_crc_sink_payload_last_be; +reg core_tx_crc_sink_ready = 1'd0; +wire core_tx_crc_sink_sink_first; +wire core_tx_crc_sink_sink_last; +wire [7:0] core_tx_crc_sink_sink_payload_data; +wire core_tx_crc_sink_sink_payload_error; +wire core_tx_crc_sink_sink_payload_last_be; +wire core_tx_crc_sink_sink_ready; +wire core_tx_crc_sink_sink_valid; +wire core_tx_crc_sink_valid; +reg core_tx_crc_source_first = 1'd0; +reg core_tx_crc_source_last = 1'd0; +reg [7:0] core_tx_crc_source_payload_data = 8'd0; +reg core_tx_crc_source_payload_error = 1'd0; +reg core_tx_crc_source_payload_last_be = 1'd0; +wire core_tx_crc_source_ready; +wire core_tx_crc_source_source_first; +wire core_tx_crc_source_source_last; +wire [7:0] core_tx_crc_source_source_payload_data; +wire core_tx_crc_source_source_payload_error; +wire core_tx_crc_source_source_payload_last_be; +wire core_tx_crc_source_source_ready; +wire core_tx_crc_source_source_valid; +reg core_tx_crc_source_valid = 1'd0; +reg [31:0] core_tx_crc_value = 32'd0; +reg [3:0] core_tx_gap_counter = 4'd0; +reg [3:0] core_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg core_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire core_tx_gap_sink_first; +wire core_tx_gap_sink_last; +wire [7:0] core_tx_gap_sink_payload_data; +wire core_tx_gap_sink_payload_error; +wire core_tx_gap_sink_payload_last_be; +reg core_tx_gap_sink_ready = 1'd0; +wire core_tx_gap_sink_valid; +reg core_tx_gap_source_first = 1'd0; +reg core_tx_gap_source_last = 1'd0; +reg [7:0] core_tx_gap_source_payload_data = 8'd0; +reg core_tx_gap_source_payload_error = 1'd0; +reg core_tx_gap_source_payload_last_be = 1'd0; +wire core_tx_gap_source_ready; +reg core_tx_gap_source_valid = 1'd0; +wire core_tx_last_be_last_handler_sink_first; +wire core_tx_last_be_last_handler_sink_last; +wire [7:0] core_tx_last_be_last_handler_sink_payload_data; +wire core_tx_last_be_last_handler_sink_payload_error; +wire core_tx_last_be_last_handler_sink_payload_last_be; +reg core_tx_last_be_last_handler_sink_ready = 1'd0; +wire core_tx_last_be_last_handler_sink_valid; +reg core_tx_last_be_last_handler_source_first = 1'd0; +reg core_tx_last_be_last_handler_source_last = 1'd0; +reg [7:0] core_tx_last_be_last_handler_source_payload_data = 8'd0; +reg core_tx_last_be_last_handler_source_payload_error = 1'd0; +reg core_tx_last_be_last_handler_source_payload_last_be = 1'd0; +wire core_tx_last_be_last_handler_source_ready; +reg core_tx_last_be_last_handler_source_valid = 1'd0; +wire core_tx_last_be_sink_sink_first; +wire core_tx_last_be_sink_sink_last; +wire [7:0] core_tx_last_be_sink_sink_payload_data; +wire core_tx_last_be_sink_sink_payload_error; +wire core_tx_last_be_sink_sink_payload_last_be; +wire core_tx_last_be_sink_sink_ready; +wire core_tx_last_be_sink_sink_valid; +wire core_tx_last_be_source_source_first; +wire core_tx_last_be_source_source_last; +wire [7:0] core_tx_last_be_source_source_payload_data; +wire core_tx_last_be_source_source_payload_error; +wire core_tx_last_be_source_source_payload_last_be; +wire core_tx_last_be_source_source_ready; +wire core_tx_last_be_source_source_valid; +reg [15:0] core_tx_padding_counter = 16'd0; +reg [15:0] core_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg core_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire core_tx_padding_counter_done; +wire core_tx_padding_sink_first; +wire core_tx_padding_sink_last; +wire [7:0] core_tx_padding_sink_payload_data; +wire core_tx_padding_sink_payload_error; +wire core_tx_padding_sink_payload_last_be; +reg core_tx_padding_sink_ready = 1'd0; +wire core_tx_padding_sink_valid; +reg core_tx_padding_source_first = 1'd0; +reg core_tx_padding_source_last = 1'd0; +reg [7:0] core_tx_padding_source_payload_data = 8'd0; +reg core_tx_padding_source_payload_error = 1'd0; +reg core_tx_padding_source_payload_last_be = 1'd0; +wire core_tx_padding_source_ready; +reg core_tx_padding_source_valid = 1'd0; +reg [2:0] core_tx_preamble_count = 3'd0; +reg [2:0] core_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg core_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] core_tx_preamble_preamble = 64'd15372286728091293013; +wire core_tx_preamble_sink_first; +wire core_tx_preamble_sink_last; +wire [7:0] core_tx_preamble_sink_payload_data; +wire core_tx_preamble_sink_payload_error; +wire core_tx_preamble_sink_payload_last_be; +reg core_tx_preamble_sink_ready = 1'd0; +wire core_tx_preamble_sink_valid; +reg core_tx_preamble_source_first = 1'd0; +reg core_tx_preamble_source_last = 1'd0; +reg [7:0] core_tx_preamble_source_payload_data = 8'd0; +reg core_tx_preamble_source_payload_error = 1'd0; +wire core_tx_preamble_source_payload_last_be; +wire core_tx_preamble_source_ready; +reg core_tx_preamble_source_valid = 1'd0; +wire core_we; +reg [19:0] count = 20'd1000000; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire csrbank1_preamble_crc_r; +reg csrbank1_preamble_crc_re = 1'd0; +wire csrbank1_preamble_crc_w; +reg csrbank1_preamble_crc_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_r; +reg csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_w; +reg csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_r; +reg csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_w; +reg csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire csrbank1_sel; +wire csrbank1_sram_reader_ev_enable0_r; +reg csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire csrbank1_sram_reader_ev_enable0_w; +reg csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire csrbank1_sram_reader_ev_pending_r; +reg csrbank1_sram_reader_ev_pending_re = 1'd0; +wire csrbank1_sram_reader_ev_pending_w; +reg csrbank1_sram_reader_ev_pending_we = 1'd0; +wire csrbank1_sram_reader_ev_status_r; +reg csrbank1_sram_reader_ev_status_re = 1'd0; +wire csrbank1_sram_reader_ev_status_w; +reg csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_r; +reg csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_w; +reg csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] csrbank1_sram_reader_level_r; +reg csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] csrbank1_sram_reader_level_w; +reg csrbank1_sram_reader_level_we = 1'd0; +wire csrbank1_sram_reader_ready_r; +reg csrbank1_sram_reader_ready_re = 1'd0; +wire csrbank1_sram_reader_ready_w; +reg csrbank1_sram_reader_ready_we = 1'd0; +wire csrbank1_sram_reader_slot0_r; +reg csrbank1_sram_reader_slot0_re = 1'd0; +wire csrbank1_sram_reader_slot0_w; +reg csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_r; +reg csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_w; +reg csrbank1_sram_writer_errors_we = 1'd0; +wire csrbank1_sram_writer_ev_enable0_r; +reg csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire csrbank1_sram_writer_ev_enable0_w; +reg csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire csrbank1_sram_writer_ev_pending_r; +reg csrbank1_sram_writer_ev_pending_re = 1'd0; +wire csrbank1_sram_writer_ev_pending_w; +reg csrbank1_sram_writer_ev_pending_we = 1'd0; +wire csrbank1_sram_writer_ev_status_r; +reg csrbank1_sram_writer_ev_status_re = 1'd0; +wire csrbank1_sram_writer_ev_status_w; +reg csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_writer_length_r; +reg csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] csrbank1_sram_writer_length_w; +reg csrbank1_sram_writer_length_we = 1'd0; +wire csrbank1_sram_writer_slot_r; +reg csrbank1_sram_writer_slot_re = 1'd0; +wire csrbank1_sram_writer_slot_w; +reg csrbank1_sram_writer_slot_we = 1'd0; +wire csrbank2_crg_reset0_r; +reg csrbank2_crg_reset0_re = 1'd0; +wire csrbank2_crg_reset0_w; +reg csrbank2_crg_reset0_we = 1'd0; +wire csrbank2_mdio_r_r; +reg csrbank2_mdio_r_re = 1'd0; +wire csrbank2_mdio_r_w; +reg csrbank2_mdio_r_we = 1'd0; +wire [2:0] csrbank2_mdio_w0_r; +reg csrbank2_mdio_w0_re = 1'd0; +wire [2:0] csrbank2_mdio_w0_w; +reg csrbank2_mdio_w0_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire done; +reg error = 1'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire grant; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; +wire interface2_bank_bus_we; +reg [1:0] liteethmacsramreader_next_state = 2'd0; +reg [1:0] liteethmacsramreader_state = 2'd0; +reg [2:0] liteethmacsramwriter_next_state = 3'd0; +reg [2:0] liteethmacsramwriter_state = 3'd0; +reg maccore__r_re = 1'd0; +reg maccore__r_status = 1'd0; +wire maccore__r_we; +reg maccore__w_re = 1'd0; +reg [2:0] maccore__w_storage = 3'd0; +wire maccore_bus_error; +reg [31:0] maccore_bus_errors = 32'd0; +reg maccore_bus_errors_re = 1'd0; +wire [31:0] maccore_bus_errors_status; +wire maccore_bus_errors_we; +wire maccore_cpu_rst; +reg [8:0] maccore_crg_counter = 9'd0; +wire maccore_crg_counter_ce; +wire maccore_crg_counter_done; +wire maccore_crg_reset0; +wire maccore_crg_reset1; +reg maccore_crg_reset_re = 1'd0; +reg maccore_crg_reset_storage = 1'd0; +wire maccore_data_oe; +wire maccore_data_r; +wire maccore_data_w; +reg maccore_int_rst = 1'd1; +reg maccore_liteethphymiirx_converter_demux = 1'd0; +wire maccore_liteethphymiirx_converter_load_part; +reg maccore_liteethphymiirx_converter_sink_first = 1'd0; +wire maccore_liteethphymiirx_converter_sink_last; +reg [3:0] maccore_liteethphymiirx_converter_sink_payload_data = 4'd0; +wire maccore_liteethphymiirx_converter_sink_ready; +reg maccore_liteethphymiirx_converter_sink_valid = 1'd0; +reg maccore_liteethphymiirx_converter_source_first = 1'd0; +reg maccore_liteethphymiirx_converter_source_last = 1'd0; +reg [7:0] maccore_liteethphymiirx_converter_source_payload_data = 8'd0; +reg [1:0] maccore_liteethphymiirx_converter_source_payload_valid_token_count = 2'd0; +wire maccore_liteethphymiirx_converter_source_ready; +wire maccore_liteethphymiirx_converter_source_valid; +reg maccore_liteethphymiirx_converter_strobe_all = 1'd0; +reg maccore_liteethphymiirx_reset = 1'd0; +wire maccore_liteethphymiirx_source_first; +wire maccore_liteethphymiirx_source_last; +wire [7:0] maccore_liteethphymiirx_source_payload_data; +reg maccore_liteethphymiirx_source_payload_error = 1'd0; +reg maccore_liteethphymiirx_source_payload_last_be = 1'd0; +wire maccore_liteethphymiirx_source_ready; +wire maccore_liteethphymiirx_source_source_first; +wire maccore_liteethphymiirx_source_source_last; +wire [7:0] maccore_liteethphymiirx_source_source_payload_data; +wire maccore_liteethphymiirx_source_source_ready; +wire maccore_liteethphymiirx_source_source_valid; +wire maccore_liteethphymiirx_source_valid; +wire maccore_liteethphymiitx_converter_first; +wire maccore_liteethphymiitx_converter_last; +reg maccore_liteethphymiitx_converter_mux = 1'd0; +reg maccore_liteethphymiitx_converter_sink_first = 1'd0; +reg maccore_liteethphymiitx_converter_sink_last = 1'd0; +wire [7:0] maccore_liteethphymiitx_converter_sink_payload_data; +wire maccore_liteethphymiitx_converter_sink_ready; +wire maccore_liteethphymiitx_converter_sink_valid; +wire maccore_liteethphymiitx_converter_source_first; +wire maccore_liteethphymiitx_converter_source_last; +reg [3:0] maccore_liteethphymiitx_converter_source_payload_data = 4'd0; +wire maccore_liteethphymiitx_converter_source_payload_valid_token_count; +wire maccore_liteethphymiitx_converter_source_ready; +wire maccore_liteethphymiitx_converter_source_valid; +wire maccore_liteethphymiitx_sink_first; +wire maccore_liteethphymiitx_sink_last; +wire [7:0] maccore_liteethphymiitx_sink_payload_data; +wire maccore_liteethphymiitx_sink_payload_error; +wire maccore_liteethphymiitx_sink_payload_last_be; +wire maccore_liteethphymiitx_sink_ready; +wire maccore_liteethphymiitx_sink_valid; +wire maccore_liteethphymiitx_source_source_first; +wire maccore_liteethphymiitx_source_source_last; +wire [3:0] maccore_liteethphymiitx_source_source_payload_data; +wire maccore_liteethphymiitx_source_source_ready; +wire maccore_liteethphymiitx_source_source_valid; +wire maccore_mdc; +wire maccore_oe; +reg maccore_r = 1'd0; +reg maccore_reset_re = 1'd0; +reg [1:0] maccore_reset_storage = 2'd0; +reg maccore_scratch_re = 1'd0; +reg [31:0] maccore_scratch_storage = 32'd305419896; +reg maccore_soc_rst = 1'd0; +wire maccore_w; +reg next_state = 1'd0; +wire por_clk; +wire re; +wire request; +wire rst_meta0; +wire rst_meta1; +reg [1:0] rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] rxdatapath_bufferizeendpoints_state = 2'd0; +reg rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] self0 = 30'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [29:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg [2:0] slave_sel = 3'd0; +reg [2:0] slave_sel_r = 3'd0; +reg state = 1'd0; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; +reg [1:0] txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] txdatapath_bufferizeendpoints_state = 2'd0; +reg txdatapath_liteethmacgap_next_state = 1'd0; +reg txdatapath_liteethmacgap_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg txdatapath_liteethmactxlastbe_state = 1'd0; +wire wait_1; +wire wb_bus_ack; +wire [29:0] wb_bus_adr; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; +wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; +wire [3:0] wb_bus_sel; +wire wb_bus_stb; +wire wb_bus_we; +wire we; +wire wishbone_interface_bus_rx_ack; +wire [29:0] wishbone_interface_bus_rx_adr; +wire [1:0] wishbone_interface_bus_rx_bte; +wire [2:0] wishbone_interface_bus_rx_cti; +wire wishbone_interface_bus_rx_cyc; +wire [31:0] wishbone_interface_bus_rx_dat_r; +wire [31:0] wishbone_interface_bus_rx_dat_w; +wire wishbone_interface_bus_rx_err; +wire [3:0] wishbone_interface_bus_rx_sel; +wire wishbone_interface_bus_rx_stb; +wire wishbone_interface_bus_rx_we; +wire wishbone_interface_bus_tx_ack; +wire [29:0] wishbone_interface_bus_tx_adr; +wire [1:0] wishbone_interface_bus_tx_bte; +wire [2:0] wishbone_interface_bus_tx_cti; +wire wishbone_interface_bus_tx_cyc; +wire [31:0] wishbone_interface_bus_tx_dat_r; +wire [31:0] wishbone_interface_bus_tx_dat_w; +wire wishbone_interface_bus_tx_err; +wire [3:0] wishbone_interface_bus_tx_sel; +wire wishbone_interface_bus_tx_stb; +wire wishbone_interface_bus_tx_we; +reg [1:0] wishbone_interface_decoder0_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder0_slave_sel_r = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel_r = 2'd0; +wire wishbone_interface_ev_irq; +reg wishbone_interface_interface0_ack = 1'd0; +wire [29:0] wishbone_interface_interface0_adr; +wire [1:0] wishbone_interface_interface0_bte; +wire [2:0] wishbone_interface_interface0_cti; +wire wishbone_interface_interface0_cyc; +wire [31:0] wishbone_interface_interface0_dat_r; +wire [31:0] wishbone_interface_interface0_dat_w; +reg wishbone_interface_interface0_err = 1'd0; +wire [3:0] wishbone_interface_interface0_sel; +wire wishbone_interface_interface0_stb; +wire wishbone_interface_interface0_we; +reg wishbone_interface_interface1_ack = 1'd0; +wire [29:0] wishbone_interface_interface1_adr; +wire [1:0] wishbone_interface_interface1_bte; +wire [2:0] wishbone_interface_interface1_cti; +wire wishbone_interface_interface1_cyc; +wire [31:0] wishbone_interface_interface1_dat_r; +wire [31:0] wishbone_interface_interface1_dat_w; +reg wishbone_interface_interface1_err = 1'd0; +wire [3:0] wishbone_interface_interface1_sel; +wire wishbone_interface_interface1_stb; +wire wishbone_interface_interface1_we; +reg wishbone_interface_interface2_ack = 1'd0; +wire [29:0] wishbone_interface_interface2_adr; +wire [1:0] wishbone_interface_interface2_bte; +wire [2:0] wishbone_interface_interface2_cti; +wire wishbone_interface_interface2_cyc; +wire [31:0] wishbone_interface_interface2_dat_r; +wire [31:0] wishbone_interface_interface2_dat_w; +reg wishbone_interface_interface2_err = 1'd0; +wire [3:0] wishbone_interface_interface2_sel; +wire wishbone_interface_interface2_stb; +wire wishbone_interface_interface2_we; +reg wishbone_interface_interface3_ack = 1'd0; +wire [29:0] wishbone_interface_interface3_adr; +wire [1:0] wishbone_interface_interface3_bte; +wire [2:0] wishbone_interface_interface3_cti; +wire wishbone_interface_interface3_cyc; +wire [31:0] wishbone_interface_interface3_dat_r; +wire [31:0] wishbone_interface_interface3_dat_w; +reg wishbone_interface_interface3_err = 1'd0; +wire [3:0] wishbone_interface_interface3_sel; +wire wishbone_interface_interface3_stb; +wire wishbone_interface_interface3_we; +reg wishbone_interface_reader_cmd_fifo_consume = 1'd0; +wire wishbone_interface_reader_cmd_fifo_do_read; +wire wishbone_interface_reader_cmd_fifo_fifo_in_first; +wire wishbone_interface_reader_cmd_fifo_fifo_in_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_in_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot; +wire wishbone_interface_reader_cmd_fifo_fifo_out_first; +wire wishbone_interface_reader_cmd_fifo_fifo_out_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_reader_cmd_fifo_level = 2'd0; +reg wishbone_interface_reader_cmd_fifo_produce = 1'd0; +wire wishbone_interface_reader_cmd_fifo_rdport_adr; +wire [13:0] wishbone_interface_reader_cmd_fifo_rdport_dat_r; +reg wishbone_interface_reader_cmd_fifo_replace = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_first = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_last = 1'd0; +wire [10:0] wishbone_interface_reader_cmd_fifo_sink_payload_length; +wire wishbone_interface_reader_cmd_fifo_sink_payload_slot; +wire wishbone_interface_reader_cmd_fifo_sink_ready; +wire wishbone_interface_reader_cmd_fifo_sink_valid; +wire wishbone_interface_reader_cmd_fifo_source_first; +wire wishbone_interface_reader_cmd_fifo_source_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_source_payload_length; +wire wishbone_interface_reader_cmd_fifo_source_payload_slot; +reg wishbone_interface_reader_cmd_fifo_source_ready = 1'd0; +wire wishbone_interface_reader_cmd_fifo_source_valid; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_din; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_dout; +wire wishbone_interface_reader_cmd_fifo_syncfifo_re; +wire wishbone_interface_reader_cmd_fifo_syncfifo_readable; +wire wishbone_interface_reader_cmd_fifo_syncfifo_we; +wire wishbone_interface_reader_cmd_fifo_syncfifo_writable; +reg wishbone_interface_reader_cmd_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_w; +wire wishbone_interface_reader_cmd_fifo_wrport_we; +reg wishbone_interface_reader_enable_re = 1'd0; +reg wishbone_interface_reader_enable_storage = 1'd0; +wire wishbone_interface_reader_event00; +wire wishbone_interface_reader_event01; +wire wishbone_interface_reader_event02; +reg wishbone_interface_reader_eventsourcepulse_clear = 1'd0; +reg wishbone_interface_reader_eventsourcepulse_pending = 1'd0; +wire wishbone_interface_reader_eventsourcepulse_status; +reg wishbone_interface_reader_eventsourcepulse_trigger = 1'd0; +wire wishbone_interface_reader_irq; +reg [10:0] wishbone_interface_reader_length = 11'd0; +reg [10:0] wishbone_interface_reader_length_liteethmacsramreader_next_value = 11'd0; +reg wishbone_interface_reader_length_liteethmacsramreader_next_value_ce = 1'd0; +reg wishbone_interface_reader_length_re = 1'd0; +reg [10:0] wishbone_interface_reader_length_storage = 11'd0; +reg wishbone_interface_reader_level_re = 1'd0; +wire [1:0] wishbone_interface_reader_level_status; +wire wishbone_interface_reader_level_we; +wire [8:0] wishbone_interface_reader_memory0_adr; +wire [31:0] wishbone_interface_reader_memory0_dat_r; +wire wishbone_interface_reader_memory0_re; +wire [8:0] wishbone_interface_reader_memory1_adr; +wire [31:0] wishbone_interface_reader_memory1_dat_r; +wire wishbone_interface_reader_memory1_re; +reg wishbone_interface_reader_pending_r = 1'd0; +reg wishbone_interface_reader_pending_re = 1'd0; +wire wishbone_interface_reader_pending_status; +wire wishbone_interface_reader_pending_we; +reg [31:0] wishbone_interface_reader_rd_data = 32'd0; +reg wishbone_interface_reader_read = 1'd0; +reg wishbone_interface_reader_ready_re = 1'd0; +wire wishbone_interface_reader_ready_status; +wire wishbone_interface_reader_ready_we; +reg wishbone_interface_reader_slot_re = 1'd0; +reg wishbone_interface_reader_slot_storage = 1'd0; +reg wishbone_interface_reader_source_source_first = 1'd0; +reg wishbone_interface_reader_source_source_last = 1'd0; +wire [31:0] wishbone_interface_reader_source_source_payload_data; +reg [3:0] wishbone_interface_reader_source_source_payload_error = 4'd0; +reg [3:0] wishbone_interface_reader_source_source_payload_last_be = 4'd0; +wire wishbone_interface_reader_source_source_ready; +reg wishbone_interface_reader_source_source_valid = 1'd0; +wire wishbone_interface_reader_start_r; +reg wishbone_interface_reader_start_re = 1'd0; +reg wishbone_interface_reader_start_w = 1'd0; +reg wishbone_interface_reader_start_we = 1'd0; +reg wishbone_interface_reader_status_re = 1'd0; +wire wishbone_interface_reader_status_status; +wire wishbone_interface_reader_status_we; +wire wishbone_interface_sink_first; +wire wishbone_interface_sink_last; +wire [31:0] wishbone_interface_sink_payload_data; +wire [3:0] wishbone_interface_sink_payload_error; +wire [3:0] wishbone_interface_sink_payload_last_be; +wire wishbone_interface_sink_ready; +wire wishbone_interface_sink_valid; +wire wishbone_interface_source_first; +wire wishbone_interface_source_last; +wire [31:0] wishbone_interface_source_payload_data; +wire [3:0] wishbone_interface_source_payload_error; +wire [3:0] wishbone_interface_source_payload_last_be; +wire wishbone_interface_source_ready; +wire wishbone_interface_source_valid; +wire [8:0] wishbone_interface_sram0_adr; +reg wishbone_interface_sram0_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram0_dat_r; +wire [8:0] wishbone_interface_sram1_adr; +reg wishbone_interface_sram1_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram1_dat_r; +wire [8:0] wishbone_interface_sram2_adr; +reg wishbone_interface_sram2_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram2_dat_r; +wire [31:0] wishbone_interface_sram2_dat_w; +reg [3:0] wishbone_interface_sram2_we = 4'd0; +wire [8:0] wishbone_interface_sram3_adr; +reg wishbone_interface_sram3_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram3_dat_r; +wire [31:0] wishbone_interface_sram3_dat_w; +reg [3:0] wishbone_interface_sram3_we = 4'd0; +wire wishbone_interface_writer_available0; +wire wishbone_interface_writer_available1; +wire wishbone_interface_writer_available2; +reg wishbone_interface_writer_available_clear = 1'd0; +wire wishbone_interface_writer_available_pending; +wire wishbone_interface_writer_available_status; +wire wishbone_interface_writer_available_trigger; +reg wishbone_interface_writer_enable_re = 1'd0; +reg wishbone_interface_writer_enable_storage = 1'd0; +reg wishbone_interface_writer_errors_re = 1'd0; +reg [31:0] wishbone_interface_writer_errors_status = 32'd0; +reg [31:0] wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value = 32'd0; +reg wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire wishbone_interface_writer_errors_we; +wire wishbone_interface_writer_irq; +reg [10:0] wishbone_interface_writer_length = 11'd0; +reg [3:0] wishbone_interface_writer_length_inc = 4'd0; +reg [10:0] wishbone_interface_writer_length_liteethmacsramwriter_t_next_value = 11'd0; +reg wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg wishbone_interface_writer_length_re = 1'd0; +wire [10:0] wishbone_interface_writer_length_status; +wire wishbone_interface_writer_length_we; +reg [8:0] wishbone_interface_writer_memory0_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory0_dat_r; +reg [31:0] wishbone_interface_writer_memory0_dat_w = 32'd0; +reg wishbone_interface_writer_memory0_we = 1'd0; +reg [8:0] wishbone_interface_writer_memory1_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory1_dat_r; +reg [31:0] wishbone_interface_writer_memory1_dat_w = 32'd0; +reg wishbone_interface_writer_memory1_we = 1'd0; +reg wishbone_interface_writer_pending_r = 1'd0; +reg wishbone_interface_writer_pending_re = 1'd0; +wire wishbone_interface_writer_pending_status; +wire wishbone_interface_writer_pending_we; +wire wishbone_interface_writer_sink_sink_first; +wire wishbone_interface_writer_sink_sink_last; +wire [31:0] wishbone_interface_writer_sink_sink_payload_data; +wire [3:0] wishbone_interface_writer_sink_sink_payload_error; +wire [3:0] wishbone_interface_writer_sink_sink_payload_last_be; +reg wishbone_interface_writer_sink_sink_ready = 1'd1; +wire wishbone_interface_writer_sink_sink_valid; +reg wishbone_interface_writer_slot = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce = 1'd0; +reg wishbone_interface_writer_slot_re = 1'd0; +wire wishbone_interface_writer_slot_status; +wire wishbone_interface_writer_slot_we; +reg wishbone_interface_writer_stat_fifo_consume = 1'd0; +wire wishbone_interface_writer_stat_fifo_do_read; +wire wishbone_interface_writer_stat_fifo_fifo_in_first; +wire wishbone_interface_writer_stat_fifo_fifo_in_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_in_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_in_payload_slot; +wire wishbone_interface_writer_stat_fifo_fifo_out_first; +wire wishbone_interface_writer_stat_fifo_fifo_out_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_writer_stat_fifo_level = 2'd0; +reg wishbone_interface_writer_stat_fifo_produce = 1'd0; +wire wishbone_interface_writer_stat_fifo_rdport_adr; +wire [13:0] wishbone_interface_writer_stat_fifo_rdport_dat_r; +reg wishbone_interface_writer_stat_fifo_replace = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_first = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_last = 1'd0; +reg [10:0] wishbone_interface_writer_stat_fifo_sink_payload_length = 11'd0; +reg wishbone_interface_writer_stat_fifo_sink_payload_slot = 1'd0; +wire wishbone_interface_writer_stat_fifo_sink_ready; +reg wishbone_interface_writer_stat_fifo_sink_valid = 1'd0; +wire wishbone_interface_writer_stat_fifo_source_first; +wire wishbone_interface_writer_stat_fifo_source_last; +wire [10:0] wishbone_interface_writer_stat_fifo_source_payload_length; +wire wishbone_interface_writer_stat_fifo_source_payload_slot; +wire wishbone_interface_writer_stat_fifo_source_ready; +wire wishbone_interface_writer_stat_fifo_source_valid; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_din; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_dout; +wire wishbone_interface_writer_stat_fifo_syncfifo_re; +wire wishbone_interface_writer_stat_fifo_syncfifo_readable; +wire wishbone_interface_writer_stat_fifo_syncfifo_we; +wire wishbone_interface_writer_stat_fifo_syncfifo_writable; +reg wishbone_interface_writer_stat_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_w; +wire wishbone_interface_writer_stat_fifo_wrport_we; +reg wishbone_interface_writer_status_re = 1'd0; +wire wishbone_interface_writer_status_status; +wire wishbone_interface_writer_status_we; +wire [31:0] wishbone_interface_writer_wr_data; +reg wishbone_interface_writer_write = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl00 = 1'd0; +reg xilinxmultiregimpl00 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl01 = 1'd0; +reg xilinxmultiregimpl01 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl10 = 6'd0; +reg [5:0] xilinxmultiregimpl10 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl11 = 6'd0; +reg [5:0] xilinxmultiregimpl11 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +reg [5:0] xilinxmultiregimpl20 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +reg [5:0] xilinxmultiregimpl21 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl30 = 1'd0; +reg xilinxmultiregimpl30 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl31 = 1'd0; +reg xilinxmultiregimpl31 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl40 = 1'd0; +reg xilinxmultiregimpl40 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl41 = 1'd0; +reg xilinxmultiregimpl41 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl50 = 6'd0; +reg [5:0] xilinxmultiregimpl50 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl51 = 6'd0; +reg [5:0] xilinxmultiregimpl51 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +reg [5:0] xilinxmultiregimpl60 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; -(* dont_touch = "true" *) -wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) -wire eth_tx_clk; -wire eth_tx_rst; -wire main_bufferizeendpoints_pipe_valid_sink_first; -wire main_bufferizeendpoints_pipe_valid_sink_last; -wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; -wire main_bufferizeendpoints_pipe_valid_sink_payload_error; -wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; -wire main_bufferizeendpoints_pipe_valid_sink_ready; -wire main_bufferizeendpoints_pipe_valid_sink_valid; -reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; -reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; -wire main_bufferizeendpoints_pipe_valid_source_ready; -reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; -wire main_bufferizeendpoints_sink_sink_first; -wire main_bufferizeendpoints_sink_sink_last; -wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; -wire main_bufferizeendpoints_sink_sink_payload_error; -wire main_bufferizeendpoints_sink_sink_payload_last_be; -wire main_bufferizeendpoints_sink_sink_ready; -wire main_bufferizeendpoints_sink_sink_valid; -wire main_bufferizeendpoints_source_source_first; -wire main_bufferizeendpoints_source_source_last; -wire [7:0] main_bufferizeendpoints_source_source_payload_data; -wire main_bufferizeendpoints_source_source_payload_error; -wire main_bufferizeendpoints_source_source_payload_last_be; -wire main_bufferizeendpoints_source_source_ready; -wire main_bufferizeendpoints_source_source_valid; -wire main_bus_ack; -wire [29:0] main_bus_adr; -wire [1:0] main_bus_bte; -wire [2:0] main_bus_cti; -wire main_bus_cyc; -wire [31:0] main_bus_dat_r; -wire [31:0] main_bus_dat_w; -wire main_bus_err; -wire [3:0] main_bus_sel; -wire main_bus_stb; -wire main_bus_we; -reg main_crc_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_interface0_ack = 1'd0; -wire [29:0] main_interface0_adr; -wire [1:0] main_interface0_bte; -wire [2:0] main_interface0_cti; -wire main_interface0_cyc; -wire [31:0] main_interface0_dat_r; -wire [31:0] main_interface0_dat_w; -reg main_interface0_err = 1'd0; -wire [3:0] main_interface0_sel; -wire main_interface0_stb; -wire main_interface0_we; -reg main_interface1_ack = 1'd0; -wire [29:0] main_interface1_adr; -wire [1:0] main_interface1_bte; -wire [2:0] main_interface1_cti; -wire main_interface1_cyc; -wire [31:0] main_interface1_dat_r; -wire [31:0] main_interface1_dat_w; -reg main_interface1_err = 1'd0; -wire [3:0] main_interface1_sel; -wire main_interface1_stb; -wire main_interface1_we; -reg main_interface2_ack = 1'd0; -wire [29:0] main_interface2_adr; -wire [1:0] main_interface2_bte; -wire [2:0] main_interface2_cti; -wire main_interface2_cyc; -wire [31:0] main_interface2_dat_r; -wire [31:0] main_interface2_dat_w; -reg main_interface2_err = 1'd0; -wire [3:0] main_interface2_sel; -wire main_interface2_stb; -wire main_interface2_we; -reg main_interface3_ack = 1'd0; -wire [29:0] main_interface3_adr; -wire [1:0] main_interface3_bte; -wire [2:0] main_interface3_cti; -wire main_interface3_cyc; -wire [31:0] main_interface3_dat_r; -wire [31:0] main_interface3_dat_w; -reg main_interface3_err = 1'd0; -wire [3:0] main_interface3_sel; -wire main_interface3_stb; -wire main_interface3_we; -reg [3:0] main_length_inc = 4'd0; -wire main_liteethmaccrc32checker_crc_be; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; -wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -reg main_liteethmaccrc32checker_crc_error0 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; -reg main_liteethmaccrc32checker_error = 1'd0; -wire main_liteethmaccrc32checker_fifo_full; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -reg main_liteethmaccrc32checker_last_be = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -wire main_liteethmaccrc32checker_source_source_first; -reg main_liteethmaccrc32checker_source_source_last = 1'd0; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_valid = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -reg main_maccore__r_re = 1'd0; -reg main_maccore__r_status = 1'd0; -wire main_maccore__r_we; -reg main_maccore__w_re = 1'd0; -reg [2:0] main_maccore__w_storage = 3'd0; -wire main_maccore_bus_error; -reg [31:0] main_maccore_bus_errors = 32'd0; -reg main_maccore_bus_errors_re = 1'd0; -wire [31:0] main_maccore_bus_errors_status; -wire main_maccore_bus_errors_we; -wire main_maccore_cpu_rst; -reg [8:0] main_maccore_crg_counter = 9'd0; -wire main_maccore_crg_counter_ce; -wire main_maccore_crg_counter_done; -wire main_maccore_crg_reset0; -wire main_maccore_crg_reset1; -reg main_maccore_crg_reset_re = 1'd0; -reg main_maccore_crg_reset_storage = 1'd0; -wire main_maccore_data_oe; -wire main_maccore_data_r; -wire main_maccore_data_w; -reg main_maccore_int_rst = 1'd1; -reg main_maccore_liteethphymiirx_converter_demux = 1'd0; -wire main_maccore_liteethphymiirx_converter_load_part; -reg main_maccore_liteethphymiirx_converter_sink_first = 1'd0; -wire main_maccore_liteethphymiirx_converter_sink_last; -reg [3:0] main_maccore_liteethphymiirx_converter_sink_payload_data = 4'd0; -wire main_maccore_liteethphymiirx_converter_sink_ready; -reg main_maccore_liteethphymiirx_converter_sink_valid = 1'd0; -reg main_maccore_liteethphymiirx_converter_source_first = 1'd0; -reg main_maccore_liteethphymiirx_converter_source_last = 1'd0; -reg [7:0] main_maccore_liteethphymiirx_converter_source_payload_data = 8'd0; -reg [1:0] main_maccore_liteethphymiirx_converter_source_payload_valid_token_count = 2'd0; -wire main_maccore_liteethphymiirx_converter_source_ready; -wire main_maccore_liteethphymiirx_converter_source_valid; -reg main_maccore_liteethphymiirx_converter_strobe_all = 1'd0; -reg main_maccore_liteethphymiirx_reset = 1'd0; -wire main_maccore_liteethphymiirx_source_first; -wire main_maccore_liteethphymiirx_source_last; -wire [7:0] main_maccore_liteethphymiirx_source_payload_data; -reg main_maccore_liteethphymiirx_source_payload_error = 1'd0; -reg main_maccore_liteethphymiirx_source_payload_last_be = 1'd0; -wire main_maccore_liteethphymiirx_source_ready; -wire main_maccore_liteethphymiirx_source_source_first; -wire main_maccore_liteethphymiirx_source_source_last; -wire [7:0] main_maccore_liteethphymiirx_source_source_payload_data; -wire main_maccore_liteethphymiirx_source_source_ready; -wire main_maccore_liteethphymiirx_source_source_valid; -wire main_maccore_liteethphymiirx_source_valid; -wire main_maccore_liteethphymiitx_converter_first; -wire main_maccore_liteethphymiitx_converter_last; -reg main_maccore_liteethphymiitx_converter_mux = 1'd0; -reg main_maccore_liteethphymiitx_converter_sink_first = 1'd0; -reg main_maccore_liteethphymiitx_converter_sink_last = 1'd0; -wire [7:0] main_maccore_liteethphymiitx_converter_sink_payload_data; -wire main_maccore_liteethphymiitx_converter_sink_ready; -wire main_maccore_liteethphymiitx_converter_sink_valid; -wire main_maccore_liteethphymiitx_converter_source_first; -wire main_maccore_liteethphymiitx_converter_source_last; -reg [3:0] main_maccore_liteethphymiitx_converter_source_payload_data = 4'd0; -wire main_maccore_liteethphymiitx_converter_source_payload_valid_token_count; -wire main_maccore_liteethphymiitx_converter_source_ready; -wire main_maccore_liteethphymiitx_converter_source_valid; -wire main_maccore_liteethphymiitx_sink_first; -wire main_maccore_liteethphymiitx_sink_last; -wire [7:0] main_maccore_liteethphymiitx_sink_payload_data; -wire main_maccore_liteethphymiitx_sink_payload_error; -wire main_maccore_liteethphymiitx_sink_payload_last_be; -wire main_maccore_liteethphymiitx_sink_ready; -wire main_maccore_liteethphymiitx_sink_valid; -wire main_maccore_liteethphymiitx_source_source_first; -wire main_maccore_liteethphymiitx_source_source_last; -wire [3:0] main_maccore_liteethphymiitx_source_source_payload_data; -wire main_maccore_liteethphymiitx_source_source_ready; -wire main_maccore_liteethphymiitx_source_source_valid; -wire main_maccore_mdc; -wire main_maccore_oe; -reg main_maccore_r = 1'd0; -reg main_maccore_reset_re = 1'd0; -reg [1:0] main_maccore_reset_storage = 2'd0; -reg main_maccore_scratch_re = 1'd0; -reg [31:0] main_maccore_scratch_storage = 32'd305419896; -reg main_maccore_soc_rst = 1'd0; -wire main_maccore_w; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -wire main_pulsesynchronizer0_i; -wire main_pulsesynchronizer0_o; -reg main_pulsesynchronizer0_toggle_i = 1'd0; -wire main_pulsesynchronizer0_toggle_o; -reg main_pulsesynchronizer0_toggle_o_r = 1'd0; -wire main_pulsesynchronizer1_i; -wire main_pulsesynchronizer1_o; -reg main_pulsesynchronizer1_toggle_i = 1'd0; -wire main_pulsesynchronizer1_toggle_o; -reg main_pulsesynchronizer1_toggle_o_r = 1'd0; -reg [31:0] main_rd_data = 32'd0; -reg main_re = 1'd0; -reg main_read = 1'd0; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_valid; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire main_rx_cdc_cdc_wrport_we; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_valid; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_valid; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -wire main_rx_converter_converter_source_ready; -wire main_rx_converter_converter_source_valid; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_valid; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_valid; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -wire main_rx_last_be_source_payload_error; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_valid; -wire main_rx_padding_sink_first; -wire main_rx_padding_sink_last; -wire [7:0] main_rx_padding_sink_payload_data; -wire main_rx_padding_sink_payload_error; -wire main_rx_padding_sink_payload_last_be; -wire main_rx_padding_sink_ready; -wire main_rx_padding_sink_valid; -wire main_rx_padding_source_first; -wire main_rx_padding_source_last; -wire [7:0] main_rx_padding_source_payload_data; -wire main_rx_padding_source_payload_error; -wire main_rx_padding_source_payload_last_be; -wire main_rx_padding_source_ready; -wire main_rx_padding_source_valid; -reg main_rx_preamble_error = 1'd0; -reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; -wire main_rx_preamble_sink_first; -wire main_rx_preamble_sink_last; -wire [7:0] main_rx_preamble_sink_payload_data; -wire main_rx_preamble_sink_payload_error; -wire main_rx_preamble_sink_payload_last_be; -reg main_rx_preamble_sink_ready = 1'd0; -wire main_rx_preamble_sink_valid; -reg main_rx_preamble_source_first = 1'd0; -reg main_rx_preamble_source_last = 1'd0; -wire [7:0] main_rx_preamble_source_payload_data; -reg main_rx_preamble_source_payload_error = 1'd0; -wire main_rx_preamble_source_payload_last_be; -wire main_rx_preamble_source_ready; -reg main_rx_preamble_source_valid = 1'd0; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_error; -wire [3:0] main_sink_payload_last_be; -wire main_sink_ready; -wire main_sink_sink_first; -wire main_sink_sink_last; -wire [31:0] main_sink_sink_payload_data; -wire [3:0] main_sink_sink_payload_error; -wire [3:0] main_sink_sink_payload_last_be; -wire main_sink_sink_ready; -wire main_sink_sink_valid; -wire main_sink_valid; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -reg main_slot = 1'd0; -reg main_slot_liteethmacsramwriter_next_value = 1'd0; -reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_error; -wire [3:0] main_source_payload_last_be; -wire main_source_ready; -wire main_source_source_first; -wire main_source_source_last; -wire [31:0] main_source_source_payload_data; -wire [3:0] main_source_source_payload_error; -wire [3:0] main_source_source_payload_last_be; -wire main_source_source_ready; -wire main_source_source_valid; -wire main_source_valid; -wire [8:0] main_sram0_adr; -reg main_sram0_adr_burst = 1'd0; -wire [31:0] main_sram0_dat_r; -wire main_sram0_sink_valid; -reg main_sram100_storage = 1'd0; -reg main_sram101_re = 1'd0; -reg [10:0] main_sram102_storage = 11'd0; -reg main_sram103_re = 1'd0; -wire main_sram104_irq; -wire main_sram105_status; -reg main_sram106_pending = 1'd0; -reg main_sram107_trigger = 1'd0; -reg main_sram108_clear = 1'd0; -wire main_sram109_event0; -wire [10:0] main_sram10_status; -reg main_sram110_status = 1'd0; -wire main_sram111_we; -reg main_sram112_re = 1'd0; -wire main_sram113_event0; -reg main_sram114_status = 1'd0; -wire main_sram115_we; -reg main_sram116_re = 1'd0; -reg main_sram117_r = 1'd0; -wire main_sram118_event0; -reg main_sram119_storage = 1'd0; -wire main_sram11_we; -reg main_sram120_re = 1'd0; -reg [10:0] main_sram122_length = 11'd0; -reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; -reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; -wire main_sram123_sink_valid; -wire main_sram124_sink_ready; -reg main_sram125_sink_first = 1'd0; -reg main_sram126_sink_last = 1'd0; -wire main_sram127_sink_payload_slot; -wire [10:0] main_sram128_sink_payload_length; -wire main_sram129_source_valid; -reg main_sram12_re = 1'd0; -reg main_sram130_source_ready = 1'd0; -wire main_sram131_source_first; -wire main_sram132_source_last; -wire main_sram133_source_payload_slot; -wire [10:0] main_sram134_source_payload_length; -wire main_sram135_we; -wire main_sram136_writable; -wire main_sram137_re; -wire main_sram138_readable; -wire [13:0] main_sram139_din; -reg [31:0] main_sram13_status = 32'd0; -reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; -reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; -wire [13:0] main_sram140_dout; -reg [1:0] main_sram141_level = 2'd0; -reg main_sram142_replace = 1'd0; -reg main_sram143_produce = 1'd0; -reg main_sram144_consume = 1'd0; -reg main_sram145_adr = 1'd0; -wire [13:0] main_sram146_dat_r; -wire main_sram147_we; -wire [13:0] main_sram148_dat_w; -wire main_sram149_do_read; -wire main_sram14_we; -wire main_sram150_adr; -wire [13:0] main_sram151_dat_r; -wire main_sram152_fifo_in_payload_slot; -wire [10:0] main_sram153_fifo_in_payload_length; -wire main_sram154_fifo_in_first; -wire main_sram155_fifo_in_last; -wire main_sram156_fifo_out_payload_slot; -wire [10:0] main_sram157_fifo_out_payload_length; -wire main_sram158_fifo_out_first; -wire main_sram159_fifo_out_last; -reg main_sram15_re = 1'd0; -wire [8:0] main_sram161_adr; -wire [31:0] main_sram162_dat_r; -wire main_sram163_re; -wire [8:0] main_sram164_adr; -wire [31:0] main_sram165_dat_r; -wire main_sram166_re; -wire main_sram167_irq; -wire main_sram16_irq; -wire main_sram17_status; -wire main_sram18_pending; -wire main_sram19_trigger; -wire [8:0] main_sram1_adr; -reg main_sram1_adr_burst = 1'd0; -wire [31:0] main_sram1_dat_r; -reg main_sram1_sink_ready = 1'd1; -reg main_sram20_clear = 1'd0; -wire main_sram21_available; -reg main_sram22_status = 1'd0; -wire main_sram23_we; -reg main_sram24_re = 1'd0; -wire main_sram25_available; -reg main_sram26_status = 1'd0; -wire main_sram27_we; -reg main_sram28_re = 1'd0; -reg main_sram29_r = 1'd0; -wire [8:0] main_sram2_adr; -reg main_sram2_adr_burst = 1'd0; -wire [31:0] main_sram2_dat_r; -wire [31:0] main_sram2_dat_w; -wire main_sram2_sink_first; -reg [3:0] main_sram2_we = 4'd0; -wire main_sram30_available; -reg main_sram31_storage = 1'd0; -reg main_sram32_re = 1'd0; -reg [10:0] main_sram35_length = 11'd0; -reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; -reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; -reg main_sram37_sink_valid = 1'd0; -wire main_sram38_sink_ready; -reg main_sram39_sink_first = 1'd0; -wire [8:0] main_sram3_adr; -reg main_sram3_adr_burst = 1'd0; -wire [31:0] main_sram3_dat_r; -wire [31:0] main_sram3_dat_w; -wire main_sram3_sink_last; -reg [3:0] main_sram3_we = 4'd0; -reg main_sram40_sink_last = 1'd0; -reg main_sram41_sink_payload_slot = 1'd0; -reg [10:0] main_sram42_sink_payload_length = 11'd0; -wire main_sram43_source_valid; -wire main_sram44_source_ready; -wire main_sram45_source_first; -wire main_sram46_source_last; -wire main_sram47_source_payload_slot; -wire [10:0] main_sram48_source_payload_length; -wire main_sram49_we; -wire [31:0] main_sram4_sink_payload_data; -wire main_sram50_writable; -wire main_sram51_re; -wire main_sram52_readable; -wire [13:0] main_sram53_din; -wire [13:0] main_sram54_dout; -reg [1:0] main_sram55_level = 2'd0; -reg main_sram56_replace = 1'd0; -reg main_sram57_produce = 1'd0; -reg main_sram58_consume = 1'd0; -reg main_sram59_adr = 1'd0; -wire [3:0] main_sram5_sink_payload_last_be; -wire [13:0] main_sram60_dat_r; -wire main_sram61_we; -wire [13:0] main_sram62_dat_w; -wire main_sram63_do_read; -wire main_sram64_adr; -wire [13:0] main_sram65_dat_r; -wire main_sram66_fifo_in_payload_slot; -wire [10:0] main_sram67_fifo_in_payload_length; -wire main_sram68_fifo_in_first; -wire main_sram69_fifo_in_last; -wire [3:0] main_sram6_sink_payload_error; -wire main_sram70_fifo_out_payload_slot; -wire [10:0] main_sram71_fifo_out_payload_length; -wire main_sram72_fifo_out_first; -wire main_sram73_fifo_out_last; -reg [8:0] main_sram75_adr = 9'd0; -wire [31:0] main_sram76_dat_r; -reg main_sram77_we = 1'd0; -reg [31:0] main_sram78_dat_w = 32'd0; -reg [8:0] main_sram79_adr = 9'd0; -wire main_sram7_status; -wire [31:0] main_sram80_dat_r; -reg main_sram81_we = 1'd0; -reg [31:0] main_sram82_dat_w = 32'd0; -reg main_sram83_source_valid = 1'd0; -wire main_sram84_source_ready; -reg main_sram85_source_first = 1'd0; -reg main_sram86_source_last = 1'd0; -wire [31:0] main_sram87_source_payload_data; -reg [3:0] main_sram88_source_payload_last_be = 4'd0; -reg [3:0] main_sram89_source_payload_error = 4'd0; -wire main_sram8_we; -wire main_sram94_status; -wire main_sram95_we; -reg main_sram96_re = 1'd0; -wire [1:0] main_sram97_status; -wire main_sram98_we; -reg main_sram99_re = 1'd0; -reg main_sram9_re = 1'd0; -wire main_start_r; -reg main_start_re = 1'd0; -reg main_start_w = 1'd0; -reg main_start_we = 1'd0; -reg main_status = 1'd1; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_valid; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire main_tx_cdc_cdc_wrport_we; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_valid; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_error; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_valid; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_valid; -wire main_tx_crc_be; -reg main_tx_crc_ce = 1'd0; -reg [1:0] main_tx_crc_cnt = 2'd3; -wire main_tx_crc_cnt_done; -reg [31:0] main_tx_crc_crc_next = 32'd0; -reg [31:0] main_tx_crc_crc_packet = 32'd0; -reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; -reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; -wire [31:0] main_tx_crc_crc_prev; -wire [7:0] main_tx_crc_data0; -wire [7:0] main_tx_crc_data1; -reg main_tx_crc_error = 1'd0; -reg main_tx_crc_is_ongoing0 = 1'd0; -reg main_tx_crc_is_ongoing1 = 1'd0; -reg main_tx_crc_last_be = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; -wire main_tx_crc_pipe_valid_sink_first; -wire main_tx_crc_pipe_valid_sink_last; -wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; -wire main_tx_crc_pipe_valid_sink_payload_error; -wire main_tx_crc_pipe_valid_sink_payload_last_be; -wire main_tx_crc_pipe_valid_sink_ready; -wire main_tx_crc_pipe_valid_sink_valid; -reg main_tx_crc_pipe_valid_source_first = 1'd0; -reg main_tx_crc_pipe_valid_source_last = 1'd0; -reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; -reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; -reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; -wire main_tx_crc_pipe_valid_source_ready; -reg main_tx_crc_pipe_valid_source_valid = 1'd0; -reg [31:0] main_tx_crc_reg = 32'd4294967295; -reg main_tx_crc_reset = 1'd0; -wire main_tx_crc_sink_first; -wire main_tx_crc_sink_last; -wire [7:0] main_tx_crc_sink_payload_data; -wire main_tx_crc_sink_payload_error; -wire main_tx_crc_sink_payload_last_be; -reg main_tx_crc_sink_ready = 1'd0; -wire main_tx_crc_sink_sink_first; -wire main_tx_crc_sink_sink_last; -wire [7:0] main_tx_crc_sink_sink_payload_data; -wire main_tx_crc_sink_sink_payload_error; -wire main_tx_crc_sink_sink_payload_last_be; -wire main_tx_crc_sink_sink_ready; -wire main_tx_crc_sink_sink_valid; -wire main_tx_crc_sink_valid; -reg main_tx_crc_source_first = 1'd0; -reg main_tx_crc_source_last = 1'd0; -reg [7:0] main_tx_crc_source_payload_data = 8'd0; -reg main_tx_crc_source_payload_error = 1'd0; -reg main_tx_crc_source_payload_last_be = 1'd0; -wire main_tx_crc_source_ready; -wire main_tx_crc_source_source_first; -wire main_tx_crc_source_source_last; -wire [7:0] main_tx_crc_source_source_payload_data; -wire main_tx_crc_source_source_payload_error; -wire main_tx_crc_source_source_payload_last_be; -wire main_tx_crc_source_source_ready; -wire main_tx_crc_source_source_valid; -reg main_tx_crc_source_valid = 1'd0; -reg [31:0] main_tx_crc_value = 32'd0; -reg [3:0] main_tx_gap_counter = 4'd0; -reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; -reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; -wire main_tx_gap_sink_first; -wire main_tx_gap_sink_last; -wire [7:0] main_tx_gap_sink_payload_data; -wire main_tx_gap_sink_payload_error; -wire main_tx_gap_sink_payload_last_be; -reg main_tx_gap_sink_ready = 1'd0; -wire main_tx_gap_sink_valid; -reg main_tx_gap_source_first = 1'd0; -reg main_tx_gap_source_last = 1'd0; -reg [7:0] main_tx_gap_source_payload_data = 8'd0; -reg main_tx_gap_source_payload_error = 1'd0; -reg main_tx_gap_source_payload_last_be = 1'd0; -wire main_tx_gap_source_ready; -reg main_tx_gap_source_valid = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_error; -wire main_tx_last_be_sink_payload_last_be; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_valid = 1'd0; -reg [15:0] main_tx_padding_counter = 16'd0; -reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; -reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; -wire main_tx_padding_counter_done; -wire main_tx_padding_sink_first; -wire main_tx_padding_sink_last; -wire [7:0] main_tx_padding_sink_payload_data; -wire main_tx_padding_sink_payload_error; -wire main_tx_padding_sink_payload_last_be; -reg main_tx_padding_sink_ready = 1'd0; -wire main_tx_padding_sink_valid; -reg main_tx_padding_source_first = 1'd0; -reg main_tx_padding_source_last = 1'd0; -reg [7:0] main_tx_padding_source_payload_data = 8'd0; -reg main_tx_padding_source_payload_error = 1'd0; -reg main_tx_padding_source_payload_last_be = 1'd0; -wire main_tx_padding_source_ready; -reg main_tx_padding_source_valid = 1'd0; -reg [2:0] main_tx_preamble_count = 3'd0; -reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; -reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; -reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; -wire main_tx_preamble_sink_first; -wire main_tx_preamble_sink_last; -wire [7:0] main_tx_preamble_sink_payload_data; -wire main_tx_preamble_sink_payload_error; -wire main_tx_preamble_sink_payload_last_be; -reg main_tx_preamble_sink_ready = 1'd0; -wire main_tx_preamble_sink_valid; -reg main_tx_preamble_source_first = 1'd0; -reg main_tx_preamble_source_last = 1'd0; -reg [7:0] main_tx_preamble_source_payload_data = 8'd0; -reg main_tx_preamble_source_payload_error = 1'd0; -wire main_tx_preamble_source_payload_last_be; -wire main_tx_preamble_source_ready; -reg main_tx_preamble_source_valid = 1'd0; -wire main_wb_bus_ack; -wire [29:0] main_wb_bus_adr; -wire [1:0] main_wb_bus_bte; -wire [2:0] main_wb_bus_cti; -wire main_wb_bus_cyc; -wire [31:0] main_wb_bus_dat_r; -wire [31:0] main_wb_bus_dat_w; -wire main_wb_bus_err; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_stb; -wire main_wb_bus_we; -wire main_we; -wire [31:0] main_wr_data; -reg main_write = 1'd0; -wire por_clk; -(* dont_touch = "true" *) -wire sys_clk; -wire sys_rst; +reg [5:0] xilinxmultiregimpl61 = 6'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign main_wb_bus_adr = wishbone_adr; -assign main_wb_bus_dat_w = wishbone_dat_w; -assign wishbone_dat_r = main_wb_bus_dat_r; -assign main_wb_bus_sel = wishbone_sel; -assign main_wb_bus_cyc = wishbone_cyc; -assign main_wb_bus_stb = wishbone_stb; -assign wishbone_ack = main_wb_bus_ack; -assign main_wb_bus_we = wishbone_we; -assign main_wb_bus_cti = wishbone_cti; -assign main_wb_bus_bte = wishbone_bte; -assign wishbone_err = main_wb_bus_err; -assign interrupt = main_sram167_irq; -assign main_maccore_bus_error = builder_error; -assign builder_shared_adr = builder_self0; -assign builder_shared_dat_w = builder_self1; -assign builder_shared_sel = builder_self2; -assign builder_shared_cyc = builder_self3; -assign builder_shared_stb = builder_self4; -assign builder_shared_we = builder_self5; -assign builder_shared_cti = builder_self6; -assign builder_shared_bte = builder_self7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; -always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); -end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_interface0_adr = builder_shared_adr; -assign builder_interface0_dat_w = builder_shared_dat_w; -assign builder_interface0_sel = builder_shared_sel; -assign builder_interface0_stb = builder_shared_stb; -assign builder_interface0_we = builder_shared_we; -assign builder_interface0_cti = builder_shared_cti; -assign builder_interface0_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_interface0_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); -always @(*) begin - builder_error <= 1'd0; - builder_shared_ack <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_interface0_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; - end -end -assign builder_done = (builder_count == 1'd0); -assign main_maccore_bus_errors_status = main_maccore_bus_errors; +assign wb_bus_adr = wishbone_adr; +assign wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wishbone_sel; +assign wb_bus_cyc = wishbone_cyc; +assign wb_bus_stb = wishbone_stb; +assign wishbone_ack = wb_bus_ack; +assign wb_bus_we = wishbone_we; +assign wb_bus_cti = wishbone_cti; +assign wb_bus_bte = wishbone_bte; +assign wishbone_err = wb_bus_err; +assign interrupt = wishbone_interface_ev_irq; +assign maccore_bus_error = error; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign wb_bus_dat_r = shared_dat_r; +assign wb_bus_ack = (shared_ack & (grant == 1'd0)); +assign wb_bus_err = (shared_err & (grant == 1'd0)); +assign request = {wb_bus_cyc}; +assign grant = 1'd0; +always @(*) begin + slave_sel <= 3'd0; + slave_sel[0] <= (shared_adr[29:10] == 5'd16); + slave_sel[1] <= (shared_adr[29:10] == 5'd17); + slave_sel[2] <= (shared_adr[29:14] == 1'd0); +end +assign wishbone_interface_bus_rx_adr = shared_adr; +assign wishbone_interface_bus_rx_dat_w = shared_dat_w; +assign wishbone_interface_bus_rx_sel = shared_sel; +assign wishbone_interface_bus_rx_stb = shared_stb; +assign wishbone_interface_bus_rx_we = shared_we; +assign wishbone_interface_bus_rx_cti = shared_cti; +assign wishbone_interface_bus_rx_bte = shared_bte; +assign wishbone_interface_bus_tx_adr = shared_adr; +assign wishbone_interface_bus_tx_dat_w = shared_dat_w; +assign wishbone_interface_bus_tx_sel = shared_sel; +assign wishbone_interface_bus_tx_stb = shared_stb; +assign wishbone_interface_bus_tx_we = shared_we; +assign wishbone_interface_bus_tx_cti = shared_cti; +assign wishbone_interface_bus_tx_bte = shared_bte; +assign interface0_adr = shared_adr; +assign interface0_dat_w = shared_dat_w; +assign interface0_sel = shared_sel; +assign interface0_stb = shared_stb; +assign interface0_we = shared_we; +assign interface0_cti = shared_cti; +assign interface0_bte = shared_bte; +assign wishbone_interface_bus_rx_cyc = (shared_cyc & slave_sel[0]); +assign wishbone_interface_bus_tx_cyc = (shared_cyc & slave_sel[1]); +assign interface0_cyc = (shared_cyc & slave_sel[2]); +assign shared_err = ((wishbone_interface_bus_rx_err | wishbone_interface_bus_tx_err) | interface0_err); +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= ((wishbone_interface_bus_rx_ack | wishbone_interface_bus_tx_ack) | interface0_ack); + shared_dat_r <= ((({32{slave_sel_r[0]}} & wishbone_interface_bus_rx_dat_r) | ({32{slave_sel_r[1]}} & wishbone_interface_bus_tx_dat_r)) | ({32{slave_sel_r[2]}} & interface0_dat_r)); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; + end +end +assign done = (count == 1'd0); +assign maccore_bus_errors_status = maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; -assign sys_rst = main_maccore_int_rst; +assign sys_rst = maccore_int_rst; assign eth_rx_clk = mii_clocks_rx; assign eth_tx_clk = mii_clocks_tx; -assign main_maccore_crg_reset0 = (main_maccore_crg_reset_storage | main_maccore_crg_reset1); -assign mii_rst_n = (~main_maccore_crg_reset0); -assign main_maccore_crg_counter_done = (main_maccore_crg_counter == 9'd256); -assign main_maccore_crg_counter_ce = (~main_maccore_crg_counter_done); -assign main_maccore_crg_reset1 = (~main_maccore_crg_counter_done); -assign main_maccore_liteethphymiitx_converter_sink_valid = main_maccore_liteethphymiitx_sink_valid; -assign main_maccore_liteethphymiitx_converter_sink_payload_data = main_maccore_liteethphymiitx_sink_payload_data; -assign main_maccore_liteethphymiitx_sink_ready = main_maccore_liteethphymiitx_converter_sink_ready; -assign main_maccore_liteethphymiitx_source_source_ready = 1'd1; -assign main_maccore_liteethphymiitx_source_source_valid = main_maccore_liteethphymiitx_converter_source_valid; -assign main_maccore_liteethphymiitx_converter_source_ready = main_maccore_liteethphymiitx_source_source_ready; -assign main_maccore_liteethphymiitx_source_source_first = main_maccore_liteethphymiitx_converter_source_first; -assign main_maccore_liteethphymiitx_source_source_last = main_maccore_liteethphymiitx_converter_source_last; -assign main_maccore_liteethphymiitx_source_source_payload_data = main_maccore_liteethphymiitx_converter_source_payload_data; -assign main_maccore_liteethphymiitx_converter_first = (main_maccore_liteethphymiitx_converter_mux == 1'd0); -assign main_maccore_liteethphymiitx_converter_last = (main_maccore_liteethphymiitx_converter_mux == 1'd1); -assign main_maccore_liteethphymiitx_converter_source_valid = main_maccore_liteethphymiitx_converter_sink_valid; -assign main_maccore_liteethphymiitx_converter_source_first = (main_maccore_liteethphymiitx_converter_sink_first & main_maccore_liteethphymiitx_converter_first); -assign main_maccore_liteethphymiitx_converter_source_last = (main_maccore_liteethphymiitx_converter_sink_last & main_maccore_liteethphymiitx_converter_last); -assign main_maccore_liteethphymiitx_converter_sink_ready = (main_maccore_liteethphymiitx_converter_last & main_maccore_liteethphymiitx_converter_source_ready); -always @(*) begin - main_maccore_liteethphymiitx_converter_source_payload_data <= 4'd0; - case (main_maccore_liteethphymiitx_converter_mux) +assign maccore_crg_reset0 = (maccore_crg_reset_storage | maccore_crg_reset1); +assign mii_rst_n = (~maccore_crg_reset0); +assign maccore_crg_counter_done = (maccore_crg_counter == 9'd256); +assign maccore_crg_counter_ce = (~maccore_crg_counter_done); +assign maccore_crg_reset1 = (~maccore_crg_counter_done); +assign maccore_liteethphymiitx_converter_sink_valid = maccore_liteethphymiitx_sink_valid; +assign maccore_liteethphymiitx_converter_sink_payload_data = maccore_liteethphymiitx_sink_payload_data; +assign maccore_liteethphymiitx_sink_ready = maccore_liteethphymiitx_converter_sink_ready; +assign maccore_liteethphymiitx_source_source_ready = 1'd1; +assign maccore_liteethphymiitx_source_source_valid = maccore_liteethphymiitx_converter_source_valid; +assign maccore_liteethphymiitx_converter_source_ready = maccore_liteethphymiitx_source_source_ready; +assign maccore_liteethphymiitx_source_source_first = maccore_liteethphymiitx_converter_source_first; +assign maccore_liteethphymiitx_source_source_last = maccore_liteethphymiitx_converter_source_last; +assign maccore_liteethphymiitx_source_source_payload_data = maccore_liteethphymiitx_converter_source_payload_data; +assign maccore_liteethphymiitx_converter_first = (maccore_liteethphymiitx_converter_mux == 1'd0); +assign maccore_liteethphymiitx_converter_last = (maccore_liteethphymiitx_converter_mux == 1'd1); +assign maccore_liteethphymiitx_converter_source_valid = maccore_liteethphymiitx_converter_sink_valid; +assign maccore_liteethphymiitx_converter_source_first = (maccore_liteethphymiitx_converter_sink_first & maccore_liteethphymiitx_converter_first); +assign maccore_liteethphymiitx_converter_source_last = (maccore_liteethphymiitx_converter_sink_last & maccore_liteethphymiitx_converter_last); +assign maccore_liteethphymiitx_converter_sink_ready = (maccore_liteethphymiitx_converter_last & maccore_liteethphymiitx_converter_source_ready); +always @(*) begin + maccore_liteethphymiitx_converter_source_payload_data <= 4'd0; + case (maccore_liteethphymiitx_converter_mux) 1'd0: begin - main_maccore_liteethphymiitx_converter_source_payload_data <= main_maccore_liteethphymiitx_converter_sink_payload_data[3:0]; + maccore_liteethphymiitx_converter_source_payload_data <= maccore_liteethphymiitx_converter_sink_payload_data[3:0]; end default: begin - main_maccore_liteethphymiitx_converter_source_payload_data <= main_maccore_liteethphymiitx_converter_sink_payload_data[7:4]; + maccore_liteethphymiitx_converter_source_payload_data <= maccore_liteethphymiitx_converter_sink_payload_data[7:4]; end endcase end -assign main_maccore_liteethphymiitx_converter_source_payload_valid_token_count = main_maccore_liteethphymiitx_converter_last; -assign main_maccore_liteethphymiirx_converter_sink_last = (~mii_rx_dv); -assign main_maccore_liteethphymiirx_source_valid = main_maccore_liteethphymiirx_source_source_valid; -assign main_maccore_liteethphymiirx_source_source_ready = main_maccore_liteethphymiirx_source_ready; -assign main_maccore_liteethphymiirx_source_first = main_maccore_liteethphymiirx_source_source_first; -assign main_maccore_liteethphymiirx_source_last = main_maccore_liteethphymiirx_source_source_last; -assign main_maccore_liteethphymiirx_source_payload_data = main_maccore_liteethphymiirx_source_source_payload_data; -assign main_maccore_liteethphymiirx_source_source_valid = main_maccore_liteethphymiirx_converter_source_valid; -assign main_maccore_liteethphymiirx_converter_source_ready = main_maccore_liteethphymiirx_source_source_ready; -assign main_maccore_liteethphymiirx_source_source_first = main_maccore_liteethphymiirx_converter_source_first; -assign main_maccore_liteethphymiirx_source_source_last = main_maccore_liteethphymiirx_converter_source_last; -assign main_maccore_liteethphymiirx_source_source_payload_data = main_maccore_liteethphymiirx_converter_source_payload_data; -assign main_maccore_liteethphymiirx_converter_sink_ready = ((~main_maccore_liteethphymiirx_converter_strobe_all) | main_maccore_liteethphymiirx_converter_source_ready); -assign main_maccore_liteethphymiirx_converter_source_valid = main_maccore_liteethphymiirx_converter_strobe_all; -assign main_maccore_liteethphymiirx_converter_load_part = (main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready); -assign mii_mdc = main_maccore__w_storage[0]; -assign main_maccore_data_oe = main_maccore__w_storage[1]; -assign main_maccore_data_w = main_maccore__w_storage[2]; -assign main_sink_valid = main_source_source_valid; -assign main_source_source_ready = main_sink_ready; -assign main_sink_first = main_source_source_first; -assign main_sink_last = main_source_source_last; -assign main_sink_payload_data = main_source_source_payload_data; -assign main_sink_payload_last_be = main_source_source_payload_last_be; -assign main_sink_payload_error = main_source_source_payload_error; -assign main_sink_sink_valid = main_source_valid; -assign main_source_ready = main_sink_sink_ready; -assign main_sink_sink_first = main_source_first; -assign main_sink_sink_last = main_source_last; -assign main_sink_sink_payload_data = main_source_payload_data; -assign main_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_sink_sink_payload_error = main_source_payload_error; -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; -always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); +assign maccore_liteethphymiitx_converter_source_payload_valid_token_count = maccore_liteethphymiitx_converter_last; +assign maccore_liteethphymiirx_converter_sink_last = (~mii_rx_dv); +assign maccore_liteethphymiirx_source_valid = maccore_liteethphymiirx_source_source_valid; +assign maccore_liteethphymiirx_source_source_ready = maccore_liteethphymiirx_source_ready; +assign maccore_liteethphymiirx_source_first = maccore_liteethphymiirx_source_source_first; +assign maccore_liteethphymiirx_source_last = maccore_liteethphymiirx_source_source_last; +assign maccore_liteethphymiirx_source_payload_data = maccore_liteethphymiirx_source_source_payload_data; +assign maccore_liteethphymiirx_source_source_valid = maccore_liteethphymiirx_converter_source_valid; +assign maccore_liteethphymiirx_converter_source_ready = maccore_liteethphymiirx_source_source_ready; +assign maccore_liteethphymiirx_source_source_first = maccore_liteethphymiirx_converter_source_first; +assign maccore_liteethphymiirx_source_source_last = maccore_liteethphymiirx_converter_source_last; +assign maccore_liteethphymiirx_source_source_payload_data = maccore_liteethphymiirx_converter_source_payload_data; +assign maccore_liteethphymiirx_converter_sink_ready = ((~maccore_liteethphymiirx_converter_strobe_all) | maccore_liteethphymiirx_converter_source_ready); +assign maccore_liteethphymiirx_converter_source_valid = maccore_liteethphymiirx_converter_strobe_all; +assign maccore_liteethphymiirx_converter_load_part = (maccore_liteethphymiirx_converter_sink_valid & maccore_liteethphymiirx_converter_sink_ready); +assign mii_mdc = maccore__w_storage[0]; +assign maccore_data_oe = maccore__w_storage[1]; +assign maccore_data_w = maccore__w_storage[2]; +assign core_sink_valid = wishbone_interface_source_valid; +assign wishbone_interface_source_ready = core_sink_ready; +assign core_sink_first = wishbone_interface_source_first; +assign core_sink_last = wishbone_interface_source_last; +assign core_sink_payload_data = wishbone_interface_source_payload_data; +assign core_sink_payload_last_be = wishbone_interface_source_payload_last_be; +assign core_sink_payload_error = wishbone_interface_source_payload_error; +assign wishbone_interface_sink_valid = core_source_valid; +assign core_source_ready = wishbone_interface_sink_ready; +assign wishbone_interface_sink_first = core_source_first; +assign wishbone_interface_sink_last = core_source_last; +assign wishbone_interface_sink_payload_data = core_source_payload_data; +assign wishbone_interface_sink_payload_last_be = core_source_payload_last_be; +assign wishbone_interface_sink_payload_error = core_source_payload_error; +assign core_tx_cdc_cdc_sink_valid = core_tx_cdc_sink_sink_valid; +assign core_tx_cdc_sink_sink_ready = core_tx_cdc_cdc_sink_ready; +assign core_tx_cdc_cdc_sink_first = core_tx_cdc_sink_sink_first; +assign core_tx_cdc_cdc_sink_last = core_tx_cdc_sink_sink_last; +assign core_tx_cdc_cdc_sink_payload_data = core_tx_cdc_sink_sink_payload_data; +assign core_tx_cdc_cdc_sink_payload_last_be = core_tx_cdc_sink_sink_payload_last_be; +assign core_tx_cdc_cdc_sink_payload_error = core_tx_cdc_sink_sink_payload_error; +assign core_tx_cdc_source_source_valid = core_tx_cdc_cdc_source_valid; +assign core_tx_cdc_cdc_source_ready = core_tx_cdc_source_source_ready; +assign core_tx_cdc_source_source_first = core_tx_cdc_cdc_source_first; +assign core_tx_cdc_source_source_last = core_tx_cdc_cdc_source_last; +assign core_tx_cdc_source_source_payload_data = core_tx_cdc_cdc_source_payload_data; +assign core_tx_cdc_source_source_payload_last_be = core_tx_cdc_cdc_source_payload_last_be; +assign core_tx_cdc_source_source_payload_error = core_tx_cdc_cdc_source_payload_error; +assign core_tx_cdc_cdc_asyncfifo_din = {core_tx_cdc_cdc_fifo_in_last, core_tx_cdc_cdc_fifo_in_first, core_tx_cdc_cdc_fifo_in_payload_error, core_tx_cdc_cdc_fifo_in_payload_last_be, core_tx_cdc_cdc_fifo_in_payload_data}; +assign {core_tx_cdc_cdc_fifo_out_last, core_tx_cdc_cdc_fifo_out_first, core_tx_cdc_cdc_fifo_out_payload_error, core_tx_cdc_cdc_fifo_out_payload_last_be, core_tx_cdc_cdc_fifo_out_payload_data} = core_tx_cdc_cdc_asyncfifo_dout; +assign core_tx_cdc_cdc_sink_ready = core_tx_cdc_cdc_asyncfifo_writable; +assign core_tx_cdc_cdc_asyncfifo_we = core_tx_cdc_cdc_sink_valid; +assign core_tx_cdc_cdc_fifo_in_first = core_tx_cdc_cdc_sink_first; +assign core_tx_cdc_cdc_fifo_in_last = core_tx_cdc_cdc_sink_last; +assign core_tx_cdc_cdc_fifo_in_payload_data = core_tx_cdc_cdc_sink_payload_data; +assign core_tx_cdc_cdc_fifo_in_payload_last_be = core_tx_cdc_cdc_sink_payload_last_be; +assign core_tx_cdc_cdc_fifo_in_payload_error = core_tx_cdc_cdc_sink_payload_error; +assign core_tx_cdc_cdc_source_valid = core_tx_cdc_cdc_asyncfifo_readable; +assign core_tx_cdc_cdc_source_first = core_tx_cdc_cdc_fifo_out_first; +assign core_tx_cdc_cdc_source_last = core_tx_cdc_cdc_fifo_out_last; +assign core_tx_cdc_cdc_source_payload_data = core_tx_cdc_cdc_fifo_out_payload_data; +assign core_tx_cdc_cdc_source_payload_last_be = core_tx_cdc_cdc_fifo_out_payload_last_be; +assign core_tx_cdc_cdc_source_payload_error = core_tx_cdc_cdc_fifo_out_payload_error; +assign core_tx_cdc_cdc_asyncfifo_re = core_tx_cdc_cdc_source_ready; +assign core_tx_cdc_cdc_graycounter0_ce = (core_tx_cdc_cdc_asyncfifo_writable & core_tx_cdc_cdc_asyncfifo_we); +assign core_tx_cdc_cdc_graycounter1_ce = (core_tx_cdc_cdc_asyncfifo_readable & core_tx_cdc_cdc_asyncfifo_re); +assign core_tx_cdc_cdc_asyncfifo_writable = (((core_tx_cdc_cdc_graycounter0_q[5] == core_tx_cdc_cdc_consume_wdomain[5]) | (core_tx_cdc_cdc_graycounter0_q[4] == core_tx_cdc_cdc_consume_wdomain[4])) | (core_tx_cdc_cdc_graycounter0_q[3:0] != core_tx_cdc_cdc_consume_wdomain[3:0])); +assign core_tx_cdc_cdc_asyncfifo_readable = (core_tx_cdc_cdc_graycounter1_q != core_tx_cdc_cdc_produce_rdomain); +assign core_tx_cdc_cdc_wrport_adr = core_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_tx_cdc_cdc_wrport_dat_w = core_tx_cdc_cdc_asyncfifo_din; +assign core_tx_cdc_cdc_wrport_we = core_tx_cdc_cdc_graycounter0_ce; +assign core_tx_cdc_cdc_rdport_adr = core_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_tx_cdc_cdc_asyncfifo_dout = core_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + core_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter0_ce) begin + core_tx_cdc_cdc_graycounter0_q_next_binary <= (core_tx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + core_tx_cdc_cdc_graycounter0_q_next_binary <= core_tx_cdc_cdc_graycounter0_q_binary; end end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_tx_cdc_cdc_graycounter0_q_next = (core_tx_cdc_cdc_graycounter0_q_next_binary ^ core_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter1_ce) begin + core_tx_cdc_cdc_graycounter1_q_next_binary <= (core_tx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; -always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; -end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); -always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) + core_tx_cdc_cdc_graycounter1_q_next_binary <= core_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign core_tx_cdc_cdc_graycounter1_q_next = (core_tx_cdc_cdc_graycounter1_q_next_binary ^ core_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_tx_converter_converter_sink_valid = core_tx_converter_sink_valid; +assign core_tx_converter_converter_sink_first = core_tx_converter_sink_first; +assign core_tx_converter_converter_sink_last = core_tx_converter_sink_last; +assign core_tx_converter_sink_ready = core_tx_converter_converter_sink_ready; +always @(*) begin + core_tx_converter_converter_sink_payload_data <= 40'd0; + core_tx_converter_converter_sink_payload_data[7:0] <= core_tx_converter_sink_payload_data[7:0]; + core_tx_converter_converter_sink_payload_data[8] <= core_tx_converter_sink_payload_last_be[0]; + core_tx_converter_converter_sink_payload_data[9] <= core_tx_converter_sink_payload_error[0]; + core_tx_converter_converter_sink_payload_data[17:10] <= core_tx_converter_sink_payload_data[15:8]; + core_tx_converter_converter_sink_payload_data[18] <= core_tx_converter_sink_payload_last_be[1]; + core_tx_converter_converter_sink_payload_data[19] <= core_tx_converter_sink_payload_error[1]; + core_tx_converter_converter_sink_payload_data[27:20] <= core_tx_converter_sink_payload_data[23:16]; + core_tx_converter_converter_sink_payload_data[28] <= core_tx_converter_sink_payload_last_be[2]; + core_tx_converter_converter_sink_payload_data[29] <= core_tx_converter_sink_payload_error[2]; + core_tx_converter_converter_sink_payload_data[37:30] <= core_tx_converter_sink_payload_data[31:24]; + core_tx_converter_converter_sink_payload_data[38] <= core_tx_converter_sink_payload_last_be[3]; + core_tx_converter_converter_sink_payload_data[39] <= core_tx_converter_sink_payload_error[3]; +end +assign core_tx_converter_source_valid = core_tx_converter_source_source_valid; +assign core_tx_converter_source_first = core_tx_converter_source_source_first; +assign core_tx_converter_source_last = core_tx_converter_source_source_last; +assign core_tx_converter_source_source_ready = core_tx_converter_source_ready; +assign {core_tx_converter_source_payload_error, core_tx_converter_source_payload_last_be, core_tx_converter_source_payload_data} = core_tx_converter_source_source_payload_data; +assign core_tx_converter_source_source_valid = core_tx_converter_converter_source_valid; +assign core_tx_converter_converter_source_ready = core_tx_converter_source_source_ready; +assign core_tx_converter_source_source_first = core_tx_converter_converter_source_first; +assign core_tx_converter_source_source_last = core_tx_converter_converter_source_last; +assign core_tx_converter_source_source_payload_data = core_tx_converter_converter_source_payload_data; +assign core_tx_converter_converter_first = (core_tx_converter_converter_mux == 1'd0); +assign core_tx_converter_converter_last = (core_tx_converter_converter_mux == 2'd3); +assign core_tx_converter_converter_source_valid = core_tx_converter_converter_sink_valid; +assign core_tx_converter_converter_source_first = (core_tx_converter_converter_sink_first & core_tx_converter_converter_first); +assign core_tx_converter_converter_source_last = (core_tx_converter_converter_sink_last & core_tx_converter_converter_last); +assign core_tx_converter_converter_sink_ready = (core_tx_converter_converter_last & core_tx_converter_converter_source_ready); +always @(*) begin + core_tx_converter_converter_source_payload_data <= 10'd0; + case (core_tx_converter_converter_mux) 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[9:0]; end 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[19:10]; end 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[29:20]; end default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[39:30]; end endcase end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; -always @(*) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - main_tx_last_be_source_payload_last_be <= 1'd0; - main_tx_last_be_source_valid <= 1'd0; - builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; - case (builder_txdatapath_liteethmactxlastbe_state) +assign core_tx_converter_converter_source_payload_valid_token_count = core_tx_converter_converter_last; +assign core_tx_last_be_last_handler_sink_valid = core_tx_last_be_sink_sink_valid; +assign core_tx_last_be_sink_sink_ready = core_tx_last_be_last_handler_sink_ready; +assign core_tx_last_be_last_handler_sink_first = core_tx_last_be_sink_sink_first; +assign core_tx_last_be_last_handler_sink_last = core_tx_last_be_sink_sink_last; +assign core_tx_last_be_last_handler_sink_payload_data = core_tx_last_be_sink_sink_payload_data; +assign core_tx_last_be_last_handler_sink_payload_last_be = core_tx_last_be_sink_sink_payload_last_be; +assign core_tx_last_be_last_handler_sink_payload_error = core_tx_last_be_sink_sink_payload_error; +assign core_tx_last_be_source_source_valid = core_tx_last_be_last_handler_source_valid; +assign core_tx_last_be_last_handler_source_ready = core_tx_last_be_source_source_ready; +assign core_tx_last_be_source_source_first = core_tx_last_be_last_handler_source_first; +assign core_tx_last_be_source_source_last = core_tx_last_be_last_handler_source_last; +assign core_tx_last_be_source_source_payload_data = core_tx_last_be_last_handler_source_payload_data; +assign core_tx_last_be_source_source_payload_last_be = core_tx_last_be_last_handler_source_payload_last_be; +assign core_tx_last_be_source_source_payload_error = core_tx_last_be_last_handler_source_payload_error; +always @(*) begin + core_tx_last_be_last_handler_sink_ready <= 1'd0; + core_tx_last_be_last_handler_source_first <= 1'd0; + core_tx_last_be_last_handler_source_last <= 1'd0; + core_tx_last_be_last_handler_source_payload_data <= 8'd0; + core_tx_last_be_last_handler_source_payload_error <= 1'd0; + core_tx_last_be_last_handler_source_payload_last_be <= 1'd0; + core_tx_last_be_last_handler_source_valid <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= txdatapath_liteethmactxlastbe_state; + case (txdatapath_liteethmactxlastbe_state) 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + core_tx_last_be_last_handler_sink_ready <= 1'd1; + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_last)) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd0; end end default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_last <= main_tx_last_be_sink_last; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + core_tx_last_be_last_handler_source_valid <= core_tx_last_be_last_handler_sink_valid; + core_tx_last_be_last_handler_sink_ready <= core_tx_last_be_last_handler_source_ready; + core_tx_last_be_last_handler_source_first <= core_tx_last_be_last_handler_sink_first; + core_tx_last_be_last_handler_source_last <= core_tx_last_be_last_handler_sink_last; + core_tx_last_be_last_handler_source_payload_data <= core_tx_last_be_last_handler_sink_payload_data; + core_tx_last_be_last_handler_source_payload_last_be <= core_tx_last_be_last_handler_sink_payload_last_be; + core_tx_last_be_last_handler_source_payload_error <= core_tx_last_be_last_handler_sink_payload_error; + core_tx_last_be_last_handler_source_last <= (core_tx_last_be_last_handler_sink_payload_last_be != 1'd0); + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_ready)) begin + if ((core_tx_last_be_last_handler_source_last & (~core_tx_last_be_last_handler_sink_last))) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd1; end end end endcase end -assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); -always @(*) begin - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; - main_tx_padding_sink_ready <= 1'd0; - main_tx_padding_source_first <= 1'd0; - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_data <= 8'd0; - main_tx_padding_source_payload_error <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - main_tx_padding_source_valid <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; - case (builder_txdatapath_liteethmacpaddinginserter_state) +assign core_tx_padding_counter_done = (core_tx_padding_counter >= 6'd59); +always @(*) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + core_tx_padding_sink_ready <= 1'd0; + core_tx_padding_source_first <= 1'd0; + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_data <= 8'd0; + core_tx_padding_source_payload_error <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + core_tx_padding_source_valid <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= txdatapath_liteethmacpaddinginserter_state; + case (txdatapath_liteethmacpaddinginserter_state) 1'd1: begin - main_tx_padding_source_valid <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_source_payload_last_be <= 1'd1; - main_tx_padding_source_last <= 1'd1; - end - main_tx_padding_source_payload_data <= 1'd0; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + core_tx_padding_source_valid <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_source_payload_last_be <= 1'd1; + core_tx_padding_source_last <= 1'd1; + end + core_tx_padding_source_payload_data <= 1'd0; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; end end end default: begin - main_tx_padding_source_valid <= main_tx_padding_sink_valid; - main_tx_padding_sink_ready <= main_tx_padding_source_ready; - main_tx_padding_source_first <= main_tx_padding_sink_first; - main_tx_padding_source_last <= main_tx_padding_sink_last; - main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; - main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; - main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_sink_last) begin - if ((~main_tx_padding_counter_done)) begin - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + core_tx_padding_source_valid <= core_tx_padding_sink_valid; + core_tx_padding_sink_ready <= core_tx_padding_source_ready; + core_tx_padding_source_first <= core_tx_padding_sink_first; + core_tx_padding_source_last <= core_tx_padding_sink_last; + core_tx_padding_source_payload_data <= core_tx_padding_sink_payload_data; + core_tx_padding_source_payload_last_be <= core_tx_padding_sink_payload_last_be; + core_tx_padding_source_payload_error <= core_tx_padding_sink_payload_error; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_sink_last) begin + if ((~core_tx_padding_counter_done)) begin + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; end else begin - if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin - main_tx_padding_source_payload_last_be <= 1'd1; + if (((core_tx_padding_counter == 6'd59) & (core_tx_padding_sink_payload_last_be < 1'd1))) begin + core_tx_padding_source_payload_last_be <= 1'd1; end else begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; end end end @@ -1665,1561 +1658,1494 @@ always @(*) begin end endcase end -assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; -assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; -assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); -assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; -assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; -assign main_tx_crc_sink_first = main_tx_crc_source_source_first; -assign main_tx_crc_sink_last = main_tx_crc_source_source_last; -assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; -assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; -assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; -assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; -assign main_tx_crc_crc_prev = main_tx_crc_reg; -always @(*) begin - main_tx_crc_error <= 1'd0; - main_tx_crc_value <= 32'd0; - if (main_tx_crc_be) begin - main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; - main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); - end -end -always @(*) begin - main_tx_crc_crc_next <= 32'd0; - main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); - main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); -end -always @(*) begin - builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; - main_tx_crc_ce <= 1'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; - main_tx_crc_is_ongoing0 <= 1'd0; - main_tx_crc_is_ongoing1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; - main_tx_crc_reset <= 1'd0; - main_tx_crc_sink_ready <= 1'd0; - main_tx_crc_source_first <= 1'd0; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_data <= 8'd0; - main_tx_crc_source_payload_error <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - main_tx_crc_source_valid <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; - case (builder_txdatapath_bufferizeendpoints_state) +assign core_tx_crc_data0 = core_tx_crc_sink_payload_data; +assign core_tx_crc_be = core_tx_crc_sink_payload_last_be; +assign core_tx_crc_cnt_done = (core_tx_crc_cnt == 1'd0); +assign core_tx_crc_sink_valid = core_tx_crc_source_source_valid; +assign core_tx_crc_source_source_ready = core_tx_crc_sink_ready; +assign core_tx_crc_sink_first = core_tx_crc_source_source_first; +assign core_tx_crc_sink_last = core_tx_crc_source_source_last; +assign core_tx_crc_sink_payload_data = core_tx_crc_source_source_payload_data; +assign core_tx_crc_sink_payload_last_be = core_tx_crc_source_source_payload_last_be; +assign core_tx_crc_sink_payload_error = core_tx_crc_source_source_payload_error; +assign core_tx_crc_data1 = core_tx_crc_data0; +assign core_tx_crc_crc_prev = core_tx_crc_reg; +always @(*) begin + core_tx_crc_error <= 1'd0; + core_tx_crc_value <= 32'd0; + if (core_tx_crc_be) begin + core_tx_crc_value <= ({core_tx_crc_crc_next[0], core_tx_crc_crc_next[1], core_tx_crc_crc_next[2], core_tx_crc_crc_next[3], core_tx_crc_crc_next[4], core_tx_crc_crc_next[5], core_tx_crc_crc_next[6], core_tx_crc_crc_next[7], core_tx_crc_crc_next[8], core_tx_crc_crc_next[9], core_tx_crc_crc_next[10], core_tx_crc_crc_next[11], core_tx_crc_crc_next[12], core_tx_crc_crc_next[13], core_tx_crc_crc_next[14], core_tx_crc_crc_next[15], core_tx_crc_crc_next[16], core_tx_crc_crc_next[17], core_tx_crc_crc_next[18], core_tx_crc_crc_next[19], core_tx_crc_crc_next[20], core_tx_crc_crc_next[21], core_tx_crc_crc_next[22], core_tx_crc_crc_next[23], core_tx_crc_crc_next[24], core_tx_crc_crc_next[25], core_tx_crc_crc_next[26], core_tx_crc_crc_next[27], core_tx_crc_crc_next[28], core_tx_crc_crc_next[29], core_tx_crc_crc_next[30], core_tx_crc_crc_next[31]} ^ 32'd4294967295); + core_tx_crc_error <= (core_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + core_tx_crc_crc_next <= 32'd0; + core_tx_crc_crc_next[0] <= (((core_tx_crc_crc_prev[24] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[1] <= (((((((core_tx_crc_crc_prev[25] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[2] <= (((((((((core_tx_crc_crc_prev[26] ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[3] <= (((((((core_tx_crc_crc_prev[27] ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[4] <= (((((((((core_tx_crc_crc_prev[28] ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[5] <= (((((((((((((core_tx_crc_crc_prev[29] ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[6] <= (((((((((((core_tx_crc_crc_prev[30] ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[7] <= (((((((((core_tx_crc_crc_prev[31] ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[8] <= ((((((((core_tx_crc_crc_prev[0] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[9] <= ((((((((core_tx_crc_crc_prev[1] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[10] <= ((((((((core_tx_crc_crc_prev[2] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[11] <= ((((((((core_tx_crc_crc_prev[3] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[12] <= ((((((((((((core_tx_crc_crc_prev[4] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[13] <= ((((((((((((core_tx_crc_crc_prev[5] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[14] <= ((((((((((core_tx_crc_crc_prev[6] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[15] <= ((((((((core_tx_crc_crc_prev[7] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[16] <= ((((((core_tx_crc_crc_prev[8] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[17] <= ((((((core_tx_crc_crc_prev[9] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[18] <= ((((((core_tx_crc_crc_prev[10] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[19] <= ((((core_tx_crc_crc_prev[11] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[20] <= ((core_tx_crc_crc_prev[12] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[21] <= ((core_tx_crc_crc_prev[13] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); + core_tx_crc_crc_next[22] <= ((core_tx_crc_crc_prev[14] ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[23] <= ((((((core_tx_crc_crc_prev[15] ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[24] <= ((((((core_tx_crc_crc_prev[16] ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[25] <= ((((core_tx_crc_crc_prev[17] ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[26] <= ((((((((core_tx_crc_crc_prev[18] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[27] <= ((((((((core_tx_crc_crc_prev[19] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[28] <= ((((((core_tx_crc_crc_prev[20] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[29] <= ((((((core_tx_crc_crc_prev[21] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[30] <= ((((core_tx_crc_crc_prev[22] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[31] <= ((core_tx_crc_crc_prev[23] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); +end +always @(*) begin + core_tx_crc_ce <= 1'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + core_tx_crc_is_ongoing0 <= 1'd0; + core_tx_crc_is_ongoing1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + core_tx_crc_reset <= 1'd0; + core_tx_crc_sink_ready <= 1'd0; + core_tx_crc_source_first <= 1'd0; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_data <= 8'd0; + core_tx_crc_source_payload_error <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + core_tx_crc_source_valid <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 2'd0; + txdatapath_bufferizeendpoints_next_state <= txdatapath_bufferizeendpoints_state; + case (txdatapath_bufferizeendpoints_state) 1'd1: begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); - main_tx_crc_source_valid <= main_tx_crc_sink_valid; - main_tx_crc_sink_ready <= main_tx_crc_source_ready; - main_tx_crc_source_first <= main_tx_crc_sink_first; - main_tx_crc_source_last <= main_tx_crc_sink_last; - main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; - main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; - main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - if (main_tx_crc_sink_last) begin - if (main_tx_crc_sink_payload_last_be) begin - main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + core_tx_crc_ce <= (core_tx_crc_sink_valid & core_tx_crc_source_ready); + core_tx_crc_source_valid <= core_tx_crc_sink_valid; + core_tx_crc_sink_ready <= core_tx_crc_source_ready; + core_tx_crc_source_first <= core_tx_crc_sink_first; + core_tx_crc_source_last <= core_tx_crc_sink_last; + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; + core_tx_crc_source_payload_last_be <= core_tx_crc_sink_payload_last_be; + core_tx_crc_source_payload_error <= core_tx_crc_sink_payload_error; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + if (core_tx_crc_sink_last) begin + if (core_tx_crc_sink_payload_last_be) begin + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; end - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - main_tx_crc_source_last <= 1'd1; - main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + core_tx_crc_source_last <= 1'd1; + core_tx_crc_source_payload_last_be <= (core_tx_crc_sink_payload_last_be <<< -3'd3); end - end else begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); end - if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (((core_tx_crc_sink_valid & core_tx_crc_sink_last) & core_tx_crc_source_ready)) begin + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end else begin - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= core_tx_crc_value; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; if (1'd0) begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (core_tx_crc_sink_payload_last_be >>> 3'd4); + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end else begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= core_tx_crc_sink_payload_last_be; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end - builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + txdatapath_bufferizeendpoints_next_state <= 2'd2; end end end 2'd2: begin - main_tx_crc_source_valid <= 1'd1; - case (main_tx_crc_cnt) + core_tx_crc_source_valid <= 1'd1; + case (core_tx_crc_cnt) 1'd0: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[31:24]; end 1'd1: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[23:16]; end 2'd2: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[15:8]; end default: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[7:0]; end endcase - if (main_tx_crc_cnt_done) begin - main_tx_crc_source_last <= 1'd1; - if (main_tx_crc_source_ready) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_tx_crc_cnt_done) begin + core_tx_crc_source_last <= 1'd1; + if (core_tx_crc_source_ready) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end end - main_tx_crc_is_ongoing1 <= 1'd1; + core_tx_crc_is_ongoing1 <= 1'd1; end default: begin - main_tx_crc_reset <= 1'd1; - main_tx_crc_sink_ready <= 1'd1; - if (main_tx_crc_sink_valid) begin - main_tx_crc_sink_ready <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + core_tx_crc_reset <= 1'd1; + core_tx_crc_sink_ready <= 1'd1; + if (core_tx_crc_sink_valid) begin + core_tx_crc_sink_ready <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 1'd1; end - main_tx_crc_is_ongoing0 <= 1'd1; + core_tx_crc_is_ongoing0 <= 1'd1; end endcase end -assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); -assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; -assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; -assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; -assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; -assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; -assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; -assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; -assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; -assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; -assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; -assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; -assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; -assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; -assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; -assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; -always @(*) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; - main_tx_preamble_sink_ready <= 1'd0; - main_tx_preamble_source_first <= 1'd0; - main_tx_preamble_source_last <= 1'd0; - main_tx_preamble_source_payload_data <= 8'd0; - main_tx_preamble_source_payload_error <= 1'd0; - main_tx_preamble_source_valid <= 1'd0; - main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; - builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; - case (builder_txdatapath_liteethmacpreambleinserter_state) +assign core_tx_crc_pipe_valid_sink_ready = ((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready); +assign core_tx_crc_pipe_valid_sink_valid = core_tx_crc_sink_sink_valid; +assign core_tx_crc_sink_sink_ready = core_tx_crc_pipe_valid_sink_ready; +assign core_tx_crc_pipe_valid_sink_first = core_tx_crc_sink_sink_first; +assign core_tx_crc_pipe_valid_sink_last = core_tx_crc_sink_sink_last; +assign core_tx_crc_pipe_valid_sink_payload_data = core_tx_crc_sink_sink_payload_data; +assign core_tx_crc_pipe_valid_sink_payload_last_be = core_tx_crc_sink_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_payload_error = core_tx_crc_sink_sink_payload_error; +assign core_tx_crc_source_source_valid = core_tx_crc_pipe_valid_source_valid; +assign core_tx_crc_pipe_valid_source_ready = core_tx_crc_source_source_ready; +assign core_tx_crc_source_source_first = core_tx_crc_pipe_valid_source_first; +assign core_tx_crc_source_source_last = core_tx_crc_pipe_valid_source_last; +assign core_tx_crc_source_source_payload_data = core_tx_crc_pipe_valid_source_payload_data; +assign core_tx_crc_source_source_payload_last_be = core_tx_crc_pipe_valid_source_payload_last_be; +assign core_tx_crc_source_source_payload_error = core_tx_crc_pipe_valid_source_payload_error; +assign core_tx_preamble_source_payload_last_be = core_tx_preamble_sink_payload_last_be; +always @(*) begin + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + core_tx_preamble_sink_ready <= 1'd0; + core_tx_preamble_source_first <= 1'd0; + core_tx_preamble_source_last <= 1'd0; + core_tx_preamble_source_payload_data <= 8'd0; + core_tx_preamble_source_payload_error <= 1'd0; + core_tx_preamble_source_valid <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + core_tx_preamble_source_payload_data <= core_tx_preamble_sink_payload_data; + txdatapath_liteethmacpreambleinserter_next_state <= txdatapath_liteethmacpreambleinserter_state; + case (txdatapath_liteethmacpreambleinserter_state) 1'd1: begin - main_tx_preamble_source_valid <= 1'd1; - case (main_tx_preamble_count) + core_tx_preamble_source_valid <= 1'd1; + case (core_tx_preamble_count) 1'd0: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[7:0]; end 1'd1: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[15:8]; end 2'd2: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[23:16]; end 2'd3: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[31:24]; end 3'd4: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[39:32]; end 3'd5: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[47:40]; end 3'd6: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[55:48]; end default: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[63:56]; end endcase - if (main_tx_preamble_source_ready) begin - if ((main_tx_preamble_count == 3'd7)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + if (core_tx_preamble_source_ready) begin + if ((core_tx_preamble_count == 3'd7)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; end else begin - main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= (core_tx_preamble_count + 1'd1); + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; end end end 2'd2: begin - main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; - main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; - main_tx_preamble_source_first <= main_tx_preamble_sink_first; - main_tx_preamble_source_last <= main_tx_preamble_sink_last; - main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; - if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + core_tx_preamble_source_valid <= core_tx_preamble_sink_valid; + core_tx_preamble_sink_ready <= core_tx_preamble_source_ready; + core_tx_preamble_source_first <= core_tx_preamble_sink_first; + core_tx_preamble_source_last <= core_tx_preamble_sink_last; + core_tx_preamble_source_payload_error <= core_tx_preamble_sink_payload_error; + if (((core_tx_preamble_sink_valid & core_tx_preamble_sink_last) & core_tx_preamble_source_ready)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; end end default: begin - main_tx_preamble_sink_ready <= 1'd1; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; - if (main_tx_preamble_sink_valid) begin - main_tx_preamble_sink_ready <= 1'd0; - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + core_tx_preamble_sink_ready <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (core_tx_preamble_sink_valid) begin + core_tx_preamble_sink_ready <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; end end endcase end always @(*) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; - main_tx_gap_sink_ready <= 1'd0; - main_tx_gap_source_first <= 1'd0; - main_tx_gap_source_last <= 1'd0; - main_tx_gap_source_payload_data <= 8'd0; - main_tx_gap_source_payload_error <= 1'd0; - main_tx_gap_source_payload_last_be <= 1'd0; - main_tx_gap_source_valid <= 1'd0; - builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; - case (builder_txdatapath_liteethmacgap_state) + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + core_tx_gap_sink_ready <= 1'd0; + core_tx_gap_source_first <= 1'd0; + core_tx_gap_source_last <= 1'd0; + core_tx_gap_source_payload_data <= 8'd0; + core_tx_gap_source_payload_error <= 1'd0; + core_tx_gap_source_payload_last_be <= 1'd0; + core_tx_gap_source_valid <= 1'd0; + txdatapath_liteethmacgap_next_state <= 1'd0; + txdatapath_liteethmacgap_next_state <= txdatapath_liteethmacgap_state; + case (txdatapath_liteethmacgap_state) 1'd1: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - if ((main_tx_gap_counter == 4'd11)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= (core_tx_gap_counter + 1'd1); + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((core_tx_gap_counter == 4'd11)) begin + txdatapath_liteethmacgap_next_state <= 1'd0; end end default: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - main_tx_gap_source_valid <= main_tx_gap_sink_valid; - main_tx_gap_sink_ready <= main_tx_gap_source_ready; - main_tx_gap_source_first <= main_tx_gap_sink_first; - main_tx_gap_source_last <= main_tx_gap_sink_last; - main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; - main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; - main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; - if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd1; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + core_tx_gap_source_valid <= core_tx_gap_sink_valid; + core_tx_gap_sink_ready <= core_tx_gap_source_ready; + core_tx_gap_source_first <= core_tx_gap_sink_first; + core_tx_gap_source_last <= core_tx_gap_sink_last; + core_tx_gap_source_payload_data <= core_tx_gap_sink_payload_data; + core_tx_gap_source_payload_last_be <= core_tx_gap_sink_payload_last_be; + core_tx_gap_source_payload_error <= core_tx_gap_sink_payload_error; + if (((core_tx_gap_sink_valid & core_tx_gap_sink_last) & core_tx_gap_sink_ready)) begin + txdatapath_liteethmacgap_next_state <= 1'd1; end end endcase end -assign main_tx_cdc_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_sink_first; -assign main_tx_cdc_sink_sink_last = main_sink_last; -assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; -assign main_tx_padding_sink_first = main_tx_last_be_source_first; -assign main_tx_padding_sink_last = main_tx_last_be_source_last; -assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; -assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; -assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; -assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; -assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; -assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; -assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; -assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; -assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; -assign main_tx_preamble_sink_first = main_tx_crc_source_first; -assign main_tx_preamble_sink_last = main_tx_crc_source_last; -assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; -assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; -assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; -assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; -assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; -assign main_tx_gap_sink_first = main_tx_preamble_source_first; -assign main_tx_gap_sink_last = main_tx_preamble_source_last; -assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; -assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; -assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; -assign main_maccore_liteethphymiitx_sink_valid = main_tx_gap_source_valid; -assign main_tx_gap_source_ready = main_maccore_liteethphymiitx_sink_ready; -assign main_maccore_liteethphymiitx_sink_first = main_tx_gap_source_first; -assign main_maccore_liteethphymiitx_sink_last = main_tx_gap_source_last; -assign main_maccore_liteethphymiitx_sink_payload_data = main_tx_gap_source_payload_data; -assign main_maccore_liteethphymiitx_sink_payload_last_be = main_tx_gap_source_payload_last_be; -assign main_maccore_liteethphymiitx_sink_payload_error = main_tx_gap_source_payload_error; -assign main_pulsesynchronizer0_i = main_rx_preamble_error; -assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; -assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; -assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; -always @(*) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; - main_rx_preamble_error <= 1'd0; - main_rx_preamble_sink_ready <= 1'd0; - main_rx_preamble_source_first <= 1'd0; - main_rx_preamble_source_last <= 1'd0; - main_rx_preamble_source_payload_error <= 1'd0; - main_rx_preamble_source_valid <= 1'd0; - builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; - case (builder_rxdatapath_liteethmacpreamblechecker_state) +assign core_tx_cdc_sink_sink_valid = core_sink_valid; +assign core_sink_ready = core_tx_cdc_sink_sink_ready; +assign core_tx_cdc_sink_sink_first = core_sink_first; +assign core_tx_cdc_sink_sink_last = core_sink_last; +assign core_tx_cdc_sink_sink_payload_data = core_sink_payload_data; +assign core_tx_cdc_sink_sink_payload_last_be = core_sink_payload_last_be; +assign core_tx_cdc_sink_sink_payload_error = core_sink_payload_error; +assign core_tx_converter_sink_valid = core_tx_cdc_source_source_valid; +assign core_tx_cdc_source_source_ready = core_tx_converter_sink_ready; +assign core_tx_converter_sink_first = core_tx_cdc_source_source_first; +assign core_tx_converter_sink_last = core_tx_cdc_source_source_last; +assign core_tx_converter_sink_payload_data = core_tx_cdc_source_source_payload_data; +assign core_tx_converter_sink_payload_last_be = core_tx_cdc_source_source_payload_last_be; +assign core_tx_converter_sink_payload_error = core_tx_cdc_source_source_payload_error; +assign core_tx_last_be_sink_sink_valid = core_tx_converter_source_valid; +assign core_tx_converter_source_ready = core_tx_last_be_sink_sink_ready; +assign core_tx_last_be_sink_sink_first = core_tx_converter_source_first; +assign core_tx_last_be_sink_sink_last = core_tx_converter_source_last; +assign core_tx_last_be_sink_sink_payload_data = core_tx_converter_source_payload_data; +assign core_tx_last_be_sink_sink_payload_last_be = core_tx_converter_source_payload_last_be; +assign core_tx_last_be_sink_sink_payload_error = core_tx_converter_source_payload_error; +assign core_tx_padding_sink_valid = core_tx_last_be_source_source_valid; +assign core_tx_last_be_source_source_ready = core_tx_padding_sink_ready; +assign core_tx_padding_sink_first = core_tx_last_be_source_source_first; +assign core_tx_padding_sink_last = core_tx_last_be_source_source_last; +assign core_tx_padding_sink_payload_data = core_tx_last_be_source_source_payload_data; +assign core_tx_padding_sink_payload_last_be = core_tx_last_be_source_source_payload_last_be; +assign core_tx_padding_sink_payload_error = core_tx_last_be_source_source_payload_error; +assign core_tx_crc_sink_sink_valid = core_tx_padding_source_valid; +assign core_tx_padding_source_ready = core_tx_crc_sink_sink_ready; +assign core_tx_crc_sink_sink_first = core_tx_padding_source_first; +assign core_tx_crc_sink_sink_last = core_tx_padding_source_last; +assign core_tx_crc_sink_sink_payload_data = core_tx_padding_source_payload_data; +assign core_tx_crc_sink_sink_payload_last_be = core_tx_padding_source_payload_last_be; +assign core_tx_crc_sink_sink_payload_error = core_tx_padding_source_payload_error; +assign core_tx_preamble_sink_valid = core_tx_crc_source_valid; +assign core_tx_crc_source_ready = core_tx_preamble_sink_ready; +assign core_tx_preamble_sink_first = core_tx_crc_source_first; +assign core_tx_preamble_sink_last = core_tx_crc_source_last; +assign core_tx_preamble_sink_payload_data = core_tx_crc_source_payload_data; +assign core_tx_preamble_sink_payload_last_be = core_tx_crc_source_payload_last_be; +assign core_tx_preamble_sink_payload_error = core_tx_crc_source_payload_error; +assign core_tx_gap_sink_valid = core_tx_preamble_source_valid; +assign core_tx_preamble_source_ready = core_tx_gap_sink_ready; +assign core_tx_gap_sink_first = core_tx_preamble_source_first; +assign core_tx_gap_sink_last = core_tx_preamble_source_last; +assign core_tx_gap_sink_payload_data = core_tx_preamble_source_payload_data; +assign core_tx_gap_sink_payload_last_be = core_tx_preamble_source_payload_last_be; +assign core_tx_gap_sink_payload_error = core_tx_preamble_source_payload_error; +assign maccore_liteethphymiitx_sink_valid = core_tx_gap_source_valid; +assign core_tx_gap_source_ready = maccore_liteethphymiitx_sink_ready; +assign maccore_liteethphymiitx_sink_first = core_tx_gap_source_first; +assign maccore_liteethphymiitx_sink_last = core_tx_gap_source_last; +assign maccore_liteethphymiitx_sink_payload_data = core_tx_gap_source_payload_data; +assign maccore_liteethphymiitx_sink_payload_last_be = core_tx_gap_source_payload_last_be; +assign maccore_liteethphymiitx_sink_payload_error = core_tx_gap_source_payload_error; +assign core_pulsesynchronizer0_i = core_rx_preamble_error; +assign core_pulsesynchronizer1_i = core_liteethmaccrc32checker_error; +assign core_rx_preamble_source_payload_data = core_rx_preamble_sink_payload_data; +assign core_rx_preamble_source_payload_last_be = core_rx_preamble_sink_payload_last_be; +always @(*) begin + core_rx_preamble_error <= 1'd0; + core_rx_preamble_sink_ready <= 1'd0; + core_rx_preamble_source_first <= 1'd0; + core_rx_preamble_source_last <= 1'd0; + core_rx_preamble_source_payload_error <= 1'd0; + core_rx_preamble_source_valid <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= rxdatapath_liteethmacpreamblechecker_state; + case (rxdatapath_liteethmacpreamblechecker_state) 1'd1: begin - main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; - main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; - main_rx_preamble_source_first <= main_rx_preamble_sink_first; - main_rx_preamble_source_last <= main_rx_preamble_sink_last; - main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; - if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + core_rx_preamble_source_valid <= core_rx_preamble_sink_valid; + core_rx_preamble_sink_ready <= core_rx_preamble_source_ready; + core_rx_preamble_source_first <= core_rx_preamble_sink_first; + core_rx_preamble_source_last <= core_rx_preamble_sink_last; + core_rx_preamble_source_payload_error <= core_rx_preamble_sink_payload_error; + if (((core_rx_preamble_source_valid & core_rx_preamble_source_last) & core_rx_preamble_source_ready)) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; end end default: begin - main_rx_preamble_sink_ready <= 1'd1; - if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + core_rx_preamble_sink_ready <= 1'd1; + if (((core_rx_preamble_sink_valid & (~core_rx_preamble_sink_last)) & (core_rx_preamble_sink_payload_data == core_rx_preamble_preamble[63:56]))) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; end - if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin - main_rx_preamble_error <= 1'd1; + if ((core_rx_preamble_sink_valid & core_rx_preamble_sink_last)) begin + core_rx_preamble_error <= 1'd1; end end endcase end -assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); -assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); -assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); -assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); -assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; -assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; -always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; -end -always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; -end -assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; -assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; -assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; -assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; -always @(*) begin - main_liteethmaccrc32checker_crc_error0 <= 1'd0; - main_liteethmaccrc32checker_crc_value <= 32'd0; - if (main_liteethmaccrc32checker_crc_be) begin - main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; - main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); - end -end -always @(*) begin - main_liteethmaccrc32checker_crc_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); -end -assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; -assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; -assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; -assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; -assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; -always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); +assign core_pulsesynchronizer0_o = (core_pulsesynchronizer0_toggle_o ^ core_pulsesynchronizer0_toggle_o_r); +assign core_liteethmaccrc32checker_fifo_full = (core_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign core_liteethmaccrc32checker_fifo_in = (core_liteethmaccrc32checker_sink_sink_valid & ((~core_liteethmaccrc32checker_fifo_full) | core_liteethmaccrc32checker_fifo_out)); +assign core_liteethmaccrc32checker_fifo_out = (core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready); +assign core_liteethmaccrc32checker_syncfifo_sink_first = core_liteethmaccrc32checker_sink_sink_first; +assign core_liteethmaccrc32checker_syncfifo_sink_last = core_liteethmaccrc32checker_sink_sink_last; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_data = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_last_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_error = core_liteethmaccrc32checker_sink_sink_payload_error; +always @(*) begin + core_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_sink_sink_valid; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_fifo_in; +end +always @(*) begin + core_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_syncfifo_sink_ready; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_fifo_in; +end +assign core_liteethmaccrc32checker_crc_data0 = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_crc_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_source_source_first = core_liteethmaccrc32checker_syncfifo_source_first; +assign core_liteethmaccrc32checker_source_source_payload_data = core_liteethmaccrc32checker_syncfifo_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_valid = core_bufferizeendpoints_source_source_valid; +assign core_bufferizeendpoints_source_source_ready = core_liteethmaccrc32checker_sink_sink_ready; +assign core_liteethmaccrc32checker_sink_sink_first = core_bufferizeendpoints_source_source_first; +assign core_liteethmaccrc32checker_sink_sink_last = core_bufferizeendpoints_source_source_last; +assign core_liteethmaccrc32checker_sink_sink_payload_data = core_bufferizeendpoints_source_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_payload_last_be = core_bufferizeendpoints_source_source_payload_last_be; +assign core_liteethmaccrc32checker_sink_sink_payload_error = core_bufferizeendpoints_source_source_payload_error; +assign core_liteethmaccrc32checker_crc_data1 = core_liteethmaccrc32checker_crc_data0; +assign core_liteethmaccrc32checker_crc_crc_prev = core_liteethmaccrc32checker_crc_reg; +always @(*) begin + core_liteethmaccrc32checker_crc_error0 <= 1'd0; + core_liteethmaccrc32checker_crc_value <= 32'd0; + if (core_liteethmaccrc32checker_crc_be) begin + core_liteethmaccrc32checker_crc_value <= ({core_liteethmaccrc32checker_crc_crc_next[0], core_liteethmaccrc32checker_crc_crc_next[1], core_liteethmaccrc32checker_crc_crc_next[2], core_liteethmaccrc32checker_crc_crc_next[3], core_liteethmaccrc32checker_crc_crc_next[4], core_liteethmaccrc32checker_crc_crc_next[5], core_liteethmaccrc32checker_crc_crc_next[6], core_liteethmaccrc32checker_crc_crc_next[7], core_liteethmaccrc32checker_crc_crc_next[8], core_liteethmaccrc32checker_crc_crc_next[9], core_liteethmaccrc32checker_crc_crc_next[10], core_liteethmaccrc32checker_crc_crc_next[11], core_liteethmaccrc32checker_crc_crc_next[12], core_liteethmaccrc32checker_crc_crc_next[13], core_liteethmaccrc32checker_crc_crc_next[14], core_liteethmaccrc32checker_crc_crc_next[15], core_liteethmaccrc32checker_crc_crc_next[16], core_liteethmaccrc32checker_crc_crc_next[17], core_liteethmaccrc32checker_crc_crc_next[18], core_liteethmaccrc32checker_crc_crc_next[19], core_liteethmaccrc32checker_crc_crc_next[20], core_liteethmaccrc32checker_crc_crc_next[21], core_liteethmaccrc32checker_crc_crc_next[22], core_liteethmaccrc32checker_crc_crc_next[23], core_liteethmaccrc32checker_crc_crc_next[24], core_liteethmaccrc32checker_crc_crc_next[25], core_liteethmaccrc32checker_crc_crc_next[26], core_liteethmaccrc32checker_crc_crc_next[27], core_liteethmaccrc32checker_crc_crc_next[28], core_liteethmaccrc32checker_crc_crc_next[29], core_liteethmaccrc32checker_crc_crc_next[30], core_liteethmaccrc32checker_crc_crc_next[31]} ^ 32'd4294967295); + core_liteethmaccrc32checker_crc_error0 <= (core_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + core_liteethmaccrc32checker_crc_crc_next <= 32'd0; + core_liteethmaccrc32checker_crc_crc_next[0] <= (((core_liteethmaccrc32checker_crc_crc_prev[24] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[1] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[25] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[26] ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[3] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[27] ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[28] ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((core_liteethmaccrc32checker_crc_crc_prev[29] ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((core_liteethmaccrc32checker_crc_crc_prev[30] ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[31] ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[0] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[1] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[2] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[3] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[4] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[5] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((core_liteethmaccrc32checker_crc_crc_prev[6] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[7] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[16] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[8] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[17] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[9] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[18] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[10] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[19] <= ((((core_liteethmaccrc32checker_crc_crc_prev[11] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[20] <= ((core_liteethmaccrc32checker_crc_crc_prev[12] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[21] <= ((core_liteethmaccrc32checker_crc_crc_prev[13] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next[22] <= ((core_liteethmaccrc32checker_crc_crc_prev[14] ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[23] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[15] ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[24] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[16] ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[25] <= ((((core_liteethmaccrc32checker_crc_crc_prev[17] ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[18] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[19] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[28] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[20] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[29] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[21] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[30] <= ((((core_liteethmaccrc32checker_crc_crc_prev[22] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[31] <= ((core_liteethmaccrc32checker_crc_crc_prev[23] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); +end +assign core_liteethmaccrc32checker_syncfifo_syncfifo_din = {core_liteethmaccrc32checker_syncfifo_fifo_in_last, core_liteethmaccrc32checker_syncfifo_fifo_in_first, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {core_liteethmaccrc32checker_syncfifo_fifo_out_last, core_liteethmaccrc32checker_syncfifo_fifo_out_first, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign core_liteethmaccrc32checker_syncfifo_sink_ready = core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_we = core_liteethmaccrc32checker_syncfifo_sink_valid; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_first = core_liteethmaccrc32checker_syncfifo_sink_first; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_last = core_liteethmaccrc32checker_syncfifo_sink_last; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = core_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = core_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign core_liteethmaccrc32checker_syncfifo_source_valid = core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign core_liteethmaccrc32checker_syncfifo_source_first = core_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign core_liteethmaccrc32checker_syncfifo_source_last = core_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign core_liteethmaccrc32checker_syncfifo_source_payload_data = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign core_liteethmaccrc32checker_syncfifo_source_payload_last_be = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_source_payload_error = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_re = core_liteethmaccrc32checker_syncfifo_source_ready; +always @(*) begin + core_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (core_liteethmaccrc32checker_syncfifo_replace) begin + core_liteethmaccrc32checker_syncfifo_wrport_adr <= (core_liteethmaccrc32checker_syncfifo_produce - 1'd1); end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; - end -end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; -assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); -assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); -assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); -assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); -always @(*) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - main_liteethmaccrc32checker_error <= 1'd0; - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; - main_liteethmaccrc32checker_source_source_last <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; - main_liteethmaccrc32checker_source_source_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; - case (builder_rxdatapath_bufferizeendpoints_state) + core_liteethmaccrc32checker_syncfifo_wrport_adr <= core_liteethmaccrc32checker_syncfifo_produce; + end +end +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_w = core_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign core_liteethmaccrc32checker_syncfifo_wrport_we = (core_liteethmaccrc32checker_syncfifo_syncfifo_we & (core_liteethmaccrc32checker_syncfifo_syncfifo_writable | core_liteethmaccrc32checker_syncfifo_replace)); +assign core_liteethmaccrc32checker_syncfifo_do_read = (core_liteethmaccrc32checker_syncfifo_syncfifo_readable & core_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign core_liteethmaccrc32checker_syncfifo_rdport_adr = core_liteethmaccrc32checker_syncfifo_consume; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_dout = core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_writable = (core_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign core_liteethmaccrc32checker_syncfifo_syncfifo_readable = (core_liteethmaccrc32checker_syncfifo_level != 1'd0); +always @(*) begin + core_liteethmaccrc32checker_crc_ce <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + core_liteethmaccrc32checker_crc_reset <= 1'd0; + core_liteethmaccrc32checker_error <= 1'd0; + core_liteethmaccrc32checker_fifo_reset <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + core_liteethmaccrc32checker_source_source_last <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + rxdatapath_bufferizeendpoints_next_state <= 2'd0; + core_liteethmaccrc32checker_source_source_payload_error <= core_liteethmaccrc32checker_syncfifo_source_payload_error; + rxdatapath_bufferizeendpoints_next_state <= rxdatapath_bufferizeendpoints_state; + case (rxdatapath_bufferizeendpoints_state) 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 2'd2; end end 2'd2: begin - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; - main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_fifo_out; + core_liteethmaccrc32checker_source_source_valid <= (core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_fifo_full); if (1'd1) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_sink_sink_payload_last_be; end else begin - if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + if ((core_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= (core_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); end else begin - main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; - main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + core_liteethmaccrc32checker_last_be_next_value0 <= (core_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + core_liteethmaccrc32checker_crc_error1_next_value1 <= core_liteethmaccrc32checker_crc_error0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; end end - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); - main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_sink_sink_payload_error | {1{(core_liteethmaccrc32checker_crc_error0 & core_liteethmaccrc32checker_sink_sink_last)}}); + core_liteethmaccrc32checker_error <= ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_last) & core_liteethmaccrc32checker_crc_error0); + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((core_liteethmaccrc32checker_sink_sink_last & (core_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + rxdatapath_bufferizeendpoints_next_state <= 2'd3; end else begin - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_liteethmaccrc32checker_sink_sink_last) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end end end 2'd3: begin - main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; - if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= core_liteethmaccrc32checker_syncfifo_source_valid; + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_source_source_ready; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_syncfifo_source_last; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_syncfifo_source_payload_error | {1{core_liteethmaccrc32checker_crc_error1}}); + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_last_be; + if ((core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready)) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + core_liteethmaccrc32checker_crc_reset <= 1'd1; + core_liteethmaccrc32checker_fifo_reset <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 1'd1; end endcase end -assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); -assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; -assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; -assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; -assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; -assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; -assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; -assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; -assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; -assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; -assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; -assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; -assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; -assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; -assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; -assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); -assign main_rx_padding_source_valid = main_rx_padding_sink_valid; -assign main_rx_padding_sink_ready = main_rx_padding_source_ready; -assign main_rx_padding_source_first = main_rx_padding_sink_first; -assign main_rx_padding_source_last = main_rx_padding_sink_last; -assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; -assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; -assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; -assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; -assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; -assign main_rx_last_be_source_first = main_rx_last_be_sink_first; -assign main_rx_last_be_source_last = main_rx_last_be_sink_last; -assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; -assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; -always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; +assign core_bufferizeendpoints_pipe_valid_sink_ready = ((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready); +assign core_bufferizeendpoints_pipe_valid_sink_valid = core_bufferizeendpoints_sink_sink_valid; +assign core_bufferizeendpoints_sink_sink_ready = core_bufferizeendpoints_pipe_valid_sink_ready; +assign core_bufferizeendpoints_pipe_valid_sink_first = core_bufferizeendpoints_sink_sink_first; +assign core_bufferizeendpoints_pipe_valid_sink_last = core_bufferizeendpoints_sink_sink_last; +assign core_bufferizeendpoints_pipe_valid_sink_payload_data = core_bufferizeendpoints_sink_sink_payload_data; +assign core_bufferizeendpoints_pipe_valid_sink_payload_last_be = core_bufferizeendpoints_sink_sink_payload_last_be; +assign core_bufferizeendpoints_pipe_valid_sink_payload_error = core_bufferizeendpoints_sink_sink_payload_error; +assign core_bufferizeendpoints_source_source_valid = core_bufferizeendpoints_pipe_valid_source_valid; +assign core_bufferizeendpoints_pipe_valid_source_ready = core_bufferizeendpoints_source_source_ready; +assign core_bufferizeendpoints_source_source_first = core_bufferizeendpoints_pipe_valid_source_first; +assign core_bufferizeendpoints_source_source_last = core_bufferizeendpoints_pipe_valid_source_last; +assign core_bufferizeendpoints_source_source_payload_data = core_bufferizeendpoints_pipe_valid_source_payload_data; +assign core_bufferizeendpoints_source_source_payload_last_be = core_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign core_bufferizeendpoints_source_source_payload_error = core_bufferizeendpoints_pipe_valid_source_payload_error; +assign core_pulsesynchronizer1_o = (core_pulsesynchronizer1_toggle_o ^ core_pulsesynchronizer1_toggle_o_r); +assign core_rx_padding_source_valid = core_rx_padding_sink_valid; +assign core_rx_padding_sink_ready = core_rx_padding_source_ready; +assign core_rx_padding_source_first = core_rx_padding_sink_first; +assign core_rx_padding_source_last = core_rx_padding_sink_last; +assign core_rx_padding_source_payload_data = core_rx_padding_sink_payload_data; +assign core_rx_padding_source_payload_last_be = core_rx_padding_sink_payload_last_be; +assign core_rx_padding_source_payload_error = core_rx_padding_sink_payload_error; +assign core_rx_last_be_source_valid = core_rx_last_be_sink_valid; +assign core_rx_last_be_sink_ready = core_rx_last_be_source_ready; +assign core_rx_last_be_source_first = core_rx_last_be_sink_first; +assign core_rx_last_be_source_last = core_rx_last_be_sink_last; +assign core_rx_last_be_source_payload_data = core_rx_last_be_sink_payload_data; +assign core_rx_last_be_source_payload_error = core_rx_last_be_sink_payload_error; +always @(*) begin + core_rx_last_be_source_payload_last_be <= 1'd0; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_payload_last_be; if (1'd1) begin - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; - end -end -assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; -assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; -assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; -assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; -assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; -assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; -assign main_rx_converter_source_first = main_rx_converter_source_source_first; -assign main_rx_converter_source_last = main_rx_converter_source_source_last; -assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; -always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; -end -always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; -end -always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; -end -assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; -assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; -assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; -assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; -assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; -assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); -assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; -assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; -assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; -assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; -assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; -assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; -assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; -assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; -assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; -assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; -assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; -assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; -assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; -assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; -assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; -assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; -assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; -assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; -assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; -assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; -assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; -assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; -assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; -assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; -assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; -assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; -assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; -assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; -assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; -assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; -assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; -assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); -assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); -assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); -assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); -assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; -assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; -assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; -always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_last; + end +end +assign core_rx_converter_converter_sink_valid = core_rx_converter_sink_valid; +assign core_rx_converter_converter_sink_first = core_rx_converter_sink_first; +assign core_rx_converter_converter_sink_last = core_rx_converter_sink_last; +assign core_rx_converter_sink_ready = core_rx_converter_converter_sink_ready; +assign core_rx_converter_converter_sink_payload_data = {core_rx_converter_sink_payload_error, core_rx_converter_sink_payload_last_be, core_rx_converter_sink_payload_data}; +assign core_rx_converter_source_valid = core_rx_converter_source_source_valid; +assign core_rx_converter_source_first = core_rx_converter_source_source_first; +assign core_rx_converter_source_last = core_rx_converter_source_source_last; +assign core_rx_converter_source_source_ready = core_rx_converter_source_ready; +always @(*) begin + core_rx_converter_source_payload_data <= 32'd0; + core_rx_converter_source_payload_data[7:0] <= core_rx_converter_source_source_payload_data[7:0]; + core_rx_converter_source_payload_data[15:8] <= core_rx_converter_source_source_payload_data[17:10]; + core_rx_converter_source_payload_data[23:16] <= core_rx_converter_source_source_payload_data[27:20]; + core_rx_converter_source_payload_data[31:24] <= core_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + core_rx_converter_source_payload_last_be <= 4'd0; + core_rx_converter_source_payload_last_be[0] <= core_rx_converter_source_source_payload_data[8]; + core_rx_converter_source_payload_last_be[1] <= core_rx_converter_source_source_payload_data[18]; + core_rx_converter_source_payload_last_be[2] <= core_rx_converter_source_source_payload_data[28]; + core_rx_converter_source_payload_last_be[3] <= core_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + core_rx_converter_source_payload_error <= 4'd0; + core_rx_converter_source_payload_error[0] <= core_rx_converter_source_source_payload_data[9]; + core_rx_converter_source_payload_error[1] <= core_rx_converter_source_source_payload_data[19]; + core_rx_converter_source_payload_error[2] <= core_rx_converter_source_source_payload_data[29]; + core_rx_converter_source_payload_error[3] <= core_rx_converter_source_source_payload_data[39]; +end +assign core_rx_converter_source_source_valid = core_rx_converter_converter_source_valid; +assign core_rx_converter_converter_source_ready = core_rx_converter_source_source_ready; +assign core_rx_converter_source_source_first = core_rx_converter_converter_source_first; +assign core_rx_converter_source_source_last = core_rx_converter_converter_source_last; +assign core_rx_converter_source_source_payload_data = core_rx_converter_converter_source_payload_data; +assign core_rx_converter_converter_sink_ready = ((~core_rx_converter_converter_strobe_all) | core_rx_converter_converter_source_ready); +assign core_rx_converter_converter_source_valid = core_rx_converter_converter_strobe_all; +assign core_rx_converter_converter_load_part = (core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready); +assign core_rx_cdc_cdc_sink_valid = core_rx_cdc_sink_sink_valid; +assign core_rx_cdc_sink_sink_ready = core_rx_cdc_cdc_sink_ready; +assign core_rx_cdc_cdc_sink_first = core_rx_cdc_sink_sink_first; +assign core_rx_cdc_cdc_sink_last = core_rx_cdc_sink_sink_last; +assign core_rx_cdc_cdc_sink_payload_data = core_rx_cdc_sink_sink_payload_data; +assign core_rx_cdc_cdc_sink_payload_last_be = core_rx_cdc_sink_sink_payload_last_be; +assign core_rx_cdc_cdc_sink_payload_error = core_rx_cdc_sink_sink_payload_error; +assign core_rx_cdc_source_source_valid = core_rx_cdc_cdc_source_valid; +assign core_rx_cdc_cdc_source_ready = core_rx_cdc_source_source_ready; +assign core_rx_cdc_source_source_first = core_rx_cdc_cdc_source_first; +assign core_rx_cdc_source_source_last = core_rx_cdc_cdc_source_last; +assign core_rx_cdc_source_source_payload_data = core_rx_cdc_cdc_source_payload_data; +assign core_rx_cdc_source_source_payload_last_be = core_rx_cdc_cdc_source_payload_last_be; +assign core_rx_cdc_source_source_payload_error = core_rx_cdc_cdc_source_payload_error; +assign core_rx_cdc_cdc_asyncfifo_din = {core_rx_cdc_cdc_fifo_in_last, core_rx_cdc_cdc_fifo_in_first, core_rx_cdc_cdc_fifo_in_payload_error, core_rx_cdc_cdc_fifo_in_payload_last_be, core_rx_cdc_cdc_fifo_in_payload_data}; +assign {core_rx_cdc_cdc_fifo_out_last, core_rx_cdc_cdc_fifo_out_first, core_rx_cdc_cdc_fifo_out_payload_error, core_rx_cdc_cdc_fifo_out_payload_last_be, core_rx_cdc_cdc_fifo_out_payload_data} = core_rx_cdc_cdc_asyncfifo_dout; +assign core_rx_cdc_cdc_sink_ready = core_rx_cdc_cdc_asyncfifo_writable; +assign core_rx_cdc_cdc_asyncfifo_we = core_rx_cdc_cdc_sink_valid; +assign core_rx_cdc_cdc_fifo_in_first = core_rx_cdc_cdc_sink_first; +assign core_rx_cdc_cdc_fifo_in_last = core_rx_cdc_cdc_sink_last; +assign core_rx_cdc_cdc_fifo_in_payload_data = core_rx_cdc_cdc_sink_payload_data; +assign core_rx_cdc_cdc_fifo_in_payload_last_be = core_rx_cdc_cdc_sink_payload_last_be; +assign core_rx_cdc_cdc_fifo_in_payload_error = core_rx_cdc_cdc_sink_payload_error; +assign core_rx_cdc_cdc_source_valid = core_rx_cdc_cdc_asyncfifo_readable; +assign core_rx_cdc_cdc_source_first = core_rx_cdc_cdc_fifo_out_first; +assign core_rx_cdc_cdc_source_last = core_rx_cdc_cdc_fifo_out_last; +assign core_rx_cdc_cdc_source_payload_data = core_rx_cdc_cdc_fifo_out_payload_data; +assign core_rx_cdc_cdc_source_payload_last_be = core_rx_cdc_cdc_fifo_out_payload_last_be; +assign core_rx_cdc_cdc_source_payload_error = core_rx_cdc_cdc_fifo_out_payload_error; +assign core_rx_cdc_cdc_asyncfifo_re = core_rx_cdc_cdc_source_ready; +assign core_rx_cdc_cdc_graycounter0_ce = (core_rx_cdc_cdc_asyncfifo_writable & core_rx_cdc_cdc_asyncfifo_we); +assign core_rx_cdc_cdc_graycounter1_ce = (core_rx_cdc_cdc_asyncfifo_readable & core_rx_cdc_cdc_asyncfifo_re); +assign core_rx_cdc_cdc_asyncfifo_writable = (((core_rx_cdc_cdc_graycounter0_q[5] == core_rx_cdc_cdc_consume_wdomain[5]) | (core_rx_cdc_cdc_graycounter0_q[4] == core_rx_cdc_cdc_consume_wdomain[4])) | (core_rx_cdc_cdc_graycounter0_q[3:0] != core_rx_cdc_cdc_consume_wdomain[3:0])); +assign core_rx_cdc_cdc_asyncfifo_readable = (core_rx_cdc_cdc_graycounter1_q != core_rx_cdc_cdc_produce_rdomain); +assign core_rx_cdc_cdc_wrport_adr = core_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_rx_cdc_cdc_wrport_dat_w = core_rx_cdc_cdc_asyncfifo_din; +assign core_rx_cdc_cdc_wrport_we = core_rx_cdc_cdc_graycounter0_ce; +assign core_rx_cdc_cdc_rdport_adr = core_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_rx_cdc_cdc_asyncfifo_dout = core_rx_cdc_cdc_rdport_dat_r; +always @(*) begin + core_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter0_ce) begin + core_rx_cdc_cdc_graycounter0_q_next_binary <= (core_rx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + core_rx_cdc_cdc_graycounter0_q_next_binary <= core_rx_cdc_cdc_graycounter0_q_binary; end end -assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_rx_cdc_cdc_graycounter0_q_next = (core_rx_cdc_cdc_graycounter0_q_next_binary ^ core_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter1_ce) begin + core_rx_cdc_cdc_graycounter1_q_next_binary <= (core_rx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; - end -end -assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_rx_preamble_sink_valid = main_maccore_liteethphymiirx_source_valid; -assign main_maccore_liteethphymiirx_source_ready = main_rx_preamble_sink_ready; -assign main_rx_preamble_sink_first = main_maccore_liteethphymiirx_source_first; -assign main_rx_preamble_sink_last = main_maccore_liteethphymiirx_source_last; -assign main_rx_preamble_sink_payload_data = main_maccore_liteethphymiirx_source_payload_data; -assign main_rx_preamble_sink_payload_last_be = main_maccore_liteethphymiirx_source_payload_last_be; -assign main_rx_preamble_sink_payload_error = main_maccore_liteethphymiirx_source_payload_error; -assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; -assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; -assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; -assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; -assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; -assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; -assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; -assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; -assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; -assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_rx_padding_source_first; -assign main_rx_last_be_sink_last = main_rx_padding_source_last; -assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; -assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; -assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; -assign main_rx_converter_sink_first = main_rx_last_be_source_first; -assign main_rx_converter_sink_last = main_rx_last_be_source_last; -assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; -assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; -assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; -assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; -assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; -assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; -assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; -assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; -assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; -assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_source_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_source_ready; -assign main_source_first = main_rx_cdc_source_source_first; -assign main_source_last = main_rx_cdc_source_source_last; -assign main_source_payload_data = main_rx_cdc_source_source_payload_data; -assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_source_payload_error = main_rx_cdc_source_source_payload_error; -assign main_sram0_sink_valid = main_sink_sink_valid; -assign main_sink_sink_ready = main_sram1_sink_ready; -assign main_sram2_sink_first = main_sink_sink_first; -assign main_sram3_sink_last = main_sink_sink_last; -assign main_sram4_sink_payload_data = main_sink_sink_payload_data; -assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; -assign main_sram6_sink_payload_error = main_sink_sink_payload_error; -assign main_source_source_valid = main_sram83_source_valid; -assign main_sram84_source_ready = main_source_source_ready; -assign main_source_source_first = main_sram85_source_first; -assign main_source_source_last = main_sram86_source_last; -assign main_source_source_payload_data = main_sram87_source_payload_data; -assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; -assign main_source_source_payload_error = main_sram89_source_payload_error; -always @(*) begin - main_length_inc <= 4'd0; - case (main_sram5_sink_payload_last_be) + core_rx_cdc_cdc_graycounter1_q_next_binary <= core_rx_cdc_cdc_graycounter1_q_binary; + end +end +assign core_rx_cdc_cdc_graycounter1_q_next = (core_rx_cdc_cdc_graycounter1_q_next_binary ^ core_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_rx_preamble_sink_valid = maccore_liteethphymiirx_source_valid; +assign maccore_liteethphymiirx_source_ready = core_rx_preamble_sink_ready; +assign core_rx_preamble_sink_first = maccore_liteethphymiirx_source_first; +assign core_rx_preamble_sink_last = maccore_liteethphymiirx_source_last; +assign core_rx_preamble_sink_payload_data = maccore_liteethphymiirx_source_payload_data; +assign core_rx_preamble_sink_payload_last_be = maccore_liteethphymiirx_source_payload_last_be; +assign core_rx_preamble_sink_payload_error = maccore_liteethphymiirx_source_payload_error; +assign core_bufferizeendpoints_sink_sink_valid = core_rx_preamble_source_valid; +assign core_rx_preamble_source_ready = core_bufferizeendpoints_sink_sink_ready; +assign core_bufferizeendpoints_sink_sink_first = core_rx_preamble_source_first; +assign core_bufferizeendpoints_sink_sink_last = core_rx_preamble_source_last; +assign core_bufferizeendpoints_sink_sink_payload_data = core_rx_preamble_source_payload_data; +assign core_bufferizeendpoints_sink_sink_payload_last_be = core_rx_preamble_source_payload_last_be; +assign core_bufferizeendpoints_sink_sink_payload_error = core_rx_preamble_source_payload_error; +assign core_rx_padding_sink_valid = core_liteethmaccrc32checker_source_source_valid; +assign core_liteethmaccrc32checker_source_source_ready = core_rx_padding_sink_ready; +assign core_rx_padding_sink_first = core_liteethmaccrc32checker_source_source_first; +assign core_rx_padding_sink_last = core_liteethmaccrc32checker_source_source_last; +assign core_rx_padding_sink_payload_data = core_liteethmaccrc32checker_source_source_payload_data; +assign core_rx_padding_sink_payload_last_be = core_liteethmaccrc32checker_source_source_payload_last_be; +assign core_rx_padding_sink_payload_error = core_liteethmaccrc32checker_source_source_payload_error; +assign core_rx_last_be_sink_valid = core_rx_padding_source_valid; +assign core_rx_padding_source_ready = core_rx_last_be_sink_ready; +assign core_rx_last_be_sink_first = core_rx_padding_source_first; +assign core_rx_last_be_sink_last = core_rx_padding_source_last; +assign core_rx_last_be_sink_payload_data = core_rx_padding_source_payload_data; +assign core_rx_last_be_sink_payload_last_be = core_rx_padding_source_payload_last_be; +assign core_rx_last_be_sink_payload_error = core_rx_padding_source_payload_error; +assign core_rx_converter_sink_valid = core_rx_last_be_source_valid; +assign core_rx_last_be_source_ready = core_rx_converter_sink_ready; +assign core_rx_converter_sink_first = core_rx_last_be_source_first; +assign core_rx_converter_sink_last = core_rx_last_be_source_last; +assign core_rx_converter_sink_payload_data = core_rx_last_be_source_payload_data; +assign core_rx_converter_sink_payload_last_be = core_rx_last_be_source_payload_last_be; +assign core_rx_converter_sink_payload_error = core_rx_last_be_source_payload_error; +assign core_rx_cdc_sink_sink_valid = core_rx_converter_source_valid; +assign core_rx_converter_source_ready = core_rx_cdc_sink_sink_ready; +assign core_rx_cdc_sink_sink_first = core_rx_converter_source_first; +assign core_rx_cdc_sink_sink_last = core_rx_converter_source_last; +assign core_rx_cdc_sink_sink_payload_data = core_rx_converter_source_payload_data; +assign core_rx_cdc_sink_sink_payload_last_be = core_rx_converter_source_payload_last_be; +assign core_rx_cdc_sink_sink_payload_error = core_rx_converter_source_payload_error; +assign core_source_valid = core_rx_cdc_source_source_valid; +assign core_rx_cdc_source_source_ready = core_source_ready; +assign core_source_first = core_rx_cdc_source_source_first; +assign core_source_last = core_rx_cdc_source_source_last; +assign core_source_payload_data = core_rx_cdc_source_source_payload_data; +assign core_source_payload_last_be = core_rx_cdc_source_source_payload_last_be; +assign core_source_payload_error = core_rx_cdc_source_source_payload_error; +assign wishbone_interface_writer_sink_sink_valid = wishbone_interface_sink_valid; +assign wishbone_interface_sink_ready = wishbone_interface_writer_sink_sink_ready; +assign wishbone_interface_writer_sink_sink_first = wishbone_interface_sink_first; +assign wishbone_interface_writer_sink_sink_last = wishbone_interface_sink_last; +assign wishbone_interface_writer_sink_sink_payload_data = wishbone_interface_sink_payload_data; +assign wishbone_interface_writer_sink_sink_payload_last_be = wishbone_interface_sink_payload_last_be; +assign wishbone_interface_writer_sink_sink_payload_error = wishbone_interface_sink_payload_error; +assign wishbone_interface_source_valid = wishbone_interface_reader_source_source_valid; +assign wishbone_interface_reader_source_source_ready = wishbone_interface_source_ready; +assign wishbone_interface_source_first = wishbone_interface_reader_source_source_first; +assign wishbone_interface_source_last = wishbone_interface_reader_source_source_last; +assign wishbone_interface_source_payload_data = wishbone_interface_reader_source_source_payload_data; +assign wishbone_interface_source_payload_last_be = wishbone_interface_reader_source_source_payload_last_be; +assign wishbone_interface_source_payload_error = wishbone_interface_reader_source_source_payload_error; +always @(*) begin + wishbone_interface_writer_length_inc <= 4'd0; + case (wishbone_interface_writer_sink_sink_payload_last_be) 1'd1: begin - main_length_inc <= 1'd1; + wishbone_interface_writer_length_inc <= 1'd1; end 2'd2: begin - main_length_inc <= 2'd2; + wishbone_interface_writer_length_inc <= 2'd2; end 3'd4: begin - main_length_inc <= 2'd3; + wishbone_interface_writer_length_inc <= 2'd3; end 4'd8: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end 5'd16: begin - main_length_inc <= 3'd5; + wishbone_interface_writer_length_inc <= 3'd5; end 6'd32: begin - main_length_inc <= 3'd6; + wishbone_interface_writer_length_inc <= 3'd6; end 7'd64: begin - main_length_inc <= 3'd7; + wishbone_interface_writer_length_inc <= 3'd7; end default: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end endcase end -assign main_sram44_source_ready = main_sram20_clear; -assign main_sram19_trigger = main_sram43_source_valid; -assign main_sram7_status = main_sram47_source_payload_slot; -assign main_sram10_status = main_sram48_source_payload_length; -assign main_wr_data = main_sram4_sink_payload_data; -always @(*) begin - main_sram75_adr <= 9'd0; - main_sram77_we <= 1'd0; - main_sram78_dat_w <= 32'd0; - main_sram79_adr <= 9'd0; - main_sram81_we <= 1'd0; - main_sram82_dat_w <= 32'd0; - case (main_slot) +assign wishbone_interface_writer_stat_fifo_source_ready = wishbone_interface_writer_available_clear; +assign wishbone_interface_writer_available_trigger = wishbone_interface_writer_stat_fifo_source_valid; +assign wishbone_interface_writer_slot_status = wishbone_interface_writer_stat_fifo_source_payload_slot; +assign wishbone_interface_writer_length_status = wishbone_interface_writer_stat_fifo_source_payload_length; +assign wishbone_interface_writer_wr_data = wishbone_interface_writer_sink_sink_payload_data; +always @(*) begin + wishbone_interface_writer_memory0_adr <= 9'd0; + wishbone_interface_writer_memory0_dat_w <= 32'd0; + wishbone_interface_writer_memory0_we <= 1'd0; + wishbone_interface_writer_memory1_adr <= 9'd0; + wishbone_interface_writer_memory1_dat_w <= 32'd0; + wishbone_interface_writer_memory1_we <= 1'd0; + case (wishbone_interface_writer_slot) 1'd0: begin - main_sram75_adr <= main_sram35_length[10:2]; - main_sram78_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram77_we <= 1'd1; + wishbone_interface_writer_memory0_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory0_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory0_we <= 1'd1; end end 1'd1: begin - main_sram79_adr <= main_sram35_length[10:2]; - main_sram82_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram81_we <= 1'd1; + wishbone_interface_writer_memory1_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory1_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory1_we <= 1'd1; end end endcase end -assign main_sram21_available = main_sram17_status; -assign main_sram25_available = main_sram18_pending; -always @(*) begin - main_sram20_clear <= 1'd0; - if ((main_sram28_re & main_sram29_r)) begin - main_sram20_clear <= 1'd1; - end -end -assign main_sram16_irq = (main_sram26_status & main_sram31_storage); -assign main_sram17_status = main_sram19_trigger; -assign main_sram18_pending = main_sram19_trigger; -assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; -assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; -assign main_sram38_sink_ready = main_sram50_writable; -assign main_sram49_we = main_sram37_sink_valid; -assign main_sram68_fifo_in_first = main_sram39_sink_first; -assign main_sram69_fifo_in_last = main_sram40_sink_last; -assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; -assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; -assign main_sram43_source_valid = main_sram52_readable; -assign main_sram45_source_first = main_sram72_fifo_out_first; -assign main_sram46_source_last = main_sram73_fifo_out_last; -assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; -assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; -assign main_sram51_re = main_sram44_source_ready; -always @(*) begin - main_sram59_adr <= 1'd0; - if (main_sram56_replace) begin - main_sram59_adr <= (main_sram57_produce - 1'd1); +assign wishbone_interface_writer_available0 = wishbone_interface_writer_available_status; +assign wishbone_interface_writer_available1 = wishbone_interface_writer_available_pending; +always @(*) begin + wishbone_interface_writer_available_clear <= 1'd0; + if ((wishbone_interface_writer_pending_re & wishbone_interface_writer_pending_r)) begin + wishbone_interface_writer_available_clear <= 1'd1; + end +end +assign wishbone_interface_writer_irq = (wishbone_interface_writer_pending_status & wishbone_interface_writer_enable_storage); +assign wishbone_interface_writer_available_status = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_available_pending = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_stat_fifo_syncfifo_din = {wishbone_interface_writer_stat_fifo_fifo_in_last, wishbone_interface_writer_stat_fifo_fifo_in_first, wishbone_interface_writer_stat_fifo_fifo_in_payload_length, wishbone_interface_writer_stat_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_writer_stat_fifo_fifo_out_last, wishbone_interface_writer_stat_fifo_fifo_out_first, wishbone_interface_writer_stat_fifo_fifo_out_payload_length, wishbone_interface_writer_stat_fifo_fifo_out_payload_slot} = wishbone_interface_writer_stat_fifo_syncfifo_dout; +assign wishbone_interface_writer_stat_fifo_sink_ready = wishbone_interface_writer_stat_fifo_syncfifo_writable; +assign wishbone_interface_writer_stat_fifo_syncfifo_we = wishbone_interface_writer_stat_fifo_sink_valid; +assign wishbone_interface_writer_stat_fifo_fifo_in_first = wishbone_interface_writer_stat_fifo_sink_first; +assign wishbone_interface_writer_stat_fifo_fifo_in_last = wishbone_interface_writer_stat_fifo_sink_last; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_slot = wishbone_interface_writer_stat_fifo_sink_payload_slot; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_length = wishbone_interface_writer_stat_fifo_sink_payload_length; +assign wishbone_interface_writer_stat_fifo_source_valid = wishbone_interface_writer_stat_fifo_syncfifo_readable; +assign wishbone_interface_writer_stat_fifo_source_first = wishbone_interface_writer_stat_fifo_fifo_out_first; +assign wishbone_interface_writer_stat_fifo_source_last = wishbone_interface_writer_stat_fifo_fifo_out_last; +assign wishbone_interface_writer_stat_fifo_source_payload_slot = wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +assign wishbone_interface_writer_stat_fifo_source_payload_length = wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +assign wishbone_interface_writer_stat_fifo_syncfifo_re = wishbone_interface_writer_stat_fifo_source_ready; +always @(*) begin + wishbone_interface_writer_stat_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_writer_stat_fifo_replace) begin + wishbone_interface_writer_stat_fifo_wrport_adr <= (wishbone_interface_writer_stat_fifo_produce - 1'd1); end else begin - main_sram59_adr <= main_sram57_produce; - end -end -assign main_sram62_dat_w = main_sram53_din; -assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); -assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); -assign main_sram64_adr = main_sram58_consume; -assign main_sram54_dout = main_sram65_dat_r; -assign main_sram50_writable = (main_sram55_level != 2'd2); -assign main_sram52_readable = (main_sram55_level != 1'd0); -always @(*) begin - builder_liteethmacsramwriter_next_state <= 3'd0; - main_slot_liteethmacsramwriter_next_value <= 1'd0; - main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; - main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; - main_sram37_sink_valid <= 1'd0; - main_sram41_sink_payload_slot <= 1'd0; - main_sram42_sink_payload_length <= 11'd0; - main_write <= 1'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) + wishbone_interface_writer_stat_fifo_wrport_adr <= wishbone_interface_writer_stat_fifo_produce; + end +end +assign wishbone_interface_writer_stat_fifo_wrport_dat_w = wishbone_interface_writer_stat_fifo_syncfifo_din; +assign wishbone_interface_writer_stat_fifo_wrport_we = (wishbone_interface_writer_stat_fifo_syncfifo_we & (wishbone_interface_writer_stat_fifo_syncfifo_writable | wishbone_interface_writer_stat_fifo_replace)); +assign wishbone_interface_writer_stat_fifo_do_read = (wishbone_interface_writer_stat_fifo_syncfifo_readable & wishbone_interface_writer_stat_fifo_syncfifo_re); +assign wishbone_interface_writer_stat_fifo_rdport_adr = wishbone_interface_writer_stat_fifo_consume; +assign wishbone_interface_writer_stat_fifo_syncfifo_dout = wishbone_interface_writer_stat_fifo_rdport_dat_r; +assign wishbone_interface_writer_stat_fifo_syncfifo_writable = (wishbone_interface_writer_stat_fifo_level != 2'd2); +assign wishbone_interface_writer_stat_fifo_syncfifo_readable = (wishbone_interface_writer_stat_fifo_level != 1'd0); +always @(*) begin + liteethmacsramwriter_next_state <= 3'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= 32'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 11'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_payload_length <= 11'd0; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd0; + wishbone_interface_writer_write <= 1'd0; + liteethmacsramwriter_next_state <= liteethmacsramwriter_state; + case (liteethmacsramwriter_state) 1'd1: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end 2'd2: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if ((main_sram5_sink_payload_last_be != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if ((wishbone_interface_writer_sink_sink_payload_last_be != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end end end 2'd3: begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end 3'd4: begin - main_sram37_sink_valid <= 1'd1; - main_sram41_sink_payload_slot <= main_slot; - main_sram42_sink_payload_length <= main_sram35_length; - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); - main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd1; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= wishbone_interface_writer_slot; + wishbone_interface_writer_stat_fifo_sink_payload_length <= wishbone_interface_writer_length; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= (wishbone_interface_writer_slot + 1'd1); + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end default: begin - if (main_sram0_sink_valid) begin - if (main_sram38_sink_ready) begin - main_write <= 1'd1; - main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - if ((main_sram35_length >= 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 1'd1; + if (wishbone_interface_writer_sink_sink_valid) begin + if (wishbone_interface_writer_stat_fifo_sink_ready) begin + wishbone_interface_writer_write <= 1'd1; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= (wishbone_interface_writer_length + wishbone_interface_writer_length_inc); + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((wishbone_interface_writer_length >= 11'd1530)) begin + liteethmacsramwriter_next_state <= 1'd1; end - if (main_sram3_sink_last) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if (wishbone_interface_writer_sink_sink_last) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end else begin - main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd2; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= (wishbone_interface_writer_errors_status + 1'd1); + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 2'd2; end end end endcase end -assign main_sram123_sink_valid = main_start_re; -assign main_sram127_sink_payload_slot = main_sram100_storage; -assign main_sram128_sink_payload_length = main_sram102_storage; -assign main_sram94_status = main_sram124_sink_ready; -assign main_sram97_status = main_sram141_level; +assign wishbone_interface_reader_cmd_fifo_sink_valid = wishbone_interface_reader_start_re; +assign wishbone_interface_reader_cmd_fifo_sink_payload_slot = wishbone_interface_reader_slot_storage; +assign wishbone_interface_reader_cmd_fifo_sink_payload_length = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_ready_status = wishbone_interface_reader_cmd_fifo_sink_ready; +assign wishbone_interface_reader_level_status = wishbone_interface_reader_cmd_fifo_level; always @(*) begin - main_sram88_source_payload_last_be <= 4'd0; - if (main_sram86_source_last) begin - case (main_sram134_source_payload_length[1:0]) + wishbone_interface_reader_source_source_payload_last_be <= 4'd0; + if (wishbone_interface_reader_source_source_last) begin + case (wishbone_interface_reader_cmd_fifo_source_payload_length[1:0]) 1'd1: begin - main_sram88_source_payload_last_be <= 1'd1; + wishbone_interface_reader_source_source_payload_last_be <= 1'd1; end 2'd2: begin - main_sram88_source_payload_last_be <= 2'd2; + wishbone_interface_reader_source_source_payload_last_be <= 2'd2; end 2'd3: begin - main_sram88_source_payload_last_be <= 3'd4; + wishbone_interface_reader_source_source_payload_last_be <= 3'd4; end 3'd4: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end 3'd5: begin - main_sram88_source_payload_last_be <= 5'd16; + wishbone_interface_reader_source_source_payload_last_be <= 5'd16; end 3'd6: begin - main_sram88_source_payload_last_be <= 6'd32; + wishbone_interface_reader_source_source_payload_last_be <= 6'd32; end 3'd7: begin - main_sram88_source_payload_last_be <= 7'd64; + wishbone_interface_reader_source_source_payload_last_be <= 7'd64; end default: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end endcase end end -assign main_sram163_re = main_read; -assign main_sram161_adr = main_sram122_length[10:2]; -assign main_sram166_re = main_read; -assign main_sram164_adr = main_sram122_length[10:2]; +assign wishbone_interface_reader_memory0_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory0_adr = wishbone_interface_reader_length[10:2]; +assign wishbone_interface_reader_memory1_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory1_adr = wishbone_interface_reader_length[10:2]; always @(*) begin - main_rd_data <= 32'd0; - case (main_sram133_source_payload_slot) + wishbone_interface_reader_rd_data <= 32'd0; + case (wishbone_interface_reader_cmd_fifo_source_payload_slot) 1'd0: begin - main_rd_data <= main_sram162_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory0_dat_r; end 1'd1: begin - main_rd_data <= main_sram165_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory1_dat_r; end endcase end -assign main_sram87_source_payload_data = main_rd_data; -assign main_sram109_event0 = main_sram105_status; -assign main_sram113_event0 = main_sram106_pending; -always @(*) begin - main_sram108_clear <= 1'd0; - if ((main_sram116_re & main_sram117_r)) begin - main_sram108_clear <= 1'd1; - end -end -assign main_sram104_irq = (main_sram114_status & main_sram119_storage); -assign main_sram105_status = 1'd0; -assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; -assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; -assign main_sram124_sink_ready = main_sram136_writable; -assign main_sram135_we = main_sram123_sink_valid; -assign main_sram154_fifo_in_first = main_sram125_sink_first; -assign main_sram155_fifo_in_last = main_sram126_sink_last; -assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; -assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; -assign main_sram129_source_valid = main_sram138_readable; -assign main_sram131_source_first = main_sram158_fifo_out_first; -assign main_sram132_source_last = main_sram159_fifo_out_last; -assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; -assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; -assign main_sram137_re = main_sram130_source_ready; -always @(*) begin - main_sram145_adr <= 1'd0; - if (main_sram142_replace) begin - main_sram145_adr <= (main_sram143_produce - 1'd1); +assign wishbone_interface_reader_source_source_payload_data = wishbone_interface_reader_rd_data; +assign wishbone_interface_reader_event00 = wishbone_interface_reader_eventsourcepulse_status; +assign wishbone_interface_reader_event01 = wishbone_interface_reader_eventsourcepulse_pending; +always @(*) begin + wishbone_interface_reader_eventsourcepulse_clear <= 1'd0; + if ((wishbone_interface_reader_pending_re & wishbone_interface_reader_pending_r)) begin + wishbone_interface_reader_eventsourcepulse_clear <= 1'd1; + end +end +assign wishbone_interface_reader_irq = (wishbone_interface_reader_pending_status & wishbone_interface_reader_enable_storage); +assign wishbone_interface_reader_eventsourcepulse_status = 1'd0; +assign wishbone_interface_reader_cmd_fifo_syncfifo_din = {wishbone_interface_reader_cmd_fifo_fifo_in_last, wishbone_interface_reader_cmd_fifo_fifo_in_first, wishbone_interface_reader_cmd_fifo_fifo_in_payload_length, wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_reader_cmd_fifo_fifo_out_last, wishbone_interface_reader_cmd_fifo_fifo_out_first, wishbone_interface_reader_cmd_fifo_fifo_out_payload_length, wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot} = wishbone_interface_reader_cmd_fifo_syncfifo_dout; +assign wishbone_interface_reader_cmd_fifo_sink_ready = wishbone_interface_reader_cmd_fifo_syncfifo_writable; +assign wishbone_interface_reader_cmd_fifo_syncfifo_we = wishbone_interface_reader_cmd_fifo_sink_valid; +assign wishbone_interface_reader_cmd_fifo_fifo_in_first = wishbone_interface_reader_cmd_fifo_sink_first; +assign wishbone_interface_reader_cmd_fifo_fifo_in_last = wishbone_interface_reader_cmd_fifo_sink_last; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot = wishbone_interface_reader_cmd_fifo_sink_payload_slot; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_length = wishbone_interface_reader_cmd_fifo_sink_payload_length; +assign wishbone_interface_reader_cmd_fifo_source_valid = wishbone_interface_reader_cmd_fifo_syncfifo_readable; +assign wishbone_interface_reader_cmd_fifo_source_first = wishbone_interface_reader_cmd_fifo_fifo_out_first; +assign wishbone_interface_reader_cmd_fifo_source_last = wishbone_interface_reader_cmd_fifo_fifo_out_last; +assign wishbone_interface_reader_cmd_fifo_source_payload_slot = wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +assign wishbone_interface_reader_cmd_fifo_source_payload_length = wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +assign wishbone_interface_reader_cmd_fifo_syncfifo_re = wishbone_interface_reader_cmd_fifo_source_ready; +always @(*) begin + wishbone_interface_reader_cmd_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_reader_cmd_fifo_replace) begin + wishbone_interface_reader_cmd_fifo_wrport_adr <= (wishbone_interface_reader_cmd_fifo_produce - 1'd1); end else begin - main_sram145_adr <= main_sram143_produce; - end -end -assign main_sram148_dat_w = main_sram139_din; -assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); -assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); -assign main_sram150_adr = main_sram144_consume; -assign main_sram140_dout = main_sram151_dat_r; -assign main_sram136_writable = (main_sram141_level != 2'd2); -assign main_sram138_readable = (main_sram141_level != 1'd0); -always @(*) begin - builder_liteethmacsramreader_next_state <= 2'd0; - main_read <= 1'd0; - main_sram107_trigger <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value <= 11'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; - main_sram130_source_ready <= 1'd0; - main_sram83_source_valid <= 1'd0; - main_sram86_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) + wishbone_interface_reader_cmd_fifo_wrport_adr <= wishbone_interface_reader_cmd_fifo_produce; + end +end +assign wishbone_interface_reader_cmd_fifo_wrport_dat_w = wishbone_interface_reader_cmd_fifo_syncfifo_din; +assign wishbone_interface_reader_cmd_fifo_wrport_we = (wishbone_interface_reader_cmd_fifo_syncfifo_we & (wishbone_interface_reader_cmd_fifo_syncfifo_writable | wishbone_interface_reader_cmd_fifo_replace)); +assign wishbone_interface_reader_cmd_fifo_do_read = (wishbone_interface_reader_cmd_fifo_syncfifo_readable & wishbone_interface_reader_cmd_fifo_syncfifo_re); +assign wishbone_interface_reader_cmd_fifo_rdport_adr = wishbone_interface_reader_cmd_fifo_consume; +assign wishbone_interface_reader_cmd_fifo_syncfifo_dout = wishbone_interface_reader_cmd_fifo_rdport_dat_r; +assign wishbone_interface_reader_cmd_fifo_syncfifo_writable = (wishbone_interface_reader_cmd_fifo_level != 2'd2); +assign wishbone_interface_reader_cmd_fifo_syncfifo_readable = (wishbone_interface_reader_cmd_fifo_level != 1'd0); +always @(*) begin + liteethmacsramreader_next_state <= 2'd0; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd0; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 11'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd0; + wishbone_interface_reader_read <= 1'd0; + wishbone_interface_reader_source_source_last <= 1'd0; + wishbone_interface_reader_source_source_valid <= 1'd0; + liteethmacsramreader_next_state <= liteethmacsramreader_state; + case (liteethmacsramreader_state) 1'd1: begin - main_sram83_source_valid <= 1'd1; - main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); - if (main_sram84_source_ready) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - if (main_sram86_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; + wishbone_interface_reader_source_source_valid <= 1'd1; + wishbone_interface_reader_source_source_last <= (wishbone_interface_reader_length >= wishbone_interface_reader_cmd_fifo_source_payload_length); + if (wishbone_interface_reader_source_source_ready) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= (wishbone_interface_reader_length + 3'd4); + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (wishbone_interface_reader_source_source_last) begin + liteethmacsramreader_next_state <= 2'd2; end end end 2'd2: begin - main_sram122_length_liteethmacsramreader_next_value <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - main_sram107_trigger <= 1'd1; - main_sram130_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd1; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd1; + liteethmacsramreader_next_state <= 1'd0; end default: begin - if (main_sram129_source_valid) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= 3'd4; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; + if (wishbone_interface_reader_cmd_fifo_source_valid) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 3'd4; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + liteethmacsramreader_next_state <= 1'd1; end end endcase end -assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); -assign main_sram0_adr = main_interface0_adr[8:0]; -assign main_interface0_dat_r = main_sram0_dat_r; -assign main_sram1_adr = main_interface1_adr[8:0]; -assign main_interface1_dat_r = main_sram1_dat_r; -always @(*) begin - main_sram2_we <= 4'd0; - main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); - main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); - main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); - main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); -end -assign main_sram2_adr = main_interface2_adr[8:0]; -assign main_interface2_dat_r = main_sram2_dat_r; -assign main_sram2_dat_w = main_interface2_dat_w; -always @(*) begin - main_sram3_we <= 4'd0; - main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); - main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); - main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); - main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); -end -assign main_sram3_adr = main_interface3_adr[8:0]; -assign main_interface3_dat_r = main_sram3_dat_r; -assign main_sram3_dat_w = main_interface3_dat_w; -always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); -end -assign main_interface0_adr = main_bus_adr; -assign main_interface0_dat_w = main_bus_dat_w; -assign main_interface0_sel = main_bus_sel; -assign main_interface0_stb = main_bus_stb; -assign main_interface0_we = main_bus_we; -assign main_interface0_cti = main_bus_cti; -assign main_interface0_bte = main_bus_bte; -assign main_interface1_adr = main_bus_adr; -assign main_interface1_dat_w = main_bus_dat_w; -assign main_interface1_sel = main_bus_sel; -assign main_interface1_stb = main_bus_stb; -assign main_interface1_we = main_bus_we; -assign main_interface1_cti = main_bus_cti; -assign main_interface1_bte = main_bus_bte; -assign main_interface2_adr = main_bus_adr; -assign main_interface2_dat_w = main_bus_dat_w; -assign main_interface2_sel = main_bus_sel; -assign main_interface2_stb = main_bus_stb; -assign main_interface2_we = main_bus_we; -assign main_interface2_cti = main_bus_cti; -assign main_interface2_bte = main_bus_bte; -assign main_interface3_adr = main_bus_adr; -assign main_interface3_dat_w = main_bus_dat_w; -assign main_interface3_sel = main_bus_sel; -assign main_interface3_stb = main_bus_stb; -assign main_interface3_we = main_bus_we; -assign main_interface3_cti = main_bus_cti; -assign main_interface3_bte = main_bus_bte; -assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); -assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); -assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); -assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); -assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); -always @(*) begin - builder_interface0_ack <= 1'd0; - builder_interface0_dat_r <= 32'd0; - builder_interface1_adr <= 14'd0; - builder_interface1_dat_w <= 32'd0; - builder_interface1_we <= 1'd0; - builder_next_state <= 1'd0; - builder_next_state <= builder_state; - case (builder_state) +assign wishbone_interface_ev_irq = (wishbone_interface_writer_irq | wishbone_interface_reader_irq); +assign wishbone_interface_sram0_adr = wishbone_interface_interface0_adr[8:0]; +assign wishbone_interface_interface0_dat_r = wishbone_interface_sram0_dat_r; +assign wishbone_interface_sram1_adr = wishbone_interface_interface1_adr[8:0]; +assign wishbone_interface_interface1_dat_r = wishbone_interface_sram1_dat_r; +always @(*) begin + wishbone_interface_decoder0_slave_sel <= 2'd0; + wishbone_interface_decoder0_slave_sel[0] <= (wishbone_interface_bus_rx_adr[9] == 1'd0); + wishbone_interface_decoder0_slave_sel[1] <= (wishbone_interface_bus_rx_adr[9] == 1'd1); +end +assign wishbone_interface_interface0_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface0_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface0_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface0_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface0_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface0_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface0_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface1_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface1_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface1_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface1_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface1_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface1_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface1_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface0_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[0]); +assign wishbone_interface_interface1_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[1]); +assign wishbone_interface_bus_rx_ack = (wishbone_interface_interface0_ack | wishbone_interface_interface1_ack); +assign wishbone_interface_bus_rx_err = (wishbone_interface_interface0_err | wishbone_interface_interface1_err); +assign wishbone_interface_bus_rx_dat_r = (({32{wishbone_interface_decoder0_slave_sel_r[0]}} & wishbone_interface_interface0_dat_r) | ({32{wishbone_interface_decoder0_slave_sel_r[1]}} & wishbone_interface_interface1_dat_r)); +always @(*) begin + wishbone_interface_sram2_we <= 4'd0; + wishbone_interface_sram2_we[0] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[0]); + wishbone_interface_sram2_we[1] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[1]); + wishbone_interface_sram2_we[2] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[2]); + wishbone_interface_sram2_we[3] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[3]); +end +assign wishbone_interface_sram2_adr = wishbone_interface_interface2_adr[8:0]; +assign wishbone_interface_interface2_dat_r = wishbone_interface_sram2_dat_r; +assign wishbone_interface_sram2_dat_w = wishbone_interface_interface2_dat_w; +always @(*) begin + wishbone_interface_sram3_we <= 4'd0; + wishbone_interface_sram3_we[0] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[0]); + wishbone_interface_sram3_we[1] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[1]); + wishbone_interface_sram3_we[2] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[2]); + wishbone_interface_sram3_we[3] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[3]); +end +assign wishbone_interface_sram3_adr = wishbone_interface_interface3_adr[8:0]; +assign wishbone_interface_interface3_dat_r = wishbone_interface_sram3_dat_r; +assign wishbone_interface_sram3_dat_w = wishbone_interface_interface3_dat_w; +always @(*) begin + wishbone_interface_decoder1_slave_sel <= 2'd0; + wishbone_interface_decoder1_slave_sel[0] <= (wishbone_interface_bus_tx_adr[9] == 1'd0); + wishbone_interface_decoder1_slave_sel[1] <= (wishbone_interface_bus_tx_adr[9] == 1'd1); +end +assign wishbone_interface_interface2_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface2_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface2_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface2_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface2_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface2_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface2_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface3_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface3_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface3_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface3_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface3_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface3_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface3_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface2_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[0]); +assign wishbone_interface_interface3_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[1]); +assign wishbone_interface_bus_tx_ack = (wishbone_interface_interface2_ack | wishbone_interface_interface3_ack); +assign wishbone_interface_bus_tx_err = (wishbone_interface_interface2_err | wishbone_interface_interface3_err); +assign wishbone_interface_bus_tx_dat_r = (({32{wishbone_interface_decoder1_slave_sel_r[0]}} & wishbone_interface_interface2_dat_r) | ({32{wishbone_interface_decoder1_slave_sel_r[1]}} & wishbone_interface_interface3_dat_r)); +always @(*) begin + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; + interface1_we <= 1'd0; + next_state <= 1'd0; + next_state <= state; + case (state) 1'd1: begin - builder_interface0_ack <= 1'd1; - builder_interface0_dat_r <= builder_interface1_dat_r; - builder_next_state <= 1'd0; + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + next_state <= 1'd0; end default: begin - builder_interface1_dat_w <= builder_interface0_dat_w; - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr <= builder_interface0_adr[29:0]; - builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); - builder_next_state <= 1'd1; + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + next_state <= 1'd1; end end endcase end -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); -assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; -always @(*) begin - builder_csrbank0_reset0_re <= 1'd0; - builder_csrbank0_reset0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); - end -end -assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank0_scratch0_re <= 1'd0; - builder_csrbank0_scratch0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); - end -end -assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= interface0_bank_bus_re; end end +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin - main_maccore_soc_rst <= 1'd0; - if (main_maccore_reset_re) begin - main_maccore_soc_rst <= main_maccore_reset_storage[0]; + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign main_maccore_cpu_rst = main_maccore_reset_storage[1]; -assign builder_csrbank0_reset0_w = main_maccore_reset_storage[1:0]; -assign builder_csrbank0_scratch0_w = main_maccore_scratch_storage[31:0]; -assign builder_csrbank0_bus_errors_w = main_maccore_bus_errors_status[31:0]; -assign main_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); -assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank1_sram_writer_slot_re <= 1'd0; - builder_csrbank1_sram_writer_slot_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + maccore_soc_rst <= 1'd0; + if (maccore_reset_re) begin + maccore_soc_rst <= maccore_reset_storage[0]; end end -assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign maccore_cpu_rst = maccore_reset_storage[1]; +assign csrbank0_reset0_w = maccore_reset_storage; +assign csrbank0_scratch0_w = maccore_scratch_storage; +assign csrbank0_bus_errors_w = maccore_bus_errors_status; +assign maccore_bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 2'd2); +assign csrbank1_sram_writer_slot_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_errors_re <= 1'd0; - builder_csrbank1_sram_writer_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_slot_re <= 1'd0; + csrbank1_sram_writer_slot_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_sram_writer_slot_re <= interface1_bank_bus_we; + csrbank1_sram_writer_slot_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_length_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_length_re <= 1'd0; + csrbank1_sram_writer_length_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_sram_writer_length_re <= interface1_bank_bus_we; + csrbank1_sram_writer_length_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_errors_re <= 1'd0; + csrbank1_sram_writer_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_sram_writer_errors_re <= interface1_bank_bus_we; + csrbank1_sram_writer_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_status_re <= 1'd0; + csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_sram_writer_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_status_we <= interface1_bank_bus_re; end end -assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - main_start_re <= 1'd0; - main_start_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_start_re <= builder_interface1_bank_bus_we; - main_start_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_pending_re <= 1'd0; + csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_sram_writer_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_re <= 1'd0; - builder_csrbank1_sram_reader_ready_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_enable0_re <= 1'd0; + csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_sram_writer_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_enable0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +assign wishbone_interface_reader_start_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_level_re <= 1'd0; - builder_csrbank1_sram_reader_level_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + wishbone_interface_reader_start_re <= 1'd0; + wishbone_interface_reader_start_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + wishbone_interface_reader_start_re <= interface1_bank_bus_we; + wishbone_interface_reader_start_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ready_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ready_re <= 1'd0; + csrbank1_sram_reader_ready_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_sram_reader_ready_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ready_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_reader_level_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_re <= 1'd0; - builder_csrbank1_sram_reader_length0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_level_re <= 1'd0; + csrbank1_sram_reader_level_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + csrbank1_sram_reader_level_re <= interface1_bank_bus_we; + csrbank1_sram_reader_level_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_slot0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_slot0_re <= 1'd0; + csrbank1_sram_reader_slot0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_sram_reader_slot0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_slot0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_length0_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_length0_re <= 1'd0; + csrbank1_sram_reader_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_sram_reader_length0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_length0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_status_re <= 1'd0; + csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_sram_reader_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_re <= 1'd0; - builder_csrbank1_preamble_crc_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_pending_re <= 1'd0; + csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_sram_reader_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_sram_reader_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_enable0_re <= 1'd0; + csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_sram_reader_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_enable0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_preamble_crc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_preamble_crc_re <= 1'd0; + csrbank1_preamble_crc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + csrbank1_preamble_crc_re <= interface1_bank_bus_we; + csrbank1_preamble_crc_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; -assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; -assign main_sram11_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; -assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; -always @(*) begin - main_sram22_status <= 1'd0; - main_sram22_status <= main_sram21_available; -end -assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; -assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; -always @(*) begin - main_sram26_status <= 1'd0; - main_sram26_status <= main_sram25_available; -end -assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; -assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_sram30_available = main_sram31_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; -assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; -assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; -assign main_sram98_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; -assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; -always @(*) begin - main_sram110_status <= 1'd0; - main_sram110_status <= main_sram109_event0; -end -assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; -assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; -always @(*) begin - main_sram114_status <= 1'd0; - main_sram114_status <= main_sram113_event0; -end -assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; -assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_sram118_event0 = main_sram119_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; -assign builder_csrbank1_preamble_crc_w = main_status; -assign main_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; -assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); -assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; -always @(*) begin - builder_csrbank2_crg_reset0_re <= 1'd0; - builder_csrbank2_crg_reset0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); - end -end -assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; -always @(*) begin - builder_csrbank2_mdio_w0_re <= 1'd0; - builder_csrbank2_mdio_w0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); - end -end -assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; -always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); - end -end -assign builder_csrbank2_crg_reset0_w = main_maccore_crg_reset_storage; -assign main_maccore_mdc = main_maccore__w_storage[0]; -assign main_maccore_oe = main_maccore__w_storage[1]; -assign main_maccore_w = main_maccore__w_storage[2]; -assign builder_csrbank2_mdio_w0_w = main_maccore__w_storage[2:0]; -assign builder_csrbank2_mdio_r_w = main_maccore__r_status; -assign main_maccore__r_we = builder_csrbank2_mdio_r_we; -assign builder_adr = builder_interface1_adr; -assign builder_we = builder_interface1_we; -assign builder_dat_w = builder_interface1_dat_w; -assign builder_interface1_dat_r = builder_dat_r; -assign builder_interface0_bank_bus_adr = builder_adr; -assign builder_interface1_bank_bus_adr = builder_adr; -assign builder_interface2_bank_bus_adr = builder_adr; -assign builder_interface0_bank_bus_we = builder_we; -assign builder_interface1_bank_bus_we = builder_we; -assign builder_interface2_bank_bus_we = builder_we; -assign builder_interface0_bank_bus_dat_w = builder_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_dat_w; -assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); -assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; -assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); -always @(*) begin - builder_self0 <= 30'd0; - case (builder_grant) +assign csrbank1_rx_datapath_preamble_errors_r = interface1_bank_bus_dat_w; +always @(*) begin + csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_rx_datapath_preamble_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_preamble_errors_we <= interface1_bank_bus_re; + end +end +assign csrbank1_rx_datapath_crc_errors_r = interface1_bank_bus_dat_w; +always @(*) begin + csrbank1_rx_datapath_crc_errors_re <= 1'd0; + csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_rx_datapath_crc_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_crc_errors_we <= interface1_bank_bus_re; + end +end +assign csrbank1_sram_writer_slot_w = wishbone_interface_writer_slot_status; +assign wishbone_interface_writer_slot_we = csrbank1_sram_writer_slot_we; +assign csrbank1_sram_writer_length_w = wishbone_interface_writer_length_status; +assign wishbone_interface_writer_length_we = csrbank1_sram_writer_length_we; +assign csrbank1_sram_writer_errors_w = wishbone_interface_writer_errors_status; +assign wishbone_interface_writer_errors_we = csrbank1_sram_writer_errors_we; +assign wishbone_interface_writer_status_status = wishbone_interface_writer_available0; +assign csrbank1_sram_writer_ev_status_w = wishbone_interface_writer_status_status; +assign wishbone_interface_writer_status_we = csrbank1_sram_writer_ev_status_we; +assign wishbone_interface_writer_pending_status = wishbone_interface_writer_available1; +assign csrbank1_sram_writer_ev_pending_w = wishbone_interface_writer_pending_status; +assign wishbone_interface_writer_pending_we = csrbank1_sram_writer_ev_pending_we; +assign wishbone_interface_writer_available2 = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_writer_ev_enable0_w = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_reader_ready_w = wishbone_interface_reader_ready_status; +assign wishbone_interface_reader_ready_we = csrbank1_sram_reader_ready_we; +assign csrbank1_sram_reader_level_w = wishbone_interface_reader_level_status; +assign wishbone_interface_reader_level_we = csrbank1_sram_reader_level_we; +assign csrbank1_sram_reader_slot0_w = wishbone_interface_reader_slot_storage; +assign csrbank1_sram_reader_length0_w = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_status_status = wishbone_interface_reader_event00; +assign csrbank1_sram_reader_ev_status_w = wishbone_interface_reader_status_status; +assign wishbone_interface_reader_status_we = csrbank1_sram_reader_ev_status_we; +assign wishbone_interface_reader_pending_status = wishbone_interface_reader_event01; +assign csrbank1_sram_reader_ev_pending_w = wishbone_interface_reader_pending_status; +assign wishbone_interface_reader_pending_we = csrbank1_sram_reader_ev_pending_we; +assign wishbone_interface_reader_event02 = wishbone_interface_reader_enable_storage; +assign csrbank1_sram_reader_ev_enable0_w = wishbone_interface_reader_enable_storage; +assign csrbank1_preamble_crc_w = core_status; +assign core_we = csrbank1_preamble_crc_we; +assign csrbank1_rx_datapath_preamble_errors_w = core_preamble_errors_status; +assign core_preamble_errors_we = csrbank1_rx_datapath_preamble_errors_we; +assign csrbank1_rx_datapath_crc_errors_w = core_crc_errors_status; +assign core_crc_errors_we = csrbank1_rx_datapath_crc_errors_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); +assign csrbank2_crg_reset0_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + csrbank2_crg_reset0_re <= 1'd0; + csrbank2_crg_reset0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_crg_reset0_re <= interface2_bank_bus_we; + csrbank2_crg_reset0_we <= interface2_bank_bus_re; + end +end +assign csrbank2_mdio_w0_r = interface2_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank2_mdio_w0_re <= 1'd0; + csrbank2_mdio_w0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_mdio_w0_re <= interface2_bank_bus_we; + csrbank2_mdio_w0_we <= interface2_bank_bus_re; + end +end +assign csrbank2_mdio_r_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + csrbank2_mdio_r_re <= 1'd0; + csrbank2_mdio_r_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_mdio_r_re <= interface2_bank_bus_we; + csrbank2_mdio_r_we <= interface2_bank_bus_re; + end +end +assign csrbank2_crg_reset0_w = maccore_crg_reset_storage; +assign maccore_mdc = maccore__w_storage[0]; +assign maccore_oe = maccore__w_storage[1]; +assign maccore_w = maccore__w_storage[2]; +assign csrbank2_mdio_w0_w = maccore__w_storage; +assign csrbank2_mdio_r_w = maccore__r_status; +assign maccore__r_we = csrbank2_mdio_r_we; +assign adr = interface1_adr; +assign re = interface1_re; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); +always @(*) begin + self0 <= 30'd0; + case (grant) default: begin - builder_self0 <= main_wb_bus_adr; + self0 <= wb_bus_adr; end endcase end always @(*) begin - builder_self1 <= 32'd0; - case (builder_grant) + self1 <= 32'd0; + case (grant) default: begin - builder_self1 <= main_wb_bus_dat_w; + self1 <= wb_bus_dat_w; end endcase end always @(*) begin - builder_self2 <= 4'd0; - case (builder_grant) + self2 <= 4'd0; + case (grant) default: begin - builder_self2 <= main_wb_bus_sel; + self2 <= wb_bus_sel; end endcase end always @(*) begin - builder_self3 <= 1'd0; - case (builder_grant) + self3 <= 1'd0; + case (grant) default: begin - builder_self3 <= main_wb_bus_cyc; + self3 <= wb_bus_cyc; end endcase end always @(*) begin - builder_self4 <= 1'd0; - case (builder_grant) + self4 <= 1'd0; + case (grant) default: begin - builder_self4 <= main_wb_bus_stb; + self4 <= wb_bus_stb; end endcase end always @(*) begin - builder_self5 <= 1'd0; - case (builder_grant) + self5 <= 1'd0; + case (grant) default: begin - builder_self5 <= main_wb_bus_we; + self5 <= wb_bus_we; end endcase end always @(*) begin - builder_self6 <= 3'd0; - case (builder_grant) + self6 <= 3'd0; + case (grant) default: begin - builder_self6 <= main_wb_bus_cti; + self6 <= wb_bus_cti; end endcase end always @(*) begin - builder_self7 <= 2'd0; - case (builder_grant) + self7 <= 2'd0; + case (grant) default: begin - builder_self7 <= main_wb_bus_bte; + self7 <= wb_bus_bte; end endcase end always @(*) begin - main_maccore__r_status <= 1'd0; - main_maccore__r_status <= main_maccore_r; - main_maccore__r_status <= builder_xilinxmultiregimpl01; + maccore__r_status <= 1'd0; + maccore__r_status <= maccore_r; + maccore__r_status <= xilinxmultiregimpl01; end -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl11; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl21; -assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl31; -assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl41; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl51; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; +assign core_tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl11; +assign core_tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl21; +assign core_pulsesynchronizer0_toggle_o = xilinxmultiregimpl31; +assign core_pulsesynchronizer1_toggle_o = xilinxmultiregimpl41; +assign core_rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl51; +assign core_rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl61; //------------------------------------------------------------------------------ @@ -3227,578 +3153,578 @@ assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; //------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_liteethphymiirx_reset <= (~mii_rx_dv); - main_maccore_liteethphymiirx_converter_sink_valid <= 1'd1; - main_maccore_liteethphymiirx_converter_sink_payload_data <= mii_rx_data; - if (main_maccore_liteethphymiirx_converter_source_ready) begin - main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; - end - if (main_maccore_liteethphymiirx_converter_load_part) begin - if (((main_maccore_liteethphymiirx_converter_demux == 1'd1) | main_maccore_liteethphymiirx_converter_sink_last)) begin - main_maccore_liteethphymiirx_converter_demux <= 1'd0; - main_maccore_liteethphymiirx_converter_strobe_all <= 1'd1; + maccore_liteethphymiirx_reset <= (~mii_rx_dv); + maccore_liteethphymiirx_converter_sink_valid <= 1'd1; + maccore_liteethphymiirx_converter_sink_payload_data <= mii_rx_data; + if (maccore_liteethphymiirx_converter_source_ready) begin + maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + end + if (maccore_liteethphymiirx_converter_load_part) begin + if (((maccore_liteethphymiirx_converter_demux == 1'd1) | maccore_liteethphymiirx_converter_sink_last)) begin + maccore_liteethphymiirx_converter_demux <= 1'd0; + maccore_liteethphymiirx_converter_strobe_all <= 1'd1; end else begin - main_maccore_liteethphymiirx_converter_demux <= (main_maccore_liteethphymiirx_converter_demux + 1'd1); + maccore_liteethphymiirx_converter_demux <= (maccore_liteethphymiirx_converter_demux + 1'd1); end end - if ((main_maccore_liteethphymiirx_converter_source_valid & main_maccore_liteethphymiirx_converter_source_ready)) begin - if ((main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready)) begin - main_maccore_liteethphymiirx_converter_source_first <= main_maccore_liteethphymiirx_converter_sink_first; - main_maccore_liteethphymiirx_converter_source_last <= main_maccore_liteethphymiirx_converter_sink_last; + if ((maccore_liteethphymiirx_converter_source_valid & maccore_liteethphymiirx_converter_source_ready)) begin + if ((maccore_liteethphymiirx_converter_sink_valid & maccore_liteethphymiirx_converter_sink_ready)) begin + maccore_liteethphymiirx_converter_source_first <= maccore_liteethphymiirx_converter_sink_first; + maccore_liteethphymiirx_converter_source_last <= maccore_liteethphymiirx_converter_sink_last; end else begin - main_maccore_liteethphymiirx_converter_source_first <= 1'd0; - main_maccore_liteethphymiirx_converter_source_last <= 1'd0; + maccore_liteethphymiirx_converter_source_first <= 1'd0; + maccore_liteethphymiirx_converter_source_last <= 1'd0; end end else begin - if ((main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready)) begin - main_maccore_liteethphymiirx_converter_source_first <= (main_maccore_liteethphymiirx_converter_sink_first | main_maccore_liteethphymiirx_converter_source_first); - main_maccore_liteethphymiirx_converter_source_last <= (main_maccore_liteethphymiirx_converter_sink_last | main_maccore_liteethphymiirx_converter_source_last); + if ((maccore_liteethphymiirx_converter_sink_valid & maccore_liteethphymiirx_converter_sink_ready)) begin + maccore_liteethphymiirx_converter_source_first <= (maccore_liteethphymiirx_converter_sink_first | maccore_liteethphymiirx_converter_source_first); + maccore_liteethphymiirx_converter_source_last <= (maccore_liteethphymiirx_converter_sink_last | maccore_liteethphymiirx_converter_source_last); end end - if (main_maccore_liteethphymiirx_converter_load_part) begin - case (main_maccore_liteethphymiirx_converter_demux) + if (maccore_liteethphymiirx_converter_load_part) begin + case (maccore_liteethphymiirx_converter_demux) 1'd0: begin - main_maccore_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_liteethphymiirx_converter_sink_payload_data; + maccore_liteethphymiirx_converter_source_payload_data[3:0] <= maccore_liteethphymiirx_converter_sink_payload_data; end 1'd1: begin - main_maccore_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_liteethphymiirx_converter_sink_payload_data; + maccore_liteethphymiirx_converter_source_payload_data[7:4] <= maccore_liteethphymiirx_converter_sink_payload_data; end endcase end - if (main_maccore_liteethphymiirx_converter_load_part) begin - main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= (main_maccore_liteethphymiirx_converter_demux + 1'd1); + if (maccore_liteethphymiirx_converter_load_part) begin + maccore_liteethphymiirx_converter_source_payload_valid_token_count <= (maccore_liteethphymiirx_converter_demux + 1'd1); end - if (main_maccore_liteethphymiirx_reset) begin - main_maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; - main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_liteethphymiirx_converter_demux <= 1'd0; - main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + if (maccore_liteethphymiirx_reset) begin + maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; + maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; + maccore_liteethphymiirx_converter_demux <= 1'd0; + maccore_liteethphymiirx_converter_strobe_all <= 1'd0; end - builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; - if (main_pulsesynchronizer0_i) begin - main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + rxdatapath_liteethmacpreamblechecker_state <= rxdatapath_liteethmacpreamblechecker_next_state; + if (core_pulsesynchronizer0_i) begin + core_pulsesynchronizer0_toggle_i <= (~core_pulsesynchronizer0_toggle_i); end - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + if (core_liteethmaccrc32checker_crc_ce) begin + core_liteethmaccrc32checker_crc_reg <= core_liteethmaccrc32checker_crc_crc_next; end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + if (core_liteethmaccrc32checker_crc_reset) begin + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((core_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_produce <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + core_liteethmaccrc32checker_syncfifo_produce <= (core_liteethmaccrc32checker_syncfifo_produce + 1'd1); end end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + if ((core_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_consume <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + core_liteethmaccrc32checker_syncfifo_consume <= (core_liteethmaccrc32checker_syncfifo_consume + 1'd1); end end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~core_liteethmaccrc32checker_syncfifo_do_read)) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level + 1'd1); end end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level - 1'd1); end end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + if (core_liteethmaccrc32checker_fifo_reset) begin + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; end - builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; - if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin - main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + rxdatapath_bufferizeendpoints_state <= rxdatapath_bufferizeendpoints_next_state; + if (core_liteethmaccrc32checker_last_be_next_value_ce0) begin + core_liteethmaccrc32checker_last_be <= core_liteethmaccrc32checker_last_be_next_value0; end - if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin - main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + if (core_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + core_liteethmaccrc32checker_crc_error1 <= core_liteethmaccrc32checker_crc_error1_next_value1; end - if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin - main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; - main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; - main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; - main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; - main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + if (((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready)) begin + core_bufferizeendpoints_pipe_valid_source_valid <= core_bufferizeendpoints_pipe_valid_sink_valid; + core_bufferizeendpoints_pipe_valid_source_first <= core_bufferizeendpoints_pipe_valid_sink_first; + core_bufferizeendpoints_pipe_valid_source_last <= core_bufferizeendpoints_pipe_valid_sink_last; + core_bufferizeendpoints_pipe_valid_source_payload_data <= core_bufferizeendpoints_pipe_valid_sink_payload_data; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= core_bufferizeendpoints_pipe_valid_sink_payload_last_be; + core_bufferizeendpoints_pipe_valid_source_payload_error <= core_bufferizeendpoints_pipe_valid_sink_payload_error; end - if (main_pulsesynchronizer1_i) begin - main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + if (core_pulsesynchronizer1_i) begin + core_pulsesynchronizer1_toggle_i <= (~core_pulsesynchronizer1_toggle_i); end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; + if (core_rx_converter_converter_source_ready) begin + core_rx_converter_converter_strobe_all <= 1'd0; end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; + if (core_rx_converter_converter_load_part) begin + if (((core_rx_converter_converter_demux == 2'd3) | core_rx_converter_converter_sink_last)) begin + core_rx_converter_converter_demux <= 1'd0; + core_rx_converter_converter_strobe_all <= 1'd1; end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + core_rx_converter_converter_demux <= (core_rx_converter_converter_demux + 1'd1); end end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + if ((core_rx_converter_converter_source_valid & core_rx_converter_converter_source_ready)) begin + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= core_rx_converter_converter_sink_first; + core_rx_converter_converter_source_last <= core_rx_converter_converter_sink_last; end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; + core_rx_converter_converter_source_first <= 1'd0; + core_rx_converter_converter_source_last <= 1'd0; end end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= (core_rx_converter_converter_sink_first | core_rx_converter_converter_source_first); + core_rx_converter_converter_source_last <= (core_rx_converter_converter_sink_last | core_rx_converter_converter_source_last); end end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) + if (core_rx_converter_converter_load_part) begin + case (core_rx_converter_converter_demux) 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[9:0] <= core_rx_converter_converter_sink_payload_data; end 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[19:10] <= core_rx_converter_converter_sink_payload_data; end 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[29:20] <= core_rx_converter_converter_sink_payload_data; end 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[39:30] <= core_rx_converter_converter_sink_payload_data; end endcase end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + if (core_rx_converter_converter_load_part) begin + core_rx_converter_converter_source_payload_valid_token_count <= (core_rx_converter_converter_demux + 1'd1); end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + core_rx_cdc_cdc_graycounter0_q_binary <= core_rx_cdc_cdc_graycounter0_q_next_binary; + core_rx_cdc_cdc_graycounter0_q <= core_rx_cdc_cdc_graycounter0_q_next; if (eth_rx_rst) begin - main_maccore_liteethphymiirx_converter_sink_valid <= 1'd0; - main_maccore_liteethphymiirx_converter_sink_payload_data <= 4'd0; - main_maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; - main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_liteethphymiirx_converter_demux <= 1'd0; - main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; - main_maccore_liteethphymiirx_reset <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_liteethmaccrc32checker_last_be <= 1'd0; - main_liteethmaccrc32checker_crc_error1 <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; - builder_rxdatapath_bufferizeendpoints_state <= 2'd0; - end - builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; + maccore_liteethphymiirx_converter_sink_valid <= 1'd0; + maccore_liteethphymiirx_converter_sink_payload_data <= 4'd0; + maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; + maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; + maccore_liteethphymiirx_converter_demux <= 1'd0; + maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + maccore_liteethphymiirx_reset <= 1'd0; + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + core_liteethmaccrc32checker_last_be <= 1'd0; + core_liteethmaccrc32checker_crc_error1 <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + core_rx_converter_converter_source_payload_data <= 40'd0; + core_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + core_rx_converter_converter_demux <= 2'd0; + core_rx_converter_converter_strobe_all <= 1'd0; + core_rx_cdc_cdc_graycounter0_q <= 6'd0; + core_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + rxdatapath_bufferizeendpoints_state <= 2'd0; + end + xilinxmultiregimpl60 <= core_rx_cdc_cdc_graycounter1_q; + xilinxmultiregimpl61 <= xilinxmultiregimpl60; end always @(posedge eth_tx_clk) begin - mii_tx_en <= main_maccore_liteethphymiitx_source_source_valid; - mii_tx_data <= main_maccore_liteethphymiitx_source_source_payload_data; - if ((main_maccore_liteethphymiitx_converter_source_valid & main_maccore_liteethphymiitx_converter_source_ready)) begin - if (main_maccore_liteethphymiitx_converter_last) begin - main_maccore_liteethphymiitx_converter_mux <= 1'd0; + mii_tx_en <= maccore_liteethphymiitx_source_source_valid; + mii_tx_data <= maccore_liteethphymiitx_source_source_payload_data; + if ((maccore_liteethphymiitx_converter_source_valid & maccore_liteethphymiitx_converter_source_ready)) begin + if (maccore_liteethphymiitx_converter_last) begin + maccore_liteethphymiitx_converter_mux <= 1'd0; end else begin - main_maccore_liteethphymiitx_converter_mux <= (main_maccore_liteethphymiitx_converter_mux + 1'd1); + maccore_liteethphymiitx_converter_mux <= (maccore_liteethphymiitx_converter_mux + 1'd1); end end - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= core_tx_cdc_cdc_graycounter1_q_next_binary; + core_tx_cdc_cdc_graycounter1_q <= core_tx_cdc_cdc_graycounter1_q_next; + if ((core_tx_converter_converter_source_valid & core_tx_converter_converter_source_ready)) begin + if (core_tx_converter_converter_last) begin + core_tx_converter_converter_mux <= 1'd0; end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + core_tx_converter_converter_mux <= (core_tx_converter_converter_mux + 1'd1); end end - builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; - builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; - if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin - main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + txdatapath_liteethmactxlastbe_state <= txdatapath_liteethmactxlastbe_next_state; + txdatapath_liteethmacpaddinginserter_state <= txdatapath_liteethmacpaddinginserter_next_state; + if (core_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + core_tx_padding_counter <= core_tx_padding_counter_clockdomainsrenamer0_next_value; end - if (main_tx_crc_is_ongoing0) begin - main_tx_crc_cnt <= 2'd3; + if (core_tx_crc_is_ongoing0) begin + core_tx_crc_cnt <= 2'd3; end else begin - if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin - main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + if ((core_tx_crc_is_ongoing1 & (~core_tx_crc_cnt_done))) begin + core_tx_crc_cnt <= (core_tx_crc_cnt - core_tx_crc_source_ready); end end - if (main_tx_crc_ce) begin - main_tx_crc_reg <= main_tx_crc_crc_next; + if (core_tx_crc_ce) begin + core_tx_crc_reg <= core_tx_crc_crc_next; end - if (main_tx_crc_reset) begin - main_tx_crc_reg <= 32'd4294967295; + if (core_tx_crc_reset) begin + core_tx_crc_reg <= 32'd4294967295; end - builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; - if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin - main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + txdatapath_bufferizeendpoints_state <= txdatapath_bufferizeendpoints_next_state; + if (core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + core_tx_crc_crc_packet <= core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; end - if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin - main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + if (core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + core_tx_crc_last_be <= core_tx_crc_last_be_clockdomainsrenamer1_next_value1; end - if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin - main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; - main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; - main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; - main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; - main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; - main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + if (((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready)) begin + core_tx_crc_pipe_valid_source_valid <= core_tx_crc_pipe_valid_sink_valid; + core_tx_crc_pipe_valid_source_first <= core_tx_crc_pipe_valid_sink_first; + core_tx_crc_pipe_valid_source_last <= core_tx_crc_pipe_valid_sink_last; + core_tx_crc_pipe_valid_source_payload_data <= core_tx_crc_pipe_valid_sink_payload_data; + core_tx_crc_pipe_valid_source_payload_last_be <= core_tx_crc_pipe_valid_sink_payload_last_be; + core_tx_crc_pipe_valid_source_payload_error <= core_tx_crc_pipe_valid_sink_payload_error; end - builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; - if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin - main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + txdatapath_liteethmacpreambleinserter_state <= txdatapath_liteethmacpreambleinserter_next_state; + if (core_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + core_tx_preamble_count <= core_tx_preamble_count_clockdomainsrenamer2_next_value; end - builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; - if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin - main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + txdatapath_liteethmacgap_state <= txdatapath_liteethmacgap_next_state; + if (core_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + core_tx_gap_counter <= core_tx_gap_counter_clockdomainsrenamer3_next_value; end if (eth_tx_rst) begin - main_maccore_liteethphymiitx_converter_mux <= 1'd0; - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_padding_counter <= 16'd0; - main_tx_crc_crc_packet <= 32'd0; - main_tx_crc_last_be <= 1'd0; - main_tx_crc_reg <= 32'd4294967295; - main_tx_crc_cnt <= 2'd3; - main_tx_crc_pipe_valid_source_valid <= 1'd0; - main_tx_crc_pipe_valid_source_payload_data <= 8'd0; - main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; - main_tx_crc_pipe_valid_source_payload_error <= 1'd0; - builder_txdatapath_liteethmactxlastbe_state <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; - builder_txdatapath_bufferizeendpoints_state <= 2'd0; - builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; - builder_txdatapath_liteethmacgap_state <= 1'd0; - end - builder_xilinxmultiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; + maccore_liteethphymiitx_converter_mux <= 1'd0; + core_tx_cdc_cdc_graycounter1_q <= 6'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + core_tx_converter_converter_mux <= 2'd0; + core_tx_padding_counter <= 16'd0; + core_tx_crc_reg <= 32'd4294967295; + core_tx_crc_cnt <= 2'd3; + core_tx_crc_pipe_valid_source_valid <= 1'd0; + core_tx_crc_pipe_valid_source_payload_data <= 8'd0; + core_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + core_tx_crc_pipe_valid_source_payload_error <= 1'd0; + txdatapath_liteethmactxlastbe_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_state <= 1'd0; + txdatapath_bufferizeendpoints_state <= 2'd0; + txdatapath_liteethmacpreambleinserter_state <= 2'd0; + txdatapath_liteethmacgap_state <= 1'd0; + end + xilinxmultiregimpl10 <= core_tx_cdc_cdc_graycounter0_q; + xilinxmultiregimpl11 <= xilinxmultiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); end end else begin - builder_count <= 20'd1000000; + count <= 20'd1000000; end - if ((main_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_bus_error) begin - main_maccore_bus_errors <= (main_maccore_bus_errors + 1'd1); + if ((maccore_bus_errors != 32'd4294967295)) begin + if (maccore_bus_error) begin + maccore_bus_errors <= (maccore_bus_errors + 1'd1); end end - if (main_maccore_crg_counter_ce) begin - main_maccore_crg_counter <= (main_maccore_crg_counter + 1'd1); + if (maccore_crg_counter_ce) begin + maccore_crg_counter <= (maccore_crg_counter + 1'd1); end - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - if (main_pulsesynchronizer0_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + core_tx_cdc_cdc_graycounter0_q_binary <= core_tx_cdc_cdc_graycounter0_q_next_binary; + core_tx_cdc_cdc_graycounter0_q <= core_tx_cdc_cdc_graycounter0_q_next; + if (core_pulsesynchronizer0_o) begin + core_preamble_errors_status <= (core_preamble_errors_status + 1'd1); end - if (main_pulsesynchronizer1_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); + if (core_pulsesynchronizer1_o) begin + core_crc_errors_status <= (core_crc_errors_status + 1'd1); end - main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; - main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - main_sram57_produce <= (main_sram57_produce + 1'd1); + core_pulsesynchronizer0_toggle_o_r <= core_pulsesynchronizer0_toggle_o; + core_pulsesynchronizer1_toggle_o_r <= core_pulsesynchronizer1_toggle_o; + core_rx_cdc_cdc_graycounter1_q_binary <= core_rx_cdc_cdc_graycounter1_q_next_binary; + core_rx_cdc_cdc_graycounter1_q <= core_rx_cdc_cdc_graycounter1_q_next; + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + wishbone_interface_writer_stat_fifo_produce <= (wishbone_interface_writer_stat_fifo_produce + 1'd1); end - if (main_sram63_do_read) begin - main_sram58_consume <= (main_sram58_consume + 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_consume <= (wishbone_interface_writer_stat_fifo_consume + 1'd1); end - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - if ((~main_sram63_do_read)) begin - main_sram55_level <= (main_sram55_level + 1'd1); + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + if ((~wishbone_interface_writer_stat_fifo_do_read)) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level + 1'd1); end end else begin - if (main_sram63_do_read) begin - main_sram55_level <= (main_sram55_level - 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level - 1'd1); end end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin - main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + liteethmacsramwriter_state <= liteethmacsramwriter_next_state; + if (wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce) begin + wishbone_interface_writer_length <= wishbone_interface_writer_length_liteethmacsramwriter_t_next_value; end - if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin - main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + if (wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce) begin + wishbone_interface_writer_errors_status <= wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value; end - if (main_slot_liteethmacsramwriter_next_value_ce) begin - main_slot <= main_slot_liteethmacsramwriter_next_value; + if (wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce) begin + wishbone_interface_writer_slot <= wishbone_interface_writer_slot_liteethmacsramwriter_next_value; end - if (main_sram108_clear) begin - main_sram106_pending <= 1'd0; + if (wishbone_interface_reader_eventsourcepulse_clear) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; end - if (main_sram107_trigger) begin - main_sram106_pending <= 1'd1; + if (wishbone_interface_reader_eventsourcepulse_trigger) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd1; end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - main_sram143_produce <= (main_sram143_produce + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + wishbone_interface_reader_cmd_fifo_produce <= (wishbone_interface_reader_cmd_fifo_produce + 1'd1); end - if (main_sram149_do_read) begin - main_sram144_consume <= (main_sram144_consume + 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_consume <= (wishbone_interface_reader_cmd_fifo_consume + 1'd1); end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - if ((~main_sram149_do_read)) begin - main_sram141_level <= (main_sram141_level + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + if ((~wishbone_interface_reader_cmd_fifo_do_read)) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level + 1'd1); end end else begin - if (main_sram149_do_read) begin - main_sram141_level <= (main_sram141_level - 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level - 1'd1); end end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_sram122_length_liteethmacsramreader_next_value_ce) begin - main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + liteethmacsramreader_state <= liteethmacsramreader_next_state; + if (wishbone_interface_reader_length_liteethmacsramreader_next_value_ce) begin + wishbone_interface_reader_length <= wishbone_interface_reader_length_liteethmacsramreader_next_value; end - main_interface0_ack <= 1'd0; - if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin - main_interface0_ack <= 1'd1; + wishbone_interface_interface0_ack <= 1'd0; + if (((wishbone_interface_interface0_cyc & wishbone_interface_interface0_stb) & ((~wishbone_interface_interface0_ack) | wishbone_interface_sram0_adr_burst))) begin + wishbone_interface_interface0_ack <= 1'd1; end - main_interface1_ack <= 1'd0; - if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin - main_interface1_ack <= 1'd1; + wishbone_interface_interface1_ack <= 1'd0; + if (((wishbone_interface_interface1_cyc & wishbone_interface_interface1_stb) & ((~wishbone_interface_interface1_ack) | wishbone_interface_sram1_adr_burst))) begin + wishbone_interface_interface1_ack <= 1'd1; end - main_interface2_ack <= 1'd0; - if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin - main_interface2_ack <= 1'd1; + wishbone_interface_decoder0_slave_sel_r <= wishbone_interface_decoder0_slave_sel; + wishbone_interface_interface2_ack <= 1'd0; + if (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & ((~wishbone_interface_interface2_ack) | wishbone_interface_sram2_adr_burst))) begin + wishbone_interface_interface2_ack <= 1'd1; end - main_interface3_ack <= 1'd0; - if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin - main_interface3_ack <= 1'd1; + wishbone_interface_interface3_ack <= 1'd0; + if (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & ((~wishbone_interface_interface3_ack) | wishbone_interface_sram3_adr_burst))) begin + wishbone_interface_interface3_ack <= 1'd1; end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) + wishbone_interface_decoder1_slave_sel_r <= wishbone_interface_decoder1_slave_sel; + state <= next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + interface0_bank_bus_dat_r <= csrbank0_reset0_w; end 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; end 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; end endcase end - if (builder_csrbank0_reset0_re) begin - main_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + if (csrbank0_reset0_re) begin + maccore_reset_storage <= csrbank0_reset0_r; end - main_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + maccore_reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + maccore_scratch_storage <= csrbank0_scratch0_r; end - main_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) + maccore_scratch_re <= csrbank0_scratch0_re; + maccore_bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_slot_w; end 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_length_w; end 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_errors_w; end 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_status_w; end 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_pending_w; end 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_enable0_w; end 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_start_w; + interface1_bank_bus_dat_r <= wishbone_interface_reader_start_w; end 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ready_w; end 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_level_w; end 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_slot0_w; end 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_length0_w; end 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_status_w; end 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_pending_w; end 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_enable0_w; end 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + interface1_bank_bus_dat_r <= csrbank1_preamble_crc_w; end 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_preamble_errors_w; end 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_crc_errors_w; end endcase end - main_sram9_re <= builder_csrbank1_sram_writer_slot_re; - main_sram12_re <= builder_csrbank1_sram_writer_length_re; - main_sram15_re <= builder_csrbank1_sram_writer_errors_re; - main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; - end - main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; - end - main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_sram96_re <= builder_csrbank1_sram_reader_ready_re; - main_sram99_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; - end - main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; - end - main_sram103_re <= builder_csrbank1_sram_reader_length0_re; - main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; - end - main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; - end - main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) + wishbone_interface_writer_slot_re <= csrbank1_sram_writer_slot_re; + wishbone_interface_writer_length_re <= csrbank1_sram_writer_length_re; + wishbone_interface_writer_errors_re <= csrbank1_sram_writer_errors_re; + wishbone_interface_writer_status_re <= csrbank1_sram_writer_ev_status_re; + if (csrbank1_sram_writer_ev_pending_re) begin + wishbone_interface_writer_pending_r <= csrbank1_sram_writer_ev_pending_r; + end + wishbone_interface_writer_pending_re <= csrbank1_sram_writer_ev_pending_re; + if (csrbank1_sram_writer_ev_enable0_re) begin + wishbone_interface_writer_enable_storage <= csrbank1_sram_writer_ev_enable0_r; + end + wishbone_interface_writer_enable_re <= csrbank1_sram_writer_ev_enable0_re; + wishbone_interface_reader_ready_re <= csrbank1_sram_reader_ready_re; + wishbone_interface_reader_level_re <= csrbank1_sram_reader_level_re; + if (csrbank1_sram_reader_slot0_re) begin + wishbone_interface_reader_slot_storage <= csrbank1_sram_reader_slot0_r; + end + wishbone_interface_reader_slot_re <= csrbank1_sram_reader_slot0_re; + if (csrbank1_sram_reader_length0_re) begin + wishbone_interface_reader_length_storage <= csrbank1_sram_reader_length0_r; + end + wishbone_interface_reader_length_re <= csrbank1_sram_reader_length0_re; + wishbone_interface_reader_status_re <= csrbank1_sram_reader_ev_status_re; + if (csrbank1_sram_reader_ev_pending_re) begin + wishbone_interface_reader_pending_r <= csrbank1_sram_reader_ev_pending_r; + end + wishbone_interface_reader_pending_re <= csrbank1_sram_reader_ev_pending_re; + if (csrbank1_sram_reader_ev_enable0_re) begin + wishbone_interface_reader_enable_storage <= csrbank1_sram_reader_ev_enable0_r; + end + wishbone_interface_reader_enable_re <= csrbank1_sram_reader_ev_enable0_re; + core_re <= csrbank1_preamble_crc_re; + core_preamble_errors_re <= csrbank1_rx_datapath_preamble_errors_re; + core_crc_errors_re <= csrbank1_rx_datapath_crc_errors_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + interface2_bank_bus_dat_r <= csrbank2_crg_reset0_w; end 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_w0_w; end 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_r_w; end endcase end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_crg_reset_storage <= builder_csrbank2_crg_reset0_r; + if (csrbank2_crg_reset0_re) begin + maccore_crg_reset_storage <= csrbank2_crg_reset0_r; end - main_maccore_crg_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + maccore_crg_reset_re <= csrbank2_crg_reset0_re; + if (csrbank2_mdio_w0_re) begin + maccore__w_storage <= csrbank2_mdio_w0_r; end - main_maccore__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore__r_re <= builder_csrbank2_mdio_r_re; + maccore__w_re <= csrbank2_mdio_w0_re; + maccore__r_re <= csrbank2_mdio_r_re; if (sys_rst) begin - main_maccore_reset_storage <= 2'd0; - main_maccore_reset_re <= 1'd0; - main_maccore_scratch_storage <= 32'd305419896; - main_maccore_scratch_re <= 1'd0; - main_maccore_bus_errors_re <= 1'd0; - main_maccore_bus_errors <= 32'd0; - main_maccore_crg_reset_storage <= 1'd0; - main_maccore_crg_reset_re <= 1'd0; - main_maccore_crg_counter <= 9'd0; - main_maccore__w_storage <= 3'd0; - main_maccore__w_re <= 1'd0; - main_maccore__r_re <= 1'd0; - main_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_sram9_re <= 1'd0; - main_sram12_re <= 1'd0; - main_sram13_status <= 32'd0; - main_sram15_re <= 1'd0; - main_sram24_re <= 1'd0; - main_sram28_re <= 1'd0; - main_sram29_r <= 1'd0; - main_sram31_storage <= 1'd0; - main_sram32_re <= 1'd0; - main_slot <= 1'd0; - main_sram35_length <= 11'd0; - main_sram55_level <= 2'd0; - main_sram57_produce <= 1'd0; - main_sram58_consume <= 1'd0; - main_sram96_re <= 1'd0; - main_sram99_re <= 1'd0; - main_sram101_re <= 1'd0; - main_sram103_re <= 1'd0; - main_sram106_pending <= 1'd0; - main_sram112_re <= 1'd0; - main_sram116_re <= 1'd0; - main_sram117_r <= 1'd0; - main_sram119_storage <= 1'd0; - main_sram120_re <= 1'd0; - main_sram122_length <= 11'd0; - main_sram141_level <= 2'd0; - main_sram143_produce <= 1'd0; - main_sram144_consume <= 1'd0; - main_interface0_ack <= 1'd0; - main_interface1_ack <= 1'd0; - main_interface2_ack <= 1'd0; - main_interface3_ack <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_state <= 1'd0; - end - builder_xilinxmultiregimpl00 <= main_maccore_data_r; - builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; - builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; - builder_xilinxmultiregimpl30 <= main_pulsesynchronizer0_toggle_i; - builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; - builder_xilinxmultiregimpl40 <= main_pulsesynchronizer1_toggle_i; - builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; - builder_xilinxmultiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; + maccore_reset_storage <= 2'd0; + maccore_reset_re <= 1'd0; + maccore_scratch_storage <= 32'd305419896; + maccore_scratch_re <= 1'd0; + maccore_bus_errors_re <= 1'd0; + maccore_bus_errors <= 32'd0; + maccore_crg_reset_storage <= 1'd0; + maccore_crg_reset_re <= 1'd0; + maccore_crg_counter <= 9'd0; + maccore__w_storage <= 3'd0; + maccore__w_re <= 1'd0; + maccore__r_re <= 1'd0; + core_re <= 1'd0; + core_tx_cdc_cdc_graycounter0_q <= 6'd0; + core_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + core_preamble_errors_status <= 32'd0; + core_preamble_errors_re <= 1'd0; + core_crc_errors_status <= 32'd0; + core_crc_errors_re <= 1'd0; + core_rx_cdc_cdc_graycounter1_q <= 6'd0; + core_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + wishbone_interface_writer_slot_re <= 1'd0; + wishbone_interface_writer_length_re <= 1'd0; + wishbone_interface_writer_errors_status <= 32'd0; + wishbone_interface_writer_errors_re <= 1'd0; + wishbone_interface_writer_status_re <= 1'd0; + wishbone_interface_writer_pending_re <= 1'd0; + wishbone_interface_writer_pending_r <= 1'd0; + wishbone_interface_writer_enable_storage <= 1'd0; + wishbone_interface_writer_enable_re <= 1'd0; + wishbone_interface_writer_slot <= 1'd0; + wishbone_interface_writer_length <= 11'd0; + wishbone_interface_writer_stat_fifo_level <= 2'd0; + wishbone_interface_writer_stat_fifo_produce <= 1'd0; + wishbone_interface_writer_stat_fifo_consume <= 1'd0; + wishbone_interface_reader_ready_re <= 1'd0; + wishbone_interface_reader_level_re <= 1'd0; + wishbone_interface_reader_slot_re <= 1'd0; + wishbone_interface_reader_length_re <= 1'd0; + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; + wishbone_interface_reader_status_re <= 1'd0; + wishbone_interface_reader_pending_re <= 1'd0; + wishbone_interface_reader_pending_r <= 1'd0; + wishbone_interface_reader_enable_storage <= 1'd0; + wishbone_interface_reader_enable_re <= 1'd0; + wishbone_interface_reader_length <= 11'd0; + wishbone_interface_reader_cmd_fifo_level <= 2'd0; + wishbone_interface_reader_cmd_fifo_produce <= 1'd0; + wishbone_interface_reader_cmd_fifo_consume <= 1'd0; + wishbone_interface_interface0_ack <= 1'd0; + wishbone_interface_interface1_ack <= 1'd0; + wishbone_interface_decoder0_slave_sel_r <= 2'd0; + wishbone_interface_interface2_ack <= 1'd0; + wishbone_interface_interface3_ack <= 1'd0; + wishbone_interface_decoder1_slave_sel_r <= 2'd0; + slave_sel_r <= 3'd0; + count <= 20'd1000000; + liteethmacsramwriter_state <= 3'd0; + liteethmacsramreader_state <= 2'd0; + state <= 1'd0; + end + xilinxmultiregimpl00 <= maccore_data_r; + xilinxmultiregimpl01 <= xilinxmultiregimpl00; + xilinxmultiregimpl20 <= core_tx_cdc_cdc_graycounter1_q; + xilinxmultiregimpl21 <= xilinxmultiregimpl20; + xilinxmultiregimpl30 <= core_pulsesynchronizer0_toggle_i; + xilinxmultiregimpl31 <= xilinxmultiregimpl30; + xilinxmultiregimpl40 <= core_pulsesynchronizer1_toggle_i; + xilinxmultiregimpl41 <= xilinxmultiregimpl40; + xilinxmultiregimpl50 <= core_rx_cdc_cdc_graycounter0_q; + xilinxmultiregimpl51 <= xilinxmultiregimpl50; end @@ -3806,8 +3732,8 @@ end // Specialized Logic //------------------------------------------------------------------------------ -assign mii_mdio = main_maccore_data_oe ? main_maccore_data_w : 1'bz; -assign main_maccore_data_r = mii_mdio; +assign mii_mdio = maccore_data_oe ? maccore_data_w : 1'bz; +assign maccore_data_r = mii_mdio; //------------------------------------------------------------------------------ // Memory storage: 32-words x 42-bit @@ -3818,15 +3744,15 @@ reg [41:0] storage[0:31]; reg [41:0] storage_dat0; reg [41:0] storage_dat1; always @(posedge sys_clk) begin - if (main_tx_cdc_cdc_wrport_we) - storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; + if (core_tx_cdc_cdc_wrport_we) + storage[core_tx_cdc_cdc_wrport_adr] <= core_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[core_tx_cdc_cdc_wrport_adr]; end always @(posedge eth_tx_clk) begin - storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; + storage_dat1 <= storage[core_tx_cdc_cdc_rdport_adr]; end -assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; -assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; +assign core_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign core_tx_cdc_cdc_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ @@ -3837,14 +3763,14 @@ assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; reg [11:0] storage_1[0:4]; reg [11:0] storage_1_dat0; always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; + if (core_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr] <= core_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr]; end always @(posedge eth_rx_clk) begin end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign core_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[core_liteethmaccrc32checker_syncfifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -3856,15 +3782,15 @@ reg [41:0] storage_2[0:31]; reg [41:0] storage_2_dat0; reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin - if (main_rx_cdc_cdc_wrport_we) - storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; + if (core_rx_cdc_cdc_wrport_we) + storage_2[core_rx_cdc_cdc_wrport_adr] <= core_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[core_rx_cdc_cdc_wrport_adr]; end always @(posedge sys_clk) begin - storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; + storage_2_dat1 <= storage_2[core_rx_cdc_cdc_rdport_adr]; end -assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; +assign core_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign core_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; //------------------------------------------------------------------------------ @@ -3875,14 +3801,14 @@ assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; reg [13:0] storage_3[0:1]; reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_sram61_we) - storage_3[main_sram59_adr] <= main_sram62_dat_w; - storage_3_dat0 <= storage_3[main_sram59_adr]; + if (wishbone_interface_writer_stat_fifo_wrport_we) + storage_3[wishbone_interface_writer_stat_fifo_wrport_adr] <= wishbone_interface_writer_stat_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[wishbone_interface_writer_stat_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram60_dat_r = storage_3_dat0; -assign main_sram65_dat_r = storage_3[main_sram64_adr]; +assign wishbone_interface_writer_stat_fifo_wrport_dat_r = storage_3_dat0; +assign wishbone_interface_writer_stat_fifo_rdport_dat_r = storage_3[wishbone_interface_writer_stat_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -3894,15 +3820,15 @@ reg [31:0] mem[0:382]; reg [8:0] mem_adr0; reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_sram77_we) - mem[main_sram75_adr] <= main_sram78_dat_w; - mem_adr0 <= main_sram75_adr; + if (wishbone_interface_writer_memory0_we) + mem[wishbone_interface_writer_memory0_adr] <= wishbone_interface_writer_memory0_dat_w; + mem_adr0 <= wishbone_interface_writer_memory0_adr; end always @(posedge sys_clk) begin - mem_dat1 <= mem[main_sram0_adr]; + mem_dat1 <= mem[wishbone_interface_sram0_adr]; end -assign main_sram76_dat_r = mem[mem_adr0]; -assign main_sram0_dat_r = mem_dat1; +assign wishbone_interface_writer_memory0_dat_r = mem[mem_adr0]; +assign wishbone_interface_sram0_dat_r = mem_dat1; //------------------------------------------------------------------------------ @@ -3914,15 +3840,15 @@ reg [31:0] mem_1[0:382]; reg [8:0] mem_1_adr0; reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_sram81_we) - mem_1[main_sram79_adr] <= main_sram82_dat_w; - mem_1_adr0 <= main_sram79_adr; + if (wishbone_interface_writer_memory1_we) + mem_1[wishbone_interface_writer_memory1_adr] <= wishbone_interface_writer_memory1_dat_w; + mem_1_adr0 <= wishbone_interface_writer_memory1_adr; end always @(posedge sys_clk) begin - mem_1_dat1 <= mem_1[main_sram1_adr]; + mem_1_dat1 <= mem_1[wishbone_interface_sram1_adr]; end -assign main_sram80_dat_r = mem_1[mem_1_adr0]; -assign main_sram1_dat_r = mem_1_dat1; +assign wishbone_interface_writer_memory1_dat_r = mem_1[mem_1_adr0]; +assign wishbone_interface_sram1_dat_r = mem_1_dat1; //------------------------------------------------------------------------------ @@ -3933,14 +3859,14 @@ assign main_sram1_dat_r = mem_1_dat1; reg [13:0] storage_4[0:1]; reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_sram147_we) - storage_4[main_sram145_adr] <= main_sram148_dat_w; - storage_4_dat0 <= storage_4[main_sram145_adr]; + if (wishbone_interface_reader_cmd_fifo_wrport_we) + storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr] <= wishbone_interface_reader_cmd_fifo_wrport_dat_w; + storage_4_dat0 <= storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram146_dat_r = storage_4_dat0; -assign main_sram151_dat_r = storage_4[main_sram150_adr]; +assign wishbone_interface_reader_cmd_fifo_wrport_dat_r = storage_4_dat0; +assign wishbone_interface_reader_cmd_fifo_rdport_dat_r = storage_4[wishbone_interface_reader_cmd_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -3952,22 +3878,22 @@ reg [31:0] mem_2[0:382]; reg [31:0] mem_2_dat0; reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - if (main_sram163_re) - mem_2_dat0 <= mem_2[main_sram161_adr]; + if (wishbone_interface_reader_memory0_re) + mem_2_dat0 <= mem_2[wishbone_interface_reader_memory0_adr]; end always @(posedge sys_clk) begin - if (main_sram2_we[0]) - mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; - if (main_sram2_we[1]) - mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; - if (main_sram2_we[2]) - mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; - if (main_sram2_we[3]) - mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; - mem_2_adr1 <= main_sram2_adr; -end -assign main_sram162_dat_r = mem_2_dat0; -assign main_sram2_dat_r = mem_2[mem_2_adr1]; + if (wishbone_interface_sram2_we[0]) + mem_2[wishbone_interface_sram2_adr][7:0] <= wishbone_interface_sram2_dat_w[7:0]; + if (wishbone_interface_sram2_we[1]) + mem_2[wishbone_interface_sram2_adr][15:8] <= wishbone_interface_sram2_dat_w[15:8]; + if (wishbone_interface_sram2_we[2]) + mem_2[wishbone_interface_sram2_adr][23:16] <= wishbone_interface_sram2_dat_w[23:16]; + if (wishbone_interface_sram2_we[3]) + mem_2[wishbone_interface_sram2_adr][31:24] <= wishbone_interface_sram2_dat_w[31:24]; + mem_2_adr1 <= wishbone_interface_sram2_adr; +end +assign wishbone_interface_reader_memory0_dat_r = mem_2_dat0; +assign wishbone_interface_sram2_dat_r = mem_2[mem_2_adr1]; //------------------------------------------------------------------------------ @@ -3979,22 +3905,22 @@ reg [31:0] mem_3[0:382]; reg [31:0] mem_3_dat0; reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - if (main_sram166_re) - mem_3_dat0 <= mem_3[main_sram164_adr]; + if (wishbone_interface_reader_memory1_re) + mem_3_dat0 <= mem_3[wishbone_interface_reader_memory1_adr]; end always @(posedge sys_clk) begin - if (main_sram3_we[0]) - mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; - if (main_sram3_we[1]) - mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; - if (main_sram3_we[2]) - mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; - if (main_sram3_we[3]) - mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; - mem_3_adr1 <= main_sram3_adr; -end -assign main_sram165_dat_r = mem_3_dat0; -assign main_sram3_dat_r = mem_3[mem_3_adr1]; + if (wishbone_interface_sram3_we[0]) + mem_3[wishbone_interface_sram3_adr][7:0] <= wishbone_interface_sram3_dat_w[7:0]; + if (wishbone_interface_sram3_we[1]) + mem_3[wishbone_interface_sram3_adr][15:8] <= wishbone_interface_sram3_dat_w[15:8]; + if (wishbone_interface_sram3_we[2]) + mem_3[wishbone_interface_sram3_adr][23:16] <= wishbone_interface_sram3_dat_w[23:16]; + if (wishbone_interface_sram3_we[3]) + mem_3[wishbone_interface_sram3_adr][31:24] <= wishbone_interface_sram3_dat_w[31:24]; + mem_3_adr1 <= wishbone_interface_sram3_adr; +end +assign wishbone_interface_reader_memory1_dat_r = mem_3_dat0; +assign wishbone_interface_sram3_dat_r = mem_3[mem_3_adr1]; (* ars_ff1 = "true", async_reg = "true" *) @@ -4009,10 +3935,10 @@ FDPE #( .C (eth_tx_clk), .CE (1'd1), .D (1'd0), - .PRE (main_maccore_crg_reset0), + .PRE (maccore_crg_reset0), // Outputs. - .Q (builder_rst_meta0) + .Q (rst_meta0) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4026,8 +3952,8 @@ FDPE #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D (builder_rst_meta0), - .PRE (main_maccore_crg_reset0), + .D (rst_meta0), + .PRE (maccore_crg_reset0), // Outputs. .Q (eth_tx_rst) @@ -4045,10 +3971,10 @@ FDPE #( .C (eth_rx_clk), .CE (1'd1), .D (1'd0), - .PRE (main_maccore_crg_reset0), + .PRE (maccore_crg_reset0), // Outputs. - .Q (builder_rst_meta1) + .Q (rst_meta1) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4062,8 +3988,8 @@ FDPE #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (builder_rst_meta1), - .PRE (main_maccore_crg_reset0), + .D (rst_meta1), + .PRE (maccore_crg_reset0), // Outputs. .Q (eth_rx_rst) @@ -4072,5 +3998,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-05 17:38:49. +// Auto-Generated by LiteX on 2025-02-15 16:17:45. //------------------------------------------------------------------------------ diff --git a/liteeth/generated/ecpix-5/liteeth_core.v b/liteeth/generated/ecpix-5/liteeth_core.v index 50fde14..5b328c3 100644 --- a/liteeth/generated/ecpix-5/liteeth_core.v +++ b/liteeth/generated/ecpix-5/liteeth_core.v @@ -8,8 +8,8 @@ // // Filename : liteeth_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-09 14:20:58 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 16:17:46 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -92,7 +92,8 @@ MACCore │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) -│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── last_handler (LiteEthLastHandler) +│ │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) @@ -149,9 +150,11 @@ MACCore │ │ │ └─── ev (SharedIRQ) │ │ └─── sram_0* (SRAM) │ │ └─── sram_1* (SRAM) +│ │ └─── decoder_0* (Decoder) │ │ └─── sram_2* (SRAM) │ │ └─── sram_3* (SRAM) -│ │ └─── decoder_0* (Decoder) +│ │ └─── decoder_1* (Decoder) +│ └─── ev (SharedIRQ) └─── csr_bridge (Wishbone2CSR) │ └─── fsm (FSM) └─── csr_bankarray (CSRBankArray) @@ -182,21 +185,22 @@ MACCore │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstatus_1* (CSRStatus) └─── csr_interconnect (InterconnectShared) -└─── [ODDRX1F] └─── [IDDRX1F] +└─── [IDDRX1F] +└─── [IDDRX1F] +└─── [IDDRX1F] +└─── [BB] └─── [ODDRX1F] └─── [ODDRX1F] └─── [FD1S3BX] └─── [FD1S3BX] └─── [ODDRX1F] -└─── [IDDRX1F] -└─── [IDDRX1F] -└─── [FD1S3BX] -└─── [ODDRX1F] └─── [ODDRX1F] └─── [FD1S3BX] └─── [IDDRX1F] -└─── [IDDRX1F] +└─── [ODDRX1F] +└─── [FD1S3BX] +└─── [ODDRX1F] * : Generated name. []: BlackBox. */ @@ -205,1412 +209,1402 @@ MACCore // Signals //------------------------------------------------------------------------------ -wire [13:0] builder_adr; -wire [39:0] builder_complexslicelowerer_slice_proxy; -reg [19:0] builder_count = 20'd1000000; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_reset0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_scratch0_we = 1'd0; -wire builder_csrbank0_sel; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; -reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; -reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; -reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; -reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; -wire builder_csrbank1_sel; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_w; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] builder_csrbank2_rx_inband_status_r; -reg builder_csrbank2_rx_inband_status_re = 1'd0; -wire [2:0] builder_csrbank2_rx_inband_status_w; -reg builder_csrbank2_rx_inband_status_we = 1'd0; -wire builder_csrbank2_sel; -wire [31:0] builder_dat_r; -wire [31:0] builder_dat_w; -wire builder_done; -reg builder_error = 1'd0; -wire builder_grant; -reg builder_interface0_ack = 1'd0; -wire [29:0] builder_interface0_adr; -wire [13:0] builder_interface0_bank_bus_adr; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface0_bank_bus_dat_w; -wire builder_interface0_bank_bus_we; -wire [1:0] builder_interface0_bte; -wire [2:0] builder_interface0_cti; -wire builder_interface0_cyc; -reg [31:0] builder_interface0_dat_r = 32'd0; -wire [31:0] builder_interface0_dat_w; -reg builder_interface0_err = 1'd0; -wire [3:0] builder_interface0_sel; -wire builder_interface0_stb; -wire builder_interface0_we; -reg [13:0] builder_interface1_adr = 14'd0; -wire [13:0] builder_interface1_bank_bus_adr; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface1_bank_bus_dat_w; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_dat_r; -reg [31:0] builder_interface1_dat_w = 32'd0; -reg builder_interface1_we = 1'd0; -wire [13:0] builder_interface2_bank_bus_adr; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface2_bank_bus_dat_w; -wire builder_interface2_bank_bus_we; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +wire [13:0] adr; +wire core_bufferizeendpoints_pipe_valid_sink_first; +wire core_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] core_bufferizeendpoints_pipe_valid_sink_payload_data; +wire core_bufferizeendpoints_pipe_valid_sink_payload_error; +wire core_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire core_bufferizeendpoints_pipe_valid_sink_ready; +wire core_bufferizeendpoints_pipe_valid_sink_valid; +reg core_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] core_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire core_bufferizeendpoints_pipe_valid_source_ready; +reg core_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire core_bufferizeendpoints_sink_sink_first; +wire core_bufferizeendpoints_sink_sink_last; +wire [7:0] core_bufferizeendpoints_sink_sink_payload_data; +wire core_bufferizeendpoints_sink_sink_payload_error; +wire core_bufferizeendpoints_sink_sink_payload_last_be; +wire core_bufferizeendpoints_sink_sink_ready; +wire core_bufferizeendpoints_sink_sink_valid; +wire core_bufferizeendpoints_source_source_first; +wire core_bufferizeendpoints_source_source_last; +wire [7:0] core_bufferizeendpoints_source_source_payload_data; +wire core_bufferizeendpoints_source_source_payload_error; +wire core_bufferizeendpoints_source_source_payload_last_be; +wire core_bufferizeendpoints_source_source_ready; +wire core_bufferizeendpoints_source_source_valid; +reg core_crc_errors_re = 1'd0; +reg [31:0] core_crc_errors_status = 32'd0; +wire core_crc_errors_we; +wire core_liteethmaccrc32checker_crc_be; +reg core_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] core_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] core_liteethmaccrc32checker_crc_data0; +wire [7:0] core_liteethmaccrc32checker_crc_data1; +reg core_liteethmaccrc32checker_crc_error0 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg core_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_value = 32'd0; +reg core_liteethmaccrc32checker_error = 1'd0; +wire core_liteethmaccrc32checker_fifo_full; +wire core_liteethmaccrc32checker_fifo_in; +wire core_liteethmaccrc32checker_fifo_out; +reg core_liteethmaccrc32checker_fifo_reset = 1'd0; +reg core_liteethmaccrc32checker_last_be = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_first; +wire core_liteethmaccrc32checker_sink_sink_last; +wire [7:0] core_liteethmaccrc32checker_sink_sink_payload_data; +wire core_liteethmaccrc32checker_sink_sink_payload_error; +wire core_liteethmaccrc32checker_sink_sink_payload_last_be; +reg core_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_valid; +wire core_liteethmaccrc32checker_source_source_first; +reg core_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] core_liteethmaccrc32checker_source_source_payload_data; +reg core_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg core_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire core_liteethmaccrc32checker_source_source_ready; +reg core_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire core_liteethmaccrc32checker_syncfifo_do_read; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] core_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] core_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg core_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_sink_first; +wire core_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_sink_ready; +reg core_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_first; +wire core_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_source_payload_data; +wire core_liteethmaccrc32checker_syncfifo_source_payload_error; +wire core_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg core_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] core_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire core_liteethmaccrc32checker_syncfifo_wrport_we; +reg core_preamble_errors_re = 1'd0; +reg [31:0] core_preamble_errors_status = 32'd0; +wire core_preamble_errors_we; +wire core_pulsesynchronizer0_i; +wire core_pulsesynchronizer0_o; +reg core_pulsesynchronizer0_toggle_i = 1'd0; +wire core_pulsesynchronizer0_toggle_o; +reg core_pulsesynchronizer0_toggle_o_r = 1'd0; +wire core_pulsesynchronizer1_i; +wire core_pulsesynchronizer1_o; +reg core_pulsesynchronizer1_toggle_i = 1'd0; +wire core_pulsesynchronizer1_toggle_o; +reg core_pulsesynchronizer1_toggle_o_r = 1'd0; +reg core_re = 1'd0; +wire [41:0] core_rx_cdc_cdc_asyncfifo_din; +wire [41:0] core_rx_cdc_cdc_asyncfifo_dout; +wire core_rx_cdc_cdc_asyncfifo_re; +wire core_rx_cdc_cdc_asyncfifo_readable; +wire core_rx_cdc_cdc_asyncfifo_we; +wire core_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_rx_cdc_cdc_consume_wdomain; +wire core_rx_cdc_cdc_fifo_in_first; +wire core_rx_cdc_cdc_fifo_in_last; +wire [31:0] core_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_last_be; +wire core_rx_cdc_cdc_fifo_out_first; +wire core_rx_cdc_cdc_fifo_out_last; +wire [31:0] core_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_last_be; +wire core_rx_cdc_cdc_graycounter0_ce; (* syn_no_retiming = "true" *) -reg builder_multiregimpl00 = 1'd0; +reg [5:0] core_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_rx_cdc_cdc_graycounter1_ce; (* syn_no_retiming = "true" *) -reg builder_multiregimpl01 = 1'd0; +reg [5:0] core_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_produce_rdomain; +wire [4:0] core_rx_cdc_cdc_rdport_adr; +wire [41:0] core_rx_cdc_cdc_rdport_dat_r; +wire core_rx_cdc_cdc_sink_first; +wire core_rx_cdc_cdc_sink_last; +wire [31:0] core_rx_cdc_cdc_sink_payload_data; +wire [3:0] core_rx_cdc_cdc_sink_payload_error; +wire [3:0] core_rx_cdc_cdc_sink_payload_last_be; +wire core_rx_cdc_cdc_sink_ready; +wire core_rx_cdc_cdc_sink_valid; +wire core_rx_cdc_cdc_source_first; +wire core_rx_cdc_cdc_source_last; +wire [31:0] core_rx_cdc_cdc_source_payload_data; +wire [3:0] core_rx_cdc_cdc_source_payload_error; +wire [3:0] core_rx_cdc_cdc_source_payload_last_be; +wire core_rx_cdc_cdc_source_ready; +wire core_rx_cdc_cdc_source_valid; +wire [4:0] core_rx_cdc_cdc_wrport_adr; +wire [41:0] core_rx_cdc_cdc_wrport_dat_r; +wire [41:0] core_rx_cdc_cdc_wrport_dat_w; +wire core_rx_cdc_cdc_wrport_we; +wire core_rx_cdc_sink_sink_first; +wire core_rx_cdc_sink_sink_last; +wire [31:0] core_rx_cdc_sink_sink_payload_data; +wire [3:0] core_rx_cdc_sink_sink_payload_error; +wire [3:0] core_rx_cdc_sink_sink_payload_last_be; +wire core_rx_cdc_sink_sink_ready; +wire core_rx_cdc_sink_sink_valid; +wire core_rx_cdc_source_source_first; +wire core_rx_cdc_source_source_last; +wire [31:0] core_rx_cdc_source_source_payload_data; +wire [3:0] core_rx_cdc_source_source_payload_error; +wire [3:0] core_rx_cdc_source_source_payload_last_be; +wire core_rx_cdc_source_source_ready; +wire core_rx_cdc_source_source_valid; +reg [1:0] core_rx_converter_converter_demux = 2'd0; +wire core_rx_converter_converter_load_part; +wire core_rx_converter_converter_sink_first; +wire core_rx_converter_converter_sink_last; +wire [9:0] core_rx_converter_converter_sink_payload_data; +wire core_rx_converter_converter_sink_ready; +wire core_rx_converter_converter_sink_valid; +reg core_rx_converter_converter_source_first = 1'd0; +reg core_rx_converter_converter_source_last = 1'd0; +reg [39:0] core_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] core_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire core_rx_converter_converter_source_ready; +wire core_rx_converter_converter_source_valid; +reg core_rx_converter_converter_strobe_all = 1'd0; +wire core_rx_converter_sink_first; +wire core_rx_converter_sink_last; +wire [7:0] core_rx_converter_sink_payload_data; +wire core_rx_converter_sink_payload_error; +wire core_rx_converter_sink_payload_last_be; +wire core_rx_converter_sink_ready; +wire core_rx_converter_sink_valid; +wire core_rx_converter_source_first; +wire core_rx_converter_source_last; +reg [31:0] core_rx_converter_source_payload_data = 32'd0; +reg [3:0] core_rx_converter_source_payload_error = 4'd0; +reg [3:0] core_rx_converter_source_payload_last_be = 4'd0; +wire core_rx_converter_source_ready; +wire core_rx_converter_source_source_first; +wire core_rx_converter_source_source_last; +wire [39:0] core_rx_converter_source_source_payload_data; +wire core_rx_converter_source_source_ready; +wire core_rx_converter_source_source_valid; +wire core_rx_converter_source_valid; +wire core_rx_last_be_sink_first; +wire core_rx_last_be_sink_last; +wire [7:0] core_rx_last_be_sink_payload_data; +wire core_rx_last_be_sink_payload_error; +wire core_rx_last_be_sink_payload_last_be; +wire core_rx_last_be_sink_ready; +wire core_rx_last_be_sink_valid; +wire core_rx_last_be_source_first; +wire core_rx_last_be_source_last; +wire [7:0] core_rx_last_be_source_payload_data; +wire core_rx_last_be_source_payload_error; +reg core_rx_last_be_source_payload_last_be = 1'd0; +wire core_rx_last_be_source_ready; +wire core_rx_last_be_source_valid; +wire core_rx_padding_sink_first; +wire core_rx_padding_sink_last; +wire [7:0] core_rx_padding_sink_payload_data; +wire core_rx_padding_sink_payload_error; +wire core_rx_padding_sink_payload_last_be; +wire core_rx_padding_sink_ready; +wire core_rx_padding_sink_valid; +wire core_rx_padding_source_first; +wire core_rx_padding_source_last; +wire [7:0] core_rx_padding_source_payload_data; +wire core_rx_padding_source_payload_error; +wire core_rx_padding_source_payload_last_be; +wire core_rx_padding_source_ready; +wire core_rx_padding_source_valid; +reg core_rx_preamble_error = 1'd0; +reg [63:0] core_rx_preamble_preamble = 64'd15372286728091293013; +wire core_rx_preamble_sink_first; +wire core_rx_preamble_sink_last; +wire [7:0] core_rx_preamble_sink_payload_data; +wire core_rx_preamble_sink_payload_error; +wire core_rx_preamble_sink_payload_last_be; +reg core_rx_preamble_sink_ready = 1'd0; +wire core_rx_preamble_sink_valid; +reg core_rx_preamble_source_first = 1'd0; +reg core_rx_preamble_source_last = 1'd0; +wire [7:0] core_rx_preamble_source_payload_data; +reg core_rx_preamble_source_payload_error = 1'd0; +wire core_rx_preamble_source_payload_last_be; +wire core_rx_preamble_source_ready; +reg core_rx_preamble_source_valid = 1'd0; +wire core_sink_first; +wire core_sink_last; +wire [31:0] core_sink_payload_data; +wire [3:0] core_sink_payload_error; +wire [3:0] core_sink_payload_last_be; +wire core_sink_ready; +wire core_sink_valid; +wire core_source_first; +wire core_source_last; +wire [31:0] core_source_payload_data; +wire [3:0] core_source_payload_error; +wire [3:0] core_source_payload_last_be; +wire core_source_ready; +wire core_source_valid; +reg core_status = 1'd1; +wire [41:0] core_tx_cdc_cdc_asyncfifo_din; +wire [41:0] core_tx_cdc_cdc_asyncfifo_dout; +wire core_tx_cdc_cdc_asyncfifo_re; +wire core_tx_cdc_cdc_asyncfifo_readable; +wire core_tx_cdc_cdc_asyncfifo_we; +wire core_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_tx_cdc_cdc_consume_wdomain; +wire core_tx_cdc_cdc_fifo_in_first; +wire core_tx_cdc_cdc_fifo_in_last; +wire [31:0] core_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_last_be; +wire core_tx_cdc_cdc_fifo_out_first; +wire core_tx_cdc_cdc_fifo_out_last; +wire [31:0] core_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_last_be; +wire core_tx_cdc_cdc_graycounter0_ce; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl10 = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_tx_cdc_cdc_graycounter1_ce; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl11 = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_produce_rdomain; +wire [4:0] core_tx_cdc_cdc_rdport_adr; +wire [41:0] core_tx_cdc_cdc_rdport_dat_r; +wire core_tx_cdc_cdc_sink_first; +wire core_tx_cdc_cdc_sink_last; +wire [31:0] core_tx_cdc_cdc_sink_payload_data; +wire [3:0] core_tx_cdc_cdc_sink_payload_error; +wire [3:0] core_tx_cdc_cdc_sink_payload_last_be; +wire core_tx_cdc_cdc_sink_ready; +wire core_tx_cdc_cdc_sink_valid; +wire core_tx_cdc_cdc_source_first; +wire core_tx_cdc_cdc_source_last; +wire [31:0] core_tx_cdc_cdc_source_payload_data; +wire [3:0] core_tx_cdc_cdc_source_payload_error; +wire [3:0] core_tx_cdc_cdc_source_payload_last_be; +wire core_tx_cdc_cdc_source_ready; +wire core_tx_cdc_cdc_source_valid; +wire [4:0] core_tx_cdc_cdc_wrport_adr; +wire [41:0] core_tx_cdc_cdc_wrport_dat_r; +wire [41:0] core_tx_cdc_cdc_wrport_dat_w; +wire core_tx_cdc_cdc_wrport_we; +wire core_tx_cdc_sink_sink_first; +wire core_tx_cdc_sink_sink_last; +wire [31:0] core_tx_cdc_sink_sink_payload_data; +wire [3:0] core_tx_cdc_sink_sink_payload_error; +wire [3:0] core_tx_cdc_sink_sink_payload_last_be; +wire core_tx_cdc_sink_sink_ready; +wire core_tx_cdc_sink_sink_valid; +wire core_tx_cdc_source_source_first; +wire core_tx_cdc_source_source_last; +wire [31:0] core_tx_cdc_source_source_payload_data; +wire [3:0] core_tx_cdc_source_source_payload_error; +wire [3:0] core_tx_cdc_source_source_payload_last_be; +wire core_tx_cdc_source_source_ready; +wire core_tx_cdc_source_source_valid; +wire core_tx_converter_converter_first; +wire core_tx_converter_converter_last; +reg [1:0] core_tx_converter_converter_mux = 2'd0; +wire core_tx_converter_converter_sink_first; +wire core_tx_converter_converter_sink_last; +reg [39:0] core_tx_converter_converter_sink_payload_data = 40'd0; +wire core_tx_converter_converter_sink_ready; +wire core_tx_converter_converter_sink_valid; +wire core_tx_converter_converter_source_first; +wire core_tx_converter_converter_source_last; +reg [9:0] core_tx_converter_converter_source_payload_data = 10'd0; +wire core_tx_converter_converter_source_payload_valid_token_count; +wire core_tx_converter_converter_source_ready; +wire core_tx_converter_converter_source_valid; +wire core_tx_converter_sink_first; +wire core_tx_converter_sink_last; +wire [31:0] core_tx_converter_sink_payload_data; +wire [3:0] core_tx_converter_sink_payload_error; +wire [3:0] core_tx_converter_sink_payload_last_be; +wire core_tx_converter_sink_ready; +wire core_tx_converter_sink_valid; +wire core_tx_converter_source_first; +wire core_tx_converter_source_last; +wire [7:0] core_tx_converter_source_payload_data; +wire core_tx_converter_source_payload_error; +wire core_tx_converter_source_payload_last_be; +wire core_tx_converter_source_ready; +wire core_tx_converter_source_source_first; +wire core_tx_converter_source_source_last; +wire [9:0] core_tx_converter_source_source_payload_data; +wire core_tx_converter_source_source_ready; +wire core_tx_converter_source_source_valid; +wire core_tx_converter_source_valid; +wire core_tx_crc_be; +reg core_tx_crc_ce = 1'd0; +reg [1:0] core_tx_crc_cnt = 2'd3; +wire core_tx_crc_cnt_done; +reg [31:0] core_tx_crc_crc_next = 32'd0; +reg [31:0] core_tx_crc_crc_packet = 32'd0; +reg [31:0] core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] core_tx_crc_crc_prev; +wire [7:0] core_tx_crc_data0; +wire [7:0] core_tx_crc_data1; +reg core_tx_crc_error = 1'd0; +reg core_tx_crc_is_ongoing0 = 1'd0; +reg core_tx_crc_is_ongoing1 = 1'd0; +reg core_tx_crc_last_be = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire core_tx_crc_pipe_valid_sink_first; +wire core_tx_crc_pipe_valid_sink_last; +wire [7:0] core_tx_crc_pipe_valid_sink_payload_data; +wire core_tx_crc_pipe_valid_sink_payload_error; +wire core_tx_crc_pipe_valid_sink_payload_last_be; +wire core_tx_crc_pipe_valid_sink_ready; +wire core_tx_crc_pipe_valid_sink_valid; +reg core_tx_crc_pipe_valid_source_first = 1'd0; +reg core_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] core_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg core_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg core_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire core_tx_crc_pipe_valid_source_ready; +reg core_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] core_tx_crc_reg = 32'd4294967295; +reg core_tx_crc_reset = 1'd0; +wire core_tx_crc_sink_first; +wire core_tx_crc_sink_last; +wire [7:0] core_tx_crc_sink_payload_data; +wire core_tx_crc_sink_payload_error; +wire core_tx_crc_sink_payload_last_be; +reg core_tx_crc_sink_ready = 1'd0; +wire core_tx_crc_sink_sink_first; +wire core_tx_crc_sink_sink_last; +wire [7:0] core_tx_crc_sink_sink_payload_data; +wire core_tx_crc_sink_sink_payload_error; +wire core_tx_crc_sink_sink_payload_last_be; +wire core_tx_crc_sink_sink_ready; +wire core_tx_crc_sink_sink_valid; +wire core_tx_crc_sink_valid; +reg core_tx_crc_source_first = 1'd0; +reg core_tx_crc_source_last = 1'd0; +reg [7:0] core_tx_crc_source_payload_data = 8'd0; +reg core_tx_crc_source_payload_error = 1'd0; +reg core_tx_crc_source_payload_last_be = 1'd0; +wire core_tx_crc_source_ready; +wire core_tx_crc_source_source_first; +wire core_tx_crc_source_source_last; +wire [7:0] core_tx_crc_source_source_payload_data; +wire core_tx_crc_source_source_payload_error; +wire core_tx_crc_source_source_payload_last_be; +wire core_tx_crc_source_source_ready; +wire core_tx_crc_source_source_valid; +reg core_tx_crc_source_valid = 1'd0; +reg [31:0] core_tx_crc_value = 32'd0; +reg [3:0] core_tx_gap_counter = 4'd0; +reg [3:0] core_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg core_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire core_tx_gap_sink_first; +wire core_tx_gap_sink_last; +wire [7:0] core_tx_gap_sink_payload_data; +wire core_tx_gap_sink_payload_error; +wire core_tx_gap_sink_payload_last_be; +reg core_tx_gap_sink_ready = 1'd0; +wire core_tx_gap_sink_valid; +reg core_tx_gap_source_first = 1'd0; +reg core_tx_gap_source_last = 1'd0; +reg [7:0] core_tx_gap_source_payload_data = 8'd0; +reg core_tx_gap_source_payload_error = 1'd0; +reg core_tx_gap_source_payload_last_be = 1'd0; +wire core_tx_gap_source_ready; +reg core_tx_gap_source_valid = 1'd0; +wire core_tx_last_be_last_handler_sink_first; +wire core_tx_last_be_last_handler_sink_last; +wire [7:0] core_tx_last_be_last_handler_sink_payload_data; +wire core_tx_last_be_last_handler_sink_payload_error; +wire core_tx_last_be_last_handler_sink_payload_last_be; +reg core_tx_last_be_last_handler_sink_ready = 1'd0; +wire core_tx_last_be_last_handler_sink_valid; +reg core_tx_last_be_last_handler_source_first = 1'd0; +reg core_tx_last_be_last_handler_source_last = 1'd0; +reg [7:0] core_tx_last_be_last_handler_source_payload_data = 8'd0; +reg core_tx_last_be_last_handler_source_payload_error = 1'd0; +reg core_tx_last_be_last_handler_source_payload_last_be = 1'd0; +wire core_tx_last_be_last_handler_source_ready; +reg core_tx_last_be_last_handler_source_valid = 1'd0; +wire core_tx_last_be_sink_sink_first; +wire core_tx_last_be_sink_sink_last; +wire [7:0] core_tx_last_be_sink_sink_payload_data; +wire core_tx_last_be_sink_sink_payload_error; +wire core_tx_last_be_sink_sink_payload_last_be; +wire core_tx_last_be_sink_sink_ready; +wire core_tx_last_be_sink_sink_valid; +wire core_tx_last_be_source_source_first; +wire core_tx_last_be_source_source_last; +wire [7:0] core_tx_last_be_source_source_payload_data; +wire core_tx_last_be_source_source_payload_error; +wire core_tx_last_be_source_source_payload_last_be; +wire core_tx_last_be_source_source_ready; +wire core_tx_last_be_source_source_valid; +reg [15:0] core_tx_padding_counter = 16'd0; +reg [15:0] core_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg core_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire core_tx_padding_counter_done; +wire core_tx_padding_sink_first; +wire core_tx_padding_sink_last; +wire [7:0] core_tx_padding_sink_payload_data; +wire core_tx_padding_sink_payload_error; +wire core_tx_padding_sink_payload_last_be; +reg core_tx_padding_sink_ready = 1'd0; +wire core_tx_padding_sink_valid; +reg core_tx_padding_source_first = 1'd0; +reg core_tx_padding_source_last = 1'd0; +reg [7:0] core_tx_padding_source_payload_data = 8'd0; +reg core_tx_padding_source_payload_error = 1'd0; +reg core_tx_padding_source_payload_last_be = 1'd0; +wire core_tx_padding_source_ready; +reg core_tx_padding_source_valid = 1'd0; +reg [2:0] core_tx_preamble_count = 3'd0; +reg [2:0] core_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg core_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] core_tx_preamble_preamble = 64'd15372286728091293013; +wire core_tx_preamble_sink_first; +wire core_tx_preamble_sink_last; +wire [7:0] core_tx_preamble_sink_payload_data; +wire core_tx_preamble_sink_payload_error; +wire core_tx_preamble_sink_payload_last_be; +reg core_tx_preamble_sink_ready = 1'd0; +wire core_tx_preamble_sink_valid; +reg core_tx_preamble_source_first = 1'd0; +reg core_tx_preamble_source_last = 1'd0; +reg [7:0] core_tx_preamble_source_payload_data = 8'd0; +reg core_tx_preamble_source_payload_error = 1'd0; +wire core_tx_preamble_source_payload_last_be; +wire core_tx_preamble_source_ready; +reg core_tx_preamble_source_valid = 1'd0; +wire core_we; +reg [19:0] count = 20'd1000000; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire csrbank1_preamble_crc_r; +reg csrbank1_preamble_crc_re = 1'd0; +wire csrbank1_preamble_crc_w; +reg csrbank1_preamble_crc_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_r; +reg csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_w; +reg csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_r; +reg csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_w; +reg csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire csrbank1_sel; +wire csrbank1_sram_reader_ev_enable0_r; +reg csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire csrbank1_sram_reader_ev_enable0_w; +reg csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire csrbank1_sram_reader_ev_pending_r; +reg csrbank1_sram_reader_ev_pending_re = 1'd0; +wire csrbank1_sram_reader_ev_pending_w; +reg csrbank1_sram_reader_ev_pending_we = 1'd0; +wire csrbank1_sram_reader_ev_status_r; +reg csrbank1_sram_reader_ev_status_re = 1'd0; +wire csrbank1_sram_reader_ev_status_w; +reg csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_r; +reg csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_w; +reg csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] csrbank1_sram_reader_level_r; +reg csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] csrbank1_sram_reader_level_w; +reg csrbank1_sram_reader_level_we = 1'd0; +wire csrbank1_sram_reader_ready_r; +reg csrbank1_sram_reader_ready_re = 1'd0; +wire csrbank1_sram_reader_ready_w; +reg csrbank1_sram_reader_ready_we = 1'd0; +wire csrbank1_sram_reader_slot0_r; +reg csrbank1_sram_reader_slot0_re = 1'd0; +wire csrbank1_sram_reader_slot0_w; +reg csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_r; +reg csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_w; +reg csrbank1_sram_writer_errors_we = 1'd0; +wire csrbank1_sram_writer_ev_enable0_r; +reg csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire csrbank1_sram_writer_ev_enable0_w; +reg csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire csrbank1_sram_writer_ev_pending_r; +reg csrbank1_sram_writer_ev_pending_re = 1'd0; +wire csrbank1_sram_writer_ev_pending_w; +reg csrbank1_sram_writer_ev_pending_we = 1'd0; +wire csrbank1_sram_writer_ev_status_r; +reg csrbank1_sram_writer_ev_status_re = 1'd0; +wire csrbank1_sram_writer_ev_status_w; +reg csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_writer_length_r; +reg csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] csrbank1_sram_writer_length_w; +reg csrbank1_sram_writer_length_we = 1'd0; +wire csrbank1_sram_writer_slot_r; +reg csrbank1_sram_writer_slot_re = 1'd0; +wire csrbank1_sram_writer_slot_w; +reg csrbank1_sram_writer_slot_we = 1'd0; +wire csrbank2_crg_reset0_r; +reg csrbank2_crg_reset0_re = 1'd0; +wire csrbank2_crg_reset0_w; +reg csrbank2_crg_reset0_we = 1'd0; +wire csrbank2_mdio_r_r; +reg csrbank2_mdio_r_re = 1'd0; +wire csrbank2_mdio_r_w; +reg csrbank2_mdio_r_we = 1'd0; +wire [2:0] csrbank2_mdio_w0_r; +reg csrbank2_mdio_w0_re = 1'd0; +wire [2:0] csrbank2_mdio_w0_w; +reg csrbank2_mdio_w0_we = 1'd0; +wire [3:0] csrbank2_rx_inband_status_r; +reg csrbank2_rx_inband_status_re = 1'd0; +wire [3:0] csrbank2_rx_inband_status_w; +reg csrbank2_rx_inband_status_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire done; +reg error = 1'd0; +(* syn_keep = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* syn_keep = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire grant; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; +wire interface2_bank_bus_we; +reg [1:0] liteethmacsramreader_next_state = 2'd0; +reg [1:0] liteethmacsramreader_state = 2'd0; +reg [2:0] liteethmacsramwriter_next_state = 3'd0; +reg [2:0] liteethmacsramwriter_state = 3'd0; +reg maccore_ethphy__r_re = 1'd0; +reg maccore_ethphy__r_status = 1'd0; +wire maccore_ethphy__r_we; +reg maccore_ethphy__w_re = 1'd0; +reg [2:0] maccore_ethphy__w_storage = 3'd0; +reg [1:0] maccore_ethphy_clock_speed = 2'd0; +wire maccore_ethphy_data_oe; +wire maccore_ethphy_data_r; +wire maccore_ethphy_data_w; +reg maccore_ethphy_duplex_status = 1'd0; +wire maccore_ethphy_eth_tx_clk_o; +wire maccore_ethphy_last; +reg maccore_ethphy_link_status = 1'd0; +wire maccore_ethphy_mdc; +wire maccore_ethphy_oe; +reg maccore_ethphy_r = 1'd0; +reg maccore_ethphy_re = 1'd0; +wire maccore_ethphy_reset; +reg maccore_ethphy_reset_re = 1'd0; +reg maccore_ethphy_reset_storage = 1'd0; +wire [1:0] maccore_ethphy_rx_ctl; +wire maccore_ethphy_rx_ctl_delayf; +reg [1:0] maccore_ethphy_rx_ctl_reg = 2'd0; +reg [1:0] maccore_ethphy_rx_ctl_reg_d = 2'd0; +wire [7:0] maccore_ethphy_rx_data; +wire [3:0] maccore_ethphy_rx_data_delayf; +reg [7:0] maccore_ethphy_rx_data_reg = 8'd0; +wire maccore_ethphy_sink_first; +wire maccore_ethphy_sink_last; +wire [7:0] maccore_ethphy_sink_payload_data; +wire maccore_ethphy_sink_payload_error; +wire maccore_ethphy_sink_payload_last_be; +wire maccore_ethphy_sink_ready; +wire maccore_ethphy_sink_valid; +reg maccore_ethphy_source_first = 1'd0; +wire maccore_ethphy_source_last; +reg [7:0] maccore_ethphy_source_payload_data = 8'd0; +reg maccore_ethphy_source_payload_error = 1'd0; +reg maccore_ethphy_source_payload_last_be = 1'd0; +wire maccore_ethphy_source_ready; +reg maccore_ethphy_source_valid = 1'd0; +reg [3:0] maccore_ethphy_status = 4'd0; +wire maccore_ethphy_tx_ctl_oddrx1f; +wire [3:0] maccore_ethphy_tx_data_oddrx1f; +wire maccore_ethphy_w; +wire maccore_ethphy_we; +reg maccore_int_rst = 1'd1; +wire maccore_maccore_bus_error; +reg [31:0] maccore_maccore_bus_errors = 32'd0; +reg maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] maccore_maccore_bus_errors_status; +wire maccore_maccore_bus_errors_we; +wire maccore_maccore_cpu_rst; +reg maccore_maccore_reset_re = 1'd0; +reg [1:0] maccore_maccore_reset_storage = 2'd0; +reg maccore_maccore_scratch_re = 1'd0; +reg [31:0] maccore_maccore_scratch_storage = 32'd305419896; +reg maccore_maccore_soc_rst = 1'd0; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl20 = 6'd0; +reg multiregimpl00 = 1'd0; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl21 = 6'd0; +reg multiregimpl01 = 1'd0; (* syn_no_retiming = "true" *) -reg builder_multiregimpl30 = 1'd0; +reg [5:0] multiregimpl10 = 6'd0; (* syn_no_retiming = "true" *) -reg builder_multiregimpl31 = 1'd0; +reg [5:0] multiregimpl11 = 6'd0; (* syn_no_retiming = "true" *) -reg builder_multiregimpl40 = 1'd0; +reg [5:0] multiregimpl20 = 6'd0; (* syn_no_retiming = "true" *) -reg builder_multiregimpl41 = 1'd0; +reg [5:0] multiregimpl21 = 6'd0; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl50 = 6'd0; +reg multiregimpl30 = 1'd0; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl51 = 6'd0; +reg multiregimpl31 = 1'd0; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl60 = 6'd0; +reg multiregimpl40 = 1'd0; (* syn_no_retiming = "true" *) -reg [5:0] builder_multiregimpl61 = 6'd0; -reg builder_next_state = 1'd0; -wire builder_request; -wire builder_rst10; -wire builder_rst11; -reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; -reg [29:0] builder_self0 = 30'd0; -reg [31:0] builder_self1 = 32'd0; -reg [3:0] builder_self2 = 4'd0; -reg builder_self3 = 1'd0; -reg builder_self4 = 1'd0; -reg builder_self5 = 1'd0; -reg [2:0] builder_self6 = 3'd0; -reg [1:0] builder_self7 = 2'd0; -reg builder_shared_ack = 1'd0; -wire [29:0] builder_shared_adr; -wire [1:0] builder_shared_bte; -wire [2:0] builder_shared_cti; -wire builder_shared_cyc; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [31:0] builder_shared_dat_w; -wire builder_shared_err; -wire [3:0] builder_shared_sel; -wire builder_shared_stb; -wire builder_shared_we; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_state = 1'd0; -wire [31:0] builder_t_slice_proxy0; -wire [31:0] builder_t_slice_proxy1; -wire [31:0] builder_t_slice_proxy10; -wire [31:0] builder_t_slice_proxy11; -wire [31:0] builder_t_slice_proxy12; -wire [31:0] builder_t_slice_proxy13; -wire [31:0] builder_t_slice_proxy14; -wire [31:0] builder_t_slice_proxy15; -wire [31:0] builder_t_slice_proxy16; -wire [31:0] builder_t_slice_proxy17; -wire [31:0] builder_t_slice_proxy18; -wire [31:0] builder_t_slice_proxy19; -wire [31:0] builder_t_slice_proxy2; -wire [31:0] builder_t_slice_proxy20; -wire [31:0] builder_t_slice_proxy21; -wire [31:0] builder_t_slice_proxy22; -wire [31:0] builder_t_slice_proxy23; -wire [31:0] builder_t_slice_proxy24; -wire [31:0] builder_t_slice_proxy25; -wire [31:0] builder_t_slice_proxy26; -wire [31:0] builder_t_slice_proxy27; -wire [31:0] builder_t_slice_proxy28; -wire [31:0] builder_t_slice_proxy29; -wire [31:0] builder_t_slice_proxy3; -wire [31:0] builder_t_slice_proxy30; -wire [31:0] builder_t_slice_proxy31; -wire [31:0] builder_t_slice_proxy32; -wire [31:0] builder_t_slice_proxy33; -wire [31:0] builder_t_slice_proxy34; -wire [31:0] builder_t_slice_proxy35; -wire [31:0] builder_t_slice_proxy36; -wire [31:0] builder_t_slice_proxy37; -wire [31:0] builder_t_slice_proxy38; -wire [31:0] builder_t_slice_proxy39; -wire [31:0] builder_t_slice_proxy4; -wire [31:0] builder_t_slice_proxy40; -wire [31:0] builder_t_slice_proxy41; -wire [31:0] builder_t_slice_proxy42; -wire [31:0] builder_t_slice_proxy43; -wire [31:0] builder_t_slice_proxy44; -wire [31:0] builder_t_slice_proxy45; -wire [31:0] builder_t_slice_proxy46; -wire [31:0] builder_t_slice_proxy47; -wire [31:0] builder_t_slice_proxy48; -wire [31:0] builder_t_slice_proxy49; -wire [31:0] builder_t_slice_proxy5; -wire [31:0] builder_t_slice_proxy50; -wire [31:0] builder_t_slice_proxy51; -wire [31:0] builder_t_slice_proxy52; -wire [31:0] builder_t_slice_proxy53; -wire [31:0] builder_t_slice_proxy54; -wire [31:0] builder_t_slice_proxy55; -wire [31:0] builder_t_slice_proxy56; -wire [31:0] builder_t_slice_proxy57; -wire [31:0] builder_t_slice_proxy58; -wire [31:0] builder_t_slice_proxy59; -wire [31:0] builder_t_slice_proxy6; -wire [31:0] builder_t_slice_proxy60; -wire [31:0] builder_t_slice_proxy61; -wire [31:0] builder_t_slice_proxy62; -wire [31:0] builder_t_slice_proxy63; -wire [31:0] builder_t_slice_proxy7; -wire [31:0] builder_t_slice_proxy8; -wire [31:0] builder_t_slice_proxy9; -reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; -reg builder_txdatapath_liteethmacgap_next_state = 1'd0; -reg builder_txdatapath_liteethmacgap_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; -reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; -reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; -wire builder_wait; -wire builder_we; -(* syn_keep = "true" *) -wire eth_rx_clk; -wire eth_rx_rst; -(* syn_keep = "true" *) -wire eth_tx_clk; -wire eth_tx_rst; -wire main_bufferizeendpoints_pipe_valid_sink_first; -wire main_bufferizeendpoints_pipe_valid_sink_last; -wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; -wire main_bufferizeendpoints_pipe_valid_sink_payload_error; -wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; -wire main_bufferizeendpoints_pipe_valid_sink_ready; -wire main_bufferizeendpoints_pipe_valid_sink_valid; -reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; -reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; -wire main_bufferizeendpoints_pipe_valid_source_ready; -reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; -wire main_bufferizeendpoints_sink_sink_first; -wire main_bufferizeendpoints_sink_sink_last; -wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; -wire main_bufferizeendpoints_sink_sink_payload_error; -wire main_bufferizeendpoints_sink_sink_payload_last_be; -wire main_bufferizeendpoints_sink_sink_ready; -wire main_bufferizeendpoints_sink_sink_valid; -wire main_bufferizeendpoints_source_source_first; -wire main_bufferizeendpoints_source_source_last; -wire [7:0] main_bufferizeendpoints_source_source_payload_data; -wire main_bufferizeendpoints_source_source_payload_error; -wire main_bufferizeendpoints_source_source_payload_last_be; -wire main_bufferizeendpoints_source_source_ready; -wire main_bufferizeendpoints_source_source_valid; -wire main_bus_ack; -wire [29:0] main_bus_adr; -wire [1:0] main_bus_bte; -wire [2:0] main_bus_cti; -wire main_bus_cyc; -wire [31:0] main_bus_dat_r; -wire [31:0] main_bus_dat_w; -wire main_bus_err; -wire [3:0] main_bus_sel; -wire main_bus_stb; -wire main_bus_we; -reg main_crc_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_interface0_ack = 1'd0; -wire [29:0] main_interface0_adr; -wire [1:0] main_interface0_bte; -wire [2:0] main_interface0_cti; -wire main_interface0_cyc; -wire [31:0] main_interface0_dat_r; -wire [31:0] main_interface0_dat_w; -reg main_interface0_err = 1'd0; -wire [3:0] main_interface0_sel; -wire main_interface0_stb; -wire main_interface0_we; -reg main_interface1_ack = 1'd0; -wire [29:0] main_interface1_adr; -wire [1:0] main_interface1_bte; -wire [2:0] main_interface1_cti; -wire main_interface1_cyc; -wire [31:0] main_interface1_dat_r; -wire [31:0] main_interface1_dat_w; -reg main_interface1_err = 1'd0; -wire [3:0] main_interface1_sel; -wire main_interface1_stb; -wire main_interface1_we; -reg main_interface2_ack = 1'd0; -wire [29:0] main_interface2_adr; -wire [1:0] main_interface2_bte; -wire [2:0] main_interface2_cti; -wire main_interface2_cyc; -wire [31:0] main_interface2_dat_r; -wire [31:0] main_interface2_dat_w; -reg main_interface2_err = 1'd0; -wire [3:0] main_interface2_sel; -wire main_interface2_stb; -wire main_interface2_we; -reg main_interface3_ack = 1'd0; -wire [29:0] main_interface3_adr; -wire [1:0] main_interface3_bte; -wire [2:0] main_interface3_cti; -wire main_interface3_cyc; -wire [31:0] main_interface3_dat_r; -wire [31:0] main_interface3_dat_w; -reg main_interface3_err = 1'd0; -wire [3:0] main_interface3_sel; -wire main_interface3_stb; -wire main_interface3_we; -reg [3:0] main_length_inc = 4'd0; -wire main_liteethmaccrc32checker_crc_be; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; -wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -reg main_liteethmaccrc32checker_crc_error0 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; -reg main_liteethmaccrc32checker_error = 1'd0; -wire main_liteethmaccrc32checker_fifo_full; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -reg main_liteethmaccrc32checker_last_be = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -wire main_liteethmaccrc32checker_source_source_first; -reg main_liteethmaccrc32checker_source_source_last = 1'd0; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_valid = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -reg main_maccore_ethphy__r_re = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__w_re = 1'd0; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -reg main_maccore_ethphy_clock_speed = 1'd0; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_maccore_ethphy_data_w; -reg main_maccore_ethphy_duplex_status = 1'd0; -wire main_maccore_ethphy_eth_tx_clk_o; -wire main_maccore_ethphy_last; -reg main_maccore_ethphy_link_status = 1'd0; -wire main_maccore_ethphy_mdc; -wire main_maccore_ethphy_oe; -reg main_maccore_ethphy_r = 1'd0; -reg main_maccore_ethphy_re = 1'd0; -wire main_maccore_ethphy_reset; -reg main_maccore_ethphy_reset_re = 1'd0; -reg main_maccore_ethphy_reset_storage = 1'd0; -wire [1:0] main_maccore_ethphy_rx_ctl; -wire main_maccore_ethphy_rx_ctl_delayf; -reg [1:0] main_maccore_ethphy_rx_ctl_reg = 2'd0; -reg [1:0] main_maccore_ethphy_rx_ctl_reg_d = 2'd0; -wire [7:0] main_maccore_ethphy_rx_data; -wire [3:0] main_maccore_ethphy_rx_data_delayf; -reg [7:0] main_maccore_ethphy_rx_data_reg = 8'd0; -wire main_maccore_ethphy_sink_first; -wire main_maccore_ethphy_sink_last; -wire [7:0] main_maccore_ethphy_sink_payload_data; -wire main_maccore_ethphy_sink_payload_error; -wire main_maccore_ethphy_sink_payload_last_be; -wire main_maccore_ethphy_sink_ready; -wire main_maccore_ethphy_sink_valid; -reg main_maccore_ethphy_source_first = 1'd0; -wire main_maccore_ethphy_source_last; -reg [7:0] main_maccore_ethphy_source_payload_data = 8'd0; -reg main_maccore_ethphy_source_payload_error = 1'd0; -reg main_maccore_ethphy_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_source_ready; -reg main_maccore_ethphy_source_valid = 1'd0; -reg [2:0] main_maccore_ethphy_status = 3'd0; -wire main_maccore_ethphy_tx_ctl_oddrx1f; -wire [3:0] main_maccore_ethphy_tx_data_oddrx1f; -wire main_maccore_ethphy_w; -wire main_maccore_ethphy_we; -reg main_maccore_int_rst = 1'd1; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -wire main_maccore_maccore_cpu_rst; -reg main_maccore_maccore_reset_re = 1'd0; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_scratch_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_soc_rst = 1'd0; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -wire main_pulsesynchronizer0_i; -wire main_pulsesynchronizer0_o; -reg main_pulsesynchronizer0_toggle_i = 1'd0; -wire main_pulsesynchronizer0_toggle_o; -reg main_pulsesynchronizer0_toggle_o_r = 1'd0; -wire main_pulsesynchronizer1_i; -wire main_pulsesynchronizer1_o; -reg main_pulsesynchronizer1_toggle_i = 1'd0; -wire main_pulsesynchronizer1_toggle_o; -reg main_pulsesynchronizer1_toggle_o_r = 1'd0; -reg [31:0] main_rd_data = 32'd0; -reg main_re = 1'd0; -reg main_read = 1'd0; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire main_rx_cdc_cdc_graycounter0_ce; +reg multiregimpl41 = 1'd0; (* syn_no_retiming = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; +reg [5:0] multiregimpl50 = 6'd0; (* syn_no_retiming = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_valid; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire main_rx_cdc_cdc_wrport_we; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_valid; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_valid; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -wire main_rx_converter_converter_source_ready; -wire main_rx_converter_converter_source_valid; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_valid; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_valid; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -wire main_rx_last_be_source_payload_error; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_valid; -wire main_rx_padding_sink_first; -wire main_rx_padding_sink_last; -wire [7:0] main_rx_padding_sink_payload_data; -wire main_rx_padding_sink_payload_error; -wire main_rx_padding_sink_payload_last_be; -wire main_rx_padding_sink_ready; -wire main_rx_padding_sink_valid; -wire main_rx_padding_source_first; -wire main_rx_padding_source_last; -wire [7:0] main_rx_padding_source_payload_data; -wire main_rx_padding_source_payload_error; -wire main_rx_padding_source_payload_last_be; -wire main_rx_padding_source_ready; -wire main_rx_padding_source_valid; -reg main_rx_preamble_error = 1'd0; -reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; -wire main_rx_preamble_sink_first; -wire main_rx_preamble_sink_last; -wire [7:0] main_rx_preamble_sink_payload_data; -wire main_rx_preamble_sink_payload_error; -wire main_rx_preamble_sink_payload_last_be; -reg main_rx_preamble_sink_ready = 1'd0; -wire main_rx_preamble_sink_valid; -reg main_rx_preamble_source_first = 1'd0; -reg main_rx_preamble_source_last = 1'd0; -wire [7:0] main_rx_preamble_source_payload_data; -reg main_rx_preamble_source_payload_error = 1'd0; -wire main_rx_preamble_source_payload_last_be; -wire main_rx_preamble_source_ready; -reg main_rx_preamble_source_valid = 1'd0; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_error; -wire [3:0] main_sink_payload_last_be; -wire main_sink_ready; -wire main_sink_sink_first; -wire main_sink_sink_last; -wire [31:0] main_sink_sink_payload_data; -wire [3:0] main_sink_sink_payload_error; -wire [3:0] main_sink_sink_payload_last_be; -wire main_sink_sink_ready; -wire main_sink_sink_valid; -wire main_sink_valid; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -reg main_slot = 1'd0; -reg main_slot_liteethmacsramwriter_next_value = 1'd0; -reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_error; -wire [3:0] main_source_payload_last_be; -wire main_source_ready; -wire main_source_source_first; -wire main_source_source_last; -wire [31:0] main_source_source_payload_data; -wire [3:0] main_source_source_payload_error; -wire [3:0] main_source_source_payload_last_be; -wire main_source_source_ready; -wire main_source_source_valid; -wire main_source_valid; -wire [8:0] main_sram0_adr; -reg main_sram0_adr_burst = 1'd0; -wire [31:0] main_sram0_dat_r; -wire main_sram0_sink_valid; -reg main_sram100_storage = 1'd0; -reg main_sram101_re = 1'd0; -reg [10:0] main_sram102_storage = 11'd0; -reg main_sram103_re = 1'd0; -wire main_sram104_irq; -wire main_sram105_status; -reg main_sram106_pending = 1'd0; -reg main_sram107_trigger = 1'd0; -reg main_sram108_clear = 1'd0; -wire main_sram109_event0; -wire [10:0] main_sram10_status; -reg main_sram110_status = 1'd0; -wire main_sram111_we; -reg main_sram112_re = 1'd0; -wire main_sram113_event0; -reg main_sram114_status = 1'd0; -wire main_sram115_we; -reg main_sram116_re = 1'd0; -reg main_sram117_r = 1'd0; -wire main_sram118_event0; -reg main_sram119_storage = 1'd0; -wire main_sram11_we; -reg main_sram120_re = 1'd0; -reg [10:0] main_sram122_length = 11'd0; -reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; -reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; -wire main_sram123_sink_valid; -wire main_sram124_sink_ready; -reg main_sram125_sink_first = 1'd0; -reg main_sram126_sink_last = 1'd0; -wire main_sram127_sink_payload_slot; -wire [10:0] main_sram128_sink_payload_length; -wire main_sram129_source_valid; -reg main_sram12_re = 1'd0; -reg main_sram130_source_ready = 1'd0; -wire main_sram131_source_first; -wire main_sram132_source_last; -wire main_sram133_source_payload_slot; -wire [10:0] main_sram134_source_payload_length; -wire main_sram135_we; -wire main_sram136_writable; -wire main_sram137_re; -wire main_sram138_readable; -wire [13:0] main_sram139_din; -reg [31:0] main_sram13_status = 32'd0; -reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; -reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; -wire [13:0] main_sram140_dout; -reg [1:0] main_sram141_level = 2'd0; -reg main_sram142_replace = 1'd0; -reg main_sram143_produce = 1'd0; -reg main_sram144_consume = 1'd0; -reg main_sram145_adr = 1'd0; -wire [13:0] main_sram146_dat_r; -wire main_sram147_we; -wire [13:0] main_sram148_dat_w; -wire main_sram149_do_read; -wire main_sram14_we; -wire main_sram150_adr; -wire [13:0] main_sram151_dat_r; -wire main_sram152_fifo_in_payload_slot; -wire [10:0] main_sram153_fifo_in_payload_length; -wire main_sram154_fifo_in_first; -wire main_sram155_fifo_in_last; -wire main_sram156_fifo_out_payload_slot; -wire [10:0] main_sram157_fifo_out_payload_length; -wire main_sram158_fifo_out_first; -wire main_sram159_fifo_out_last; -reg main_sram15_re = 1'd0; -wire [8:0] main_sram161_adr; -wire [31:0] main_sram162_dat_r; -wire main_sram163_re; -wire [8:0] main_sram164_adr; -wire [31:0] main_sram165_dat_r; -wire main_sram166_re; -wire main_sram167_irq; -wire main_sram16_irq; -wire main_sram17_status; -wire main_sram18_pending; -wire main_sram19_trigger; -wire [8:0] main_sram1_adr; -reg main_sram1_adr_burst = 1'd0; -wire [31:0] main_sram1_dat_r; -reg main_sram1_sink_ready = 1'd1; -reg main_sram20_clear = 1'd0; -wire main_sram21_available; -reg main_sram22_status = 1'd0; -wire main_sram23_we; -reg main_sram24_re = 1'd0; -wire main_sram25_available; -reg main_sram26_status = 1'd0; -wire main_sram27_we; -reg main_sram28_re = 1'd0; -reg main_sram29_r = 1'd0; -wire [8:0] main_sram2_adr; -reg main_sram2_adr_burst = 1'd0; -wire [31:0] main_sram2_dat_r; -wire [31:0] main_sram2_dat_w; -wire main_sram2_sink_first; -reg [3:0] main_sram2_we = 4'd0; -wire main_sram30_available; -reg main_sram31_storage = 1'd0; -reg main_sram32_re = 1'd0; -reg [10:0] main_sram35_length = 11'd0; -reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; -reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; -reg main_sram37_sink_valid = 1'd0; -wire main_sram38_sink_ready; -reg main_sram39_sink_first = 1'd0; -wire [8:0] main_sram3_adr; -reg main_sram3_adr_burst = 1'd0; -wire [31:0] main_sram3_dat_r; -wire [31:0] main_sram3_dat_w; -wire main_sram3_sink_last; -reg [3:0] main_sram3_we = 4'd0; -reg main_sram40_sink_last = 1'd0; -reg main_sram41_sink_payload_slot = 1'd0; -reg [10:0] main_sram42_sink_payload_length = 11'd0; -wire main_sram43_source_valid; -wire main_sram44_source_ready; -wire main_sram45_source_first; -wire main_sram46_source_last; -wire main_sram47_source_payload_slot; -wire [10:0] main_sram48_source_payload_length; -wire main_sram49_we; -wire [31:0] main_sram4_sink_payload_data; -wire main_sram50_writable; -wire main_sram51_re; -wire main_sram52_readable; -wire [13:0] main_sram53_din; -wire [13:0] main_sram54_dout; -reg [1:0] main_sram55_level = 2'd0; -reg main_sram56_replace = 1'd0; -reg main_sram57_produce = 1'd0; -reg main_sram58_consume = 1'd0; -reg main_sram59_adr = 1'd0; -wire [3:0] main_sram5_sink_payload_last_be; -wire [13:0] main_sram60_dat_r; -wire main_sram61_we; -wire [13:0] main_sram62_dat_w; -wire main_sram63_do_read; -wire main_sram64_adr; -wire [13:0] main_sram65_dat_r; -wire main_sram66_fifo_in_payload_slot; -wire [10:0] main_sram67_fifo_in_payload_length; -wire main_sram68_fifo_in_first; -wire main_sram69_fifo_in_last; -wire [3:0] main_sram6_sink_payload_error; -wire main_sram70_fifo_out_payload_slot; -wire [10:0] main_sram71_fifo_out_payload_length; -wire main_sram72_fifo_out_first; -wire main_sram73_fifo_out_last; -reg [8:0] main_sram75_adr = 9'd0; -wire [31:0] main_sram76_dat_r; -reg main_sram77_we = 1'd0; -reg [31:0] main_sram78_dat_w = 32'd0; -reg [8:0] main_sram79_adr = 9'd0; -wire main_sram7_status; -wire [31:0] main_sram80_dat_r; -reg main_sram81_we = 1'd0; -reg [31:0] main_sram82_dat_w = 32'd0; -reg main_sram83_source_valid = 1'd0; -wire main_sram84_source_ready; -reg main_sram85_source_first = 1'd0; -reg main_sram86_source_last = 1'd0; -wire [31:0] main_sram87_source_payload_data; -reg [3:0] main_sram88_source_payload_last_be = 4'd0; -reg [3:0] main_sram89_source_payload_error = 4'd0; -wire main_sram8_we; -wire main_sram94_status; -wire main_sram95_we; -reg main_sram96_re = 1'd0; -wire [1:0] main_sram97_status; -wire main_sram98_we; -reg main_sram99_re = 1'd0; -reg main_sram9_re = 1'd0; -wire main_start_r; -reg main_start_re = 1'd0; -reg main_start_w = 1'd0; -reg main_start_we = 1'd0; -reg main_status = 1'd1; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire main_tx_cdc_cdc_graycounter0_ce; +reg [5:0] multiregimpl51 = 6'd0; (* syn_no_retiming = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; +reg [5:0] multiregimpl60 = 6'd0; (* syn_no_retiming = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_valid; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire main_tx_cdc_cdc_wrport_we; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_valid; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_error; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_valid; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_valid; -wire main_tx_crc_be; -reg main_tx_crc_ce = 1'd0; -reg [1:0] main_tx_crc_cnt = 2'd3; -wire main_tx_crc_cnt_done; -reg [31:0] main_tx_crc_crc_next = 32'd0; -reg [31:0] main_tx_crc_crc_packet = 32'd0; -reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; -reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; -wire [31:0] main_tx_crc_crc_prev; -wire [7:0] main_tx_crc_data0; -wire [7:0] main_tx_crc_data1; -reg main_tx_crc_error = 1'd0; -reg main_tx_crc_is_ongoing0 = 1'd0; -reg main_tx_crc_is_ongoing1 = 1'd0; -reg main_tx_crc_last_be = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; -wire main_tx_crc_pipe_valid_sink_first; -wire main_tx_crc_pipe_valid_sink_last; -wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; -wire main_tx_crc_pipe_valid_sink_payload_error; -wire main_tx_crc_pipe_valid_sink_payload_last_be; -wire main_tx_crc_pipe_valid_sink_ready; -wire main_tx_crc_pipe_valid_sink_valid; -reg main_tx_crc_pipe_valid_source_first = 1'd0; -reg main_tx_crc_pipe_valid_source_last = 1'd0; -reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; -reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; -reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; -wire main_tx_crc_pipe_valid_source_ready; -reg main_tx_crc_pipe_valid_source_valid = 1'd0; -reg [31:0] main_tx_crc_reg = 32'd4294967295; -reg main_tx_crc_reset = 1'd0; -wire main_tx_crc_sink_first; -wire main_tx_crc_sink_last; -wire [7:0] main_tx_crc_sink_payload_data; -wire main_tx_crc_sink_payload_error; -wire main_tx_crc_sink_payload_last_be; -reg main_tx_crc_sink_ready = 1'd0; -wire main_tx_crc_sink_sink_first; -wire main_tx_crc_sink_sink_last; -wire [7:0] main_tx_crc_sink_sink_payload_data; -wire main_tx_crc_sink_sink_payload_error; -wire main_tx_crc_sink_sink_payload_last_be; -wire main_tx_crc_sink_sink_ready; -wire main_tx_crc_sink_sink_valid; -wire main_tx_crc_sink_valid; -reg main_tx_crc_source_first = 1'd0; -reg main_tx_crc_source_last = 1'd0; -reg [7:0] main_tx_crc_source_payload_data = 8'd0; -reg main_tx_crc_source_payload_error = 1'd0; -reg main_tx_crc_source_payload_last_be = 1'd0; -wire main_tx_crc_source_ready; -wire main_tx_crc_source_source_first; -wire main_tx_crc_source_source_last; -wire [7:0] main_tx_crc_source_source_payload_data; -wire main_tx_crc_source_source_payload_error; -wire main_tx_crc_source_source_payload_last_be; -wire main_tx_crc_source_source_ready; -wire main_tx_crc_source_source_valid; -reg main_tx_crc_source_valid = 1'd0; -reg [31:0] main_tx_crc_value = 32'd0; -reg [3:0] main_tx_gap_counter = 4'd0; -reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; -reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; -wire main_tx_gap_sink_first; -wire main_tx_gap_sink_last; -wire [7:0] main_tx_gap_sink_payload_data; -wire main_tx_gap_sink_payload_error; -wire main_tx_gap_sink_payload_last_be; -reg main_tx_gap_sink_ready = 1'd0; -wire main_tx_gap_sink_valid; -reg main_tx_gap_source_first = 1'd0; -reg main_tx_gap_source_last = 1'd0; -reg [7:0] main_tx_gap_source_payload_data = 8'd0; -reg main_tx_gap_source_payload_error = 1'd0; -reg main_tx_gap_source_payload_last_be = 1'd0; -wire main_tx_gap_source_ready; -reg main_tx_gap_source_valid = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_error; -wire main_tx_last_be_sink_payload_last_be; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_valid = 1'd0; -reg [15:0] main_tx_padding_counter = 16'd0; -reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; -reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; -wire main_tx_padding_counter_done; -wire main_tx_padding_sink_first; -wire main_tx_padding_sink_last; -wire [7:0] main_tx_padding_sink_payload_data; -wire main_tx_padding_sink_payload_error; -wire main_tx_padding_sink_payload_last_be; -reg main_tx_padding_sink_ready = 1'd0; -wire main_tx_padding_sink_valid; -reg main_tx_padding_source_first = 1'd0; -reg main_tx_padding_source_last = 1'd0; -reg [7:0] main_tx_padding_source_payload_data = 8'd0; -reg main_tx_padding_source_payload_error = 1'd0; -reg main_tx_padding_source_payload_last_be = 1'd0; -wire main_tx_padding_source_ready; -reg main_tx_padding_source_valid = 1'd0; -reg [2:0] main_tx_preamble_count = 3'd0; -reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; -reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; -reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; -wire main_tx_preamble_sink_first; -wire main_tx_preamble_sink_last; -wire [7:0] main_tx_preamble_sink_payload_data; -wire main_tx_preamble_sink_payload_error; -wire main_tx_preamble_sink_payload_last_be; -reg main_tx_preamble_sink_ready = 1'd0; -wire main_tx_preamble_sink_valid; -reg main_tx_preamble_source_first = 1'd0; -reg main_tx_preamble_source_last = 1'd0; -reg [7:0] main_tx_preamble_source_payload_data = 8'd0; -reg main_tx_preamble_source_payload_error = 1'd0; -wire main_tx_preamble_source_payload_last_be; -wire main_tx_preamble_source_ready; -reg main_tx_preamble_source_valid = 1'd0; -wire main_wb_bus_ack; -wire [29:0] main_wb_bus_adr; -wire [1:0] main_wb_bus_bte; -wire [2:0] main_wb_bus_cti; -wire main_wb_bus_cyc; -wire [31:0] main_wb_bus_dat_r; -wire [31:0] main_wb_bus_dat_w; -wire main_wb_bus_err; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_stb; -wire main_wb_bus_we; -wire main_we; -wire [31:0] main_wr_data; -reg main_write = 1'd0; +reg [5:0] multiregimpl61 = 6'd0; +reg next_state = 1'd0; wire por_clk; +wire re; +wire request; +wire rst10; +wire rst11; +reg [1:0] rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] rxdatapath_bufferizeendpoints_state = 2'd0; +reg rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] self0 = 30'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [29:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg [2:0] slave_sel = 3'd0; +reg [2:0] slave_sel_r = 3'd0; +reg state = 1'd0; (* syn_keep = "true" *) wire sys_clk; wire sys_rst; +reg [1:0] txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] txdatapath_bufferizeendpoints_state = 2'd0; +reg txdatapath_liteethmacgap_next_state = 1'd0; +reg txdatapath_liteethmacgap_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg txdatapath_liteethmactxlastbe_state = 1'd0; +wire wait_1; +wire wb_bus_ack; +wire [29:0] wb_bus_adr; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; +wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; +wire [3:0] wb_bus_sel; +wire wb_bus_stb; +wire wb_bus_we; +wire we; +wire wishbone_interface_bus_rx_ack; +wire [29:0] wishbone_interface_bus_rx_adr; +wire [1:0] wishbone_interface_bus_rx_bte; +wire [2:0] wishbone_interface_bus_rx_cti; +wire wishbone_interface_bus_rx_cyc; +wire [31:0] wishbone_interface_bus_rx_dat_r; +wire [31:0] wishbone_interface_bus_rx_dat_w; +wire wishbone_interface_bus_rx_err; +wire [3:0] wishbone_interface_bus_rx_sel; +wire wishbone_interface_bus_rx_stb; +wire wishbone_interface_bus_rx_we; +wire wishbone_interface_bus_tx_ack; +wire [29:0] wishbone_interface_bus_tx_adr; +wire [1:0] wishbone_interface_bus_tx_bte; +wire [2:0] wishbone_interface_bus_tx_cti; +wire wishbone_interface_bus_tx_cyc; +wire [31:0] wishbone_interface_bus_tx_dat_r; +wire [31:0] wishbone_interface_bus_tx_dat_w; +wire wishbone_interface_bus_tx_err; +wire [3:0] wishbone_interface_bus_tx_sel; +wire wishbone_interface_bus_tx_stb; +wire wishbone_interface_bus_tx_we; +reg [1:0] wishbone_interface_decoder0_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder0_slave_sel_r = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel_r = 2'd0; +wire wishbone_interface_ev_irq; +reg wishbone_interface_interface0_ack = 1'd0; +wire [29:0] wishbone_interface_interface0_adr; +wire [1:0] wishbone_interface_interface0_bte; +wire [2:0] wishbone_interface_interface0_cti; +wire wishbone_interface_interface0_cyc; +wire [31:0] wishbone_interface_interface0_dat_r; +wire [31:0] wishbone_interface_interface0_dat_w; +reg wishbone_interface_interface0_err = 1'd0; +wire [3:0] wishbone_interface_interface0_sel; +wire wishbone_interface_interface0_stb; +wire wishbone_interface_interface0_we; +reg wishbone_interface_interface1_ack = 1'd0; +wire [29:0] wishbone_interface_interface1_adr; +wire [1:0] wishbone_interface_interface1_bte; +wire [2:0] wishbone_interface_interface1_cti; +wire wishbone_interface_interface1_cyc; +wire [31:0] wishbone_interface_interface1_dat_r; +wire [31:0] wishbone_interface_interface1_dat_w; +reg wishbone_interface_interface1_err = 1'd0; +wire [3:0] wishbone_interface_interface1_sel; +wire wishbone_interface_interface1_stb; +wire wishbone_interface_interface1_we; +reg wishbone_interface_interface2_ack = 1'd0; +wire [29:0] wishbone_interface_interface2_adr; +wire [1:0] wishbone_interface_interface2_bte; +wire [2:0] wishbone_interface_interface2_cti; +wire wishbone_interface_interface2_cyc; +wire [31:0] wishbone_interface_interface2_dat_r; +wire [31:0] wishbone_interface_interface2_dat_w; +reg wishbone_interface_interface2_err = 1'd0; +wire [3:0] wishbone_interface_interface2_sel; +wire wishbone_interface_interface2_stb; +wire wishbone_interface_interface2_we; +reg wishbone_interface_interface3_ack = 1'd0; +wire [29:0] wishbone_interface_interface3_adr; +wire [1:0] wishbone_interface_interface3_bte; +wire [2:0] wishbone_interface_interface3_cti; +wire wishbone_interface_interface3_cyc; +wire [31:0] wishbone_interface_interface3_dat_r; +wire [31:0] wishbone_interface_interface3_dat_w; +reg wishbone_interface_interface3_err = 1'd0; +wire [3:0] wishbone_interface_interface3_sel; +wire wishbone_interface_interface3_stb; +wire wishbone_interface_interface3_we; +reg wishbone_interface_reader_cmd_fifo_consume = 1'd0; +wire wishbone_interface_reader_cmd_fifo_do_read; +wire wishbone_interface_reader_cmd_fifo_fifo_in_first; +wire wishbone_interface_reader_cmd_fifo_fifo_in_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_in_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot; +wire wishbone_interface_reader_cmd_fifo_fifo_out_first; +wire wishbone_interface_reader_cmd_fifo_fifo_out_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_reader_cmd_fifo_level = 2'd0; +reg wishbone_interface_reader_cmd_fifo_produce = 1'd0; +wire wishbone_interface_reader_cmd_fifo_rdport_adr; +wire [13:0] wishbone_interface_reader_cmd_fifo_rdport_dat_r; +reg wishbone_interface_reader_cmd_fifo_replace = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_first = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_last = 1'd0; +wire [10:0] wishbone_interface_reader_cmd_fifo_sink_payload_length; +wire wishbone_interface_reader_cmd_fifo_sink_payload_slot; +wire wishbone_interface_reader_cmd_fifo_sink_ready; +wire wishbone_interface_reader_cmd_fifo_sink_valid; +wire wishbone_interface_reader_cmd_fifo_source_first; +wire wishbone_interface_reader_cmd_fifo_source_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_source_payload_length; +wire wishbone_interface_reader_cmd_fifo_source_payload_slot; +reg wishbone_interface_reader_cmd_fifo_source_ready = 1'd0; +wire wishbone_interface_reader_cmd_fifo_source_valid; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_din; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_dout; +wire wishbone_interface_reader_cmd_fifo_syncfifo_re; +wire wishbone_interface_reader_cmd_fifo_syncfifo_readable; +wire wishbone_interface_reader_cmd_fifo_syncfifo_we; +wire wishbone_interface_reader_cmd_fifo_syncfifo_writable; +reg wishbone_interface_reader_cmd_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_w; +wire wishbone_interface_reader_cmd_fifo_wrport_we; +reg wishbone_interface_reader_enable_re = 1'd0; +reg wishbone_interface_reader_enable_storage = 1'd0; +wire wishbone_interface_reader_event00; +wire wishbone_interface_reader_event01; +wire wishbone_interface_reader_event02; +reg wishbone_interface_reader_eventsourcepulse_clear = 1'd0; +reg wishbone_interface_reader_eventsourcepulse_pending = 1'd0; +wire wishbone_interface_reader_eventsourcepulse_status; +reg wishbone_interface_reader_eventsourcepulse_trigger = 1'd0; +wire wishbone_interface_reader_irq; +reg [10:0] wishbone_interface_reader_length = 11'd0; +reg [10:0] wishbone_interface_reader_length_liteethmacsramreader_next_value = 11'd0; +reg wishbone_interface_reader_length_liteethmacsramreader_next_value_ce = 1'd0; +reg wishbone_interface_reader_length_re = 1'd0; +reg [10:0] wishbone_interface_reader_length_storage = 11'd0; +reg wishbone_interface_reader_level_re = 1'd0; +wire [1:0] wishbone_interface_reader_level_status; +wire wishbone_interface_reader_level_we; +wire [8:0] wishbone_interface_reader_memory0_adr; +wire [31:0] wishbone_interface_reader_memory0_dat_r; +wire wishbone_interface_reader_memory0_re; +wire [8:0] wishbone_interface_reader_memory1_adr; +wire [31:0] wishbone_interface_reader_memory1_dat_r; +wire wishbone_interface_reader_memory1_re; +reg wishbone_interface_reader_pending_r = 1'd0; +reg wishbone_interface_reader_pending_re = 1'd0; +wire wishbone_interface_reader_pending_status; +wire wishbone_interface_reader_pending_we; +reg [31:0] wishbone_interface_reader_rd_data = 32'd0; +reg wishbone_interface_reader_read = 1'd0; +reg wishbone_interface_reader_ready_re = 1'd0; +wire wishbone_interface_reader_ready_status; +wire wishbone_interface_reader_ready_we; +reg wishbone_interface_reader_slot_re = 1'd0; +reg wishbone_interface_reader_slot_storage = 1'd0; +reg wishbone_interface_reader_source_source_first = 1'd0; +reg wishbone_interface_reader_source_source_last = 1'd0; +wire [31:0] wishbone_interface_reader_source_source_payload_data; +reg [3:0] wishbone_interface_reader_source_source_payload_error = 4'd0; +reg [3:0] wishbone_interface_reader_source_source_payload_last_be = 4'd0; +wire wishbone_interface_reader_source_source_ready; +reg wishbone_interface_reader_source_source_valid = 1'd0; +wire wishbone_interface_reader_start_r; +reg wishbone_interface_reader_start_re = 1'd0; +reg wishbone_interface_reader_start_w = 1'd0; +reg wishbone_interface_reader_start_we = 1'd0; +reg wishbone_interface_reader_status_re = 1'd0; +wire wishbone_interface_reader_status_status; +wire wishbone_interface_reader_status_we; +wire wishbone_interface_sink_first; +wire wishbone_interface_sink_last; +wire [31:0] wishbone_interface_sink_payload_data; +wire [3:0] wishbone_interface_sink_payload_error; +wire [3:0] wishbone_interface_sink_payload_last_be; +wire wishbone_interface_sink_ready; +wire wishbone_interface_sink_valid; +wire wishbone_interface_source_first; +wire wishbone_interface_source_last; +wire [31:0] wishbone_interface_source_payload_data; +wire [3:0] wishbone_interface_source_payload_error; +wire [3:0] wishbone_interface_source_payload_last_be; +wire wishbone_interface_source_ready; +wire wishbone_interface_source_valid; +wire [8:0] wishbone_interface_sram0_adr; +reg wishbone_interface_sram0_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram0_dat_r; +wire [8:0] wishbone_interface_sram1_adr; +reg wishbone_interface_sram1_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram1_dat_r; +wire [8:0] wishbone_interface_sram2_adr; +reg wishbone_interface_sram2_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram2_dat_r; +wire [31:0] wishbone_interface_sram2_dat_w; +reg [3:0] wishbone_interface_sram2_we = 4'd0; +wire [8:0] wishbone_interface_sram3_adr; +reg wishbone_interface_sram3_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram3_dat_r; +wire [31:0] wishbone_interface_sram3_dat_w; +reg [3:0] wishbone_interface_sram3_we = 4'd0; +wire wishbone_interface_writer_available0; +wire wishbone_interface_writer_available1; +wire wishbone_interface_writer_available2; +reg wishbone_interface_writer_available_clear = 1'd0; +wire wishbone_interface_writer_available_pending; +wire wishbone_interface_writer_available_status; +wire wishbone_interface_writer_available_trigger; +reg wishbone_interface_writer_enable_re = 1'd0; +reg wishbone_interface_writer_enable_storage = 1'd0; +reg wishbone_interface_writer_errors_re = 1'd0; +reg [31:0] wishbone_interface_writer_errors_status = 32'd0; +reg [31:0] wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value = 32'd0; +reg wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire wishbone_interface_writer_errors_we; +wire wishbone_interface_writer_irq; +reg [10:0] wishbone_interface_writer_length = 11'd0; +reg [3:0] wishbone_interface_writer_length_inc = 4'd0; +reg [10:0] wishbone_interface_writer_length_liteethmacsramwriter_t_next_value = 11'd0; +reg wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg wishbone_interface_writer_length_re = 1'd0; +wire [10:0] wishbone_interface_writer_length_status; +wire wishbone_interface_writer_length_we; +reg [8:0] wishbone_interface_writer_memory0_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory0_dat_r; +reg [31:0] wishbone_interface_writer_memory0_dat_w = 32'd0; +reg wishbone_interface_writer_memory0_we = 1'd0; +reg [8:0] wishbone_interface_writer_memory1_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory1_dat_r; +reg [31:0] wishbone_interface_writer_memory1_dat_w = 32'd0; +reg wishbone_interface_writer_memory1_we = 1'd0; +reg wishbone_interface_writer_pending_r = 1'd0; +reg wishbone_interface_writer_pending_re = 1'd0; +wire wishbone_interface_writer_pending_status; +wire wishbone_interface_writer_pending_we; +wire wishbone_interface_writer_sink_sink_first; +wire wishbone_interface_writer_sink_sink_last; +wire [31:0] wishbone_interface_writer_sink_sink_payload_data; +wire [3:0] wishbone_interface_writer_sink_sink_payload_error; +wire [3:0] wishbone_interface_writer_sink_sink_payload_last_be; +reg wishbone_interface_writer_sink_sink_ready = 1'd1; +wire wishbone_interface_writer_sink_sink_valid; +reg wishbone_interface_writer_slot = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce = 1'd0; +reg wishbone_interface_writer_slot_re = 1'd0; +wire wishbone_interface_writer_slot_status; +wire wishbone_interface_writer_slot_we; +reg wishbone_interface_writer_stat_fifo_consume = 1'd0; +wire wishbone_interface_writer_stat_fifo_do_read; +wire wishbone_interface_writer_stat_fifo_fifo_in_first; +wire wishbone_interface_writer_stat_fifo_fifo_in_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_in_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_in_payload_slot; +wire wishbone_interface_writer_stat_fifo_fifo_out_first; +wire wishbone_interface_writer_stat_fifo_fifo_out_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_writer_stat_fifo_level = 2'd0; +reg wishbone_interface_writer_stat_fifo_produce = 1'd0; +wire wishbone_interface_writer_stat_fifo_rdport_adr; +wire [13:0] wishbone_interface_writer_stat_fifo_rdport_dat_r; +reg wishbone_interface_writer_stat_fifo_replace = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_first = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_last = 1'd0; +reg [10:0] wishbone_interface_writer_stat_fifo_sink_payload_length = 11'd0; +reg wishbone_interface_writer_stat_fifo_sink_payload_slot = 1'd0; +wire wishbone_interface_writer_stat_fifo_sink_ready; +reg wishbone_interface_writer_stat_fifo_sink_valid = 1'd0; +wire wishbone_interface_writer_stat_fifo_source_first; +wire wishbone_interface_writer_stat_fifo_source_last; +wire [10:0] wishbone_interface_writer_stat_fifo_source_payload_length; +wire wishbone_interface_writer_stat_fifo_source_payload_slot; +wire wishbone_interface_writer_stat_fifo_source_ready; +wire wishbone_interface_writer_stat_fifo_source_valid; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_din; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_dout; +wire wishbone_interface_writer_stat_fifo_syncfifo_re; +wire wishbone_interface_writer_stat_fifo_syncfifo_readable; +wire wishbone_interface_writer_stat_fifo_syncfifo_we; +wire wishbone_interface_writer_stat_fifo_syncfifo_writable; +reg wishbone_interface_writer_stat_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_w; +wire wishbone_interface_writer_stat_fifo_wrport_we; +reg wishbone_interface_writer_status_re = 1'd0; +wire wishbone_interface_writer_status_status; +wire wishbone_interface_writer_status_we; +wire [31:0] wishbone_interface_writer_wr_data; +reg wishbone_interface_writer_write = 1'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign main_wb_bus_adr = wishbone_adr; -assign main_wb_bus_dat_w = wishbone_dat_w; -assign wishbone_dat_r = main_wb_bus_dat_r; -assign main_wb_bus_sel = wishbone_sel; -assign main_wb_bus_cyc = wishbone_cyc; -assign main_wb_bus_stb = wishbone_stb; -assign wishbone_ack = main_wb_bus_ack; -assign main_wb_bus_we = wishbone_we; -assign main_wb_bus_cti = wishbone_cti; -assign main_wb_bus_bte = wishbone_bte; -assign wishbone_err = main_wb_bus_err; -assign interrupt = main_sram167_irq; -assign main_maccore_maccore_bus_error = builder_error; -assign builder_shared_adr = builder_self0; -assign builder_shared_dat_w = builder_self1; -assign builder_shared_sel = builder_self2; -assign builder_shared_cyc = builder_self3; -assign builder_shared_stb = builder_self4; -assign builder_shared_we = builder_self5; -assign builder_shared_cti = builder_self6; -assign builder_shared_bte = builder_self7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; +assign wb_bus_adr = wishbone_adr; +assign wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wishbone_sel; +assign wb_bus_cyc = wishbone_cyc; +assign wb_bus_stb = wishbone_stb; +assign wishbone_ack = wb_bus_ack; +assign wb_bus_we = wishbone_we; +assign wb_bus_cti = wishbone_cti; +assign wb_bus_bte = wishbone_bte; +assign wishbone_err = wb_bus_err; +assign interrupt = wishbone_interface_ev_irq; +assign maccore_maccore_bus_error = error; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign wb_bus_dat_r = shared_dat_r; +assign wb_bus_ack = (shared_ack & (grant == 1'd0)); +assign wb_bus_err = (shared_err & (grant == 1'd0)); +assign request = {wb_bus_cyc}; +assign grant = 1'd0; always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); + slave_sel <= 3'd0; + slave_sel[0] <= (shared_adr[29:10] == 5'd16); + slave_sel[1] <= (shared_adr[29:10] == 5'd17); + slave_sel[2] <= (shared_adr[29:14] == 1'd0); end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_interface0_adr = builder_shared_adr; -assign builder_interface0_dat_w = builder_shared_dat_w; -assign builder_interface0_sel = builder_shared_sel; -assign builder_interface0_stb = builder_shared_stb; -assign builder_interface0_we = builder_shared_we; -assign builder_interface0_cti = builder_shared_cti; -assign builder_interface0_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_interface0_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +assign wishbone_interface_bus_rx_adr = shared_adr; +assign wishbone_interface_bus_rx_dat_w = shared_dat_w; +assign wishbone_interface_bus_rx_sel = shared_sel; +assign wishbone_interface_bus_rx_stb = shared_stb; +assign wishbone_interface_bus_rx_we = shared_we; +assign wishbone_interface_bus_rx_cti = shared_cti; +assign wishbone_interface_bus_rx_bte = shared_bte; +assign wishbone_interface_bus_tx_adr = shared_adr; +assign wishbone_interface_bus_tx_dat_w = shared_dat_w; +assign wishbone_interface_bus_tx_sel = shared_sel; +assign wishbone_interface_bus_tx_stb = shared_stb; +assign wishbone_interface_bus_tx_we = shared_we; +assign wishbone_interface_bus_tx_cti = shared_cti; +assign wishbone_interface_bus_tx_bte = shared_bte; +assign interface0_adr = shared_adr; +assign interface0_dat_w = shared_dat_w; +assign interface0_sel = shared_sel; +assign interface0_stb = shared_stb; +assign interface0_we = shared_we; +assign interface0_cti = shared_cti; +assign interface0_bte = shared_bte; +assign wishbone_interface_bus_rx_cyc = (shared_cyc & slave_sel[0]); +assign wishbone_interface_bus_tx_cyc = (shared_cyc & slave_sel[1]); +assign interface0_cyc = (shared_cyc & slave_sel[2]); +assign shared_err = ((wishbone_interface_bus_rx_err | wishbone_interface_bus_tx_err) | interface0_err); +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); always @(*) begin - builder_error <= 1'd0; - builder_shared_ack <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_interface0_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= ((wishbone_interface_bus_rx_ack | wishbone_interface_bus_tx_ack) | interface0_ack); + shared_dat_r <= ((({32{slave_sel_r[0]}} & wishbone_interface_bus_rx_dat_r) | ({32{slave_sel_r[1]}} & wishbone_interface_bus_tx_dat_r)) | ({32{slave_sel_r[2]}} & interface0_dat_r)); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; end end -assign builder_done = (builder_count == 1'd0); -assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign done = (count == 1'd0); +assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; -assign sys_rst = main_maccore_int_rst; +assign sys_rst = maccore_int_rst; assign eth_rx_clk = rgmii_clocks_rx; assign eth_tx_clk = eth_rx_clk; -assign main_maccore_ethphy_reset = main_maccore_ethphy_reset_storage; -assign rgmii_rst_n = (~main_maccore_ethphy_reset); -assign main_maccore_ethphy_sink_ready = 1'd1; -assign main_maccore_ethphy_last = ((~main_maccore_ethphy_rx_ctl_reg[0]) & main_maccore_ethphy_rx_ctl_reg_d[0]); -assign main_maccore_ethphy_source_last = main_maccore_ethphy_last; -assign rgmii_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_sink_valid = main_source_source_valid; -assign main_source_source_ready = main_sink_ready; -assign main_sink_first = main_source_source_first; -assign main_sink_last = main_source_source_last; -assign main_sink_payload_data = main_source_source_payload_data; -assign main_sink_payload_last_be = main_source_source_payload_last_be; -assign main_sink_payload_error = main_source_source_payload_error; -assign main_sink_sink_valid = main_source_valid; -assign main_source_ready = main_sink_sink_ready; -assign main_sink_sink_first = main_source_first; -assign main_sink_sink_last = main_source_last; -assign main_sink_sink_payload_data = main_source_payload_data; -assign main_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_sink_sink_payload_error = main_source_payload_error; -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +assign maccore_ethphy_reset = maccore_ethphy_reset_storage; +assign rgmii_rst_n = (~maccore_ethphy_reset); +assign maccore_ethphy_sink_ready = 1'd1; +assign maccore_ethphy_last = ((~maccore_ethphy_rx_ctl_reg[0]) & maccore_ethphy_rx_ctl_reg_d[0]); +assign maccore_ethphy_source_last = maccore_ethphy_last; +assign rgmii_mdc = maccore_ethphy__w_storage[0]; +assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1]; +assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2]; +assign core_sink_valid = wishbone_interface_source_valid; +assign wishbone_interface_source_ready = core_sink_ready; +assign core_sink_first = wishbone_interface_source_first; +assign core_sink_last = wishbone_interface_source_last; +assign core_sink_payload_data = wishbone_interface_source_payload_data; +assign core_sink_payload_last_be = wishbone_interface_source_payload_last_be; +assign core_sink_payload_error = wishbone_interface_source_payload_error; +assign wishbone_interface_sink_valid = core_source_valid; +assign core_source_ready = wishbone_interface_sink_ready; +assign wishbone_interface_sink_first = core_source_first; +assign wishbone_interface_sink_last = core_source_last; +assign wishbone_interface_sink_payload_data = core_source_payload_data; +assign wishbone_interface_sink_payload_last_be = core_source_payload_last_be; +assign wishbone_interface_sink_payload_error = core_source_payload_error; +assign core_tx_cdc_cdc_sink_valid = core_tx_cdc_sink_sink_valid; +assign core_tx_cdc_sink_sink_ready = core_tx_cdc_cdc_sink_ready; +assign core_tx_cdc_cdc_sink_first = core_tx_cdc_sink_sink_first; +assign core_tx_cdc_cdc_sink_last = core_tx_cdc_sink_sink_last; +assign core_tx_cdc_cdc_sink_payload_data = core_tx_cdc_sink_sink_payload_data; +assign core_tx_cdc_cdc_sink_payload_last_be = core_tx_cdc_sink_sink_payload_last_be; +assign core_tx_cdc_cdc_sink_payload_error = core_tx_cdc_sink_sink_payload_error; +assign core_tx_cdc_source_source_valid = core_tx_cdc_cdc_source_valid; +assign core_tx_cdc_cdc_source_ready = core_tx_cdc_source_source_ready; +assign core_tx_cdc_source_source_first = core_tx_cdc_cdc_source_first; +assign core_tx_cdc_source_source_last = core_tx_cdc_cdc_source_last; +assign core_tx_cdc_source_source_payload_data = core_tx_cdc_cdc_source_payload_data; +assign core_tx_cdc_source_source_payload_last_be = core_tx_cdc_cdc_source_payload_last_be; +assign core_tx_cdc_source_source_payload_error = core_tx_cdc_cdc_source_payload_error; +assign core_tx_cdc_cdc_asyncfifo_din = {core_tx_cdc_cdc_fifo_in_last, core_tx_cdc_cdc_fifo_in_first, core_tx_cdc_cdc_fifo_in_payload_error, core_tx_cdc_cdc_fifo_in_payload_last_be, core_tx_cdc_cdc_fifo_in_payload_data}; +assign {core_tx_cdc_cdc_fifo_out_last, core_tx_cdc_cdc_fifo_out_first, core_tx_cdc_cdc_fifo_out_payload_error, core_tx_cdc_cdc_fifo_out_payload_last_be, core_tx_cdc_cdc_fifo_out_payload_data} = core_tx_cdc_cdc_asyncfifo_dout; +assign core_tx_cdc_cdc_sink_ready = core_tx_cdc_cdc_asyncfifo_writable; +assign core_tx_cdc_cdc_asyncfifo_we = core_tx_cdc_cdc_sink_valid; +assign core_tx_cdc_cdc_fifo_in_first = core_tx_cdc_cdc_sink_first; +assign core_tx_cdc_cdc_fifo_in_last = core_tx_cdc_cdc_sink_last; +assign core_tx_cdc_cdc_fifo_in_payload_data = core_tx_cdc_cdc_sink_payload_data; +assign core_tx_cdc_cdc_fifo_in_payload_last_be = core_tx_cdc_cdc_sink_payload_last_be; +assign core_tx_cdc_cdc_fifo_in_payload_error = core_tx_cdc_cdc_sink_payload_error; +assign core_tx_cdc_cdc_source_valid = core_tx_cdc_cdc_asyncfifo_readable; +assign core_tx_cdc_cdc_source_first = core_tx_cdc_cdc_fifo_out_first; +assign core_tx_cdc_cdc_source_last = core_tx_cdc_cdc_fifo_out_last; +assign core_tx_cdc_cdc_source_payload_data = core_tx_cdc_cdc_fifo_out_payload_data; +assign core_tx_cdc_cdc_source_payload_last_be = core_tx_cdc_cdc_fifo_out_payload_last_be; +assign core_tx_cdc_cdc_source_payload_error = core_tx_cdc_cdc_fifo_out_payload_error; +assign core_tx_cdc_cdc_asyncfifo_re = core_tx_cdc_cdc_source_ready; +assign core_tx_cdc_cdc_graycounter0_ce = (core_tx_cdc_cdc_asyncfifo_writable & core_tx_cdc_cdc_asyncfifo_we); +assign core_tx_cdc_cdc_graycounter1_ce = (core_tx_cdc_cdc_asyncfifo_readable & core_tx_cdc_cdc_asyncfifo_re); +assign core_tx_cdc_cdc_asyncfifo_writable = (((core_tx_cdc_cdc_graycounter0_q[5] == core_tx_cdc_cdc_consume_wdomain[5]) | (core_tx_cdc_cdc_graycounter0_q[4] == core_tx_cdc_cdc_consume_wdomain[4])) | (core_tx_cdc_cdc_graycounter0_q[3:0] != core_tx_cdc_cdc_consume_wdomain[3:0])); +assign core_tx_cdc_cdc_asyncfifo_readable = (core_tx_cdc_cdc_graycounter1_q != core_tx_cdc_cdc_produce_rdomain); +assign core_tx_cdc_cdc_wrport_adr = core_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_tx_cdc_cdc_wrport_dat_w = core_tx_cdc_cdc_asyncfifo_din; +assign core_tx_cdc_cdc_wrport_we = core_tx_cdc_cdc_graycounter0_ce; +assign core_tx_cdc_cdc_rdport_adr = core_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_tx_cdc_cdc_asyncfifo_dout = core_tx_cdc_cdc_rdport_dat_r; always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter0_ce) begin + core_tx_cdc_cdc_graycounter0_q_next_binary <= (core_tx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + core_tx_cdc_cdc_graycounter0_q_next_binary <= core_tx_cdc_cdc_graycounter0_q_binary; end end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_tx_cdc_cdc_graycounter0_q_next = (core_tx_cdc_cdc_graycounter0_q_next_binary ^ core_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter1_ce) begin + core_tx_cdc_cdc_graycounter1_q_next_binary <= (core_tx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + core_tx_cdc_cdc_graycounter1_q_next_binary <= core_tx_cdc_cdc_graycounter1_q_binary; end end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +assign core_tx_cdc_cdc_graycounter1_q_next = (core_tx_cdc_cdc_graycounter1_q_next_binary ^ core_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_tx_converter_converter_sink_valid = core_tx_converter_sink_valid; +assign core_tx_converter_converter_sink_first = core_tx_converter_sink_first; +assign core_tx_converter_converter_sink_last = core_tx_converter_sink_last; +assign core_tx_converter_sink_ready = core_tx_converter_converter_sink_ready; always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; + core_tx_converter_converter_sink_payload_data <= 40'd0; + core_tx_converter_converter_sink_payload_data[7:0] <= core_tx_converter_sink_payload_data[7:0]; + core_tx_converter_converter_sink_payload_data[8] <= core_tx_converter_sink_payload_last_be[0]; + core_tx_converter_converter_sink_payload_data[9] <= core_tx_converter_sink_payload_error[0]; + core_tx_converter_converter_sink_payload_data[17:10] <= core_tx_converter_sink_payload_data[15:8]; + core_tx_converter_converter_sink_payload_data[18] <= core_tx_converter_sink_payload_last_be[1]; + core_tx_converter_converter_sink_payload_data[19] <= core_tx_converter_sink_payload_error[1]; + core_tx_converter_converter_sink_payload_data[27:20] <= core_tx_converter_sink_payload_data[23:16]; + core_tx_converter_converter_sink_payload_data[28] <= core_tx_converter_sink_payload_last_be[2]; + core_tx_converter_converter_sink_payload_data[29] <= core_tx_converter_sink_payload_error[2]; + core_tx_converter_converter_sink_payload_data[37:30] <= core_tx_converter_sink_payload_data[31:24]; + core_tx_converter_converter_sink_payload_data[38] <= core_tx_converter_sink_payload_last_be[3]; + core_tx_converter_converter_sink_payload_data[39] <= core_tx_converter_sink_payload_error[3]; end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +assign core_tx_converter_source_valid = core_tx_converter_source_source_valid; +assign core_tx_converter_source_first = core_tx_converter_source_source_first; +assign core_tx_converter_source_last = core_tx_converter_source_source_last; +assign core_tx_converter_source_source_ready = core_tx_converter_source_ready; +assign {core_tx_converter_source_payload_error, core_tx_converter_source_payload_last_be, core_tx_converter_source_payload_data} = core_tx_converter_source_source_payload_data; +assign core_tx_converter_source_source_valid = core_tx_converter_converter_source_valid; +assign core_tx_converter_converter_source_ready = core_tx_converter_source_source_ready; +assign core_tx_converter_source_source_first = core_tx_converter_converter_source_first; +assign core_tx_converter_source_source_last = core_tx_converter_converter_source_last; +assign core_tx_converter_source_source_payload_data = core_tx_converter_converter_source_payload_data; +assign core_tx_converter_converter_first = (core_tx_converter_converter_mux == 1'd0); +assign core_tx_converter_converter_last = (core_tx_converter_converter_mux == 2'd3); +assign core_tx_converter_converter_source_valid = core_tx_converter_converter_sink_valid; +assign core_tx_converter_converter_source_first = (core_tx_converter_converter_sink_first & core_tx_converter_converter_first); +assign core_tx_converter_converter_source_last = (core_tx_converter_converter_sink_last & core_tx_converter_converter_last); +assign core_tx_converter_converter_sink_ready = (core_tx_converter_converter_last & core_tx_converter_converter_source_ready); always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) + core_tx_converter_converter_source_payload_data <= 10'd0; + case (core_tx_converter_converter_mux) 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[9:0]; end 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[19:10]; end 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[29:20]; end default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[39:30]; end endcase end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +assign core_tx_converter_converter_source_payload_valid_token_count = core_tx_converter_converter_last; +assign core_tx_last_be_last_handler_sink_valid = core_tx_last_be_sink_sink_valid; +assign core_tx_last_be_sink_sink_ready = core_tx_last_be_last_handler_sink_ready; +assign core_tx_last_be_last_handler_sink_first = core_tx_last_be_sink_sink_first; +assign core_tx_last_be_last_handler_sink_last = core_tx_last_be_sink_sink_last; +assign core_tx_last_be_last_handler_sink_payload_data = core_tx_last_be_sink_sink_payload_data; +assign core_tx_last_be_last_handler_sink_payload_last_be = core_tx_last_be_sink_sink_payload_last_be; +assign core_tx_last_be_last_handler_sink_payload_error = core_tx_last_be_sink_sink_payload_error; +assign core_tx_last_be_source_source_valid = core_tx_last_be_last_handler_source_valid; +assign core_tx_last_be_last_handler_source_ready = core_tx_last_be_source_source_ready; +assign core_tx_last_be_source_source_first = core_tx_last_be_last_handler_source_first; +assign core_tx_last_be_source_source_last = core_tx_last_be_last_handler_source_last; +assign core_tx_last_be_source_source_payload_data = core_tx_last_be_last_handler_source_payload_data; +assign core_tx_last_be_source_source_payload_last_be = core_tx_last_be_last_handler_source_payload_last_be; +assign core_tx_last_be_source_source_payload_error = core_tx_last_be_last_handler_source_payload_error; always @(*) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - main_tx_last_be_source_payload_last_be <= 1'd0; - main_tx_last_be_source_valid <= 1'd0; - builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; - case (builder_txdatapath_liteethmactxlastbe_state) + core_tx_last_be_last_handler_sink_ready <= 1'd0; + core_tx_last_be_last_handler_source_first <= 1'd0; + core_tx_last_be_last_handler_source_last <= 1'd0; + core_tx_last_be_last_handler_source_payload_data <= 8'd0; + core_tx_last_be_last_handler_source_payload_error <= 1'd0; + core_tx_last_be_last_handler_source_payload_last_be <= 1'd0; + core_tx_last_be_last_handler_source_valid <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= txdatapath_liteethmactxlastbe_state; + case (txdatapath_liteethmactxlastbe_state) 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + core_tx_last_be_last_handler_sink_ready <= 1'd1; + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_last)) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd0; end end default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_last <= main_tx_last_be_sink_last; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + core_tx_last_be_last_handler_source_valid <= core_tx_last_be_last_handler_sink_valid; + core_tx_last_be_last_handler_sink_ready <= core_tx_last_be_last_handler_source_ready; + core_tx_last_be_last_handler_source_first <= core_tx_last_be_last_handler_sink_first; + core_tx_last_be_last_handler_source_last <= core_tx_last_be_last_handler_sink_last; + core_tx_last_be_last_handler_source_payload_data <= core_tx_last_be_last_handler_sink_payload_data; + core_tx_last_be_last_handler_source_payload_last_be <= core_tx_last_be_last_handler_sink_payload_last_be; + core_tx_last_be_last_handler_source_payload_error <= core_tx_last_be_last_handler_sink_payload_error; + core_tx_last_be_last_handler_source_last <= (core_tx_last_be_last_handler_sink_payload_last_be != 1'd0); + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_ready)) begin + if ((core_tx_last_be_last_handler_source_last & (~core_tx_last_be_last_handler_sink_last))) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd1; end end end endcase end -assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +assign core_tx_padding_counter_done = (core_tx_padding_counter >= 6'd59); always @(*) begin - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; - main_tx_padding_sink_ready <= 1'd0; - main_tx_padding_source_first <= 1'd0; - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_data <= 8'd0; - main_tx_padding_source_payload_error <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - main_tx_padding_source_valid <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; - case (builder_txdatapath_liteethmacpaddinginserter_state) + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + core_tx_padding_sink_ready <= 1'd0; + core_tx_padding_source_first <= 1'd0; + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_data <= 8'd0; + core_tx_padding_source_payload_error <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + core_tx_padding_source_valid <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= txdatapath_liteethmacpaddinginserter_state; + case (txdatapath_liteethmacpaddinginserter_state) 1'd1: begin - main_tx_padding_source_valid <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_source_payload_last_be <= 1'd1; - main_tx_padding_source_last <= 1'd1; + core_tx_padding_source_valid <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_source_payload_last_be <= 1'd1; + core_tx_padding_source_last <= 1'd1; end - main_tx_padding_source_payload_data <= 1'd0; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + core_tx_padding_source_payload_data <= 1'd0; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; end end end default: begin - main_tx_padding_source_valid <= main_tx_padding_sink_valid; - main_tx_padding_sink_ready <= main_tx_padding_source_ready; - main_tx_padding_source_first <= main_tx_padding_sink_first; - main_tx_padding_source_last <= main_tx_padding_sink_last; - main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; - main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; - main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_sink_last) begin - if ((~main_tx_padding_counter_done)) begin - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + core_tx_padding_source_valid <= core_tx_padding_sink_valid; + core_tx_padding_sink_ready <= core_tx_padding_source_ready; + core_tx_padding_source_first <= core_tx_padding_sink_first; + core_tx_padding_source_last <= core_tx_padding_sink_last; + core_tx_padding_source_payload_data <= core_tx_padding_sink_payload_data; + core_tx_padding_source_payload_last_be <= core_tx_padding_sink_payload_last_be; + core_tx_padding_source_payload_error <= core_tx_padding_sink_payload_error; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_sink_last) begin + if ((~core_tx_padding_counter_done)) begin + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; end else begin - if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin - main_tx_padding_source_payload_last_be <= 1'd1; + if (((core_tx_padding_counter == 6'd59) & (core_tx_padding_sink_payload_last_be < 1'd1))) begin + core_tx_padding_source_payload_last_be <= 1'd1; end else begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; end end end @@ -1618,1578 +1612,1511 @@ always @(*) begin end endcase end -assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; -assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; -assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); -assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; -assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; -assign main_tx_crc_sink_first = main_tx_crc_source_source_first; -assign main_tx_crc_sink_last = main_tx_crc_source_source_last; -assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; -assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; -assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; -assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; -assign main_tx_crc_crc_prev = main_tx_crc_reg; +assign core_tx_crc_data0 = core_tx_crc_sink_payload_data; +assign core_tx_crc_be = core_tx_crc_sink_payload_last_be; +assign core_tx_crc_cnt_done = (core_tx_crc_cnt == 1'd0); +assign core_tx_crc_sink_valid = core_tx_crc_source_source_valid; +assign core_tx_crc_source_source_ready = core_tx_crc_sink_ready; +assign core_tx_crc_sink_first = core_tx_crc_source_source_first; +assign core_tx_crc_sink_last = core_tx_crc_source_source_last; +assign core_tx_crc_sink_payload_data = core_tx_crc_source_source_payload_data; +assign core_tx_crc_sink_payload_last_be = core_tx_crc_source_source_payload_last_be; +assign core_tx_crc_sink_payload_error = core_tx_crc_source_source_payload_error; +assign core_tx_crc_data1 = core_tx_crc_data0; +assign core_tx_crc_crc_prev = core_tx_crc_reg; always @(*) begin - main_tx_crc_error <= 1'd0; - main_tx_crc_value <= 32'd0; - if (main_tx_crc_be) begin - main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; - main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + core_tx_crc_error <= 1'd0; + core_tx_crc_value <= 32'd0; + if (core_tx_crc_be) begin + core_tx_crc_value <= ({core_tx_crc_crc_next[0], core_tx_crc_crc_next[1], core_tx_crc_crc_next[2], core_tx_crc_crc_next[3], core_tx_crc_crc_next[4], core_tx_crc_crc_next[5], core_tx_crc_crc_next[6], core_tx_crc_crc_next[7], core_tx_crc_crc_next[8], core_tx_crc_crc_next[9], core_tx_crc_crc_next[10], core_tx_crc_crc_next[11], core_tx_crc_crc_next[12], core_tx_crc_crc_next[13], core_tx_crc_crc_next[14], core_tx_crc_crc_next[15], core_tx_crc_crc_next[16], core_tx_crc_crc_next[17], core_tx_crc_crc_next[18], core_tx_crc_crc_next[19], core_tx_crc_crc_next[20], core_tx_crc_crc_next[21], core_tx_crc_crc_next[22], core_tx_crc_crc_next[23], core_tx_crc_crc_next[24], core_tx_crc_crc_next[25], core_tx_crc_crc_next[26], core_tx_crc_crc_next[27], core_tx_crc_crc_next[28], core_tx_crc_crc_next[29], core_tx_crc_crc_next[30], core_tx_crc_crc_next[31]} ^ 32'd4294967295); + core_tx_crc_error <= (core_tx_crc_crc_next != 32'd3338984827); end end always @(*) begin - main_tx_crc_crc_next <= 32'd0; - main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); - main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + core_tx_crc_crc_next <= 32'd0; + core_tx_crc_crc_next[0] <= (((core_tx_crc_crc_prev[24] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[1] <= (((((((core_tx_crc_crc_prev[25] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[2] <= (((((((((core_tx_crc_crc_prev[26] ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[3] <= (((((((core_tx_crc_crc_prev[27] ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[4] <= (((((((((core_tx_crc_crc_prev[28] ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[5] <= (((((((((((((core_tx_crc_crc_prev[29] ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[6] <= (((((((((((core_tx_crc_crc_prev[30] ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[7] <= (((((((((core_tx_crc_crc_prev[31] ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[8] <= ((((((((core_tx_crc_crc_prev[0] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[9] <= ((((((((core_tx_crc_crc_prev[1] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[10] <= ((((((((core_tx_crc_crc_prev[2] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[11] <= ((((((((core_tx_crc_crc_prev[3] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[12] <= ((((((((((((core_tx_crc_crc_prev[4] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[13] <= ((((((((((((core_tx_crc_crc_prev[5] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[14] <= ((((((((((core_tx_crc_crc_prev[6] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[15] <= ((((((((core_tx_crc_crc_prev[7] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[16] <= ((((((core_tx_crc_crc_prev[8] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[17] <= ((((((core_tx_crc_crc_prev[9] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[18] <= ((((((core_tx_crc_crc_prev[10] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[19] <= ((((core_tx_crc_crc_prev[11] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[20] <= ((core_tx_crc_crc_prev[12] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[21] <= ((core_tx_crc_crc_prev[13] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); + core_tx_crc_crc_next[22] <= ((core_tx_crc_crc_prev[14] ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[23] <= ((((((core_tx_crc_crc_prev[15] ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[24] <= ((((((core_tx_crc_crc_prev[16] ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[25] <= ((((core_tx_crc_crc_prev[17] ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[26] <= ((((((((core_tx_crc_crc_prev[18] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[27] <= ((((((((core_tx_crc_crc_prev[19] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[28] <= ((((((core_tx_crc_crc_prev[20] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[29] <= ((((((core_tx_crc_crc_prev[21] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[30] <= ((((core_tx_crc_crc_prev[22] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[31] <= ((core_tx_crc_crc_prev[23] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); end always @(*) begin - builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; - main_tx_crc_ce <= 1'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; - main_tx_crc_is_ongoing0 <= 1'd0; - main_tx_crc_is_ongoing1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; - main_tx_crc_reset <= 1'd0; - main_tx_crc_sink_ready <= 1'd0; - main_tx_crc_source_first <= 1'd0; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_data <= 8'd0; - main_tx_crc_source_payload_error <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - main_tx_crc_source_valid <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; - case (builder_txdatapath_bufferizeendpoints_state) + core_tx_crc_ce <= 1'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + core_tx_crc_is_ongoing0 <= 1'd0; + core_tx_crc_is_ongoing1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + core_tx_crc_reset <= 1'd0; + core_tx_crc_sink_ready <= 1'd0; + core_tx_crc_source_first <= 1'd0; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_data <= 8'd0; + core_tx_crc_source_payload_error <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + core_tx_crc_source_valid <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 2'd0; + txdatapath_bufferizeendpoints_next_state <= txdatapath_bufferizeendpoints_state; + case (txdatapath_bufferizeendpoints_state) 1'd1: begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); - main_tx_crc_source_valid <= main_tx_crc_sink_valid; - main_tx_crc_sink_ready <= main_tx_crc_source_ready; - main_tx_crc_source_first <= main_tx_crc_sink_first; - main_tx_crc_source_last <= main_tx_crc_sink_last; - main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; - main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; - main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - if (main_tx_crc_sink_last) begin - if (main_tx_crc_sink_payload_last_be) begin - main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + core_tx_crc_ce <= (core_tx_crc_sink_valid & core_tx_crc_source_ready); + core_tx_crc_source_valid <= core_tx_crc_sink_valid; + core_tx_crc_sink_ready <= core_tx_crc_source_ready; + core_tx_crc_source_first <= core_tx_crc_sink_first; + core_tx_crc_source_last <= core_tx_crc_sink_last; + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; + core_tx_crc_source_payload_last_be <= core_tx_crc_sink_payload_last_be; + core_tx_crc_source_payload_error <= core_tx_crc_sink_payload_error; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + if (core_tx_crc_sink_last) begin + if (core_tx_crc_sink_payload_last_be) begin + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; end - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - main_tx_crc_source_last <= 1'd1; - main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + core_tx_crc_source_last <= 1'd1; + core_tx_crc_source_payload_last_be <= (core_tx_crc_sink_payload_last_be <<< -3'd3); end - end else begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); end - if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (((core_tx_crc_sink_valid & core_tx_crc_sink_last) & core_tx_crc_source_ready)) begin + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end else begin - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= core_tx_crc_value; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; if (1'd0) begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (core_tx_crc_sink_payload_last_be >>> 3'd4); + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end else begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= core_tx_crc_sink_payload_last_be; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end - builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + txdatapath_bufferizeendpoints_next_state <= 2'd2; end end end 2'd2: begin - main_tx_crc_source_valid <= 1'd1; - case (main_tx_crc_cnt) + core_tx_crc_source_valid <= 1'd1; + case (core_tx_crc_cnt) 1'd0: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[31:24]; end 1'd1: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[23:16]; end 2'd2: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[15:8]; end default: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[7:0]; end endcase - if (main_tx_crc_cnt_done) begin - main_tx_crc_source_last <= 1'd1; - if (main_tx_crc_source_ready) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_tx_crc_cnt_done) begin + core_tx_crc_source_last <= 1'd1; + if (core_tx_crc_source_ready) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end end - main_tx_crc_is_ongoing1 <= 1'd1; + core_tx_crc_is_ongoing1 <= 1'd1; end default: begin - main_tx_crc_reset <= 1'd1; - main_tx_crc_sink_ready <= 1'd1; - if (main_tx_crc_sink_valid) begin - main_tx_crc_sink_ready <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + core_tx_crc_reset <= 1'd1; + core_tx_crc_sink_ready <= 1'd1; + if (core_tx_crc_sink_valid) begin + core_tx_crc_sink_ready <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 1'd1; end - main_tx_crc_is_ongoing0 <= 1'd1; + core_tx_crc_is_ongoing0 <= 1'd1; end endcase end -assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); -assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; -assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; -assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; -assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; -assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; -assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; -assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; -assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; -assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; -assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; -assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; -assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; -assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; -assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; -assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_ready = ((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready); +assign core_tx_crc_pipe_valid_sink_valid = core_tx_crc_sink_sink_valid; +assign core_tx_crc_sink_sink_ready = core_tx_crc_pipe_valid_sink_ready; +assign core_tx_crc_pipe_valid_sink_first = core_tx_crc_sink_sink_first; +assign core_tx_crc_pipe_valid_sink_last = core_tx_crc_sink_sink_last; +assign core_tx_crc_pipe_valid_sink_payload_data = core_tx_crc_sink_sink_payload_data; +assign core_tx_crc_pipe_valid_sink_payload_last_be = core_tx_crc_sink_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_payload_error = core_tx_crc_sink_sink_payload_error; +assign core_tx_crc_source_source_valid = core_tx_crc_pipe_valid_source_valid; +assign core_tx_crc_pipe_valid_source_ready = core_tx_crc_source_source_ready; +assign core_tx_crc_source_source_first = core_tx_crc_pipe_valid_source_first; +assign core_tx_crc_source_source_last = core_tx_crc_pipe_valid_source_last; +assign core_tx_crc_source_source_payload_data = core_tx_crc_pipe_valid_source_payload_data; +assign core_tx_crc_source_source_payload_last_be = core_tx_crc_pipe_valid_source_payload_last_be; +assign core_tx_crc_source_source_payload_error = core_tx_crc_pipe_valid_source_payload_error; +assign core_tx_preamble_source_payload_last_be = core_tx_preamble_sink_payload_last_be; always @(*) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; - main_tx_preamble_sink_ready <= 1'd0; - main_tx_preamble_source_first <= 1'd0; - main_tx_preamble_source_last <= 1'd0; - main_tx_preamble_source_payload_data <= 8'd0; - main_tx_preamble_source_payload_error <= 1'd0; - main_tx_preamble_source_valid <= 1'd0; - main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; - builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; - case (builder_txdatapath_liteethmacpreambleinserter_state) + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + core_tx_preamble_sink_ready <= 1'd0; + core_tx_preamble_source_first <= 1'd0; + core_tx_preamble_source_last <= 1'd0; + core_tx_preamble_source_payload_data <= 8'd0; + core_tx_preamble_source_payload_error <= 1'd0; + core_tx_preamble_source_valid <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + core_tx_preamble_source_payload_data <= core_tx_preamble_sink_payload_data; + txdatapath_liteethmacpreambleinserter_next_state <= txdatapath_liteethmacpreambleinserter_state; + case (txdatapath_liteethmacpreambleinserter_state) 1'd1: begin - main_tx_preamble_source_valid <= 1'd1; - case (main_tx_preamble_count) + core_tx_preamble_source_valid <= 1'd1; + case (core_tx_preamble_count) 1'd0: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[7:0]; end 1'd1: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[15:8]; end 2'd2: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[23:16]; end 2'd3: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[31:24]; end 3'd4: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[39:32]; end 3'd5: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[47:40]; end 3'd6: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[55:48]; end default: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[63:56]; end endcase - if (main_tx_preamble_source_ready) begin - if ((main_tx_preamble_count == 3'd7)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + if (core_tx_preamble_source_ready) begin + if ((core_tx_preamble_count == 3'd7)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; end else begin - main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= (core_tx_preamble_count + 1'd1); + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; end end end 2'd2: begin - main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; - main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; - main_tx_preamble_source_first <= main_tx_preamble_sink_first; - main_tx_preamble_source_last <= main_tx_preamble_sink_last; - main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; - if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + core_tx_preamble_source_valid <= core_tx_preamble_sink_valid; + core_tx_preamble_sink_ready <= core_tx_preamble_source_ready; + core_tx_preamble_source_first <= core_tx_preamble_sink_first; + core_tx_preamble_source_last <= core_tx_preamble_sink_last; + core_tx_preamble_source_payload_error <= core_tx_preamble_sink_payload_error; + if (((core_tx_preamble_sink_valid & core_tx_preamble_sink_last) & core_tx_preamble_source_ready)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; end end default: begin - main_tx_preamble_sink_ready <= 1'd1; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; - if (main_tx_preamble_sink_valid) begin - main_tx_preamble_sink_ready <= 1'd0; - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + core_tx_preamble_sink_ready <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (core_tx_preamble_sink_valid) begin + core_tx_preamble_sink_ready <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; end end endcase end always @(*) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; - main_tx_gap_sink_ready <= 1'd0; - main_tx_gap_source_first <= 1'd0; - main_tx_gap_source_last <= 1'd0; - main_tx_gap_source_payload_data <= 8'd0; - main_tx_gap_source_payload_error <= 1'd0; - main_tx_gap_source_payload_last_be <= 1'd0; - main_tx_gap_source_valid <= 1'd0; - builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; - case (builder_txdatapath_liteethmacgap_state) + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + core_tx_gap_sink_ready <= 1'd0; + core_tx_gap_source_first <= 1'd0; + core_tx_gap_source_last <= 1'd0; + core_tx_gap_source_payload_data <= 8'd0; + core_tx_gap_source_payload_error <= 1'd0; + core_tx_gap_source_payload_last_be <= 1'd0; + core_tx_gap_source_valid <= 1'd0; + txdatapath_liteethmacgap_next_state <= 1'd0; + txdatapath_liteethmacgap_next_state <= txdatapath_liteethmacgap_state; + case (txdatapath_liteethmacgap_state) 1'd1: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - if ((main_tx_gap_counter == 4'd11)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= (core_tx_gap_counter + 1'd1); + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((core_tx_gap_counter == 4'd11)) begin + txdatapath_liteethmacgap_next_state <= 1'd0; end end default: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - main_tx_gap_source_valid <= main_tx_gap_sink_valid; - main_tx_gap_sink_ready <= main_tx_gap_source_ready; - main_tx_gap_source_first <= main_tx_gap_sink_first; - main_tx_gap_source_last <= main_tx_gap_sink_last; - main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; - main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; - main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; - if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd1; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + core_tx_gap_source_valid <= core_tx_gap_sink_valid; + core_tx_gap_sink_ready <= core_tx_gap_source_ready; + core_tx_gap_source_first <= core_tx_gap_sink_first; + core_tx_gap_source_last <= core_tx_gap_sink_last; + core_tx_gap_source_payload_data <= core_tx_gap_sink_payload_data; + core_tx_gap_source_payload_last_be <= core_tx_gap_sink_payload_last_be; + core_tx_gap_source_payload_error <= core_tx_gap_sink_payload_error; + if (((core_tx_gap_sink_valid & core_tx_gap_sink_last) & core_tx_gap_sink_ready)) begin + txdatapath_liteethmacgap_next_state <= 1'd1; end end endcase end -assign main_tx_cdc_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_sink_first; -assign main_tx_cdc_sink_sink_last = main_sink_last; -assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; -assign main_tx_padding_sink_first = main_tx_last_be_source_first; -assign main_tx_padding_sink_last = main_tx_last_be_source_last; -assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; -assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; -assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; -assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; -assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; -assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; -assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; -assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; -assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; -assign main_tx_preamble_sink_first = main_tx_crc_source_first; -assign main_tx_preamble_sink_last = main_tx_crc_source_last; -assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; -assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; -assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; -assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; -assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; -assign main_tx_gap_sink_first = main_tx_preamble_source_first; -assign main_tx_gap_sink_last = main_tx_preamble_source_last; -assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; -assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; -assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; -assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; -assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; -assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; -assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; -assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; -assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; -assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; -assign main_pulsesynchronizer0_i = main_rx_preamble_error; -assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; -assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; -assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +assign core_tx_cdc_sink_sink_valid = core_sink_valid; +assign core_sink_ready = core_tx_cdc_sink_sink_ready; +assign core_tx_cdc_sink_sink_first = core_sink_first; +assign core_tx_cdc_sink_sink_last = core_sink_last; +assign core_tx_cdc_sink_sink_payload_data = core_sink_payload_data; +assign core_tx_cdc_sink_sink_payload_last_be = core_sink_payload_last_be; +assign core_tx_cdc_sink_sink_payload_error = core_sink_payload_error; +assign core_tx_converter_sink_valid = core_tx_cdc_source_source_valid; +assign core_tx_cdc_source_source_ready = core_tx_converter_sink_ready; +assign core_tx_converter_sink_first = core_tx_cdc_source_source_first; +assign core_tx_converter_sink_last = core_tx_cdc_source_source_last; +assign core_tx_converter_sink_payload_data = core_tx_cdc_source_source_payload_data; +assign core_tx_converter_sink_payload_last_be = core_tx_cdc_source_source_payload_last_be; +assign core_tx_converter_sink_payload_error = core_tx_cdc_source_source_payload_error; +assign core_tx_last_be_sink_sink_valid = core_tx_converter_source_valid; +assign core_tx_converter_source_ready = core_tx_last_be_sink_sink_ready; +assign core_tx_last_be_sink_sink_first = core_tx_converter_source_first; +assign core_tx_last_be_sink_sink_last = core_tx_converter_source_last; +assign core_tx_last_be_sink_sink_payload_data = core_tx_converter_source_payload_data; +assign core_tx_last_be_sink_sink_payload_last_be = core_tx_converter_source_payload_last_be; +assign core_tx_last_be_sink_sink_payload_error = core_tx_converter_source_payload_error; +assign core_tx_padding_sink_valid = core_tx_last_be_source_source_valid; +assign core_tx_last_be_source_source_ready = core_tx_padding_sink_ready; +assign core_tx_padding_sink_first = core_tx_last_be_source_source_first; +assign core_tx_padding_sink_last = core_tx_last_be_source_source_last; +assign core_tx_padding_sink_payload_data = core_tx_last_be_source_source_payload_data; +assign core_tx_padding_sink_payload_last_be = core_tx_last_be_source_source_payload_last_be; +assign core_tx_padding_sink_payload_error = core_tx_last_be_source_source_payload_error; +assign core_tx_crc_sink_sink_valid = core_tx_padding_source_valid; +assign core_tx_padding_source_ready = core_tx_crc_sink_sink_ready; +assign core_tx_crc_sink_sink_first = core_tx_padding_source_first; +assign core_tx_crc_sink_sink_last = core_tx_padding_source_last; +assign core_tx_crc_sink_sink_payload_data = core_tx_padding_source_payload_data; +assign core_tx_crc_sink_sink_payload_last_be = core_tx_padding_source_payload_last_be; +assign core_tx_crc_sink_sink_payload_error = core_tx_padding_source_payload_error; +assign core_tx_preamble_sink_valid = core_tx_crc_source_valid; +assign core_tx_crc_source_ready = core_tx_preamble_sink_ready; +assign core_tx_preamble_sink_first = core_tx_crc_source_first; +assign core_tx_preamble_sink_last = core_tx_crc_source_last; +assign core_tx_preamble_sink_payload_data = core_tx_crc_source_payload_data; +assign core_tx_preamble_sink_payload_last_be = core_tx_crc_source_payload_last_be; +assign core_tx_preamble_sink_payload_error = core_tx_crc_source_payload_error; +assign core_tx_gap_sink_valid = core_tx_preamble_source_valid; +assign core_tx_preamble_source_ready = core_tx_gap_sink_ready; +assign core_tx_gap_sink_first = core_tx_preamble_source_first; +assign core_tx_gap_sink_last = core_tx_preamble_source_last; +assign core_tx_gap_sink_payload_data = core_tx_preamble_source_payload_data; +assign core_tx_gap_sink_payload_last_be = core_tx_preamble_source_payload_last_be; +assign core_tx_gap_sink_payload_error = core_tx_preamble_source_payload_error; +assign maccore_ethphy_sink_valid = core_tx_gap_source_valid; +assign core_tx_gap_source_ready = maccore_ethphy_sink_ready; +assign maccore_ethphy_sink_first = core_tx_gap_source_first; +assign maccore_ethphy_sink_last = core_tx_gap_source_last; +assign maccore_ethphy_sink_payload_data = core_tx_gap_source_payload_data; +assign maccore_ethphy_sink_payload_last_be = core_tx_gap_source_payload_last_be; +assign maccore_ethphy_sink_payload_error = core_tx_gap_source_payload_error; +assign core_pulsesynchronizer0_i = core_rx_preamble_error; +assign core_pulsesynchronizer1_i = core_liteethmaccrc32checker_error; +assign core_rx_preamble_source_payload_data = core_rx_preamble_sink_payload_data; +assign core_rx_preamble_source_payload_last_be = core_rx_preamble_sink_payload_last_be; always @(*) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; - main_rx_preamble_error <= 1'd0; - main_rx_preamble_sink_ready <= 1'd0; - main_rx_preamble_source_first <= 1'd0; - main_rx_preamble_source_last <= 1'd0; - main_rx_preamble_source_payload_error <= 1'd0; - main_rx_preamble_source_valid <= 1'd0; - builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; - case (builder_rxdatapath_liteethmacpreamblechecker_state) + core_rx_preamble_error <= 1'd0; + core_rx_preamble_sink_ready <= 1'd0; + core_rx_preamble_source_first <= 1'd0; + core_rx_preamble_source_last <= 1'd0; + core_rx_preamble_source_payload_error <= 1'd0; + core_rx_preamble_source_valid <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= rxdatapath_liteethmacpreamblechecker_state; + case (rxdatapath_liteethmacpreamblechecker_state) 1'd1: begin - main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; - main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; - main_rx_preamble_source_first <= main_rx_preamble_sink_first; - main_rx_preamble_source_last <= main_rx_preamble_sink_last; - main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; - if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + core_rx_preamble_source_valid <= core_rx_preamble_sink_valid; + core_rx_preamble_sink_ready <= core_rx_preamble_source_ready; + core_rx_preamble_source_first <= core_rx_preamble_sink_first; + core_rx_preamble_source_last <= core_rx_preamble_sink_last; + core_rx_preamble_source_payload_error <= core_rx_preamble_sink_payload_error; + if (((core_rx_preamble_source_valid & core_rx_preamble_source_last) & core_rx_preamble_source_ready)) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; end end default: begin - main_rx_preamble_sink_ready <= 1'd1; - if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + core_rx_preamble_sink_ready <= 1'd1; + if (((core_rx_preamble_sink_valid & (~core_rx_preamble_sink_last)) & (core_rx_preamble_sink_payload_data == core_rx_preamble_preamble[63:56]))) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; end - if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin - main_rx_preamble_error <= 1'd1; + if ((core_rx_preamble_sink_valid & core_rx_preamble_sink_last)) begin + core_rx_preamble_error <= 1'd1; end end endcase end -assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); -assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); -assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); -assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); -assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; -assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +assign core_pulsesynchronizer0_o = (core_pulsesynchronizer0_toggle_o ^ core_pulsesynchronizer0_toggle_o_r); +assign core_liteethmaccrc32checker_fifo_full = (core_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign core_liteethmaccrc32checker_fifo_in = (core_liteethmaccrc32checker_sink_sink_valid & ((~core_liteethmaccrc32checker_fifo_full) | core_liteethmaccrc32checker_fifo_out)); +assign core_liteethmaccrc32checker_fifo_out = (core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready); +assign core_liteethmaccrc32checker_syncfifo_sink_first = core_liteethmaccrc32checker_sink_sink_first; +assign core_liteethmaccrc32checker_syncfifo_sink_last = core_liteethmaccrc32checker_sink_sink_last; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_data = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_last_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_error = core_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; + core_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_sink_sink_valid; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_fifo_in; end always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + core_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_syncfifo_sink_ready; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; -assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; -assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; -assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +assign core_liteethmaccrc32checker_crc_data0 = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_crc_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_source_source_first = core_liteethmaccrc32checker_syncfifo_source_first; +assign core_liteethmaccrc32checker_source_source_payload_data = core_liteethmaccrc32checker_syncfifo_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_valid = core_bufferizeendpoints_source_source_valid; +assign core_bufferizeendpoints_source_source_ready = core_liteethmaccrc32checker_sink_sink_ready; +assign core_liteethmaccrc32checker_sink_sink_first = core_bufferizeendpoints_source_source_first; +assign core_liteethmaccrc32checker_sink_sink_last = core_bufferizeendpoints_source_source_last; +assign core_liteethmaccrc32checker_sink_sink_payload_data = core_bufferizeendpoints_source_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_payload_last_be = core_bufferizeendpoints_source_source_payload_last_be; +assign core_liteethmaccrc32checker_sink_sink_payload_error = core_bufferizeendpoints_source_source_payload_error; +assign core_liteethmaccrc32checker_crc_data1 = core_liteethmaccrc32checker_crc_data0; +assign core_liteethmaccrc32checker_crc_crc_prev = core_liteethmaccrc32checker_crc_reg; always @(*) begin - main_liteethmaccrc32checker_crc_error0 <= 1'd0; - main_liteethmaccrc32checker_crc_value <= 32'd0; - if (main_liteethmaccrc32checker_crc_be) begin - main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; - main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + core_liteethmaccrc32checker_crc_error0 <= 1'd0; + core_liteethmaccrc32checker_crc_value <= 32'd0; + if (core_liteethmaccrc32checker_crc_be) begin + core_liteethmaccrc32checker_crc_value <= ({core_liteethmaccrc32checker_crc_crc_next[0], core_liteethmaccrc32checker_crc_crc_next[1], core_liteethmaccrc32checker_crc_crc_next[2], core_liteethmaccrc32checker_crc_crc_next[3], core_liteethmaccrc32checker_crc_crc_next[4], core_liteethmaccrc32checker_crc_crc_next[5], core_liteethmaccrc32checker_crc_crc_next[6], core_liteethmaccrc32checker_crc_crc_next[7], core_liteethmaccrc32checker_crc_crc_next[8], core_liteethmaccrc32checker_crc_crc_next[9], core_liteethmaccrc32checker_crc_crc_next[10], core_liteethmaccrc32checker_crc_crc_next[11], core_liteethmaccrc32checker_crc_crc_next[12], core_liteethmaccrc32checker_crc_crc_next[13], core_liteethmaccrc32checker_crc_crc_next[14], core_liteethmaccrc32checker_crc_crc_next[15], core_liteethmaccrc32checker_crc_crc_next[16], core_liteethmaccrc32checker_crc_crc_next[17], core_liteethmaccrc32checker_crc_crc_next[18], core_liteethmaccrc32checker_crc_crc_next[19], core_liteethmaccrc32checker_crc_crc_next[20], core_liteethmaccrc32checker_crc_crc_next[21], core_liteethmaccrc32checker_crc_crc_next[22], core_liteethmaccrc32checker_crc_crc_next[23], core_liteethmaccrc32checker_crc_crc_next[24], core_liteethmaccrc32checker_crc_crc_next[25], core_liteethmaccrc32checker_crc_crc_next[26], core_liteethmaccrc32checker_crc_crc_next[27], core_liteethmaccrc32checker_crc_crc_next[28], core_liteethmaccrc32checker_crc_crc_next[29], core_liteethmaccrc32checker_crc_crc_next[30], core_liteethmaccrc32checker_crc_crc_next[31]} ^ 32'd4294967295); + core_liteethmaccrc32checker_crc_error0 <= (core_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); end end always @(*) begin - main_liteethmaccrc32checker_crc_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next <= 32'd0; + core_liteethmaccrc32checker_crc_crc_next[0] <= (((core_liteethmaccrc32checker_crc_crc_prev[24] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[1] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[25] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[26] ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[3] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[27] ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[28] ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((core_liteethmaccrc32checker_crc_crc_prev[29] ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((core_liteethmaccrc32checker_crc_crc_prev[30] ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[31] ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[0] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[1] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[2] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[3] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[4] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[5] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((core_liteethmaccrc32checker_crc_crc_prev[6] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[7] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[16] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[8] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[17] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[9] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[18] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[10] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[19] <= ((((core_liteethmaccrc32checker_crc_crc_prev[11] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[20] <= ((core_liteethmaccrc32checker_crc_crc_prev[12] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[21] <= ((core_liteethmaccrc32checker_crc_crc_prev[13] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next[22] <= ((core_liteethmaccrc32checker_crc_crc_prev[14] ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[23] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[15] ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[24] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[16] ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[25] <= ((((core_liteethmaccrc32checker_crc_crc_prev[17] ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[18] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[19] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[28] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[20] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[29] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[21] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[30] <= ((((core_liteethmaccrc32checker_crc_crc_prev[22] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[31] <= ((core_liteethmaccrc32checker_crc_crc_prev[23] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); end -assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; -assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; -assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; -assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; -assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_din = {core_liteethmaccrc32checker_syncfifo_fifo_in_last, core_liteethmaccrc32checker_syncfifo_fifo_in_first, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {core_liteethmaccrc32checker_syncfifo_fifo_out_last, core_liteethmaccrc32checker_syncfifo_fifo_out_first, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign core_liteethmaccrc32checker_syncfifo_sink_ready = core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_we = core_liteethmaccrc32checker_syncfifo_sink_valid; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_first = core_liteethmaccrc32checker_syncfifo_sink_first; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_last = core_liteethmaccrc32checker_syncfifo_sink_last; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = core_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = core_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign core_liteethmaccrc32checker_syncfifo_source_valid = core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign core_liteethmaccrc32checker_syncfifo_source_first = core_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign core_liteethmaccrc32checker_syncfifo_source_last = core_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign core_liteethmaccrc32checker_syncfifo_source_payload_data = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign core_liteethmaccrc32checker_syncfifo_source_payload_last_be = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_source_payload_error = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_re = core_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + core_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (core_liteethmaccrc32checker_syncfifo_replace) begin + core_liteethmaccrc32checker_syncfifo_wrport_adr <= (core_liteethmaccrc32checker_syncfifo_produce - 1'd1); end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + core_liteethmaccrc32checker_syncfifo_wrport_adr <= core_liteethmaccrc32checker_syncfifo_produce; end end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; -assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); -assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); -assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); -assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_w = core_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign core_liteethmaccrc32checker_syncfifo_wrport_we = (core_liteethmaccrc32checker_syncfifo_syncfifo_we & (core_liteethmaccrc32checker_syncfifo_syncfifo_writable | core_liteethmaccrc32checker_syncfifo_replace)); +assign core_liteethmaccrc32checker_syncfifo_do_read = (core_liteethmaccrc32checker_syncfifo_syncfifo_readable & core_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign core_liteethmaccrc32checker_syncfifo_rdport_adr = core_liteethmaccrc32checker_syncfifo_consume; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_dout = core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_writable = (core_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign core_liteethmaccrc32checker_syncfifo_syncfifo_readable = (core_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - main_liteethmaccrc32checker_error <= 1'd0; - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; - main_liteethmaccrc32checker_source_source_last <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; - main_liteethmaccrc32checker_source_source_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; - case (builder_rxdatapath_bufferizeendpoints_state) + core_liteethmaccrc32checker_crc_ce <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + core_liteethmaccrc32checker_crc_reset <= 1'd0; + core_liteethmaccrc32checker_error <= 1'd0; + core_liteethmaccrc32checker_fifo_reset <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + core_liteethmaccrc32checker_source_source_last <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + rxdatapath_bufferizeendpoints_next_state <= 2'd0; + core_liteethmaccrc32checker_source_source_payload_error <= core_liteethmaccrc32checker_syncfifo_source_payload_error; + rxdatapath_bufferizeendpoints_next_state <= rxdatapath_bufferizeendpoints_state; + case (rxdatapath_bufferizeendpoints_state) 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 2'd2; end end 2'd2: begin - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; - main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_fifo_out; + core_liteethmaccrc32checker_source_source_valid <= (core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_fifo_full); if (1'd1) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_sink_sink_payload_last_be; end else begin - if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + if ((core_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= (core_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); end else begin - main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; - main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + core_liteethmaccrc32checker_last_be_next_value0 <= (core_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + core_liteethmaccrc32checker_crc_error1_next_value1 <= core_liteethmaccrc32checker_crc_error0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; end end - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); - main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_sink_sink_payload_error | {1{(core_liteethmaccrc32checker_crc_error0 & core_liteethmaccrc32checker_sink_sink_last)}}); + core_liteethmaccrc32checker_error <= ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_last) & core_liteethmaccrc32checker_crc_error0); + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((core_liteethmaccrc32checker_sink_sink_last & (core_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + rxdatapath_bufferizeendpoints_next_state <= 2'd3; end else begin - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_liteethmaccrc32checker_sink_sink_last) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end end end 2'd3: begin - main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; - if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= core_liteethmaccrc32checker_syncfifo_source_valid; + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_source_source_ready; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_syncfifo_source_last; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_syncfifo_source_payload_error | {1{core_liteethmaccrc32checker_crc_error1}}); + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_last_be; + if ((core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready)) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + core_liteethmaccrc32checker_crc_reset <= 1'd1; + core_liteethmaccrc32checker_fifo_reset <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 1'd1; end endcase end -assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); -assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; -assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; -assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; -assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; -assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; -assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; -assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; -assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; -assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; -assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; -assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; -assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; -assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; -assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; -assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); -assign main_rx_padding_source_valid = main_rx_padding_sink_valid; -assign main_rx_padding_sink_ready = main_rx_padding_source_ready; -assign main_rx_padding_source_first = main_rx_padding_sink_first; -assign main_rx_padding_source_last = main_rx_padding_sink_last; -assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; -assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; -assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; -assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; -assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; -assign main_rx_last_be_source_first = main_rx_last_be_sink_first; -assign main_rx_last_be_source_last = main_rx_last_be_sink_last; -assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; -assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +assign core_bufferizeendpoints_pipe_valid_sink_ready = ((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready); +assign core_bufferizeendpoints_pipe_valid_sink_valid = core_bufferizeendpoints_sink_sink_valid; +assign core_bufferizeendpoints_sink_sink_ready = core_bufferizeendpoints_pipe_valid_sink_ready; +assign core_bufferizeendpoints_pipe_valid_sink_first = core_bufferizeendpoints_sink_sink_first; +assign core_bufferizeendpoints_pipe_valid_sink_last = core_bufferizeendpoints_sink_sink_last; +assign core_bufferizeendpoints_pipe_valid_sink_payload_data = core_bufferizeendpoints_sink_sink_payload_data; +assign core_bufferizeendpoints_pipe_valid_sink_payload_last_be = core_bufferizeendpoints_sink_sink_payload_last_be; +assign core_bufferizeendpoints_pipe_valid_sink_payload_error = core_bufferizeendpoints_sink_sink_payload_error; +assign core_bufferizeendpoints_source_source_valid = core_bufferizeendpoints_pipe_valid_source_valid; +assign core_bufferizeendpoints_pipe_valid_source_ready = core_bufferizeendpoints_source_source_ready; +assign core_bufferizeendpoints_source_source_first = core_bufferizeendpoints_pipe_valid_source_first; +assign core_bufferizeendpoints_source_source_last = core_bufferizeendpoints_pipe_valid_source_last; +assign core_bufferizeendpoints_source_source_payload_data = core_bufferizeendpoints_pipe_valid_source_payload_data; +assign core_bufferizeendpoints_source_source_payload_last_be = core_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign core_bufferizeendpoints_source_source_payload_error = core_bufferizeendpoints_pipe_valid_source_payload_error; +assign core_pulsesynchronizer1_o = (core_pulsesynchronizer1_toggle_o ^ core_pulsesynchronizer1_toggle_o_r); +assign core_rx_padding_source_valid = core_rx_padding_sink_valid; +assign core_rx_padding_sink_ready = core_rx_padding_source_ready; +assign core_rx_padding_source_first = core_rx_padding_sink_first; +assign core_rx_padding_source_last = core_rx_padding_sink_last; +assign core_rx_padding_source_payload_data = core_rx_padding_sink_payload_data; +assign core_rx_padding_source_payload_last_be = core_rx_padding_sink_payload_last_be; +assign core_rx_padding_source_payload_error = core_rx_padding_sink_payload_error; +assign core_rx_last_be_source_valid = core_rx_last_be_sink_valid; +assign core_rx_last_be_sink_ready = core_rx_last_be_source_ready; +assign core_rx_last_be_source_first = core_rx_last_be_sink_first; +assign core_rx_last_be_source_last = core_rx_last_be_sink_last; +assign core_rx_last_be_source_payload_data = core_rx_last_be_sink_payload_data; +assign core_rx_last_be_source_payload_error = core_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + core_rx_last_be_source_payload_last_be <= 1'd0; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_payload_last_be; if (1'd1) begin - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_last; end end -assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; -assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; -assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; -assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; -assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; -assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; -assign main_rx_converter_source_first = main_rx_converter_source_source_first; -assign main_rx_converter_source_last = main_rx_converter_source_source_last; -assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +assign core_rx_converter_converter_sink_valid = core_rx_converter_sink_valid; +assign core_rx_converter_converter_sink_first = core_rx_converter_sink_first; +assign core_rx_converter_converter_sink_last = core_rx_converter_sink_last; +assign core_rx_converter_sink_ready = core_rx_converter_converter_sink_ready; +assign core_rx_converter_converter_sink_payload_data = {core_rx_converter_sink_payload_error, core_rx_converter_sink_payload_last_be, core_rx_converter_sink_payload_data}; +assign core_rx_converter_source_valid = core_rx_converter_source_source_valid; +assign core_rx_converter_source_first = core_rx_converter_source_source_first; +assign core_rx_converter_source_last = core_rx_converter_source_source_last; +assign core_rx_converter_source_source_ready = core_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + core_rx_converter_source_payload_data <= 32'd0; + core_rx_converter_source_payload_data[7:0] <= core_rx_converter_source_source_payload_data[7:0]; + core_rx_converter_source_payload_data[15:8] <= core_rx_converter_source_source_payload_data[17:10]; + core_rx_converter_source_payload_data[23:16] <= core_rx_converter_source_source_payload_data[27:20]; + core_rx_converter_source_payload_data[31:24] <= core_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + core_rx_converter_source_payload_last_be <= 4'd0; + core_rx_converter_source_payload_last_be[0] <= core_rx_converter_source_source_payload_data[8]; + core_rx_converter_source_payload_last_be[1] <= core_rx_converter_source_source_payload_data[18]; + core_rx_converter_source_payload_last_be[2] <= core_rx_converter_source_source_payload_data[28]; + core_rx_converter_source_payload_last_be[3] <= core_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + core_rx_converter_source_payload_error <= 4'd0; + core_rx_converter_source_payload_error[0] <= core_rx_converter_source_source_payload_data[9]; + core_rx_converter_source_payload_error[1] <= core_rx_converter_source_source_payload_data[19]; + core_rx_converter_source_payload_error[2] <= core_rx_converter_source_source_payload_data[29]; + core_rx_converter_source_payload_error[3] <= core_rx_converter_source_source_payload_data[39]; end -assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; -assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; -assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; -assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; -assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; -assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); -assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; -assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; -assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; -assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; -assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; -assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; -assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; -assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; -assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; -assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; -assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; -assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; -assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; -assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; -assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; -assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; -assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; -assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; -assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; -assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; -assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; -assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; -assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; -assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; -assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; -assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; -assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; -assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; -assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; -assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; -assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; -assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); -assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); -assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); -assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); -assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; -assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; -assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +assign core_rx_converter_source_source_valid = core_rx_converter_converter_source_valid; +assign core_rx_converter_converter_source_ready = core_rx_converter_source_source_ready; +assign core_rx_converter_source_source_first = core_rx_converter_converter_source_first; +assign core_rx_converter_source_source_last = core_rx_converter_converter_source_last; +assign core_rx_converter_source_source_payload_data = core_rx_converter_converter_source_payload_data; +assign core_rx_converter_converter_sink_ready = ((~core_rx_converter_converter_strobe_all) | core_rx_converter_converter_source_ready); +assign core_rx_converter_converter_source_valid = core_rx_converter_converter_strobe_all; +assign core_rx_converter_converter_load_part = (core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready); +assign core_rx_cdc_cdc_sink_valid = core_rx_cdc_sink_sink_valid; +assign core_rx_cdc_sink_sink_ready = core_rx_cdc_cdc_sink_ready; +assign core_rx_cdc_cdc_sink_first = core_rx_cdc_sink_sink_first; +assign core_rx_cdc_cdc_sink_last = core_rx_cdc_sink_sink_last; +assign core_rx_cdc_cdc_sink_payload_data = core_rx_cdc_sink_sink_payload_data; +assign core_rx_cdc_cdc_sink_payload_last_be = core_rx_cdc_sink_sink_payload_last_be; +assign core_rx_cdc_cdc_sink_payload_error = core_rx_cdc_sink_sink_payload_error; +assign core_rx_cdc_source_source_valid = core_rx_cdc_cdc_source_valid; +assign core_rx_cdc_cdc_source_ready = core_rx_cdc_source_source_ready; +assign core_rx_cdc_source_source_first = core_rx_cdc_cdc_source_first; +assign core_rx_cdc_source_source_last = core_rx_cdc_cdc_source_last; +assign core_rx_cdc_source_source_payload_data = core_rx_cdc_cdc_source_payload_data; +assign core_rx_cdc_source_source_payload_last_be = core_rx_cdc_cdc_source_payload_last_be; +assign core_rx_cdc_source_source_payload_error = core_rx_cdc_cdc_source_payload_error; +assign core_rx_cdc_cdc_asyncfifo_din = {core_rx_cdc_cdc_fifo_in_last, core_rx_cdc_cdc_fifo_in_first, core_rx_cdc_cdc_fifo_in_payload_error, core_rx_cdc_cdc_fifo_in_payload_last_be, core_rx_cdc_cdc_fifo_in_payload_data}; +assign {core_rx_cdc_cdc_fifo_out_last, core_rx_cdc_cdc_fifo_out_first, core_rx_cdc_cdc_fifo_out_payload_error, core_rx_cdc_cdc_fifo_out_payload_last_be, core_rx_cdc_cdc_fifo_out_payload_data} = core_rx_cdc_cdc_asyncfifo_dout; +assign core_rx_cdc_cdc_sink_ready = core_rx_cdc_cdc_asyncfifo_writable; +assign core_rx_cdc_cdc_asyncfifo_we = core_rx_cdc_cdc_sink_valid; +assign core_rx_cdc_cdc_fifo_in_first = core_rx_cdc_cdc_sink_first; +assign core_rx_cdc_cdc_fifo_in_last = core_rx_cdc_cdc_sink_last; +assign core_rx_cdc_cdc_fifo_in_payload_data = core_rx_cdc_cdc_sink_payload_data; +assign core_rx_cdc_cdc_fifo_in_payload_last_be = core_rx_cdc_cdc_sink_payload_last_be; +assign core_rx_cdc_cdc_fifo_in_payload_error = core_rx_cdc_cdc_sink_payload_error; +assign core_rx_cdc_cdc_source_valid = core_rx_cdc_cdc_asyncfifo_readable; +assign core_rx_cdc_cdc_source_first = core_rx_cdc_cdc_fifo_out_first; +assign core_rx_cdc_cdc_source_last = core_rx_cdc_cdc_fifo_out_last; +assign core_rx_cdc_cdc_source_payload_data = core_rx_cdc_cdc_fifo_out_payload_data; +assign core_rx_cdc_cdc_source_payload_last_be = core_rx_cdc_cdc_fifo_out_payload_last_be; +assign core_rx_cdc_cdc_source_payload_error = core_rx_cdc_cdc_fifo_out_payload_error; +assign core_rx_cdc_cdc_asyncfifo_re = core_rx_cdc_cdc_source_ready; +assign core_rx_cdc_cdc_graycounter0_ce = (core_rx_cdc_cdc_asyncfifo_writable & core_rx_cdc_cdc_asyncfifo_we); +assign core_rx_cdc_cdc_graycounter1_ce = (core_rx_cdc_cdc_asyncfifo_readable & core_rx_cdc_cdc_asyncfifo_re); +assign core_rx_cdc_cdc_asyncfifo_writable = (((core_rx_cdc_cdc_graycounter0_q[5] == core_rx_cdc_cdc_consume_wdomain[5]) | (core_rx_cdc_cdc_graycounter0_q[4] == core_rx_cdc_cdc_consume_wdomain[4])) | (core_rx_cdc_cdc_graycounter0_q[3:0] != core_rx_cdc_cdc_consume_wdomain[3:0])); +assign core_rx_cdc_cdc_asyncfifo_readable = (core_rx_cdc_cdc_graycounter1_q != core_rx_cdc_cdc_produce_rdomain); +assign core_rx_cdc_cdc_wrport_adr = core_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_rx_cdc_cdc_wrport_dat_w = core_rx_cdc_cdc_asyncfifo_din; +assign core_rx_cdc_cdc_wrport_we = core_rx_cdc_cdc_graycounter0_ce; +assign core_rx_cdc_cdc_rdport_adr = core_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_rx_cdc_cdc_asyncfifo_dout = core_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter0_ce) begin + core_rx_cdc_cdc_graycounter0_q_next_binary <= (core_rx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + core_rx_cdc_cdc_graycounter0_q_next_binary <= core_rx_cdc_cdc_graycounter0_q_binary; end end -assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_rx_cdc_cdc_graycounter0_q_next = (core_rx_cdc_cdc_graycounter0_q_next_binary ^ core_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter1_ce) begin + core_rx_cdc_cdc_graycounter1_q_next_binary <= (core_rx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + core_rx_cdc_cdc_graycounter1_q_next_binary <= core_rx_cdc_cdc_graycounter1_q_binary; end end -assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_valid; -assign main_maccore_ethphy_source_ready = main_rx_preamble_sink_ready; -assign main_rx_preamble_sink_first = main_maccore_ethphy_source_first; -assign main_rx_preamble_sink_last = main_maccore_ethphy_source_last; -assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_payload_data; -assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_payload_last_be; -assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_payload_error; -assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; -assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; -assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; -assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; -assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; -assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; -assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; -assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; -assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; -assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_rx_padding_source_first; -assign main_rx_last_be_sink_last = main_rx_padding_source_last; -assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; -assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; -assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; -assign main_rx_converter_sink_first = main_rx_last_be_source_first; -assign main_rx_converter_sink_last = main_rx_last_be_source_last; -assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; -assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; -assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; -assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; -assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; -assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; -assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; -assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; -assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; -assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_source_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_source_ready; -assign main_source_first = main_rx_cdc_source_source_first; -assign main_source_last = main_rx_cdc_source_source_last; -assign main_source_payload_data = main_rx_cdc_source_source_payload_data; -assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_source_payload_error = main_rx_cdc_source_source_payload_error; -assign main_sram0_sink_valid = main_sink_sink_valid; -assign main_sink_sink_ready = main_sram1_sink_ready; -assign main_sram2_sink_first = main_sink_sink_first; -assign main_sram3_sink_last = main_sink_sink_last; -assign main_sram4_sink_payload_data = main_sink_sink_payload_data; -assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; -assign main_sram6_sink_payload_error = main_sink_sink_payload_error; -assign main_source_source_valid = main_sram83_source_valid; -assign main_sram84_source_ready = main_source_source_ready; -assign main_source_source_first = main_sram85_source_first; -assign main_source_source_last = main_sram86_source_last; -assign main_source_source_payload_data = main_sram87_source_payload_data; -assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; -assign main_source_source_payload_error = main_sram89_source_payload_error; +assign core_rx_cdc_cdc_graycounter1_q_next = (core_rx_cdc_cdc_graycounter1_q_next_binary ^ core_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_rx_preamble_sink_valid = maccore_ethphy_source_valid; +assign maccore_ethphy_source_ready = core_rx_preamble_sink_ready; +assign core_rx_preamble_sink_first = maccore_ethphy_source_first; +assign core_rx_preamble_sink_last = maccore_ethphy_source_last; +assign core_rx_preamble_sink_payload_data = maccore_ethphy_source_payload_data; +assign core_rx_preamble_sink_payload_last_be = maccore_ethphy_source_payload_last_be; +assign core_rx_preamble_sink_payload_error = maccore_ethphy_source_payload_error; +assign core_bufferizeendpoints_sink_sink_valid = core_rx_preamble_source_valid; +assign core_rx_preamble_source_ready = core_bufferizeendpoints_sink_sink_ready; +assign core_bufferizeendpoints_sink_sink_first = core_rx_preamble_source_first; +assign core_bufferizeendpoints_sink_sink_last = core_rx_preamble_source_last; +assign core_bufferizeendpoints_sink_sink_payload_data = core_rx_preamble_source_payload_data; +assign core_bufferizeendpoints_sink_sink_payload_last_be = core_rx_preamble_source_payload_last_be; +assign core_bufferizeendpoints_sink_sink_payload_error = core_rx_preamble_source_payload_error; +assign core_rx_padding_sink_valid = core_liteethmaccrc32checker_source_source_valid; +assign core_liteethmaccrc32checker_source_source_ready = core_rx_padding_sink_ready; +assign core_rx_padding_sink_first = core_liteethmaccrc32checker_source_source_first; +assign core_rx_padding_sink_last = core_liteethmaccrc32checker_source_source_last; +assign core_rx_padding_sink_payload_data = core_liteethmaccrc32checker_source_source_payload_data; +assign core_rx_padding_sink_payload_last_be = core_liteethmaccrc32checker_source_source_payload_last_be; +assign core_rx_padding_sink_payload_error = core_liteethmaccrc32checker_source_source_payload_error; +assign core_rx_last_be_sink_valid = core_rx_padding_source_valid; +assign core_rx_padding_source_ready = core_rx_last_be_sink_ready; +assign core_rx_last_be_sink_first = core_rx_padding_source_first; +assign core_rx_last_be_sink_last = core_rx_padding_source_last; +assign core_rx_last_be_sink_payload_data = core_rx_padding_source_payload_data; +assign core_rx_last_be_sink_payload_last_be = core_rx_padding_source_payload_last_be; +assign core_rx_last_be_sink_payload_error = core_rx_padding_source_payload_error; +assign core_rx_converter_sink_valid = core_rx_last_be_source_valid; +assign core_rx_last_be_source_ready = core_rx_converter_sink_ready; +assign core_rx_converter_sink_first = core_rx_last_be_source_first; +assign core_rx_converter_sink_last = core_rx_last_be_source_last; +assign core_rx_converter_sink_payload_data = core_rx_last_be_source_payload_data; +assign core_rx_converter_sink_payload_last_be = core_rx_last_be_source_payload_last_be; +assign core_rx_converter_sink_payload_error = core_rx_last_be_source_payload_error; +assign core_rx_cdc_sink_sink_valid = core_rx_converter_source_valid; +assign core_rx_converter_source_ready = core_rx_cdc_sink_sink_ready; +assign core_rx_cdc_sink_sink_first = core_rx_converter_source_first; +assign core_rx_cdc_sink_sink_last = core_rx_converter_source_last; +assign core_rx_cdc_sink_sink_payload_data = core_rx_converter_source_payload_data; +assign core_rx_cdc_sink_sink_payload_last_be = core_rx_converter_source_payload_last_be; +assign core_rx_cdc_sink_sink_payload_error = core_rx_converter_source_payload_error; +assign core_source_valid = core_rx_cdc_source_source_valid; +assign core_rx_cdc_source_source_ready = core_source_ready; +assign core_source_first = core_rx_cdc_source_source_first; +assign core_source_last = core_rx_cdc_source_source_last; +assign core_source_payload_data = core_rx_cdc_source_source_payload_data; +assign core_source_payload_last_be = core_rx_cdc_source_source_payload_last_be; +assign core_source_payload_error = core_rx_cdc_source_source_payload_error; +assign wishbone_interface_writer_sink_sink_valid = wishbone_interface_sink_valid; +assign wishbone_interface_sink_ready = wishbone_interface_writer_sink_sink_ready; +assign wishbone_interface_writer_sink_sink_first = wishbone_interface_sink_first; +assign wishbone_interface_writer_sink_sink_last = wishbone_interface_sink_last; +assign wishbone_interface_writer_sink_sink_payload_data = wishbone_interface_sink_payload_data; +assign wishbone_interface_writer_sink_sink_payload_last_be = wishbone_interface_sink_payload_last_be; +assign wishbone_interface_writer_sink_sink_payload_error = wishbone_interface_sink_payload_error; +assign wishbone_interface_source_valid = wishbone_interface_reader_source_source_valid; +assign wishbone_interface_reader_source_source_ready = wishbone_interface_source_ready; +assign wishbone_interface_source_first = wishbone_interface_reader_source_source_first; +assign wishbone_interface_source_last = wishbone_interface_reader_source_source_last; +assign wishbone_interface_source_payload_data = wishbone_interface_reader_source_source_payload_data; +assign wishbone_interface_source_payload_last_be = wishbone_interface_reader_source_source_payload_last_be; +assign wishbone_interface_source_payload_error = wishbone_interface_reader_source_source_payload_error; always @(*) begin - main_length_inc <= 4'd0; - case (main_sram5_sink_payload_last_be) + wishbone_interface_writer_length_inc <= 4'd0; + case (wishbone_interface_writer_sink_sink_payload_last_be) 1'd1: begin - main_length_inc <= 1'd1; + wishbone_interface_writer_length_inc <= 1'd1; end 2'd2: begin - main_length_inc <= 2'd2; + wishbone_interface_writer_length_inc <= 2'd2; end 3'd4: begin - main_length_inc <= 2'd3; + wishbone_interface_writer_length_inc <= 2'd3; end 4'd8: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end 5'd16: begin - main_length_inc <= 3'd5; + wishbone_interface_writer_length_inc <= 3'd5; end 6'd32: begin - main_length_inc <= 3'd6; + wishbone_interface_writer_length_inc <= 3'd6; end 7'd64: begin - main_length_inc <= 3'd7; + wishbone_interface_writer_length_inc <= 3'd7; end default: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end endcase end -assign main_sram44_source_ready = main_sram20_clear; -assign main_sram19_trigger = main_sram43_source_valid; -assign main_sram7_status = main_sram47_source_payload_slot; -assign main_sram10_status = main_sram48_source_payload_length; -assign main_wr_data = main_sram4_sink_payload_data; +assign wishbone_interface_writer_stat_fifo_source_ready = wishbone_interface_writer_available_clear; +assign wishbone_interface_writer_available_trigger = wishbone_interface_writer_stat_fifo_source_valid; +assign wishbone_interface_writer_slot_status = wishbone_interface_writer_stat_fifo_source_payload_slot; +assign wishbone_interface_writer_length_status = wishbone_interface_writer_stat_fifo_source_payload_length; +assign wishbone_interface_writer_wr_data = wishbone_interface_writer_sink_sink_payload_data; always @(*) begin - main_sram75_adr <= 9'd0; - main_sram77_we <= 1'd0; - main_sram78_dat_w <= 32'd0; - main_sram79_adr <= 9'd0; - main_sram81_we <= 1'd0; - main_sram82_dat_w <= 32'd0; - case (main_slot) + wishbone_interface_writer_memory0_adr <= 9'd0; + wishbone_interface_writer_memory0_dat_w <= 32'd0; + wishbone_interface_writer_memory0_we <= 1'd0; + wishbone_interface_writer_memory1_adr <= 9'd0; + wishbone_interface_writer_memory1_dat_w <= 32'd0; + wishbone_interface_writer_memory1_we <= 1'd0; + case (wishbone_interface_writer_slot) 1'd0: begin - main_sram75_adr <= main_sram35_length[10:2]; - main_sram78_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram77_we <= 1'd1; + wishbone_interface_writer_memory0_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory0_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory0_we <= 1'd1; end end 1'd1: begin - main_sram79_adr <= main_sram35_length[10:2]; - main_sram82_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram81_we <= 1'd1; + wishbone_interface_writer_memory1_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory1_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory1_we <= 1'd1; end end endcase end -assign main_sram21_available = main_sram17_status; -assign main_sram25_available = main_sram18_pending; +assign wishbone_interface_writer_available0 = wishbone_interface_writer_available_status; +assign wishbone_interface_writer_available1 = wishbone_interface_writer_available_pending; always @(*) begin - main_sram20_clear <= 1'd0; - if ((main_sram28_re & main_sram29_r)) begin - main_sram20_clear <= 1'd1; + wishbone_interface_writer_available_clear <= 1'd0; + if ((wishbone_interface_writer_pending_re & wishbone_interface_writer_pending_r)) begin + wishbone_interface_writer_available_clear <= 1'd1; end end -assign main_sram16_irq = (main_sram26_status & main_sram31_storage); -assign main_sram17_status = main_sram19_trigger; -assign main_sram18_pending = main_sram19_trigger; -assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; -assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; -assign main_sram38_sink_ready = main_sram50_writable; -assign main_sram49_we = main_sram37_sink_valid; -assign main_sram68_fifo_in_first = main_sram39_sink_first; -assign main_sram69_fifo_in_last = main_sram40_sink_last; -assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; -assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; -assign main_sram43_source_valid = main_sram52_readable; -assign main_sram45_source_first = main_sram72_fifo_out_first; -assign main_sram46_source_last = main_sram73_fifo_out_last; -assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; -assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; -assign main_sram51_re = main_sram44_source_ready; +assign wishbone_interface_writer_irq = (wishbone_interface_writer_pending_status & wishbone_interface_writer_enable_storage); +assign wishbone_interface_writer_available_status = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_available_pending = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_stat_fifo_syncfifo_din = {wishbone_interface_writer_stat_fifo_fifo_in_last, wishbone_interface_writer_stat_fifo_fifo_in_first, wishbone_interface_writer_stat_fifo_fifo_in_payload_length, wishbone_interface_writer_stat_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_writer_stat_fifo_fifo_out_last, wishbone_interface_writer_stat_fifo_fifo_out_first, wishbone_interface_writer_stat_fifo_fifo_out_payload_length, wishbone_interface_writer_stat_fifo_fifo_out_payload_slot} = wishbone_interface_writer_stat_fifo_syncfifo_dout; +assign wishbone_interface_writer_stat_fifo_sink_ready = wishbone_interface_writer_stat_fifo_syncfifo_writable; +assign wishbone_interface_writer_stat_fifo_syncfifo_we = wishbone_interface_writer_stat_fifo_sink_valid; +assign wishbone_interface_writer_stat_fifo_fifo_in_first = wishbone_interface_writer_stat_fifo_sink_first; +assign wishbone_interface_writer_stat_fifo_fifo_in_last = wishbone_interface_writer_stat_fifo_sink_last; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_slot = wishbone_interface_writer_stat_fifo_sink_payload_slot; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_length = wishbone_interface_writer_stat_fifo_sink_payload_length; +assign wishbone_interface_writer_stat_fifo_source_valid = wishbone_interface_writer_stat_fifo_syncfifo_readable; +assign wishbone_interface_writer_stat_fifo_source_first = wishbone_interface_writer_stat_fifo_fifo_out_first; +assign wishbone_interface_writer_stat_fifo_source_last = wishbone_interface_writer_stat_fifo_fifo_out_last; +assign wishbone_interface_writer_stat_fifo_source_payload_slot = wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +assign wishbone_interface_writer_stat_fifo_source_payload_length = wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +assign wishbone_interface_writer_stat_fifo_syncfifo_re = wishbone_interface_writer_stat_fifo_source_ready; always @(*) begin - main_sram59_adr <= 1'd0; - if (main_sram56_replace) begin - main_sram59_adr <= (main_sram57_produce - 1'd1); + wishbone_interface_writer_stat_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_writer_stat_fifo_replace) begin + wishbone_interface_writer_stat_fifo_wrport_adr <= (wishbone_interface_writer_stat_fifo_produce - 1'd1); end else begin - main_sram59_adr <= main_sram57_produce; + wishbone_interface_writer_stat_fifo_wrport_adr <= wishbone_interface_writer_stat_fifo_produce; end end -assign main_sram62_dat_w = main_sram53_din; -assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); -assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); -assign main_sram64_adr = main_sram58_consume; -assign main_sram54_dout = main_sram65_dat_r; -assign main_sram50_writable = (main_sram55_level != 2'd2); -assign main_sram52_readable = (main_sram55_level != 1'd0); +assign wishbone_interface_writer_stat_fifo_wrport_dat_w = wishbone_interface_writer_stat_fifo_syncfifo_din; +assign wishbone_interface_writer_stat_fifo_wrport_we = (wishbone_interface_writer_stat_fifo_syncfifo_we & (wishbone_interface_writer_stat_fifo_syncfifo_writable | wishbone_interface_writer_stat_fifo_replace)); +assign wishbone_interface_writer_stat_fifo_do_read = (wishbone_interface_writer_stat_fifo_syncfifo_readable & wishbone_interface_writer_stat_fifo_syncfifo_re); +assign wishbone_interface_writer_stat_fifo_rdport_adr = wishbone_interface_writer_stat_fifo_consume; +assign wishbone_interface_writer_stat_fifo_syncfifo_dout = wishbone_interface_writer_stat_fifo_rdport_dat_r; +assign wishbone_interface_writer_stat_fifo_syncfifo_writable = (wishbone_interface_writer_stat_fifo_level != 2'd2); +assign wishbone_interface_writer_stat_fifo_syncfifo_readable = (wishbone_interface_writer_stat_fifo_level != 1'd0); always @(*) begin - builder_liteethmacsramwriter_next_state <= 3'd0; - main_slot_liteethmacsramwriter_next_value <= 1'd0; - main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; - main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; - main_sram37_sink_valid <= 1'd0; - main_sram41_sink_payload_slot <= 1'd0; - main_sram42_sink_payload_length <= 11'd0; - main_write <= 1'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) + liteethmacsramwriter_next_state <= 3'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= 32'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 11'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_payload_length <= 11'd0; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd0; + wishbone_interface_writer_write <= 1'd0; + liteethmacsramwriter_next_state <= liteethmacsramwriter_state; + case (liteethmacsramwriter_state) 1'd1: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end 2'd2: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if ((main_sram5_sink_payload_last_be != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if ((wishbone_interface_writer_sink_sink_payload_last_be != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end end end 2'd3: begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end 3'd4: begin - main_sram37_sink_valid <= 1'd1; - main_sram41_sink_payload_slot <= main_slot; - main_sram42_sink_payload_length <= main_sram35_length; - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); - main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd1; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= wishbone_interface_writer_slot; + wishbone_interface_writer_stat_fifo_sink_payload_length <= wishbone_interface_writer_length; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= (wishbone_interface_writer_slot + 1'd1); + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end default: begin - if (main_sram0_sink_valid) begin - if (main_sram38_sink_ready) begin - main_write <= 1'd1; - main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - if ((main_sram35_length >= 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 1'd1; + if (wishbone_interface_writer_sink_sink_valid) begin + if (wishbone_interface_writer_stat_fifo_sink_ready) begin + wishbone_interface_writer_write <= 1'd1; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= (wishbone_interface_writer_length + wishbone_interface_writer_length_inc); + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((wishbone_interface_writer_length >= 11'd1530)) begin + liteethmacsramwriter_next_state <= 1'd1; end - if (main_sram3_sink_last) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if (wishbone_interface_writer_sink_sink_last) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end else begin - main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd2; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= (wishbone_interface_writer_errors_status + 1'd1); + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 2'd2; end end end endcase end -assign main_sram123_sink_valid = main_start_re; -assign main_sram127_sink_payload_slot = main_sram100_storage; -assign main_sram128_sink_payload_length = main_sram102_storage; -assign main_sram94_status = main_sram124_sink_ready; -assign main_sram97_status = main_sram141_level; +assign wishbone_interface_reader_cmd_fifo_sink_valid = wishbone_interface_reader_start_re; +assign wishbone_interface_reader_cmd_fifo_sink_payload_slot = wishbone_interface_reader_slot_storage; +assign wishbone_interface_reader_cmd_fifo_sink_payload_length = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_ready_status = wishbone_interface_reader_cmd_fifo_sink_ready; +assign wishbone_interface_reader_level_status = wishbone_interface_reader_cmd_fifo_level; always @(*) begin - main_sram88_source_payload_last_be <= 4'd0; - if (main_sram86_source_last) begin - case (main_sram134_source_payload_length[1:0]) + wishbone_interface_reader_source_source_payload_last_be <= 4'd0; + if (wishbone_interface_reader_source_source_last) begin + case (wishbone_interface_reader_cmd_fifo_source_payload_length[1:0]) 1'd1: begin - main_sram88_source_payload_last_be <= 1'd1; + wishbone_interface_reader_source_source_payload_last_be <= 1'd1; end 2'd2: begin - main_sram88_source_payload_last_be <= 2'd2; + wishbone_interface_reader_source_source_payload_last_be <= 2'd2; end 2'd3: begin - main_sram88_source_payload_last_be <= 3'd4; + wishbone_interface_reader_source_source_payload_last_be <= 3'd4; end 3'd4: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end 3'd5: begin - main_sram88_source_payload_last_be <= 5'd16; + wishbone_interface_reader_source_source_payload_last_be <= 5'd16; end 3'd6: begin - main_sram88_source_payload_last_be <= 6'd32; + wishbone_interface_reader_source_source_payload_last_be <= 6'd32; end 3'd7: begin - main_sram88_source_payload_last_be <= 7'd64; + wishbone_interface_reader_source_source_payload_last_be <= 7'd64; end default: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end endcase end end -assign main_sram163_re = main_read; -assign main_sram161_adr = main_sram122_length[10:2]; -assign main_sram166_re = main_read; -assign main_sram164_adr = main_sram122_length[10:2]; +assign wishbone_interface_reader_memory0_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory0_adr = wishbone_interface_reader_length[10:2]; +assign wishbone_interface_reader_memory1_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory1_adr = wishbone_interface_reader_length[10:2]; always @(*) begin - main_rd_data <= 32'd0; - case (main_sram133_source_payload_slot) + wishbone_interface_reader_rd_data <= 32'd0; + case (wishbone_interface_reader_cmd_fifo_source_payload_slot) 1'd0: begin - main_rd_data <= main_sram162_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory0_dat_r; end 1'd1: begin - main_rd_data <= main_sram165_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory1_dat_r; end endcase end -assign main_sram87_source_payload_data = main_rd_data; -assign main_sram109_event0 = main_sram105_status; -assign main_sram113_event0 = main_sram106_pending; +assign wishbone_interface_reader_source_source_payload_data = wishbone_interface_reader_rd_data; +assign wishbone_interface_reader_event00 = wishbone_interface_reader_eventsourcepulse_status; +assign wishbone_interface_reader_event01 = wishbone_interface_reader_eventsourcepulse_pending; always @(*) begin - main_sram108_clear <= 1'd0; - if ((main_sram116_re & main_sram117_r)) begin - main_sram108_clear <= 1'd1; + wishbone_interface_reader_eventsourcepulse_clear <= 1'd0; + if ((wishbone_interface_reader_pending_re & wishbone_interface_reader_pending_r)) begin + wishbone_interface_reader_eventsourcepulse_clear <= 1'd1; end end -assign main_sram104_irq = (main_sram114_status & main_sram119_storage); -assign main_sram105_status = 1'd0; -assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; -assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; -assign main_sram124_sink_ready = main_sram136_writable; -assign main_sram135_we = main_sram123_sink_valid; -assign main_sram154_fifo_in_first = main_sram125_sink_first; -assign main_sram155_fifo_in_last = main_sram126_sink_last; -assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; -assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; -assign main_sram129_source_valid = main_sram138_readable; -assign main_sram131_source_first = main_sram158_fifo_out_first; -assign main_sram132_source_last = main_sram159_fifo_out_last; -assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; -assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; -assign main_sram137_re = main_sram130_source_ready; +assign wishbone_interface_reader_irq = (wishbone_interface_reader_pending_status & wishbone_interface_reader_enable_storage); +assign wishbone_interface_reader_eventsourcepulse_status = 1'd0; +assign wishbone_interface_reader_cmd_fifo_syncfifo_din = {wishbone_interface_reader_cmd_fifo_fifo_in_last, wishbone_interface_reader_cmd_fifo_fifo_in_first, wishbone_interface_reader_cmd_fifo_fifo_in_payload_length, wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_reader_cmd_fifo_fifo_out_last, wishbone_interface_reader_cmd_fifo_fifo_out_first, wishbone_interface_reader_cmd_fifo_fifo_out_payload_length, wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot} = wishbone_interface_reader_cmd_fifo_syncfifo_dout; +assign wishbone_interface_reader_cmd_fifo_sink_ready = wishbone_interface_reader_cmd_fifo_syncfifo_writable; +assign wishbone_interface_reader_cmd_fifo_syncfifo_we = wishbone_interface_reader_cmd_fifo_sink_valid; +assign wishbone_interface_reader_cmd_fifo_fifo_in_first = wishbone_interface_reader_cmd_fifo_sink_first; +assign wishbone_interface_reader_cmd_fifo_fifo_in_last = wishbone_interface_reader_cmd_fifo_sink_last; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot = wishbone_interface_reader_cmd_fifo_sink_payload_slot; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_length = wishbone_interface_reader_cmd_fifo_sink_payload_length; +assign wishbone_interface_reader_cmd_fifo_source_valid = wishbone_interface_reader_cmd_fifo_syncfifo_readable; +assign wishbone_interface_reader_cmd_fifo_source_first = wishbone_interface_reader_cmd_fifo_fifo_out_first; +assign wishbone_interface_reader_cmd_fifo_source_last = wishbone_interface_reader_cmd_fifo_fifo_out_last; +assign wishbone_interface_reader_cmd_fifo_source_payload_slot = wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +assign wishbone_interface_reader_cmd_fifo_source_payload_length = wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +assign wishbone_interface_reader_cmd_fifo_syncfifo_re = wishbone_interface_reader_cmd_fifo_source_ready; always @(*) begin - main_sram145_adr <= 1'd0; - if (main_sram142_replace) begin - main_sram145_adr <= (main_sram143_produce - 1'd1); + wishbone_interface_reader_cmd_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_reader_cmd_fifo_replace) begin + wishbone_interface_reader_cmd_fifo_wrport_adr <= (wishbone_interface_reader_cmd_fifo_produce - 1'd1); end else begin - main_sram145_adr <= main_sram143_produce; + wishbone_interface_reader_cmd_fifo_wrport_adr <= wishbone_interface_reader_cmd_fifo_produce; end end -assign main_sram148_dat_w = main_sram139_din; -assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); -assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); -assign main_sram150_adr = main_sram144_consume; -assign main_sram140_dout = main_sram151_dat_r; -assign main_sram136_writable = (main_sram141_level != 2'd2); -assign main_sram138_readable = (main_sram141_level != 1'd0); +assign wishbone_interface_reader_cmd_fifo_wrport_dat_w = wishbone_interface_reader_cmd_fifo_syncfifo_din; +assign wishbone_interface_reader_cmd_fifo_wrport_we = (wishbone_interface_reader_cmd_fifo_syncfifo_we & (wishbone_interface_reader_cmd_fifo_syncfifo_writable | wishbone_interface_reader_cmd_fifo_replace)); +assign wishbone_interface_reader_cmd_fifo_do_read = (wishbone_interface_reader_cmd_fifo_syncfifo_readable & wishbone_interface_reader_cmd_fifo_syncfifo_re); +assign wishbone_interface_reader_cmd_fifo_rdport_adr = wishbone_interface_reader_cmd_fifo_consume; +assign wishbone_interface_reader_cmd_fifo_syncfifo_dout = wishbone_interface_reader_cmd_fifo_rdport_dat_r; +assign wishbone_interface_reader_cmd_fifo_syncfifo_writable = (wishbone_interface_reader_cmd_fifo_level != 2'd2); +assign wishbone_interface_reader_cmd_fifo_syncfifo_readable = (wishbone_interface_reader_cmd_fifo_level != 1'd0); always @(*) begin - builder_liteethmacsramreader_next_state <= 2'd0; - main_read <= 1'd0; - main_sram107_trigger <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value <= 11'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; - main_sram130_source_ready <= 1'd0; - main_sram83_source_valid <= 1'd0; - main_sram86_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) + liteethmacsramreader_next_state <= 2'd0; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd0; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 11'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd0; + wishbone_interface_reader_read <= 1'd0; + wishbone_interface_reader_source_source_last <= 1'd0; + wishbone_interface_reader_source_source_valid <= 1'd0; + liteethmacsramreader_next_state <= liteethmacsramreader_state; + case (liteethmacsramreader_state) 1'd1: begin - main_sram83_source_valid <= 1'd1; - main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); - if (main_sram84_source_ready) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - if (main_sram86_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; + wishbone_interface_reader_source_source_valid <= 1'd1; + wishbone_interface_reader_source_source_last <= (wishbone_interface_reader_length >= wishbone_interface_reader_cmd_fifo_source_payload_length); + if (wishbone_interface_reader_source_source_ready) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= (wishbone_interface_reader_length + 3'd4); + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (wishbone_interface_reader_source_source_last) begin + liteethmacsramreader_next_state <= 2'd2; end end end 2'd2: begin - main_sram122_length_liteethmacsramreader_next_value <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - main_sram107_trigger <= 1'd1; - main_sram130_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd1; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd1; + liteethmacsramreader_next_state <= 1'd0; end default: begin - if (main_sram129_source_valid) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= 3'd4; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; + if (wishbone_interface_reader_cmd_fifo_source_valid) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 3'd4; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + liteethmacsramreader_next_state <= 1'd1; end end endcase end -assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); -assign main_sram0_adr = main_interface0_adr[8:0]; -assign main_interface0_dat_r = main_sram0_dat_r; -assign main_sram1_adr = main_interface1_adr[8:0]; -assign main_interface1_dat_r = main_sram1_dat_r; +assign wishbone_interface_ev_irq = (wishbone_interface_writer_irq | wishbone_interface_reader_irq); +assign wishbone_interface_sram0_adr = wishbone_interface_interface0_adr[8:0]; +assign wishbone_interface_interface0_dat_r = wishbone_interface_sram0_dat_r; +assign wishbone_interface_sram1_adr = wishbone_interface_interface1_adr[8:0]; +assign wishbone_interface_interface1_dat_r = wishbone_interface_sram1_dat_r; +always @(*) begin + wishbone_interface_decoder0_slave_sel <= 2'd0; + wishbone_interface_decoder0_slave_sel[0] <= (wishbone_interface_bus_rx_adr[9] == 1'd0); + wishbone_interface_decoder0_slave_sel[1] <= (wishbone_interface_bus_rx_adr[9] == 1'd1); +end +assign wishbone_interface_interface0_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface0_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface0_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface0_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface0_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface0_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface0_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface1_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface1_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface1_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface1_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface1_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface1_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface1_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface0_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[0]); +assign wishbone_interface_interface1_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[1]); +assign wishbone_interface_bus_rx_ack = (wishbone_interface_interface0_ack | wishbone_interface_interface1_ack); +assign wishbone_interface_bus_rx_err = (wishbone_interface_interface0_err | wishbone_interface_interface1_err); +assign wishbone_interface_bus_rx_dat_r = (({32{wishbone_interface_decoder0_slave_sel_r[0]}} & wishbone_interface_interface0_dat_r) | ({32{wishbone_interface_decoder0_slave_sel_r[1]}} & wishbone_interface_interface1_dat_r)); always @(*) begin - main_sram2_we <= 4'd0; - main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); - main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); - main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); - main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); + wishbone_interface_sram2_we <= 4'd0; + wishbone_interface_sram2_we[0] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[0]); + wishbone_interface_sram2_we[1] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[1]); + wishbone_interface_sram2_we[2] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[2]); + wishbone_interface_sram2_we[3] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[3]); end -assign main_sram2_adr = main_interface2_adr[8:0]; -assign main_interface2_dat_r = main_sram2_dat_r; -assign main_sram2_dat_w = main_interface2_dat_w; +assign wishbone_interface_sram2_adr = wishbone_interface_interface2_adr[8:0]; +assign wishbone_interface_interface2_dat_r = wishbone_interface_sram2_dat_r; +assign wishbone_interface_sram2_dat_w = wishbone_interface_interface2_dat_w; always @(*) begin - main_sram3_we <= 4'd0; - main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); - main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); - main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); - main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); + wishbone_interface_sram3_we <= 4'd0; + wishbone_interface_sram3_we[0] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[0]); + wishbone_interface_sram3_we[1] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[1]); + wishbone_interface_sram3_we[2] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[2]); + wishbone_interface_sram3_we[3] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[3]); end -assign main_sram3_adr = main_interface3_adr[8:0]; -assign main_interface3_dat_r = main_sram3_dat_r; -assign main_sram3_dat_w = main_interface3_dat_w; +assign wishbone_interface_sram3_adr = wishbone_interface_interface3_adr[8:0]; +assign wishbone_interface_interface3_dat_r = wishbone_interface_sram3_dat_r; +assign wishbone_interface_sram3_dat_w = wishbone_interface_interface3_dat_w; always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); + wishbone_interface_decoder1_slave_sel <= 2'd0; + wishbone_interface_decoder1_slave_sel[0] <= (wishbone_interface_bus_tx_adr[9] == 1'd0); + wishbone_interface_decoder1_slave_sel[1] <= (wishbone_interface_bus_tx_adr[9] == 1'd1); end -assign main_interface0_adr = main_bus_adr; -assign main_interface0_dat_w = main_bus_dat_w; -assign main_interface0_sel = main_bus_sel; -assign main_interface0_stb = main_bus_stb; -assign main_interface0_we = main_bus_we; -assign main_interface0_cti = main_bus_cti; -assign main_interface0_bte = main_bus_bte; -assign main_interface1_adr = main_bus_adr; -assign main_interface1_dat_w = main_bus_dat_w; -assign main_interface1_sel = main_bus_sel; -assign main_interface1_stb = main_bus_stb; -assign main_interface1_we = main_bus_we; -assign main_interface1_cti = main_bus_cti; -assign main_interface1_bte = main_bus_bte; -assign main_interface2_adr = main_bus_adr; -assign main_interface2_dat_w = main_bus_dat_w; -assign main_interface2_sel = main_bus_sel; -assign main_interface2_stb = main_bus_stb; -assign main_interface2_we = main_bus_we; -assign main_interface2_cti = main_bus_cti; -assign main_interface2_bte = main_bus_bte; -assign main_interface3_adr = main_bus_adr; -assign main_interface3_dat_w = main_bus_dat_w; -assign main_interface3_sel = main_bus_sel; -assign main_interface3_stb = main_bus_stb; -assign main_interface3_we = main_bus_we; -assign main_interface3_cti = main_bus_cti; -assign main_interface3_bte = main_bus_bte; -assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); -assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); -assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); -assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); -assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +assign wishbone_interface_interface2_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface2_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface2_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface2_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface2_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface2_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface2_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface3_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface3_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface3_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface3_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface3_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface3_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface3_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface2_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[0]); +assign wishbone_interface_interface3_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[1]); +assign wishbone_interface_bus_tx_ack = (wishbone_interface_interface2_ack | wishbone_interface_interface3_ack); +assign wishbone_interface_bus_tx_err = (wishbone_interface_interface2_err | wishbone_interface_interface3_err); +assign wishbone_interface_bus_tx_dat_r = (({32{wishbone_interface_decoder1_slave_sel_r[0]}} & wishbone_interface_interface2_dat_r) | ({32{wishbone_interface_decoder1_slave_sel_r[1]}} & wishbone_interface_interface3_dat_r)); always @(*) begin - builder_interface0_ack <= 1'd0; - builder_interface0_dat_r <= 32'd0; - builder_interface1_adr <= 14'd0; - builder_interface1_dat_w <= 32'd0; - builder_interface1_we <= 1'd0; - builder_next_state <= 1'd0; - builder_next_state <= builder_state; - case (builder_state) + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; + interface1_we <= 1'd0; + next_state <= 1'd0; + next_state <= state; + case (state) 1'd1: begin - builder_interface0_ack <= 1'd1; - builder_interface0_dat_r <= builder_interface1_dat_r; - builder_next_state <= 1'd0; + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + next_state <= 1'd0; end default: begin - builder_interface1_dat_w <= builder_interface0_dat_w; - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr <= builder_interface0_adr[29:0]; - builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); - builder_next_state <= 1'd1; + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + next_state <= 1'd1; end end endcase end -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); -assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_re <= 1'd0; - builder_csrbank0_reset0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= interface0_bank_bus_re; end end -assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank0_scratch0_re <= 1'd0; - builder_csrbank0_scratch0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + maccore_maccore_soc_rst <= 1'd0; + if (maccore_maccore_reset_re) begin + maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0]; end end -assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; -assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; -assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; -assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; -assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); -assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1]; +assign csrbank0_reset0_w = maccore_maccore_reset_storage; +assign csrbank0_scratch0_w = maccore_maccore_scratch_storage; +assign csrbank0_bus_errors_w = maccore_maccore_bus_errors_status; +assign maccore_maccore_bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 2'd2); +assign csrbank1_sram_writer_slot_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_re <= 1'd0; - builder_csrbank1_sram_writer_slot_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_slot_re <= 1'd0; + csrbank1_sram_writer_slot_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_sram_writer_slot_re <= interface1_bank_bus_we; + csrbank1_sram_writer_slot_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_writer_length_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_length_re <= 1'd0; + csrbank1_sram_writer_length_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_sram_writer_length_re <= interface1_bank_bus_we; + csrbank1_sram_writer_length_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_sram_writer_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_sram_writer_errors_re <= 1'd0; - builder_csrbank1_sram_writer_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_errors_re <= 1'd0; + csrbank1_sram_writer_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_sram_writer_errors_re <= interface1_bank_bus_we; + csrbank1_sram_writer_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_status_re <= 1'd0; + csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_sram_writer_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_pending_re <= 1'd0; + csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_sram_writer_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_enable0_re <= 1'd0; + csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_sram_writer_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_enable0_we <= interface1_bank_bus_re; end end -assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +assign wishbone_interface_reader_start_r = interface1_bank_bus_dat_w[0]; always @(*) begin - main_start_re <= 1'd0; - main_start_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_start_re <= builder_interface1_bank_bus_we; - main_start_we <= (~builder_interface1_bank_bus_we); + wishbone_interface_reader_start_re <= 1'd0; + wishbone_interface_reader_start_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + wishbone_interface_reader_start_re <= interface1_bank_bus_we; + wishbone_interface_reader_start_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ready_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_re <= 1'd0; - builder_csrbank1_sram_reader_ready_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ready_re <= 1'd0; + csrbank1_sram_reader_ready_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_sram_reader_ready_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ready_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +assign csrbank1_sram_reader_level_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_re <= 1'd0; - builder_csrbank1_sram_reader_level_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_level_re <= 1'd0; + csrbank1_sram_reader_level_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + csrbank1_sram_reader_level_re <= interface1_bank_bus_we; + csrbank1_sram_reader_level_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_slot0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_slot0_re <= 1'd0; + csrbank1_sram_reader_slot0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_sram_reader_slot0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_slot0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_reader_length0_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_re <= 1'd0; - builder_csrbank1_sram_reader_length0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_length0_re <= 1'd0; + csrbank1_sram_reader_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_sram_reader_length0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_length0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_status_re <= 1'd0; + csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_sram_reader_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_pending_re <= 1'd0; + csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_sram_reader_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_enable0_re <= 1'd0; + csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_sram_reader_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_enable0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_preamble_crc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_re <= 1'd0; - builder_csrbank1_preamble_crc_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + csrbank1_preamble_crc_re <= 1'd0; + csrbank1_preamble_crc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + csrbank1_preamble_crc_re <= interface1_bank_bus_we; + csrbank1_preamble_crc_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_rx_datapath_preamble_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_rx_datapath_preamble_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_preamble_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_rx_datapath_crc_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_rx_datapath_crc_errors_re <= 1'd0; + csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_rx_datapath_crc_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_crc_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; -assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; -assign main_sram11_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; -assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; -always @(*) begin - main_sram22_status <= 1'd0; - main_sram22_status <= main_sram21_available; -end -assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; -assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; -always @(*) begin - main_sram26_status <= 1'd0; - main_sram26_status <= main_sram25_available; -end -assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; -assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_sram30_available = main_sram31_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; -assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; -assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; -assign main_sram98_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; -assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; -always @(*) begin - main_sram110_status <= 1'd0; - main_sram110_status <= main_sram109_event0; -end -assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; -assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +assign csrbank1_sram_writer_slot_w = wishbone_interface_writer_slot_status; +assign wishbone_interface_writer_slot_we = csrbank1_sram_writer_slot_we; +assign csrbank1_sram_writer_length_w = wishbone_interface_writer_length_status; +assign wishbone_interface_writer_length_we = csrbank1_sram_writer_length_we; +assign csrbank1_sram_writer_errors_w = wishbone_interface_writer_errors_status; +assign wishbone_interface_writer_errors_we = csrbank1_sram_writer_errors_we; +assign wishbone_interface_writer_status_status = wishbone_interface_writer_available0; +assign csrbank1_sram_writer_ev_status_w = wishbone_interface_writer_status_status; +assign wishbone_interface_writer_status_we = csrbank1_sram_writer_ev_status_we; +assign wishbone_interface_writer_pending_status = wishbone_interface_writer_available1; +assign csrbank1_sram_writer_ev_pending_w = wishbone_interface_writer_pending_status; +assign wishbone_interface_writer_pending_we = csrbank1_sram_writer_ev_pending_we; +assign wishbone_interface_writer_available2 = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_writer_ev_enable0_w = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_reader_ready_w = wishbone_interface_reader_ready_status; +assign wishbone_interface_reader_ready_we = csrbank1_sram_reader_ready_we; +assign csrbank1_sram_reader_level_w = wishbone_interface_reader_level_status; +assign wishbone_interface_reader_level_we = csrbank1_sram_reader_level_we; +assign csrbank1_sram_reader_slot0_w = wishbone_interface_reader_slot_storage; +assign csrbank1_sram_reader_length0_w = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_status_status = wishbone_interface_reader_event00; +assign csrbank1_sram_reader_ev_status_w = wishbone_interface_reader_status_status; +assign wishbone_interface_reader_status_we = csrbank1_sram_reader_ev_status_we; +assign wishbone_interface_reader_pending_status = wishbone_interface_reader_event01; +assign csrbank1_sram_reader_ev_pending_w = wishbone_interface_reader_pending_status; +assign wishbone_interface_reader_pending_we = csrbank1_sram_reader_ev_pending_we; +assign wishbone_interface_reader_event02 = wishbone_interface_reader_enable_storage; +assign csrbank1_sram_reader_ev_enable0_w = wishbone_interface_reader_enable_storage; +assign csrbank1_preamble_crc_w = core_status; +assign core_we = csrbank1_preamble_crc_we; +assign csrbank1_rx_datapath_preamble_errors_w = core_preamble_errors_status; +assign core_preamble_errors_we = csrbank1_rx_datapath_preamble_errors_we; +assign csrbank1_rx_datapath_crc_errors_w = core_crc_errors_status; +assign core_crc_errors_we = csrbank1_rx_datapath_crc_errors_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); +assign csrbank2_crg_reset0_r = interface2_bank_bus_dat_w[0]; always @(*) begin - main_sram114_status <= 1'd0; - main_sram114_status <= main_sram113_event0; -end -assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; -assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_sram118_event0 = main_sram119_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; -assign builder_csrbank1_preamble_crc_w = main_status; -assign main_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; -assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); -assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; -always @(*) begin - builder_csrbank2_crg_reset0_re <= 1'd0; - builder_csrbank2_crg_reset0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + csrbank2_crg_reset0_re <= 1'd0; + csrbank2_crg_reset0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_crg_reset0_re <= interface2_bank_bus_we; + csrbank2_crg_reset0_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_rx_inband_status_r = builder_interface2_bank_bus_dat_w[2:0]; +assign csrbank2_rx_inband_status_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - builder_csrbank2_rx_inband_status_re <= 1'd0; - builder_csrbank2_rx_inband_status_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_rx_inband_status_re <= builder_interface2_bank_bus_we; - builder_csrbank2_rx_inband_status_we <= (~builder_interface2_bank_bus_we); + csrbank2_rx_inband_status_re <= 1'd0; + csrbank2_rx_inband_status_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_rx_inband_status_re <= interface2_bank_bus_we; + csrbank2_rx_inband_status_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +assign csrbank2_mdio_w0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_re <= 1'd0; - builder_csrbank2_mdio_w0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + csrbank2_mdio_w0_re <= 1'd0; + csrbank2_mdio_w0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_mdio_w0_re <= interface2_bank_bus_we; + csrbank2_mdio_w0_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +assign csrbank2_mdio_r_r = interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + csrbank2_mdio_r_re <= 1'd0; + csrbank2_mdio_r_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_mdio_r_re <= interface2_bank_bus_we; + csrbank2_mdio_r_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +assign csrbank2_crg_reset0_w = maccore_ethphy_reset_storage; always @(*) begin - main_maccore_ethphy_status <= 3'd0; - main_maccore_ethphy_status[0] <= main_maccore_ethphy_link_status; - main_maccore_ethphy_status[1] <= main_maccore_ethphy_clock_speed; - main_maccore_ethphy_status[2] <= main_maccore_ethphy_duplex_status; + maccore_ethphy_status <= 4'd0; + maccore_ethphy_status[0] <= maccore_ethphy_link_status; + maccore_ethphy_status[2:1] <= maccore_ethphy_clock_speed; + maccore_ethphy_status[3] <= maccore_ethphy_duplex_status; end -assign builder_csrbank2_rx_inband_status_w = main_maccore_ethphy_status[2:0]; -assign main_maccore_ethphy_we = builder_csrbank2_rx_inband_status_we; -assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; -assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; -assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; -assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_adr = builder_interface1_adr; -assign builder_we = builder_interface1_we; -assign builder_dat_w = builder_interface1_dat_w; -assign builder_interface1_dat_r = builder_dat_r; -assign builder_interface0_bank_bus_adr = builder_adr; -assign builder_interface1_bank_bus_adr = builder_adr; -assign builder_interface2_bank_bus_adr = builder_adr; -assign builder_interface0_bank_bus_we = builder_we; -assign builder_interface1_bank_bus_we = builder_we; -assign builder_interface2_bank_bus_we = builder_we; -assign builder_interface0_bank_bus_dat_w = builder_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_dat_w; -assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); -assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; -assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +assign csrbank2_rx_inband_status_w = maccore_ethphy_status; +assign maccore_ethphy_we = csrbank2_rx_inband_status_we; +assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0]; +assign maccore_ethphy_oe = maccore_ethphy__w_storage[1]; +assign maccore_ethphy_w = maccore_ethphy__w_storage[2]; +assign csrbank2_mdio_w0_w = maccore_ethphy__w_storage; +assign csrbank2_mdio_r_w = maccore_ethphy__r_status; +assign maccore_ethphy__r_we = csrbank2_mdio_r_we; +assign adr = interface1_adr; +assign re = interface1_re; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - builder_self0 <= 30'd0; - case (builder_grant) + self0 <= 30'd0; + case (grant) default: begin - builder_self0 <= main_wb_bus_adr; + self0 <= wb_bus_adr; end endcase end always @(*) begin - builder_self1 <= 32'd0; - case (builder_grant) + self1 <= 32'd0; + case (grant) default: begin - builder_self1 <= main_wb_bus_dat_w; + self1 <= wb_bus_dat_w; end endcase end always @(*) begin - builder_self2 <= 4'd0; - case (builder_grant) + self2 <= 4'd0; + case (grant) default: begin - builder_self2 <= main_wb_bus_sel; + self2 <= wb_bus_sel; end endcase end always @(*) begin - builder_self3 <= 1'd0; - case (builder_grant) + self3 <= 1'd0; + case (grant) default: begin - builder_self3 <= main_wb_bus_cyc; + self3 <= wb_bus_cyc; end endcase end always @(*) begin - builder_self4 <= 1'd0; - case (builder_grant) + self4 <= 1'd0; + case (grant) default: begin - builder_self4 <= main_wb_bus_stb; + self4 <= wb_bus_stb; end endcase end always @(*) begin - builder_self5 <= 1'd0; - case (builder_grant) + self5 <= 1'd0; + case (grant) default: begin - builder_self5 <= main_wb_bus_we; + self5 <= wb_bus_we; end endcase end always @(*) begin - builder_self6 <= 3'd0; - case (builder_grant) + self6 <= 3'd0; + case (grant) default: begin - builder_self6 <= main_wb_bus_cti; + self6 <= wb_bus_cti; end endcase end always @(*) begin - builder_self7 <= 2'd0; - case (builder_grant) + self7 <= 2'd0; + case (grant) default: begin - builder_self7 <= main_wb_bus_bte; + self7 <= wb_bus_bte; end endcase end always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_multiregimpl01; + maccore_ethphy__r_status <= 1'd0; + maccore_ethphy__r_status <= maccore_ethphy_r; + maccore_ethphy__r_status <= multiregimpl01; end -assign main_tx_cdc_cdc_produce_rdomain = builder_multiregimpl11; -assign main_tx_cdc_cdc_consume_wdomain = builder_multiregimpl21; -assign main_pulsesynchronizer0_toggle_o = builder_multiregimpl31; -assign main_pulsesynchronizer1_toggle_o = builder_multiregimpl41; -assign main_rx_cdc_cdc_produce_rdomain = builder_multiregimpl51; -assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl61; +assign core_tx_cdc_cdc_produce_rdomain = multiregimpl11; +assign core_tx_cdc_cdc_consume_wdomain = multiregimpl21; +assign core_pulsesynchronizer0_toggle_o = multiregimpl31; +assign core_pulsesynchronizer1_toggle_o = multiregimpl41; +assign core_rx_cdc_cdc_produce_rdomain = multiregimpl51; +assign core_rx_cdc_cdc_consume_wdomain = multiregimpl61; //------------------------------------------------------------------------------ @@ -3197,533 +3124,533 @@ assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl61; //------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_rx_ctl_reg <= main_maccore_ethphy_rx_ctl; - main_maccore_ethphy_rx_data_reg <= main_maccore_ethphy_rx_data; - main_maccore_ethphy_rx_ctl_reg_d <= main_maccore_ethphy_rx_ctl_reg; - main_maccore_ethphy_source_valid <= main_maccore_ethphy_rx_ctl_reg[0]; - main_maccore_ethphy_source_payload_data <= main_maccore_ethphy_rx_data_reg; - if ((main_maccore_ethphy_rx_ctl == 1'd0)) begin - main_maccore_ethphy_link_status <= main_maccore_ethphy_rx_data[0]; - main_maccore_ethphy_clock_speed <= main_maccore_ethphy_rx_data[2:1]; - main_maccore_ethphy_duplex_status <= main_maccore_ethphy_rx_data[3]; + maccore_ethphy_rx_ctl_reg <= maccore_ethphy_rx_ctl; + maccore_ethphy_rx_data_reg <= maccore_ethphy_rx_data; + maccore_ethphy_rx_ctl_reg_d <= maccore_ethphy_rx_ctl_reg; + maccore_ethphy_source_valid <= maccore_ethphy_rx_ctl_reg[0]; + maccore_ethphy_source_payload_data <= maccore_ethphy_rx_data_reg; + if ((maccore_ethphy_rx_ctl == 1'd0)) begin + maccore_ethphy_link_status <= maccore_ethphy_rx_data[0]; + maccore_ethphy_clock_speed <= maccore_ethphy_rx_data[2:1]; + maccore_ethphy_duplex_status <= maccore_ethphy_rx_data[3]; end - builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; - if (main_pulsesynchronizer0_i) begin - main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + rxdatapath_liteethmacpreamblechecker_state <= rxdatapath_liteethmacpreamblechecker_next_state; + if (core_pulsesynchronizer0_i) begin + core_pulsesynchronizer0_toggle_i <= (~core_pulsesynchronizer0_toggle_i); end - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + if (core_liteethmaccrc32checker_crc_ce) begin + core_liteethmaccrc32checker_crc_reg <= core_liteethmaccrc32checker_crc_crc_next; end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + if (core_liteethmaccrc32checker_crc_reset) begin + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((core_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_produce <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + core_liteethmaccrc32checker_syncfifo_produce <= (core_liteethmaccrc32checker_syncfifo_produce + 1'd1); end end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + if ((core_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_consume <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + core_liteethmaccrc32checker_syncfifo_consume <= (core_liteethmaccrc32checker_syncfifo_consume + 1'd1); end end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~core_liteethmaccrc32checker_syncfifo_do_read)) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level + 1'd1); end end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level - 1'd1); end end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + if (core_liteethmaccrc32checker_fifo_reset) begin + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; end - builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; - if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin - main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + rxdatapath_bufferizeendpoints_state <= rxdatapath_bufferizeendpoints_next_state; + if (core_liteethmaccrc32checker_last_be_next_value_ce0) begin + core_liteethmaccrc32checker_last_be <= core_liteethmaccrc32checker_last_be_next_value0; end - if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin - main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + if (core_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + core_liteethmaccrc32checker_crc_error1 <= core_liteethmaccrc32checker_crc_error1_next_value1; end - if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin - main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; - main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; - main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; - main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; - main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + if (((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready)) begin + core_bufferizeendpoints_pipe_valid_source_valid <= core_bufferizeendpoints_pipe_valid_sink_valid; + core_bufferizeendpoints_pipe_valid_source_first <= core_bufferizeendpoints_pipe_valid_sink_first; + core_bufferizeendpoints_pipe_valid_source_last <= core_bufferizeendpoints_pipe_valid_sink_last; + core_bufferizeendpoints_pipe_valid_source_payload_data <= core_bufferizeendpoints_pipe_valid_sink_payload_data; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= core_bufferizeendpoints_pipe_valid_sink_payload_last_be; + core_bufferizeendpoints_pipe_valid_source_payload_error <= core_bufferizeendpoints_pipe_valid_sink_payload_error; end - if (main_pulsesynchronizer1_i) begin - main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + if (core_pulsesynchronizer1_i) begin + core_pulsesynchronizer1_toggle_i <= (~core_pulsesynchronizer1_toggle_i); end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; + if (core_rx_converter_converter_source_ready) begin + core_rx_converter_converter_strobe_all <= 1'd0; end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; + if (core_rx_converter_converter_load_part) begin + if (((core_rx_converter_converter_demux == 2'd3) | core_rx_converter_converter_sink_last)) begin + core_rx_converter_converter_demux <= 1'd0; + core_rx_converter_converter_strobe_all <= 1'd1; end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + core_rx_converter_converter_demux <= (core_rx_converter_converter_demux + 1'd1); end end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + if ((core_rx_converter_converter_source_valid & core_rx_converter_converter_source_ready)) begin + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= core_rx_converter_converter_sink_first; + core_rx_converter_converter_source_last <= core_rx_converter_converter_sink_last; end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; + core_rx_converter_converter_source_first <= 1'd0; + core_rx_converter_converter_source_last <= 1'd0; end end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= (core_rx_converter_converter_sink_first | core_rx_converter_converter_source_first); + core_rx_converter_converter_source_last <= (core_rx_converter_converter_sink_last | core_rx_converter_converter_source_last); end end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) + if (core_rx_converter_converter_load_part) begin + case (core_rx_converter_converter_demux) 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[9:0] <= core_rx_converter_converter_sink_payload_data; end 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[19:10] <= core_rx_converter_converter_sink_payload_data; end 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[29:20] <= core_rx_converter_converter_sink_payload_data; end 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[39:30] <= core_rx_converter_converter_sink_payload_data; end endcase end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + if (core_rx_converter_converter_load_part) begin + core_rx_converter_converter_source_payload_valid_token_count <= (core_rx_converter_converter_demux + 1'd1); end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + core_rx_cdc_cdc_graycounter0_q_binary <= core_rx_cdc_cdc_graycounter0_q_next_binary; + core_rx_cdc_cdc_graycounter0_q <= core_rx_cdc_cdc_graycounter0_q_next; if (eth_rx_rst) begin - main_maccore_ethphy_source_valid <= 1'd0; - main_maccore_ethphy_source_payload_data <= 8'd0; - main_maccore_ethphy_link_status <= 1'd0; - main_maccore_ethphy_clock_speed <= 1'd0; - main_maccore_ethphy_duplex_status <= 1'd0; - main_maccore_ethphy_rx_ctl_reg <= 2'd0; - main_maccore_ethphy_rx_data_reg <= 8'd0; - main_maccore_ethphy_rx_ctl_reg_d <= 2'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_liteethmaccrc32checker_last_be <= 1'd0; - main_liteethmaccrc32checker_crc_error1 <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; - builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + maccore_ethphy_source_valid <= 1'd0; + maccore_ethphy_source_payload_data <= 8'd0; + maccore_ethphy_link_status <= 1'd0; + maccore_ethphy_clock_speed <= 2'd0; + maccore_ethphy_duplex_status <= 1'd0; + maccore_ethphy_rx_ctl_reg <= 2'd0; + maccore_ethphy_rx_data_reg <= 8'd0; + maccore_ethphy_rx_ctl_reg_d <= 2'd0; + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + core_liteethmaccrc32checker_last_be <= 1'd0; + core_liteethmaccrc32checker_crc_error1 <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + core_rx_converter_converter_source_payload_data <= 40'd0; + core_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + core_rx_converter_converter_demux <= 2'd0; + core_rx_converter_converter_strobe_all <= 1'd0; + core_rx_cdc_cdc_graycounter0_q <= 6'd0; + core_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + rxdatapath_bufferizeendpoints_state <= 2'd0; end - builder_multiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; - builder_multiregimpl61 <= builder_multiregimpl60; + multiregimpl60 <= core_rx_cdc_cdc_graycounter1_q; + multiregimpl61 <= multiregimpl60; end always @(posedge eth_tx_clk) begin - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= core_tx_cdc_cdc_graycounter1_q_next_binary; + core_tx_cdc_cdc_graycounter1_q <= core_tx_cdc_cdc_graycounter1_q_next; + if ((core_tx_converter_converter_source_valid & core_tx_converter_converter_source_ready)) begin + if (core_tx_converter_converter_last) begin + core_tx_converter_converter_mux <= 1'd0; end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + core_tx_converter_converter_mux <= (core_tx_converter_converter_mux + 1'd1); end end - builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; - builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; - if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin - main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + txdatapath_liteethmactxlastbe_state <= txdatapath_liteethmactxlastbe_next_state; + txdatapath_liteethmacpaddinginserter_state <= txdatapath_liteethmacpaddinginserter_next_state; + if (core_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + core_tx_padding_counter <= core_tx_padding_counter_clockdomainsrenamer0_next_value; end - if (main_tx_crc_is_ongoing0) begin - main_tx_crc_cnt <= 2'd3; + if (core_tx_crc_is_ongoing0) begin + core_tx_crc_cnt <= 2'd3; end else begin - if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin - main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + if ((core_tx_crc_is_ongoing1 & (~core_tx_crc_cnt_done))) begin + core_tx_crc_cnt <= (core_tx_crc_cnt - core_tx_crc_source_ready); end end - if (main_tx_crc_ce) begin - main_tx_crc_reg <= main_tx_crc_crc_next; + if (core_tx_crc_ce) begin + core_tx_crc_reg <= core_tx_crc_crc_next; end - if (main_tx_crc_reset) begin - main_tx_crc_reg <= 32'd4294967295; + if (core_tx_crc_reset) begin + core_tx_crc_reg <= 32'd4294967295; end - builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; - if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin - main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + txdatapath_bufferizeendpoints_state <= txdatapath_bufferizeendpoints_next_state; + if (core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + core_tx_crc_crc_packet <= core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; end - if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin - main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + if (core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + core_tx_crc_last_be <= core_tx_crc_last_be_clockdomainsrenamer1_next_value1; end - if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin - main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; - main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; - main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; - main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; - main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; - main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + if (((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready)) begin + core_tx_crc_pipe_valid_source_valid <= core_tx_crc_pipe_valid_sink_valid; + core_tx_crc_pipe_valid_source_first <= core_tx_crc_pipe_valid_sink_first; + core_tx_crc_pipe_valid_source_last <= core_tx_crc_pipe_valid_sink_last; + core_tx_crc_pipe_valid_source_payload_data <= core_tx_crc_pipe_valid_sink_payload_data; + core_tx_crc_pipe_valid_source_payload_last_be <= core_tx_crc_pipe_valid_sink_payload_last_be; + core_tx_crc_pipe_valid_source_payload_error <= core_tx_crc_pipe_valid_sink_payload_error; end - builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; - if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin - main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + txdatapath_liteethmacpreambleinserter_state <= txdatapath_liteethmacpreambleinserter_next_state; + if (core_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + core_tx_preamble_count <= core_tx_preamble_count_clockdomainsrenamer2_next_value; end - builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; - if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin - main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + txdatapath_liteethmacgap_state <= txdatapath_liteethmacgap_next_state; + if (core_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + core_tx_gap_counter <= core_tx_gap_counter_clockdomainsrenamer3_next_value; end if (eth_tx_rst) begin - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_padding_counter <= 16'd0; - main_tx_crc_crc_packet <= 32'd0; - main_tx_crc_last_be <= 1'd0; - main_tx_crc_reg <= 32'd4294967295; - main_tx_crc_cnt <= 2'd3; - main_tx_crc_pipe_valid_source_valid <= 1'd0; - main_tx_crc_pipe_valid_source_payload_data <= 8'd0; - main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; - main_tx_crc_pipe_valid_source_payload_error <= 1'd0; - builder_txdatapath_liteethmactxlastbe_state <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; - builder_txdatapath_bufferizeendpoints_state <= 2'd0; - builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; - builder_txdatapath_liteethmacgap_state <= 1'd0; + core_tx_cdc_cdc_graycounter1_q <= 6'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + core_tx_converter_converter_mux <= 2'd0; + core_tx_padding_counter <= 16'd0; + core_tx_crc_reg <= 32'd4294967295; + core_tx_crc_cnt <= 2'd3; + core_tx_crc_pipe_valid_source_valid <= 1'd0; + core_tx_crc_pipe_valid_source_payload_data <= 8'd0; + core_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + core_tx_crc_pipe_valid_source_payload_error <= 1'd0; + txdatapath_liteethmactxlastbe_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_state <= 1'd0; + txdatapath_bufferizeendpoints_state <= 2'd0; + txdatapath_liteethmacpreambleinserter_state <= 2'd0; + txdatapath_liteethmacgap_state <= 1'd0; end - builder_multiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; - builder_multiregimpl11 <= builder_multiregimpl10; + multiregimpl10 <= core_tx_cdc_cdc_graycounter0_q; + multiregimpl11 <= multiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); end end else begin - builder_count <= 20'd1000000; + count <= 20'd1000000; end - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + if ((maccore_maccore_bus_errors != 32'd4294967295)) begin + if (maccore_maccore_bus_error) begin + maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1); end end - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - if (main_pulsesynchronizer0_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + core_tx_cdc_cdc_graycounter0_q_binary <= core_tx_cdc_cdc_graycounter0_q_next_binary; + core_tx_cdc_cdc_graycounter0_q <= core_tx_cdc_cdc_graycounter0_q_next; + if (core_pulsesynchronizer0_o) begin + core_preamble_errors_status <= (core_preamble_errors_status + 1'd1); end - if (main_pulsesynchronizer1_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); + if (core_pulsesynchronizer1_o) begin + core_crc_errors_status <= (core_crc_errors_status + 1'd1); end - main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; - main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - main_sram57_produce <= (main_sram57_produce + 1'd1); + core_pulsesynchronizer0_toggle_o_r <= core_pulsesynchronizer0_toggle_o; + core_pulsesynchronizer1_toggle_o_r <= core_pulsesynchronizer1_toggle_o; + core_rx_cdc_cdc_graycounter1_q_binary <= core_rx_cdc_cdc_graycounter1_q_next_binary; + core_rx_cdc_cdc_graycounter1_q <= core_rx_cdc_cdc_graycounter1_q_next; + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + wishbone_interface_writer_stat_fifo_produce <= (wishbone_interface_writer_stat_fifo_produce + 1'd1); end - if (main_sram63_do_read) begin - main_sram58_consume <= (main_sram58_consume + 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_consume <= (wishbone_interface_writer_stat_fifo_consume + 1'd1); end - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - if ((~main_sram63_do_read)) begin - main_sram55_level <= (main_sram55_level + 1'd1); + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + if ((~wishbone_interface_writer_stat_fifo_do_read)) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level + 1'd1); end end else begin - if (main_sram63_do_read) begin - main_sram55_level <= (main_sram55_level - 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level - 1'd1); end end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin - main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + liteethmacsramwriter_state <= liteethmacsramwriter_next_state; + if (wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce) begin + wishbone_interface_writer_length <= wishbone_interface_writer_length_liteethmacsramwriter_t_next_value; end - if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin - main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + if (wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce) begin + wishbone_interface_writer_errors_status <= wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value; end - if (main_slot_liteethmacsramwriter_next_value_ce) begin - main_slot <= main_slot_liteethmacsramwriter_next_value; + if (wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce) begin + wishbone_interface_writer_slot <= wishbone_interface_writer_slot_liteethmacsramwriter_next_value; end - if (main_sram108_clear) begin - main_sram106_pending <= 1'd0; + if (wishbone_interface_reader_eventsourcepulse_clear) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; end - if (main_sram107_trigger) begin - main_sram106_pending <= 1'd1; + if (wishbone_interface_reader_eventsourcepulse_trigger) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd1; end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - main_sram143_produce <= (main_sram143_produce + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + wishbone_interface_reader_cmd_fifo_produce <= (wishbone_interface_reader_cmd_fifo_produce + 1'd1); end - if (main_sram149_do_read) begin - main_sram144_consume <= (main_sram144_consume + 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_consume <= (wishbone_interface_reader_cmd_fifo_consume + 1'd1); end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - if ((~main_sram149_do_read)) begin - main_sram141_level <= (main_sram141_level + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + if ((~wishbone_interface_reader_cmd_fifo_do_read)) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level + 1'd1); end end else begin - if (main_sram149_do_read) begin - main_sram141_level <= (main_sram141_level - 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level - 1'd1); end end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_sram122_length_liteethmacsramreader_next_value_ce) begin - main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + liteethmacsramreader_state <= liteethmacsramreader_next_state; + if (wishbone_interface_reader_length_liteethmacsramreader_next_value_ce) begin + wishbone_interface_reader_length <= wishbone_interface_reader_length_liteethmacsramreader_next_value; end - main_interface0_ack <= 1'd0; - if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin - main_interface0_ack <= 1'd1; + wishbone_interface_interface0_ack <= 1'd0; + if (((wishbone_interface_interface0_cyc & wishbone_interface_interface0_stb) & ((~wishbone_interface_interface0_ack) | wishbone_interface_sram0_adr_burst))) begin + wishbone_interface_interface0_ack <= 1'd1; end - main_interface1_ack <= 1'd0; - if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin - main_interface1_ack <= 1'd1; + wishbone_interface_interface1_ack <= 1'd0; + if (((wishbone_interface_interface1_cyc & wishbone_interface_interface1_stb) & ((~wishbone_interface_interface1_ack) | wishbone_interface_sram1_adr_burst))) begin + wishbone_interface_interface1_ack <= 1'd1; end - main_interface2_ack <= 1'd0; - if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin - main_interface2_ack <= 1'd1; + wishbone_interface_decoder0_slave_sel_r <= wishbone_interface_decoder0_slave_sel; + wishbone_interface_interface2_ack <= 1'd0; + if (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & ((~wishbone_interface_interface2_ack) | wishbone_interface_sram2_adr_burst))) begin + wishbone_interface_interface2_ack <= 1'd1; end - main_interface3_ack <= 1'd0; - if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin - main_interface3_ack <= 1'd1; + wishbone_interface_interface3_ack <= 1'd0; + if (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & ((~wishbone_interface_interface3_ack) | wishbone_interface_sram3_adr_burst))) begin + wishbone_interface_interface3_ack <= 1'd1; end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) + wishbone_interface_decoder1_slave_sel_r <= wishbone_interface_decoder1_slave_sel; + state <= next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + interface0_bank_bus_dat_r <= csrbank0_reset0_w; end 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; end 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; end endcase end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + if (csrbank0_reset0_re) begin + maccore_maccore_reset_storage <= csrbank0_reset0_r; end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + maccore_maccore_reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + maccore_maccore_scratch_storage <= csrbank0_scratch0_r; end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) + maccore_maccore_scratch_re <= csrbank0_scratch0_re; + maccore_maccore_bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_slot_w; end 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_length_w; end 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_errors_w; end 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_status_w; end 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_pending_w; end 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_enable0_w; end 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_start_w; + interface1_bank_bus_dat_r <= wishbone_interface_reader_start_w; end 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ready_w; end 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_level_w; end 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_slot0_w; end 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_length0_w; end 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_status_w; end 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_pending_w; end 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_enable0_w; end 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + interface1_bank_bus_dat_r <= csrbank1_preamble_crc_w; end 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_preamble_errors_w; end 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_crc_errors_w; end endcase end - main_sram9_re <= builder_csrbank1_sram_writer_slot_re; - main_sram12_re <= builder_csrbank1_sram_writer_length_re; - main_sram15_re <= builder_csrbank1_sram_writer_errors_re; - main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + wishbone_interface_writer_slot_re <= csrbank1_sram_writer_slot_re; + wishbone_interface_writer_length_re <= csrbank1_sram_writer_length_re; + wishbone_interface_writer_errors_re <= csrbank1_sram_writer_errors_re; + wishbone_interface_writer_status_re <= csrbank1_sram_writer_ev_status_re; + if (csrbank1_sram_writer_ev_pending_re) begin + wishbone_interface_writer_pending_r <= csrbank1_sram_writer_ev_pending_r; end - main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + wishbone_interface_writer_pending_re <= csrbank1_sram_writer_ev_pending_re; + if (csrbank1_sram_writer_ev_enable0_re) begin + wishbone_interface_writer_enable_storage <= csrbank1_sram_writer_ev_enable0_r; end - main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_sram96_re <= builder_csrbank1_sram_reader_ready_re; - main_sram99_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + wishbone_interface_writer_enable_re <= csrbank1_sram_writer_ev_enable0_re; + wishbone_interface_reader_ready_re <= csrbank1_sram_reader_ready_re; + wishbone_interface_reader_level_re <= csrbank1_sram_reader_level_re; + if (csrbank1_sram_reader_slot0_re) begin + wishbone_interface_reader_slot_storage <= csrbank1_sram_reader_slot0_r; end - main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + wishbone_interface_reader_slot_re <= csrbank1_sram_reader_slot0_re; + if (csrbank1_sram_reader_length0_re) begin + wishbone_interface_reader_length_storage <= csrbank1_sram_reader_length0_r; end - main_sram103_re <= builder_csrbank1_sram_reader_length0_re; - main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + wishbone_interface_reader_length_re <= csrbank1_sram_reader_length0_re; + wishbone_interface_reader_status_re <= csrbank1_sram_reader_ev_status_re; + if (csrbank1_sram_reader_ev_pending_re) begin + wishbone_interface_reader_pending_r <= csrbank1_sram_reader_ev_pending_r; end - main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + wishbone_interface_reader_pending_re <= csrbank1_sram_reader_ev_pending_re; + if (csrbank1_sram_reader_ev_enable0_re) begin + wishbone_interface_reader_enable_storage <= csrbank1_sram_reader_ev_enable0_r; end - main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) + wishbone_interface_reader_enable_re <= csrbank1_sram_reader_ev_enable0_re; + core_re <= csrbank1_preamble_crc_re; + core_preamble_errors_re <= csrbank1_rx_datapath_preamble_errors_re; + core_crc_errors_re <= csrbank1_rx_datapath_crc_errors_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + interface2_bank_bus_dat_r <= csrbank2_crg_reset0_w; end 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_rx_inband_status_w; + interface2_bank_bus_dat_r <= csrbank2_rx_inband_status_w; end 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_w0_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_r_w; end endcase end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + if (csrbank2_crg_reset0_re) begin + maccore_ethphy_reset_storage <= csrbank2_crg_reset0_r; end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - main_maccore_ethphy_re <= builder_csrbank2_rx_inband_status_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + maccore_ethphy_reset_re <= csrbank2_crg_reset0_re; + maccore_ethphy_re <= csrbank2_rx_inband_status_re; + if (csrbank2_mdio_w0_re) begin + maccore_ethphy__w_storage <= csrbank2_mdio_w0_r; end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + maccore_ethphy__w_re <= csrbank2_mdio_w0_re; + maccore_ethphy__r_re <= csrbank2_mdio_r_re; if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy_re <= 1'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_sram9_re <= 1'd0; - main_sram12_re <= 1'd0; - main_sram13_status <= 32'd0; - main_sram15_re <= 1'd0; - main_sram24_re <= 1'd0; - main_sram28_re <= 1'd0; - main_sram29_r <= 1'd0; - main_sram31_storage <= 1'd0; - main_sram32_re <= 1'd0; - main_slot <= 1'd0; - main_sram35_length <= 11'd0; - main_sram55_level <= 2'd0; - main_sram57_produce <= 1'd0; - main_sram58_consume <= 1'd0; - main_sram96_re <= 1'd0; - main_sram99_re <= 1'd0; - main_sram101_re <= 1'd0; - main_sram103_re <= 1'd0; - main_sram106_pending <= 1'd0; - main_sram112_re <= 1'd0; - main_sram116_re <= 1'd0; - main_sram117_r <= 1'd0; - main_sram119_storage <= 1'd0; - main_sram120_re <= 1'd0; - main_sram122_length <= 11'd0; - main_sram141_level <= 2'd0; - main_sram143_produce <= 1'd0; - main_sram144_consume <= 1'd0; - main_interface0_ack <= 1'd0; - main_interface1_ack <= 1'd0; - main_interface2_ack <= 1'd0; - main_interface3_ack <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_state <= 1'd0; + maccore_maccore_reset_storage <= 2'd0; + maccore_maccore_reset_re <= 1'd0; + maccore_maccore_scratch_storage <= 32'd305419896; + maccore_maccore_scratch_re <= 1'd0; + maccore_maccore_bus_errors_re <= 1'd0; + maccore_maccore_bus_errors <= 32'd0; + maccore_ethphy_reset_storage <= 1'd0; + maccore_ethphy_reset_re <= 1'd0; + maccore_ethphy_re <= 1'd0; + maccore_ethphy__w_storage <= 3'd0; + maccore_ethphy__w_re <= 1'd0; + maccore_ethphy__r_re <= 1'd0; + core_re <= 1'd0; + core_tx_cdc_cdc_graycounter0_q <= 6'd0; + core_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + core_preamble_errors_status <= 32'd0; + core_preamble_errors_re <= 1'd0; + core_crc_errors_status <= 32'd0; + core_crc_errors_re <= 1'd0; + core_rx_cdc_cdc_graycounter1_q <= 6'd0; + core_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + wishbone_interface_writer_slot_re <= 1'd0; + wishbone_interface_writer_length_re <= 1'd0; + wishbone_interface_writer_errors_status <= 32'd0; + wishbone_interface_writer_errors_re <= 1'd0; + wishbone_interface_writer_status_re <= 1'd0; + wishbone_interface_writer_pending_re <= 1'd0; + wishbone_interface_writer_pending_r <= 1'd0; + wishbone_interface_writer_enable_storage <= 1'd0; + wishbone_interface_writer_enable_re <= 1'd0; + wishbone_interface_writer_slot <= 1'd0; + wishbone_interface_writer_length <= 11'd0; + wishbone_interface_writer_stat_fifo_level <= 2'd0; + wishbone_interface_writer_stat_fifo_produce <= 1'd0; + wishbone_interface_writer_stat_fifo_consume <= 1'd0; + wishbone_interface_reader_ready_re <= 1'd0; + wishbone_interface_reader_level_re <= 1'd0; + wishbone_interface_reader_slot_re <= 1'd0; + wishbone_interface_reader_length_re <= 1'd0; + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; + wishbone_interface_reader_status_re <= 1'd0; + wishbone_interface_reader_pending_re <= 1'd0; + wishbone_interface_reader_pending_r <= 1'd0; + wishbone_interface_reader_enable_storage <= 1'd0; + wishbone_interface_reader_enable_re <= 1'd0; + wishbone_interface_reader_length <= 11'd0; + wishbone_interface_reader_cmd_fifo_level <= 2'd0; + wishbone_interface_reader_cmd_fifo_produce <= 1'd0; + wishbone_interface_reader_cmd_fifo_consume <= 1'd0; + wishbone_interface_interface0_ack <= 1'd0; + wishbone_interface_interface1_ack <= 1'd0; + wishbone_interface_decoder0_slave_sel_r <= 2'd0; + wishbone_interface_interface2_ack <= 1'd0; + wishbone_interface_interface3_ack <= 1'd0; + wishbone_interface_decoder1_slave_sel_r <= 2'd0; + slave_sel_r <= 3'd0; + count <= 20'd1000000; + liteethmacsramwriter_state <= 3'd0; + liteethmacsramreader_state <= 2'd0; + state <= 1'd0; end - builder_multiregimpl00 <= main_maccore_ethphy_data_r; - builder_multiregimpl01 <= builder_multiregimpl00; - builder_multiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; - builder_multiregimpl21 <= builder_multiregimpl20; - builder_multiregimpl30 <= main_pulsesynchronizer0_toggle_i; - builder_multiregimpl31 <= builder_multiregimpl30; - builder_multiregimpl40 <= main_pulsesynchronizer1_toggle_i; - builder_multiregimpl41 <= builder_multiregimpl40; - builder_multiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; - builder_multiregimpl51 <= builder_multiregimpl50; + multiregimpl00 <= maccore_ethphy_data_r; + multiregimpl01 <= multiregimpl00; + multiregimpl20 <= core_tx_cdc_cdc_graycounter1_q; + multiregimpl21 <= multiregimpl20; + multiregimpl30 <= core_pulsesynchronizer0_toggle_i; + multiregimpl31 <= multiregimpl30; + multiregimpl40 <= core_pulsesynchronizer1_toggle_i; + multiregimpl41 <= multiregimpl40; + multiregimpl50 <= core_rx_cdc_cdc_graycounter0_q; + multiregimpl51 <= multiregimpl50; end @@ -3740,7 +3667,7 @@ DELAYG #( .DEL_VALUE (7'd80) ) DELAYG ( // Inputs. - .A (main_maccore_ethphy_eth_tx_clk_o), + .A (maccore_ethphy_eth_tx_clk_o), // Outputs. .Z (rgmii_clocks_tx) @@ -3755,7 +3682,7 @@ DELAYG #( .DEL_VALUE (1'd0) ) DELAYG_1 ( // Inputs. - .A (main_maccore_ethphy_tx_ctl_oddrx1f), + .A (maccore_ethphy_tx_ctl_oddrx1f), // Outputs. .Z (rgmii_tx_ctl) @@ -3770,7 +3697,7 @@ DELAYG #( .DEL_VALUE (1'd0) ) DELAYG_2 ( // Inputs. - .A (main_maccore_ethphy_tx_data_oddrx1f[0]), + .A (maccore_ethphy_tx_data_oddrx1f[0]), // Outputs. .Z (rgmii_tx_data[0]) @@ -3785,7 +3712,7 @@ DELAYG #( .DEL_VALUE (1'd0) ) DELAYG_3 ( // Inputs. - .A (main_maccore_ethphy_tx_data_oddrx1f[1]), + .A (maccore_ethphy_tx_data_oddrx1f[1]), // Outputs. .Z (rgmii_tx_data[1]) @@ -3800,7 +3727,7 @@ DELAYG #( .DEL_VALUE (1'd0) ) DELAYG_4 ( // Inputs. - .A (main_maccore_ethphy_tx_data_oddrx1f[2]), + .A (maccore_ethphy_tx_data_oddrx1f[2]), // Outputs. .Z (rgmii_tx_data[2]) @@ -3815,7 +3742,7 @@ DELAYG #( .DEL_VALUE (1'd0) ) DELAYG_5 ( // Inputs. - .A (main_maccore_ethphy_tx_data_oddrx1f[3]), + .A (maccore_ethphy_tx_data_oddrx1f[3]), // Outputs. .Z (rgmii_tx_data[3]) @@ -3833,7 +3760,7 @@ DELAYG #( .A (rgmii_rx_ctl), // Outputs. - .Z (main_maccore_ethphy_rx_ctl_delayf) + .Z (maccore_ethphy_rx_ctl_delayf) ); //------------------------------------------------------------------------------ @@ -3848,7 +3775,7 @@ DELAYG #( .A (rgmii_rx_data[0]), // Outputs. - .Z (main_maccore_ethphy_rx_data_delayf[0]) + .Z (maccore_ethphy_rx_data_delayf[0]) ); //------------------------------------------------------------------------------ @@ -3863,7 +3790,7 @@ DELAYG #( .A (rgmii_rx_data[1]), // Outputs. - .Z (main_maccore_ethphy_rx_data_delayf[1]) + .Z (maccore_ethphy_rx_data_delayf[1]) ); //------------------------------------------------------------------------------ @@ -3878,7 +3805,7 @@ DELAYG #( .A (rgmii_rx_data[2]), // Outputs. - .Z (main_maccore_ethphy_rx_data_delayf[2]) + .Z (maccore_ethphy_rx_data_delayf[2]) ); //------------------------------------------------------------------------------ @@ -3893,12 +3820,9 @@ DELAYG #( .A (rgmii_rx_data[3]), // Outputs. - .Z (main_maccore_ethphy_rx_data_delayf[3]) + .Z (maccore_ethphy_rx_data_delayf[3]) ); -assign rgmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = rgmii_mdio; - //------------------------------------------------------------------------------ // Memory storage: 32-words x 42-bit //------------------------------------------------------------------------------ @@ -3908,15 +3832,15 @@ reg [41:0] storage[0:31]; reg [41:0] storage_dat0; reg [41:0] storage_dat1; always @(posedge sys_clk) begin - if (main_tx_cdc_cdc_wrport_we) - storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; + if (core_tx_cdc_cdc_wrport_we) + storage[core_tx_cdc_cdc_wrport_adr] <= core_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[core_tx_cdc_cdc_wrport_adr]; end always @(posedge eth_tx_clk) begin - storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; + storage_dat1 <= storage[core_tx_cdc_cdc_rdport_adr]; end -assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; -assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; +assign core_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign core_tx_cdc_cdc_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ @@ -3927,14 +3851,14 @@ assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; reg [11:0] storage_1[0:4]; reg [11:0] storage_1_dat0; always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; + if (core_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr] <= core_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr]; end always @(posedge eth_rx_clk) begin end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign core_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[core_liteethmaccrc32checker_syncfifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -3946,15 +3870,15 @@ reg [41:0] storage_2[0:31]; reg [41:0] storage_2_dat0; reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin - if (main_rx_cdc_cdc_wrport_we) - storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; + if (core_rx_cdc_cdc_wrport_we) + storage_2[core_rx_cdc_cdc_wrport_adr] <= core_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[core_rx_cdc_cdc_wrport_adr]; end always @(posedge sys_clk) begin - storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; + storage_2_dat1 <= storage_2[core_rx_cdc_cdc_rdport_adr]; end -assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; +assign core_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign core_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; //------------------------------------------------------------------------------ @@ -3965,14 +3889,14 @@ assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; reg [13:0] storage_3[0:1]; reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_sram61_we) - storage_3[main_sram59_adr] <= main_sram62_dat_w; - storage_3_dat0 <= storage_3[main_sram59_adr]; + if (wishbone_interface_writer_stat_fifo_wrport_we) + storage_3[wishbone_interface_writer_stat_fifo_wrport_adr] <= wishbone_interface_writer_stat_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[wishbone_interface_writer_stat_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram60_dat_r = storage_3_dat0; -assign main_sram65_dat_r = storage_3[main_sram64_adr]; +assign wishbone_interface_writer_stat_fifo_wrport_dat_r = storage_3_dat0; +assign wishbone_interface_writer_stat_fifo_rdport_dat_r = storage_3[wishbone_interface_writer_stat_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -3984,15 +3908,15 @@ reg [31:0] mem[0:382]; reg [8:0] mem_adr0; reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_sram77_we) - mem[main_sram75_adr] <= main_sram78_dat_w; - mem_adr0 <= main_sram75_adr; + if (wishbone_interface_writer_memory0_we) + mem[wishbone_interface_writer_memory0_adr] <= wishbone_interface_writer_memory0_dat_w; + mem_adr0 <= wishbone_interface_writer_memory0_adr; end always @(posedge sys_clk) begin - mem_dat1 <= mem[main_sram0_adr]; + mem_dat1 <= mem[wishbone_interface_sram0_adr]; end -assign main_sram76_dat_r = mem[mem_adr0]; -assign main_sram0_dat_r = mem_dat1; +assign wishbone_interface_writer_memory0_dat_r = mem[mem_adr0]; +assign wishbone_interface_sram0_dat_r = mem_dat1; //------------------------------------------------------------------------------ @@ -4004,15 +3928,15 @@ reg [31:0] mem_1[0:382]; reg [8:0] mem_1_adr0; reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_sram81_we) - mem_1[main_sram79_adr] <= main_sram82_dat_w; - mem_1_adr0 <= main_sram79_adr; + if (wishbone_interface_writer_memory1_we) + mem_1[wishbone_interface_writer_memory1_adr] <= wishbone_interface_writer_memory1_dat_w; + mem_1_adr0 <= wishbone_interface_writer_memory1_adr; end always @(posedge sys_clk) begin - mem_1_dat1 <= mem_1[main_sram1_adr]; + mem_1_dat1 <= mem_1[wishbone_interface_sram1_adr]; end -assign main_sram80_dat_r = mem_1[mem_1_adr0]; -assign main_sram1_dat_r = mem_1_dat1; +assign wishbone_interface_writer_memory1_dat_r = mem_1[mem_1_adr0]; +assign wishbone_interface_sram1_dat_r = mem_1_dat1; //------------------------------------------------------------------------------ @@ -4023,14 +3947,14 @@ assign main_sram1_dat_r = mem_1_dat1; reg [13:0] storage_4[0:1]; reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_sram147_we) - storage_4[main_sram145_adr] <= main_sram148_dat_w; - storage_4_dat0 <= storage_4[main_sram145_adr]; + if (wishbone_interface_reader_cmd_fifo_wrport_we) + storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr] <= wishbone_interface_reader_cmd_fifo_wrport_dat_w; + storage_4_dat0 <= storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram146_dat_r = storage_4_dat0; -assign main_sram151_dat_r = storage_4[main_sram150_adr]; +assign wishbone_interface_reader_cmd_fifo_wrport_dat_r = storage_4_dat0; +assign wishbone_interface_reader_cmd_fifo_rdport_dat_r = storage_4[wishbone_interface_reader_cmd_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4042,22 +3966,22 @@ reg [31:0] mem_2[0:382]; reg [31:0] mem_2_dat0; reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - if (main_sram163_re) - mem_2_dat0 <= mem_2[main_sram161_adr]; + if (wishbone_interface_reader_memory0_re) + mem_2_dat0 <= mem_2[wishbone_interface_reader_memory0_adr]; end always @(posedge sys_clk) begin - if (main_sram2_we[0]) - mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; - if (main_sram2_we[1]) - mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; - if (main_sram2_we[2]) - mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; - if (main_sram2_we[3]) - mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; - mem_2_adr1 <= main_sram2_adr; + if (wishbone_interface_sram2_we[0]) + mem_2[wishbone_interface_sram2_adr][7:0] <= wishbone_interface_sram2_dat_w[7:0]; + if (wishbone_interface_sram2_we[1]) + mem_2[wishbone_interface_sram2_adr][15:8] <= wishbone_interface_sram2_dat_w[15:8]; + if (wishbone_interface_sram2_we[2]) + mem_2[wishbone_interface_sram2_adr][23:16] <= wishbone_interface_sram2_dat_w[23:16]; + if (wishbone_interface_sram2_we[3]) + mem_2[wishbone_interface_sram2_adr][31:24] <= wishbone_interface_sram2_dat_w[31:24]; + mem_2_adr1 <= wishbone_interface_sram2_adr; end -assign main_sram162_dat_r = mem_2_dat0; -assign main_sram2_dat_r = mem_2[mem_2_adr1]; +assign wishbone_interface_reader_memory0_dat_r = mem_2_dat0; +assign wishbone_interface_sram2_dat_r = mem_2[mem_2_adr1]; //------------------------------------------------------------------------------ @@ -4069,22 +3993,22 @@ reg [31:0] mem_3[0:382]; reg [31:0] mem_3_dat0; reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - if (main_sram166_re) - mem_3_dat0 <= mem_3[main_sram164_adr]; + if (wishbone_interface_reader_memory1_re) + mem_3_dat0 <= mem_3[wishbone_interface_reader_memory1_adr]; end always @(posedge sys_clk) begin - if (main_sram3_we[0]) - mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; - if (main_sram3_we[1]) - mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; - if (main_sram3_we[2]) - mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; - if (main_sram3_we[3]) - mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; - mem_3_adr1 <= main_sram3_adr; + if (wishbone_interface_sram3_we[0]) + mem_3[wishbone_interface_sram3_adr][7:0] <= wishbone_interface_sram3_dat_w[7:0]; + if (wishbone_interface_sram3_we[1]) + mem_3[wishbone_interface_sram3_adr][15:8] <= wishbone_interface_sram3_dat_w[15:8]; + if (wishbone_interface_sram3_we[2]) + mem_3[wishbone_interface_sram3_adr][23:16] <= wishbone_interface_sram3_dat_w[23:16]; + if (wishbone_interface_sram3_we[3]) + mem_3[wishbone_interface_sram3_adr][31:24] <= wishbone_interface_sram3_dat_w[31:24]; + mem_3_adr1 <= wishbone_interface_sram3_adr; end -assign main_sram165_dat_r = mem_3_dat0; -assign main_sram3_dat_r = mem_3[mem_3_adr1]; +assign wishbone_interface_reader_memory1_dat_r = mem_3_dat0; +assign wishbone_interface_sram3_dat_r = mem_3[mem_3_adr1]; //------------------------------------------------------------------------------ @@ -4097,7 +4021,7 @@ ODDRX1F ODDRX1F( .SCLK (eth_tx_clk), // Outputs. - .Q (main_maccore_ethphy_eth_tx_clk_o) + .Q (maccore_ethphy_eth_tx_clk_o) ); //------------------------------------------------------------------------------ @@ -4107,10 +4031,10 @@ FD1S3BX FD1S3BX( // Inputs. .CK (eth_tx_clk), .D (1'd0), - .PD (main_maccore_ethphy_reset), + .PD (maccore_ethphy_reset), // Outputs. - .Q (builder_rst10) + .Q (rst10) ); //------------------------------------------------------------------------------ @@ -4119,8 +4043,8 @@ FD1S3BX FD1S3BX( FD1S3BX FD1S3BX_1( // Inputs. .CK (eth_tx_clk), - .D (builder_rst10), - .PD (main_maccore_ethphy_reset), + .D (rst10), + .PD (maccore_ethphy_reset), // Outputs. .Q (eth_tx_rst) @@ -4133,10 +4057,10 @@ FD1S3BX FD1S3BX_2( // Inputs. .CK (eth_rx_clk), .D (1'd0), - .PD (main_maccore_ethphy_reset), + .PD (maccore_ethphy_reset), // Outputs. - .Q (builder_rst11) + .Q (rst11) ); //------------------------------------------------------------------------------ @@ -4145,8 +4069,8 @@ FD1S3BX FD1S3BX_2( FD1S3BX FD1S3BX_3( // Inputs. .CK (eth_rx_clk), - .D (builder_rst11), - .PD (main_maccore_ethphy_reset), + .D (rst11), + .PD (maccore_ethphy_reset), // Outputs. .Q (eth_rx_rst) @@ -4157,12 +4081,12 @@ FD1S3BX FD1S3BX_3( //------------------------------------------------------------------------------ ODDRX1F ODDRX1F_1( // Inputs. - .D0 (main_maccore_ethphy_sink_valid), - .D1 (main_maccore_ethphy_sink_valid), + .D0 (maccore_ethphy_sink_valid), + .D1 (maccore_ethphy_sink_valid), .SCLK (eth_tx_clk), // Outputs. - .Q (main_maccore_ethphy_tx_ctl_oddrx1f) + .Q (maccore_ethphy_tx_ctl_oddrx1f) ); //------------------------------------------------------------------------------ @@ -4170,12 +4094,12 @@ ODDRX1F ODDRX1F_1( //------------------------------------------------------------------------------ ODDRX1F ODDRX1F_2( // Inputs. - .D0 (main_maccore_ethphy_sink_payload_data[0]), - .D1 (main_maccore_ethphy_sink_payload_data[4]), + .D0 (maccore_ethphy_sink_payload_data[0]), + .D1 (maccore_ethphy_sink_payload_data[4]), .SCLK (eth_tx_clk), // Outputs. - .Q (main_maccore_ethphy_tx_data_oddrx1f[0]) + .Q (maccore_ethphy_tx_data_oddrx1f[0]) ); //------------------------------------------------------------------------------ @@ -4183,12 +4107,12 @@ ODDRX1F ODDRX1F_2( //------------------------------------------------------------------------------ ODDRX1F ODDRX1F_3( // Inputs. - .D0 (main_maccore_ethphy_sink_payload_data[1]), - .D1 (main_maccore_ethphy_sink_payload_data[5]), + .D0 (maccore_ethphy_sink_payload_data[1]), + .D1 (maccore_ethphy_sink_payload_data[5]), .SCLK (eth_tx_clk), // Outputs. - .Q (main_maccore_ethphy_tx_data_oddrx1f[1]) + .Q (maccore_ethphy_tx_data_oddrx1f[1]) ); //------------------------------------------------------------------------------ @@ -4196,12 +4120,12 @@ ODDRX1F ODDRX1F_3( //------------------------------------------------------------------------------ ODDRX1F ODDRX1F_4( // Inputs. - .D0 (main_maccore_ethphy_sink_payload_data[2]), - .D1 (main_maccore_ethphy_sink_payload_data[6]), + .D0 (maccore_ethphy_sink_payload_data[2]), + .D1 (maccore_ethphy_sink_payload_data[6]), .SCLK (eth_tx_clk), // Outputs. - .Q (main_maccore_ethphy_tx_data_oddrx1f[2]) + .Q (maccore_ethphy_tx_data_oddrx1f[2]) ); //------------------------------------------------------------------------------ @@ -4209,12 +4133,12 @@ ODDRX1F ODDRX1F_4( //------------------------------------------------------------------------------ ODDRX1F ODDRX1F_5( // Inputs. - .D0 (main_maccore_ethphy_sink_payload_data[3]), - .D1 (main_maccore_ethphy_sink_payload_data[7]), + .D0 (maccore_ethphy_sink_payload_data[3]), + .D1 (maccore_ethphy_sink_payload_data[7]), .SCLK (eth_tx_clk), // Outputs. - .Q (main_maccore_ethphy_tx_data_oddrx1f[3]) + .Q (maccore_ethphy_tx_data_oddrx1f[3]) ); //------------------------------------------------------------------------------ @@ -4222,12 +4146,12 @@ ODDRX1F ODDRX1F_5( //------------------------------------------------------------------------------ IDDRX1F IDDRX1F( // Inputs. - .D (main_maccore_ethphy_rx_ctl_delayf), + .D (maccore_ethphy_rx_ctl_delayf), .SCLK (eth_rx_clk), // Outputs. - .Q0 (main_maccore_ethphy_rx_ctl[0]), - .Q1 (main_maccore_ethphy_rx_ctl[1]) + .Q0 (maccore_ethphy_rx_ctl[0]), + .Q1 (maccore_ethphy_rx_ctl[1]) ); //------------------------------------------------------------------------------ @@ -4235,12 +4159,12 @@ IDDRX1F IDDRX1F( //------------------------------------------------------------------------------ IDDRX1F IDDRX1F_1( // Inputs. - .D (main_maccore_ethphy_rx_data_delayf[0]), + .D (maccore_ethphy_rx_data_delayf[0]), .SCLK (eth_rx_clk), // Outputs. - .Q0 (main_maccore_ethphy_rx_data[0]), - .Q1 (main_maccore_ethphy_rx_data[4]) + .Q0 (maccore_ethphy_rx_data[0]), + .Q1 (maccore_ethphy_rx_data[4]) ); //------------------------------------------------------------------------------ @@ -4248,12 +4172,12 @@ IDDRX1F IDDRX1F_1( //------------------------------------------------------------------------------ IDDRX1F IDDRX1F_2( // Inputs. - .D (main_maccore_ethphy_rx_data_delayf[1]), + .D (maccore_ethphy_rx_data_delayf[1]), .SCLK (eth_rx_clk), // Outputs. - .Q0 (main_maccore_ethphy_rx_data[1]), - .Q1 (main_maccore_ethphy_rx_data[5]) + .Q0 (maccore_ethphy_rx_data[1]), + .Q1 (maccore_ethphy_rx_data[5]) ); //------------------------------------------------------------------------------ @@ -4261,12 +4185,12 @@ IDDRX1F IDDRX1F_2( //------------------------------------------------------------------------------ IDDRX1F IDDRX1F_3( // Inputs. - .D (main_maccore_ethphy_rx_data_delayf[2]), + .D (maccore_ethphy_rx_data_delayf[2]), .SCLK (eth_rx_clk), // Outputs. - .Q0 (main_maccore_ethphy_rx_data[2]), - .Q1 (main_maccore_ethphy_rx_data[6]) + .Q0 (maccore_ethphy_rx_data[2]), + .Q1 (maccore_ethphy_rx_data[6]) ); //------------------------------------------------------------------------------ @@ -4274,16 +4198,31 @@ IDDRX1F IDDRX1F_3( //------------------------------------------------------------------------------ IDDRX1F IDDRX1F_4( // Inputs. - .D (main_maccore_ethphy_rx_data_delayf[3]), + .D (maccore_ethphy_rx_data_delayf[3]), .SCLK (eth_rx_clk), // Outputs. - .Q0 (main_maccore_ethphy_rx_data[3]), - .Q1 (main_maccore_ethphy_rx_data[7]) + .Q0 (maccore_ethphy_rx_data[3]), + .Q1 (maccore_ethphy_rx_data[7]) +); + +//------------------------------------------------------------------------------ +// Instance BB of BB Module. +//------------------------------------------------------------------------------ +BB BB( + // Inputs. + .I (maccore_ethphy_data_w), + .T ((~maccore_ethphy_data_oe)), + + // Outputs. + .O (maccore_ethphy_data_r), + + // InOuts. + .B (rgmii_mdio) ); endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-09 14:20:59. +// Auto-Generated by LiteX on 2025-02-15 16:17:46. //------------------------------------------------------------------------------ diff --git a/liteeth/generated/nexys-video/liteeth_core.v b/liteeth/generated/nexys-video/liteeth_core.v index 1d780a9..67b81ee 100644 --- a/liteeth/generated/nexys-video/liteeth_core.v +++ b/liteeth/generated/nexys-video/liteeth_core.v @@ -8,8 +8,8 @@ // // Filename : liteeth_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-05 17:38:49 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 16:17:45 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -72,43 +72,43 @@ MACCore │ │ │ └─── [FDCE] │ │ │ └─── [FDCE] │ │ │ └─── [FDCE] -│ │ │ └─── [BUFG] │ │ │ └─── [FDCE] │ │ │ └─── [FDCE] │ │ │ └─── [FDCE] │ │ │ └─── [PLLE2_ADV] │ │ │ └─── [BUFG] -│ │ └─── [BUFG] +│ │ │ └─── [BUFG] +│ │ └─── [OBUF] │ │ └─── [ODDR] +│ │ └─── [BUFG] │ │ └─── [IBUF] -│ │ └─── [OBUF] │ └─── tx (LiteEthPHYRGMIITX) -│ │ └─── [OBUF] │ │ └─── [ODDR] │ │ └─── [OBUF] -│ │ └─── [OBUF] +│ │ └─── [ODDR] │ │ └─── [OBUF] │ │ └─── [ODDR] +│ │ └─── [OBUF] │ │ └─── [ODDR] │ │ └─── [ODDR] │ │ └─── [OBUF] -│ │ └─── [ODDR] +│ │ └─── [OBUF] │ └─── rx (LiteEthPHYRGMIIRX) -│ │ └─── [IDDR] │ │ └─── [IBUF] +│ │ └─── [IDELAYE2] │ │ └─── [IBUF] +│ │ └─── [IDELAYE2] │ │ └─── [IDDR] │ │ └─── [IBUF] │ │ └─── [IDELAYE2] │ │ └─── [IDDR] -│ │ └─── [IDDR] │ │ └─── [IBUF] │ │ └─── [IDELAYE2] +│ │ └─── [IDDR] │ │ └─── [IDELAYE2] -│ │ └─── [IDELAYE2] +│ │ └─── [IDDR] │ │ └─── [IBUF] │ │ └─── [IDDR] -│ │ └─── [IDELAYE2] │ └─── mdio (LiteEthPHYMDIO) └─── ethmac (LiteEthMAC) │ └─── core (LiteEthMACCore) @@ -122,7 +122,8 @@ MACCore │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) -│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── last_handler (LiteEthLastHandler) +│ │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) @@ -179,9 +180,11 @@ MACCore │ │ │ └─── ev (SharedIRQ) │ │ └─── sram_0* (SRAM) │ │ └─── sram_1* (SRAM) +│ │ └─── decoder_0* (Decoder) │ │ └─── sram_2* (SRAM) │ │ └─── sram_3* (SRAM) -│ │ └─── decoder_0* (Decoder) +│ │ └─── decoder_1* (Decoder) +│ └─── ev (SharedIRQ) └─── csr_bridge (Wishbone2CSR) │ └─── fsm (FSM) └─── csr_bankarray (CSRBankArray) @@ -225,1426 +228,1416 @@ MACCore // Signals //------------------------------------------------------------------------------ -wire [13:0] builder_adr; -wire [39:0] builder_complexslicelowerer_slice_proxy; -reg [19:0] builder_count = 20'd1000000; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_reset0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_scratch0_we = 1'd0; -wire builder_csrbank0_sel; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; -reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; -reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; -reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; -reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; -wire builder_csrbank1_sel; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_w; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire builder_csrbank2_sel; -wire [31:0] builder_dat_r; -wire [31:0] builder_dat_w; -wire builder_done; -reg builder_error = 1'd0; -wire builder_grant; -reg builder_interface0_ack = 1'd0; -wire [29:0] builder_interface0_adr; -wire [13:0] builder_interface0_bank_bus_adr; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface0_bank_bus_dat_w; -wire builder_interface0_bank_bus_we; -wire [1:0] builder_interface0_bte; -wire [2:0] builder_interface0_cti; -wire builder_interface0_cyc; -reg [31:0] builder_interface0_dat_r = 32'd0; -wire [31:0] builder_interface0_dat_w; -reg builder_interface0_err = 1'd0; -wire [3:0] builder_interface0_sel; -wire builder_interface0_stb; -wire builder_interface0_we; -reg [13:0] builder_interface1_adr = 14'd0; -wire [13:0] builder_interface1_bank_bus_adr; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface1_bank_bus_dat_w; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_dat_r; -reg [31:0] builder_interface1_dat_w = 32'd0; -reg builder_interface1_we = 1'd0; -wire [13:0] builder_interface2_bank_bus_adr; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface2_bank_bus_dat_w; -wire builder_interface2_bank_bus_we; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg builder_next_state = 1'd0; -wire builder_pll_fb; -wire builder_request; -wire builder_reset0; -wire builder_reset1; -wire builder_reset2; -wire builder_reset3; -wire builder_reset4; -wire builder_reset5; -wire builder_reset6; -wire builder_reset7; -reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; -reg [29:0] builder_self0 = 30'd0; -reg [31:0] builder_self1 = 32'd0; -reg [3:0] builder_self2 = 4'd0; -reg builder_self3 = 1'd0; -reg builder_self4 = 1'd0; -reg builder_self5 = 1'd0; -reg [2:0] builder_self6 = 3'd0; -reg [1:0] builder_self7 = 2'd0; -reg builder_shared_ack = 1'd0; -wire [29:0] builder_shared_adr; -wire [1:0] builder_shared_bte; -wire [2:0] builder_shared_cti; -wire builder_shared_cyc; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [31:0] builder_shared_dat_w; -wire builder_shared_err; -wire [3:0] builder_shared_sel; -wire builder_shared_stb; -wire builder_shared_we; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_state = 1'd0; -wire [31:0] builder_t_slice_proxy0; -wire [31:0] builder_t_slice_proxy1; -wire [31:0] builder_t_slice_proxy10; -wire [31:0] builder_t_slice_proxy11; -wire [31:0] builder_t_slice_proxy12; -wire [31:0] builder_t_slice_proxy13; -wire [31:0] builder_t_slice_proxy14; -wire [31:0] builder_t_slice_proxy15; -wire [31:0] builder_t_slice_proxy16; -wire [31:0] builder_t_slice_proxy17; -wire [31:0] builder_t_slice_proxy18; -wire [31:0] builder_t_slice_proxy19; -wire [31:0] builder_t_slice_proxy2; -wire [31:0] builder_t_slice_proxy20; -wire [31:0] builder_t_slice_proxy21; -wire [31:0] builder_t_slice_proxy22; -wire [31:0] builder_t_slice_proxy23; -wire [31:0] builder_t_slice_proxy24; -wire [31:0] builder_t_slice_proxy25; -wire [31:0] builder_t_slice_proxy26; -wire [31:0] builder_t_slice_proxy27; -wire [31:0] builder_t_slice_proxy28; -wire [31:0] builder_t_slice_proxy29; -wire [31:0] builder_t_slice_proxy3; -wire [31:0] builder_t_slice_proxy30; -wire [31:0] builder_t_slice_proxy31; -wire [31:0] builder_t_slice_proxy32; -wire [31:0] builder_t_slice_proxy33; -wire [31:0] builder_t_slice_proxy34; -wire [31:0] builder_t_slice_proxy35; -wire [31:0] builder_t_slice_proxy36; -wire [31:0] builder_t_slice_proxy37; -wire [31:0] builder_t_slice_proxy38; -wire [31:0] builder_t_slice_proxy39; -wire [31:0] builder_t_slice_proxy4; -wire [31:0] builder_t_slice_proxy40; -wire [31:0] builder_t_slice_proxy41; -wire [31:0] builder_t_slice_proxy42; -wire [31:0] builder_t_slice_proxy43; -wire [31:0] builder_t_slice_proxy44; -wire [31:0] builder_t_slice_proxy45; -wire [31:0] builder_t_slice_proxy46; -wire [31:0] builder_t_slice_proxy47; -wire [31:0] builder_t_slice_proxy48; -wire [31:0] builder_t_slice_proxy49; -wire [31:0] builder_t_slice_proxy5; -wire [31:0] builder_t_slice_proxy50; -wire [31:0] builder_t_slice_proxy51; -wire [31:0] builder_t_slice_proxy52; -wire [31:0] builder_t_slice_proxy53; -wire [31:0] builder_t_slice_proxy54; -wire [31:0] builder_t_slice_proxy55; -wire [31:0] builder_t_slice_proxy56; -wire [31:0] builder_t_slice_proxy57; -wire [31:0] builder_t_slice_proxy58; -wire [31:0] builder_t_slice_proxy59; -wire [31:0] builder_t_slice_proxy6; -wire [31:0] builder_t_slice_proxy60; -wire [31:0] builder_t_slice_proxy61; -wire [31:0] builder_t_slice_proxy62; -wire [31:0] builder_t_slice_proxy63; -wire [31:0] builder_t_slice_proxy7; -wire [31:0] builder_t_slice_proxy8; -wire [31:0] builder_t_slice_proxy9; -reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; -reg builder_txdatapath_liteethmacgap_next_state = 1'd0; -reg builder_txdatapath_liteethmacgap_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; -reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; -reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; -wire builder_wait; -wire builder_we; -wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; -wire builder_xilinxasyncresetsynchronizerimpl0_expr; -wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire [13:0] adr; +wire core_bufferizeendpoints_pipe_valid_sink_first; +wire core_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] core_bufferizeendpoints_pipe_valid_sink_payload_data; +wire core_bufferizeendpoints_pipe_valid_sink_payload_error; +wire core_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire core_bufferizeendpoints_pipe_valid_sink_ready; +wire core_bufferizeendpoints_pipe_valid_sink_valid; +reg core_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] core_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire core_bufferizeendpoints_pipe_valid_source_ready; +reg core_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire core_bufferizeendpoints_sink_sink_first; +wire core_bufferizeendpoints_sink_sink_last; +wire [7:0] core_bufferizeendpoints_sink_sink_payload_data; +wire core_bufferizeendpoints_sink_sink_payload_error; +wire core_bufferizeendpoints_sink_sink_payload_last_be; +wire core_bufferizeendpoints_sink_sink_ready; +wire core_bufferizeendpoints_sink_sink_valid; +wire core_bufferizeendpoints_source_source_first; +wire core_bufferizeendpoints_source_source_last; +wire [7:0] core_bufferizeendpoints_source_source_payload_data; +wire core_bufferizeendpoints_source_source_payload_error; +wire core_bufferizeendpoints_source_source_payload_last_be; +wire core_bufferizeendpoints_source_source_ready; +wire core_bufferizeendpoints_source_source_valid; +reg core_crc_errors_re = 1'd0; +reg [31:0] core_crc_errors_status = 32'd0; +wire core_crc_errors_we; +wire core_liteethmaccrc32checker_crc_be; +reg core_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] core_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] core_liteethmaccrc32checker_crc_data0; +wire [7:0] core_liteethmaccrc32checker_crc_data1; +reg core_liteethmaccrc32checker_crc_error0 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg core_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_value = 32'd0; +reg core_liteethmaccrc32checker_error = 1'd0; +wire core_liteethmaccrc32checker_fifo_full; +wire core_liteethmaccrc32checker_fifo_in; +wire core_liteethmaccrc32checker_fifo_out; +reg core_liteethmaccrc32checker_fifo_reset = 1'd0; +reg core_liteethmaccrc32checker_last_be = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_first; +wire core_liteethmaccrc32checker_sink_sink_last; +wire [7:0] core_liteethmaccrc32checker_sink_sink_payload_data; +wire core_liteethmaccrc32checker_sink_sink_payload_error; +wire core_liteethmaccrc32checker_sink_sink_payload_last_be; +reg core_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_valid; +wire core_liteethmaccrc32checker_source_source_first; +reg core_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] core_liteethmaccrc32checker_source_source_payload_data; +reg core_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg core_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire core_liteethmaccrc32checker_source_source_ready; +reg core_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire core_liteethmaccrc32checker_syncfifo_do_read; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] core_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] core_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg core_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_sink_first; +wire core_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_sink_ready; +reg core_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_first; +wire core_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_source_payload_data; +wire core_liteethmaccrc32checker_syncfifo_source_payload_error; +wire core_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg core_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] core_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire core_liteethmaccrc32checker_syncfifo_wrport_we; +reg core_preamble_errors_re = 1'd0; +reg [31:0] core_preamble_errors_status = 32'd0; +wire core_preamble_errors_we; +wire core_pulsesynchronizer0_i; +wire core_pulsesynchronizer0_o; +reg core_pulsesynchronizer0_toggle_i = 1'd0; +wire core_pulsesynchronizer0_toggle_o; +reg core_pulsesynchronizer0_toggle_o_r = 1'd0; +wire core_pulsesynchronizer1_i; +wire core_pulsesynchronizer1_o; +reg core_pulsesynchronizer1_toggle_i = 1'd0; +wire core_pulsesynchronizer1_toggle_o; +reg core_pulsesynchronizer1_toggle_o_r = 1'd0; +reg core_re = 1'd0; +wire [41:0] core_rx_cdc_cdc_asyncfifo_din; +wire [41:0] core_rx_cdc_cdc_asyncfifo_dout; +wire core_rx_cdc_cdc_asyncfifo_re; +wire core_rx_cdc_cdc_asyncfifo_readable; +wire core_rx_cdc_cdc_asyncfifo_we; +wire core_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_rx_cdc_cdc_consume_wdomain; +wire core_rx_cdc_cdc_fifo_in_first; +wire core_rx_cdc_cdc_fifo_in_last; +wire [31:0] core_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_last_be; +wire core_rx_cdc_cdc_fifo_out_first; +wire core_rx_cdc_cdc_fifo_out_last; +wire [31:0] core_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_last_be; +wire core_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] core_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] core_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_produce_rdomain; +wire [4:0] core_rx_cdc_cdc_rdport_adr; +wire [41:0] core_rx_cdc_cdc_rdport_dat_r; +wire core_rx_cdc_cdc_sink_first; +wire core_rx_cdc_cdc_sink_last; +wire [31:0] core_rx_cdc_cdc_sink_payload_data; +wire [3:0] core_rx_cdc_cdc_sink_payload_error; +wire [3:0] core_rx_cdc_cdc_sink_payload_last_be; +wire core_rx_cdc_cdc_sink_ready; +wire core_rx_cdc_cdc_sink_valid; +wire core_rx_cdc_cdc_source_first; +wire core_rx_cdc_cdc_source_last; +wire [31:0] core_rx_cdc_cdc_source_payload_data; +wire [3:0] core_rx_cdc_cdc_source_payload_error; +wire [3:0] core_rx_cdc_cdc_source_payload_last_be; +wire core_rx_cdc_cdc_source_ready; +wire core_rx_cdc_cdc_source_valid; +wire [4:0] core_rx_cdc_cdc_wrport_adr; +wire [41:0] core_rx_cdc_cdc_wrport_dat_r; +wire [41:0] core_rx_cdc_cdc_wrport_dat_w; +wire core_rx_cdc_cdc_wrport_we; +wire core_rx_cdc_sink_sink_first; +wire core_rx_cdc_sink_sink_last; +wire [31:0] core_rx_cdc_sink_sink_payload_data; +wire [3:0] core_rx_cdc_sink_sink_payload_error; +wire [3:0] core_rx_cdc_sink_sink_payload_last_be; +wire core_rx_cdc_sink_sink_ready; +wire core_rx_cdc_sink_sink_valid; +wire core_rx_cdc_source_source_first; +wire core_rx_cdc_source_source_last; +wire [31:0] core_rx_cdc_source_source_payload_data; +wire [3:0] core_rx_cdc_source_source_payload_error; +wire [3:0] core_rx_cdc_source_source_payload_last_be; +wire core_rx_cdc_source_source_ready; +wire core_rx_cdc_source_source_valid; +reg [1:0] core_rx_converter_converter_demux = 2'd0; +wire core_rx_converter_converter_load_part; +wire core_rx_converter_converter_sink_first; +wire core_rx_converter_converter_sink_last; +wire [9:0] core_rx_converter_converter_sink_payload_data; +wire core_rx_converter_converter_sink_ready; +wire core_rx_converter_converter_sink_valid; +reg core_rx_converter_converter_source_first = 1'd0; +reg core_rx_converter_converter_source_last = 1'd0; +reg [39:0] core_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] core_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire core_rx_converter_converter_source_ready; +wire core_rx_converter_converter_source_valid; +reg core_rx_converter_converter_strobe_all = 1'd0; +wire core_rx_converter_sink_first; +wire core_rx_converter_sink_last; +wire [7:0] core_rx_converter_sink_payload_data; +wire core_rx_converter_sink_payload_error; +wire core_rx_converter_sink_payload_last_be; +wire core_rx_converter_sink_ready; +wire core_rx_converter_sink_valid; +wire core_rx_converter_source_first; +wire core_rx_converter_source_last; +reg [31:0] core_rx_converter_source_payload_data = 32'd0; +reg [3:0] core_rx_converter_source_payload_error = 4'd0; +reg [3:0] core_rx_converter_source_payload_last_be = 4'd0; +wire core_rx_converter_source_ready; +wire core_rx_converter_source_source_first; +wire core_rx_converter_source_source_last; +wire [39:0] core_rx_converter_source_source_payload_data; +wire core_rx_converter_source_source_ready; +wire core_rx_converter_source_source_valid; +wire core_rx_converter_source_valid; +wire core_rx_last_be_sink_first; +wire core_rx_last_be_sink_last; +wire [7:0] core_rx_last_be_sink_payload_data; +wire core_rx_last_be_sink_payload_error; +wire core_rx_last_be_sink_payload_last_be; +wire core_rx_last_be_sink_ready; +wire core_rx_last_be_sink_valid; +wire core_rx_last_be_source_first; +wire core_rx_last_be_source_last; +wire [7:0] core_rx_last_be_source_payload_data; +wire core_rx_last_be_source_payload_error; +reg core_rx_last_be_source_payload_last_be = 1'd0; +wire core_rx_last_be_source_ready; +wire core_rx_last_be_source_valid; +wire core_rx_padding_sink_first; +wire core_rx_padding_sink_last; +wire [7:0] core_rx_padding_sink_payload_data; +wire core_rx_padding_sink_payload_error; +wire core_rx_padding_sink_payload_last_be; +wire core_rx_padding_sink_ready; +wire core_rx_padding_sink_valid; +wire core_rx_padding_source_first; +wire core_rx_padding_source_last; +wire [7:0] core_rx_padding_source_payload_data; +wire core_rx_padding_source_payload_error; +wire core_rx_padding_source_payload_last_be; +wire core_rx_padding_source_ready; +wire core_rx_padding_source_valid; +reg core_rx_preamble_error = 1'd0; +reg [63:0] core_rx_preamble_preamble = 64'd15372286728091293013; +wire core_rx_preamble_sink_first; +wire core_rx_preamble_sink_last; +wire [7:0] core_rx_preamble_sink_payload_data; +wire core_rx_preamble_sink_payload_error; +wire core_rx_preamble_sink_payload_last_be; +reg core_rx_preamble_sink_ready = 1'd0; +wire core_rx_preamble_sink_valid; +reg core_rx_preamble_source_first = 1'd0; +reg core_rx_preamble_source_last = 1'd0; +wire [7:0] core_rx_preamble_source_payload_data; +reg core_rx_preamble_source_payload_error = 1'd0; +wire core_rx_preamble_source_payload_last_be; +wire core_rx_preamble_source_ready; +reg core_rx_preamble_source_valid = 1'd0; +wire core_sink_first; +wire core_sink_last; +wire [31:0] core_sink_payload_data; +wire [3:0] core_sink_payload_error; +wire [3:0] core_sink_payload_last_be; +wire core_sink_ready; +wire core_sink_valid; +wire core_source_first; +wire core_source_last; +wire [31:0] core_source_payload_data; +wire [3:0] core_source_payload_error; +wire [3:0] core_source_payload_last_be; +wire core_source_ready; +wire core_source_valid; +reg core_status = 1'd1; +wire [41:0] core_tx_cdc_cdc_asyncfifo_din; +wire [41:0] core_tx_cdc_cdc_asyncfifo_dout; +wire core_tx_cdc_cdc_asyncfifo_re; +wire core_tx_cdc_cdc_asyncfifo_readable; +wire core_tx_cdc_cdc_asyncfifo_we; +wire core_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_tx_cdc_cdc_consume_wdomain; +wire core_tx_cdc_cdc_fifo_in_first; +wire core_tx_cdc_cdc_fifo_in_last; +wire [31:0] core_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_last_be; +wire core_tx_cdc_cdc_fifo_out_first; +wire core_tx_cdc_cdc_fifo_out_last; +wire [31:0] core_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_last_be; +wire core_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] core_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] core_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_produce_rdomain; +wire [4:0] core_tx_cdc_cdc_rdport_adr; +wire [41:0] core_tx_cdc_cdc_rdport_dat_r; +wire core_tx_cdc_cdc_sink_first; +wire core_tx_cdc_cdc_sink_last; +wire [31:0] core_tx_cdc_cdc_sink_payload_data; +wire [3:0] core_tx_cdc_cdc_sink_payload_error; +wire [3:0] core_tx_cdc_cdc_sink_payload_last_be; +wire core_tx_cdc_cdc_sink_ready; +wire core_tx_cdc_cdc_sink_valid; +wire core_tx_cdc_cdc_source_first; +wire core_tx_cdc_cdc_source_last; +wire [31:0] core_tx_cdc_cdc_source_payload_data; +wire [3:0] core_tx_cdc_cdc_source_payload_error; +wire [3:0] core_tx_cdc_cdc_source_payload_last_be; +wire core_tx_cdc_cdc_source_ready; +wire core_tx_cdc_cdc_source_valid; +wire [4:0] core_tx_cdc_cdc_wrport_adr; +wire [41:0] core_tx_cdc_cdc_wrport_dat_r; +wire [41:0] core_tx_cdc_cdc_wrport_dat_w; +wire core_tx_cdc_cdc_wrport_we; +wire core_tx_cdc_sink_sink_first; +wire core_tx_cdc_sink_sink_last; +wire [31:0] core_tx_cdc_sink_sink_payload_data; +wire [3:0] core_tx_cdc_sink_sink_payload_error; +wire [3:0] core_tx_cdc_sink_sink_payload_last_be; +wire core_tx_cdc_sink_sink_ready; +wire core_tx_cdc_sink_sink_valid; +wire core_tx_cdc_source_source_first; +wire core_tx_cdc_source_source_last; +wire [31:0] core_tx_cdc_source_source_payload_data; +wire [3:0] core_tx_cdc_source_source_payload_error; +wire [3:0] core_tx_cdc_source_source_payload_last_be; +wire core_tx_cdc_source_source_ready; +wire core_tx_cdc_source_source_valid; +wire core_tx_converter_converter_first; +wire core_tx_converter_converter_last; +reg [1:0] core_tx_converter_converter_mux = 2'd0; +wire core_tx_converter_converter_sink_first; +wire core_tx_converter_converter_sink_last; +reg [39:0] core_tx_converter_converter_sink_payload_data = 40'd0; +wire core_tx_converter_converter_sink_ready; +wire core_tx_converter_converter_sink_valid; +wire core_tx_converter_converter_source_first; +wire core_tx_converter_converter_source_last; +reg [9:0] core_tx_converter_converter_source_payload_data = 10'd0; +wire core_tx_converter_converter_source_payload_valid_token_count; +wire core_tx_converter_converter_source_ready; +wire core_tx_converter_converter_source_valid; +wire core_tx_converter_sink_first; +wire core_tx_converter_sink_last; +wire [31:0] core_tx_converter_sink_payload_data; +wire [3:0] core_tx_converter_sink_payload_error; +wire [3:0] core_tx_converter_sink_payload_last_be; +wire core_tx_converter_sink_ready; +wire core_tx_converter_sink_valid; +wire core_tx_converter_source_first; +wire core_tx_converter_source_last; +wire [7:0] core_tx_converter_source_payload_data; +wire core_tx_converter_source_payload_error; +wire core_tx_converter_source_payload_last_be; +wire core_tx_converter_source_ready; +wire core_tx_converter_source_source_first; +wire core_tx_converter_source_source_last; +wire [9:0] core_tx_converter_source_source_payload_data; +wire core_tx_converter_source_source_ready; +wire core_tx_converter_source_source_valid; +wire core_tx_converter_source_valid; +wire core_tx_crc_be; +reg core_tx_crc_ce = 1'd0; +reg [1:0] core_tx_crc_cnt = 2'd3; +wire core_tx_crc_cnt_done; +reg [31:0] core_tx_crc_crc_next = 32'd0; +reg [31:0] core_tx_crc_crc_packet = 32'd0; +reg [31:0] core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] core_tx_crc_crc_prev; +wire [7:0] core_tx_crc_data0; +wire [7:0] core_tx_crc_data1; +reg core_tx_crc_error = 1'd0; +reg core_tx_crc_is_ongoing0 = 1'd0; +reg core_tx_crc_is_ongoing1 = 1'd0; +reg core_tx_crc_last_be = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire core_tx_crc_pipe_valid_sink_first; +wire core_tx_crc_pipe_valid_sink_last; +wire [7:0] core_tx_crc_pipe_valid_sink_payload_data; +wire core_tx_crc_pipe_valid_sink_payload_error; +wire core_tx_crc_pipe_valid_sink_payload_last_be; +wire core_tx_crc_pipe_valid_sink_ready; +wire core_tx_crc_pipe_valid_sink_valid; +reg core_tx_crc_pipe_valid_source_first = 1'd0; +reg core_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] core_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg core_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg core_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire core_tx_crc_pipe_valid_source_ready; +reg core_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] core_tx_crc_reg = 32'd4294967295; +reg core_tx_crc_reset = 1'd0; +wire core_tx_crc_sink_first; +wire core_tx_crc_sink_last; +wire [7:0] core_tx_crc_sink_payload_data; +wire core_tx_crc_sink_payload_error; +wire core_tx_crc_sink_payload_last_be; +reg core_tx_crc_sink_ready = 1'd0; +wire core_tx_crc_sink_sink_first; +wire core_tx_crc_sink_sink_last; +wire [7:0] core_tx_crc_sink_sink_payload_data; +wire core_tx_crc_sink_sink_payload_error; +wire core_tx_crc_sink_sink_payload_last_be; +wire core_tx_crc_sink_sink_ready; +wire core_tx_crc_sink_sink_valid; +wire core_tx_crc_sink_valid; +reg core_tx_crc_source_first = 1'd0; +reg core_tx_crc_source_last = 1'd0; +reg [7:0] core_tx_crc_source_payload_data = 8'd0; +reg core_tx_crc_source_payload_error = 1'd0; +reg core_tx_crc_source_payload_last_be = 1'd0; +wire core_tx_crc_source_ready; +wire core_tx_crc_source_source_first; +wire core_tx_crc_source_source_last; +wire [7:0] core_tx_crc_source_source_payload_data; +wire core_tx_crc_source_source_payload_error; +wire core_tx_crc_source_source_payload_last_be; +wire core_tx_crc_source_source_ready; +wire core_tx_crc_source_source_valid; +reg core_tx_crc_source_valid = 1'd0; +reg [31:0] core_tx_crc_value = 32'd0; +reg [3:0] core_tx_gap_counter = 4'd0; +reg [3:0] core_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg core_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire core_tx_gap_sink_first; +wire core_tx_gap_sink_last; +wire [7:0] core_tx_gap_sink_payload_data; +wire core_tx_gap_sink_payload_error; +wire core_tx_gap_sink_payload_last_be; +reg core_tx_gap_sink_ready = 1'd0; +wire core_tx_gap_sink_valid; +reg core_tx_gap_source_first = 1'd0; +reg core_tx_gap_source_last = 1'd0; +reg [7:0] core_tx_gap_source_payload_data = 8'd0; +reg core_tx_gap_source_payload_error = 1'd0; +reg core_tx_gap_source_payload_last_be = 1'd0; +wire core_tx_gap_source_ready; +reg core_tx_gap_source_valid = 1'd0; +wire core_tx_last_be_last_handler_sink_first; +wire core_tx_last_be_last_handler_sink_last; +wire [7:0] core_tx_last_be_last_handler_sink_payload_data; +wire core_tx_last_be_last_handler_sink_payload_error; +wire core_tx_last_be_last_handler_sink_payload_last_be; +reg core_tx_last_be_last_handler_sink_ready = 1'd0; +wire core_tx_last_be_last_handler_sink_valid; +reg core_tx_last_be_last_handler_source_first = 1'd0; +reg core_tx_last_be_last_handler_source_last = 1'd0; +reg [7:0] core_tx_last_be_last_handler_source_payload_data = 8'd0; +reg core_tx_last_be_last_handler_source_payload_error = 1'd0; +reg core_tx_last_be_last_handler_source_payload_last_be = 1'd0; +wire core_tx_last_be_last_handler_source_ready; +reg core_tx_last_be_last_handler_source_valid = 1'd0; +wire core_tx_last_be_sink_sink_first; +wire core_tx_last_be_sink_sink_last; +wire [7:0] core_tx_last_be_sink_sink_payload_data; +wire core_tx_last_be_sink_sink_payload_error; +wire core_tx_last_be_sink_sink_payload_last_be; +wire core_tx_last_be_sink_sink_ready; +wire core_tx_last_be_sink_sink_valid; +wire core_tx_last_be_source_source_first; +wire core_tx_last_be_source_source_last; +wire [7:0] core_tx_last_be_source_source_payload_data; +wire core_tx_last_be_source_source_payload_error; +wire core_tx_last_be_source_source_payload_last_be; +wire core_tx_last_be_source_source_ready; +wire core_tx_last_be_source_source_valid; +reg [15:0] core_tx_padding_counter = 16'd0; +reg [15:0] core_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg core_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire core_tx_padding_counter_done; +wire core_tx_padding_sink_first; +wire core_tx_padding_sink_last; +wire [7:0] core_tx_padding_sink_payload_data; +wire core_tx_padding_sink_payload_error; +wire core_tx_padding_sink_payload_last_be; +reg core_tx_padding_sink_ready = 1'd0; +wire core_tx_padding_sink_valid; +reg core_tx_padding_source_first = 1'd0; +reg core_tx_padding_source_last = 1'd0; +reg [7:0] core_tx_padding_source_payload_data = 8'd0; +reg core_tx_padding_source_payload_error = 1'd0; +reg core_tx_padding_source_payload_last_be = 1'd0; +wire core_tx_padding_source_ready; +reg core_tx_padding_source_valid = 1'd0; +reg [2:0] core_tx_preamble_count = 3'd0; +reg [2:0] core_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg core_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] core_tx_preamble_preamble = 64'd15372286728091293013; +wire core_tx_preamble_sink_first; +wire core_tx_preamble_sink_last; +wire [7:0] core_tx_preamble_sink_payload_data; +wire core_tx_preamble_sink_payload_error; +wire core_tx_preamble_sink_payload_last_be; +reg core_tx_preamble_sink_ready = 1'd0; +wire core_tx_preamble_sink_valid; +reg core_tx_preamble_source_first = 1'd0; +reg core_tx_preamble_source_last = 1'd0; +reg [7:0] core_tx_preamble_source_payload_data = 8'd0; +reg core_tx_preamble_source_payload_error = 1'd0; +wire core_tx_preamble_source_payload_last_be; +wire core_tx_preamble_source_ready; +reg core_tx_preamble_source_valid = 1'd0; +wire core_we; +reg [19:0] count = 20'd1000000; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire csrbank1_preamble_crc_r; +reg csrbank1_preamble_crc_re = 1'd0; +wire csrbank1_preamble_crc_w; +reg csrbank1_preamble_crc_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_r; +reg csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_w; +reg csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_r; +reg csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_w; +reg csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire csrbank1_sel; +wire csrbank1_sram_reader_ev_enable0_r; +reg csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire csrbank1_sram_reader_ev_enable0_w; +reg csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire csrbank1_sram_reader_ev_pending_r; +reg csrbank1_sram_reader_ev_pending_re = 1'd0; +wire csrbank1_sram_reader_ev_pending_w; +reg csrbank1_sram_reader_ev_pending_we = 1'd0; +wire csrbank1_sram_reader_ev_status_r; +reg csrbank1_sram_reader_ev_status_re = 1'd0; +wire csrbank1_sram_reader_ev_status_w; +reg csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_r; +reg csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_w; +reg csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] csrbank1_sram_reader_level_r; +reg csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] csrbank1_sram_reader_level_w; +reg csrbank1_sram_reader_level_we = 1'd0; +wire csrbank1_sram_reader_ready_r; +reg csrbank1_sram_reader_ready_re = 1'd0; +wire csrbank1_sram_reader_ready_w; +reg csrbank1_sram_reader_ready_we = 1'd0; +wire csrbank1_sram_reader_slot0_r; +reg csrbank1_sram_reader_slot0_re = 1'd0; +wire csrbank1_sram_reader_slot0_w; +reg csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_r; +reg csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_w; +reg csrbank1_sram_writer_errors_we = 1'd0; +wire csrbank1_sram_writer_ev_enable0_r; +reg csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire csrbank1_sram_writer_ev_enable0_w; +reg csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire csrbank1_sram_writer_ev_pending_r; +reg csrbank1_sram_writer_ev_pending_re = 1'd0; +wire csrbank1_sram_writer_ev_pending_w; +reg csrbank1_sram_writer_ev_pending_we = 1'd0; +wire csrbank1_sram_writer_ev_status_r; +reg csrbank1_sram_writer_ev_status_re = 1'd0; +wire csrbank1_sram_writer_ev_status_w; +reg csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_writer_length_r; +reg csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] csrbank1_sram_writer_length_w; +reg csrbank1_sram_writer_length_we = 1'd0; +wire csrbank1_sram_writer_slot_r; +reg csrbank1_sram_writer_slot_re = 1'd0; +wire csrbank1_sram_writer_slot_w; +reg csrbank1_sram_writer_slot_we = 1'd0; +wire csrbank2_crg_reset0_r; +reg csrbank2_crg_reset0_re = 1'd0; +wire csrbank2_crg_reset0_w; +reg csrbank2_crg_reset0_we = 1'd0; +wire csrbank2_mdio_r_r; +reg csrbank2_mdio_r_re = 1'd0; +wire csrbank2_mdio_r_w; +reg csrbank2_mdio_r_we = 1'd0; +wire [2:0] csrbank2_mdio_w0_r; +reg csrbank2_mdio_w0_re = 1'd0; +wire [2:0] csrbank2_mdio_w0_w; +reg csrbank2_mdio_w0_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire done; +reg error = 1'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_delayed_clk; +wire eth_tx_rst; +wire grant; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; +wire interface2_bank_bus_we; +reg [1:0] liteethmacsramreader_next_state = 2'd0; +reg [1:0] liteethmacsramreader_state = 2'd0; +reg [2:0] liteethmacsramwriter_next_state = 3'd0; +reg [2:0] liteethmacsramwriter_state = 3'd0; +reg maccore_ethphy__r_re = 1'd0; +reg maccore_ethphy__r_status = 1'd0; +wire maccore_ethphy__r_we; +reg maccore_ethphy__w_re = 1'd0; +reg [2:0] maccore_ethphy__w_storage = 3'd0; +wire maccore_ethphy_clkin; +wire maccore_ethphy_clkout0; +wire maccore_ethphy_clkout1; +wire maccore_ethphy_clkout_buf0; +wire maccore_ethphy_clkout_buf1; +wire maccore_ethphy_data_oe; +wire maccore_ethphy_data_r; +wire maccore_ethphy_data_w; +wire maccore_ethphy_eth_rx_clk_ibuf; +wire maccore_ethphy_eth_tx_clk_obuf; +wire maccore_ethphy_liteethphyrgmiirx; +wire maccore_ethphy_liteethphyrgmiirx_last; +wire maccore_ethphy_liteethphyrgmiirx_rx_ctl; +reg maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; +wire maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; +wire maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; +wire [7:0] maccore_ethphy_liteethphyrgmiirx_rx_data; +wire [3:0] maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; +wire [3:0] maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; +reg maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; +wire maccore_ethphy_liteethphyrgmiirx_source_last; +reg [7:0] maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; +reg maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; +reg maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; +wire maccore_ethphy_liteethphyrgmiirx_source_ready; +reg maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; +wire maccore_ethphy_locked; +wire maccore_ethphy_mdc; +wire maccore_ethphy_oe; +reg maccore_ethphy_power_down = 1'd0; +reg maccore_ethphy_r = 1'd0; +reg maccore_ethphy_reset0 = 1'd0; +wire maccore_ethphy_reset1; +reg maccore_ethphy_reset_re = 1'd0; +reg maccore_ethphy_reset_storage = 1'd0; +wire maccore_ethphy_sink_first; +wire maccore_ethphy_sink_last; +wire [7:0] maccore_ethphy_sink_payload_data; +wire maccore_ethphy_sink_payload_error; +wire maccore_ethphy_sink_payload_last_be; +wire maccore_ethphy_sink_ready; +wire maccore_ethphy_sink_valid; +wire maccore_ethphy_tx_ctl_obuf; +wire [3:0] maccore_ethphy_tx_data_obuf; +wire maccore_ethphy_w; +reg maccore_int_rst = 1'd1; +wire maccore_maccore_bus_error; +reg [31:0] maccore_maccore_bus_errors = 32'd0; +reg maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] maccore_maccore_bus_errors_status; +wire maccore_maccore_bus_errors_we; +wire maccore_maccore_cpu_rst; +reg maccore_maccore_reset_re = 1'd0; +reg [1:0] maccore_maccore_reset_storage = 2'd0; +reg maccore_maccore_scratch_re = 1'd0; +reg [31:0] maccore_maccore_scratch_storage = 32'd305419896; +reg maccore_maccore_soc_rst = 1'd0; +reg next_state = 1'd0; +wire pll_fb; +wire por_clk; +wire re; +wire request; +wire reset0; +wire reset1; +wire reset2; +wire reset3; +wire reset4; +wire reset5; +wire reset6; +wire reset7; +reg [1:0] rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] rxdatapath_bufferizeendpoints_state = 2'd0; +reg rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] self0 = 30'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [29:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg [2:0] slave_sel = 3'd0; +reg [2:0] slave_sel_r = 3'd0; +reg state = 1'd0; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; +reg [1:0] txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] txdatapath_bufferizeendpoints_state = 2'd0; +reg txdatapath_liteethmacgap_next_state = 1'd0; +reg txdatapath_liteethmacgap_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg txdatapath_liteethmactxlastbe_state = 1'd0; +wire wait_1; +wire wb_bus_ack; +wire [29:0] wb_bus_adr; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; +wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; +wire [3:0] wb_bus_sel; +wire wb_bus_stb; +wire wb_bus_we; +wire we; +wire wishbone_interface_bus_rx_ack; +wire [29:0] wishbone_interface_bus_rx_adr; +wire [1:0] wishbone_interface_bus_rx_bte; +wire [2:0] wishbone_interface_bus_rx_cti; +wire wishbone_interface_bus_rx_cyc; +wire [31:0] wishbone_interface_bus_rx_dat_r; +wire [31:0] wishbone_interface_bus_rx_dat_w; +wire wishbone_interface_bus_rx_err; +wire [3:0] wishbone_interface_bus_rx_sel; +wire wishbone_interface_bus_rx_stb; +wire wishbone_interface_bus_rx_we; +wire wishbone_interface_bus_tx_ack; +wire [29:0] wishbone_interface_bus_tx_adr; +wire [1:0] wishbone_interface_bus_tx_bte; +wire [2:0] wishbone_interface_bus_tx_cti; +wire wishbone_interface_bus_tx_cyc; +wire [31:0] wishbone_interface_bus_tx_dat_r; +wire [31:0] wishbone_interface_bus_tx_dat_w; +wire wishbone_interface_bus_tx_err; +wire [3:0] wishbone_interface_bus_tx_sel; +wire wishbone_interface_bus_tx_stb; +wire wishbone_interface_bus_tx_we; +reg [1:0] wishbone_interface_decoder0_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder0_slave_sel_r = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel_r = 2'd0; +wire wishbone_interface_ev_irq; +reg wishbone_interface_interface0_ack = 1'd0; +wire [29:0] wishbone_interface_interface0_adr; +wire [1:0] wishbone_interface_interface0_bte; +wire [2:0] wishbone_interface_interface0_cti; +wire wishbone_interface_interface0_cyc; +wire [31:0] wishbone_interface_interface0_dat_r; +wire [31:0] wishbone_interface_interface0_dat_w; +reg wishbone_interface_interface0_err = 1'd0; +wire [3:0] wishbone_interface_interface0_sel; +wire wishbone_interface_interface0_stb; +wire wishbone_interface_interface0_we; +reg wishbone_interface_interface1_ack = 1'd0; +wire [29:0] wishbone_interface_interface1_adr; +wire [1:0] wishbone_interface_interface1_bte; +wire [2:0] wishbone_interface_interface1_cti; +wire wishbone_interface_interface1_cyc; +wire [31:0] wishbone_interface_interface1_dat_r; +wire [31:0] wishbone_interface_interface1_dat_w; +reg wishbone_interface_interface1_err = 1'd0; +wire [3:0] wishbone_interface_interface1_sel; +wire wishbone_interface_interface1_stb; +wire wishbone_interface_interface1_we; +reg wishbone_interface_interface2_ack = 1'd0; +wire [29:0] wishbone_interface_interface2_adr; +wire [1:0] wishbone_interface_interface2_bte; +wire [2:0] wishbone_interface_interface2_cti; +wire wishbone_interface_interface2_cyc; +wire [31:0] wishbone_interface_interface2_dat_r; +wire [31:0] wishbone_interface_interface2_dat_w; +reg wishbone_interface_interface2_err = 1'd0; +wire [3:0] wishbone_interface_interface2_sel; +wire wishbone_interface_interface2_stb; +wire wishbone_interface_interface2_we; +reg wishbone_interface_interface3_ack = 1'd0; +wire [29:0] wishbone_interface_interface3_adr; +wire [1:0] wishbone_interface_interface3_bte; +wire [2:0] wishbone_interface_interface3_cti; +wire wishbone_interface_interface3_cyc; +wire [31:0] wishbone_interface_interface3_dat_r; +wire [31:0] wishbone_interface_interface3_dat_w; +reg wishbone_interface_interface3_err = 1'd0; +wire [3:0] wishbone_interface_interface3_sel; +wire wishbone_interface_interface3_stb; +wire wishbone_interface_interface3_we; +reg wishbone_interface_reader_cmd_fifo_consume = 1'd0; +wire wishbone_interface_reader_cmd_fifo_do_read; +wire wishbone_interface_reader_cmd_fifo_fifo_in_first; +wire wishbone_interface_reader_cmd_fifo_fifo_in_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_in_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot; +wire wishbone_interface_reader_cmd_fifo_fifo_out_first; +wire wishbone_interface_reader_cmd_fifo_fifo_out_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_reader_cmd_fifo_level = 2'd0; +reg wishbone_interface_reader_cmd_fifo_produce = 1'd0; +wire wishbone_interface_reader_cmd_fifo_rdport_adr; +wire [13:0] wishbone_interface_reader_cmd_fifo_rdport_dat_r; +reg wishbone_interface_reader_cmd_fifo_replace = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_first = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_last = 1'd0; +wire [10:0] wishbone_interface_reader_cmd_fifo_sink_payload_length; +wire wishbone_interface_reader_cmd_fifo_sink_payload_slot; +wire wishbone_interface_reader_cmd_fifo_sink_ready; +wire wishbone_interface_reader_cmd_fifo_sink_valid; +wire wishbone_interface_reader_cmd_fifo_source_first; +wire wishbone_interface_reader_cmd_fifo_source_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_source_payload_length; +wire wishbone_interface_reader_cmd_fifo_source_payload_slot; +reg wishbone_interface_reader_cmd_fifo_source_ready = 1'd0; +wire wishbone_interface_reader_cmd_fifo_source_valid; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_din; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_dout; +wire wishbone_interface_reader_cmd_fifo_syncfifo_re; +wire wishbone_interface_reader_cmd_fifo_syncfifo_readable; +wire wishbone_interface_reader_cmd_fifo_syncfifo_we; +wire wishbone_interface_reader_cmd_fifo_syncfifo_writable; +reg wishbone_interface_reader_cmd_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_w; +wire wishbone_interface_reader_cmd_fifo_wrport_we; +reg wishbone_interface_reader_enable_re = 1'd0; +reg wishbone_interface_reader_enable_storage = 1'd0; +wire wishbone_interface_reader_event00; +wire wishbone_interface_reader_event01; +wire wishbone_interface_reader_event02; +reg wishbone_interface_reader_eventsourcepulse_clear = 1'd0; +reg wishbone_interface_reader_eventsourcepulse_pending = 1'd0; +wire wishbone_interface_reader_eventsourcepulse_status; +reg wishbone_interface_reader_eventsourcepulse_trigger = 1'd0; +wire wishbone_interface_reader_irq; +reg [10:0] wishbone_interface_reader_length = 11'd0; +reg [10:0] wishbone_interface_reader_length_liteethmacsramreader_next_value = 11'd0; +reg wishbone_interface_reader_length_liteethmacsramreader_next_value_ce = 1'd0; +reg wishbone_interface_reader_length_re = 1'd0; +reg [10:0] wishbone_interface_reader_length_storage = 11'd0; +reg wishbone_interface_reader_level_re = 1'd0; +wire [1:0] wishbone_interface_reader_level_status; +wire wishbone_interface_reader_level_we; +wire [8:0] wishbone_interface_reader_memory0_adr; +wire [31:0] wishbone_interface_reader_memory0_dat_r; +wire wishbone_interface_reader_memory0_re; +wire [8:0] wishbone_interface_reader_memory1_adr; +wire [31:0] wishbone_interface_reader_memory1_dat_r; +wire wishbone_interface_reader_memory1_re; +reg wishbone_interface_reader_pending_r = 1'd0; +reg wishbone_interface_reader_pending_re = 1'd0; +wire wishbone_interface_reader_pending_status; +wire wishbone_interface_reader_pending_we; +reg [31:0] wishbone_interface_reader_rd_data = 32'd0; +reg wishbone_interface_reader_read = 1'd0; +reg wishbone_interface_reader_ready_re = 1'd0; +wire wishbone_interface_reader_ready_status; +wire wishbone_interface_reader_ready_we; +reg wishbone_interface_reader_slot_re = 1'd0; +reg wishbone_interface_reader_slot_storage = 1'd0; +reg wishbone_interface_reader_source_source_first = 1'd0; +reg wishbone_interface_reader_source_source_last = 1'd0; +wire [31:0] wishbone_interface_reader_source_source_payload_data; +reg [3:0] wishbone_interface_reader_source_source_payload_error = 4'd0; +reg [3:0] wishbone_interface_reader_source_source_payload_last_be = 4'd0; +wire wishbone_interface_reader_source_source_ready; +reg wishbone_interface_reader_source_source_valid = 1'd0; +wire wishbone_interface_reader_start_r; +reg wishbone_interface_reader_start_re = 1'd0; +reg wishbone_interface_reader_start_w = 1'd0; +reg wishbone_interface_reader_start_we = 1'd0; +reg wishbone_interface_reader_status_re = 1'd0; +wire wishbone_interface_reader_status_status; +wire wishbone_interface_reader_status_we; +wire wishbone_interface_sink_first; +wire wishbone_interface_sink_last; +wire [31:0] wishbone_interface_sink_payload_data; +wire [3:0] wishbone_interface_sink_payload_error; +wire [3:0] wishbone_interface_sink_payload_last_be; +wire wishbone_interface_sink_ready; +wire wishbone_interface_sink_valid; +wire wishbone_interface_source_first; +wire wishbone_interface_source_last; +wire [31:0] wishbone_interface_source_payload_data; +wire [3:0] wishbone_interface_source_payload_error; +wire [3:0] wishbone_interface_source_payload_last_be; +wire wishbone_interface_source_ready; +wire wishbone_interface_source_valid; +wire [8:0] wishbone_interface_sram0_adr; +reg wishbone_interface_sram0_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram0_dat_r; +wire [8:0] wishbone_interface_sram1_adr; +reg wishbone_interface_sram1_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram1_dat_r; +wire [8:0] wishbone_interface_sram2_adr; +reg wishbone_interface_sram2_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram2_dat_r; +wire [31:0] wishbone_interface_sram2_dat_w; +reg [3:0] wishbone_interface_sram2_we = 4'd0; +wire [8:0] wishbone_interface_sram3_adr; +reg wishbone_interface_sram3_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram3_dat_r; +wire [31:0] wishbone_interface_sram3_dat_w; +reg [3:0] wishbone_interface_sram3_we = 4'd0; +wire wishbone_interface_writer_available0; +wire wishbone_interface_writer_available1; +wire wishbone_interface_writer_available2; +reg wishbone_interface_writer_available_clear = 1'd0; +wire wishbone_interface_writer_available_pending; +wire wishbone_interface_writer_available_status; +wire wishbone_interface_writer_available_trigger; +reg wishbone_interface_writer_enable_re = 1'd0; +reg wishbone_interface_writer_enable_storage = 1'd0; +reg wishbone_interface_writer_errors_re = 1'd0; +reg [31:0] wishbone_interface_writer_errors_status = 32'd0; +reg [31:0] wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value = 32'd0; +reg wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire wishbone_interface_writer_errors_we; +wire wishbone_interface_writer_irq; +reg [10:0] wishbone_interface_writer_length = 11'd0; +reg [3:0] wishbone_interface_writer_length_inc = 4'd0; +reg [10:0] wishbone_interface_writer_length_liteethmacsramwriter_t_next_value = 11'd0; +reg wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg wishbone_interface_writer_length_re = 1'd0; +wire [10:0] wishbone_interface_writer_length_status; +wire wishbone_interface_writer_length_we; +reg [8:0] wishbone_interface_writer_memory0_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory0_dat_r; +reg [31:0] wishbone_interface_writer_memory0_dat_w = 32'd0; +reg wishbone_interface_writer_memory0_we = 1'd0; +reg [8:0] wishbone_interface_writer_memory1_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory1_dat_r; +reg [31:0] wishbone_interface_writer_memory1_dat_w = 32'd0; +reg wishbone_interface_writer_memory1_we = 1'd0; +reg wishbone_interface_writer_pending_r = 1'd0; +reg wishbone_interface_writer_pending_re = 1'd0; +wire wishbone_interface_writer_pending_status; +wire wishbone_interface_writer_pending_we; +wire wishbone_interface_writer_sink_sink_first; +wire wishbone_interface_writer_sink_sink_last; +wire [31:0] wishbone_interface_writer_sink_sink_payload_data; +wire [3:0] wishbone_interface_writer_sink_sink_payload_error; +wire [3:0] wishbone_interface_writer_sink_sink_payload_last_be; +reg wishbone_interface_writer_sink_sink_ready = 1'd1; +wire wishbone_interface_writer_sink_sink_valid; +reg wishbone_interface_writer_slot = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce = 1'd0; +reg wishbone_interface_writer_slot_re = 1'd0; +wire wishbone_interface_writer_slot_status; +wire wishbone_interface_writer_slot_we; +reg wishbone_interface_writer_stat_fifo_consume = 1'd0; +wire wishbone_interface_writer_stat_fifo_do_read; +wire wishbone_interface_writer_stat_fifo_fifo_in_first; +wire wishbone_interface_writer_stat_fifo_fifo_in_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_in_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_in_payload_slot; +wire wishbone_interface_writer_stat_fifo_fifo_out_first; +wire wishbone_interface_writer_stat_fifo_fifo_out_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_writer_stat_fifo_level = 2'd0; +reg wishbone_interface_writer_stat_fifo_produce = 1'd0; +wire wishbone_interface_writer_stat_fifo_rdport_adr; +wire [13:0] wishbone_interface_writer_stat_fifo_rdport_dat_r; +reg wishbone_interface_writer_stat_fifo_replace = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_first = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_last = 1'd0; +reg [10:0] wishbone_interface_writer_stat_fifo_sink_payload_length = 11'd0; +reg wishbone_interface_writer_stat_fifo_sink_payload_slot = 1'd0; +wire wishbone_interface_writer_stat_fifo_sink_ready; +reg wishbone_interface_writer_stat_fifo_sink_valid = 1'd0; +wire wishbone_interface_writer_stat_fifo_source_first; +wire wishbone_interface_writer_stat_fifo_source_last; +wire [10:0] wishbone_interface_writer_stat_fifo_source_payload_length; +wire wishbone_interface_writer_stat_fifo_source_payload_slot; +wire wishbone_interface_writer_stat_fifo_source_ready; +wire wishbone_interface_writer_stat_fifo_source_valid; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_din; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_dout; +wire wishbone_interface_writer_stat_fifo_syncfifo_re; +wire wishbone_interface_writer_stat_fifo_syncfifo_readable; +wire wishbone_interface_writer_stat_fifo_syncfifo_we; +wire wishbone_interface_writer_stat_fifo_syncfifo_writable; +reg wishbone_interface_writer_stat_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_w; +wire wishbone_interface_writer_stat_fifo_wrport_we; +reg wishbone_interface_writer_status_re = 1'd0; +wire wishbone_interface_writer_status_status; +wire wishbone_interface_writer_status_we; +wire [31:0] wishbone_interface_writer_wr_data; +reg wishbone_interface_writer_write = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_expr; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl00 = 1'd0; +reg xilinxmultiregimpl00 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl01 = 1'd0; +reg xilinxmultiregimpl01 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl10 = 6'd0; +reg [5:0] xilinxmultiregimpl10 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl11 = 6'd0; +reg [5:0] xilinxmultiregimpl11 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +reg [5:0] xilinxmultiregimpl20 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +reg [5:0] xilinxmultiregimpl21 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl30 = 1'd0; +reg xilinxmultiregimpl30 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl31 = 1'd0; +reg xilinxmultiregimpl31 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl40 = 1'd0; +reg xilinxmultiregimpl40 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl41 = 1'd0; +reg xilinxmultiregimpl41 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl50 = 6'd0; +reg [5:0] xilinxmultiregimpl50 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl51 = 6'd0; +reg [5:0] xilinxmultiregimpl51 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +reg [5:0] xilinxmultiregimpl60 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; -(* dont_touch = "true" *) -wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) -wire eth_tx_clk; -wire eth_tx_delayed_clk; -wire eth_tx_rst; -wire main_bufferizeendpoints_pipe_valid_sink_first; -wire main_bufferizeendpoints_pipe_valid_sink_last; -wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; -wire main_bufferizeendpoints_pipe_valid_sink_payload_error; -wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; -wire main_bufferizeendpoints_pipe_valid_sink_ready; -wire main_bufferizeendpoints_pipe_valid_sink_valid; -reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; -reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; -wire main_bufferizeendpoints_pipe_valid_source_ready; -reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; -wire main_bufferizeendpoints_sink_sink_first; -wire main_bufferizeendpoints_sink_sink_last; -wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; -wire main_bufferizeendpoints_sink_sink_payload_error; -wire main_bufferizeendpoints_sink_sink_payload_last_be; -wire main_bufferizeendpoints_sink_sink_ready; -wire main_bufferizeendpoints_sink_sink_valid; -wire main_bufferizeendpoints_source_source_first; -wire main_bufferizeendpoints_source_source_last; -wire [7:0] main_bufferizeendpoints_source_source_payload_data; -wire main_bufferizeendpoints_source_source_payload_error; -wire main_bufferizeendpoints_source_source_payload_last_be; -wire main_bufferizeendpoints_source_source_ready; -wire main_bufferizeendpoints_source_source_valid; -wire main_bus_ack; -wire [29:0] main_bus_adr; -wire [1:0] main_bus_bte; -wire [2:0] main_bus_cti; -wire main_bus_cyc; -wire [31:0] main_bus_dat_r; -wire [31:0] main_bus_dat_w; -wire main_bus_err; -wire [3:0] main_bus_sel; -wire main_bus_stb; -wire main_bus_we; -reg main_crc_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_interface0_ack = 1'd0; -wire [29:0] main_interface0_adr; -wire [1:0] main_interface0_bte; -wire [2:0] main_interface0_cti; -wire main_interface0_cyc; -wire [31:0] main_interface0_dat_r; -wire [31:0] main_interface0_dat_w; -reg main_interface0_err = 1'd0; -wire [3:0] main_interface0_sel; -wire main_interface0_stb; -wire main_interface0_we; -reg main_interface1_ack = 1'd0; -wire [29:0] main_interface1_adr; -wire [1:0] main_interface1_bte; -wire [2:0] main_interface1_cti; -wire main_interface1_cyc; -wire [31:0] main_interface1_dat_r; -wire [31:0] main_interface1_dat_w; -reg main_interface1_err = 1'd0; -wire [3:0] main_interface1_sel; -wire main_interface1_stb; -wire main_interface1_we; -reg main_interface2_ack = 1'd0; -wire [29:0] main_interface2_adr; -wire [1:0] main_interface2_bte; -wire [2:0] main_interface2_cti; -wire main_interface2_cyc; -wire [31:0] main_interface2_dat_r; -wire [31:0] main_interface2_dat_w; -reg main_interface2_err = 1'd0; -wire [3:0] main_interface2_sel; -wire main_interface2_stb; -wire main_interface2_we; -reg main_interface3_ack = 1'd0; -wire [29:0] main_interface3_adr; -wire [1:0] main_interface3_bte; -wire [2:0] main_interface3_cti; -wire main_interface3_cyc; -wire [31:0] main_interface3_dat_r; -wire [31:0] main_interface3_dat_w; -reg main_interface3_err = 1'd0; -wire [3:0] main_interface3_sel; -wire main_interface3_stb; -wire main_interface3_we; -reg [3:0] main_length_inc = 4'd0; -wire main_liteethmaccrc32checker_crc_be; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; -wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -reg main_liteethmaccrc32checker_crc_error0 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; -reg main_liteethmaccrc32checker_error = 1'd0; -wire main_liteethmaccrc32checker_fifo_full; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -reg main_liteethmaccrc32checker_last_be = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -wire main_liteethmaccrc32checker_source_source_first; -reg main_liteethmaccrc32checker_source_source_last = 1'd0; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_valid = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -reg main_maccore_ethphy__r_re = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__w_re = 1'd0; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -wire main_maccore_ethphy_clkin; -wire main_maccore_ethphy_clkout0; -wire main_maccore_ethphy_clkout1; -wire main_maccore_ethphy_clkout_buf0; -wire main_maccore_ethphy_clkout_buf1; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_maccore_ethphy_data_w; -wire main_maccore_ethphy_eth_rx_clk_ibuf; -wire main_maccore_ethphy_eth_tx_clk_obuf; -wire main_maccore_ethphy_liteethphyrgmiirx; -wire main_maccore_ethphy_liteethphyrgmiirx_last; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; -reg main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; -wire [7:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data; -wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; -wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; -reg main_maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_source_last; -reg [7:0] main_maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; -reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; -reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_source_ready; -reg main_maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; -wire main_maccore_ethphy_locked; -wire main_maccore_ethphy_mdc; -wire main_maccore_ethphy_oe; -reg main_maccore_ethphy_power_down = 1'd0; -reg main_maccore_ethphy_r = 1'd0; -reg main_maccore_ethphy_reset0 = 1'd0; -wire main_maccore_ethphy_reset1; -reg main_maccore_ethphy_reset_re = 1'd0; -reg main_maccore_ethphy_reset_storage = 1'd0; -wire main_maccore_ethphy_sink_first; -wire main_maccore_ethphy_sink_last; -wire [7:0] main_maccore_ethphy_sink_payload_data; -wire main_maccore_ethphy_sink_payload_error; -wire main_maccore_ethphy_sink_payload_last_be; -wire main_maccore_ethphy_sink_ready; -wire main_maccore_ethphy_sink_valid; -wire main_maccore_ethphy_tx_ctl_obuf; -wire [3:0] main_maccore_ethphy_tx_data_obuf; -wire main_maccore_ethphy_w; -reg main_maccore_int_rst = 1'd1; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -wire main_maccore_maccore_cpu_rst; -reg main_maccore_maccore_reset_re = 1'd0; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_scratch_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_soc_rst = 1'd0; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -wire main_pulsesynchronizer0_i; -wire main_pulsesynchronizer0_o; -reg main_pulsesynchronizer0_toggle_i = 1'd0; -wire main_pulsesynchronizer0_toggle_o; -reg main_pulsesynchronizer0_toggle_o_r = 1'd0; -wire main_pulsesynchronizer1_i; -wire main_pulsesynchronizer1_o; -reg main_pulsesynchronizer1_toggle_i = 1'd0; -wire main_pulsesynchronizer1_toggle_o; -reg main_pulsesynchronizer1_toggle_o_r = 1'd0; -reg [31:0] main_rd_data = 32'd0; -reg main_re = 1'd0; -reg main_read = 1'd0; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_valid; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire main_rx_cdc_cdc_wrport_we; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_valid; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_valid; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -wire main_rx_converter_converter_source_ready; -wire main_rx_converter_converter_source_valid; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_valid; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_valid; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -wire main_rx_last_be_source_payload_error; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_valid; -wire main_rx_padding_sink_first; -wire main_rx_padding_sink_last; -wire [7:0] main_rx_padding_sink_payload_data; -wire main_rx_padding_sink_payload_error; -wire main_rx_padding_sink_payload_last_be; -wire main_rx_padding_sink_ready; -wire main_rx_padding_sink_valid; -wire main_rx_padding_source_first; -wire main_rx_padding_source_last; -wire [7:0] main_rx_padding_source_payload_data; -wire main_rx_padding_source_payload_error; -wire main_rx_padding_source_payload_last_be; -wire main_rx_padding_source_ready; -wire main_rx_padding_source_valid; -reg main_rx_preamble_error = 1'd0; -reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; -wire main_rx_preamble_sink_first; -wire main_rx_preamble_sink_last; -wire [7:0] main_rx_preamble_sink_payload_data; -wire main_rx_preamble_sink_payload_error; -wire main_rx_preamble_sink_payload_last_be; -reg main_rx_preamble_sink_ready = 1'd0; -wire main_rx_preamble_sink_valid; -reg main_rx_preamble_source_first = 1'd0; -reg main_rx_preamble_source_last = 1'd0; -wire [7:0] main_rx_preamble_source_payload_data; -reg main_rx_preamble_source_payload_error = 1'd0; -wire main_rx_preamble_source_payload_last_be; -wire main_rx_preamble_source_ready; -reg main_rx_preamble_source_valid = 1'd0; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_error; -wire [3:0] main_sink_payload_last_be; -wire main_sink_ready; -wire main_sink_sink_first; -wire main_sink_sink_last; -wire [31:0] main_sink_sink_payload_data; -wire [3:0] main_sink_sink_payload_error; -wire [3:0] main_sink_sink_payload_last_be; -wire main_sink_sink_ready; -wire main_sink_sink_valid; -wire main_sink_valid; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -reg main_slot = 1'd0; -reg main_slot_liteethmacsramwriter_next_value = 1'd0; -reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_error; -wire [3:0] main_source_payload_last_be; -wire main_source_ready; -wire main_source_source_first; -wire main_source_source_last; -wire [31:0] main_source_source_payload_data; -wire [3:0] main_source_source_payload_error; -wire [3:0] main_source_source_payload_last_be; -wire main_source_source_ready; -wire main_source_source_valid; -wire main_source_valid; -wire [8:0] main_sram0_adr; -reg main_sram0_adr_burst = 1'd0; -wire [31:0] main_sram0_dat_r; -wire main_sram0_sink_valid; -reg main_sram100_storage = 1'd0; -reg main_sram101_re = 1'd0; -reg [10:0] main_sram102_storage = 11'd0; -reg main_sram103_re = 1'd0; -wire main_sram104_irq; -wire main_sram105_status; -reg main_sram106_pending = 1'd0; -reg main_sram107_trigger = 1'd0; -reg main_sram108_clear = 1'd0; -wire main_sram109_event0; -wire [10:0] main_sram10_status; -reg main_sram110_status = 1'd0; -wire main_sram111_we; -reg main_sram112_re = 1'd0; -wire main_sram113_event0; -reg main_sram114_status = 1'd0; -wire main_sram115_we; -reg main_sram116_re = 1'd0; -reg main_sram117_r = 1'd0; -wire main_sram118_event0; -reg main_sram119_storage = 1'd0; -wire main_sram11_we; -reg main_sram120_re = 1'd0; -reg [10:0] main_sram122_length = 11'd0; -reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; -reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; -wire main_sram123_sink_valid; -wire main_sram124_sink_ready; -reg main_sram125_sink_first = 1'd0; -reg main_sram126_sink_last = 1'd0; -wire main_sram127_sink_payload_slot; -wire [10:0] main_sram128_sink_payload_length; -wire main_sram129_source_valid; -reg main_sram12_re = 1'd0; -reg main_sram130_source_ready = 1'd0; -wire main_sram131_source_first; -wire main_sram132_source_last; -wire main_sram133_source_payload_slot; -wire [10:0] main_sram134_source_payload_length; -wire main_sram135_we; -wire main_sram136_writable; -wire main_sram137_re; -wire main_sram138_readable; -wire [13:0] main_sram139_din; -reg [31:0] main_sram13_status = 32'd0; -reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; -reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; -wire [13:0] main_sram140_dout; -reg [1:0] main_sram141_level = 2'd0; -reg main_sram142_replace = 1'd0; -reg main_sram143_produce = 1'd0; -reg main_sram144_consume = 1'd0; -reg main_sram145_adr = 1'd0; -wire [13:0] main_sram146_dat_r; -wire main_sram147_we; -wire [13:0] main_sram148_dat_w; -wire main_sram149_do_read; -wire main_sram14_we; -wire main_sram150_adr; -wire [13:0] main_sram151_dat_r; -wire main_sram152_fifo_in_payload_slot; -wire [10:0] main_sram153_fifo_in_payload_length; -wire main_sram154_fifo_in_first; -wire main_sram155_fifo_in_last; -wire main_sram156_fifo_out_payload_slot; -wire [10:0] main_sram157_fifo_out_payload_length; -wire main_sram158_fifo_out_first; -wire main_sram159_fifo_out_last; -reg main_sram15_re = 1'd0; -wire [8:0] main_sram161_adr; -wire [31:0] main_sram162_dat_r; -wire main_sram163_re; -wire [8:0] main_sram164_adr; -wire [31:0] main_sram165_dat_r; -wire main_sram166_re; -wire main_sram167_irq; -wire main_sram16_irq; -wire main_sram17_status; -wire main_sram18_pending; -wire main_sram19_trigger; -wire [8:0] main_sram1_adr; -reg main_sram1_adr_burst = 1'd0; -wire [31:0] main_sram1_dat_r; -reg main_sram1_sink_ready = 1'd1; -reg main_sram20_clear = 1'd0; -wire main_sram21_available; -reg main_sram22_status = 1'd0; -wire main_sram23_we; -reg main_sram24_re = 1'd0; -wire main_sram25_available; -reg main_sram26_status = 1'd0; -wire main_sram27_we; -reg main_sram28_re = 1'd0; -reg main_sram29_r = 1'd0; -wire [8:0] main_sram2_adr; -reg main_sram2_adr_burst = 1'd0; -wire [31:0] main_sram2_dat_r; -wire [31:0] main_sram2_dat_w; -wire main_sram2_sink_first; -reg [3:0] main_sram2_we = 4'd0; -wire main_sram30_available; -reg main_sram31_storage = 1'd0; -reg main_sram32_re = 1'd0; -reg [10:0] main_sram35_length = 11'd0; -reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; -reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; -reg main_sram37_sink_valid = 1'd0; -wire main_sram38_sink_ready; -reg main_sram39_sink_first = 1'd0; -wire [8:0] main_sram3_adr; -reg main_sram3_adr_burst = 1'd0; -wire [31:0] main_sram3_dat_r; -wire [31:0] main_sram3_dat_w; -wire main_sram3_sink_last; -reg [3:0] main_sram3_we = 4'd0; -reg main_sram40_sink_last = 1'd0; -reg main_sram41_sink_payload_slot = 1'd0; -reg [10:0] main_sram42_sink_payload_length = 11'd0; -wire main_sram43_source_valid; -wire main_sram44_source_ready; -wire main_sram45_source_first; -wire main_sram46_source_last; -wire main_sram47_source_payload_slot; -wire [10:0] main_sram48_source_payload_length; -wire main_sram49_we; -wire [31:0] main_sram4_sink_payload_data; -wire main_sram50_writable; -wire main_sram51_re; -wire main_sram52_readable; -wire [13:0] main_sram53_din; -wire [13:0] main_sram54_dout; -reg [1:0] main_sram55_level = 2'd0; -reg main_sram56_replace = 1'd0; -reg main_sram57_produce = 1'd0; -reg main_sram58_consume = 1'd0; -reg main_sram59_adr = 1'd0; -wire [3:0] main_sram5_sink_payload_last_be; -wire [13:0] main_sram60_dat_r; -wire main_sram61_we; -wire [13:0] main_sram62_dat_w; -wire main_sram63_do_read; -wire main_sram64_adr; -wire [13:0] main_sram65_dat_r; -wire main_sram66_fifo_in_payload_slot; -wire [10:0] main_sram67_fifo_in_payload_length; -wire main_sram68_fifo_in_first; -wire main_sram69_fifo_in_last; -wire [3:0] main_sram6_sink_payload_error; -wire main_sram70_fifo_out_payload_slot; -wire [10:0] main_sram71_fifo_out_payload_length; -wire main_sram72_fifo_out_first; -wire main_sram73_fifo_out_last; -reg [8:0] main_sram75_adr = 9'd0; -wire [31:0] main_sram76_dat_r; -reg main_sram77_we = 1'd0; -reg [31:0] main_sram78_dat_w = 32'd0; -reg [8:0] main_sram79_adr = 9'd0; -wire main_sram7_status; -wire [31:0] main_sram80_dat_r; -reg main_sram81_we = 1'd0; -reg [31:0] main_sram82_dat_w = 32'd0; -reg main_sram83_source_valid = 1'd0; -wire main_sram84_source_ready; -reg main_sram85_source_first = 1'd0; -reg main_sram86_source_last = 1'd0; -wire [31:0] main_sram87_source_payload_data; -reg [3:0] main_sram88_source_payload_last_be = 4'd0; -reg [3:0] main_sram89_source_payload_error = 4'd0; -wire main_sram8_we; -wire main_sram94_status; -wire main_sram95_we; -reg main_sram96_re = 1'd0; -wire [1:0] main_sram97_status; -wire main_sram98_we; -reg main_sram99_re = 1'd0; -reg main_sram9_re = 1'd0; -wire main_start_r; -reg main_start_re = 1'd0; -reg main_start_w = 1'd0; -reg main_start_we = 1'd0; -reg main_status = 1'd1; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_valid; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire main_tx_cdc_cdc_wrport_we; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_valid; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_error; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_valid; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_valid; -wire main_tx_crc_be; -reg main_tx_crc_ce = 1'd0; -reg [1:0] main_tx_crc_cnt = 2'd3; -wire main_tx_crc_cnt_done; -reg [31:0] main_tx_crc_crc_next = 32'd0; -reg [31:0] main_tx_crc_crc_packet = 32'd0; -reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; -reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; -wire [31:0] main_tx_crc_crc_prev; -wire [7:0] main_tx_crc_data0; -wire [7:0] main_tx_crc_data1; -reg main_tx_crc_error = 1'd0; -reg main_tx_crc_is_ongoing0 = 1'd0; -reg main_tx_crc_is_ongoing1 = 1'd0; -reg main_tx_crc_last_be = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; -wire main_tx_crc_pipe_valid_sink_first; -wire main_tx_crc_pipe_valid_sink_last; -wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; -wire main_tx_crc_pipe_valid_sink_payload_error; -wire main_tx_crc_pipe_valid_sink_payload_last_be; -wire main_tx_crc_pipe_valid_sink_ready; -wire main_tx_crc_pipe_valid_sink_valid; -reg main_tx_crc_pipe_valid_source_first = 1'd0; -reg main_tx_crc_pipe_valid_source_last = 1'd0; -reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; -reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; -reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; -wire main_tx_crc_pipe_valid_source_ready; -reg main_tx_crc_pipe_valid_source_valid = 1'd0; -reg [31:0] main_tx_crc_reg = 32'd4294967295; -reg main_tx_crc_reset = 1'd0; -wire main_tx_crc_sink_first; -wire main_tx_crc_sink_last; -wire [7:0] main_tx_crc_sink_payload_data; -wire main_tx_crc_sink_payload_error; -wire main_tx_crc_sink_payload_last_be; -reg main_tx_crc_sink_ready = 1'd0; -wire main_tx_crc_sink_sink_first; -wire main_tx_crc_sink_sink_last; -wire [7:0] main_tx_crc_sink_sink_payload_data; -wire main_tx_crc_sink_sink_payload_error; -wire main_tx_crc_sink_sink_payload_last_be; -wire main_tx_crc_sink_sink_ready; -wire main_tx_crc_sink_sink_valid; -wire main_tx_crc_sink_valid; -reg main_tx_crc_source_first = 1'd0; -reg main_tx_crc_source_last = 1'd0; -reg [7:0] main_tx_crc_source_payload_data = 8'd0; -reg main_tx_crc_source_payload_error = 1'd0; -reg main_tx_crc_source_payload_last_be = 1'd0; -wire main_tx_crc_source_ready; -wire main_tx_crc_source_source_first; -wire main_tx_crc_source_source_last; -wire [7:0] main_tx_crc_source_source_payload_data; -wire main_tx_crc_source_source_payload_error; -wire main_tx_crc_source_source_payload_last_be; -wire main_tx_crc_source_source_ready; -wire main_tx_crc_source_source_valid; -reg main_tx_crc_source_valid = 1'd0; -reg [31:0] main_tx_crc_value = 32'd0; -reg [3:0] main_tx_gap_counter = 4'd0; -reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; -reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; -wire main_tx_gap_sink_first; -wire main_tx_gap_sink_last; -wire [7:0] main_tx_gap_sink_payload_data; -wire main_tx_gap_sink_payload_error; -wire main_tx_gap_sink_payload_last_be; -reg main_tx_gap_sink_ready = 1'd0; -wire main_tx_gap_sink_valid; -reg main_tx_gap_source_first = 1'd0; -reg main_tx_gap_source_last = 1'd0; -reg [7:0] main_tx_gap_source_payload_data = 8'd0; -reg main_tx_gap_source_payload_error = 1'd0; -reg main_tx_gap_source_payload_last_be = 1'd0; -wire main_tx_gap_source_ready; -reg main_tx_gap_source_valid = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_error; -wire main_tx_last_be_sink_payload_last_be; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_valid = 1'd0; -reg [15:0] main_tx_padding_counter = 16'd0; -reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; -reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; -wire main_tx_padding_counter_done; -wire main_tx_padding_sink_first; -wire main_tx_padding_sink_last; -wire [7:0] main_tx_padding_sink_payload_data; -wire main_tx_padding_sink_payload_error; -wire main_tx_padding_sink_payload_last_be; -reg main_tx_padding_sink_ready = 1'd0; -wire main_tx_padding_sink_valid; -reg main_tx_padding_source_first = 1'd0; -reg main_tx_padding_source_last = 1'd0; -reg [7:0] main_tx_padding_source_payload_data = 8'd0; -reg main_tx_padding_source_payload_error = 1'd0; -reg main_tx_padding_source_payload_last_be = 1'd0; -wire main_tx_padding_source_ready; -reg main_tx_padding_source_valid = 1'd0; -reg [2:0] main_tx_preamble_count = 3'd0; -reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; -reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; -reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; -wire main_tx_preamble_sink_first; -wire main_tx_preamble_sink_last; -wire [7:0] main_tx_preamble_sink_payload_data; -wire main_tx_preamble_sink_payload_error; -wire main_tx_preamble_sink_payload_last_be; -reg main_tx_preamble_sink_ready = 1'd0; -wire main_tx_preamble_sink_valid; -reg main_tx_preamble_source_first = 1'd0; -reg main_tx_preamble_source_last = 1'd0; -reg [7:0] main_tx_preamble_source_payload_data = 8'd0; -reg main_tx_preamble_source_payload_error = 1'd0; -wire main_tx_preamble_source_payload_last_be; -wire main_tx_preamble_source_ready; -reg main_tx_preamble_source_valid = 1'd0; -wire main_wb_bus_ack; -wire [29:0] main_wb_bus_adr; -wire [1:0] main_wb_bus_bte; -wire [2:0] main_wb_bus_cti; -wire main_wb_bus_cyc; -wire [31:0] main_wb_bus_dat_r; -wire [31:0] main_wb_bus_dat_w; -wire main_wb_bus_err; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_stb; -wire main_wb_bus_we; -wire main_we; -wire [31:0] main_wr_data; -reg main_write = 1'd0; -wire por_clk; -(* dont_touch = "true" *) -wire sys_clk; -wire sys_rst; +reg [5:0] xilinxmultiregimpl61 = 6'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign main_wb_bus_adr = wishbone_adr; -assign main_wb_bus_dat_w = wishbone_dat_w; -assign wishbone_dat_r = main_wb_bus_dat_r; -assign main_wb_bus_sel = wishbone_sel; -assign main_wb_bus_cyc = wishbone_cyc; -assign main_wb_bus_stb = wishbone_stb; -assign wishbone_ack = main_wb_bus_ack; -assign main_wb_bus_we = wishbone_we; -assign main_wb_bus_cti = wishbone_cti; -assign main_wb_bus_bte = wishbone_bte; -assign wishbone_err = main_wb_bus_err; -assign interrupt = main_sram167_irq; -assign main_maccore_maccore_bus_error = builder_error; -assign builder_shared_adr = builder_self0; -assign builder_shared_dat_w = builder_self1; -assign builder_shared_sel = builder_self2; -assign builder_shared_cyc = builder_self3; -assign builder_shared_stb = builder_self4; -assign builder_shared_we = builder_self5; -assign builder_shared_cti = builder_self6; -assign builder_shared_bte = builder_self7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; +assign wb_bus_adr = wishbone_adr; +assign wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wishbone_sel; +assign wb_bus_cyc = wishbone_cyc; +assign wb_bus_stb = wishbone_stb; +assign wishbone_ack = wb_bus_ack; +assign wb_bus_we = wishbone_we; +assign wb_bus_cti = wishbone_cti; +assign wb_bus_bte = wishbone_bte; +assign wishbone_err = wb_bus_err; +assign interrupt = wishbone_interface_ev_irq; +assign maccore_maccore_bus_error = error; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign wb_bus_dat_r = shared_dat_r; +assign wb_bus_ack = (shared_ack & (grant == 1'd0)); +assign wb_bus_err = (shared_err & (grant == 1'd0)); +assign request = {wb_bus_cyc}; +assign grant = 1'd0; always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); + slave_sel <= 3'd0; + slave_sel[0] <= (shared_adr[29:10] == 5'd16); + slave_sel[1] <= (shared_adr[29:10] == 5'd17); + slave_sel[2] <= (shared_adr[29:14] == 1'd0); end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_interface0_adr = builder_shared_adr; -assign builder_interface0_dat_w = builder_shared_dat_w; -assign builder_interface0_sel = builder_shared_sel; -assign builder_interface0_stb = builder_shared_stb; -assign builder_interface0_we = builder_shared_we; -assign builder_interface0_cti = builder_shared_cti; -assign builder_interface0_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_interface0_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +assign wishbone_interface_bus_rx_adr = shared_adr; +assign wishbone_interface_bus_rx_dat_w = shared_dat_w; +assign wishbone_interface_bus_rx_sel = shared_sel; +assign wishbone_interface_bus_rx_stb = shared_stb; +assign wishbone_interface_bus_rx_we = shared_we; +assign wishbone_interface_bus_rx_cti = shared_cti; +assign wishbone_interface_bus_rx_bte = shared_bte; +assign wishbone_interface_bus_tx_adr = shared_adr; +assign wishbone_interface_bus_tx_dat_w = shared_dat_w; +assign wishbone_interface_bus_tx_sel = shared_sel; +assign wishbone_interface_bus_tx_stb = shared_stb; +assign wishbone_interface_bus_tx_we = shared_we; +assign wishbone_interface_bus_tx_cti = shared_cti; +assign wishbone_interface_bus_tx_bte = shared_bte; +assign interface0_adr = shared_adr; +assign interface0_dat_w = shared_dat_w; +assign interface0_sel = shared_sel; +assign interface0_stb = shared_stb; +assign interface0_we = shared_we; +assign interface0_cti = shared_cti; +assign interface0_bte = shared_bte; +assign wishbone_interface_bus_rx_cyc = (shared_cyc & slave_sel[0]); +assign wishbone_interface_bus_tx_cyc = (shared_cyc & slave_sel[1]); +assign interface0_cyc = (shared_cyc & slave_sel[2]); +assign shared_err = ((wishbone_interface_bus_rx_err | wishbone_interface_bus_tx_err) | interface0_err); +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); always @(*) begin - builder_error <= 1'd0; - builder_shared_ack <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_interface0_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= ((wishbone_interface_bus_rx_ack | wishbone_interface_bus_tx_ack) | interface0_ack); + shared_dat_r <= ((({32{slave_sel_r[0]}} & wishbone_interface_bus_rx_dat_r) | ({32{slave_sel_r[1]}} & wishbone_interface_bus_tx_dat_r)) | ({32{slave_sel_r[2]}} & interface0_dat_r)); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; end end -assign builder_done = (builder_count == 1'd0); -assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign done = (count == 1'd0); +assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; -assign sys_rst = main_maccore_int_rst; -assign main_maccore_ethphy_reset1 = main_maccore_ethphy_reset_storage; -assign rgmii_rst_n = (~main_maccore_ethphy_reset1); -assign main_maccore_ethphy_clkin = eth_rx_clk; -assign eth_tx_clk = main_maccore_ethphy_clkout_buf0; -assign eth_tx_delayed_clk = main_maccore_ethphy_clkout_buf1; -assign main_maccore_ethphy_sink_ready = 1'd1; -assign main_maccore_ethphy_liteethphyrgmiirx_last = ((~main_maccore_ethphy_liteethphyrgmiirx_rx_ctl) & main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d); -assign main_maccore_ethphy_liteethphyrgmiirx_source_last = main_maccore_ethphy_liteethphyrgmiirx_last; -assign rgmii_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_sink_valid = main_source_source_valid; -assign main_source_source_ready = main_sink_ready; -assign main_sink_first = main_source_source_first; -assign main_sink_last = main_source_source_last; -assign main_sink_payload_data = main_source_source_payload_data; -assign main_sink_payload_last_be = main_source_source_payload_last_be; -assign main_sink_payload_error = main_source_source_payload_error; -assign main_sink_sink_valid = main_source_valid; -assign main_source_ready = main_sink_sink_ready; -assign main_sink_sink_first = main_source_first; -assign main_sink_sink_last = main_source_last; -assign main_sink_sink_payload_data = main_source_payload_data; -assign main_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_sink_sink_payload_error = main_source_payload_error; -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +assign sys_rst = maccore_int_rst; +assign maccore_ethphy_reset1 = maccore_ethphy_reset_storage; +assign rgmii_rst_n = (~maccore_ethphy_reset1); +assign maccore_ethphy_clkin = eth_rx_clk; +assign eth_tx_clk = maccore_ethphy_clkout_buf0; +assign eth_tx_delayed_clk = maccore_ethphy_clkout_buf1; +assign maccore_ethphy_sink_ready = 1'd1; +assign maccore_ethphy_liteethphyrgmiirx_last = ((~maccore_ethphy_liteethphyrgmiirx_rx_ctl) & maccore_ethphy_liteethphyrgmiirx_rx_ctl_d); +assign maccore_ethphy_liteethphyrgmiirx_source_last = maccore_ethphy_liteethphyrgmiirx_last; +assign rgmii_mdc = maccore_ethphy__w_storage[0]; +assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1]; +assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2]; +assign core_sink_valid = wishbone_interface_source_valid; +assign wishbone_interface_source_ready = core_sink_ready; +assign core_sink_first = wishbone_interface_source_first; +assign core_sink_last = wishbone_interface_source_last; +assign core_sink_payload_data = wishbone_interface_source_payload_data; +assign core_sink_payload_last_be = wishbone_interface_source_payload_last_be; +assign core_sink_payload_error = wishbone_interface_source_payload_error; +assign wishbone_interface_sink_valid = core_source_valid; +assign core_source_ready = wishbone_interface_sink_ready; +assign wishbone_interface_sink_first = core_source_first; +assign wishbone_interface_sink_last = core_source_last; +assign wishbone_interface_sink_payload_data = core_source_payload_data; +assign wishbone_interface_sink_payload_last_be = core_source_payload_last_be; +assign wishbone_interface_sink_payload_error = core_source_payload_error; +assign core_tx_cdc_cdc_sink_valid = core_tx_cdc_sink_sink_valid; +assign core_tx_cdc_sink_sink_ready = core_tx_cdc_cdc_sink_ready; +assign core_tx_cdc_cdc_sink_first = core_tx_cdc_sink_sink_first; +assign core_tx_cdc_cdc_sink_last = core_tx_cdc_sink_sink_last; +assign core_tx_cdc_cdc_sink_payload_data = core_tx_cdc_sink_sink_payload_data; +assign core_tx_cdc_cdc_sink_payload_last_be = core_tx_cdc_sink_sink_payload_last_be; +assign core_tx_cdc_cdc_sink_payload_error = core_tx_cdc_sink_sink_payload_error; +assign core_tx_cdc_source_source_valid = core_tx_cdc_cdc_source_valid; +assign core_tx_cdc_cdc_source_ready = core_tx_cdc_source_source_ready; +assign core_tx_cdc_source_source_first = core_tx_cdc_cdc_source_first; +assign core_tx_cdc_source_source_last = core_tx_cdc_cdc_source_last; +assign core_tx_cdc_source_source_payload_data = core_tx_cdc_cdc_source_payload_data; +assign core_tx_cdc_source_source_payload_last_be = core_tx_cdc_cdc_source_payload_last_be; +assign core_tx_cdc_source_source_payload_error = core_tx_cdc_cdc_source_payload_error; +assign core_tx_cdc_cdc_asyncfifo_din = {core_tx_cdc_cdc_fifo_in_last, core_tx_cdc_cdc_fifo_in_first, core_tx_cdc_cdc_fifo_in_payload_error, core_tx_cdc_cdc_fifo_in_payload_last_be, core_tx_cdc_cdc_fifo_in_payload_data}; +assign {core_tx_cdc_cdc_fifo_out_last, core_tx_cdc_cdc_fifo_out_first, core_tx_cdc_cdc_fifo_out_payload_error, core_tx_cdc_cdc_fifo_out_payload_last_be, core_tx_cdc_cdc_fifo_out_payload_data} = core_tx_cdc_cdc_asyncfifo_dout; +assign core_tx_cdc_cdc_sink_ready = core_tx_cdc_cdc_asyncfifo_writable; +assign core_tx_cdc_cdc_asyncfifo_we = core_tx_cdc_cdc_sink_valid; +assign core_tx_cdc_cdc_fifo_in_first = core_tx_cdc_cdc_sink_first; +assign core_tx_cdc_cdc_fifo_in_last = core_tx_cdc_cdc_sink_last; +assign core_tx_cdc_cdc_fifo_in_payload_data = core_tx_cdc_cdc_sink_payload_data; +assign core_tx_cdc_cdc_fifo_in_payload_last_be = core_tx_cdc_cdc_sink_payload_last_be; +assign core_tx_cdc_cdc_fifo_in_payload_error = core_tx_cdc_cdc_sink_payload_error; +assign core_tx_cdc_cdc_source_valid = core_tx_cdc_cdc_asyncfifo_readable; +assign core_tx_cdc_cdc_source_first = core_tx_cdc_cdc_fifo_out_first; +assign core_tx_cdc_cdc_source_last = core_tx_cdc_cdc_fifo_out_last; +assign core_tx_cdc_cdc_source_payload_data = core_tx_cdc_cdc_fifo_out_payload_data; +assign core_tx_cdc_cdc_source_payload_last_be = core_tx_cdc_cdc_fifo_out_payload_last_be; +assign core_tx_cdc_cdc_source_payload_error = core_tx_cdc_cdc_fifo_out_payload_error; +assign core_tx_cdc_cdc_asyncfifo_re = core_tx_cdc_cdc_source_ready; +assign core_tx_cdc_cdc_graycounter0_ce = (core_tx_cdc_cdc_asyncfifo_writable & core_tx_cdc_cdc_asyncfifo_we); +assign core_tx_cdc_cdc_graycounter1_ce = (core_tx_cdc_cdc_asyncfifo_readable & core_tx_cdc_cdc_asyncfifo_re); +assign core_tx_cdc_cdc_asyncfifo_writable = (((core_tx_cdc_cdc_graycounter0_q[5] == core_tx_cdc_cdc_consume_wdomain[5]) | (core_tx_cdc_cdc_graycounter0_q[4] == core_tx_cdc_cdc_consume_wdomain[4])) | (core_tx_cdc_cdc_graycounter0_q[3:0] != core_tx_cdc_cdc_consume_wdomain[3:0])); +assign core_tx_cdc_cdc_asyncfifo_readable = (core_tx_cdc_cdc_graycounter1_q != core_tx_cdc_cdc_produce_rdomain); +assign core_tx_cdc_cdc_wrport_adr = core_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_tx_cdc_cdc_wrport_dat_w = core_tx_cdc_cdc_asyncfifo_din; +assign core_tx_cdc_cdc_wrport_we = core_tx_cdc_cdc_graycounter0_ce; +assign core_tx_cdc_cdc_rdport_adr = core_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_tx_cdc_cdc_asyncfifo_dout = core_tx_cdc_cdc_rdport_dat_r; always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter0_ce) begin + core_tx_cdc_cdc_graycounter0_q_next_binary <= (core_tx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + core_tx_cdc_cdc_graycounter0_q_next_binary <= core_tx_cdc_cdc_graycounter0_q_binary; end end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_tx_cdc_cdc_graycounter0_q_next = (core_tx_cdc_cdc_graycounter0_q_next_binary ^ core_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter1_ce) begin + core_tx_cdc_cdc_graycounter1_q_next_binary <= (core_tx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + core_tx_cdc_cdc_graycounter1_q_next_binary <= core_tx_cdc_cdc_graycounter1_q_binary; end end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +assign core_tx_cdc_cdc_graycounter1_q_next = (core_tx_cdc_cdc_graycounter1_q_next_binary ^ core_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_tx_converter_converter_sink_valid = core_tx_converter_sink_valid; +assign core_tx_converter_converter_sink_first = core_tx_converter_sink_first; +assign core_tx_converter_converter_sink_last = core_tx_converter_sink_last; +assign core_tx_converter_sink_ready = core_tx_converter_converter_sink_ready; always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; + core_tx_converter_converter_sink_payload_data <= 40'd0; + core_tx_converter_converter_sink_payload_data[7:0] <= core_tx_converter_sink_payload_data[7:0]; + core_tx_converter_converter_sink_payload_data[8] <= core_tx_converter_sink_payload_last_be[0]; + core_tx_converter_converter_sink_payload_data[9] <= core_tx_converter_sink_payload_error[0]; + core_tx_converter_converter_sink_payload_data[17:10] <= core_tx_converter_sink_payload_data[15:8]; + core_tx_converter_converter_sink_payload_data[18] <= core_tx_converter_sink_payload_last_be[1]; + core_tx_converter_converter_sink_payload_data[19] <= core_tx_converter_sink_payload_error[1]; + core_tx_converter_converter_sink_payload_data[27:20] <= core_tx_converter_sink_payload_data[23:16]; + core_tx_converter_converter_sink_payload_data[28] <= core_tx_converter_sink_payload_last_be[2]; + core_tx_converter_converter_sink_payload_data[29] <= core_tx_converter_sink_payload_error[2]; + core_tx_converter_converter_sink_payload_data[37:30] <= core_tx_converter_sink_payload_data[31:24]; + core_tx_converter_converter_sink_payload_data[38] <= core_tx_converter_sink_payload_last_be[3]; + core_tx_converter_converter_sink_payload_data[39] <= core_tx_converter_sink_payload_error[3]; end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +assign core_tx_converter_source_valid = core_tx_converter_source_source_valid; +assign core_tx_converter_source_first = core_tx_converter_source_source_first; +assign core_tx_converter_source_last = core_tx_converter_source_source_last; +assign core_tx_converter_source_source_ready = core_tx_converter_source_ready; +assign {core_tx_converter_source_payload_error, core_tx_converter_source_payload_last_be, core_tx_converter_source_payload_data} = core_tx_converter_source_source_payload_data; +assign core_tx_converter_source_source_valid = core_tx_converter_converter_source_valid; +assign core_tx_converter_converter_source_ready = core_tx_converter_source_source_ready; +assign core_tx_converter_source_source_first = core_tx_converter_converter_source_first; +assign core_tx_converter_source_source_last = core_tx_converter_converter_source_last; +assign core_tx_converter_source_source_payload_data = core_tx_converter_converter_source_payload_data; +assign core_tx_converter_converter_first = (core_tx_converter_converter_mux == 1'd0); +assign core_tx_converter_converter_last = (core_tx_converter_converter_mux == 2'd3); +assign core_tx_converter_converter_source_valid = core_tx_converter_converter_sink_valid; +assign core_tx_converter_converter_source_first = (core_tx_converter_converter_sink_first & core_tx_converter_converter_first); +assign core_tx_converter_converter_source_last = (core_tx_converter_converter_sink_last & core_tx_converter_converter_last); +assign core_tx_converter_converter_sink_ready = (core_tx_converter_converter_last & core_tx_converter_converter_source_ready); always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) + core_tx_converter_converter_source_payload_data <= 10'd0; + case (core_tx_converter_converter_mux) 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[9:0]; end 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[19:10]; end 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[29:20]; end default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[39:30]; end endcase end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +assign core_tx_converter_converter_source_payload_valid_token_count = core_tx_converter_converter_last; +assign core_tx_last_be_last_handler_sink_valid = core_tx_last_be_sink_sink_valid; +assign core_tx_last_be_sink_sink_ready = core_tx_last_be_last_handler_sink_ready; +assign core_tx_last_be_last_handler_sink_first = core_tx_last_be_sink_sink_first; +assign core_tx_last_be_last_handler_sink_last = core_tx_last_be_sink_sink_last; +assign core_tx_last_be_last_handler_sink_payload_data = core_tx_last_be_sink_sink_payload_data; +assign core_tx_last_be_last_handler_sink_payload_last_be = core_tx_last_be_sink_sink_payload_last_be; +assign core_tx_last_be_last_handler_sink_payload_error = core_tx_last_be_sink_sink_payload_error; +assign core_tx_last_be_source_source_valid = core_tx_last_be_last_handler_source_valid; +assign core_tx_last_be_last_handler_source_ready = core_tx_last_be_source_source_ready; +assign core_tx_last_be_source_source_first = core_tx_last_be_last_handler_source_first; +assign core_tx_last_be_source_source_last = core_tx_last_be_last_handler_source_last; +assign core_tx_last_be_source_source_payload_data = core_tx_last_be_last_handler_source_payload_data; +assign core_tx_last_be_source_source_payload_last_be = core_tx_last_be_last_handler_source_payload_last_be; +assign core_tx_last_be_source_source_payload_error = core_tx_last_be_last_handler_source_payload_error; always @(*) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - main_tx_last_be_source_payload_last_be <= 1'd0; - main_tx_last_be_source_valid <= 1'd0; - builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; - case (builder_txdatapath_liteethmactxlastbe_state) + core_tx_last_be_last_handler_sink_ready <= 1'd0; + core_tx_last_be_last_handler_source_first <= 1'd0; + core_tx_last_be_last_handler_source_last <= 1'd0; + core_tx_last_be_last_handler_source_payload_data <= 8'd0; + core_tx_last_be_last_handler_source_payload_error <= 1'd0; + core_tx_last_be_last_handler_source_payload_last_be <= 1'd0; + core_tx_last_be_last_handler_source_valid <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= txdatapath_liteethmactxlastbe_state; + case (txdatapath_liteethmactxlastbe_state) 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + core_tx_last_be_last_handler_sink_ready <= 1'd1; + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_last)) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd0; end end default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_last <= main_tx_last_be_sink_last; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + core_tx_last_be_last_handler_source_valid <= core_tx_last_be_last_handler_sink_valid; + core_tx_last_be_last_handler_sink_ready <= core_tx_last_be_last_handler_source_ready; + core_tx_last_be_last_handler_source_first <= core_tx_last_be_last_handler_sink_first; + core_tx_last_be_last_handler_source_last <= core_tx_last_be_last_handler_sink_last; + core_tx_last_be_last_handler_source_payload_data <= core_tx_last_be_last_handler_sink_payload_data; + core_tx_last_be_last_handler_source_payload_last_be <= core_tx_last_be_last_handler_sink_payload_last_be; + core_tx_last_be_last_handler_source_payload_error <= core_tx_last_be_last_handler_sink_payload_error; + core_tx_last_be_last_handler_source_last <= (core_tx_last_be_last_handler_sink_payload_last_be != 1'd0); + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_ready)) begin + if ((core_tx_last_be_last_handler_source_last & (~core_tx_last_be_last_handler_sink_last))) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd1; end end end endcase end -assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +assign core_tx_padding_counter_done = (core_tx_padding_counter >= 6'd59); always @(*) begin - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; - main_tx_padding_sink_ready <= 1'd0; - main_tx_padding_source_first <= 1'd0; - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_data <= 8'd0; - main_tx_padding_source_payload_error <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - main_tx_padding_source_valid <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; - case (builder_txdatapath_liteethmacpaddinginserter_state) + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + core_tx_padding_sink_ready <= 1'd0; + core_tx_padding_source_first <= 1'd0; + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_data <= 8'd0; + core_tx_padding_source_payload_error <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + core_tx_padding_source_valid <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= txdatapath_liteethmacpaddinginserter_state; + case (txdatapath_liteethmacpaddinginserter_state) 1'd1: begin - main_tx_padding_source_valid <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_source_payload_last_be <= 1'd1; - main_tx_padding_source_last <= 1'd1; + core_tx_padding_source_valid <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_source_payload_last_be <= 1'd1; + core_tx_padding_source_last <= 1'd1; end - main_tx_padding_source_payload_data <= 1'd0; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + core_tx_padding_source_payload_data <= 1'd0; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; end end end default: begin - main_tx_padding_source_valid <= main_tx_padding_sink_valid; - main_tx_padding_sink_ready <= main_tx_padding_source_ready; - main_tx_padding_source_first <= main_tx_padding_sink_first; - main_tx_padding_source_last <= main_tx_padding_sink_last; - main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; - main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; - main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_sink_last) begin - if ((~main_tx_padding_counter_done)) begin - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + core_tx_padding_source_valid <= core_tx_padding_sink_valid; + core_tx_padding_sink_ready <= core_tx_padding_source_ready; + core_tx_padding_source_first <= core_tx_padding_sink_first; + core_tx_padding_source_last <= core_tx_padding_sink_last; + core_tx_padding_source_payload_data <= core_tx_padding_sink_payload_data; + core_tx_padding_source_payload_last_be <= core_tx_padding_sink_payload_last_be; + core_tx_padding_source_payload_error <= core_tx_padding_sink_payload_error; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_sink_last) begin + if ((~core_tx_padding_counter_done)) begin + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; end else begin - if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin - main_tx_padding_source_payload_last_be <= 1'd1; + if (((core_tx_padding_counter == 6'd59) & (core_tx_padding_sink_payload_last_be < 1'd1))) begin + core_tx_padding_source_payload_last_be <= 1'd1; end else begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; end end end @@ -1652,1562 +1645,1495 @@ always @(*) begin end endcase end -assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; -assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; -assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); -assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; -assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; -assign main_tx_crc_sink_first = main_tx_crc_source_source_first; -assign main_tx_crc_sink_last = main_tx_crc_source_source_last; -assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; -assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; -assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; -assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; -assign main_tx_crc_crc_prev = main_tx_crc_reg; +assign core_tx_crc_data0 = core_tx_crc_sink_payload_data; +assign core_tx_crc_be = core_tx_crc_sink_payload_last_be; +assign core_tx_crc_cnt_done = (core_tx_crc_cnt == 1'd0); +assign core_tx_crc_sink_valid = core_tx_crc_source_source_valid; +assign core_tx_crc_source_source_ready = core_tx_crc_sink_ready; +assign core_tx_crc_sink_first = core_tx_crc_source_source_first; +assign core_tx_crc_sink_last = core_tx_crc_source_source_last; +assign core_tx_crc_sink_payload_data = core_tx_crc_source_source_payload_data; +assign core_tx_crc_sink_payload_last_be = core_tx_crc_source_source_payload_last_be; +assign core_tx_crc_sink_payload_error = core_tx_crc_source_source_payload_error; +assign core_tx_crc_data1 = core_tx_crc_data0; +assign core_tx_crc_crc_prev = core_tx_crc_reg; always @(*) begin - main_tx_crc_error <= 1'd0; - main_tx_crc_value <= 32'd0; - if (main_tx_crc_be) begin - main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; - main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + core_tx_crc_error <= 1'd0; + core_tx_crc_value <= 32'd0; + if (core_tx_crc_be) begin + core_tx_crc_value <= ({core_tx_crc_crc_next[0], core_tx_crc_crc_next[1], core_tx_crc_crc_next[2], core_tx_crc_crc_next[3], core_tx_crc_crc_next[4], core_tx_crc_crc_next[5], core_tx_crc_crc_next[6], core_tx_crc_crc_next[7], core_tx_crc_crc_next[8], core_tx_crc_crc_next[9], core_tx_crc_crc_next[10], core_tx_crc_crc_next[11], core_tx_crc_crc_next[12], core_tx_crc_crc_next[13], core_tx_crc_crc_next[14], core_tx_crc_crc_next[15], core_tx_crc_crc_next[16], core_tx_crc_crc_next[17], core_tx_crc_crc_next[18], core_tx_crc_crc_next[19], core_tx_crc_crc_next[20], core_tx_crc_crc_next[21], core_tx_crc_crc_next[22], core_tx_crc_crc_next[23], core_tx_crc_crc_next[24], core_tx_crc_crc_next[25], core_tx_crc_crc_next[26], core_tx_crc_crc_next[27], core_tx_crc_crc_next[28], core_tx_crc_crc_next[29], core_tx_crc_crc_next[30], core_tx_crc_crc_next[31]} ^ 32'd4294967295); + core_tx_crc_error <= (core_tx_crc_crc_next != 32'd3338984827); end end always @(*) begin - main_tx_crc_crc_next <= 32'd0; - main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); - main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + core_tx_crc_crc_next <= 32'd0; + core_tx_crc_crc_next[0] <= (((core_tx_crc_crc_prev[24] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[1] <= (((((((core_tx_crc_crc_prev[25] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[2] <= (((((((((core_tx_crc_crc_prev[26] ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[3] <= (((((((core_tx_crc_crc_prev[27] ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[4] <= (((((((((core_tx_crc_crc_prev[28] ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[5] <= (((((((((((((core_tx_crc_crc_prev[29] ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[6] <= (((((((((((core_tx_crc_crc_prev[30] ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[7] <= (((((((((core_tx_crc_crc_prev[31] ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[8] <= ((((((((core_tx_crc_crc_prev[0] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[9] <= ((((((((core_tx_crc_crc_prev[1] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[10] <= ((((((((core_tx_crc_crc_prev[2] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[11] <= ((((((((core_tx_crc_crc_prev[3] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[12] <= ((((((((((((core_tx_crc_crc_prev[4] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[13] <= ((((((((((((core_tx_crc_crc_prev[5] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[14] <= ((((((((((core_tx_crc_crc_prev[6] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[15] <= ((((((((core_tx_crc_crc_prev[7] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[16] <= ((((((core_tx_crc_crc_prev[8] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[17] <= ((((((core_tx_crc_crc_prev[9] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[18] <= ((((((core_tx_crc_crc_prev[10] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[19] <= ((((core_tx_crc_crc_prev[11] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[20] <= ((core_tx_crc_crc_prev[12] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[21] <= ((core_tx_crc_crc_prev[13] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); + core_tx_crc_crc_next[22] <= ((core_tx_crc_crc_prev[14] ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[23] <= ((((((core_tx_crc_crc_prev[15] ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[24] <= ((((((core_tx_crc_crc_prev[16] ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[25] <= ((((core_tx_crc_crc_prev[17] ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[26] <= ((((((((core_tx_crc_crc_prev[18] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[27] <= ((((((((core_tx_crc_crc_prev[19] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[28] <= ((((((core_tx_crc_crc_prev[20] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[29] <= ((((((core_tx_crc_crc_prev[21] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[30] <= ((((core_tx_crc_crc_prev[22] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[31] <= ((core_tx_crc_crc_prev[23] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); end always @(*) begin - builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; - main_tx_crc_ce <= 1'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; - main_tx_crc_is_ongoing0 <= 1'd0; - main_tx_crc_is_ongoing1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; - main_tx_crc_reset <= 1'd0; - main_tx_crc_sink_ready <= 1'd0; - main_tx_crc_source_first <= 1'd0; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_data <= 8'd0; - main_tx_crc_source_payload_error <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - main_tx_crc_source_valid <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; - case (builder_txdatapath_bufferizeendpoints_state) + core_tx_crc_ce <= 1'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + core_tx_crc_is_ongoing0 <= 1'd0; + core_tx_crc_is_ongoing1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + core_tx_crc_reset <= 1'd0; + core_tx_crc_sink_ready <= 1'd0; + core_tx_crc_source_first <= 1'd0; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_data <= 8'd0; + core_tx_crc_source_payload_error <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + core_tx_crc_source_valid <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 2'd0; + txdatapath_bufferizeendpoints_next_state <= txdatapath_bufferizeendpoints_state; + case (txdatapath_bufferizeendpoints_state) 1'd1: begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); - main_tx_crc_source_valid <= main_tx_crc_sink_valid; - main_tx_crc_sink_ready <= main_tx_crc_source_ready; - main_tx_crc_source_first <= main_tx_crc_sink_first; - main_tx_crc_source_last <= main_tx_crc_sink_last; - main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; - main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; - main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - if (main_tx_crc_sink_last) begin - if (main_tx_crc_sink_payload_last_be) begin - main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + core_tx_crc_ce <= (core_tx_crc_sink_valid & core_tx_crc_source_ready); + core_tx_crc_source_valid <= core_tx_crc_sink_valid; + core_tx_crc_sink_ready <= core_tx_crc_source_ready; + core_tx_crc_source_first <= core_tx_crc_sink_first; + core_tx_crc_source_last <= core_tx_crc_sink_last; + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; + core_tx_crc_source_payload_last_be <= core_tx_crc_sink_payload_last_be; + core_tx_crc_source_payload_error <= core_tx_crc_sink_payload_error; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + if (core_tx_crc_sink_last) begin + if (core_tx_crc_sink_payload_last_be) begin + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; end - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - main_tx_crc_source_last <= 1'd1; - main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + core_tx_crc_source_last <= 1'd1; + core_tx_crc_source_payload_last_be <= (core_tx_crc_sink_payload_last_be <<< -3'd3); end - end else begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); end - if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (((core_tx_crc_sink_valid & core_tx_crc_sink_last) & core_tx_crc_source_ready)) begin + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end else begin - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= core_tx_crc_value; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; if (1'd0) begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (core_tx_crc_sink_payload_last_be >>> 3'd4); + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end else begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= core_tx_crc_sink_payload_last_be; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end - builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + txdatapath_bufferizeendpoints_next_state <= 2'd2; end end end 2'd2: begin - main_tx_crc_source_valid <= 1'd1; - case (main_tx_crc_cnt) + core_tx_crc_source_valid <= 1'd1; + case (core_tx_crc_cnt) 1'd0: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[31:24]; end 1'd1: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[23:16]; end 2'd2: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[15:8]; end default: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[7:0]; end endcase - if (main_tx_crc_cnt_done) begin - main_tx_crc_source_last <= 1'd1; - if (main_tx_crc_source_ready) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_tx_crc_cnt_done) begin + core_tx_crc_source_last <= 1'd1; + if (core_tx_crc_source_ready) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end end - main_tx_crc_is_ongoing1 <= 1'd1; + core_tx_crc_is_ongoing1 <= 1'd1; end default: begin - main_tx_crc_reset <= 1'd1; - main_tx_crc_sink_ready <= 1'd1; - if (main_tx_crc_sink_valid) begin - main_tx_crc_sink_ready <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + core_tx_crc_reset <= 1'd1; + core_tx_crc_sink_ready <= 1'd1; + if (core_tx_crc_sink_valid) begin + core_tx_crc_sink_ready <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 1'd1; end - main_tx_crc_is_ongoing0 <= 1'd1; + core_tx_crc_is_ongoing0 <= 1'd1; end endcase end -assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); -assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; -assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; -assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; -assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; -assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; -assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; -assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; -assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; -assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; -assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; -assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; -assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; -assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; -assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; -assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_ready = ((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready); +assign core_tx_crc_pipe_valid_sink_valid = core_tx_crc_sink_sink_valid; +assign core_tx_crc_sink_sink_ready = core_tx_crc_pipe_valid_sink_ready; +assign core_tx_crc_pipe_valid_sink_first = core_tx_crc_sink_sink_first; +assign core_tx_crc_pipe_valid_sink_last = core_tx_crc_sink_sink_last; +assign core_tx_crc_pipe_valid_sink_payload_data = core_tx_crc_sink_sink_payload_data; +assign core_tx_crc_pipe_valid_sink_payload_last_be = core_tx_crc_sink_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_payload_error = core_tx_crc_sink_sink_payload_error; +assign core_tx_crc_source_source_valid = core_tx_crc_pipe_valid_source_valid; +assign core_tx_crc_pipe_valid_source_ready = core_tx_crc_source_source_ready; +assign core_tx_crc_source_source_first = core_tx_crc_pipe_valid_source_first; +assign core_tx_crc_source_source_last = core_tx_crc_pipe_valid_source_last; +assign core_tx_crc_source_source_payload_data = core_tx_crc_pipe_valid_source_payload_data; +assign core_tx_crc_source_source_payload_last_be = core_tx_crc_pipe_valid_source_payload_last_be; +assign core_tx_crc_source_source_payload_error = core_tx_crc_pipe_valid_source_payload_error; +assign core_tx_preamble_source_payload_last_be = core_tx_preamble_sink_payload_last_be; always @(*) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; - main_tx_preamble_sink_ready <= 1'd0; - main_tx_preamble_source_first <= 1'd0; - main_tx_preamble_source_last <= 1'd0; - main_tx_preamble_source_payload_data <= 8'd0; - main_tx_preamble_source_payload_error <= 1'd0; - main_tx_preamble_source_valid <= 1'd0; - main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; - builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; - case (builder_txdatapath_liteethmacpreambleinserter_state) + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + core_tx_preamble_sink_ready <= 1'd0; + core_tx_preamble_source_first <= 1'd0; + core_tx_preamble_source_last <= 1'd0; + core_tx_preamble_source_payload_data <= 8'd0; + core_tx_preamble_source_payload_error <= 1'd0; + core_tx_preamble_source_valid <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + core_tx_preamble_source_payload_data <= core_tx_preamble_sink_payload_data; + txdatapath_liteethmacpreambleinserter_next_state <= txdatapath_liteethmacpreambleinserter_state; + case (txdatapath_liteethmacpreambleinserter_state) 1'd1: begin - main_tx_preamble_source_valid <= 1'd1; - case (main_tx_preamble_count) + core_tx_preamble_source_valid <= 1'd1; + case (core_tx_preamble_count) 1'd0: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[7:0]; end 1'd1: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[15:8]; end 2'd2: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[23:16]; end 2'd3: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[31:24]; end 3'd4: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[39:32]; end 3'd5: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[47:40]; end 3'd6: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[55:48]; end default: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[63:56]; end endcase - if (main_tx_preamble_source_ready) begin - if ((main_tx_preamble_count == 3'd7)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + if (core_tx_preamble_source_ready) begin + if ((core_tx_preamble_count == 3'd7)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; end else begin - main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= (core_tx_preamble_count + 1'd1); + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; end end end 2'd2: begin - main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; - main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; - main_tx_preamble_source_first <= main_tx_preamble_sink_first; - main_tx_preamble_source_last <= main_tx_preamble_sink_last; - main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; - if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + core_tx_preamble_source_valid <= core_tx_preamble_sink_valid; + core_tx_preamble_sink_ready <= core_tx_preamble_source_ready; + core_tx_preamble_source_first <= core_tx_preamble_sink_first; + core_tx_preamble_source_last <= core_tx_preamble_sink_last; + core_tx_preamble_source_payload_error <= core_tx_preamble_sink_payload_error; + if (((core_tx_preamble_sink_valid & core_tx_preamble_sink_last) & core_tx_preamble_source_ready)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; end end default: begin - main_tx_preamble_sink_ready <= 1'd1; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; - if (main_tx_preamble_sink_valid) begin - main_tx_preamble_sink_ready <= 1'd0; - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + core_tx_preamble_sink_ready <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (core_tx_preamble_sink_valid) begin + core_tx_preamble_sink_ready <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; end end endcase end always @(*) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; - main_tx_gap_sink_ready <= 1'd0; - main_tx_gap_source_first <= 1'd0; - main_tx_gap_source_last <= 1'd0; - main_tx_gap_source_payload_data <= 8'd0; - main_tx_gap_source_payload_error <= 1'd0; - main_tx_gap_source_payload_last_be <= 1'd0; - main_tx_gap_source_valid <= 1'd0; - builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; - case (builder_txdatapath_liteethmacgap_state) + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + core_tx_gap_sink_ready <= 1'd0; + core_tx_gap_source_first <= 1'd0; + core_tx_gap_source_last <= 1'd0; + core_tx_gap_source_payload_data <= 8'd0; + core_tx_gap_source_payload_error <= 1'd0; + core_tx_gap_source_payload_last_be <= 1'd0; + core_tx_gap_source_valid <= 1'd0; + txdatapath_liteethmacgap_next_state <= 1'd0; + txdatapath_liteethmacgap_next_state <= txdatapath_liteethmacgap_state; + case (txdatapath_liteethmacgap_state) 1'd1: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - if ((main_tx_gap_counter == 4'd11)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= (core_tx_gap_counter + 1'd1); + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((core_tx_gap_counter == 4'd11)) begin + txdatapath_liteethmacgap_next_state <= 1'd0; end end default: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - main_tx_gap_source_valid <= main_tx_gap_sink_valid; - main_tx_gap_sink_ready <= main_tx_gap_source_ready; - main_tx_gap_source_first <= main_tx_gap_sink_first; - main_tx_gap_source_last <= main_tx_gap_sink_last; - main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; - main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; - main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; - if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd1; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + core_tx_gap_source_valid <= core_tx_gap_sink_valid; + core_tx_gap_sink_ready <= core_tx_gap_source_ready; + core_tx_gap_source_first <= core_tx_gap_sink_first; + core_tx_gap_source_last <= core_tx_gap_sink_last; + core_tx_gap_source_payload_data <= core_tx_gap_sink_payload_data; + core_tx_gap_source_payload_last_be <= core_tx_gap_sink_payload_last_be; + core_tx_gap_source_payload_error <= core_tx_gap_sink_payload_error; + if (((core_tx_gap_sink_valid & core_tx_gap_sink_last) & core_tx_gap_sink_ready)) begin + txdatapath_liteethmacgap_next_state <= 1'd1; end end endcase end -assign main_tx_cdc_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_sink_first; -assign main_tx_cdc_sink_sink_last = main_sink_last; -assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; -assign main_tx_padding_sink_first = main_tx_last_be_source_first; -assign main_tx_padding_sink_last = main_tx_last_be_source_last; -assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; -assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; -assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; -assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; -assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; -assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; -assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; -assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; -assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; -assign main_tx_preamble_sink_first = main_tx_crc_source_first; -assign main_tx_preamble_sink_last = main_tx_crc_source_last; -assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; -assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; -assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; -assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; -assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; -assign main_tx_gap_sink_first = main_tx_preamble_source_first; -assign main_tx_gap_sink_last = main_tx_preamble_source_last; -assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; -assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; -assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; -assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; -assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; -assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; -assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; -assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; -assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; -assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; -assign main_pulsesynchronizer0_i = main_rx_preamble_error; -assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; -assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; -assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +assign core_tx_cdc_sink_sink_valid = core_sink_valid; +assign core_sink_ready = core_tx_cdc_sink_sink_ready; +assign core_tx_cdc_sink_sink_first = core_sink_first; +assign core_tx_cdc_sink_sink_last = core_sink_last; +assign core_tx_cdc_sink_sink_payload_data = core_sink_payload_data; +assign core_tx_cdc_sink_sink_payload_last_be = core_sink_payload_last_be; +assign core_tx_cdc_sink_sink_payload_error = core_sink_payload_error; +assign core_tx_converter_sink_valid = core_tx_cdc_source_source_valid; +assign core_tx_cdc_source_source_ready = core_tx_converter_sink_ready; +assign core_tx_converter_sink_first = core_tx_cdc_source_source_first; +assign core_tx_converter_sink_last = core_tx_cdc_source_source_last; +assign core_tx_converter_sink_payload_data = core_tx_cdc_source_source_payload_data; +assign core_tx_converter_sink_payload_last_be = core_tx_cdc_source_source_payload_last_be; +assign core_tx_converter_sink_payload_error = core_tx_cdc_source_source_payload_error; +assign core_tx_last_be_sink_sink_valid = core_tx_converter_source_valid; +assign core_tx_converter_source_ready = core_tx_last_be_sink_sink_ready; +assign core_tx_last_be_sink_sink_first = core_tx_converter_source_first; +assign core_tx_last_be_sink_sink_last = core_tx_converter_source_last; +assign core_tx_last_be_sink_sink_payload_data = core_tx_converter_source_payload_data; +assign core_tx_last_be_sink_sink_payload_last_be = core_tx_converter_source_payload_last_be; +assign core_tx_last_be_sink_sink_payload_error = core_tx_converter_source_payload_error; +assign core_tx_padding_sink_valid = core_tx_last_be_source_source_valid; +assign core_tx_last_be_source_source_ready = core_tx_padding_sink_ready; +assign core_tx_padding_sink_first = core_tx_last_be_source_source_first; +assign core_tx_padding_sink_last = core_tx_last_be_source_source_last; +assign core_tx_padding_sink_payload_data = core_tx_last_be_source_source_payload_data; +assign core_tx_padding_sink_payload_last_be = core_tx_last_be_source_source_payload_last_be; +assign core_tx_padding_sink_payload_error = core_tx_last_be_source_source_payload_error; +assign core_tx_crc_sink_sink_valid = core_tx_padding_source_valid; +assign core_tx_padding_source_ready = core_tx_crc_sink_sink_ready; +assign core_tx_crc_sink_sink_first = core_tx_padding_source_first; +assign core_tx_crc_sink_sink_last = core_tx_padding_source_last; +assign core_tx_crc_sink_sink_payload_data = core_tx_padding_source_payload_data; +assign core_tx_crc_sink_sink_payload_last_be = core_tx_padding_source_payload_last_be; +assign core_tx_crc_sink_sink_payload_error = core_tx_padding_source_payload_error; +assign core_tx_preamble_sink_valid = core_tx_crc_source_valid; +assign core_tx_crc_source_ready = core_tx_preamble_sink_ready; +assign core_tx_preamble_sink_first = core_tx_crc_source_first; +assign core_tx_preamble_sink_last = core_tx_crc_source_last; +assign core_tx_preamble_sink_payload_data = core_tx_crc_source_payload_data; +assign core_tx_preamble_sink_payload_last_be = core_tx_crc_source_payload_last_be; +assign core_tx_preamble_sink_payload_error = core_tx_crc_source_payload_error; +assign core_tx_gap_sink_valid = core_tx_preamble_source_valid; +assign core_tx_preamble_source_ready = core_tx_gap_sink_ready; +assign core_tx_gap_sink_first = core_tx_preamble_source_first; +assign core_tx_gap_sink_last = core_tx_preamble_source_last; +assign core_tx_gap_sink_payload_data = core_tx_preamble_source_payload_data; +assign core_tx_gap_sink_payload_last_be = core_tx_preamble_source_payload_last_be; +assign core_tx_gap_sink_payload_error = core_tx_preamble_source_payload_error; +assign maccore_ethphy_sink_valid = core_tx_gap_source_valid; +assign core_tx_gap_source_ready = maccore_ethphy_sink_ready; +assign maccore_ethphy_sink_first = core_tx_gap_source_first; +assign maccore_ethphy_sink_last = core_tx_gap_source_last; +assign maccore_ethphy_sink_payload_data = core_tx_gap_source_payload_data; +assign maccore_ethphy_sink_payload_last_be = core_tx_gap_source_payload_last_be; +assign maccore_ethphy_sink_payload_error = core_tx_gap_source_payload_error; +assign core_pulsesynchronizer0_i = core_rx_preamble_error; +assign core_pulsesynchronizer1_i = core_liteethmaccrc32checker_error; +assign core_rx_preamble_source_payload_data = core_rx_preamble_sink_payload_data; +assign core_rx_preamble_source_payload_last_be = core_rx_preamble_sink_payload_last_be; always @(*) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; - main_rx_preamble_error <= 1'd0; - main_rx_preamble_sink_ready <= 1'd0; - main_rx_preamble_source_first <= 1'd0; - main_rx_preamble_source_last <= 1'd0; - main_rx_preamble_source_payload_error <= 1'd0; - main_rx_preamble_source_valid <= 1'd0; - builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; - case (builder_rxdatapath_liteethmacpreamblechecker_state) + core_rx_preamble_error <= 1'd0; + core_rx_preamble_sink_ready <= 1'd0; + core_rx_preamble_source_first <= 1'd0; + core_rx_preamble_source_last <= 1'd0; + core_rx_preamble_source_payload_error <= 1'd0; + core_rx_preamble_source_valid <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= rxdatapath_liteethmacpreamblechecker_state; + case (rxdatapath_liteethmacpreamblechecker_state) 1'd1: begin - main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; - main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; - main_rx_preamble_source_first <= main_rx_preamble_sink_first; - main_rx_preamble_source_last <= main_rx_preamble_sink_last; - main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; - if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + core_rx_preamble_source_valid <= core_rx_preamble_sink_valid; + core_rx_preamble_sink_ready <= core_rx_preamble_source_ready; + core_rx_preamble_source_first <= core_rx_preamble_sink_first; + core_rx_preamble_source_last <= core_rx_preamble_sink_last; + core_rx_preamble_source_payload_error <= core_rx_preamble_sink_payload_error; + if (((core_rx_preamble_source_valid & core_rx_preamble_source_last) & core_rx_preamble_source_ready)) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; end end default: begin - main_rx_preamble_sink_ready <= 1'd1; - if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + core_rx_preamble_sink_ready <= 1'd1; + if (((core_rx_preamble_sink_valid & (~core_rx_preamble_sink_last)) & (core_rx_preamble_sink_payload_data == core_rx_preamble_preamble[63:56]))) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; end - if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin - main_rx_preamble_error <= 1'd1; + if ((core_rx_preamble_sink_valid & core_rx_preamble_sink_last)) begin + core_rx_preamble_error <= 1'd1; end end endcase end -assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); -assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); -assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); -assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); -assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; -assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +assign core_pulsesynchronizer0_o = (core_pulsesynchronizer0_toggle_o ^ core_pulsesynchronizer0_toggle_o_r); +assign core_liteethmaccrc32checker_fifo_full = (core_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign core_liteethmaccrc32checker_fifo_in = (core_liteethmaccrc32checker_sink_sink_valid & ((~core_liteethmaccrc32checker_fifo_full) | core_liteethmaccrc32checker_fifo_out)); +assign core_liteethmaccrc32checker_fifo_out = (core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready); +assign core_liteethmaccrc32checker_syncfifo_sink_first = core_liteethmaccrc32checker_sink_sink_first; +assign core_liteethmaccrc32checker_syncfifo_sink_last = core_liteethmaccrc32checker_sink_sink_last; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_data = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_last_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_error = core_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; + core_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_sink_sink_valid; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_fifo_in; end always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + core_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_syncfifo_sink_ready; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; -assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; -assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; -assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +assign core_liteethmaccrc32checker_crc_data0 = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_crc_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_source_source_first = core_liteethmaccrc32checker_syncfifo_source_first; +assign core_liteethmaccrc32checker_source_source_payload_data = core_liteethmaccrc32checker_syncfifo_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_valid = core_bufferizeendpoints_source_source_valid; +assign core_bufferizeendpoints_source_source_ready = core_liteethmaccrc32checker_sink_sink_ready; +assign core_liteethmaccrc32checker_sink_sink_first = core_bufferizeendpoints_source_source_first; +assign core_liteethmaccrc32checker_sink_sink_last = core_bufferizeendpoints_source_source_last; +assign core_liteethmaccrc32checker_sink_sink_payload_data = core_bufferizeendpoints_source_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_payload_last_be = core_bufferizeendpoints_source_source_payload_last_be; +assign core_liteethmaccrc32checker_sink_sink_payload_error = core_bufferizeendpoints_source_source_payload_error; +assign core_liteethmaccrc32checker_crc_data1 = core_liteethmaccrc32checker_crc_data0; +assign core_liteethmaccrc32checker_crc_crc_prev = core_liteethmaccrc32checker_crc_reg; always @(*) begin - main_liteethmaccrc32checker_crc_error0 <= 1'd0; - main_liteethmaccrc32checker_crc_value <= 32'd0; - if (main_liteethmaccrc32checker_crc_be) begin - main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; - main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + core_liteethmaccrc32checker_crc_error0 <= 1'd0; + core_liteethmaccrc32checker_crc_value <= 32'd0; + if (core_liteethmaccrc32checker_crc_be) begin + core_liteethmaccrc32checker_crc_value <= ({core_liteethmaccrc32checker_crc_crc_next[0], core_liteethmaccrc32checker_crc_crc_next[1], core_liteethmaccrc32checker_crc_crc_next[2], core_liteethmaccrc32checker_crc_crc_next[3], core_liteethmaccrc32checker_crc_crc_next[4], core_liteethmaccrc32checker_crc_crc_next[5], core_liteethmaccrc32checker_crc_crc_next[6], core_liteethmaccrc32checker_crc_crc_next[7], core_liteethmaccrc32checker_crc_crc_next[8], core_liteethmaccrc32checker_crc_crc_next[9], core_liteethmaccrc32checker_crc_crc_next[10], core_liteethmaccrc32checker_crc_crc_next[11], core_liteethmaccrc32checker_crc_crc_next[12], core_liteethmaccrc32checker_crc_crc_next[13], core_liteethmaccrc32checker_crc_crc_next[14], core_liteethmaccrc32checker_crc_crc_next[15], core_liteethmaccrc32checker_crc_crc_next[16], core_liteethmaccrc32checker_crc_crc_next[17], core_liteethmaccrc32checker_crc_crc_next[18], core_liteethmaccrc32checker_crc_crc_next[19], core_liteethmaccrc32checker_crc_crc_next[20], core_liteethmaccrc32checker_crc_crc_next[21], core_liteethmaccrc32checker_crc_crc_next[22], core_liteethmaccrc32checker_crc_crc_next[23], core_liteethmaccrc32checker_crc_crc_next[24], core_liteethmaccrc32checker_crc_crc_next[25], core_liteethmaccrc32checker_crc_crc_next[26], core_liteethmaccrc32checker_crc_crc_next[27], core_liteethmaccrc32checker_crc_crc_next[28], core_liteethmaccrc32checker_crc_crc_next[29], core_liteethmaccrc32checker_crc_crc_next[30], core_liteethmaccrc32checker_crc_crc_next[31]} ^ 32'd4294967295); + core_liteethmaccrc32checker_crc_error0 <= (core_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); end end always @(*) begin - main_liteethmaccrc32checker_crc_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next <= 32'd0; + core_liteethmaccrc32checker_crc_crc_next[0] <= (((core_liteethmaccrc32checker_crc_crc_prev[24] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[1] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[25] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[26] ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[3] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[27] ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[28] ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((core_liteethmaccrc32checker_crc_crc_prev[29] ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((core_liteethmaccrc32checker_crc_crc_prev[30] ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[31] ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[0] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[1] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[2] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[3] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[4] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[5] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((core_liteethmaccrc32checker_crc_crc_prev[6] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[7] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[16] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[8] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[17] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[9] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[18] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[10] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[19] <= ((((core_liteethmaccrc32checker_crc_crc_prev[11] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[20] <= ((core_liteethmaccrc32checker_crc_crc_prev[12] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[21] <= ((core_liteethmaccrc32checker_crc_crc_prev[13] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next[22] <= ((core_liteethmaccrc32checker_crc_crc_prev[14] ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[23] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[15] ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[24] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[16] ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[25] <= ((((core_liteethmaccrc32checker_crc_crc_prev[17] ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[18] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[19] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[28] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[20] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[29] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[21] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[30] <= ((((core_liteethmaccrc32checker_crc_crc_prev[22] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[31] <= ((core_liteethmaccrc32checker_crc_crc_prev[23] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); end -assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; -assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; -assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; -assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; -assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_din = {core_liteethmaccrc32checker_syncfifo_fifo_in_last, core_liteethmaccrc32checker_syncfifo_fifo_in_first, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {core_liteethmaccrc32checker_syncfifo_fifo_out_last, core_liteethmaccrc32checker_syncfifo_fifo_out_first, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign core_liteethmaccrc32checker_syncfifo_sink_ready = core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_we = core_liteethmaccrc32checker_syncfifo_sink_valid; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_first = core_liteethmaccrc32checker_syncfifo_sink_first; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_last = core_liteethmaccrc32checker_syncfifo_sink_last; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = core_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = core_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign core_liteethmaccrc32checker_syncfifo_source_valid = core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign core_liteethmaccrc32checker_syncfifo_source_first = core_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign core_liteethmaccrc32checker_syncfifo_source_last = core_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign core_liteethmaccrc32checker_syncfifo_source_payload_data = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign core_liteethmaccrc32checker_syncfifo_source_payload_last_be = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_source_payload_error = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_re = core_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + core_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (core_liteethmaccrc32checker_syncfifo_replace) begin + core_liteethmaccrc32checker_syncfifo_wrport_adr <= (core_liteethmaccrc32checker_syncfifo_produce - 1'd1); end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + core_liteethmaccrc32checker_syncfifo_wrport_adr <= core_liteethmaccrc32checker_syncfifo_produce; end end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; -assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); -assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); -assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); -assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_w = core_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign core_liteethmaccrc32checker_syncfifo_wrport_we = (core_liteethmaccrc32checker_syncfifo_syncfifo_we & (core_liteethmaccrc32checker_syncfifo_syncfifo_writable | core_liteethmaccrc32checker_syncfifo_replace)); +assign core_liteethmaccrc32checker_syncfifo_do_read = (core_liteethmaccrc32checker_syncfifo_syncfifo_readable & core_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign core_liteethmaccrc32checker_syncfifo_rdport_adr = core_liteethmaccrc32checker_syncfifo_consume; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_dout = core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_writable = (core_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign core_liteethmaccrc32checker_syncfifo_syncfifo_readable = (core_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - main_liteethmaccrc32checker_error <= 1'd0; - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; - main_liteethmaccrc32checker_source_source_last <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; - main_liteethmaccrc32checker_source_source_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; - case (builder_rxdatapath_bufferizeendpoints_state) + core_liteethmaccrc32checker_crc_ce <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + core_liteethmaccrc32checker_crc_reset <= 1'd0; + core_liteethmaccrc32checker_error <= 1'd0; + core_liteethmaccrc32checker_fifo_reset <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + core_liteethmaccrc32checker_source_source_last <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + rxdatapath_bufferizeendpoints_next_state <= 2'd0; + core_liteethmaccrc32checker_source_source_payload_error <= core_liteethmaccrc32checker_syncfifo_source_payload_error; + rxdatapath_bufferizeendpoints_next_state <= rxdatapath_bufferizeendpoints_state; + case (rxdatapath_bufferizeendpoints_state) 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 2'd2; end end 2'd2: begin - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; - main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_fifo_out; + core_liteethmaccrc32checker_source_source_valid <= (core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_fifo_full); if (1'd1) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_sink_sink_payload_last_be; end else begin - if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + if ((core_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= (core_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); end else begin - main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; - main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + core_liteethmaccrc32checker_last_be_next_value0 <= (core_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + core_liteethmaccrc32checker_crc_error1_next_value1 <= core_liteethmaccrc32checker_crc_error0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; end end - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); - main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_sink_sink_payload_error | {1{(core_liteethmaccrc32checker_crc_error0 & core_liteethmaccrc32checker_sink_sink_last)}}); + core_liteethmaccrc32checker_error <= ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_last) & core_liteethmaccrc32checker_crc_error0); + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((core_liteethmaccrc32checker_sink_sink_last & (core_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + rxdatapath_bufferizeendpoints_next_state <= 2'd3; end else begin - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_liteethmaccrc32checker_sink_sink_last) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end end end 2'd3: begin - main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; - if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= core_liteethmaccrc32checker_syncfifo_source_valid; + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_source_source_ready; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_syncfifo_source_last; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_syncfifo_source_payload_error | {1{core_liteethmaccrc32checker_crc_error1}}); + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_last_be; + if ((core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready)) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + core_liteethmaccrc32checker_crc_reset <= 1'd1; + core_liteethmaccrc32checker_fifo_reset <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 1'd1; end endcase end -assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); -assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; -assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; -assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; -assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; -assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; -assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; -assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; -assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; -assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; -assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; -assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; -assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; -assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; -assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; -assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); -assign main_rx_padding_source_valid = main_rx_padding_sink_valid; -assign main_rx_padding_sink_ready = main_rx_padding_source_ready; -assign main_rx_padding_source_first = main_rx_padding_sink_first; -assign main_rx_padding_source_last = main_rx_padding_sink_last; -assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; -assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; -assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; -assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; -assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; -assign main_rx_last_be_source_first = main_rx_last_be_sink_first; -assign main_rx_last_be_source_last = main_rx_last_be_sink_last; -assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; -assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +assign core_bufferizeendpoints_pipe_valid_sink_ready = ((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready); +assign core_bufferizeendpoints_pipe_valid_sink_valid = core_bufferizeendpoints_sink_sink_valid; +assign core_bufferizeendpoints_sink_sink_ready = core_bufferizeendpoints_pipe_valid_sink_ready; +assign core_bufferizeendpoints_pipe_valid_sink_first = core_bufferizeendpoints_sink_sink_first; +assign core_bufferizeendpoints_pipe_valid_sink_last = core_bufferizeendpoints_sink_sink_last; +assign core_bufferizeendpoints_pipe_valid_sink_payload_data = core_bufferizeendpoints_sink_sink_payload_data; +assign core_bufferizeendpoints_pipe_valid_sink_payload_last_be = core_bufferizeendpoints_sink_sink_payload_last_be; +assign core_bufferizeendpoints_pipe_valid_sink_payload_error = core_bufferizeendpoints_sink_sink_payload_error; +assign core_bufferizeendpoints_source_source_valid = core_bufferizeendpoints_pipe_valid_source_valid; +assign core_bufferizeendpoints_pipe_valid_source_ready = core_bufferizeendpoints_source_source_ready; +assign core_bufferizeendpoints_source_source_first = core_bufferizeendpoints_pipe_valid_source_first; +assign core_bufferizeendpoints_source_source_last = core_bufferizeendpoints_pipe_valid_source_last; +assign core_bufferizeendpoints_source_source_payload_data = core_bufferizeendpoints_pipe_valid_source_payload_data; +assign core_bufferizeendpoints_source_source_payload_last_be = core_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign core_bufferizeendpoints_source_source_payload_error = core_bufferizeendpoints_pipe_valid_source_payload_error; +assign core_pulsesynchronizer1_o = (core_pulsesynchronizer1_toggle_o ^ core_pulsesynchronizer1_toggle_o_r); +assign core_rx_padding_source_valid = core_rx_padding_sink_valid; +assign core_rx_padding_sink_ready = core_rx_padding_source_ready; +assign core_rx_padding_source_first = core_rx_padding_sink_first; +assign core_rx_padding_source_last = core_rx_padding_sink_last; +assign core_rx_padding_source_payload_data = core_rx_padding_sink_payload_data; +assign core_rx_padding_source_payload_last_be = core_rx_padding_sink_payload_last_be; +assign core_rx_padding_source_payload_error = core_rx_padding_sink_payload_error; +assign core_rx_last_be_source_valid = core_rx_last_be_sink_valid; +assign core_rx_last_be_sink_ready = core_rx_last_be_source_ready; +assign core_rx_last_be_source_first = core_rx_last_be_sink_first; +assign core_rx_last_be_source_last = core_rx_last_be_sink_last; +assign core_rx_last_be_source_payload_data = core_rx_last_be_sink_payload_data; +assign core_rx_last_be_source_payload_error = core_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + core_rx_last_be_source_payload_last_be <= 1'd0; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_payload_last_be; if (1'd1) begin - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_last; end end -assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; -assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; -assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; -assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; -assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; -assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; -assign main_rx_converter_source_first = main_rx_converter_source_source_first; -assign main_rx_converter_source_last = main_rx_converter_source_source_last; -assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +assign core_rx_converter_converter_sink_valid = core_rx_converter_sink_valid; +assign core_rx_converter_converter_sink_first = core_rx_converter_sink_first; +assign core_rx_converter_converter_sink_last = core_rx_converter_sink_last; +assign core_rx_converter_sink_ready = core_rx_converter_converter_sink_ready; +assign core_rx_converter_converter_sink_payload_data = {core_rx_converter_sink_payload_error, core_rx_converter_sink_payload_last_be, core_rx_converter_sink_payload_data}; +assign core_rx_converter_source_valid = core_rx_converter_source_source_valid; +assign core_rx_converter_source_first = core_rx_converter_source_source_first; +assign core_rx_converter_source_last = core_rx_converter_source_source_last; +assign core_rx_converter_source_source_ready = core_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + core_rx_converter_source_payload_data <= 32'd0; + core_rx_converter_source_payload_data[7:0] <= core_rx_converter_source_source_payload_data[7:0]; + core_rx_converter_source_payload_data[15:8] <= core_rx_converter_source_source_payload_data[17:10]; + core_rx_converter_source_payload_data[23:16] <= core_rx_converter_source_source_payload_data[27:20]; + core_rx_converter_source_payload_data[31:24] <= core_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + core_rx_converter_source_payload_last_be <= 4'd0; + core_rx_converter_source_payload_last_be[0] <= core_rx_converter_source_source_payload_data[8]; + core_rx_converter_source_payload_last_be[1] <= core_rx_converter_source_source_payload_data[18]; + core_rx_converter_source_payload_last_be[2] <= core_rx_converter_source_source_payload_data[28]; + core_rx_converter_source_payload_last_be[3] <= core_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + core_rx_converter_source_payload_error <= 4'd0; + core_rx_converter_source_payload_error[0] <= core_rx_converter_source_source_payload_data[9]; + core_rx_converter_source_payload_error[1] <= core_rx_converter_source_source_payload_data[19]; + core_rx_converter_source_payload_error[2] <= core_rx_converter_source_source_payload_data[29]; + core_rx_converter_source_payload_error[3] <= core_rx_converter_source_source_payload_data[39]; end -assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; -assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; -assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; -assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; -assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; -assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); -assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; -assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; -assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; -assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; -assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; -assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; -assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; -assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; -assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; -assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; -assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; -assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; -assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; -assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; -assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; -assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; -assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; -assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; -assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; -assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; -assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; -assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; -assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; -assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; -assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; -assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; -assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; -assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; -assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; -assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; -assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; -assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); -assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); -assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); -assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); -assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; -assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; -assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +assign core_rx_converter_source_source_valid = core_rx_converter_converter_source_valid; +assign core_rx_converter_converter_source_ready = core_rx_converter_source_source_ready; +assign core_rx_converter_source_source_first = core_rx_converter_converter_source_first; +assign core_rx_converter_source_source_last = core_rx_converter_converter_source_last; +assign core_rx_converter_source_source_payload_data = core_rx_converter_converter_source_payload_data; +assign core_rx_converter_converter_sink_ready = ((~core_rx_converter_converter_strobe_all) | core_rx_converter_converter_source_ready); +assign core_rx_converter_converter_source_valid = core_rx_converter_converter_strobe_all; +assign core_rx_converter_converter_load_part = (core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready); +assign core_rx_cdc_cdc_sink_valid = core_rx_cdc_sink_sink_valid; +assign core_rx_cdc_sink_sink_ready = core_rx_cdc_cdc_sink_ready; +assign core_rx_cdc_cdc_sink_first = core_rx_cdc_sink_sink_first; +assign core_rx_cdc_cdc_sink_last = core_rx_cdc_sink_sink_last; +assign core_rx_cdc_cdc_sink_payload_data = core_rx_cdc_sink_sink_payload_data; +assign core_rx_cdc_cdc_sink_payload_last_be = core_rx_cdc_sink_sink_payload_last_be; +assign core_rx_cdc_cdc_sink_payload_error = core_rx_cdc_sink_sink_payload_error; +assign core_rx_cdc_source_source_valid = core_rx_cdc_cdc_source_valid; +assign core_rx_cdc_cdc_source_ready = core_rx_cdc_source_source_ready; +assign core_rx_cdc_source_source_first = core_rx_cdc_cdc_source_first; +assign core_rx_cdc_source_source_last = core_rx_cdc_cdc_source_last; +assign core_rx_cdc_source_source_payload_data = core_rx_cdc_cdc_source_payload_data; +assign core_rx_cdc_source_source_payload_last_be = core_rx_cdc_cdc_source_payload_last_be; +assign core_rx_cdc_source_source_payload_error = core_rx_cdc_cdc_source_payload_error; +assign core_rx_cdc_cdc_asyncfifo_din = {core_rx_cdc_cdc_fifo_in_last, core_rx_cdc_cdc_fifo_in_first, core_rx_cdc_cdc_fifo_in_payload_error, core_rx_cdc_cdc_fifo_in_payload_last_be, core_rx_cdc_cdc_fifo_in_payload_data}; +assign {core_rx_cdc_cdc_fifo_out_last, core_rx_cdc_cdc_fifo_out_first, core_rx_cdc_cdc_fifo_out_payload_error, core_rx_cdc_cdc_fifo_out_payload_last_be, core_rx_cdc_cdc_fifo_out_payload_data} = core_rx_cdc_cdc_asyncfifo_dout; +assign core_rx_cdc_cdc_sink_ready = core_rx_cdc_cdc_asyncfifo_writable; +assign core_rx_cdc_cdc_asyncfifo_we = core_rx_cdc_cdc_sink_valid; +assign core_rx_cdc_cdc_fifo_in_first = core_rx_cdc_cdc_sink_first; +assign core_rx_cdc_cdc_fifo_in_last = core_rx_cdc_cdc_sink_last; +assign core_rx_cdc_cdc_fifo_in_payload_data = core_rx_cdc_cdc_sink_payload_data; +assign core_rx_cdc_cdc_fifo_in_payload_last_be = core_rx_cdc_cdc_sink_payload_last_be; +assign core_rx_cdc_cdc_fifo_in_payload_error = core_rx_cdc_cdc_sink_payload_error; +assign core_rx_cdc_cdc_source_valid = core_rx_cdc_cdc_asyncfifo_readable; +assign core_rx_cdc_cdc_source_first = core_rx_cdc_cdc_fifo_out_first; +assign core_rx_cdc_cdc_source_last = core_rx_cdc_cdc_fifo_out_last; +assign core_rx_cdc_cdc_source_payload_data = core_rx_cdc_cdc_fifo_out_payload_data; +assign core_rx_cdc_cdc_source_payload_last_be = core_rx_cdc_cdc_fifo_out_payload_last_be; +assign core_rx_cdc_cdc_source_payload_error = core_rx_cdc_cdc_fifo_out_payload_error; +assign core_rx_cdc_cdc_asyncfifo_re = core_rx_cdc_cdc_source_ready; +assign core_rx_cdc_cdc_graycounter0_ce = (core_rx_cdc_cdc_asyncfifo_writable & core_rx_cdc_cdc_asyncfifo_we); +assign core_rx_cdc_cdc_graycounter1_ce = (core_rx_cdc_cdc_asyncfifo_readable & core_rx_cdc_cdc_asyncfifo_re); +assign core_rx_cdc_cdc_asyncfifo_writable = (((core_rx_cdc_cdc_graycounter0_q[5] == core_rx_cdc_cdc_consume_wdomain[5]) | (core_rx_cdc_cdc_graycounter0_q[4] == core_rx_cdc_cdc_consume_wdomain[4])) | (core_rx_cdc_cdc_graycounter0_q[3:0] != core_rx_cdc_cdc_consume_wdomain[3:0])); +assign core_rx_cdc_cdc_asyncfifo_readable = (core_rx_cdc_cdc_graycounter1_q != core_rx_cdc_cdc_produce_rdomain); +assign core_rx_cdc_cdc_wrport_adr = core_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_rx_cdc_cdc_wrport_dat_w = core_rx_cdc_cdc_asyncfifo_din; +assign core_rx_cdc_cdc_wrport_we = core_rx_cdc_cdc_graycounter0_ce; +assign core_rx_cdc_cdc_rdport_adr = core_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_rx_cdc_cdc_asyncfifo_dout = core_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter0_ce) begin + core_rx_cdc_cdc_graycounter0_q_next_binary <= (core_rx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + core_rx_cdc_cdc_graycounter0_q_next_binary <= core_rx_cdc_cdc_graycounter0_q_binary; end end -assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_rx_cdc_cdc_graycounter0_q_next = (core_rx_cdc_cdc_graycounter0_q_next_binary ^ core_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter1_ce) begin + core_rx_cdc_cdc_graycounter1_q_next_binary <= (core_rx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + core_rx_cdc_cdc_graycounter1_q_next_binary <= core_rx_cdc_cdc_graycounter1_q_binary; end end -assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_rx_preamble_sink_valid = main_maccore_ethphy_liteethphyrgmiirx_source_valid; -assign main_maccore_ethphy_liteethphyrgmiirx_source_ready = main_rx_preamble_sink_ready; -assign main_rx_preamble_sink_first = main_maccore_ethphy_liteethphyrgmiirx_source_first; -assign main_rx_preamble_sink_last = main_maccore_ethphy_liteethphyrgmiirx_source_last; -assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_liteethphyrgmiirx_source_payload_data; -assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; -assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_liteethphyrgmiirx_source_payload_error; -assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; -assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; -assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; -assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; -assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; -assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; -assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; -assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; -assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; -assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_rx_padding_source_first; -assign main_rx_last_be_sink_last = main_rx_padding_source_last; -assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; -assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; -assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; -assign main_rx_converter_sink_first = main_rx_last_be_source_first; -assign main_rx_converter_sink_last = main_rx_last_be_source_last; -assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; -assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; -assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; -assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; -assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; -assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; -assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; -assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; -assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; -assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_source_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_source_ready; -assign main_source_first = main_rx_cdc_source_source_first; -assign main_source_last = main_rx_cdc_source_source_last; -assign main_source_payload_data = main_rx_cdc_source_source_payload_data; -assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_source_payload_error = main_rx_cdc_source_source_payload_error; -assign main_sram0_sink_valid = main_sink_sink_valid; -assign main_sink_sink_ready = main_sram1_sink_ready; -assign main_sram2_sink_first = main_sink_sink_first; -assign main_sram3_sink_last = main_sink_sink_last; -assign main_sram4_sink_payload_data = main_sink_sink_payload_data; -assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; -assign main_sram6_sink_payload_error = main_sink_sink_payload_error; -assign main_source_source_valid = main_sram83_source_valid; -assign main_sram84_source_ready = main_source_source_ready; -assign main_source_source_first = main_sram85_source_first; -assign main_source_source_last = main_sram86_source_last; -assign main_source_source_payload_data = main_sram87_source_payload_data; -assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; -assign main_source_source_payload_error = main_sram89_source_payload_error; +assign core_rx_cdc_cdc_graycounter1_q_next = (core_rx_cdc_cdc_graycounter1_q_next_binary ^ core_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_rx_preamble_sink_valid = maccore_ethphy_liteethphyrgmiirx_source_valid; +assign maccore_ethphy_liteethphyrgmiirx_source_ready = core_rx_preamble_sink_ready; +assign core_rx_preamble_sink_first = maccore_ethphy_liteethphyrgmiirx_source_first; +assign core_rx_preamble_sink_last = maccore_ethphy_liteethphyrgmiirx_source_last; +assign core_rx_preamble_sink_payload_data = maccore_ethphy_liteethphyrgmiirx_source_payload_data; +assign core_rx_preamble_sink_payload_last_be = maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; +assign core_rx_preamble_sink_payload_error = maccore_ethphy_liteethphyrgmiirx_source_payload_error; +assign core_bufferizeendpoints_sink_sink_valid = core_rx_preamble_source_valid; +assign core_rx_preamble_source_ready = core_bufferizeendpoints_sink_sink_ready; +assign core_bufferizeendpoints_sink_sink_first = core_rx_preamble_source_first; +assign core_bufferizeendpoints_sink_sink_last = core_rx_preamble_source_last; +assign core_bufferizeendpoints_sink_sink_payload_data = core_rx_preamble_source_payload_data; +assign core_bufferizeendpoints_sink_sink_payload_last_be = core_rx_preamble_source_payload_last_be; +assign core_bufferizeendpoints_sink_sink_payload_error = core_rx_preamble_source_payload_error; +assign core_rx_padding_sink_valid = core_liteethmaccrc32checker_source_source_valid; +assign core_liteethmaccrc32checker_source_source_ready = core_rx_padding_sink_ready; +assign core_rx_padding_sink_first = core_liteethmaccrc32checker_source_source_first; +assign core_rx_padding_sink_last = core_liteethmaccrc32checker_source_source_last; +assign core_rx_padding_sink_payload_data = core_liteethmaccrc32checker_source_source_payload_data; +assign core_rx_padding_sink_payload_last_be = core_liteethmaccrc32checker_source_source_payload_last_be; +assign core_rx_padding_sink_payload_error = core_liteethmaccrc32checker_source_source_payload_error; +assign core_rx_last_be_sink_valid = core_rx_padding_source_valid; +assign core_rx_padding_source_ready = core_rx_last_be_sink_ready; +assign core_rx_last_be_sink_first = core_rx_padding_source_first; +assign core_rx_last_be_sink_last = core_rx_padding_source_last; +assign core_rx_last_be_sink_payload_data = core_rx_padding_source_payload_data; +assign core_rx_last_be_sink_payload_last_be = core_rx_padding_source_payload_last_be; +assign core_rx_last_be_sink_payload_error = core_rx_padding_source_payload_error; +assign core_rx_converter_sink_valid = core_rx_last_be_source_valid; +assign core_rx_last_be_source_ready = core_rx_converter_sink_ready; +assign core_rx_converter_sink_first = core_rx_last_be_source_first; +assign core_rx_converter_sink_last = core_rx_last_be_source_last; +assign core_rx_converter_sink_payload_data = core_rx_last_be_source_payload_data; +assign core_rx_converter_sink_payload_last_be = core_rx_last_be_source_payload_last_be; +assign core_rx_converter_sink_payload_error = core_rx_last_be_source_payload_error; +assign core_rx_cdc_sink_sink_valid = core_rx_converter_source_valid; +assign core_rx_converter_source_ready = core_rx_cdc_sink_sink_ready; +assign core_rx_cdc_sink_sink_first = core_rx_converter_source_first; +assign core_rx_cdc_sink_sink_last = core_rx_converter_source_last; +assign core_rx_cdc_sink_sink_payload_data = core_rx_converter_source_payload_data; +assign core_rx_cdc_sink_sink_payload_last_be = core_rx_converter_source_payload_last_be; +assign core_rx_cdc_sink_sink_payload_error = core_rx_converter_source_payload_error; +assign core_source_valid = core_rx_cdc_source_source_valid; +assign core_rx_cdc_source_source_ready = core_source_ready; +assign core_source_first = core_rx_cdc_source_source_first; +assign core_source_last = core_rx_cdc_source_source_last; +assign core_source_payload_data = core_rx_cdc_source_source_payload_data; +assign core_source_payload_last_be = core_rx_cdc_source_source_payload_last_be; +assign core_source_payload_error = core_rx_cdc_source_source_payload_error; +assign wishbone_interface_writer_sink_sink_valid = wishbone_interface_sink_valid; +assign wishbone_interface_sink_ready = wishbone_interface_writer_sink_sink_ready; +assign wishbone_interface_writer_sink_sink_first = wishbone_interface_sink_first; +assign wishbone_interface_writer_sink_sink_last = wishbone_interface_sink_last; +assign wishbone_interface_writer_sink_sink_payload_data = wishbone_interface_sink_payload_data; +assign wishbone_interface_writer_sink_sink_payload_last_be = wishbone_interface_sink_payload_last_be; +assign wishbone_interface_writer_sink_sink_payload_error = wishbone_interface_sink_payload_error; +assign wishbone_interface_source_valid = wishbone_interface_reader_source_source_valid; +assign wishbone_interface_reader_source_source_ready = wishbone_interface_source_ready; +assign wishbone_interface_source_first = wishbone_interface_reader_source_source_first; +assign wishbone_interface_source_last = wishbone_interface_reader_source_source_last; +assign wishbone_interface_source_payload_data = wishbone_interface_reader_source_source_payload_data; +assign wishbone_interface_source_payload_last_be = wishbone_interface_reader_source_source_payload_last_be; +assign wishbone_interface_source_payload_error = wishbone_interface_reader_source_source_payload_error; always @(*) begin - main_length_inc <= 4'd0; - case (main_sram5_sink_payload_last_be) + wishbone_interface_writer_length_inc <= 4'd0; + case (wishbone_interface_writer_sink_sink_payload_last_be) 1'd1: begin - main_length_inc <= 1'd1; + wishbone_interface_writer_length_inc <= 1'd1; end 2'd2: begin - main_length_inc <= 2'd2; + wishbone_interface_writer_length_inc <= 2'd2; end 3'd4: begin - main_length_inc <= 2'd3; + wishbone_interface_writer_length_inc <= 2'd3; end 4'd8: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end 5'd16: begin - main_length_inc <= 3'd5; + wishbone_interface_writer_length_inc <= 3'd5; end 6'd32: begin - main_length_inc <= 3'd6; + wishbone_interface_writer_length_inc <= 3'd6; end 7'd64: begin - main_length_inc <= 3'd7; + wishbone_interface_writer_length_inc <= 3'd7; end default: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end endcase end -assign main_sram44_source_ready = main_sram20_clear; -assign main_sram19_trigger = main_sram43_source_valid; -assign main_sram7_status = main_sram47_source_payload_slot; -assign main_sram10_status = main_sram48_source_payload_length; -assign main_wr_data = main_sram4_sink_payload_data; +assign wishbone_interface_writer_stat_fifo_source_ready = wishbone_interface_writer_available_clear; +assign wishbone_interface_writer_available_trigger = wishbone_interface_writer_stat_fifo_source_valid; +assign wishbone_interface_writer_slot_status = wishbone_interface_writer_stat_fifo_source_payload_slot; +assign wishbone_interface_writer_length_status = wishbone_interface_writer_stat_fifo_source_payload_length; +assign wishbone_interface_writer_wr_data = wishbone_interface_writer_sink_sink_payload_data; always @(*) begin - main_sram75_adr <= 9'd0; - main_sram77_we <= 1'd0; - main_sram78_dat_w <= 32'd0; - main_sram79_adr <= 9'd0; - main_sram81_we <= 1'd0; - main_sram82_dat_w <= 32'd0; - case (main_slot) + wishbone_interface_writer_memory0_adr <= 9'd0; + wishbone_interface_writer_memory0_dat_w <= 32'd0; + wishbone_interface_writer_memory0_we <= 1'd0; + wishbone_interface_writer_memory1_adr <= 9'd0; + wishbone_interface_writer_memory1_dat_w <= 32'd0; + wishbone_interface_writer_memory1_we <= 1'd0; + case (wishbone_interface_writer_slot) 1'd0: begin - main_sram75_adr <= main_sram35_length[10:2]; - main_sram78_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram77_we <= 1'd1; + wishbone_interface_writer_memory0_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory0_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory0_we <= 1'd1; end end 1'd1: begin - main_sram79_adr <= main_sram35_length[10:2]; - main_sram82_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram81_we <= 1'd1; + wishbone_interface_writer_memory1_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory1_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory1_we <= 1'd1; end end endcase end -assign main_sram21_available = main_sram17_status; -assign main_sram25_available = main_sram18_pending; +assign wishbone_interface_writer_available0 = wishbone_interface_writer_available_status; +assign wishbone_interface_writer_available1 = wishbone_interface_writer_available_pending; always @(*) begin - main_sram20_clear <= 1'd0; - if ((main_sram28_re & main_sram29_r)) begin - main_sram20_clear <= 1'd1; + wishbone_interface_writer_available_clear <= 1'd0; + if ((wishbone_interface_writer_pending_re & wishbone_interface_writer_pending_r)) begin + wishbone_interface_writer_available_clear <= 1'd1; end end -assign main_sram16_irq = (main_sram26_status & main_sram31_storage); -assign main_sram17_status = main_sram19_trigger; -assign main_sram18_pending = main_sram19_trigger; -assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; -assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; -assign main_sram38_sink_ready = main_sram50_writable; -assign main_sram49_we = main_sram37_sink_valid; -assign main_sram68_fifo_in_first = main_sram39_sink_first; -assign main_sram69_fifo_in_last = main_sram40_sink_last; -assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; -assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; -assign main_sram43_source_valid = main_sram52_readable; -assign main_sram45_source_first = main_sram72_fifo_out_first; -assign main_sram46_source_last = main_sram73_fifo_out_last; -assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; -assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; -assign main_sram51_re = main_sram44_source_ready; +assign wishbone_interface_writer_irq = (wishbone_interface_writer_pending_status & wishbone_interface_writer_enable_storage); +assign wishbone_interface_writer_available_status = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_available_pending = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_stat_fifo_syncfifo_din = {wishbone_interface_writer_stat_fifo_fifo_in_last, wishbone_interface_writer_stat_fifo_fifo_in_first, wishbone_interface_writer_stat_fifo_fifo_in_payload_length, wishbone_interface_writer_stat_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_writer_stat_fifo_fifo_out_last, wishbone_interface_writer_stat_fifo_fifo_out_first, wishbone_interface_writer_stat_fifo_fifo_out_payload_length, wishbone_interface_writer_stat_fifo_fifo_out_payload_slot} = wishbone_interface_writer_stat_fifo_syncfifo_dout; +assign wishbone_interface_writer_stat_fifo_sink_ready = wishbone_interface_writer_stat_fifo_syncfifo_writable; +assign wishbone_interface_writer_stat_fifo_syncfifo_we = wishbone_interface_writer_stat_fifo_sink_valid; +assign wishbone_interface_writer_stat_fifo_fifo_in_first = wishbone_interface_writer_stat_fifo_sink_first; +assign wishbone_interface_writer_stat_fifo_fifo_in_last = wishbone_interface_writer_stat_fifo_sink_last; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_slot = wishbone_interface_writer_stat_fifo_sink_payload_slot; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_length = wishbone_interface_writer_stat_fifo_sink_payload_length; +assign wishbone_interface_writer_stat_fifo_source_valid = wishbone_interface_writer_stat_fifo_syncfifo_readable; +assign wishbone_interface_writer_stat_fifo_source_first = wishbone_interface_writer_stat_fifo_fifo_out_first; +assign wishbone_interface_writer_stat_fifo_source_last = wishbone_interface_writer_stat_fifo_fifo_out_last; +assign wishbone_interface_writer_stat_fifo_source_payload_slot = wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +assign wishbone_interface_writer_stat_fifo_source_payload_length = wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +assign wishbone_interface_writer_stat_fifo_syncfifo_re = wishbone_interface_writer_stat_fifo_source_ready; always @(*) begin - main_sram59_adr <= 1'd0; - if (main_sram56_replace) begin - main_sram59_adr <= (main_sram57_produce - 1'd1); + wishbone_interface_writer_stat_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_writer_stat_fifo_replace) begin + wishbone_interface_writer_stat_fifo_wrport_adr <= (wishbone_interface_writer_stat_fifo_produce - 1'd1); end else begin - main_sram59_adr <= main_sram57_produce; + wishbone_interface_writer_stat_fifo_wrport_adr <= wishbone_interface_writer_stat_fifo_produce; end end -assign main_sram62_dat_w = main_sram53_din; -assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); -assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); -assign main_sram64_adr = main_sram58_consume; -assign main_sram54_dout = main_sram65_dat_r; -assign main_sram50_writable = (main_sram55_level != 2'd2); -assign main_sram52_readable = (main_sram55_level != 1'd0); +assign wishbone_interface_writer_stat_fifo_wrport_dat_w = wishbone_interface_writer_stat_fifo_syncfifo_din; +assign wishbone_interface_writer_stat_fifo_wrport_we = (wishbone_interface_writer_stat_fifo_syncfifo_we & (wishbone_interface_writer_stat_fifo_syncfifo_writable | wishbone_interface_writer_stat_fifo_replace)); +assign wishbone_interface_writer_stat_fifo_do_read = (wishbone_interface_writer_stat_fifo_syncfifo_readable & wishbone_interface_writer_stat_fifo_syncfifo_re); +assign wishbone_interface_writer_stat_fifo_rdport_adr = wishbone_interface_writer_stat_fifo_consume; +assign wishbone_interface_writer_stat_fifo_syncfifo_dout = wishbone_interface_writer_stat_fifo_rdport_dat_r; +assign wishbone_interface_writer_stat_fifo_syncfifo_writable = (wishbone_interface_writer_stat_fifo_level != 2'd2); +assign wishbone_interface_writer_stat_fifo_syncfifo_readable = (wishbone_interface_writer_stat_fifo_level != 1'd0); always @(*) begin - builder_liteethmacsramwriter_next_state <= 3'd0; - main_slot_liteethmacsramwriter_next_value <= 1'd0; - main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; - main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; - main_sram37_sink_valid <= 1'd0; - main_sram41_sink_payload_slot <= 1'd0; - main_sram42_sink_payload_length <= 11'd0; - main_write <= 1'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) + liteethmacsramwriter_next_state <= 3'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= 32'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 11'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_payload_length <= 11'd0; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd0; + wishbone_interface_writer_write <= 1'd0; + liteethmacsramwriter_next_state <= liteethmacsramwriter_state; + case (liteethmacsramwriter_state) 1'd1: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end 2'd2: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if ((main_sram5_sink_payload_last_be != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if ((wishbone_interface_writer_sink_sink_payload_last_be != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end end end 2'd3: begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end 3'd4: begin - main_sram37_sink_valid <= 1'd1; - main_sram41_sink_payload_slot <= main_slot; - main_sram42_sink_payload_length <= main_sram35_length; - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); - main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd1; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= wishbone_interface_writer_slot; + wishbone_interface_writer_stat_fifo_sink_payload_length <= wishbone_interface_writer_length; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= (wishbone_interface_writer_slot + 1'd1); + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end default: begin - if (main_sram0_sink_valid) begin - if (main_sram38_sink_ready) begin - main_write <= 1'd1; - main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - if ((main_sram35_length >= 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 1'd1; + if (wishbone_interface_writer_sink_sink_valid) begin + if (wishbone_interface_writer_stat_fifo_sink_ready) begin + wishbone_interface_writer_write <= 1'd1; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= (wishbone_interface_writer_length + wishbone_interface_writer_length_inc); + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((wishbone_interface_writer_length >= 11'd1530)) begin + liteethmacsramwriter_next_state <= 1'd1; end - if (main_sram3_sink_last) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if (wishbone_interface_writer_sink_sink_last) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end else begin - main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd2; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= (wishbone_interface_writer_errors_status + 1'd1); + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 2'd2; end end end endcase end -assign main_sram123_sink_valid = main_start_re; -assign main_sram127_sink_payload_slot = main_sram100_storage; -assign main_sram128_sink_payload_length = main_sram102_storage; -assign main_sram94_status = main_sram124_sink_ready; -assign main_sram97_status = main_sram141_level; +assign wishbone_interface_reader_cmd_fifo_sink_valid = wishbone_interface_reader_start_re; +assign wishbone_interface_reader_cmd_fifo_sink_payload_slot = wishbone_interface_reader_slot_storage; +assign wishbone_interface_reader_cmd_fifo_sink_payload_length = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_ready_status = wishbone_interface_reader_cmd_fifo_sink_ready; +assign wishbone_interface_reader_level_status = wishbone_interface_reader_cmd_fifo_level; always @(*) begin - main_sram88_source_payload_last_be <= 4'd0; - if (main_sram86_source_last) begin - case (main_sram134_source_payload_length[1:0]) + wishbone_interface_reader_source_source_payload_last_be <= 4'd0; + if (wishbone_interface_reader_source_source_last) begin + case (wishbone_interface_reader_cmd_fifo_source_payload_length[1:0]) 1'd1: begin - main_sram88_source_payload_last_be <= 1'd1; + wishbone_interface_reader_source_source_payload_last_be <= 1'd1; end 2'd2: begin - main_sram88_source_payload_last_be <= 2'd2; + wishbone_interface_reader_source_source_payload_last_be <= 2'd2; end 2'd3: begin - main_sram88_source_payload_last_be <= 3'd4; + wishbone_interface_reader_source_source_payload_last_be <= 3'd4; end 3'd4: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end 3'd5: begin - main_sram88_source_payload_last_be <= 5'd16; + wishbone_interface_reader_source_source_payload_last_be <= 5'd16; end 3'd6: begin - main_sram88_source_payload_last_be <= 6'd32; + wishbone_interface_reader_source_source_payload_last_be <= 6'd32; end 3'd7: begin - main_sram88_source_payload_last_be <= 7'd64; + wishbone_interface_reader_source_source_payload_last_be <= 7'd64; end default: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end endcase end end -assign main_sram163_re = main_read; -assign main_sram161_adr = main_sram122_length[10:2]; -assign main_sram166_re = main_read; -assign main_sram164_adr = main_sram122_length[10:2]; +assign wishbone_interface_reader_memory0_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory0_adr = wishbone_interface_reader_length[10:2]; +assign wishbone_interface_reader_memory1_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory1_adr = wishbone_interface_reader_length[10:2]; always @(*) begin - main_rd_data <= 32'd0; - case (main_sram133_source_payload_slot) + wishbone_interface_reader_rd_data <= 32'd0; + case (wishbone_interface_reader_cmd_fifo_source_payload_slot) 1'd0: begin - main_rd_data <= main_sram162_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory0_dat_r; end 1'd1: begin - main_rd_data <= main_sram165_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory1_dat_r; end endcase end -assign main_sram87_source_payload_data = main_rd_data; -assign main_sram109_event0 = main_sram105_status; -assign main_sram113_event0 = main_sram106_pending; +assign wishbone_interface_reader_source_source_payload_data = wishbone_interface_reader_rd_data; +assign wishbone_interface_reader_event00 = wishbone_interface_reader_eventsourcepulse_status; +assign wishbone_interface_reader_event01 = wishbone_interface_reader_eventsourcepulse_pending; always @(*) begin - main_sram108_clear <= 1'd0; - if ((main_sram116_re & main_sram117_r)) begin - main_sram108_clear <= 1'd1; + wishbone_interface_reader_eventsourcepulse_clear <= 1'd0; + if ((wishbone_interface_reader_pending_re & wishbone_interface_reader_pending_r)) begin + wishbone_interface_reader_eventsourcepulse_clear <= 1'd1; end end -assign main_sram104_irq = (main_sram114_status & main_sram119_storage); -assign main_sram105_status = 1'd0; -assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; -assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; -assign main_sram124_sink_ready = main_sram136_writable; -assign main_sram135_we = main_sram123_sink_valid; -assign main_sram154_fifo_in_first = main_sram125_sink_first; -assign main_sram155_fifo_in_last = main_sram126_sink_last; -assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; -assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; -assign main_sram129_source_valid = main_sram138_readable; -assign main_sram131_source_first = main_sram158_fifo_out_first; -assign main_sram132_source_last = main_sram159_fifo_out_last; -assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; -assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; -assign main_sram137_re = main_sram130_source_ready; +assign wishbone_interface_reader_irq = (wishbone_interface_reader_pending_status & wishbone_interface_reader_enable_storage); +assign wishbone_interface_reader_eventsourcepulse_status = 1'd0; +assign wishbone_interface_reader_cmd_fifo_syncfifo_din = {wishbone_interface_reader_cmd_fifo_fifo_in_last, wishbone_interface_reader_cmd_fifo_fifo_in_first, wishbone_interface_reader_cmd_fifo_fifo_in_payload_length, wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_reader_cmd_fifo_fifo_out_last, wishbone_interface_reader_cmd_fifo_fifo_out_first, wishbone_interface_reader_cmd_fifo_fifo_out_payload_length, wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot} = wishbone_interface_reader_cmd_fifo_syncfifo_dout; +assign wishbone_interface_reader_cmd_fifo_sink_ready = wishbone_interface_reader_cmd_fifo_syncfifo_writable; +assign wishbone_interface_reader_cmd_fifo_syncfifo_we = wishbone_interface_reader_cmd_fifo_sink_valid; +assign wishbone_interface_reader_cmd_fifo_fifo_in_first = wishbone_interface_reader_cmd_fifo_sink_first; +assign wishbone_interface_reader_cmd_fifo_fifo_in_last = wishbone_interface_reader_cmd_fifo_sink_last; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot = wishbone_interface_reader_cmd_fifo_sink_payload_slot; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_length = wishbone_interface_reader_cmd_fifo_sink_payload_length; +assign wishbone_interface_reader_cmd_fifo_source_valid = wishbone_interface_reader_cmd_fifo_syncfifo_readable; +assign wishbone_interface_reader_cmd_fifo_source_first = wishbone_interface_reader_cmd_fifo_fifo_out_first; +assign wishbone_interface_reader_cmd_fifo_source_last = wishbone_interface_reader_cmd_fifo_fifo_out_last; +assign wishbone_interface_reader_cmd_fifo_source_payload_slot = wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +assign wishbone_interface_reader_cmd_fifo_source_payload_length = wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +assign wishbone_interface_reader_cmd_fifo_syncfifo_re = wishbone_interface_reader_cmd_fifo_source_ready; always @(*) begin - main_sram145_adr <= 1'd0; - if (main_sram142_replace) begin - main_sram145_adr <= (main_sram143_produce - 1'd1); + wishbone_interface_reader_cmd_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_reader_cmd_fifo_replace) begin + wishbone_interface_reader_cmd_fifo_wrport_adr <= (wishbone_interface_reader_cmd_fifo_produce - 1'd1); end else begin - main_sram145_adr <= main_sram143_produce; + wishbone_interface_reader_cmd_fifo_wrport_adr <= wishbone_interface_reader_cmd_fifo_produce; end end -assign main_sram148_dat_w = main_sram139_din; -assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); -assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); -assign main_sram150_adr = main_sram144_consume; -assign main_sram140_dout = main_sram151_dat_r; -assign main_sram136_writable = (main_sram141_level != 2'd2); -assign main_sram138_readable = (main_sram141_level != 1'd0); +assign wishbone_interface_reader_cmd_fifo_wrport_dat_w = wishbone_interface_reader_cmd_fifo_syncfifo_din; +assign wishbone_interface_reader_cmd_fifo_wrport_we = (wishbone_interface_reader_cmd_fifo_syncfifo_we & (wishbone_interface_reader_cmd_fifo_syncfifo_writable | wishbone_interface_reader_cmd_fifo_replace)); +assign wishbone_interface_reader_cmd_fifo_do_read = (wishbone_interface_reader_cmd_fifo_syncfifo_readable & wishbone_interface_reader_cmd_fifo_syncfifo_re); +assign wishbone_interface_reader_cmd_fifo_rdport_adr = wishbone_interface_reader_cmd_fifo_consume; +assign wishbone_interface_reader_cmd_fifo_syncfifo_dout = wishbone_interface_reader_cmd_fifo_rdport_dat_r; +assign wishbone_interface_reader_cmd_fifo_syncfifo_writable = (wishbone_interface_reader_cmd_fifo_level != 2'd2); +assign wishbone_interface_reader_cmd_fifo_syncfifo_readable = (wishbone_interface_reader_cmd_fifo_level != 1'd0); always @(*) begin - builder_liteethmacsramreader_next_state <= 2'd0; - main_read <= 1'd0; - main_sram107_trigger <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value <= 11'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; - main_sram130_source_ready <= 1'd0; - main_sram83_source_valid <= 1'd0; - main_sram86_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) + liteethmacsramreader_next_state <= 2'd0; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd0; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 11'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd0; + wishbone_interface_reader_read <= 1'd0; + wishbone_interface_reader_source_source_last <= 1'd0; + wishbone_interface_reader_source_source_valid <= 1'd0; + liteethmacsramreader_next_state <= liteethmacsramreader_state; + case (liteethmacsramreader_state) 1'd1: begin - main_sram83_source_valid <= 1'd1; - main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); - if (main_sram84_source_ready) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - if (main_sram86_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; + wishbone_interface_reader_source_source_valid <= 1'd1; + wishbone_interface_reader_source_source_last <= (wishbone_interface_reader_length >= wishbone_interface_reader_cmd_fifo_source_payload_length); + if (wishbone_interface_reader_source_source_ready) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= (wishbone_interface_reader_length + 3'd4); + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (wishbone_interface_reader_source_source_last) begin + liteethmacsramreader_next_state <= 2'd2; end end end 2'd2: begin - main_sram122_length_liteethmacsramreader_next_value <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - main_sram107_trigger <= 1'd1; - main_sram130_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd1; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd1; + liteethmacsramreader_next_state <= 1'd0; end default: begin - if (main_sram129_source_valid) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= 3'd4; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; + if (wishbone_interface_reader_cmd_fifo_source_valid) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 3'd4; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + liteethmacsramreader_next_state <= 1'd1; end end endcase end -assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); -assign main_sram0_adr = main_interface0_adr[8:0]; -assign main_interface0_dat_r = main_sram0_dat_r; -assign main_sram1_adr = main_interface1_adr[8:0]; -assign main_interface1_dat_r = main_sram1_dat_r; +assign wishbone_interface_ev_irq = (wishbone_interface_writer_irq | wishbone_interface_reader_irq); +assign wishbone_interface_sram0_adr = wishbone_interface_interface0_adr[8:0]; +assign wishbone_interface_interface0_dat_r = wishbone_interface_sram0_dat_r; +assign wishbone_interface_sram1_adr = wishbone_interface_interface1_adr[8:0]; +assign wishbone_interface_interface1_dat_r = wishbone_interface_sram1_dat_r; +always @(*) begin + wishbone_interface_decoder0_slave_sel <= 2'd0; + wishbone_interface_decoder0_slave_sel[0] <= (wishbone_interface_bus_rx_adr[9] == 1'd0); + wishbone_interface_decoder0_slave_sel[1] <= (wishbone_interface_bus_rx_adr[9] == 1'd1); +end +assign wishbone_interface_interface0_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface0_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface0_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface0_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface0_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface0_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface0_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface1_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface1_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface1_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface1_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface1_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface1_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface1_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface0_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[0]); +assign wishbone_interface_interface1_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[1]); +assign wishbone_interface_bus_rx_ack = (wishbone_interface_interface0_ack | wishbone_interface_interface1_ack); +assign wishbone_interface_bus_rx_err = (wishbone_interface_interface0_err | wishbone_interface_interface1_err); +assign wishbone_interface_bus_rx_dat_r = (({32{wishbone_interface_decoder0_slave_sel_r[0]}} & wishbone_interface_interface0_dat_r) | ({32{wishbone_interface_decoder0_slave_sel_r[1]}} & wishbone_interface_interface1_dat_r)); always @(*) begin - main_sram2_we <= 4'd0; - main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); - main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); - main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); - main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); + wishbone_interface_sram2_we <= 4'd0; + wishbone_interface_sram2_we[0] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[0]); + wishbone_interface_sram2_we[1] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[1]); + wishbone_interface_sram2_we[2] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[2]); + wishbone_interface_sram2_we[3] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[3]); end -assign main_sram2_adr = main_interface2_adr[8:0]; -assign main_interface2_dat_r = main_sram2_dat_r; -assign main_sram2_dat_w = main_interface2_dat_w; +assign wishbone_interface_sram2_adr = wishbone_interface_interface2_adr[8:0]; +assign wishbone_interface_interface2_dat_r = wishbone_interface_sram2_dat_r; +assign wishbone_interface_sram2_dat_w = wishbone_interface_interface2_dat_w; always @(*) begin - main_sram3_we <= 4'd0; - main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); - main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); - main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); - main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); + wishbone_interface_sram3_we <= 4'd0; + wishbone_interface_sram3_we[0] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[0]); + wishbone_interface_sram3_we[1] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[1]); + wishbone_interface_sram3_we[2] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[2]); + wishbone_interface_sram3_we[3] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[3]); end -assign main_sram3_adr = main_interface3_adr[8:0]; -assign main_interface3_dat_r = main_sram3_dat_r; -assign main_sram3_dat_w = main_interface3_dat_w; +assign wishbone_interface_sram3_adr = wishbone_interface_interface3_adr[8:0]; +assign wishbone_interface_interface3_dat_r = wishbone_interface_sram3_dat_r; +assign wishbone_interface_sram3_dat_w = wishbone_interface_interface3_dat_w; always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); + wishbone_interface_decoder1_slave_sel <= 2'd0; + wishbone_interface_decoder1_slave_sel[0] <= (wishbone_interface_bus_tx_adr[9] == 1'd0); + wishbone_interface_decoder1_slave_sel[1] <= (wishbone_interface_bus_tx_adr[9] == 1'd1); end -assign main_interface0_adr = main_bus_adr; -assign main_interface0_dat_w = main_bus_dat_w; -assign main_interface0_sel = main_bus_sel; -assign main_interface0_stb = main_bus_stb; -assign main_interface0_we = main_bus_we; -assign main_interface0_cti = main_bus_cti; -assign main_interface0_bte = main_bus_bte; -assign main_interface1_adr = main_bus_adr; -assign main_interface1_dat_w = main_bus_dat_w; -assign main_interface1_sel = main_bus_sel; -assign main_interface1_stb = main_bus_stb; -assign main_interface1_we = main_bus_we; -assign main_interface1_cti = main_bus_cti; -assign main_interface1_bte = main_bus_bte; -assign main_interface2_adr = main_bus_adr; -assign main_interface2_dat_w = main_bus_dat_w; -assign main_interface2_sel = main_bus_sel; -assign main_interface2_stb = main_bus_stb; -assign main_interface2_we = main_bus_we; -assign main_interface2_cti = main_bus_cti; -assign main_interface2_bte = main_bus_bte; -assign main_interface3_adr = main_bus_adr; -assign main_interface3_dat_w = main_bus_dat_w; -assign main_interface3_sel = main_bus_sel; -assign main_interface3_stb = main_bus_stb; -assign main_interface3_we = main_bus_we; -assign main_interface3_cti = main_bus_cti; -assign main_interface3_bte = main_bus_bte; -assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); -assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); -assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); -assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); -assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +assign wishbone_interface_interface2_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface2_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface2_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface2_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface2_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface2_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface2_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface3_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface3_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface3_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface3_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface3_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface3_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface3_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface2_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[0]); +assign wishbone_interface_interface3_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[1]); +assign wishbone_interface_bus_tx_ack = (wishbone_interface_interface2_ack | wishbone_interface_interface3_ack); +assign wishbone_interface_bus_tx_err = (wishbone_interface_interface2_err | wishbone_interface_interface3_err); +assign wishbone_interface_bus_tx_dat_r = (({32{wishbone_interface_decoder1_slave_sel_r[0]}} & wishbone_interface_interface2_dat_r) | ({32{wishbone_interface_decoder1_slave_sel_r[1]}} & wishbone_interface_interface3_dat_r)); always @(*) begin - builder_interface0_ack <= 1'd0; - builder_interface0_dat_r <= 32'd0; - builder_interface1_adr <= 14'd0; - builder_interface1_dat_w <= 32'd0; - builder_interface1_we <= 1'd0; - builder_next_state <= 1'd0; - builder_next_state <= builder_state; - case (builder_state) + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; + interface1_we <= 1'd0; + next_state <= 1'd0; + next_state <= state; + case (state) 1'd1: begin - builder_interface0_ack <= 1'd1; - builder_interface0_dat_r <= builder_interface1_dat_r; - builder_next_state <= 1'd0; + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + next_state <= 1'd0; end default: begin - builder_interface1_dat_w <= builder_interface0_dat_w; - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr <= builder_interface0_adr[29:0]; - builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); - builder_next_state <= 1'd1; + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + next_state <= 1'd1; end end endcase end -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); -assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_re <= 1'd0; - builder_csrbank0_reset0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= interface0_bank_bus_re; end end -assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank0_scratch0_re <= 1'd0; - builder_csrbank0_scratch0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + maccore_maccore_soc_rst <= 1'd0; + if (maccore_maccore_reset_re) begin + maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0]; end end -assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; -assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; -assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; -assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; -assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); -assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1]; +assign csrbank0_reset0_w = maccore_maccore_reset_storage; +assign csrbank0_scratch0_w = maccore_maccore_scratch_storage; +assign csrbank0_bus_errors_w = maccore_maccore_bus_errors_status; +assign maccore_maccore_bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 2'd2); +assign csrbank1_sram_writer_slot_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_re <= 1'd0; - builder_csrbank1_sram_writer_slot_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_slot_re <= 1'd0; + csrbank1_sram_writer_slot_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_sram_writer_slot_re <= interface1_bank_bus_we; + csrbank1_sram_writer_slot_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_writer_length_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_length_re <= 1'd0; + csrbank1_sram_writer_length_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_sram_writer_length_re <= interface1_bank_bus_we; + csrbank1_sram_writer_length_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_sram_writer_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_sram_writer_errors_re <= 1'd0; - builder_csrbank1_sram_writer_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_errors_re <= 1'd0; + csrbank1_sram_writer_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_sram_writer_errors_re <= interface1_bank_bus_we; + csrbank1_sram_writer_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_status_re <= 1'd0; + csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_sram_writer_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_pending_re <= 1'd0; + csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_sram_writer_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_enable0_re <= 1'd0; + csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_sram_writer_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_enable0_we <= interface1_bank_bus_re; end end -assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +assign wishbone_interface_reader_start_r = interface1_bank_bus_dat_w[0]; always @(*) begin - main_start_re <= 1'd0; - main_start_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_start_re <= builder_interface1_bank_bus_we; - main_start_we <= (~builder_interface1_bank_bus_we); + wishbone_interface_reader_start_re <= 1'd0; + wishbone_interface_reader_start_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + wishbone_interface_reader_start_re <= interface1_bank_bus_we; + wishbone_interface_reader_start_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ready_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_re <= 1'd0; - builder_csrbank1_sram_reader_ready_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ready_re <= 1'd0; + csrbank1_sram_reader_ready_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_sram_reader_ready_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ready_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +assign csrbank1_sram_reader_level_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_re <= 1'd0; - builder_csrbank1_sram_reader_level_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_level_re <= 1'd0; + csrbank1_sram_reader_level_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + csrbank1_sram_reader_level_re <= interface1_bank_bus_we; + csrbank1_sram_reader_level_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_slot0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_slot0_re <= 1'd0; + csrbank1_sram_reader_slot0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_sram_reader_slot0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_slot0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_reader_length0_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_re <= 1'd0; - builder_csrbank1_sram_reader_length0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_length0_re <= 1'd0; + csrbank1_sram_reader_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_sram_reader_length0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_length0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_status_re <= 1'd0; + csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_sram_reader_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_pending_re <= 1'd0; + csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_sram_reader_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_enable0_re <= 1'd0; + csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_sram_reader_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_enable0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_preamble_crc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_re <= 1'd0; - builder_csrbank1_preamble_crc_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + csrbank1_preamble_crc_re <= 1'd0; + csrbank1_preamble_crc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + csrbank1_preamble_crc_re <= interface1_bank_bus_we; + csrbank1_preamble_crc_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_rx_datapath_preamble_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_rx_datapath_preamble_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_preamble_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_rx_datapath_crc_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_rx_datapath_crc_errors_re <= 1'd0; + csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_rx_datapath_crc_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_crc_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; -assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; -assign main_sram11_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; -assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; -always @(*) begin - main_sram22_status <= 1'd0; - main_sram22_status <= main_sram21_available; -end -assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; -assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; -always @(*) begin - main_sram26_status <= 1'd0; - main_sram26_status <= main_sram25_available; -end -assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; -assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_sram30_available = main_sram31_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; -assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; -assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; -assign main_sram98_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; -assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; -always @(*) begin - main_sram110_status <= 1'd0; - main_sram110_status <= main_sram109_event0; -end -assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; -assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; -always @(*) begin - main_sram114_status <= 1'd0; - main_sram114_status <= main_sram113_event0; -end -assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; -assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_sram118_event0 = main_sram119_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; -assign builder_csrbank1_preamble_crc_w = main_status; -assign main_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; -assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); -assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_slot_w = wishbone_interface_writer_slot_status; +assign wishbone_interface_writer_slot_we = csrbank1_sram_writer_slot_we; +assign csrbank1_sram_writer_length_w = wishbone_interface_writer_length_status; +assign wishbone_interface_writer_length_we = csrbank1_sram_writer_length_we; +assign csrbank1_sram_writer_errors_w = wishbone_interface_writer_errors_status; +assign wishbone_interface_writer_errors_we = csrbank1_sram_writer_errors_we; +assign wishbone_interface_writer_status_status = wishbone_interface_writer_available0; +assign csrbank1_sram_writer_ev_status_w = wishbone_interface_writer_status_status; +assign wishbone_interface_writer_status_we = csrbank1_sram_writer_ev_status_we; +assign wishbone_interface_writer_pending_status = wishbone_interface_writer_available1; +assign csrbank1_sram_writer_ev_pending_w = wishbone_interface_writer_pending_status; +assign wishbone_interface_writer_pending_we = csrbank1_sram_writer_ev_pending_we; +assign wishbone_interface_writer_available2 = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_writer_ev_enable0_w = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_reader_ready_w = wishbone_interface_reader_ready_status; +assign wishbone_interface_reader_ready_we = csrbank1_sram_reader_ready_we; +assign csrbank1_sram_reader_level_w = wishbone_interface_reader_level_status; +assign wishbone_interface_reader_level_we = csrbank1_sram_reader_level_we; +assign csrbank1_sram_reader_slot0_w = wishbone_interface_reader_slot_storage; +assign csrbank1_sram_reader_length0_w = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_status_status = wishbone_interface_reader_event00; +assign csrbank1_sram_reader_ev_status_w = wishbone_interface_reader_status_status; +assign wishbone_interface_reader_status_we = csrbank1_sram_reader_ev_status_we; +assign wishbone_interface_reader_pending_status = wishbone_interface_reader_event01; +assign csrbank1_sram_reader_ev_pending_w = wishbone_interface_reader_pending_status; +assign wishbone_interface_reader_pending_we = csrbank1_sram_reader_ev_pending_we; +assign wishbone_interface_reader_event02 = wishbone_interface_reader_enable_storage; +assign csrbank1_sram_reader_ev_enable0_w = wishbone_interface_reader_enable_storage; +assign csrbank1_preamble_crc_w = core_status; +assign core_we = csrbank1_preamble_crc_we; +assign csrbank1_rx_datapath_preamble_errors_w = core_preamble_errors_status; +assign core_preamble_errors_we = csrbank1_rx_datapath_preamble_errors_we; +assign csrbank1_rx_datapath_crc_errors_w = core_crc_errors_status; +assign core_crc_errors_we = csrbank1_rx_datapath_crc_errors_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); +assign csrbank2_crg_reset0_r = interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_crg_reset0_re <= 1'd0; - builder_csrbank2_crg_reset0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + csrbank2_crg_reset0_re <= 1'd0; + csrbank2_crg_reset0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_crg_reset0_re <= interface2_bank_bus_we; + csrbank2_crg_reset0_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +assign csrbank2_mdio_w0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_re <= 1'd0; - builder_csrbank2_mdio_w0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + csrbank2_mdio_w0_re <= 1'd0; + csrbank2_mdio_w0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_mdio_w0_re <= interface2_bank_bus_we; + csrbank2_mdio_w0_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +assign csrbank2_mdio_r_r = interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + csrbank2_mdio_r_re <= 1'd0; + csrbank2_mdio_r_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_mdio_r_re <= interface2_bank_bus_we; + csrbank2_mdio_r_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; -assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; -assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; -assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; -assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_adr = builder_interface1_adr; -assign builder_we = builder_interface1_we; -assign builder_dat_w = builder_interface1_dat_w; -assign builder_interface1_dat_r = builder_dat_r; -assign builder_interface0_bank_bus_adr = builder_adr; -assign builder_interface1_bank_bus_adr = builder_adr; -assign builder_interface2_bank_bus_adr = builder_adr; -assign builder_interface0_bank_bus_we = builder_we; -assign builder_interface1_bank_bus_we = builder_we; -assign builder_interface2_bank_bus_we = builder_we; -assign builder_interface0_bank_bus_dat_w = builder_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_dat_w; -assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); -assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; -assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +assign csrbank2_crg_reset0_w = maccore_ethphy_reset_storage; +assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0]; +assign maccore_ethphy_oe = maccore_ethphy__w_storage[1]; +assign maccore_ethphy_w = maccore_ethphy__w_storage[2]; +assign csrbank2_mdio_w0_w = maccore_ethphy__w_storage; +assign csrbank2_mdio_r_w = maccore_ethphy__r_status; +assign maccore_ethphy__r_we = csrbank2_mdio_r_we; +assign adr = interface1_adr; +assign re = interface1_re; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - builder_self0 <= 30'd0; - case (builder_grant) + self0 <= 30'd0; + case (grant) default: begin - builder_self0 <= main_wb_bus_adr; + self0 <= wb_bus_adr; end endcase end always @(*) begin - builder_self1 <= 32'd0; - case (builder_grant) + self1 <= 32'd0; + case (grant) default: begin - builder_self1 <= main_wb_bus_dat_w; + self1 <= wb_bus_dat_w; end endcase end always @(*) begin - builder_self2 <= 4'd0; - case (builder_grant) + self2 <= 4'd0; + case (grant) default: begin - builder_self2 <= main_wb_bus_sel; + self2 <= wb_bus_sel; end endcase end always @(*) begin - builder_self3 <= 1'd0; - case (builder_grant) + self3 <= 1'd0; + case (grant) default: begin - builder_self3 <= main_wb_bus_cyc; + self3 <= wb_bus_cyc; end endcase end always @(*) begin - builder_self4 <= 1'd0; - case (builder_grant) + self4 <= 1'd0; + case (grant) default: begin - builder_self4 <= main_wb_bus_stb; + self4 <= wb_bus_stb; end endcase end always @(*) begin - builder_self5 <= 1'd0; - case (builder_grant) + self5 <= 1'd0; + case (grant) default: begin - builder_self5 <= main_wb_bus_we; + self5 <= wb_bus_we; end endcase end always @(*) begin - builder_self6 <= 3'd0; - case (builder_grant) + self6 <= 3'd0; + case (grant) default: begin - builder_self6 <= main_wb_bus_cti; + self6 <= wb_bus_cti; end endcase end always @(*) begin - builder_self7 <= 2'd0; - case (builder_grant) + self7 <= 2'd0; + case (grant) default: begin - builder_self7 <= main_wb_bus_bte; + self7 <= wb_bus_bte; end endcase end -assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_maccore_ethphy_locked); +assign xilinxasyncresetsynchronizerimpl0 = (~maccore_ethphy_locked); always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl01; + maccore_ethphy__r_status <= 1'd0; + maccore_ethphy__r_status <= maccore_ethphy_r; + maccore_ethphy__r_status <= xilinxmultiregimpl01; end -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl11; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl21; -assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl31; -assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl41; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl51; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; +assign core_tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl11; +assign core_tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl21; +assign core_pulsesynchronizer0_toggle_o = xilinxmultiregimpl31; +assign core_pulsesynchronizer1_toggle_o = xilinxmultiregimpl41; +assign core_rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl51; +assign core_rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl61; //------------------------------------------------------------------------------ @@ -3215,516 +3141,516 @@ assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; //------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; - main_maccore_ethphy_liteethphyrgmiirx_source_valid <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; - main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= main_maccore_ethphy_liteethphyrgmiirx_rx_data; - builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; - if (main_pulsesynchronizer0_i) begin - main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= maccore_ethphy_liteethphyrgmiirx_rx_ctl; + maccore_ethphy_liteethphyrgmiirx_source_valid <= maccore_ethphy_liteethphyrgmiirx_rx_ctl; + maccore_ethphy_liteethphyrgmiirx_source_payload_data <= maccore_ethphy_liteethphyrgmiirx_rx_data; + rxdatapath_liteethmacpreamblechecker_state <= rxdatapath_liteethmacpreamblechecker_next_state; + if (core_pulsesynchronizer0_i) begin + core_pulsesynchronizer0_toggle_i <= (~core_pulsesynchronizer0_toggle_i); end - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + if (core_liteethmaccrc32checker_crc_ce) begin + core_liteethmaccrc32checker_crc_reg <= core_liteethmaccrc32checker_crc_crc_next; end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + if (core_liteethmaccrc32checker_crc_reset) begin + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((core_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_produce <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + core_liteethmaccrc32checker_syncfifo_produce <= (core_liteethmaccrc32checker_syncfifo_produce + 1'd1); end end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + if ((core_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_consume <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + core_liteethmaccrc32checker_syncfifo_consume <= (core_liteethmaccrc32checker_syncfifo_consume + 1'd1); end end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~core_liteethmaccrc32checker_syncfifo_do_read)) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level + 1'd1); end end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level - 1'd1); end end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + if (core_liteethmaccrc32checker_fifo_reset) begin + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; end - builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; - if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin - main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + rxdatapath_bufferizeendpoints_state <= rxdatapath_bufferizeendpoints_next_state; + if (core_liteethmaccrc32checker_last_be_next_value_ce0) begin + core_liteethmaccrc32checker_last_be <= core_liteethmaccrc32checker_last_be_next_value0; end - if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin - main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + if (core_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + core_liteethmaccrc32checker_crc_error1 <= core_liteethmaccrc32checker_crc_error1_next_value1; end - if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin - main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; - main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; - main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; - main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; - main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + if (((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready)) begin + core_bufferizeendpoints_pipe_valid_source_valid <= core_bufferizeendpoints_pipe_valid_sink_valid; + core_bufferizeendpoints_pipe_valid_source_first <= core_bufferizeendpoints_pipe_valid_sink_first; + core_bufferizeendpoints_pipe_valid_source_last <= core_bufferizeendpoints_pipe_valid_sink_last; + core_bufferizeendpoints_pipe_valid_source_payload_data <= core_bufferizeendpoints_pipe_valid_sink_payload_data; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= core_bufferizeendpoints_pipe_valid_sink_payload_last_be; + core_bufferizeendpoints_pipe_valid_source_payload_error <= core_bufferizeendpoints_pipe_valid_sink_payload_error; end - if (main_pulsesynchronizer1_i) begin - main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + if (core_pulsesynchronizer1_i) begin + core_pulsesynchronizer1_toggle_i <= (~core_pulsesynchronizer1_toggle_i); end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; + if (core_rx_converter_converter_source_ready) begin + core_rx_converter_converter_strobe_all <= 1'd0; end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; + if (core_rx_converter_converter_load_part) begin + if (((core_rx_converter_converter_demux == 2'd3) | core_rx_converter_converter_sink_last)) begin + core_rx_converter_converter_demux <= 1'd0; + core_rx_converter_converter_strobe_all <= 1'd1; end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + core_rx_converter_converter_demux <= (core_rx_converter_converter_demux + 1'd1); end end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + if ((core_rx_converter_converter_source_valid & core_rx_converter_converter_source_ready)) begin + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= core_rx_converter_converter_sink_first; + core_rx_converter_converter_source_last <= core_rx_converter_converter_sink_last; end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; + core_rx_converter_converter_source_first <= 1'd0; + core_rx_converter_converter_source_last <= 1'd0; end end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= (core_rx_converter_converter_sink_first | core_rx_converter_converter_source_first); + core_rx_converter_converter_source_last <= (core_rx_converter_converter_sink_last | core_rx_converter_converter_source_last); end end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) + if (core_rx_converter_converter_load_part) begin + case (core_rx_converter_converter_demux) 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[9:0] <= core_rx_converter_converter_sink_payload_data; end 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[19:10] <= core_rx_converter_converter_sink_payload_data; end 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[29:20] <= core_rx_converter_converter_sink_payload_data; end 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[39:30] <= core_rx_converter_converter_sink_payload_data; end endcase end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + if (core_rx_converter_converter_load_part) begin + core_rx_converter_converter_source_payload_valid_token_count <= (core_rx_converter_converter_demux + 1'd1); end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + core_rx_cdc_cdc_graycounter0_q_binary <= core_rx_cdc_cdc_graycounter0_q_next_binary; + core_rx_cdc_cdc_graycounter0_q <= core_rx_cdc_cdc_graycounter0_q_next; if (eth_rx_rst) begin - main_maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; - main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_liteethmaccrc32checker_last_be <= 1'd0; - main_liteethmaccrc32checker_crc_error1 <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; - builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; + maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; + maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + core_liteethmaccrc32checker_last_be <= 1'd0; + core_liteethmaccrc32checker_crc_error1 <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + core_rx_converter_converter_source_payload_data <= 40'd0; + core_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + core_rx_converter_converter_demux <= 2'd0; + core_rx_converter_converter_strobe_all <= 1'd0; + core_rx_cdc_cdc_graycounter0_q <= 6'd0; + core_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + rxdatapath_bufferizeendpoints_state <= 2'd0; end - builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; + xilinxmultiregimpl60 <= core_rx_cdc_cdc_graycounter1_q; + xilinxmultiregimpl61 <= xilinxmultiregimpl60; end always @(posedge eth_tx_clk) begin - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= core_tx_cdc_cdc_graycounter1_q_next_binary; + core_tx_cdc_cdc_graycounter1_q <= core_tx_cdc_cdc_graycounter1_q_next; + if ((core_tx_converter_converter_source_valid & core_tx_converter_converter_source_ready)) begin + if (core_tx_converter_converter_last) begin + core_tx_converter_converter_mux <= 1'd0; end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + core_tx_converter_converter_mux <= (core_tx_converter_converter_mux + 1'd1); end end - builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; - builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; - if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin - main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + txdatapath_liteethmactxlastbe_state <= txdatapath_liteethmactxlastbe_next_state; + txdatapath_liteethmacpaddinginserter_state <= txdatapath_liteethmacpaddinginserter_next_state; + if (core_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + core_tx_padding_counter <= core_tx_padding_counter_clockdomainsrenamer0_next_value; end - if (main_tx_crc_is_ongoing0) begin - main_tx_crc_cnt <= 2'd3; + if (core_tx_crc_is_ongoing0) begin + core_tx_crc_cnt <= 2'd3; end else begin - if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin - main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + if ((core_tx_crc_is_ongoing1 & (~core_tx_crc_cnt_done))) begin + core_tx_crc_cnt <= (core_tx_crc_cnt - core_tx_crc_source_ready); end end - if (main_tx_crc_ce) begin - main_tx_crc_reg <= main_tx_crc_crc_next; + if (core_tx_crc_ce) begin + core_tx_crc_reg <= core_tx_crc_crc_next; end - if (main_tx_crc_reset) begin - main_tx_crc_reg <= 32'd4294967295; + if (core_tx_crc_reset) begin + core_tx_crc_reg <= 32'd4294967295; end - builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; - if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin - main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + txdatapath_bufferizeendpoints_state <= txdatapath_bufferizeendpoints_next_state; + if (core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + core_tx_crc_crc_packet <= core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; end - if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin - main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + if (core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + core_tx_crc_last_be <= core_tx_crc_last_be_clockdomainsrenamer1_next_value1; end - if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin - main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; - main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; - main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; - main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; - main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; - main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + if (((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready)) begin + core_tx_crc_pipe_valid_source_valid <= core_tx_crc_pipe_valid_sink_valid; + core_tx_crc_pipe_valid_source_first <= core_tx_crc_pipe_valid_sink_first; + core_tx_crc_pipe_valid_source_last <= core_tx_crc_pipe_valid_sink_last; + core_tx_crc_pipe_valid_source_payload_data <= core_tx_crc_pipe_valid_sink_payload_data; + core_tx_crc_pipe_valid_source_payload_last_be <= core_tx_crc_pipe_valid_sink_payload_last_be; + core_tx_crc_pipe_valid_source_payload_error <= core_tx_crc_pipe_valid_sink_payload_error; end - builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; - if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin - main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + txdatapath_liteethmacpreambleinserter_state <= txdatapath_liteethmacpreambleinserter_next_state; + if (core_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + core_tx_preamble_count <= core_tx_preamble_count_clockdomainsrenamer2_next_value; end - builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; - if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin - main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + txdatapath_liteethmacgap_state <= txdatapath_liteethmacgap_next_state; + if (core_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + core_tx_gap_counter <= core_tx_gap_counter_clockdomainsrenamer3_next_value; end if (eth_tx_rst) begin - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_padding_counter <= 16'd0; - main_tx_crc_crc_packet <= 32'd0; - main_tx_crc_last_be <= 1'd0; - main_tx_crc_reg <= 32'd4294967295; - main_tx_crc_cnt <= 2'd3; - main_tx_crc_pipe_valid_source_valid <= 1'd0; - main_tx_crc_pipe_valid_source_payload_data <= 8'd0; - main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; - main_tx_crc_pipe_valid_source_payload_error <= 1'd0; - builder_txdatapath_liteethmactxlastbe_state <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; - builder_txdatapath_bufferizeendpoints_state <= 2'd0; - builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; - builder_txdatapath_liteethmacgap_state <= 1'd0; + core_tx_cdc_cdc_graycounter1_q <= 6'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + core_tx_converter_converter_mux <= 2'd0; + core_tx_padding_counter <= 16'd0; + core_tx_crc_reg <= 32'd4294967295; + core_tx_crc_cnt <= 2'd3; + core_tx_crc_pipe_valid_source_valid <= 1'd0; + core_tx_crc_pipe_valid_source_payload_data <= 8'd0; + core_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + core_tx_crc_pipe_valid_source_payload_error <= 1'd0; + txdatapath_liteethmactxlastbe_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_state <= 1'd0; + txdatapath_bufferizeendpoints_state <= 2'd0; + txdatapath_liteethmacpreambleinserter_state <= 2'd0; + txdatapath_liteethmacgap_state <= 1'd0; end - builder_xilinxmultiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; + xilinxmultiregimpl10 <= core_tx_cdc_cdc_graycounter0_q; + xilinxmultiregimpl11 <= xilinxmultiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); end end else begin - builder_count <= 20'd1000000; + count <= 20'd1000000; end - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + if ((maccore_maccore_bus_errors != 32'd4294967295)) begin + if (maccore_maccore_bus_error) begin + maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1); end end - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - if (main_pulsesynchronizer0_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + core_tx_cdc_cdc_graycounter0_q_binary <= core_tx_cdc_cdc_graycounter0_q_next_binary; + core_tx_cdc_cdc_graycounter0_q <= core_tx_cdc_cdc_graycounter0_q_next; + if (core_pulsesynchronizer0_o) begin + core_preamble_errors_status <= (core_preamble_errors_status + 1'd1); end - if (main_pulsesynchronizer1_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); + if (core_pulsesynchronizer1_o) begin + core_crc_errors_status <= (core_crc_errors_status + 1'd1); end - main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; - main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - main_sram57_produce <= (main_sram57_produce + 1'd1); + core_pulsesynchronizer0_toggle_o_r <= core_pulsesynchronizer0_toggle_o; + core_pulsesynchronizer1_toggle_o_r <= core_pulsesynchronizer1_toggle_o; + core_rx_cdc_cdc_graycounter1_q_binary <= core_rx_cdc_cdc_graycounter1_q_next_binary; + core_rx_cdc_cdc_graycounter1_q <= core_rx_cdc_cdc_graycounter1_q_next; + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + wishbone_interface_writer_stat_fifo_produce <= (wishbone_interface_writer_stat_fifo_produce + 1'd1); end - if (main_sram63_do_read) begin - main_sram58_consume <= (main_sram58_consume + 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_consume <= (wishbone_interface_writer_stat_fifo_consume + 1'd1); end - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - if ((~main_sram63_do_read)) begin - main_sram55_level <= (main_sram55_level + 1'd1); + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + if ((~wishbone_interface_writer_stat_fifo_do_read)) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level + 1'd1); end end else begin - if (main_sram63_do_read) begin - main_sram55_level <= (main_sram55_level - 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level - 1'd1); end end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin - main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + liteethmacsramwriter_state <= liteethmacsramwriter_next_state; + if (wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce) begin + wishbone_interface_writer_length <= wishbone_interface_writer_length_liteethmacsramwriter_t_next_value; end - if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin - main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + if (wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce) begin + wishbone_interface_writer_errors_status <= wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value; end - if (main_slot_liteethmacsramwriter_next_value_ce) begin - main_slot <= main_slot_liteethmacsramwriter_next_value; + if (wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce) begin + wishbone_interface_writer_slot <= wishbone_interface_writer_slot_liteethmacsramwriter_next_value; end - if (main_sram108_clear) begin - main_sram106_pending <= 1'd0; + if (wishbone_interface_reader_eventsourcepulse_clear) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; end - if (main_sram107_trigger) begin - main_sram106_pending <= 1'd1; + if (wishbone_interface_reader_eventsourcepulse_trigger) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd1; end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - main_sram143_produce <= (main_sram143_produce + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + wishbone_interface_reader_cmd_fifo_produce <= (wishbone_interface_reader_cmd_fifo_produce + 1'd1); end - if (main_sram149_do_read) begin - main_sram144_consume <= (main_sram144_consume + 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_consume <= (wishbone_interface_reader_cmd_fifo_consume + 1'd1); end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - if ((~main_sram149_do_read)) begin - main_sram141_level <= (main_sram141_level + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + if ((~wishbone_interface_reader_cmd_fifo_do_read)) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level + 1'd1); end end else begin - if (main_sram149_do_read) begin - main_sram141_level <= (main_sram141_level - 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level - 1'd1); end end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_sram122_length_liteethmacsramreader_next_value_ce) begin - main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + liteethmacsramreader_state <= liteethmacsramreader_next_state; + if (wishbone_interface_reader_length_liteethmacsramreader_next_value_ce) begin + wishbone_interface_reader_length <= wishbone_interface_reader_length_liteethmacsramreader_next_value; end - main_interface0_ack <= 1'd0; - if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin - main_interface0_ack <= 1'd1; + wishbone_interface_interface0_ack <= 1'd0; + if (((wishbone_interface_interface0_cyc & wishbone_interface_interface0_stb) & ((~wishbone_interface_interface0_ack) | wishbone_interface_sram0_adr_burst))) begin + wishbone_interface_interface0_ack <= 1'd1; end - main_interface1_ack <= 1'd0; - if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin - main_interface1_ack <= 1'd1; + wishbone_interface_interface1_ack <= 1'd0; + if (((wishbone_interface_interface1_cyc & wishbone_interface_interface1_stb) & ((~wishbone_interface_interface1_ack) | wishbone_interface_sram1_adr_burst))) begin + wishbone_interface_interface1_ack <= 1'd1; end - main_interface2_ack <= 1'd0; - if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin - main_interface2_ack <= 1'd1; + wishbone_interface_decoder0_slave_sel_r <= wishbone_interface_decoder0_slave_sel; + wishbone_interface_interface2_ack <= 1'd0; + if (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & ((~wishbone_interface_interface2_ack) | wishbone_interface_sram2_adr_burst))) begin + wishbone_interface_interface2_ack <= 1'd1; end - main_interface3_ack <= 1'd0; - if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin - main_interface3_ack <= 1'd1; + wishbone_interface_interface3_ack <= 1'd0; + if (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & ((~wishbone_interface_interface3_ack) | wishbone_interface_sram3_adr_burst))) begin + wishbone_interface_interface3_ack <= 1'd1; end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) + wishbone_interface_decoder1_slave_sel_r <= wishbone_interface_decoder1_slave_sel; + state <= next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + interface0_bank_bus_dat_r <= csrbank0_reset0_w; end 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; end 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; end endcase end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + if (csrbank0_reset0_re) begin + maccore_maccore_reset_storage <= csrbank0_reset0_r; end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + maccore_maccore_reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + maccore_maccore_scratch_storage <= csrbank0_scratch0_r; end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) + maccore_maccore_scratch_re <= csrbank0_scratch0_re; + maccore_maccore_bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_slot_w; end 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_length_w; end 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_errors_w; end 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_status_w; end 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_pending_w; end 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_enable0_w; end 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_start_w; + interface1_bank_bus_dat_r <= wishbone_interface_reader_start_w; end 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ready_w; end 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_level_w; end 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_slot0_w; end 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_length0_w; end 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_status_w; end 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_pending_w; end 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_enable0_w; end 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + interface1_bank_bus_dat_r <= csrbank1_preamble_crc_w; end 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_preamble_errors_w; end 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_crc_errors_w; end endcase end - main_sram9_re <= builder_csrbank1_sram_writer_slot_re; - main_sram12_re <= builder_csrbank1_sram_writer_length_re; - main_sram15_re <= builder_csrbank1_sram_writer_errors_re; - main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + wishbone_interface_writer_slot_re <= csrbank1_sram_writer_slot_re; + wishbone_interface_writer_length_re <= csrbank1_sram_writer_length_re; + wishbone_interface_writer_errors_re <= csrbank1_sram_writer_errors_re; + wishbone_interface_writer_status_re <= csrbank1_sram_writer_ev_status_re; + if (csrbank1_sram_writer_ev_pending_re) begin + wishbone_interface_writer_pending_r <= csrbank1_sram_writer_ev_pending_r; end - main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + wishbone_interface_writer_pending_re <= csrbank1_sram_writer_ev_pending_re; + if (csrbank1_sram_writer_ev_enable0_re) begin + wishbone_interface_writer_enable_storage <= csrbank1_sram_writer_ev_enable0_r; end - main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_sram96_re <= builder_csrbank1_sram_reader_ready_re; - main_sram99_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + wishbone_interface_writer_enable_re <= csrbank1_sram_writer_ev_enable0_re; + wishbone_interface_reader_ready_re <= csrbank1_sram_reader_ready_re; + wishbone_interface_reader_level_re <= csrbank1_sram_reader_level_re; + if (csrbank1_sram_reader_slot0_re) begin + wishbone_interface_reader_slot_storage <= csrbank1_sram_reader_slot0_r; end - main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + wishbone_interface_reader_slot_re <= csrbank1_sram_reader_slot0_re; + if (csrbank1_sram_reader_length0_re) begin + wishbone_interface_reader_length_storage <= csrbank1_sram_reader_length0_r; end - main_sram103_re <= builder_csrbank1_sram_reader_length0_re; - main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + wishbone_interface_reader_length_re <= csrbank1_sram_reader_length0_re; + wishbone_interface_reader_status_re <= csrbank1_sram_reader_ev_status_re; + if (csrbank1_sram_reader_ev_pending_re) begin + wishbone_interface_reader_pending_r <= csrbank1_sram_reader_ev_pending_r; end - main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + wishbone_interface_reader_pending_re <= csrbank1_sram_reader_ev_pending_re; + if (csrbank1_sram_reader_ev_enable0_re) begin + wishbone_interface_reader_enable_storage <= csrbank1_sram_reader_ev_enable0_r; end - main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) + wishbone_interface_reader_enable_re <= csrbank1_sram_reader_ev_enable0_re; + core_re <= csrbank1_preamble_crc_re; + core_preamble_errors_re <= csrbank1_rx_datapath_preamble_errors_re; + core_crc_errors_re <= csrbank1_rx_datapath_crc_errors_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + interface2_bank_bus_dat_r <= csrbank2_crg_reset0_w; end 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_w0_w; end 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_r_w; end endcase end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + if (csrbank2_crg_reset0_re) begin + maccore_ethphy_reset_storage <= csrbank2_crg_reset0_r; end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + maccore_ethphy_reset_re <= csrbank2_crg_reset0_re; + if (csrbank2_mdio_w0_re) begin + maccore_ethphy__w_storage <= csrbank2_mdio_w0_r; end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + maccore_ethphy__w_re <= csrbank2_mdio_w0_re; + maccore_ethphy__r_re <= csrbank2_mdio_r_re; if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_sram9_re <= 1'd0; - main_sram12_re <= 1'd0; - main_sram13_status <= 32'd0; - main_sram15_re <= 1'd0; - main_sram24_re <= 1'd0; - main_sram28_re <= 1'd0; - main_sram29_r <= 1'd0; - main_sram31_storage <= 1'd0; - main_sram32_re <= 1'd0; - main_slot <= 1'd0; - main_sram35_length <= 11'd0; - main_sram55_level <= 2'd0; - main_sram57_produce <= 1'd0; - main_sram58_consume <= 1'd0; - main_sram96_re <= 1'd0; - main_sram99_re <= 1'd0; - main_sram101_re <= 1'd0; - main_sram103_re <= 1'd0; - main_sram106_pending <= 1'd0; - main_sram112_re <= 1'd0; - main_sram116_re <= 1'd0; - main_sram117_r <= 1'd0; - main_sram119_storage <= 1'd0; - main_sram120_re <= 1'd0; - main_sram122_length <= 11'd0; - main_sram141_level <= 2'd0; - main_sram143_produce <= 1'd0; - main_sram144_consume <= 1'd0; - main_interface0_ack <= 1'd0; - main_interface1_ack <= 1'd0; - main_interface2_ack <= 1'd0; - main_interface3_ack <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_state <= 1'd0; + maccore_maccore_reset_storage <= 2'd0; + maccore_maccore_reset_re <= 1'd0; + maccore_maccore_scratch_storage <= 32'd305419896; + maccore_maccore_scratch_re <= 1'd0; + maccore_maccore_bus_errors_re <= 1'd0; + maccore_maccore_bus_errors <= 32'd0; + maccore_ethphy_reset_storage <= 1'd0; + maccore_ethphy_reset_re <= 1'd0; + maccore_ethphy__w_storage <= 3'd0; + maccore_ethphy__w_re <= 1'd0; + maccore_ethphy__r_re <= 1'd0; + core_re <= 1'd0; + core_tx_cdc_cdc_graycounter0_q <= 6'd0; + core_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + core_preamble_errors_status <= 32'd0; + core_preamble_errors_re <= 1'd0; + core_crc_errors_status <= 32'd0; + core_crc_errors_re <= 1'd0; + core_rx_cdc_cdc_graycounter1_q <= 6'd0; + core_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + wishbone_interface_writer_slot_re <= 1'd0; + wishbone_interface_writer_length_re <= 1'd0; + wishbone_interface_writer_errors_status <= 32'd0; + wishbone_interface_writer_errors_re <= 1'd0; + wishbone_interface_writer_status_re <= 1'd0; + wishbone_interface_writer_pending_re <= 1'd0; + wishbone_interface_writer_pending_r <= 1'd0; + wishbone_interface_writer_enable_storage <= 1'd0; + wishbone_interface_writer_enable_re <= 1'd0; + wishbone_interface_writer_slot <= 1'd0; + wishbone_interface_writer_length <= 11'd0; + wishbone_interface_writer_stat_fifo_level <= 2'd0; + wishbone_interface_writer_stat_fifo_produce <= 1'd0; + wishbone_interface_writer_stat_fifo_consume <= 1'd0; + wishbone_interface_reader_ready_re <= 1'd0; + wishbone_interface_reader_level_re <= 1'd0; + wishbone_interface_reader_slot_re <= 1'd0; + wishbone_interface_reader_length_re <= 1'd0; + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; + wishbone_interface_reader_status_re <= 1'd0; + wishbone_interface_reader_pending_re <= 1'd0; + wishbone_interface_reader_pending_r <= 1'd0; + wishbone_interface_reader_enable_storage <= 1'd0; + wishbone_interface_reader_enable_re <= 1'd0; + wishbone_interface_reader_length <= 11'd0; + wishbone_interface_reader_cmd_fifo_level <= 2'd0; + wishbone_interface_reader_cmd_fifo_produce <= 1'd0; + wishbone_interface_reader_cmd_fifo_consume <= 1'd0; + wishbone_interface_interface0_ack <= 1'd0; + wishbone_interface_interface1_ack <= 1'd0; + wishbone_interface_decoder0_slave_sel_r <= 2'd0; + wishbone_interface_interface2_ack <= 1'd0; + wishbone_interface_interface3_ack <= 1'd0; + wishbone_interface_decoder1_slave_sel_r <= 2'd0; + slave_sel_r <= 3'd0; + count <= 20'd1000000; + liteethmacsramwriter_state <= 3'd0; + liteethmacsramreader_state <= 2'd0; + state <= 1'd0; end - builder_xilinxmultiregimpl00 <= main_maccore_ethphy_data_r; - builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; - builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; - builder_xilinxmultiregimpl30 <= main_pulsesynchronizer0_toggle_i; - builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; - builder_xilinxmultiregimpl40 <= main_pulsesynchronizer1_toggle_i; - builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; - builder_xilinxmultiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; + xilinxmultiregimpl00 <= maccore_ethphy_data_r; + xilinxmultiregimpl01 <= xilinxmultiregimpl00; + xilinxmultiregimpl20 <= core_tx_cdc_cdc_graycounter1_q; + xilinxmultiregimpl21 <= xilinxmultiregimpl20; + xilinxmultiregimpl30 <= core_pulsesynchronizer0_toggle_i; + xilinxmultiregimpl31 <= xilinxmultiregimpl30; + xilinxmultiregimpl40 <= core_pulsesynchronizer1_toggle_i; + xilinxmultiregimpl41 <= xilinxmultiregimpl40; + xilinxmultiregimpl50 <= core_rx_cdc_cdc_graycounter0_q; + xilinxmultiregimpl51 <= xilinxmultiregimpl50; end @@ -3740,7 +3666,7 @@ IBUF IBUF( .I (rgmii_clocks_rx), // Outputs. - .O (main_maccore_ethphy_eth_rx_clk_ibuf) + .O (maccore_ethphy_eth_rx_clk_ibuf) ); //------------------------------------------------------------------------------ @@ -3748,7 +3674,7 @@ IBUF IBUF( //------------------------------------------------------------------------------ BUFG BUFG( // Inputs. - .I (main_maccore_ethphy_eth_rx_clk_ibuf), + .I (maccore_ethphy_eth_rx_clk_ibuf), // Outputs. .O (eth_rx_clk) @@ -3759,10 +3685,10 @@ BUFG BUFG( //------------------------------------------------------------------------------ BUFG BUFG_1( // Inputs. - .I (main_maccore_ethphy_clkout0), + .I (maccore_ethphy_clkout0), // Outputs. - .O (main_maccore_ethphy_clkout_buf0) + .O (maccore_ethphy_clkout_buf0) ); //------------------------------------------------------------------------------ @@ -3770,10 +3696,10 @@ BUFG BUFG_1( //------------------------------------------------------------------------------ BUFG BUFG_2( // Inputs. - .I (main_maccore_ethphy_clkout1), + .I (maccore_ethphy_clkout1), // Outputs. - .O (main_maccore_ethphy_clkout_buf1) + .O (maccore_ethphy_clkout_buf1) ); //------------------------------------------------------------------------------ @@ -3792,7 +3718,7 @@ ODDR #( .S (1'd0), // Outputs. - .Q (main_maccore_ethphy_eth_tx_clk_obuf) + .Q (maccore_ethphy_eth_tx_clk_obuf) ); //------------------------------------------------------------------------------ @@ -3800,7 +3726,7 @@ ODDR #( //------------------------------------------------------------------------------ OBUF OBUF( // Inputs. - .I (main_maccore_ethphy_eth_tx_clk_obuf), + .I (maccore_ethphy_eth_tx_clk_obuf), // Outputs. .O (rgmii_clocks_tx) @@ -3816,13 +3742,13 @@ ODDR #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D1 (main_maccore_ethphy_sink_valid), - .D2 (main_maccore_ethphy_sink_valid), + .D1 (maccore_ethphy_sink_valid), + .D2 (maccore_ethphy_sink_valid), .R (1'd0), .S (1'd0), // Outputs. - .Q (main_maccore_ethphy_tx_ctl_obuf) + .Q (maccore_ethphy_tx_ctl_obuf) ); //------------------------------------------------------------------------------ @@ -3830,7 +3756,7 @@ ODDR #( //------------------------------------------------------------------------------ OBUF OBUF_1( // Inputs. - .I (main_maccore_ethphy_tx_ctl_obuf), + .I (maccore_ethphy_tx_ctl_obuf), // Outputs. .O (rgmii_tx_ctl) @@ -3846,13 +3772,13 @@ ODDR #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D1 (main_maccore_ethphy_sink_payload_data[0]), - .D2 (main_maccore_ethphy_sink_payload_data[4]), + .D1 (maccore_ethphy_sink_payload_data[0]), + .D2 (maccore_ethphy_sink_payload_data[4]), .R (1'd0), .S (1'd0), // Outputs. - .Q (main_maccore_ethphy_tx_data_obuf[0]) + .Q (maccore_ethphy_tx_data_obuf[0]) ); //------------------------------------------------------------------------------ @@ -3860,7 +3786,7 @@ ODDR #( //------------------------------------------------------------------------------ OBUF OBUF_2( // Inputs. - .I (main_maccore_ethphy_tx_data_obuf[0]), + .I (maccore_ethphy_tx_data_obuf[0]), // Outputs. .O (rgmii_tx_data[0]) @@ -3876,13 +3802,13 @@ ODDR #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D1 (main_maccore_ethphy_sink_payload_data[1]), - .D2 (main_maccore_ethphy_sink_payload_data[5]), + .D1 (maccore_ethphy_sink_payload_data[1]), + .D2 (maccore_ethphy_sink_payload_data[5]), .R (1'd0), .S (1'd0), // Outputs. - .Q (main_maccore_ethphy_tx_data_obuf[1]) + .Q (maccore_ethphy_tx_data_obuf[1]) ); //------------------------------------------------------------------------------ @@ -3890,7 +3816,7 @@ ODDR #( //------------------------------------------------------------------------------ OBUF OBUF_3( // Inputs. - .I (main_maccore_ethphy_tx_data_obuf[1]), + .I (maccore_ethphy_tx_data_obuf[1]), // Outputs. .O (rgmii_tx_data[1]) @@ -3906,13 +3832,13 @@ ODDR #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D1 (main_maccore_ethphy_sink_payload_data[2]), - .D2 (main_maccore_ethphy_sink_payload_data[6]), + .D1 (maccore_ethphy_sink_payload_data[2]), + .D2 (maccore_ethphy_sink_payload_data[6]), .R (1'd0), .S (1'd0), // Outputs. - .Q (main_maccore_ethphy_tx_data_obuf[2]) + .Q (maccore_ethphy_tx_data_obuf[2]) ); //------------------------------------------------------------------------------ @@ -3920,7 +3846,7 @@ ODDR #( //------------------------------------------------------------------------------ OBUF OBUF_4( // Inputs. - .I (main_maccore_ethphy_tx_data_obuf[2]), + .I (maccore_ethphy_tx_data_obuf[2]), // Outputs. .O (rgmii_tx_data[2]) @@ -3936,13 +3862,13 @@ ODDR #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D1 (main_maccore_ethphy_sink_payload_data[3]), - .D2 (main_maccore_ethphy_sink_payload_data[7]), + .D1 (maccore_ethphy_sink_payload_data[3]), + .D2 (maccore_ethphy_sink_payload_data[7]), .R (1'd0), .S (1'd0), // Outputs. - .Q (main_maccore_ethphy_tx_data_obuf[3]) + .Q (maccore_ethphy_tx_data_obuf[3]) ); //------------------------------------------------------------------------------ @@ -3950,7 +3876,7 @@ ODDR #( //------------------------------------------------------------------------------ OBUF OBUF_5( // Inputs. - .I (main_maccore_ethphy_tx_data_obuf[3]), + .I (maccore_ethphy_tx_data_obuf[3]), // Outputs. .O (rgmii_tx_data[3]) @@ -3964,7 +3890,7 @@ IBUF IBUF_1( .I (rgmii_rx_ctl), // Outputs. - .O (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) + .O (maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) ); //------------------------------------------------------------------------------ @@ -3979,13 +3905,13 @@ IDELAYE2 #( // Inputs. .C (1'd0), .CE (1'd0), - .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), + .IDATAIN (maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), .INC (1'd0), .LD (1'd0), .LDPIPEEN (1'd0), // Outputs. - .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) + .DATAOUT (maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) ); //------------------------------------------------------------------------------ @@ -3998,13 +3924,13 @@ IDDR #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), + .D (maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), .R (1'd0), .S (1'd0), // Outputs. - .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl), - .Q2 (main_maccore_ethphy_liteethphyrgmiirx) + .Q1 (maccore_ethphy_liteethphyrgmiirx_rx_ctl), + .Q2 (maccore_ethphy_liteethphyrgmiirx) ); //------------------------------------------------------------------------------ @@ -4015,7 +3941,7 @@ IBUF IBUF_2( .I (rgmii_rx_data[0]), // Outputs. - .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) + .O (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) ); //------------------------------------------------------------------------------ @@ -4030,13 +3956,13 @@ IDELAYE2 #( // Inputs. .C (1'd0), .CE (1'd0), - .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), + .IDATAIN (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), .INC (1'd0), .LD (1'd0), .LDPIPEEN (1'd0), // Outputs. - .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) + .DATAOUT (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) ); //------------------------------------------------------------------------------ @@ -4049,13 +3975,13 @@ IDDR #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), + .D (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), .R (1'd0), .S (1'd0), // Outputs. - .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[0]), - .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[4]) + .Q1 (maccore_ethphy_liteethphyrgmiirx_rx_data[0]), + .Q2 (maccore_ethphy_liteethphyrgmiirx_rx_data[4]) ); //------------------------------------------------------------------------------ @@ -4066,7 +3992,7 @@ IBUF IBUF_3( .I (rgmii_rx_data[1]), // Outputs. - .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) + .O (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) ); //------------------------------------------------------------------------------ @@ -4081,13 +4007,13 @@ IDELAYE2 #( // Inputs. .C (1'd0), .CE (1'd0), - .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), + .IDATAIN (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), .INC (1'd0), .LD (1'd0), .LDPIPEEN (1'd0), // Outputs. - .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) + .DATAOUT (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) ); //------------------------------------------------------------------------------ @@ -4100,13 +4026,13 @@ IDDR #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), + .D (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), .R (1'd0), .S (1'd0), // Outputs. - .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[1]), - .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[5]) + .Q1 (maccore_ethphy_liteethphyrgmiirx_rx_data[1]), + .Q2 (maccore_ethphy_liteethphyrgmiirx_rx_data[5]) ); //------------------------------------------------------------------------------ @@ -4117,7 +4043,7 @@ IBUF IBUF_4( .I (rgmii_rx_data[2]), // Outputs. - .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) + .O (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) ); //------------------------------------------------------------------------------ @@ -4132,13 +4058,13 @@ IDELAYE2 #( // Inputs. .C (1'd0), .CE (1'd0), - .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), + .IDATAIN (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), .INC (1'd0), .LD (1'd0), .LDPIPEEN (1'd0), // Outputs. - .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) + .DATAOUT (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) ); //------------------------------------------------------------------------------ @@ -4151,13 +4077,13 @@ IDDR #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), + .D (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), .R (1'd0), .S (1'd0), // Outputs. - .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[2]), - .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[6]) + .Q1 (maccore_ethphy_liteethphyrgmiirx_rx_data[2]), + .Q2 (maccore_ethphy_liteethphyrgmiirx_rx_data[6]) ); //------------------------------------------------------------------------------ @@ -4168,7 +4094,7 @@ IBUF IBUF_5( .I (rgmii_rx_data[3]), // Outputs. - .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) + .O (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) ); //------------------------------------------------------------------------------ @@ -4183,13 +4109,13 @@ IDELAYE2 #( // Inputs. .C (1'd0), .CE (1'd0), - .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), + .IDATAIN (maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), .INC (1'd0), .LD (1'd0), .LDPIPEEN (1'd0), // Outputs. - .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) + .DATAOUT (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) ); //------------------------------------------------------------------------------ @@ -4202,17 +4128,17 @@ IDDR #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), + .D (maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), .R (1'd0), .S (1'd0), // Outputs. - .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[3]), - .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[7]) + .Q1 (maccore_ethphy_liteethphyrgmiirx_rx_data[3]), + .Q2 (maccore_ethphy_liteethphyrgmiirx_rx_data[7]) ); -assign rgmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = rgmii_mdio; +assign rgmii_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz; +assign maccore_ethphy_data_r = rgmii_mdio; //------------------------------------------------------------------------------ // Memory storage: 32-words x 42-bit @@ -4223,15 +4149,15 @@ reg [41:0] storage[0:31]; reg [41:0] storage_dat0; reg [41:0] storage_dat1; always @(posedge sys_clk) begin - if (main_tx_cdc_cdc_wrport_we) - storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; + if (core_tx_cdc_cdc_wrport_we) + storage[core_tx_cdc_cdc_wrport_adr] <= core_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[core_tx_cdc_cdc_wrport_adr]; end always @(posedge eth_tx_clk) begin - storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; + storage_dat1 <= storage[core_tx_cdc_cdc_rdport_adr]; end -assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; -assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; +assign core_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign core_tx_cdc_cdc_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ @@ -4242,14 +4168,14 @@ assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; reg [11:0] storage_1[0:4]; reg [11:0] storage_1_dat0; always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; + if (core_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr] <= core_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr]; end always @(posedge eth_rx_clk) begin end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign core_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[core_liteethmaccrc32checker_syncfifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4261,15 +4187,15 @@ reg [41:0] storage_2[0:31]; reg [41:0] storage_2_dat0; reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin - if (main_rx_cdc_cdc_wrport_we) - storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; + if (core_rx_cdc_cdc_wrport_we) + storage_2[core_rx_cdc_cdc_wrport_adr] <= core_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[core_rx_cdc_cdc_wrport_adr]; end always @(posedge sys_clk) begin - storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; + storage_2_dat1 <= storage_2[core_rx_cdc_cdc_rdport_adr]; end -assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; +assign core_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign core_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; //------------------------------------------------------------------------------ @@ -4280,14 +4206,14 @@ assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; reg [13:0] storage_3[0:1]; reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_sram61_we) - storage_3[main_sram59_adr] <= main_sram62_dat_w; - storage_3_dat0 <= storage_3[main_sram59_adr]; + if (wishbone_interface_writer_stat_fifo_wrport_we) + storage_3[wishbone_interface_writer_stat_fifo_wrport_adr] <= wishbone_interface_writer_stat_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[wishbone_interface_writer_stat_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram60_dat_r = storage_3_dat0; -assign main_sram65_dat_r = storage_3[main_sram64_adr]; +assign wishbone_interface_writer_stat_fifo_wrport_dat_r = storage_3_dat0; +assign wishbone_interface_writer_stat_fifo_rdport_dat_r = storage_3[wishbone_interface_writer_stat_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4299,15 +4225,15 @@ reg [31:0] mem[0:382]; reg [8:0] mem_adr0; reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_sram77_we) - mem[main_sram75_adr] <= main_sram78_dat_w; - mem_adr0 <= main_sram75_adr; + if (wishbone_interface_writer_memory0_we) + mem[wishbone_interface_writer_memory0_adr] <= wishbone_interface_writer_memory0_dat_w; + mem_adr0 <= wishbone_interface_writer_memory0_adr; end always @(posedge sys_clk) begin - mem_dat1 <= mem[main_sram0_adr]; + mem_dat1 <= mem[wishbone_interface_sram0_adr]; end -assign main_sram76_dat_r = mem[mem_adr0]; -assign main_sram0_dat_r = mem_dat1; +assign wishbone_interface_writer_memory0_dat_r = mem[mem_adr0]; +assign wishbone_interface_sram0_dat_r = mem_dat1; //------------------------------------------------------------------------------ @@ -4319,15 +4245,15 @@ reg [31:0] mem_1[0:382]; reg [8:0] mem_1_adr0; reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_sram81_we) - mem_1[main_sram79_adr] <= main_sram82_dat_w; - mem_1_adr0 <= main_sram79_adr; + if (wishbone_interface_writer_memory1_we) + mem_1[wishbone_interface_writer_memory1_adr] <= wishbone_interface_writer_memory1_dat_w; + mem_1_adr0 <= wishbone_interface_writer_memory1_adr; end always @(posedge sys_clk) begin - mem_1_dat1 <= mem_1[main_sram1_adr]; + mem_1_dat1 <= mem_1[wishbone_interface_sram1_adr]; end -assign main_sram80_dat_r = mem_1[mem_1_adr0]; -assign main_sram1_dat_r = mem_1_dat1; +assign wishbone_interface_writer_memory1_dat_r = mem_1[mem_1_adr0]; +assign wishbone_interface_sram1_dat_r = mem_1_dat1; //------------------------------------------------------------------------------ @@ -4338,14 +4264,14 @@ assign main_sram1_dat_r = mem_1_dat1; reg [13:0] storage_4[0:1]; reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_sram147_we) - storage_4[main_sram145_adr] <= main_sram148_dat_w; - storage_4_dat0 <= storage_4[main_sram145_adr]; + if (wishbone_interface_reader_cmd_fifo_wrport_we) + storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr] <= wishbone_interface_reader_cmd_fifo_wrport_dat_w; + storage_4_dat0 <= storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram146_dat_r = storage_4_dat0; -assign main_sram151_dat_r = storage_4[main_sram150_adr]; +assign wishbone_interface_reader_cmd_fifo_wrport_dat_r = storage_4_dat0; +assign wishbone_interface_reader_cmd_fifo_rdport_dat_r = storage_4[wishbone_interface_reader_cmd_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4357,22 +4283,22 @@ reg [31:0] mem_2[0:382]; reg [31:0] mem_2_dat0; reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - if (main_sram163_re) - mem_2_dat0 <= mem_2[main_sram161_adr]; + if (wishbone_interface_reader_memory0_re) + mem_2_dat0 <= mem_2[wishbone_interface_reader_memory0_adr]; end always @(posedge sys_clk) begin - if (main_sram2_we[0]) - mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; - if (main_sram2_we[1]) - mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; - if (main_sram2_we[2]) - mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; - if (main_sram2_we[3]) - mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; - mem_2_adr1 <= main_sram2_adr; + if (wishbone_interface_sram2_we[0]) + mem_2[wishbone_interface_sram2_adr][7:0] <= wishbone_interface_sram2_dat_w[7:0]; + if (wishbone_interface_sram2_we[1]) + mem_2[wishbone_interface_sram2_adr][15:8] <= wishbone_interface_sram2_dat_w[15:8]; + if (wishbone_interface_sram2_we[2]) + mem_2[wishbone_interface_sram2_adr][23:16] <= wishbone_interface_sram2_dat_w[23:16]; + if (wishbone_interface_sram2_we[3]) + mem_2[wishbone_interface_sram2_adr][31:24] <= wishbone_interface_sram2_dat_w[31:24]; + mem_2_adr1 <= wishbone_interface_sram2_adr; end -assign main_sram162_dat_r = mem_2_dat0; -assign main_sram2_dat_r = mem_2[mem_2_adr1]; +assign wishbone_interface_reader_memory0_dat_r = mem_2_dat0; +assign wishbone_interface_sram2_dat_r = mem_2[mem_2_adr1]; //------------------------------------------------------------------------------ @@ -4384,22 +4310,22 @@ reg [31:0] mem_3[0:382]; reg [31:0] mem_3_dat0; reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - if (main_sram166_re) - mem_3_dat0 <= mem_3[main_sram164_adr]; + if (wishbone_interface_reader_memory1_re) + mem_3_dat0 <= mem_3[wishbone_interface_reader_memory1_adr]; end always @(posedge sys_clk) begin - if (main_sram3_we[0]) - mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; - if (main_sram3_we[1]) - mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; - if (main_sram3_we[2]) - mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; - if (main_sram3_we[3]) - mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; - mem_3_adr1 <= main_sram3_adr; + if (wishbone_interface_sram3_we[0]) + mem_3[wishbone_interface_sram3_adr][7:0] <= wishbone_interface_sram3_dat_w[7:0]; + if (wishbone_interface_sram3_we[1]) + mem_3[wishbone_interface_sram3_adr][15:8] <= wishbone_interface_sram3_dat_w[15:8]; + if (wishbone_interface_sram3_we[2]) + mem_3[wishbone_interface_sram3_adr][23:16] <= wishbone_interface_sram3_dat_w[23:16]; + if (wishbone_interface_sram3_we[3]) + mem_3[wishbone_interface_sram3_adr][31:24] <= wishbone_interface_sram3_dat_w[31:24]; + mem_3_adr1 <= wishbone_interface_sram3_adr; end -assign main_sram165_dat_r = mem_3_dat0; -assign main_sram3_dat_r = mem_3[mem_3_adr1]; +assign wishbone_interface_reader_memory1_dat_r = mem_3_dat0; +assign wishbone_interface_sram3_dat_r = mem_3[mem_3_adr1]; //------------------------------------------------------------------------------ @@ -4407,13 +4333,13 @@ assign main_sram3_dat_r = mem_3[mem_3_adr1]; //------------------------------------------------------------------------------ FDCE FDCE( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (main_maccore_ethphy_reset0), + .D (maccore_ethphy_reset0), // Outputs. - .Q (builder_reset0) + .Q (reset0) ); //------------------------------------------------------------------------------ @@ -4421,13 +4347,13 @@ FDCE FDCE( //------------------------------------------------------------------------------ FDCE FDCE_1( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset0), + .D (reset0), // Outputs. - .Q (builder_reset1) + .Q (reset1) ); //------------------------------------------------------------------------------ @@ -4435,13 +4361,13 @@ FDCE FDCE_1( //------------------------------------------------------------------------------ FDCE FDCE_2( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset1), + .D (reset1), // Outputs. - .Q (builder_reset2) + .Q (reset2) ); //------------------------------------------------------------------------------ @@ -4449,13 +4375,13 @@ FDCE FDCE_2( //------------------------------------------------------------------------------ FDCE FDCE_3( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset2), + .D (reset2), // Outputs. - .Q (builder_reset3) + .Q (reset3) ); //------------------------------------------------------------------------------ @@ -4463,13 +4389,13 @@ FDCE FDCE_3( //------------------------------------------------------------------------------ FDCE FDCE_4( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset3), + .D (reset3), // Outputs. - .Q (builder_reset4) + .Q (reset4) ); //------------------------------------------------------------------------------ @@ -4477,13 +4403,13 @@ FDCE FDCE_4( //------------------------------------------------------------------------------ FDCE FDCE_5( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset4), + .D (reset4), // Outputs. - .Q (builder_reset5) + .Q (reset5) ); //------------------------------------------------------------------------------ @@ -4491,13 +4417,13 @@ FDCE FDCE_5( //------------------------------------------------------------------------------ FDCE FDCE_6( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset5), + .D (reset5), // Outputs. - .Q (builder_reset6) + .Q (reset6) ); //------------------------------------------------------------------------------ @@ -4505,13 +4431,13 @@ FDCE FDCE_6( //------------------------------------------------------------------------------ FDCE FDCE_7( // Inputs. - .C (main_maccore_ethphy_clkin), + .C (maccore_ethphy_clkin), .CE (1'd1), .CLR (1'd0), - .D (builder_reset6), + .D (reset6), // Outputs. - .Q (builder_reset7) + .Q (reset7) ); //------------------------------------------------------------------------------ @@ -4530,16 +4456,16 @@ PLLE2_ADV #( .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( // Inputs. - .CLKFBIN (builder_pll_fb), - .CLKIN1 (main_maccore_ethphy_clkin), - .PWRDWN (main_maccore_ethphy_power_down), - .RST (builder_reset7), + .CLKFBIN (pll_fb), + .CLKIN1 (maccore_ethphy_clkin), + .PWRDWN (maccore_ethphy_power_down), + .RST (reset7), // Outputs. - .CLKFBOUT (builder_pll_fb), - .CLKOUT0 (main_maccore_ethphy_clkout0), - .CLKOUT1 (main_maccore_ethphy_clkout1), - .LOCKED (main_maccore_ethphy_locked) + .CLKFBOUT (pll_fb), + .CLKOUT0 (maccore_ethphy_clkout0), + .CLKOUT1 (maccore_ethphy_clkout1), + .LOCKED (maccore_ethphy_locked) ); (* ars_ff1 = "true", async_reg = "true" *) @@ -4554,10 +4480,10 @@ FDPE #( .C (eth_tx_delayed_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (xilinxasyncresetsynchronizerimpl0), // Outputs. - .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) + .Q (xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4571,11 +4497,11 @@ FDPE #( // Inputs. .C (eth_tx_delayed_clk), .CE (1'd1), - .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .D (xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (xilinxasyncresetsynchronizerimpl0), // Outputs. - .Q (builder_xilinxasyncresetsynchronizerimpl0_expr) + .Q (xilinxasyncresetsynchronizerimpl0_expr) ); (* ars_ff1 = "true", async_reg = "true" *) @@ -4590,10 +4516,10 @@ FDPE #( .C (eth_tx_clk), .CE (1'd1), .D (1'd0), - .PRE (main_maccore_ethphy_reset1), + .PRE (maccore_ethphy_reset1), // Outputs. - .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) + .Q (xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4607,8 +4533,8 @@ FDPE #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE (main_maccore_ethphy_reset1), + .D (xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (maccore_ethphy_reset1), // Outputs. .Q (eth_tx_rst) @@ -4626,10 +4552,10 @@ FDPE #( .C (eth_rx_clk), .CE (1'd1), .D (1'd0), - .PRE (main_maccore_ethphy_reset1), + .PRE (maccore_ethphy_reset1), // Outputs. - .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) + .Q (xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4643,8 +4569,8 @@ FDPE #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE (main_maccore_ethphy_reset1), + .D (xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (maccore_ethphy_reset1), // Outputs. .Q (eth_rx_rst) @@ -4653,5 +4579,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-05 17:38:49. +// Auto-Generated by LiteX on 2025-02-15 16:17:45. //------------------------------------------------------------------------------ diff --git a/liteeth/generated/wukong-v2/liteeth_core.v b/liteeth/generated/wukong-v2/liteeth_core.v index 9a2da5a..2dc187e 100644 --- a/liteeth/generated/wukong-v2/liteeth_core.v +++ b/liteeth/generated/wukong-v2/liteeth_core.v @@ -8,8 +8,8 @@ // // Filename : liteeth_core.v // Device : xc7 -// LiteX sha1 : 87137c30 -// Date : 2024-04-05 17:38:50 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 16:17:45 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -102,7 +102,8 @@ MACCore │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) -│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── last_handler (LiteEthLastHandler) +│ │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) @@ -159,9 +160,11 @@ MACCore │ │ │ └─── ev (SharedIRQ) │ │ └─── sram_0* (SRAM) │ │ └─── sram_1* (SRAM) +│ │ └─── decoder_0* (Decoder) │ │ └─── sram_2* (SRAM) │ │ └─── sram_3* (SRAM) -│ │ └─── decoder_0* (Decoder) +│ │ └─── decoder_1* (Decoder) +│ └─── ev (SharedIRQ) └─── csr_bridge (Wishbone2CSR) │ └─── fsm (FSM) └─── csr_bankarray (CSRBankArray) @@ -205,1737 +208,1727 @@ MACCore // Signals //------------------------------------------------------------------------------ -wire [13:0] builder_adr; -wire [39:0] builder_complexslicelowerer_slice_proxy; -reg [19:0] builder_count = 20'd1000000; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_reset0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_scratch0_we = 1'd0; -wire builder_csrbank0_sel; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; -reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; -reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; -reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; -reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; -wire builder_csrbank1_sel; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [10:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_w; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire builder_csrbank2_mode_detection_mode_r; -reg builder_csrbank2_mode_detection_mode_re = 1'd0; -wire builder_csrbank2_mode_detection_mode_w; -reg builder_csrbank2_mode_detection_mode_we = 1'd0; -wire builder_csrbank2_sel; -wire [31:0] builder_dat_r; -wire [31:0] builder_dat_w; -wire builder_done; -reg builder_error = 1'd0; -wire builder_grant; -reg builder_interface0_ack = 1'd0; -wire [29:0] builder_interface0_adr; -wire [13:0] builder_interface0_bank_bus_adr; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface0_bank_bus_dat_w; -wire builder_interface0_bank_bus_we; -wire [1:0] builder_interface0_bte; -wire [2:0] builder_interface0_cti; -wire builder_interface0_cyc; -reg [31:0] builder_interface0_dat_r = 32'd0; -wire [31:0] builder_interface0_dat_w; -reg builder_interface0_err = 1'd0; -wire [3:0] builder_interface0_sel; -wire builder_interface0_stb; -wire builder_interface0_we; -reg [13:0] builder_interface1_adr = 14'd0; -wire [13:0] builder_interface1_bank_bus_adr; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface1_bank_bus_dat_w; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_dat_r; -reg [31:0] builder_interface1_dat_w = 32'd0; -reg builder_interface1_we = 1'd0; -wire [13:0] builder_interface2_bank_bus_adr; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -wire [31:0] builder_interface2_bank_bus_dat_w; -wire builder_interface2_bank_bus_we; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg [1:0] builder_liteethphygmiimii_next_state = 2'd0; -reg [1:0] builder_liteethphygmiimii_state = 2'd0; -wire builder_request; -wire builder_rst_meta0; -wire builder_rst_meta1; -reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; -reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; -reg [29:0] builder_self0 = 30'd0; -reg [31:0] builder_self1 = 32'd0; -reg [3:0] builder_self2 = 4'd0; -reg builder_self3 = 1'd0; -reg builder_self4 = 1'd0; -reg builder_self5 = 1'd0; -reg [2:0] builder_self6 = 3'd0; -reg [1:0] builder_self7 = 2'd0; -reg builder_shared_ack = 1'd0; -wire [29:0] builder_shared_adr; -wire [1:0] builder_shared_bte; -wire [2:0] builder_shared_cti; -wire builder_shared_cyc; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [31:0] builder_shared_dat_w; -wire builder_shared_err; -wire [3:0] builder_shared_sel; -wire builder_shared_stb; -wire builder_shared_we; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -wire [31:0] builder_t_slice_proxy0; -wire [31:0] builder_t_slice_proxy1; -wire [31:0] builder_t_slice_proxy10; -wire [31:0] builder_t_slice_proxy11; -wire [31:0] builder_t_slice_proxy12; -wire [31:0] builder_t_slice_proxy13; -wire [31:0] builder_t_slice_proxy14; -wire [31:0] builder_t_slice_proxy15; -wire [31:0] builder_t_slice_proxy16; -wire [31:0] builder_t_slice_proxy17; -wire [31:0] builder_t_slice_proxy18; -wire [31:0] builder_t_slice_proxy19; -wire [31:0] builder_t_slice_proxy2; -wire [31:0] builder_t_slice_proxy20; -wire [31:0] builder_t_slice_proxy21; -wire [31:0] builder_t_slice_proxy22; -wire [31:0] builder_t_slice_proxy23; -wire [31:0] builder_t_slice_proxy24; -wire [31:0] builder_t_slice_proxy25; -wire [31:0] builder_t_slice_proxy26; -wire [31:0] builder_t_slice_proxy27; -wire [31:0] builder_t_slice_proxy28; -wire [31:0] builder_t_slice_proxy29; -wire [31:0] builder_t_slice_proxy3; -wire [31:0] builder_t_slice_proxy30; -wire [31:0] builder_t_slice_proxy31; -wire [31:0] builder_t_slice_proxy32; -wire [31:0] builder_t_slice_proxy33; -wire [31:0] builder_t_slice_proxy34; -wire [31:0] builder_t_slice_proxy35; -wire [31:0] builder_t_slice_proxy36; -wire [31:0] builder_t_slice_proxy37; -wire [31:0] builder_t_slice_proxy38; -wire [31:0] builder_t_slice_proxy39; -wire [31:0] builder_t_slice_proxy4; -wire [31:0] builder_t_slice_proxy40; -wire [31:0] builder_t_slice_proxy41; -wire [31:0] builder_t_slice_proxy42; -wire [31:0] builder_t_slice_proxy43; -wire [31:0] builder_t_slice_proxy44; -wire [31:0] builder_t_slice_proxy45; -wire [31:0] builder_t_slice_proxy46; -wire [31:0] builder_t_slice_proxy47; -wire [31:0] builder_t_slice_proxy48; -wire [31:0] builder_t_slice_proxy49; -wire [31:0] builder_t_slice_proxy5; -wire [31:0] builder_t_slice_proxy50; -wire [31:0] builder_t_slice_proxy51; -wire [31:0] builder_t_slice_proxy52; -wire [31:0] builder_t_slice_proxy53; -wire [31:0] builder_t_slice_proxy54; -wire [31:0] builder_t_slice_proxy55; -wire [31:0] builder_t_slice_proxy56; -wire [31:0] builder_t_slice_proxy57; -wire [31:0] builder_t_slice_proxy58; -wire [31:0] builder_t_slice_proxy59; -wire [31:0] builder_t_slice_proxy6; -wire [31:0] builder_t_slice_proxy60; -wire [31:0] builder_t_slice_proxy61; -wire [31:0] builder_t_slice_proxy62; -wire [31:0] builder_t_slice_proxy63; -wire [31:0] builder_t_slice_proxy7; -wire [31:0] builder_t_slice_proxy8; -wire [31:0] builder_t_slice_proxy9; -reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; -reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; -reg builder_txdatapath_liteethmacgap_next_state = 1'd0; -reg builder_txdatapath_liteethmacgap_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; -reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; -reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; -reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; -reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; -wire builder_wait; -wire builder_we; -reg builder_wishbone2csr_next_state = 1'd0; -reg builder_wishbone2csr_state = 1'd0; +wire [13:0] adr; +wire core_bufferizeendpoints_pipe_valid_sink_first; +wire core_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] core_bufferizeendpoints_pipe_valid_sink_payload_data; +wire core_bufferizeendpoints_pipe_valid_sink_payload_error; +wire core_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire core_bufferizeendpoints_pipe_valid_sink_ready; +wire core_bufferizeendpoints_pipe_valid_sink_valid; +reg core_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] core_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg core_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire core_bufferizeendpoints_pipe_valid_source_ready; +reg core_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire core_bufferizeendpoints_sink_sink_first; +wire core_bufferizeendpoints_sink_sink_last; +wire [7:0] core_bufferizeendpoints_sink_sink_payload_data; +wire core_bufferizeendpoints_sink_sink_payload_error; +wire core_bufferizeendpoints_sink_sink_payload_last_be; +wire core_bufferizeendpoints_sink_sink_ready; +wire core_bufferizeendpoints_sink_sink_valid; +wire core_bufferizeendpoints_source_source_first; +wire core_bufferizeendpoints_source_source_last; +wire [7:0] core_bufferizeendpoints_source_source_payload_data; +wire core_bufferizeendpoints_source_source_payload_error; +wire core_bufferizeendpoints_source_source_payload_last_be; +wire core_bufferizeendpoints_source_source_ready; +wire core_bufferizeendpoints_source_source_valid; +reg core_crc_errors_re = 1'd0; +reg [31:0] core_crc_errors_status = 32'd0; +wire core_crc_errors_we; +wire core_liteethmaccrc32checker_crc_be; +reg core_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] core_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] core_liteethmaccrc32checker_crc_data0; +wire [7:0] core_liteethmaccrc32checker_crc_data1; +reg core_liteethmaccrc32checker_crc_error0 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg core_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg core_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] core_liteethmaccrc32checker_crc_value = 32'd0; +reg core_liteethmaccrc32checker_error = 1'd0; +wire core_liteethmaccrc32checker_fifo_full; +wire core_liteethmaccrc32checker_fifo_in; +wire core_liteethmaccrc32checker_fifo_out; +reg core_liteethmaccrc32checker_fifo_reset = 1'd0; +reg core_liteethmaccrc32checker_last_be = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg core_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_first; +wire core_liteethmaccrc32checker_sink_sink_last; +wire [7:0] core_liteethmaccrc32checker_sink_sink_payload_data; +wire core_liteethmaccrc32checker_sink_sink_payload_error; +wire core_liteethmaccrc32checker_sink_sink_payload_last_be; +reg core_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire core_liteethmaccrc32checker_sink_sink_valid; +wire core_liteethmaccrc32checker_source_source_first; +reg core_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] core_liteethmaccrc32checker_source_source_payload_data; +reg core_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg core_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire core_liteethmaccrc32checker_source_source_ready; +reg core_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire core_liteethmaccrc32checker_syncfifo_do_read; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] core_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] core_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] core_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg core_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_sink_first; +wire core_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire core_liteethmaccrc32checker_syncfifo_sink_ready; +reg core_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_first; +wire core_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] core_liteethmaccrc32checker_syncfifo_source_payload_data; +wire core_liteethmaccrc32checker_syncfifo_source_payload_error; +wire core_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg core_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire core_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] core_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire core_liteethmaccrc32checker_syncfifo_wrport_we; +reg core_preamble_errors_re = 1'd0; +reg [31:0] core_preamble_errors_status = 32'd0; +wire core_preamble_errors_we; +wire core_pulsesynchronizer0_i; +wire core_pulsesynchronizer0_o; +reg core_pulsesynchronizer0_toggle_i = 1'd0; +wire core_pulsesynchronizer0_toggle_o; +reg core_pulsesynchronizer0_toggle_o_r = 1'd0; +wire core_pulsesynchronizer1_i; +wire core_pulsesynchronizer1_o; +reg core_pulsesynchronizer1_toggle_i = 1'd0; +wire core_pulsesynchronizer1_toggle_o; +reg core_pulsesynchronizer1_toggle_o_r = 1'd0; +reg core_re = 1'd0; +wire [41:0] core_rx_cdc_cdc_asyncfifo_din; +wire [41:0] core_rx_cdc_cdc_asyncfifo_dout; +wire core_rx_cdc_cdc_asyncfifo_re; +wire core_rx_cdc_cdc_asyncfifo_readable; +wire core_rx_cdc_cdc_asyncfifo_we; +wire core_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_rx_cdc_cdc_consume_wdomain; +wire core_rx_cdc_cdc_fifo_in_first; +wire core_rx_cdc_cdc_fifo_in_last; +wire [31:0] core_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_in_payload_last_be; +wire core_rx_cdc_cdc_fifo_out_first; +wire core_rx_cdc_cdc_fifo_out_last; +wire [31:0] core_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_rx_cdc_cdc_fifo_out_payload_last_be; +wire core_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] core_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] core_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_rx_cdc_cdc_produce_rdomain; +wire [4:0] core_rx_cdc_cdc_rdport_adr; +wire [41:0] core_rx_cdc_cdc_rdport_dat_r; +wire core_rx_cdc_cdc_sink_first; +wire core_rx_cdc_cdc_sink_last; +wire [31:0] core_rx_cdc_cdc_sink_payload_data; +wire [3:0] core_rx_cdc_cdc_sink_payload_error; +wire [3:0] core_rx_cdc_cdc_sink_payload_last_be; +wire core_rx_cdc_cdc_sink_ready; +wire core_rx_cdc_cdc_sink_valid; +wire core_rx_cdc_cdc_source_first; +wire core_rx_cdc_cdc_source_last; +wire [31:0] core_rx_cdc_cdc_source_payload_data; +wire [3:0] core_rx_cdc_cdc_source_payload_error; +wire [3:0] core_rx_cdc_cdc_source_payload_last_be; +wire core_rx_cdc_cdc_source_ready; +wire core_rx_cdc_cdc_source_valid; +wire [4:0] core_rx_cdc_cdc_wrport_adr; +wire [41:0] core_rx_cdc_cdc_wrport_dat_r; +wire [41:0] core_rx_cdc_cdc_wrport_dat_w; +wire core_rx_cdc_cdc_wrport_we; +wire core_rx_cdc_sink_sink_first; +wire core_rx_cdc_sink_sink_last; +wire [31:0] core_rx_cdc_sink_sink_payload_data; +wire [3:0] core_rx_cdc_sink_sink_payload_error; +wire [3:0] core_rx_cdc_sink_sink_payload_last_be; +wire core_rx_cdc_sink_sink_ready; +wire core_rx_cdc_sink_sink_valid; +wire core_rx_cdc_source_source_first; +wire core_rx_cdc_source_source_last; +wire [31:0] core_rx_cdc_source_source_payload_data; +wire [3:0] core_rx_cdc_source_source_payload_error; +wire [3:0] core_rx_cdc_source_source_payload_last_be; +wire core_rx_cdc_source_source_ready; +wire core_rx_cdc_source_source_valid; +reg [1:0] core_rx_converter_converter_demux = 2'd0; +wire core_rx_converter_converter_load_part; +wire core_rx_converter_converter_sink_first; +wire core_rx_converter_converter_sink_last; +wire [9:0] core_rx_converter_converter_sink_payload_data; +wire core_rx_converter_converter_sink_ready; +wire core_rx_converter_converter_sink_valid; +reg core_rx_converter_converter_source_first = 1'd0; +reg core_rx_converter_converter_source_last = 1'd0; +reg [39:0] core_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] core_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire core_rx_converter_converter_source_ready; +wire core_rx_converter_converter_source_valid; +reg core_rx_converter_converter_strobe_all = 1'd0; +wire core_rx_converter_sink_first; +wire core_rx_converter_sink_last; +wire [7:0] core_rx_converter_sink_payload_data; +wire core_rx_converter_sink_payload_error; +wire core_rx_converter_sink_payload_last_be; +wire core_rx_converter_sink_ready; +wire core_rx_converter_sink_valid; +wire core_rx_converter_source_first; +wire core_rx_converter_source_last; +reg [31:0] core_rx_converter_source_payload_data = 32'd0; +reg [3:0] core_rx_converter_source_payload_error = 4'd0; +reg [3:0] core_rx_converter_source_payload_last_be = 4'd0; +wire core_rx_converter_source_ready; +wire core_rx_converter_source_source_first; +wire core_rx_converter_source_source_last; +wire [39:0] core_rx_converter_source_source_payload_data; +wire core_rx_converter_source_source_ready; +wire core_rx_converter_source_source_valid; +wire core_rx_converter_source_valid; +wire core_rx_last_be_sink_first; +wire core_rx_last_be_sink_last; +wire [7:0] core_rx_last_be_sink_payload_data; +wire core_rx_last_be_sink_payload_error; +wire core_rx_last_be_sink_payload_last_be; +wire core_rx_last_be_sink_ready; +wire core_rx_last_be_sink_valid; +wire core_rx_last_be_source_first; +wire core_rx_last_be_source_last; +wire [7:0] core_rx_last_be_source_payload_data; +wire core_rx_last_be_source_payload_error; +reg core_rx_last_be_source_payload_last_be = 1'd0; +wire core_rx_last_be_source_ready; +wire core_rx_last_be_source_valid; +wire core_rx_padding_sink_first; +wire core_rx_padding_sink_last; +wire [7:0] core_rx_padding_sink_payload_data; +wire core_rx_padding_sink_payload_error; +wire core_rx_padding_sink_payload_last_be; +wire core_rx_padding_sink_ready; +wire core_rx_padding_sink_valid; +wire core_rx_padding_source_first; +wire core_rx_padding_source_last; +wire [7:0] core_rx_padding_source_payload_data; +wire core_rx_padding_source_payload_error; +wire core_rx_padding_source_payload_last_be; +wire core_rx_padding_source_ready; +wire core_rx_padding_source_valid; +reg core_rx_preamble_error = 1'd0; +reg [63:0] core_rx_preamble_preamble = 64'd15372286728091293013; +wire core_rx_preamble_sink_first; +wire core_rx_preamble_sink_last; +wire [7:0] core_rx_preamble_sink_payload_data; +wire core_rx_preamble_sink_payload_error; +wire core_rx_preamble_sink_payload_last_be; +reg core_rx_preamble_sink_ready = 1'd0; +wire core_rx_preamble_sink_valid; +reg core_rx_preamble_source_first = 1'd0; +reg core_rx_preamble_source_last = 1'd0; +wire [7:0] core_rx_preamble_source_payload_data; +reg core_rx_preamble_source_payload_error = 1'd0; +wire core_rx_preamble_source_payload_last_be; +wire core_rx_preamble_source_ready; +reg core_rx_preamble_source_valid = 1'd0; +wire core_sink_first; +wire core_sink_last; +wire [31:0] core_sink_payload_data; +wire [3:0] core_sink_payload_error; +wire [3:0] core_sink_payload_last_be; +wire core_sink_ready; +wire core_sink_valid; +wire core_source_first; +wire core_source_last; +wire [31:0] core_source_payload_data; +wire [3:0] core_source_payload_error; +wire [3:0] core_source_payload_last_be; +wire core_source_ready; +wire core_source_valid; +reg core_status = 1'd1; +wire [41:0] core_tx_cdc_cdc_asyncfifo_din; +wire [41:0] core_tx_cdc_cdc_asyncfifo_dout; +wire core_tx_cdc_cdc_asyncfifo_re; +wire core_tx_cdc_cdc_asyncfifo_readable; +wire core_tx_cdc_cdc_asyncfifo_we; +wire core_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] core_tx_cdc_cdc_consume_wdomain; +wire core_tx_cdc_cdc_fifo_in_first; +wire core_tx_cdc_cdc_fifo_in_last; +wire [31:0] core_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_in_payload_last_be; +wire core_tx_cdc_cdc_fifo_out_first; +wire core_tx_cdc_cdc_fifo_out_last; +wire [31:0] core_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] core_tx_cdc_cdc_fifo_out_payload_last_be; +wire core_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] core_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire core_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] core_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] core_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] core_tx_cdc_cdc_produce_rdomain; +wire [4:0] core_tx_cdc_cdc_rdport_adr; +wire [41:0] core_tx_cdc_cdc_rdport_dat_r; +wire core_tx_cdc_cdc_sink_first; +wire core_tx_cdc_cdc_sink_last; +wire [31:0] core_tx_cdc_cdc_sink_payload_data; +wire [3:0] core_tx_cdc_cdc_sink_payload_error; +wire [3:0] core_tx_cdc_cdc_sink_payload_last_be; +wire core_tx_cdc_cdc_sink_ready; +wire core_tx_cdc_cdc_sink_valid; +wire core_tx_cdc_cdc_source_first; +wire core_tx_cdc_cdc_source_last; +wire [31:0] core_tx_cdc_cdc_source_payload_data; +wire [3:0] core_tx_cdc_cdc_source_payload_error; +wire [3:0] core_tx_cdc_cdc_source_payload_last_be; +wire core_tx_cdc_cdc_source_ready; +wire core_tx_cdc_cdc_source_valid; +wire [4:0] core_tx_cdc_cdc_wrport_adr; +wire [41:0] core_tx_cdc_cdc_wrport_dat_r; +wire [41:0] core_tx_cdc_cdc_wrport_dat_w; +wire core_tx_cdc_cdc_wrport_we; +wire core_tx_cdc_sink_sink_first; +wire core_tx_cdc_sink_sink_last; +wire [31:0] core_tx_cdc_sink_sink_payload_data; +wire [3:0] core_tx_cdc_sink_sink_payload_error; +wire [3:0] core_tx_cdc_sink_sink_payload_last_be; +wire core_tx_cdc_sink_sink_ready; +wire core_tx_cdc_sink_sink_valid; +wire core_tx_cdc_source_source_first; +wire core_tx_cdc_source_source_last; +wire [31:0] core_tx_cdc_source_source_payload_data; +wire [3:0] core_tx_cdc_source_source_payload_error; +wire [3:0] core_tx_cdc_source_source_payload_last_be; +wire core_tx_cdc_source_source_ready; +wire core_tx_cdc_source_source_valid; +wire core_tx_converter_converter_first; +wire core_tx_converter_converter_last; +reg [1:0] core_tx_converter_converter_mux = 2'd0; +wire core_tx_converter_converter_sink_first; +wire core_tx_converter_converter_sink_last; +reg [39:0] core_tx_converter_converter_sink_payload_data = 40'd0; +wire core_tx_converter_converter_sink_ready; +wire core_tx_converter_converter_sink_valid; +wire core_tx_converter_converter_source_first; +wire core_tx_converter_converter_source_last; +reg [9:0] core_tx_converter_converter_source_payload_data = 10'd0; +wire core_tx_converter_converter_source_payload_valid_token_count; +wire core_tx_converter_converter_source_ready; +wire core_tx_converter_converter_source_valid; +wire core_tx_converter_sink_first; +wire core_tx_converter_sink_last; +wire [31:0] core_tx_converter_sink_payload_data; +wire [3:0] core_tx_converter_sink_payload_error; +wire [3:0] core_tx_converter_sink_payload_last_be; +wire core_tx_converter_sink_ready; +wire core_tx_converter_sink_valid; +wire core_tx_converter_source_first; +wire core_tx_converter_source_last; +wire [7:0] core_tx_converter_source_payload_data; +wire core_tx_converter_source_payload_error; +wire core_tx_converter_source_payload_last_be; +wire core_tx_converter_source_ready; +wire core_tx_converter_source_source_first; +wire core_tx_converter_source_source_last; +wire [9:0] core_tx_converter_source_source_payload_data; +wire core_tx_converter_source_source_ready; +wire core_tx_converter_source_source_valid; +wire core_tx_converter_source_valid; +wire core_tx_crc_be; +reg core_tx_crc_ce = 1'd0; +reg [1:0] core_tx_crc_cnt = 2'd3; +wire core_tx_crc_cnt_done; +reg [31:0] core_tx_crc_crc_next = 32'd0; +reg [31:0] core_tx_crc_crc_packet = 32'd0; +reg [31:0] core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] core_tx_crc_crc_prev; +wire [7:0] core_tx_crc_data0; +wire [7:0] core_tx_crc_data1; +reg core_tx_crc_error = 1'd0; +reg core_tx_crc_is_ongoing0 = 1'd0; +reg core_tx_crc_is_ongoing1 = 1'd0; +reg core_tx_crc_last_be = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire core_tx_crc_pipe_valid_sink_first; +wire core_tx_crc_pipe_valid_sink_last; +wire [7:0] core_tx_crc_pipe_valid_sink_payload_data; +wire core_tx_crc_pipe_valid_sink_payload_error; +wire core_tx_crc_pipe_valid_sink_payload_last_be; +wire core_tx_crc_pipe_valid_sink_ready; +wire core_tx_crc_pipe_valid_sink_valid; +reg core_tx_crc_pipe_valid_source_first = 1'd0; +reg core_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] core_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg core_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg core_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire core_tx_crc_pipe_valid_source_ready; +reg core_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] core_tx_crc_reg = 32'd4294967295; +reg core_tx_crc_reset = 1'd0; +wire core_tx_crc_sink_first; +wire core_tx_crc_sink_last; +wire [7:0] core_tx_crc_sink_payload_data; +wire core_tx_crc_sink_payload_error; +wire core_tx_crc_sink_payload_last_be; +reg core_tx_crc_sink_ready = 1'd0; +wire core_tx_crc_sink_sink_first; +wire core_tx_crc_sink_sink_last; +wire [7:0] core_tx_crc_sink_sink_payload_data; +wire core_tx_crc_sink_sink_payload_error; +wire core_tx_crc_sink_sink_payload_last_be; +wire core_tx_crc_sink_sink_ready; +wire core_tx_crc_sink_sink_valid; +wire core_tx_crc_sink_valid; +reg core_tx_crc_source_first = 1'd0; +reg core_tx_crc_source_last = 1'd0; +reg [7:0] core_tx_crc_source_payload_data = 8'd0; +reg core_tx_crc_source_payload_error = 1'd0; +reg core_tx_crc_source_payload_last_be = 1'd0; +wire core_tx_crc_source_ready; +wire core_tx_crc_source_source_first; +wire core_tx_crc_source_source_last; +wire [7:0] core_tx_crc_source_source_payload_data; +wire core_tx_crc_source_source_payload_error; +wire core_tx_crc_source_source_payload_last_be; +wire core_tx_crc_source_source_ready; +wire core_tx_crc_source_source_valid; +reg core_tx_crc_source_valid = 1'd0; +reg [31:0] core_tx_crc_value = 32'd0; +reg [3:0] core_tx_gap_counter = 4'd0; +reg [3:0] core_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg core_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire core_tx_gap_sink_first; +wire core_tx_gap_sink_last; +wire [7:0] core_tx_gap_sink_payload_data; +wire core_tx_gap_sink_payload_error; +wire core_tx_gap_sink_payload_last_be; +reg core_tx_gap_sink_ready = 1'd0; +wire core_tx_gap_sink_valid; +reg core_tx_gap_source_first = 1'd0; +reg core_tx_gap_source_last = 1'd0; +reg [7:0] core_tx_gap_source_payload_data = 8'd0; +reg core_tx_gap_source_payload_error = 1'd0; +reg core_tx_gap_source_payload_last_be = 1'd0; +wire core_tx_gap_source_ready; +reg core_tx_gap_source_valid = 1'd0; +wire core_tx_last_be_last_handler_sink_first; +wire core_tx_last_be_last_handler_sink_last; +wire [7:0] core_tx_last_be_last_handler_sink_payload_data; +wire core_tx_last_be_last_handler_sink_payload_error; +wire core_tx_last_be_last_handler_sink_payload_last_be; +reg core_tx_last_be_last_handler_sink_ready = 1'd0; +wire core_tx_last_be_last_handler_sink_valid; +reg core_tx_last_be_last_handler_source_first = 1'd0; +reg core_tx_last_be_last_handler_source_last = 1'd0; +reg [7:0] core_tx_last_be_last_handler_source_payload_data = 8'd0; +reg core_tx_last_be_last_handler_source_payload_error = 1'd0; +reg core_tx_last_be_last_handler_source_payload_last_be = 1'd0; +wire core_tx_last_be_last_handler_source_ready; +reg core_tx_last_be_last_handler_source_valid = 1'd0; +wire core_tx_last_be_sink_sink_first; +wire core_tx_last_be_sink_sink_last; +wire [7:0] core_tx_last_be_sink_sink_payload_data; +wire core_tx_last_be_sink_sink_payload_error; +wire core_tx_last_be_sink_sink_payload_last_be; +wire core_tx_last_be_sink_sink_ready; +wire core_tx_last_be_sink_sink_valid; +wire core_tx_last_be_source_source_first; +wire core_tx_last_be_source_source_last; +wire [7:0] core_tx_last_be_source_source_payload_data; +wire core_tx_last_be_source_source_payload_error; +wire core_tx_last_be_source_source_payload_last_be; +wire core_tx_last_be_source_source_ready; +wire core_tx_last_be_source_source_valid; +reg [15:0] core_tx_padding_counter = 16'd0; +reg [15:0] core_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg core_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire core_tx_padding_counter_done; +wire core_tx_padding_sink_first; +wire core_tx_padding_sink_last; +wire [7:0] core_tx_padding_sink_payload_data; +wire core_tx_padding_sink_payload_error; +wire core_tx_padding_sink_payload_last_be; +reg core_tx_padding_sink_ready = 1'd0; +wire core_tx_padding_sink_valid; +reg core_tx_padding_source_first = 1'd0; +reg core_tx_padding_source_last = 1'd0; +reg [7:0] core_tx_padding_source_payload_data = 8'd0; +reg core_tx_padding_source_payload_error = 1'd0; +reg core_tx_padding_source_payload_last_be = 1'd0; +wire core_tx_padding_source_ready; +reg core_tx_padding_source_valid = 1'd0; +reg [2:0] core_tx_preamble_count = 3'd0; +reg [2:0] core_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg core_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] core_tx_preamble_preamble = 64'd15372286728091293013; +wire core_tx_preamble_sink_first; +wire core_tx_preamble_sink_last; +wire [7:0] core_tx_preamble_sink_payload_data; +wire core_tx_preamble_sink_payload_error; +wire core_tx_preamble_sink_payload_last_be; +reg core_tx_preamble_sink_ready = 1'd0; +wire core_tx_preamble_sink_valid; +reg core_tx_preamble_source_first = 1'd0; +reg core_tx_preamble_source_last = 1'd0; +reg [7:0] core_tx_preamble_source_payload_data = 8'd0; +reg core_tx_preamble_source_payload_error = 1'd0; +wire core_tx_preamble_source_payload_last_be; +wire core_tx_preamble_source_ready; +reg core_tx_preamble_source_valid = 1'd0; +wire core_we; +reg [19:0] count = 20'd1000000; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire csrbank1_preamble_crc_r; +reg csrbank1_preamble_crc_re = 1'd0; +wire csrbank1_preamble_crc_w; +reg csrbank1_preamble_crc_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_r; +reg csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_crc_errors_w; +reg csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_r; +reg csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] csrbank1_rx_datapath_preamble_errors_w; +reg csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire csrbank1_sel; +wire csrbank1_sram_reader_ev_enable0_r; +reg csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire csrbank1_sram_reader_ev_enable0_w; +reg csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire csrbank1_sram_reader_ev_pending_r; +reg csrbank1_sram_reader_ev_pending_re = 1'd0; +wire csrbank1_sram_reader_ev_pending_w; +reg csrbank1_sram_reader_ev_pending_we = 1'd0; +wire csrbank1_sram_reader_ev_status_r; +reg csrbank1_sram_reader_ev_status_re = 1'd0; +wire csrbank1_sram_reader_ev_status_w; +reg csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_r; +reg csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] csrbank1_sram_reader_length0_w; +reg csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] csrbank1_sram_reader_level_r; +reg csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] csrbank1_sram_reader_level_w; +reg csrbank1_sram_reader_level_we = 1'd0; +wire csrbank1_sram_reader_ready_r; +reg csrbank1_sram_reader_ready_re = 1'd0; +wire csrbank1_sram_reader_ready_w; +reg csrbank1_sram_reader_ready_we = 1'd0; +wire csrbank1_sram_reader_slot0_r; +reg csrbank1_sram_reader_slot0_re = 1'd0; +wire csrbank1_sram_reader_slot0_w; +reg csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_r; +reg csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] csrbank1_sram_writer_errors_w; +reg csrbank1_sram_writer_errors_we = 1'd0; +wire csrbank1_sram_writer_ev_enable0_r; +reg csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire csrbank1_sram_writer_ev_enable0_w; +reg csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire csrbank1_sram_writer_ev_pending_r; +reg csrbank1_sram_writer_ev_pending_re = 1'd0; +wire csrbank1_sram_writer_ev_pending_w; +reg csrbank1_sram_writer_ev_pending_we = 1'd0; +wire csrbank1_sram_writer_ev_status_r; +reg csrbank1_sram_writer_ev_status_re = 1'd0; +wire csrbank1_sram_writer_ev_status_w; +reg csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] csrbank1_sram_writer_length_r; +reg csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] csrbank1_sram_writer_length_w; +reg csrbank1_sram_writer_length_we = 1'd0; +wire csrbank1_sram_writer_slot_r; +reg csrbank1_sram_writer_slot_re = 1'd0; +wire csrbank1_sram_writer_slot_w; +reg csrbank1_sram_writer_slot_we = 1'd0; +wire csrbank2_crg_reset0_r; +reg csrbank2_crg_reset0_re = 1'd0; +wire csrbank2_crg_reset0_w; +reg csrbank2_crg_reset0_we = 1'd0; +wire csrbank2_mdio_r_r; +reg csrbank2_mdio_r_re = 1'd0; +wire csrbank2_mdio_r_w; +reg csrbank2_mdio_r_we = 1'd0; +wire [2:0] csrbank2_mdio_w0_r; +reg csrbank2_mdio_w0_re = 1'd0; +wire [2:0] csrbank2_mdio_w0_w; +reg csrbank2_mdio_w0_we = 1'd0; +wire csrbank2_mode_detection_mode_r; +reg csrbank2_mode_detection_mode_re = 1'd0; +wire csrbank2_mode_detection_mode_w; +reg csrbank2_mode_detection_mode_we = 1'd0; +wire csrbank2_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +wire done; +reg error = 1'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire grant; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; +wire interface1_bank_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; +wire interface2_bank_bus_we; +reg [1:0] liteethmacsramreader_next_state = 2'd0; +reg [1:0] liteethmacsramreader_state = 2'd0; +reg [2:0] liteethmacsramwriter_next_state = 3'd0; +reg [2:0] liteethmacsramwriter_state = 3'd0; +reg [1:0] liteethphygmiimii_next_state = 2'd0; +reg [1:0] liteethphygmiimii_state = 2'd0; +reg maccore_ethphy__r_re = 1'd0; +reg maccore_ethphy__r_status = 1'd0; +wire maccore_ethphy__r_we; +reg maccore_ethphy__w_re = 1'd0; +reg [2:0] maccore_ethphy__w_storage = 3'd0; +reg [8:0] maccore_ethphy_counter = 9'd0; +wire maccore_ethphy_counter_ce; +wire maccore_ethphy_counter_done; +wire maccore_ethphy_data_oe; +wire maccore_ethphy_data_r; +wire maccore_ethphy_data_w; +reg maccore_ethphy_demux_endpoint0_source_first = 1'd0; +reg maccore_ethphy_demux_endpoint0_source_last = 1'd0; +reg [7:0] maccore_ethphy_demux_endpoint0_source_payload_data = 8'd0; +reg maccore_ethphy_demux_endpoint0_source_payload_error = 1'd0; +reg maccore_ethphy_demux_endpoint0_source_payload_last_be = 1'd0; +wire maccore_ethphy_demux_endpoint0_source_ready; +reg maccore_ethphy_demux_endpoint0_source_valid = 1'd0; +reg maccore_ethphy_demux_endpoint1_source_first = 1'd0; +reg maccore_ethphy_demux_endpoint1_source_last = 1'd0; +reg [7:0] maccore_ethphy_demux_endpoint1_source_payload_data = 8'd0; +reg maccore_ethphy_demux_endpoint1_source_payload_error = 1'd0; +reg maccore_ethphy_demux_endpoint1_source_payload_last_be = 1'd0; +wire maccore_ethphy_demux_endpoint1_source_ready; +reg maccore_ethphy_demux_endpoint1_source_valid = 1'd0; +wire maccore_ethphy_demux_sel; +wire maccore_ethphy_demux_sink_first; +wire maccore_ethphy_demux_sink_last; +wire [7:0] maccore_ethphy_demux_sink_payload_data; +wire maccore_ethphy_demux_sink_payload_error; +wire maccore_ethphy_demux_sink_payload_last_be; +reg maccore_ethphy_demux_sink_ready = 1'd0; +wire maccore_ethphy_demux_sink_valid; +reg [9:0] maccore_ethphy_eth_counter = 10'd0; +wire maccore_ethphy_eth_tick; +reg maccore_ethphy_eth_tx_clk = 1'd0; +reg maccore_ethphy_gmii_rx_dv_d = 1'd0; +reg maccore_ethphy_gmii_rx_source_first = 1'd0; +wire maccore_ethphy_gmii_rx_source_last; +reg [7:0] maccore_ethphy_gmii_rx_source_payload_data = 8'd0; +reg maccore_ethphy_gmii_rx_source_payload_error = 1'd0; +reg maccore_ethphy_gmii_rx_source_payload_last_be = 1'd0; +wire maccore_ethphy_gmii_rx_source_ready; +reg maccore_ethphy_gmii_rx_source_valid = 1'd0; +reg [7:0] maccore_ethphy_gmii_tx_pads_tx_data = 8'd0; +reg maccore_ethphy_gmii_tx_pads_tx_en = 1'd0; +reg maccore_ethphy_gmii_tx_pads_tx_er = 1'd0; +wire maccore_ethphy_gmii_tx_sink_first; +wire maccore_ethphy_gmii_tx_sink_last; +wire [7:0] maccore_ethphy_gmii_tx_sink_payload_data; +wire maccore_ethphy_gmii_tx_sink_payload_error; +wire maccore_ethphy_gmii_tx_sink_payload_last_be; +reg maccore_ethphy_gmii_tx_sink_ready = 1'd0; +wire maccore_ethphy_gmii_tx_sink_valid; +wire maccore_ethphy_i; +wire maccore_ethphy_mdc; +reg maccore_ethphy_mii_rx_converter_demux = 1'd0; +wire maccore_ethphy_mii_rx_converter_load_part; +reg maccore_ethphy_mii_rx_converter_sink_first = 1'd0; +wire maccore_ethphy_mii_rx_converter_sink_last; +reg [3:0] maccore_ethphy_mii_rx_converter_sink_payload_data = 4'd0; +wire maccore_ethphy_mii_rx_converter_sink_ready; +reg maccore_ethphy_mii_rx_converter_sink_valid = 1'd0; +reg maccore_ethphy_mii_rx_converter_source_first = 1'd0; +reg maccore_ethphy_mii_rx_converter_source_last = 1'd0; +reg [7:0] maccore_ethphy_mii_rx_converter_source_payload_data = 8'd0; +reg [1:0] maccore_ethphy_mii_rx_converter_source_payload_valid_token_count = 2'd0; +wire maccore_ethphy_mii_rx_converter_source_ready; +wire maccore_ethphy_mii_rx_converter_source_valid; +reg maccore_ethphy_mii_rx_converter_strobe_all = 1'd0; +reg maccore_ethphy_mii_rx_reset = 1'd0; +wire maccore_ethphy_mii_rx_source_first; +wire maccore_ethphy_mii_rx_source_last; +wire [7:0] maccore_ethphy_mii_rx_source_payload_data; +reg maccore_ethphy_mii_rx_source_payload_error = 1'd0; +reg maccore_ethphy_mii_rx_source_payload_last_be = 1'd0; +wire maccore_ethphy_mii_rx_source_ready; +wire maccore_ethphy_mii_rx_source_source_first; +wire maccore_ethphy_mii_rx_source_source_last; +wire [7:0] maccore_ethphy_mii_rx_source_source_payload_data; +wire maccore_ethphy_mii_rx_source_source_ready; +wire maccore_ethphy_mii_rx_source_source_valid; +wire maccore_ethphy_mii_rx_source_valid; +wire maccore_ethphy_mii_tx_converter_first; +wire maccore_ethphy_mii_tx_converter_last; +reg maccore_ethphy_mii_tx_converter_mux = 1'd0; +reg maccore_ethphy_mii_tx_converter_sink_first = 1'd0; +reg maccore_ethphy_mii_tx_converter_sink_last = 1'd0; +wire [7:0] maccore_ethphy_mii_tx_converter_sink_payload_data; +wire maccore_ethphy_mii_tx_converter_sink_ready; +wire maccore_ethphy_mii_tx_converter_sink_valid; +wire maccore_ethphy_mii_tx_converter_source_first; +wire maccore_ethphy_mii_tx_converter_source_last; +reg [3:0] maccore_ethphy_mii_tx_converter_source_payload_data = 4'd0; +wire maccore_ethphy_mii_tx_converter_source_payload_valid_token_count; +wire maccore_ethphy_mii_tx_converter_source_ready; +wire maccore_ethphy_mii_tx_converter_source_valid; +reg [7:0] maccore_ethphy_mii_tx_pads_tx_data = 8'd0; +reg maccore_ethphy_mii_tx_pads_tx_en = 1'd0; +reg maccore_ethphy_mii_tx_pads_tx_er = 1'd0; +wire maccore_ethphy_mii_tx_sink_first; +wire maccore_ethphy_mii_tx_sink_last; +wire [7:0] maccore_ethphy_mii_tx_sink_payload_data; +wire maccore_ethphy_mii_tx_sink_payload_error; +wire maccore_ethphy_mii_tx_sink_payload_last_be; +wire maccore_ethphy_mii_tx_sink_ready; +wire maccore_ethphy_mii_tx_sink_valid; +wire maccore_ethphy_mii_tx_source_source_first; +wire maccore_ethphy_mii_tx_source_source_last; +wire [3:0] maccore_ethphy_mii_tx_source_source_payload_data; +wire maccore_ethphy_mii_tx_source_source_ready; +wire maccore_ethphy_mii_tx_source_source_valid; +reg maccore_ethphy_mode0 = 1'd0; +reg maccore_ethphy_mode1 = 1'd0; +reg maccore_ethphy_mode_re = 1'd0; +wire maccore_ethphy_mode_status; +wire maccore_ethphy_mode_we; +wire maccore_ethphy_mux_endpoint0_sink_first; +wire maccore_ethphy_mux_endpoint0_sink_last; +wire [7:0] maccore_ethphy_mux_endpoint0_sink_payload_data; +wire maccore_ethphy_mux_endpoint0_sink_payload_error; +wire maccore_ethphy_mux_endpoint0_sink_payload_last_be; +reg maccore_ethphy_mux_endpoint0_sink_ready = 1'd0; +wire maccore_ethphy_mux_endpoint0_sink_valid; +wire maccore_ethphy_mux_endpoint1_sink_first; +wire maccore_ethphy_mux_endpoint1_sink_last; +wire [7:0] maccore_ethphy_mux_endpoint1_sink_payload_data; +wire maccore_ethphy_mux_endpoint1_sink_payload_error; +wire maccore_ethphy_mux_endpoint1_sink_payload_last_be; +reg maccore_ethphy_mux_endpoint1_sink_ready = 1'd0; +wire maccore_ethphy_mux_endpoint1_sink_valid; +wire maccore_ethphy_mux_sel; +reg maccore_ethphy_mux_source_first = 1'd0; +reg maccore_ethphy_mux_source_last = 1'd0; +reg [7:0] maccore_ethphy_mux_source_payload_data = 8'd0; +reg maccore_ethphy_mux_source_payload_error = 1'd0; +reg maccore_ethphy_mux_source_payload_last_be = 1'd0; +wire maccore_ethphy_mux_source_ready; +reg maccore_ethphy_mux_source_valid = 1'd0; +wire maccore_ethphy_o; +wire maccore_ethphy_oe; +reg [7:0] maccore_ethphy_pads_d_rx_data = 8'd0; +reg maccore_ethphy_pads_d_rx_dv = 1'd0; +reg maccore_ethphy_r = 1'd0; +wire maccore_ethphy_reset0; +wire maccore_ethphy_reset1; +reg maccore_ethphy_reset_re = 1'd0; +reg maccore_ethphy_reset_storage = 1'd0; +wire maccore_ethphy_sink_sink_first; +wire maccore_ethphy_sink_sink_last; +wire [7:0] maccore_ethphy_sink_sink_payload_data; +wire maccore_ethphy_sink_sink_payload_error; +wire maccore_ethphy_sink_sink_payload_last_be; +wire maccore_ethphy_sink_sink_ready; +wire maccore_ethphy_sink_sink_valid; +wire maccore_ethphy_source_source_first; +wire maccore_ethphy_source_source_last; +wire [7:0] maccore_ethphy_source_source_payload_data; +wire maccore_ethphy_source_source_payload_error; +wire maccore_ethphy_source_source_payload_last_be; +wire maccore_ethphy_source_source_ready; +wire maccore_ethphy_source_source_valid; +reg [23:0] maccore_ethphy_sys_counter = 24'd0; +reg maccore_ethphy_sys_counter_ce = 1'd0; +reg maccore_ethphy_sys_counter_reset = 1'd0; +wire maccore_ethphy_sys_tick; +reg maccore_ethphy_toggle_i = 1'd0; +wire maccore_ethphy_toggle_o; +reg maccore_ethphy_toggle_o_r = 1'd0; +reg maccore_ethphy_update_mode = 1'd0; +wire maccore_ethphy_w; +reg maccore_int_rst = 1'd1; +wire maccore_maccore_bus_error; +reg [31:0] maccore_maccore_bus_errors = 32'd0; +reg maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] maccore_maccore_bus_errors_status; +wire maccore_maccore_bus_errors_we; +wire maccore_maccore_cpu_rst; +reg maccore_maccore_reset_re = 1'd0; +reg [1:0] maccore_maccore_reset_storage = 2'd0; +reg maccore_maccore_scratch_re = 1'd0; +reg [31:0] maccore_maccore_scratch_storage = 32'd305419896; +reg maccore_maccore_soc_rst = 1'd0; +wire por_clk; +wire re; +wire request; +wire rst_meta0; +wire rst_meta1; +reg [1:0] rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] rxdatapath_bufferizeendpoints_state = 2'd0; +reg rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] self0 = 30'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [29:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg [2:0] slave_sel = 3'd0; +reg [2:0] slave_sel_r = 3'd0; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; +reg [1:0] txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] txdatapath_bufferizeendpoints_state = 2'd0; +reg txdatapath_liteethmacgap_next_state = 1'd0; +reg txdatapath_liteethmacgap_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg txdatapath_liteethmactxlastbe_state = 1'd0; +wire wait_1; +wire wb_bus_ack; +wire [29:0] wb_bus_adr; +wire [1:0] wb_bus_bte; +wire [2:0] wb_bus_cti; +wire wb_bus_cyc; +wire [31:0] wb_bus_dat_r; +wire [31:0] wb_bus_dat_w; +wire wb_bus_err; +wire [3:0] wb_bus_sel; +wire wb_bus_stb; +wire wb_bus_we; +wire we; +reg wishbone2csr_next_state = 1'd0; +reg wishbone2csr_state = 1'd0; +wire wishbone_interface_bus_rx_ack; +wire [29:0] wishbone_interface_bus_rx_adr; +wire [1:0] wishbone_interface_bus_rx_bte; +wire [2:0] wishbone_interface_bus_rx_cti; +wire wishbone_interface_bus_rx_cyc; +wire [31:0] wishbone_interface_bus_rx_dat_r; +wire [31:0] wishbone_interface_bus_rx_dat_w; +wire wishbone_interface_bus_rx_err; +wire [3:0] wishbone_interface_bus_rx_sel; +wire wishbone_interface_bus_rx_stb; +wire wishbone_interface_bus_rx_we; +wire wishbone_interface_bus_tx_ack; +wire [29:0] wishbone_interface_bus_tx_adr; +wire [1:0] wishbone_interface_bus_tx_bte; +wire [2:0] wishbone_interface_bus_tx_cti; +wire wishbone_interface_bus_tx_cyc; +wire [31:0] wishbone_interface_bus_tx_dat_r; +wire [31:0] wishbone_interface_bus_tx_dat_w; +wire wishbone_interface_bus_tx_err; +wire [3:0] wishbone_interface_bus_tx_sel; +wire wishbone_interface_bus_tx_stb; +wire wishbone_interface_bus_tx_we; +reg [1:0] wishbone_interface_decoder0_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder0_slave_sel_r = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel = 2'd0; +reg [1:0] wishbone_interface_decoder1_slave_sel_r = 2'd0; +wire wishbone_interface_ev_irq; +reg wishbone_interface_interface0_ack = 1'd0; +wire [29:0] wishbone_interface_interface0_adr; +wire [1:0] wishbone_interface_interface0_bte; +wire [2:0] wishbone_interface_interface0_cti; +wire wishbone_interface_interface0_cyc; +wire [31:0] wishbone_interface_interface0_dat_r; +wire [31:0] wishbone_interface_interface0_dat_w; +reg wishbone_interface_interface0_err = 1'd0; +wire [3:0] wishbone_interface_interface0_sel; +wire wishbone_interface_interface0_stb; +wire wishbone_interface_interface0_we; +reg wishbone_interface_interface1_ack = 1'd0; +wire [29:0] wishbone_interface_interface1_adr; +wire [1:0] wishbone_interface_interface1_bte; +wire [2:0] wishbone_interface_interface1_cti; +wire wishbone_interface_interface1_cyc; +wire [31:0] wishbone_interface_interface1_dat_r; +wire [31:0] wishbone_interface_interface1_dat_w; +reg wishbone_interface_interface1_err = 1'd0; +wire [3:0] wishbone_interface_interface1_sel; +wire wishbone_interface_interface1_stb; +wire wishbone_interface_interface1_we; +reg wishbone_interface_interface2_ack = 1'd0; +wire [29:0] wishbone_interface_interface2_adr; +wire [1:0] wishbone_interface_interface2_bte; +wire [2:0] wishbone_interface_interface2_cti; +wire wishbone_interface_interface2_cyc; +wire [31:0] wishbone_interface_interface2_dat_r; +wire [31:0] wishbone_interface_interface2_dat_w; +reg wishbone_interface_interface2_err = 1'd0; +wire [3:0] wishbone_interface_interface2_sel; +wire wishbone_interface_interface2_stb; +wire wishbone_interface_interface2_we; +reg wishbone_interface_interface3_ack = 1'd0; +wire [29:0] wishbone_interface_interface3_adr; +wire [1:0] wishbone_interface_interface3_bte; +wire [2:0] wishbone_interface_interface3_cti; +wire wishbone_interface_interface3_cyc; +wire [31:0] wishbone_interface_interface3_dat_r; +wire [31:0] wishbone_interface_interface3_dat_w; +reg wishbone_interface_interface3_err = 1'd0; +wire [3:0] wishbone_interface_interface3_sel; +wire wishbone_interface_interface3_stb; +wire wishbone_interface_interface3_we; +reg wishbone_interface_reader_cmd_fifo_consume = 1'd0; +wire wishbone_interface_reader_cmd_fifo_do_read; +wire wishbone_interface_reader_cmd_fifo_fifo_in_first; +wire wishbone_interface_reader_cmd_fifo_fifo_in_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_in_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot; +wire wishbone_interface_reader_cmd_fifo_fifo_out_first; +wire wishbone_interface_reader_cmd_fifo_fifo_out_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +wire wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_reader_cmd_fifo_level = 2'd0; +reg wishbone_interface_reader_cmd_fifo_produce = 1'd0; +wire wishbone_interface_reader_cmd_fifo_rdport_adr; +wire [13:0] wishbone_interface_reader_cmd_fifo_rdport_dat_r; +reg wishbone_interface_reader_cmd_fifo_replace = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_first = 1'd0; +reg wishbone_interface_reader_cmd_fifo_sink_last = 1'd0; +wire [10:0] wishbone_interface_reader_cmd_fifo_sink_payload_length; +wire wishbone_interface_reader_cmd_fifo_sink_payload_slot; +wire wishbone_interface_reader_cmd_fifo_sink_ready; +wire wishbone_interface_reader_cmd_fifo_sink_valid; +wire wishbone_interface_reader_cmd_fifo_source_first; +wire wishbone_interface_reader_cmd_fifo_source_last; +wire [10:0] wishbone_interface_reader_cmd_fifo_source_payload_length; +wire wishbone_interface_reader_cmd_fifo_source_payload_slot; +reg wishbone_interface_reader_cmd_fifo_source_ready = 1'd0; +wire wishbone_interface_reader_cmd_fifo_source_valid; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_din; +wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_dout; +wire wishbone_interface_reader_cmd_fifo_syncfifo_re; +wire wishbone_interface_reader_cmd_fifo_syncfifo_readable; +wire wishbone_interface_reader_cmd_fifo_syncfifo_we; +wire wishbone_interface_reader_cmd_fifo_syncfifo_writable; +reg wishbone_interface_reader_cmd_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_w; +wire wishbone_interface_reader_cmd_fifo_wrport_we; +reg wishbone_interface_reader_enable_re = 1'd0; +reg wishbone_interface_reader_enable_storage = 1'd0; +wire wishbone_interface_reader_event00; +wire wishbone_interface_reader_event01; +wire wishbone_interface_reader_event02; +reg wishbone_interface_reader_eventsourcepulse_clear = 1'd0; +reg wishbone_interface_reader_eventsourcepulse_pending = 1'd0; +wire wishbone_interface_reader_eventsourcepulse_status; +reg wishbone_interface_reader_eventsourcepulse_trigger = 1'd0; +wire wishbone_interface_reader_irq; +reg [10:0] wishbone_interface_reader_length = 11'd0; +reg [10:0] wishbone_interface_reader_length_liteethmacsramreader_next_value = 11'd0; +reg wishbone_interface_reader_length_liteethmacsramreader_next_value_ce = 1'd0; +reg wishbone_interface_reader_length_re = 1'd0; +reg [10:0] wishbone_interface_reader_length_storage = 11'd0; +reg wishbone_interface_reader_level_re = 1'd0; +wire [1:0] wishbone_interface_reader_level_status; +wire wishbone_interface_reader_level_we; +wire [8:0] wishbone_interface_reader_memory0_adr; +wire [31:0] wishbone_interface_reader_memory0_dat_r; +wire wishbone_interface_reader_memory0_re; +wire [8:0] wishbone_interface_reader_memory1_adr; +wire [31:0] wishbone_interface_reader_memory1_dat_r; +wire wishbone_interface_reader_memory1_re; +reg wishbone_interface_reader_pending_r = 1'd0; +reg wishbone_interface_reader_pending_re = 1'd0; +wire wishbone_interface_reader_pending_status; +wire wishbone_interface_reader_pending_we; +reg [31:0] wishbone_interface_reader_rd_data = 32'd0; +reg wishbone_interface_reader_read = 1'd0; +reg wishbone_interface_reader_ready_re = 1'd0; +wire wishbone_interface_reader_ready_status; +wire wishbone_interface_reader_ready_we; +reg wishbone_interface_reader_slot_re = 1'd0; +reg wishbone_interface_reader_slot_storage = 1'd0; +reg wishbone_interface_reader_source_source_first = 1'd0; +reg wishbone_interface_reader_source_source_last = 1'd0; +wire [31:0] wishbone_interface_reader_source_source_payload_data; +reg [3:0] wishbone_interface_reader_source_source_payload_error = 4'd0; +reg [3:0] wishbone_interface_reader_source_source_payload_last_be = 4'd0; +wire wishbone_interface_reader_source_source_ready; +reg wishbone_interface_reader_source_source_valid = 1'd0; +wire wishbone_interface_reader_start_r; +reg wishbone_interface_reader_start_re = 1'd0; +reg wishbone_interface_reader_start_w = 1'd0; +reg wishbone_interface_reader_start_we = 1'd0; +reg wishbone_interface_reader_status_re = 1'd0; +wire wishbone_interface_reader_status_status; +wire wishbone_interface_reader_status_we; +wire wishbone_interface_sink_first; +wire wishbone_interface_sink_last; +wire [31:0] wishbone_interface_sink_payload_data; +wire [3:0] wishbone_interface_sink_payload_error; +wire [3:0] wishbone_interface_sink_payload_last_be; +wire wishbone_interface_sink_ready; +wire wishbone_interface_sink_valid; +wire wishbone_interface_source_first; +wire wishbone_interface_source_last; +wire [31:0] wishbone_interface_source_payload_data; +wire [3:0] wishbone_interface_source_payload_error; +wire [3:0] wishbone_interface_source_payload_last_be; +wire wishbone_interface_source_ready; +wire wishbone_interface_source_valid; +wire [8:0] wishbone_interface_sram0_adr; +reg wishbone_interface_sram0_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram0_dat_r; +wire [8:0] wishbone_interface_sram1_adr; +reg wishbone_interface_sram1_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram1_dat_r; +wire [8:0] wishbone_interface_sram2_adr; +reg wishbone_interface_sram2_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram2_dat_r; +wire [31:0] wishbone_interface_sram2_dat_w; +reg [3:0] wishbone_interface_sram2_we = 4'd0; +wire [8:0] wishbone_interface_sram3_adr; +reg wishbone_interface_sram3_adr_burst = 1'd0; +wire [31:0] wishbone_interface_sram3_dat_r; +wire [31:0] wishbone_interface_sram3_dat_w; +reg [3:0] wishbone_interface_sram3_we = 4'd0; +wire wishbone_interface_writer_available0; +wire wishbone_interface_writer_available1; +wire wishbone_interface_writer_available2; +reg wishbone_interface_writer_available_clear = 1'd0; +wire wishbone_interface_writer_available_pending; +wire wishbone_interface_writer_available_status; +wire wishbone_interface_writer_available_trigger; +reg wishbone_interface_writer_enable_re = 1'd0; +reg wishbone_interface_writer_enable_storage = 1'd0; +reg wishbone_interface_writer_errors_re = 1'd0; +reg [31:0] wishbone_interface_writer_errors_status = 32'd0; +reg [31:0] wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value = 32'd0; +reg wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire wishbone_interface_writer_errors_we; +wire wishbone_interface_writer_irq; +reg [10:0] wishbone_interface_writer_length = 11'd0; +reg [3:0] wishbone_interface_writer_length_inc = 4'd0; +reg [10:0] wishbone_interface_writer_length_liteethmacsramwriter_t_next_value = 11'd0; +reg wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg wishbone_interface_writer_length_re = 1'd0; +wire [10:0] wishbone_interface_writer_length_status; +wire wishbone_interface_writer_length_we; +reg [8:0] wishbone_interface_writer_memory0_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory0_dat_r; +reg [31:0] wishbone_interface_writer_memory0_dat_w = 32'd0; +reg wishbone_interface_writer_memory0_we = 1'd0; +reg [8:0] wishbone_interface_writer_memory1_adr = 9'd0; +wire [31:0] wishbone_interface_writer_memory1_dat_r; +reg [31:0] wishbone_interface_writer_memory1_dat_w = 32'd0; +reg wishbone_interface_writer_memory1_we = 1'd0; +reg wishbone_interface_writer_pending_r = 1'd0; +reg wishbone_interface_writer_pending_re = 1'd0; +wire wishbone_interface_writer_pending_status; +wire wishbone_interface_writer_pending_we; +wire wishbone_interface_writer_sink_sink_first; +wire wishbone_interface_writer_sink_sink_last; +wire [31:0] wishbone_interface_writer_sink_sink_payload_data; +wire [3:0] wishbone_interface_writer_sink_sink_payload_error; +wire [3:0] wishbone_interface_writer_sink_sink_payload_last_be; +reg wishbone_interface_writer_sink_sink_ready = 1'd1; +wire wishbone_interface_writer_sink_sink_valid; +reg wishbone_interface_writer_slot = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value = 1'd0; +reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce = 1'd0; +reg wishbone_interface_writer_slot_re = 1'd0; +wire wishbone_interface_writer_slot_status; +wire wishbone_interface_writer_slot_we; +reg wishbone_interface_writer_stat_fifo_consume = 1'd0; +wire wishbone_interface_writer_stat_fifo_do_read; +wire wishbone_interface_writer_stat_fifo_fifo_in_first; +wire wishbone_interface_writer_stat_fifo_fifo_in_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_in_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_in_payload_slot; +wire wishbone_interface_writer_stat_fifo_fifo_out_first; +wire wishbone_interface_writer_stat_fifo_fifo_out_last; +wire [10:0] wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +wire wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +reg [1:0] wishbone_interface_writer_stat_fifo_level = 2'd0; +reg wishbone_interface_writer_stat_fifo_produce = 1'd0; +wire wishbone_interface_writer_stat_fifo_rdport_adr; +wire [13:0] wishbone_interface_writer_stat_fifo_rdport_dat_r; +reg wishbone_interface_writer_stat_fifo_replace = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_first = 1'd0; +reg wishbone_interface_writer_stat_fifo_sink_last = 1'd0; +reg [10:0] wishbone_interface_writer_stat_fifo_sink_payload_length = 11'd0; +reg wishbone_interface_writer_stat_fifo_sink_payload_slot = 1'd0; +wire wishbone_interface_writer_stat_fifo_sink_ready; +reg wishbone_interface_writer_stat_fifo_sink_valid = 1'd0; +wire wishbone_interface_writer_stat_fifo_source_first; +wire wishbone_interface_writer_stat_fifo_source_last; +wire [10:0] wishbone_interface_writer_stat_fifo_source_payload_length; +wire wishbone_interface_writer_stat_fifo_source_payload_slot; +wire wishbone_interface_writer_stat_fifo_source_ready; +wire wishbone_interface_writer_stat_fifo_source_valid; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_din; +wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_dout; +wire wishbone_interface_writer_stat_fifo_syncfifo_re; +wire wishbone_interface_writer_stat_fifo_syncfifo_readable; +wire wishbone_interface_writer_stat_fifo_syncfifo_we; +wire wishbone_interface_writer_stat_fifo_syncfifo_writable; +reg wishbone_interface_writer_stat_fifo_wrport_adr = 1'd0; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_r; +wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_w; +wire wishbone_interface_writer_stat_fifo_wrport_we; +reg wishbone_interface_writer_status_re = 1'd0; +wire wishbone_interface_writer_status_status; +wire wishbone_interface_writer_status_we; +wire [31:0] wishbone_interface_writer_wr_data; +reg wishbone_interface_writer_write = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl00 = 1'd0; +reg xilinxmultiregimpl00 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl01 = 1'd0; +reg xilinxmultiregimpl01 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl10 = 1'd0; +reg xilinxmultiregimpl10 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl11 = 1'd0; +reg xilinxmultiregimpl11 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +reg [5:0] xilinxmultiregimpl20 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +reg [5:0] xilinxmultiregimpl21 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl30 = 6'd0; +reg [5:0] xilinxmultiregimpl30 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl31 = 6'd0; +reg [5:0] xilinxmultiregimpl31 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl40 = 1'd0; +reg xilinxmultiregimpl40 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl41 = 1'd0; +reg xilinxmultiregimpl41 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl50 = 1'd0; +reg xilinxmultiregimpl50 = 1'd0; (* async_reg = "true", dont_touch = "true" *) -reg builder_xilinxmultiregimpl51 = 1'd0; +reg xilinxmultiregimpl51 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +reg [5:0] xilinxmultiregimpl60 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +reg [5:0] xilinxmultiregimpl61 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl70 = 6'd0; +reg [5:0] xilinxmultiregimpl70 = 6'd0; (* async_reg = "true", dont_touch = "true" *) -reg [5:0] builder_xilinxmultiregimpl71 = 6'd0; -(* dont_touch = "true" *) -wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) -wire eth_tx_clk; -wire eth_tx_rst; -wire main_bufferizeendpoints_pipe_valid_sink_first; -wire main_bufferizeendpoints_pipe_valid_sink_last; -wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; -wire main_bufferizeendpoints_pipe_valid_sink_payload_error; -wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; -wire main_bufferizeendpoints_pipe_valid_sink_ready; -wire main_bufferizeendpoints_pipe_valid_sink_valid; -reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; -reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; -reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; -wire main_bufferizeendpoints_pipe_valid_source_ready; -reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; -wire main_bufferizeendpoints_sink_sink_first; -wire main_bufferizeendpoints_sink_sink_last; -wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; -wire main_bufferizeendpoints_sink_sink_payload_error; -wire main_bufferizeendpoints_sink_sink_payload_last_be; -wire main_bufferizeendpoints_sink_sink_ready; -wire main_bufferizeendpoints_sink_sink_valid; -wire main_bufferizeendpoints_source_source_first; -wire main_bufferizeendpoints_source_source_last; -wire [7:0] main_bufferizeendpoints_source_source_payload_data; -wire main_bufferizeendpoints_source_source_payload_error; -wire main_bufferizeendpoints_source_source_payload_last_be; -wire main_bufferizeendpoints_source_source_ready; -wire main_bufferizeendpoints_source_source_valid; -wire main_bus_ack; -wire [29:0] main_bus_adr; -wire [1:0] main_bus_bte; -wire [2:0] main_bus_cti; -wire main_bus_cyc; -wire [31:0] main_bus_dat_r; -wire [31:0] main_bus_dat_w; -wire main_bus_err; -wire [3:0] main_bus_sel; -wire main_bus_stb; -wire main_bus_we; -reg main_crc_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_interface0_ack = 1'd0; -wire [29:0] main_interface0_adr; -wire [1:0] main_interface0_bte; -wire [2:0] main_interface0_cti; -wire main_interface0_cyc; -wire [31:0] main_interface0_dat_r; -wire [31:0] main_interface0_dat_w; -reg main_interface0_err = 1'd0; -wire [3:0] main_interface0_sel; -wire main_interface0_stb; -wire main_interface0_we; -reg main_interface1_ack = 1'd0; -wire [29:0] main_interface1_adr; -wire [1:0] main_interface1_bte; -wire [2:0] main_interface1_cti; -wire main_interface1_cyc; -wire [31:0] main_interface1_dat_r; -wire [31:0] main_interface1_dat_w; -reg main_interface1_err = 1'd0; -wire [3:0] main_interface1_sel; -wire main_interface1_stb; -wire main_interface1_we; -reg main_interface2_ack = 1'd0; -wire [29:0] main_interface2_adr; -wire [1:0] main_interface2_bte; -wire [2:0] main_interface2_cti; -wire main_interface2_cyc; -wire [31:0] main_interface2_dat_r; -wire [31:0] main_interface2_dat_w; -reg main_interface2_err = 1'd0; -wire [3:0] main_interface2_sel; -wire main_interface2_stb; -wire main_interface2_we; -reg main_interface3_ack = 1'd0; -wire [29:0] main_interface3_adr; -wire [1:0] main_interface3_bte; -wire [2:0] main_interface3_cti; -wire main_interface3_cyc; -wire [31:0] main_interface3_dat_r; -wire [31:0] main_interface3_dat_w; -reg main_interface3_err = 1'd0; -wire [3:0] main_interface3_sel; -wire main_interface3_stb; -wire main_interface3_we; -reg [3:0] main_length_inc = 4'd0; -wire main_liteethmaccrc32checker_crc_be; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; -wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -reg main_liteethmaccrc32checker_crc_error0 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; -reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; -reg main_liteethmaccrc32checker_error = 1'd0; -wire main_liteethmaccrc32checker_fifo_full; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -reg main_liteethmaccrc32checker_last_be = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; -reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -wire main_liteethmaccrc32checker_source_source_first; -reg main_liteethmaccrc32checker_source_source_last = 1'd0; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_valid = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -reg main_maccore_ethphy__r_re = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__w_re = 1'd0; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -reg [8:0] main_maccore_ethphy_counter = 9'd0; -wire main_maccore_ethphy_counter_ce; -wire main_maccore_ethphy_counter_done; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_maccore_ethphy_data_w; -reg main_maccore_ethphy_demux_endpoint0_source_first = 1'd0; -reg main_maccore_ethphy_demux_endpoint0_source_last = 1'd0; -reg [7:0] main_maccore_ethphy_demux_endpoint0_source_payload_data = 8'd0; -reg main_maccore_ethphy_demux_endpoint0_source_payload_error = 1'd0; -reg main_maccore_ethphy_demux_endpoint0_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_demux_endpoint0_source_ready; -reg main_maccore_ethphy_demux_endpoint0_source_valid = 1'd0; -reg main_maccore_ethphy_demux_endpoint1_source_first = 1'd0; -reg main_maccore_ethphy_demux_endpoint1_source_last = 1'd0; -reg [7:0] main_maccore_ethphy_demux_endpoint1_source_payload_data = 8'd0; -reg main_maccore_ethphy_demux_endpoint1_source_payload_error = 1'd0; -reg main_maccore_ethphy_demux_endpoint1_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_demux_endpoint1_source_ready; -reg main_maccore_ethphy_demux_endpoint1_source_valid = 1'd0; -wire main_maccore_ethphy_demux_sel; -wire main_maccore_ethphy_demux_sink_first; -wire main_maccore_ethphy_demux_sink_last; -wire [7:0] main_maccore_ethphy_demux_sink_payload_data; -wire main_maccore_ethphy_demux_sink_payload_error; -wire main_maccore_ethphy_demux_sink_payload_last_be; -reg main_maccore_ethphy_demux_sink_ready = 1'd0; -wire main_maccore_ethphy_demux_sink_valid; -reg [9:0] main_maccore_ethphy_eth_counter = 10'd0; -wire main_maccore_ethphy_eth_tick; -reg main_maccore_ethphy_eth_tx_clk = 1'd0; -reg main_maccore_ethphy_gmii_rx_dv_d = 1'd0; -reg main_maccore_ethphy_gmii_rx_source_first = 1'd0; -wire main_maccore_ethphy_gmii_rx_source_last; -reg [7:0] main_maccore_ethphy_gmii_rx_source_payload_data = 8'd0; -reg main_maccore_ethphy_gmii_rx_source_payload_error = 1'd0; -reg main_maccore_ethphy_gmii_rx_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_gmii_rx_source_ready; -reg main_maccore_ethphy_gmii_rx_source_valid = 1'd0; -reg [7:0] main_maccore_ethphy_gmii_tx_pads_tx_data = 8'd0; -reg main_maccore_ethphy_gmii_tx_pads_tx_en = 1'd0; -reg main_maccore_ethphy_gmii_tx_pads_tx_er = 1'd0; -wire main_maccore_ethphy_gmii_tx_sink_first; -wire main_maccore_ethphy_gmii_tx_sink_last; -wire [7:0] main_maccore_ethphy_gmii_tx_sink_payload_data; -wire main_maccore_ethphy_gmii_tx_sink_payload_error; -wire main_maccore_ethphy_gmii_tx_sink_payload_last_be; -reg main_maccore_ethphy_gmii_tx_sink_ready = 1'd0; -wire main_maccore_ethphy_gmii_tx_sink_valid; -wire main_maccore_ethphy_i; -wire main_maccore_ethphy_mdc; -reg main_maccore_ethphy_mii_rx_converter_demux = 1'd0; -wire main_maccore_ethphy_mii_rx_converter_load_part; -reg main_maccore_ethphy_mii_rx_converter_sink_first = 1'd0; -wire main_maccore_ethphy_mii_rx_converter_sink_last; -reg [3:0] main_maccore_ethphy_mii_rx_converter_sink_payload_data = 4'd0; -wire main_maccore_ethphy_mii_rx_converter_sink_ready; -reg main_maccore_ethphy_mii_rx_converter_sink_valid = 1'd0; -reg main_maccore_ethphy_mii_rx_converter_source_first = 1'd0; -reg main_maccore_ethphy_mii_rx_converter_source_last = 1'd0; -reg [7:0] main_maccore_ethphy_mii_rx_converter_source_payload_data = 8'd0; -reg [1:0] main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count = 2'd0; -wire main_maccore_ethphy_mii_rx_converter_source_ready; -wire main_maccore_ethphy_mii_rx_converter_source_valid; -reg main_maccore_ethphy_mii_rx_converter_strobe_all = 1'd0; -reg main_maccore_ethphy_mii_rx_reset = 1'd0; -wire main_maccore_ethphy_mii_rx_source_first; -wire main_maccore_ethphy_mii_rx_source_last; -wire [7:0] main_maccore_ethphy_mii_rx_source_payload_data; -reg main_maccore_ethphy_mii_rx_source_payload_error = 1'd0; -reg main_maccore_ethphy_mii_rx_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_mii_rx_source_ready; -wire main_maccore_ethphy_mii_rx_source_source_first; -wire main_maccore_ethphy_mii_rx_source_source_last; -wire [7:0] main_maccore_ethphy_mii_rx_source_source_payload_data; -wire main_maccore_ethphy_mii_rx_source_source_ready; -wire main_maccore_ethphy_mii_rx_source_source_valid; -wire main_maccore_ethphy_mii_rx_source_valid; -wire main_maccore_ethphy_mii_tx_converter_first; -wire main_maccore_ethphy_mii_tx_converter_last; -reg main_maccore_ethphy_mii_tx_converter_mux = 1'd0; -reg main_maccore_ethphy_mii_tx_converter_sink_first = 1'd0; -reg main_maccore_ethphy_mii_tx_converter_sink_last = 1'd0; -wire [7:0] main_maccore_ethphy_mii_tx_converter_sink_payload_data; -wire main_maccore_ethphy_mii_tx_converter_sink_ready; -wire main_maccore_ethphy_mii_tx_converter_sink_valid; -wire main_maccore_ethphy_mii_tx_converter_source_first; -wire main_maccore_ethphy_mii_tx_converter_source_last; -reg [3:0] main_maccore_ethphy_mii_tx_converter_source_payload_data = 4'd0; -wire main_maccore_ethphy_mii_tx_converter_source_payload_valid_token_count; -wire main_maccore_ethphy_mii_tx_converter_source_ready; -wire main_maccore_ethphy_mii_tx_converter_source_valid; -reg [7:0] main_maccore_ethphy_mii_tx_pads_tx_data = 8'd0; -reg main_maccore_ethphy_mii_tx_pads_tx_en = 1'd0; -reg main_maccore_ethphy_mii_tx_pads_tx_er = 1'd0; -wire main_maccore_ethphy_mii_tx_sink_first; -wire main_maccore_ethphy_mii_tx_sink_last; -wire [7:0] main_maccore_ethphy_mii_tx_sink_payload_data; -wire main_maccore_ethphy_mii_tx_sink_payload_error; -wire main_maccore_ethphy_mii_tx_sink_payload_last_be; -wire main_maccore_ethphy_mii_tx_sink_ready; -wire main_maccore_ethphy_mii_tx_sink_valid; -wire main_maccore_ethphy_mii_tx_source_source_first; -wire main_maccore_ethphy_mii_tx_source_source_last; -wire [3:0] main_maccore_ethphy_mii_tx_source_source_payload_data; -wire main_maccore_ethphy_mii_tx_source_source_ready; -wire main_maccore_ethphy_mii_tx_source_source_valid; -reg main_maccore_ethphy_mode0 = 1'd0; -reg main_maccore_ethphy_mode1 = 1'd0; -reg main_maccore_ethphy_mode_re = 1'd0; -wire main_maccore_ethphy_mode_status; -wire main_maccore_ethphy_mode_we; -wire main_maccore_ethphy_mux_endpoint0_sink_first; -wire main_maccore_ethphy_mux_endpoint0_sink_last; -wire [7:0] main_maccore_ethphy_mux_endpoint0_sink_payload_data; -wire main_maccore_ethphy_mux_endpoint0_sink_payload_error; -wire main_maccore_ethphy_mux_endpoint0_sink_payload_last_be; -reg main_maccore_ethphy_mux_endpoint0_sink_ready = 1'd0; -wire main_maccore_ethphy_mux_endpoint0_sink_valid; -wire main_maccore_ethphy_mux_endpoint1_sink_first; -wire main_maccore_ethphy_mux_endpoint1_sink_last; -wire [7:0] main_maccore_ethphy_mux_endpoint1_sink_payload_data; -wire main_maccore_ethphy_mux_endpoint1_sink_payload_error; -wire main_maccore_ethphy_mux_endpoint1_sink_payload_last_be; -reg main_maccore_ethphy_mux_endpoint1_sink_ready = 1'd0; -wire main_maccore_ethphy_mux_endpoint1_sink_valid; -wire main_maccore_ethphy_mux_sel; -reg main_maccore_ethphy_mux_source_first = 1'd0; -reg main_maccore_ethphy_mux_source_last = 1'd0; -reg [7:0] main_maccore_ethphy_mux_source_payload_data = 8'd0; -reg main_maccore_ethphy_mux_source_payload_error = 1'd0; -reg main_maccore_ethphy_mux_source_payload_last_be = 1'd0; -wire main_maccore_ethphy_mux_source_ready; -reg main_maccore_ethphy_mux_source_valid = 1'd0; -wire main_maccore_ethphy_o; -wire main_maccore_ethphy_oe; -reg [7:0] main_maccore_ethphy_pads_d_rx_data = 8'd0; -reg main_maccore_ethphy_pads_d_rx_dv = 1'd0; -reg main_maccore_ethphy_r = 1'd0; -wire main_maccore_ethphy_reset0; -wire main_maccore_ethphy_reset1; -reg main_maccore_ethphy_reset_re = 1'd0; -reg main_maccore_ethphy_reset_storage = 1'd0; -wire main_maccore_ethphy_sink_sink_first; -wire main_maccore_ethphy_sink_sink_last; -wire [7:0] main_maccore_ethphy_sink_sink_payload_data; -wire main_maccore_ethphy_sink_sink_payload_error; -wire main_maccore_ethphy_sink_sink_payload_last_be; -wire main_maccore_ethphy_sink_sink_ready; -wire main_maccore_ethphy_sink_sink_valid; -wire main_maccore_ethphy_source_source_first; -wire main_maccore_ethphy_source_source_last; -wire [7:0] main_maccore_ethphy_source_source_payload_data; -wire main_maccore_ethphy_source_source_payload_error; -wire main_maccore_ethphy_source_source_payload_last_be; -wire main_maccore_ethphy_source_source_ready; -wire main_maccore_ethphy_source_source_valid; -reg [23:0] main_maccore_ethphy_sys_counter = 24'd0; -reg main_maccore_ethphy_sys_counter_ce = 1'd0; -reg main_maccore_ethphy_sys_counter_reset = 1'd0; -wire main_maccore_ethphy_sys_tick; -reg main_maccore_ethphy_toggle_i = 1'd0; -wire main_maccore_ethphy_toggle_o; -reg main_maccore_ethphy_toggle_o_r = 1'd0; -reg main_maccore_ethphy_update_mode = 1'd0; -wire main_maccore_ethphy_w; -reg main_maccore_int_rst = 1'd1; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -wire main_maccore_maccore_cpu_rst; -reg main_maccore_maccore_reset_re = 1'd0; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_scratch_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_soc_rst = 1'd0; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -wire main_pulsesynchronizer0_i; -wire main_pulsesynchronizer0_o; -reg main_pulsesynchronizer0_toggle_i = 1'd0; -wire main_pulsesynchronizer0_toggle_o; -reg main_pulsesynchronizer0_toggle_o_r = 1'd0; -wire main_pulsesynchronizer1_i; -wire main_pulsesynchronizer1_o; -reg main_pulsesynchronizer1_toggle_i = 1'd0; -wire main_pulsesynchronizer1_toggle_o; -reg main_pulsesynchronizer1_toggle_o_r = 1'd0; -reg [31:0] main_rd_data = 32'd0; -reg main_re = 1'd0; -reg main_read = 1'd0; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) -reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_valid; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire main_rx_cdc_cdc_wrport_we; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_valid; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_valid; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -wire main_rx_converter_converter_source_ready; -wire main_rx_converter_converter_source_valid; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_valid; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_valid; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -wire main_rx_last_be_source_payload_error; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_valid; -wire main_rx_padding_sink_first; -wire main_rx_padding_sink_last; -wire [7:0] main_rx_padding_sink_payload_data; -wire main_rx_padding_sink_payload_error; -wire main_rx_padding_sink_payload_last_be; -wire main_rx_padding_sink_ready; -wire main_rx_padding_sink_valid; -wire main_rx_padding_source_first; -wire main_rx_padding_source_last; -wire [7:0] main_rx_padding_source_payload_data; -wire main_rx_padding_source_payload_error; -wire main_rx_padding_source_payload_last_be; -wire main_rx_padding_source_ready; -wire main_rx_padding_source_valid; -reg main_rx_preamble_error = 1'd0; -reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; -wire main_rx_preamble_sink_first; -wire main_rx_preamble_sink_last; -wire [7:0] main_rx_preamble_sink_payload_data; -wire main_rx_preamble_sink_payload_error; -wire main_rx_preamble_sink_payload_last_be; -reg main_rx_preamble_sink_ready = 1'd0; -wire main_rx_preamble_sink_valid; -reg main_rx_preamble_source_first = 1'd0; -reg main_rx_preamble_source_last = 1'd0; -wire [7:0] main_rx_preamble_source_payload_data; -reg main_rx_preamble_source_payload_error = 1'd0; -wire main_rx_preamble_source_payload_last_be; -wire main_rx_preamble_source_ready; -reg main_rx_preamble_source_valid = 1'd0; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_error; -wire [3:0] main_sink_payload_last_be; -wire main_sink_ready; -wire main_sink_sink_first; -wire main_sink_sink_last; -wire [31:0] main_sink_sink_payload_data; -wire [3:0] main_sink_sink_payload_error; -wire [3:0] main_sink_sink_payload_last_be; -wire main_sink_sink_ready; -wire main_sink_sink_valid; -wire main_sink_valid; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -reg main_slot = 1'd0; -reg main_slot_liteethmacsramwriter_next_value = 1'd0; -reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_error; -wire [3:0] main_source_payload_last_be; -wire main_source_ready; -wire main_source_source_first; -wire main_source_source_last; -wire [31:0] main_source_source_payload_data; -wire [3:0] main_source_source_payload_error; -wire [3:0] main_source_source_payload_last_be; -wire main_source_source_ready; -wire main_source_source_valid; -wire main_source_valid; -wire [8:0] main_sram0_adr; -reg main_sram0_adr_burst = 1'd0; -wire [31:0] main_sram0_dat_r; -wire main_sram0_sink_valid; -reg main_sram100_storage = 1'd0; -reg main_sram101_re = 1'd0; -reg [10:0] main_sram102_storage = 11'd0; -reg main_sram103_re = 1'd0; -wire main_sram104_irq; -wire main_sram105_status; -reg main_sram106_pending = 1'd0; -reg main_sram107_trigger = 1'd0; -reg main_sram108_clear = 1'd0; -wire main_sram109_event0; -wire [10:0] main_sram10_status; -reg main_sram110_status = 1'd0; -wire main_sram111_we; -reg main_sram112_re = 1'd0; -wire main_sram113_event0; -reg main_sram114_status = 1'd0; -wire main_sram115_we; -reg main_sram116_re = 1'd0; -reg main_sram117_r = 1'd0; -wire main_sram118_event0; -reg main_sram119_storage = 1'd0; -wire main_sram11_we; -reg main_sram120_re = 1'd0; -reg [10:0] main_sram122_length = 11'd0; -reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; -reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; -wire main_sram123_sink_valid; -wire main_sram124_sink_ready; -reg main_sram125_sink_first = 1'd0; -reg main_sram126_sink_last = 1'd0; -wire main_sram127_sink_payload_slot; -wire [10:0] main_sram128_sink_payload_length; -wire main_sram129_source_valid; -reg main_sram12_re = 1'd0; -reg main_sram130_source_ready = 1'd0; -wire main_sram131_source_first; -wire main_sram132_source_last; -wire main_sram133_source_payload_slot; -wire [10:0] main_sram134_source_payload_length; -wire main_sram135_we; -wire main_sram136_writable; -wire main_sram137_re; -wire main_sram138_readable; -wire [13:0] main_sram139_din; -reg [31:0] main_sram13_status = 32'd0; -reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; -reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; -wire [13:0] main_sram140_dout; -reg [1:0] main_sram141_level = 2'd0; -reg main_sram142_replace = 1'd0; -reg main_sram143_produce = 1'd0; -reg main_sram144_consume = 1'd0; -reg main_sram145_adr = 1'd0; -wire [13:0] main_sram146_dat_r; -wire main_sram147_we; -wire [13:0] main_sram148_dat_w; -wire main_sram149_do_read; -wire main_sram14_we; -wire main_sram150_adr; -wire [13:0] main_sram151_dat_r; -wire main_sram152_fifo_in_payload_slot; -wire [10:0] main_sram153_fifo_in_payload_length; -wire main_sram154_fifo_in_first; -wire main_sram155_fifo_in_last; -wire main_sram156_fifo_out_payload_slot; -wire [10:0] main_sram157_fifo_out_payload_length; -wire main_sram158_fifo_out_first; -wire main_sram159_fifo_out_last; -reg main_sram15_re = 1'd0; -wire [8:0] main_sram161_adr; -wire [31:0] main_sram162_dat_r; -wire main_sram163_re; -wire [8:0] main_sram164_adr; -wire [31:0] main_sram165_dat_r; -wire main_sram166_re; -wire main_sram167_irq; -wire main_sram16_irq; -wire main_sram17_status; -wire main_sram18_pending; -wire main_sram19_trigger; -wire [8:0] main_sram1_adr; -reg main_sram1_adr_burst = 1'd0; -wire [31:0] main_sram1_dat_r; -reg main_sram1_sink_ready = 1'd1; -reg main_sram20_clear = 1'd0; -wire main_sram21_available; -reg main_sram22_status = 1'd0; -wire main_sram23_we; -reg main_sram24_re = 1'd0; -wire main_sram25_available; -reg main_sram26_status = 1'd0; -wire main_sram27_we; -reg main_sram28_re = 1'd0; -reg main_sram29_r = 1'd0; -wire [8:0] main_sram2_adr; -reg main_sram2_adr_burst = 1'd0; -wire [31:0] main_sram2_dat_r; -wire [31:0] main_sram2_dat_w; -wire main_sram2_sink_first; -reg [3:0] main_sram2_we = 4'd0; -wire main_sram30_available; -reg main_sram31_storage = 1'd0; -reg main_sram32_re = 1'd0; -reg [10:0] main_sram35_length = 11'd0; -reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; -reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; -reg main_sram37_sink_valid = 1'd0; -wire main_sram38_sink_ready; -reg main_sram39_sink_first = 1'd0; -wire [8:0] main_sram3_adr; -reg main_sram3_adr_burst = 1'd0; -wire [31:0] main_sram3_dat_r; -wire [31:0] main_sram3_dat_w; -wire main_sram3_sink_last; -reg [3:0] main_sram3_we = 4'd0; -reg main_sram40_sink_last = 1'd0; -reg main_sram41_sink_payload_slot = 1'd0; -reg [10:0] main_sram42_sink_payload_length = 11'd0; -wire main_sram43_source_valid; -wire main_sram44_source_ready; -wire main_sram45_source_first; -wire main_sram46_source_last; -wire main_sram47_source_payload_slot; -wire [10:0] main_sram48_source_payload_length; -wire main_sram49_we; -wire [31:0] main_sram4_sink_payload_data; -wire main_sram50_writable; -wire main_sram51_re; -wire main_sram52_readable; -wire [13:0] main_sram53_din; -wire [13:0] main_sram54_dout; -reg [1:0] main_sram55_level = 2'd0; -reg main_sram56_replace = 1'd0; -reg main_sram57_produce = 1'd0; -reg main_sram58_consume = 1'd0; -reg main_sram59_adr = 1'd0; -wire [3:0] main_sram5_sink_payload_last_be; -wire [13:0] main_sram60_dat_r; -wire main_sram61_we; -wire [13:0] main_sram62_dat_w; -wire main_sram63_do_read; -wire main_sram64_adr; -wire [13:0] main_sram65_dat_r; -wire main_sram66_fifo_in_payload_slot; -wire [10:0] main_sram67_fifo_in_payload_length; -wire main_sram68_fifo_in_first; -wire main_sram69_fifo_in_last; -wire [3:0] main_sram6_sink_payload_error; -wire main_sram70_fifo_out_payload_slot; -wire [10:0] main_sram71_fifo_out_payload_length; -wire main_sram72_fifo_out_first; -wire main_sram73_fifo_out_last; -reg [8:0] main_sram75_adr = 9'd0; -wire [31:0] main_sram76_dat_r; -reg main_sram77_we = 1'd0; -reg [31:0] main_sram78_dat_w = 32'd0; -reg [8:0] main_sram79_adr = 9'd0; -wire main_sram7_status; -wire [31:0] main_sram80_dat_r; -reg main_sram81_we = 1'd0; -reg [31:0] main_sram82_dat_w = 32'd0; -reg main_sram83_source_valid = 1'd0; -wire main_sram84_source_ready; -reg main_sram85_source_first = 1'd0; -reg main_sram86_source_last = 1'd0; -wire [31:0] main_sram87_source_payload_data; -reg [3:0] main_sram88_source_payload_last_be = 4'd0; -reg [3:0] main_sram89_source_payload_error = 4'd0; -wire main_sram8_we; -wire main_sram94_status; -wire main_sram95_we; -reg main_sram96_re = 1'd0; -wire [1:0] main_sram97_status; -wire main_sram98_we; -reg main_sram99_re = 1'd0; -reg main_sram9_re = 1'd0; -wire main_start_r; -reg main_start_re = 1'd0; -reg main_start_w = 1'd0; -reg main_start_we = 1'd0; -reg main_status = 1'd1; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) -reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_valid; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire main_tx_cdc_cdc_wrport_we; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_valid; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_error; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_valid; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_valid; -wire main_tx_crc_be; -reg main_tx_crc_ce = 1'd0; -reg [1:0] main_tx_crc_cnt = 2'd3; -wire main_tx_crc_cnt_done; -reg [31:0] main_tx_crc_crc_next = 32'd0; -reg [31:0] main_tx_crc_crc_packet = 32'd0; -reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; -reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; -wire [31:0] main_tx_crc_crc_prev; -wire [7:0] main_tx_crc_data0; -wire [7:0] main_tx_crc_data1; -reg main_tx_crc_error = 1'd0; -reg main_tx_crc_is_ongoing0 = 1'd0; -reg main_tx_crc_is_ongoing1 = 1'd0; -reg main_tx_crc_last_be = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; -reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; -wire main_tx_crc_pipe_valid_sink_first; -wire main_tx_crc_pipe_valid_sink_last; -wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; -wire main_tx_crc_pipe_valid_sink_payload_error; -wire main_tx_crc_pipe_valid_sink_payload_last_be; -wire main_tx_crc_pipe_valid_sink_ready; -wire main_tx_crc_pipe_valid_sink_valid; -reg main_tx_crc_pipe_valid_source_first = 1'd0; -reg main_tx_crc_pipe_valid_source_last = 1'd0; -reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; -reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; -reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; -wire main_tx_crc_pipe_valid_source_ready; -reg main_tx_crc_pipe_valid_source_valid = 1'd0; -reg [31:0] main_tx_crc_reg = 32'd4294967295; -reg main_tx_crc_reset = 1'd0; -wire main_tx_crc_sink_first; -wire main_tx_crc_sink_last; -wire [7:0] main_tx_crc_sink_payload_data; -wire main_tx_crc_sink_payload_error; -wire main_tx_crc_sink_payload_last_be; -reg main_tx_crc_sink_ready = 1'd0; -wire main_tx_crc_sink_sink_first; -wire main_tx_crc_sink_sink_last; -wire [7:0] main_tx_crc_sink_sink_payload_data; -wire main_tx_crc_sink_sink_payload_error; -wire main_tx_crc_sink_sink_payload_last_be; -wire main_tx_crc_sink_sink_ready; -wire main_tx_crc_sink_sink_valid; -wire main_tx_crc_sink_valid; -reg main_tx_crc_source_first = 1'd0; -reg main_tx_crc_source_last = 1'd0; -reg [7:0] main_tx_crc_source_payload_data = 8'd0; -reg main_tx_crc_source_payload_error = 1'd0; -reg main_tx_crc_source_payload_last_be = 1'd0; -wire main_tx_crc_source_ready; -wire main_tx_crc_source_source_first; -wire main_tx_crc_source_source_last; -wire [7:0] main_tx_crc_source_source_payload_data; -wire main_tx_crc_source_source_payload_error; -wire main_tx_crc_source_source_payload_last_be; -wire main_tx_crc_source_source_ready; -wire main_tx_crc_source_source_valid; -reg main_tx_crc_source_valid = 1'd0; -reg [31:0] main_tx_crc_value = 32'd0; -reg [3:0] main_tx_gap_counter = 4'd0; -reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; -reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; -wire main_tx_gap_sink_first; -wire main_tx_gap_sink_last; -wire [7:0] main_tx_gap_sink_payload_data; -wire main_tx_gap_sink_payload_error; -wire main_tx_gap_sink_payload_last_be; -reg main_tx_gap_sink_ready = 1'd0; -wire main_tx_gap_sink_valid; -reg main_tx_gap_source_first = 1'd0; -reg main_tx_gap_source_last = 1'd0; -reg [7:0] main_tx_gap_source_payload_data = 8'd0; -reg main_tx_gap_source_payload_error = 1'd0; -reg main_tx_gap_source_payload_last_be = 1'd0; -wire main_tx_gap_source_ready; -reg main_tx_gap_source_valid = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_error; -wire main_tx_last_be_sink_payload_last_be; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_valid = 1'd0; -reg [15:0] main_tx_padding_counter = 16'd0; -reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; -reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; -wire main_tx_padding_counter_done; -wire main_tx_padding_sink_first; -wire main_tx_padding_sink_last; -wire [7:0] main_tx_padding_sink_payload_data; -wire main_tx_padding_sink_payload_error; -wire main_tx_padding_sink_payload_last_be; -reg main_tx_padding_sink_ready = 1'd0; -wire main_tx_padding_sink_valid; -reg main_tx_padding_source_first = 1'd0; -reg main_tx_padding_source_last = 1'd0; -reg [7:0] main_tx_padding_source_payload_data = 8'd0; -reg main_tx_padding_source_payload_error = 1'd0; -reg main_tx_padding_source_payload_last_be = 1'd0; -wire main_tx_padding_source_ready; -reg main_tx_padding_source_valid = 1'd0; -reg [2:0] main_tx_preamble_count = 3'd0; -reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; -reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; -reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; -wire main_tx_preamble_sink_first; -wire main_tx_preamble_sink_last; -wire [7:0] main_tx_preamble_sink_payload_data; -wire main_tx_preamble_sink_payload_error; -wire main_tx_preamble_sink_payload_last_be; -reg main_tx_preamble_sink_ready = 1'd0; -wire main_tx_preamble_sink_valid; -reg main_tx_preamble_source_first = 1'd0; -reg main_tx_preamble_source_last = 1'd0; -reg [7:0] main_tx_preamble_source_payload_data = 8'd0; -reg main_tx_preamble_source_payload_error = 1'd0; -wire main_tx_preamble_source_payload_last_be; -wire main_tx_preamble_source_ready; -reg main_tx_preamble_source_valid = 1'd0; -wire main_wb_bus_ack; -wire [29:0] main_wb_bus_adr; -wire [1:0] main_wb_bus_bte; -wire [2:0] main_wb_bus_cti; -wire main_wb_bus_cyc; -wire [31:0] main_wb_bus_dat_r; -wire [31:0] main_wb_bus_dat_w; -wire main_wb_bus_err; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_stb; -wire main_wb_bus_we; -wire main_we; -wire [31:0] main_wr_data; -reg main_write = 1'd0; -wire por_clk; -(* dont_touch = "true" *) -wire sys_clk; -wire sys_rst; +reg [5:0] xilinxmultiregimpl71 = 6'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ -assign main_wb_bus_adr = wishbone_adr; -assign main_wb_bus_dat_w = wishbone_dat_w; -assign wishbone_dat_r = main_wb_bus_dat_r; -assign main_wb_bus_sel = wishbone_sel; -assign main_wb_bus_cyc = wishbone_cyc; -assign main_wb_bus_stb = wishbone_stb; -assign wishbone_ack = main_wb_bus_ack; -assign main_wb_bus_we = wishbone_we; -assign main_wb_bus_cti = wishbone_cti; -assign main_wb_bus_bte = wishbone_bte; -assign wishbone_err = main_wb_bus_err; -assign interrupt = main_sram167_irq; -assign main_maccore_maccore_bus_error = builder_error; -assign builder_shared_adr = builder_self0; -assign builder_shared_dat_w = builder_self1; -assign builder_shared_sel = builder_self2; -assign builder_shared_cyc = builder_self3; -assign builder_shared_stb = builder_self4; -assign builder_shared_we = builder_self5; -assign builder_shared_cti = builder_self6; -assign builder_shared_bte = builder_self7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; +assign wb_bus_adr = wishbone_adr; +assign wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wishbone_sel; +assign wb_bus_cyc = wishbone_cyc; +assign wb_bus_stb = wishbone_stb; +assign wishbone_ack = wb_bus_ack; +assign wb_bus_we = wishbone_we; +assign wb_bus_cti = wishbone_cti; +assign wb_bus_bte = wishbone_bte; +assign wishbone_err = wb_bus_err; +assign interrupt = wishbone_interface_ev_irq; +assign maccore_maccore_bus_error = error; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign wb_bus_dat_r = shared_dat_r; +assign wb_bus_ack = (shared_ack & (grant == 1'd0)); +assign wb_bus_err = (shared_err & (grant == 1'd0)); +assign request = {wb_bus_cyc}; +assign grant = 1'd0; always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); + slave_sel <= 3'd0; + slave_sel[0] <= (shared_adr[29:10] == 5'd16); + slave_sel[1] <= (shared_adr[29:10] == 5'd17); + slave_sel[2] <= (shared_adr[29:14] == 1'd0); end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_interface0_adr = builder_shared_adr; -assign builder_interface0_dat_w = builder_shared_dat_w; -assign builder_interface0_sel = builder_shared_sel; -assign builder_interface0_stb = builder_shared_stb; -assign builder_interface0_we = builder_shared_we; -assign builder_interface0_cti = builder_shared_cti; -assign builder_interface0_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_interface0_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +assign wishbone_interface_bus_rx_adr = shared_adr; +assign wishbone_interface_bus_rx_dat_w = shared_dat_w; +assign wishbone_interface_bus_rx_sel = shared_sel; +assign wishbone_interface_bus_rx_stb = shared_stb; +assign wishbone_interface_bus_rx_we = shared_we; +assign wishbone_interface_bus_rx_cti = shared_cti; +assign wishbone_interface_bus_rx_bte = shared_bte; +assign wishbone_interface_bus_tx_adr = shared_adr; +assign wishbone_interface_bus_tx_dat_w = shared_dat_w; +assign wishbone_interface_bus_tx_sel = shared_sel; +assign wishbone_interface_bus_tx_stb = shared_stb; +assign wishbone_interface_bus_tx_we = shared_we; +assign wishbone_interface_bus_tx_cti = shared_cti; +assign wishbone_interface_bus_tx_bte = shared_bte; +assign interface0_adr = shared_adr; +assign interface0_dat_w = shared_dat_w; +assign interface0_sel = shared_sel; +assign interface0_stb = shared_stb; +assign interface0_we = shared_we; +assign interface0_cti = shared_cti; +assign interface0_bte = shared_bte; +assign wishbone_interface_bus_rx_cyc = (shared_cyc & slave_sel[0]); +assign wishbone_interface_bus_tx_cyc = (shared_cyc & slave_sel[1]); +assign interface0_cyc = (shared_cyc & slave_sel[2]); +assign shared_err = ((wishbone_interface_bus_rx_err | wishbone_interface_bus_tx_err) | interface0_err); +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); always @(*) begin - builder_error <= 1'd0; - builder_shared_ack <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_interface0_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= ((wishbone_interface_bus_rx_ack | wishbone_interface_bus_tx_ack) | interface0_ack); + shared_dat_r <= ((({32{slave_sel_r[0]}} & wishbone_interface_bus_rx_dat_r) | ({32{slave_sel_r[1]}} & wishbone_interface_bus_tx_dat_r)) | ({32{slave_sel_r[2]}} & interface0_dat_r)); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; end end -assign builder_done = (builder_count == 1'd0); -assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign done = (count == 1'd0); +assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; -assign sys_rst = main_maccore_int_rst; -assign main_maccore_ethphy_mode_status = main_maccore_ethphy_mode0; -assign main_maccore_ethphy_eth_tick = (main_maccore_ethphy_eth_counter == 1'd0); -assign main_maccore_ethphy_i = main_maccore_ethphy_eth_tick; -assign main_maccore_ethphy_sys_tick = main_maccore_ethphy_o; -assign main_maccore_ethphy_o = (main_maccore_ethphy_toggle_o ^ main_maccore_ethphy_toggle_o_r); +assign sys_rst = maccore_int_rst; +assign maccore_ethphy_mode_status = maccore_ethphy_mode0; +assign maccore_ethphy_eth_tick = (maccore_ethphy_eth_counter == 1'd0); +assign maccore_ethphy_i = maccore_ethphy_eth_tick; +assign maccore_ethphy_sys_tick = maccore_ethphy_o; +assign maccore_ethphy_o = (maccore_ethphy_toggle_o ^ maccore_ethphy_toggle_o_r); always @(*) begin - builder_liteethphygmiimii_next_state <= 2'd0; - main_maccore_ethphy_mode1 <= 1'd0; - main_maccore_ethphy_sys_counter_ce <= 1'd0; - main_maccore_ethphy_sys_counter_reset <= 1'd0; - main_maccore_ethphy_update_mode <= 1'd0; - builder_liteethphygmiimii_next_state <= builder_liteethphygmiimii_state; - case (builder_liteethphygmiimii_state) + liteethphygmiimii_next_state <= 2'd0; + maccore_ethphy_mode1 <= 1'd0; + maccore_ethphy_sys_counter_ce <= 1'd0; + maccore_ethphy_sys_counter_reset <= 1'd0; + maccore_ethphy_update_mode <= 1'd0; + liteethphygmiimii_next_state <= liteethphygmiimii_state; + case (liteethphygmiimii_state) 1'd1: begin - main_maccore_ethphy_sys_counter_ce <= 1'd1; - if (main_maccore_ethphy_sys_tick) begin - builder_liteethphygmiimii_next_state <= 2'd2; + maccore_ethphy_sys_counter_ce <= 1'd1; + if (maccore_ethphy_sys_tick) begin + liteethphygmiimii_next_state <= 2'd2; end end 2'd2: begin - main_maccore_ethphy_update_mode <= 1'd1; - if ((main_maccore_ethphy_sys_counter > 10'd860)) begin - main_maccore_ethphy_mode1 <= 1'd1; + maccore_ethphy_update_mode <= 1'd1; + if ((maccore_ethphy_sys_counter > 10'd860)) begin + maccore_ethphy_mode1 <= 1'd1; end else begin - main_maccore_ethphy_mode1 <= 1'd0; + maccore_ethphy_mode1 <= 1'd0; end - builder_liteethphygmiimii_next_state <= 1'd0; + liteethphygmiimii_next_state <= 1'd0; end default: begin - main_maccore_ethphy_sys_counter_reset <= 1'd1; - if (main_maccore_ethphy_sys_tick) begin - builder_liteethphygmiimii_next_state <= 1'd1; + maccore_ethphy_sys_counter_reset <= 1'd1; + if (maccore_ethphy_sys_tick) begin + liteethphygmiimii_next_state <= 1'd1; end end endcase end always @(*) begin - main_maccore_ethphy_eth_tx_clk <= 1'd0; - if ((main_maccore_ethphy_mode0 == 1'd1)) begin - main_maccore_ethphy_eth_tx_clk <= gmii_clocks_tx; + maccore_ethphy_eth_tx_clk <= 1'd0; + if ((maccore_ethphy_mode0 == 1'd1)) begin + maccore_ethphy_eth_tx_clk <= gmii_clocks_tx; end else begin - main_maccore_ethphy_eth_tx_clk <= gmii_clocks_rx; + maccore_ethphy_eth_tx_clk <= gmii_clocks_rx; end end -assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1); -assign gmii_rst_n = (~main_maccore_ethphy_reset0); -assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256); -assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done); -assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done); -assign main_maccore_ethphy_demux_sel = (main_maccore_ethphy_mode0 == 1'd1); -assign main_maccore_ethphy_demux_sink_valid = main_maccore_ethphy_sink_sink_valid; -assign main_maccore_ethphy_sink_sink_ready = main_maccore_ethphy_demux_sink_ready; -assign main_maccore_ethphy_demux_sink_first = main_maccore_ethphy_sink_sink_first; -assign main_maccore_ethphy_demux_sink_last = main_maccore_ethphy_sink_sink_last; -assign main_maccore_ethphy_demux_sink_payload_data = main_maccore_ethphy_sink_sink_payload_data; -assign main_maccore_ethphy_demux_sink_payload_last_be = main_maccore_ethphy_sink_sink_payload_last_be; -assign main_maccore_ethphy_demux_sink_payload_error = main_maccore_ethphy_sink_sink_payload_error; -assign main_maccore_ethphy_gmii_tx_sink_valid = main_maccore_ethphy_demux_endpoint0_source_valid; -assign main_maccore_ethphy_demux_endpoint0_source_ready = main_maccore_ethphy_gmii_tx_sink_ready; -assign main_maccore_ethphy_gmii_tx_sink_first = main_maccore_ethphy_demux_endpoint0_source_first; -assign main_maccore_ethphy_gmii_tx_sink_last = main_maccore_ethphy_demux_endpoint0_source_last; -assign main_maccore_ethphy_gmii_tx_sink_payload_data = main_maccore_ethphy_demux_endpoint0_source_payload_data; -assign main_maccore_ethphy_gmii_tx_sink_payload_last_be = main_maccore_ethphy_demux_endpoint0_source_payload_last_be; -assign main_maccore_ethphy_gmii_tx_sink_payload_error = main_maccore_ethphy_demux_endpoint0_source_payload_error; -assign main_maccore_ethphy_mii_tx_sink_valid = main_maccore_ethphy_demux_endpoint1_source_valid; -assign main_maccore_ethphy_demux_endpoint1_source_ready = main_maccore_ethphy_mii_tx_sink_ready; -assign main_maccore_ethphy_mii_tx_sink_first = main_maccore_ethphy_demux_endpoint1_source_first; -assign main_maccore_ethphy_mii_tx_sink_last = main_maccore_ethphy_demux_endpoint1_source_last; -assign main_maccore_ethphy_mii_tx_sink_payload_data = main_maccore_ethphy_demux_endpoint1_source_payload_data; -assign main_maccore_ethphy_mii_tx_sink_payload_last_be = main_maccore_ethphy_demux_endpoint1_source_payload_last_be; -assign main_maccore_ethphy_mii_tx_sink_payload_error = main_maccore_ethphy_demux_endpoint1_source_payload_error; +assign maccore_ethphy_reset0 = (maccore_ethphy_reset_storage | maccore_ethphy_reset1); +assign gmii_rst_n = (~maccore_ethphy_reset0); +assign maccore_ethphy_counter_done = (maccore_ethphy_counter == 9'd256); +assign maccore_ethphy_counter_ce = (~maccore_ethphy_counter_done); +assign maccore_ethphy_reset1 = (~maccore_ethphy_counter_done); +assign maccore_ethphy_demux_sel = (maccore_ethphy_mode0 == 1'd1); +assign maccore_ethphy_demux_sink_valid = maccore_ethphy_sink_sink_valid; +assign maccore_ethphy_sink_sink_ready = maccore_ethphy_demux_sink_ready; +assign maccore_ethphy_demux_sink_first = maccore_ethphy_sink_sink_first; +assign maccore_ethphy_demux_sink_last = maccore_ethphy_sink_sink_last; +assign maccore_ethphy_demux_sink_payload_data = maccore_ethphy_sink_sink_payload_data; +assign maccore_ethphy_demux_sink_payload_last_be = maccore_ethphy_sink_sink_payload_last_be; +assign maccore_ethphy_demux_sink_payload_error = maccore_ethphy_sink_sink_payload_error; +assign maccore_ethphy_gmii_tx_sink_valid = maccore_ethphy_demux_endpoint0_source_valid; +assign maccore_ethphy_demux_endpoint0_source_ready = maccore_ethphy_gmii_tx_sink_ready; +assign maccore_ethphy_gmii_tx_sink_first = maccore_ethphy_demux_endpoint0_source_first; +assign maccore_ethphy_gmii_tx_sink_last = maccore_ethphy_demux_endpoint0_source_last; +assign maccore_ethphy_gmii_tx_sink_payload_data = maccore_ethphy_demux_endpoint0_source_payload_data; +assign maccore_ethphy_gmii_tx_sink_payload_last_be = maccore_ethphy_demux_endpoint0_source_payload_last_be; +assign maccore_ethphy_gmii_tx_sink_payload_error = maccore_ethphy_demux_endpoint0_source_payload_error; +assign maccore_ethphy_mii_tx_sink_valid = maccore_ethphy_demux_endpoint1_source_valid; +assign maccore_ethphy_demux_endpoint1_source_ready = maccore_ethphy_mii_tx_sink_ready; +assign maccore_ethphy_mii_tx_sink_first = maccore_ethphy_demux_endpoint1_source_first; +assign maccore_ethphy_mii_tx_sink_last = maccore_ethphy_demux_endpoint1_source_last; +assign maccore_ethphy_mii_tx_sink_payload_data = maccore_ethphy_demux_endpoint1_source_payload_data; +assign maccore_ethphy_mii_tx_sink_payload_last_be = maccore_ethphy_demux_endpoint1_source_payload_last_be; +assign maccore_ethphy_mii_tx_sink_payload_error = maccore_ethphy_demux_endpoint1_source_payload_error; assign gmii_tx_er = 1'd0; -assign main_maccore_ethphy_mii_tx_converter_sink_valid = main_maccore_ethphy_mii_tx_sink_valid; -assign main_maccore_ethphy_mii_tx_converter_sink_payload_data = main_maccore_ethphy_mii_tx_sink_payload_data; -assign main_maccore_ethphy_mii_tx_sink_ready = main_maccore_ethphy_mii_tx_converter_sink_ready; -assign main_maccore_ethphy_mii_tx_source_source_ready = 1'd1; -assign main_maccore_ethphy_mii_tx_source_source_valid = main_maccore_ethphy_mii_tx_converter_source_valid; -assign main_maccore_ethphy_mii_tx_converter_source_ready = main_maccore_ethphy_mii_tx_source_source_ready; -assign main_maccore_ethphy_mii_tx_source_source_first = main_maccore_ethphy_mii_tx_converter_source_first; -assign main_maccore_ethphy_mii_tx_source_source_last = main_maccore_ethphy_mii_tx_converter_source_last; -assign main_maccore_ethphy_mii_tx_source_source_payload_data = main_maccore_ethphy_mii_tx_converter_source_payload_data; -assign main_maccore_ethphy_mii_tx_converter_first = (main_maccore_ethphy_mii_tx_converter_mux == 1'd0); -assign main_maccore_ethphy_mii_tx_converter_last = (main_maccore_ethphy_mii_tx_converter_mux == 1'd1); -assign main_maccore_ethphy_mii_tx_converter_source_valid = main_maccore_ethphy_mii_tx_converter_sink_valid; -assign main_maccore_ethphy_mii_tx_converter_source_first = (main_maccore_ethphy_mii_tx_converter_sink_first & main_maccore_ethphy_mii_tx_converter_first); -assign main_maccore_ethphy_mii_tx_converter_source_last = (main_maccore_ethphy_mii_tx_converter_sink_last & main_maccore_ethphy_mii_tx_converter_last); -assign main_maccore_ethphy_mii_tx_converter_sink_ready = (main_maccore_ethphy_mii_tx_converter_last & main_maccore_ethphy_mii_tx_converter_source_ready); +assign maccore_ethphy_mii_tx_converter_sink_valid = maccore_ethphy_mii_tx_sink_valid; +assign maccore_ethphy_mii_tx_converter_sink_payload_data = maccore_ethphy_mii_tx_sink_payload_data; +assign maccore_ethphy_mii_tx_sink_ready = maccore_ethphy_mii_tx_converter_sink_ready; +assign maccore_ethphy_mii_tx_source_source_ready = 1'd1; +assign maccore_ethphy_mii_tx_source_source_valid = maccore_ethphy_mii_tx_converter_source_valid; +assign maccore_ethphy_mii_tx_converter_source_ready = maccore_ethphy_mii_tx_source_source_ready; +assign maccore_ethphy_mii_tx_source_source_first = maccore_ethphy_mii_tx_converter_source_first; +assign maccore_ethphy_mii_tx_source_source_last = maccore_ethphy_mii_tx_converter_source_last; +assign maccore_ethphy_mii_tx_source_source_payload_data = maccore_ethphy_mii_tx_converter_source_payload_data; +assign maccore_ethphy_mii_tx_converter_first = (maccore_ethphy_mii_tx_converter_mux == 1'd0); +assign maccore_ethphy_mii_tx_converter_last = (maccore_ethphy_mii_tx_converter_mux == 1'd1); +assign maccore_ethphy_mii_tx_converter_source_valid = maccore_ethphy_mii_tx_converter_sink_valid; +assign maccore_ethphy_mii_tx_converter_source_first = (maccore_ethphy_mii_tx_converter_sink_first & maccore_ethphy_mii_tx_converter_first); +assign maccore_ethphy_mii_tx_converter_source_last = (maccore_ethphy_mii_tx_converter_sink_last & maccore_ethphy_mii_tx_converter_last); +assign maccore_ethphy_mii_tx_converter_sink_ready = (maccore_ethphy_mii_tx_converter_last & maccore_ethphy_mii_tx_converter_source_ready); always @(*) begin - main_maccore_ethphy_mii_tx_converter_source_payload_data <= 4'd0; - case (main_maccore_ethphy_mii_tx_converter_mux) + maccore_ethphy_mii_tx_converter_source_payload_data <= 4'd0; + case (maccore_ethphy_mii_tx_converter_mux) 1'd0: begin - main_maccore_ethphy_mii_tx_converter_source_payload_data <= main_maccore_ethphy_mii_tx_converter_sink_payload_data[3:0]; + maccore_ethphy_mii_tx_converter_source_payload_data <= maccore_ethphy_mii_tx_converter_sink_payload_data[3:0]; end default: begin - main_maccore_ethphy_mii_tx_converter_source_payload_data <= main_maccore_ethphy_mii_tx_converter_sink_payload_data[7:4]; + maccore_ethphy_mii_tx_converter_source_payload_data <= maccore_ethphy_mii_tx_converter_sink_payload_data[7:4]; end endcase end -assign main_maccore_ethphy_mii_tx_converter_source_payload_valid_token_count = main_maccore_ethphy_mii_tx_converter_last; +assign maccore_ethphy_mii_tx_converter_source_payload_valid_token_count = maccore_ethphy_mii_tx_converter_last; always @(*) begin - main_maccore_ethphy_demux_endpoint0_source_first <= 1'd0; - main_maccore_ethphy_demux_endpoint0_source_last <= 1'd0; - main_maccore_ethphy_demux_endpoint0_source_payload_data <= 8'd0; - main_maccore_ethphy_demux_endpoint0_source_payload_error <= 1'd0; - main_maccore_ethphy_demux_endpoint0_source_payload_last_be <= 1'd0; - main_maccore_ethphy_demux_endpoint0_source_valid <= 1'd0; - main_maccore_ethphy_demux_endpoint1_source_first <= 1'd0; - main_maccore_ethphy_demux_endpoint1_source_last <= 1'd0; - main_maccore_ethphy_demux_endpoint1_source_payload_data <= 8'd0; - main_maccore_ethphy_demux_endpoint1_source_payload_error <= 1'd0; - main_maccore_ethphy_demux_endpoint1_source_payload_last_be <= 1'd0; - main_maccore_ethphy_demux_endpoint1_source_valid <= 1'd0; - main_maccore_ethphy_demux_sink_ready <= 1'd0; - case (main_maccore_ethphy_demux_sel) + maccore_ethphy_demux_endpoint0_source_first <= 1'd0; + maccore_ethphy_demux_endpoint0_source_last <= 1'd0; + maccore_ethphy_demux_endpoint0_source_payload_data <= 8'd0; + maccore_ethphy_demux_endpoint0_source_payload_error <= 1'd0; + maccore_ethphy_demux_endpoint0_source_payload_last_be <= 1'd0; + maccore_ethphy_demux_endpoint0_source_valid <= 1'd0; + maccore_ethphy_demux_endpoint1_source_first <= 1'd0; + maccore_ethphy_demux_endpoint1_source_last <= 1'd0; + maccore_ethphy_demux_endpoint1_source_payload_data <= 8'd0; + maccore_ethphy_demux_endpoint1_source_payload_error <= 1'd0; + maccore_ethphy_demux_endpoint1_source_payload_last_be <= 1'd0; + maccore_ethphy_demux_endpoint1_source_valid <= 1'd0; + maccore_ethphy_demux_sink_ready <= 1'd0; + case (maccore_ethphy_demux_sel) 1'd0: begin - main_maccore_ethphy_demux_endpoint0_source_valid <= main_maccore_ethphy_demux_sink_valid; - main_maccore_ethphy_demux_sink_ready <= main_maccore_ethphy_demux_endpoint0_source_ready; - main_maccore_ethphy_demux_endpoint0_source_first <= main_maccore_ethphy_demux_sink_first; - main_maccore_ethphy_demux_endpoint0_source_last <= main_maccore_ethphy_demux_sink_last; - main_maccore_ethphy_demux_endpoint0_source_payload_data <= main_maccore_ethphy_demux_sink_payload_data; - main_maccore_ethphy_demux_endpoint0_source_payload_last_be <= main_maccore_ethphy_demux_sink_payload_last_be; - main_maccore_ethphy_demux_endpoint0_source_payload_error <= main_maccore_ethphy_demux_sink_payload_error; + maccore_ethphy_demux_endpoint0_source_valid <= maccore_ethphy_demux_sink_valid; + maccore_ethphy_demux_sink_ready <= maccore_ethphy_demux_endpoint0_source_ready; + maccore_ethphy_demux_endpoint0_source_first <= maccore_ethphy_demux_sink_first; + maccore_ethphy_demux_endpoint0_source_last <= maccore_ethphy_demux_sink_last; + maccore_ethphy_demux_endpoint0_source_payload_data <= maccore_ethphy_demux_sink_payload_data; + maccore_ethphy_demux_endpoint0_source_payload_last_be <= maccore_ethphy_demux_sink_payload_last_be; + maccore_ethphy_demux_endpoint0_source_payload_error <= maccore_ethphy_demux_sink_payload_error; end 1'd1: begin - main_maccore_ethphy_demux_endpoint1_source_valid <= main_maccore_ethphy_demux_sink_valid; - main_maccore_ethphy_demux_sink_ready <= main_maccore_ethphy_demux_endpoint1_source_ready; - main_maccore_ethphy_demux_endpoint1_source_first <= main_maccore_ethphy_demux_sink_first; - main_maccore_ethphy_demux_endpoint1_source_last <= main_maccore_ethphy_demux_sink_last; - main_maccore_ethphy_demux_endpoint1_source_payload_data <= main_maccore_ethphy_demux_sink_payload_data; - main_maccore_ethphy_demux_endpoint1_source_payload_last_be <= main_maccore_ethphy_demux_sink_payload_last_be; - main_maccore_ethphy_demux_endpoint1_source_payload_error <= main_maccore_ethphy_demux_sink_payload_error; + maccore_ethphy_demux_endpoint1_source_valid <= maccore_ethphy_demux_sink_valid; + maccore_ethphy_demux_sink_ready <= maccore_ethphy_demux_endpoint1_source_ready; + maccore_ethphy_demux_endpoint1_source_first <= maccore_ethphy_demux_sink_first; + maccore_ethphy_demux_endpoint1_source_last <= maccore_ethphy_demux_sink_last; + maccore_ethphy_demux_endpoint1_source_payload_data <= maccore_ethphy_demux_sink_payload_data; + maccore_ethphy_demux_endpoint1_source_payload_last_be <= maccore_ethphy_demux_sink_payload_last_be; + maccore_ethphy_demux_endpoint1_source_payload_error <= maccore_ethphy_demux_sink_payload_error; end endcase end -assign main_maccore_ethphy_mux_sel = (main_maccore_ethphy_mode0 == 1'd1); -assign main_maccore_ethphy_mux_endpoint0_sink_valid = main_maccore_ethphy_gmii_rx_source_valid; -assign main_maccore_ethphy_gmii_rx_source_ready = main_maccore_ethphy_mux_endpoint0_sink_ready; -assign main_maccore_ethphy_mux_endpoint0_sink_first = main_maccore_ethphy_gmii_rx_source_first; -assign main_maccore_ethphy_mux_endpoint0_sink_last = main_maccore_ethphy_gmii_rx_source_last; -assign main_maccore_ethphy_mux_endpoint0_sink_payload_data = main_maccore_ethphy_gmii_rx_source_payload_data; -assign main_maccore_ethphy_mux_endpoint0_sink_payload_last_be = main_maccore_ethphy_gmii_rx_source_payload_last_be; -assign main_maccore_ethphy_mux_endpoint0_sink_payload_error = main_maccore_ethphy_gmii_rx_source_payload_error; -assign main_maccore_ethphy_mux_endpoint1_sink_valid = main_maccore_ethphy_mii_rx_source_valid; -assign main_maccore_ethphy_mii_rx_source_ready = main_maccore_ethphy_mux_endpoint1_sink_ready; -assign main_maccore_ethphy_mux_endpoint1_sink_first = main_maccore_ethphy_mii_rx_source_first; -assign main_maccore_ethphy_mux_endpoint1_sink_last = main_maccore_ethphy_mii_rx_source_last; -assign main_maccore_ethphy_mux_endpoint1_sink_payload_data = main_maccore_ethphy_mii_rx_source_payload_data; -assign main_maccore_ethphy_mux_endpoint1_sink_payload_last_be = main_maccore_ethphy_mii_rx_source_payload_last_be; -assign main_maccore_ethphy_mux_endpoint1_sink_payload_error = main_maccore_ethphy_mii_rx_source_payload_error; -assign main_maccore_ethphy_source_source_valid = main_maccore_ethphy_mux_source_valid; -assign main_maccore_ethphy_mux_source_ready = main_maccore_ethphy_source_source_ready; -assign main_maccore_ethphy_source_source_first = main_maccore_ethphy_mux_source_first; -assign main_maccore_ethphy_source_source_last = main_maccore_ethphy_mux_source_last; -assign main_maccore_ethphy_source_source_payload_data = main_maccore_ethphy_mux_source_payload_data; -assign main_maccore_ethphy_source_source_payload_last_be = main_maccore_ethphy_mux_source_payload_last_be; -assign main_maccore_ethphy_source_source_payload_error = main_maccore_ethphy_mux_source_payload_error; -assign main_maccore_ethphy_gmii_rx_source_last = ((~main_maccore_ethphy_pads_d_rx_dv) & main_maccore_ethphy_gmii_rx_dv_d); -assign main_maccore_ethphy_mii_rx_converter_sink_last = (~main_maccore_ethphy_pads_d_rx_dv); -assign main_maccore_ethphy_mii_rx_source_valid = main_maccore_ethphy_mii_rx_source_source_valid; -assign main_maccore_ethphy_mii_rx_source_source_ready = main_maccore_ethphy_mii_rx_source_ready; -assign main_maccore_ethphy_mii_rx_source_first = main_maccore_ethphy_mii_rx_source_source_first; -assign main_maccore_ethphy_mii_rx_source_last = main_maccore_ethphy_mii_rx_source_source_last; -assign main_maccore_ethphy_mii_rx_source_payload_data = main_maccore_ethphy_mii_rx_source_source_payload_data; -assign main_maccore_ethphy_mii_rx_source_source_valid = main_maccore_ethphy_mii_rx_converter_source_valid; -assign main_maccore_ethphy_mii_rx_converter_source_ready = main_maccore_ethphy_mii_rx_source_source_ready; -assign main_maccore_ethphy_mii_rx_source_source_first = main_maccore_ethphy_mii_rx_converter_source_first; -assign main_maccore_ethphy_mii_rx_source_source_last = main_maccore_ethphy_mii_rx_converter_source_last; -assign main_maccore_ethphy_mii_rx_source_source_payload_data = main_maccore_ethphy_mii_rx_converter_source_payload_data; -assign main_maccore_ethphy_mii_rx_converter_sink_ready = ((~main_maccore_ethphy_mii_rx_converter_strobe_all) | main_maccore_ethphy_mii_rx_converter_source_ready); -assign main_maccore_ethphy_mii_rx_converter_source_valid = main_maccore_ethphy_mii_rx_converter_strobe_all; -assign main_maccore_ethphy_mii_rx_converter_load_part = (main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready); +assign maccore_ethphy_mux_sel = (maccore_ethphy_mode0 == 1'd1); +assign maccore_ethphy_mux_endpoint0_sink_valid = maccore_ethphy_gmii_rx_source_valid; +assign maccore_ethphy_gmii_rx_source_ready = maccore_ethphy_mux_endpoint0_sink_ready; +assign maccore_ethphy_mux_endpoint0_sink_first = maccore_ethphy_gmii_rx_source_first; +assign maccore_ethphy_mux_endpoint0_sink_last = maccore_ethphy_gmii_rx_source_last; +assign maccore_ethphy_mux_endpoint0_sink_payload_data = maccore_ethphy_gmii_rx_source_payload_data; +assign maccore_ethphy_mux_endpoint0_sink_payload_last_be = maccore_ethphy_gmii_rx_source_payload_last_be; +assign maccore_ethphy_mux_endpoint0_sink_payload_error = maccore_ethphy_gmii_rx_source_payload_error; +assign maccore_ethphy_mux_endpoint1_sink_valid = maccore_ethphy_mii_rx_source_valid; +assign maccore_ethphy_mii_rx_source_ready = maccore_ethphy_mux_endpoint1_sink_ready; +assign maccore_ethphy_mux_endpoint1_sink_first = maccore_ethphy_mii_rx_source_first; +assign maccore_ethphy_mux_endpoint1_sink_last = maccore_ethphy_mii_rx_source_last; +assign maccore_ethphy_mux_endpoint1_sink_payload_data = maccore_ethphy_mii_rx_source_payload_data; +assign maccore_ethphy_mux_endpoint1_sink_payload_last_be = maccore_ethphy_mii_rx_source_payload_last_be; +assign maccore_ethphy_mux_endpoint1_sink_payload_error = maccore_ethphy_mii_rx_source_payload_error; +assign maccore_ethphy_source_source_valid = maccore_ethphy_mux_source_valid; +assign maccore_ethphy_mux_source_ready = maccore_ethphy_source_source_ready; +assign maccore_ethphy_source_source_first = maccore_ethphy_mux_source_first; +assign maccore_ethphy_source_source_last = maccore_ethphy_mux_source_last; +assign maccore_ethphy_source_source_payload_data = maccore_ethphy_mux_source_payload_data; +assign maccore_ethphy_source_source_payload_last_be = maccore_ethphy_mux_source_payload_last_be; +assign maccore_ethphy_source_source_payload_error = maccore_ethphy_mux_source_payload_error; +assign maccore_ethphy_gmii_rx_source_last = ((~maccore_ethphy_pads_d_rx_dv) & maccore_ethphy_gmii_rx_dv_d); +assign maccore_ethphy_mii_rx_converter_sink_last = (~maccore_ethphy_pads_d_rx_dv); +assign maccore_ethphy_mii_rx_source_valid = maccore_ethphy_mii_rx_source_source_valid; +assign maccore_ethphy_mii_rx_source_source_ready = maccore_ethphy_mii_rx_source_ready; +assign maccore_ethphy_mii_rx_source_first = maccore_ethphy_mii_rx_source_source_first; +assign maccore_ethphy_mii_rx_source_last = maccore_ethphy_mii_rx_source_source_last; +assign maccore_ethphy_mii_rx_source_payload_data = maccore_ethphy_mii_rx_source_source_payload_data; +assign maccore_ethphy_mii_rx_source_source_valid = maccore_ethphy_mii_rx_converter_source_valid; +assign maccore_ethphy_mii_rx_converter_source_ready = maccore_ethphy_mii_rx_source_source_ready; +assign maccore_ethphy_mii_rx_source_source_first = maccore_ethphy_mii_rx_converter_source_first; +assign maccore_ethphy_mii_rx_source_source_last = maccore_ethphy_mii_rx_converter_source_last; +assign maccore_ethphy_mii_rx_source_source_payload_data = maccore_ethphy_mii_rx_converter_source_payload_data; +assign maccore_ethphy_mii_rx_converter_sink_ready = ((~maccore_ethphy_mii_rx_converter_strobe_all) | maccore_ethphy_mii_rx_converter_source_ready); +assign maccore_ethphy_mii_rx_converter_source_valid = maccore_ethphy_mii_rx_converter_strobe_all; +assign maccore_ethphy_mii_rx_converter_load_part = (maccore_ethphy_mii_rx_converter_sink_valid & maccore_ethphy_mii_rx_converter_sink_ready); always @(*) begin - main_maccore_ethphy_mux_endpoint0_sink_ready <= 1'd0; - main_maccore_ethphy_mux_endpoint1_sink_ready <= 1'd0; - main_maccore_ethphy_mux_source_first <= 1'd0; - main_maccore_ethphy_mux_source_last <= 1'd0; - main_maccore_ethphy_mux_source_payload_data <= 8'd0; - main_maccore_ethphy_mux_source_payload_error <= 1'd0; - main_maccore_ethphy_mux_source_payload_last_be <= 1'd0; - main_maccore_ethphy_mux_source_valid <= 1'd0; - case (main_maccore_ethphy_mux_sel) + maccore_ethphy_mux_endpoint0_sink_ready <= 1'd0; + maccore_ethphy_mux_endpoint1_sink_ready <= 1'd0; + maccore_ethphy_mux_source_first <= 1'd0; + maccore_ethphy_mux_source_last <= 1'd0; + maccore_ethphy_mux_source_payload_data <= 8'd0; + maccore_ethphy_mux_source_payload_error <= 1'd0; + maccore_ethphy_mux_source_payload_last_be <= 1'd0; + maccore_ethphy_mux_source_valid <= 1'd0; + case (maccore_ethphy_mux_sel) 1'd0: begin - main_maccore_ethphy_mux_source_valid <= main_maccore_ethphy_mux_endpoint0_sink_valid; - main_maccore_ethphy_mux_endpoint0_sink_ready <= main_maccore_ethphy_mux_source_ready; - main_maccore_ethphy_mux_source_first <= main_maccore_ethphy_mux_endpoint0_sink_first; - main_maccore_ethphy_mux_source_last <= main_maccore_ethphy_mux_endpoint0_sink_last; - main_maccore_ethphy_mux_source_payload_data <= main_maccore_ethphy_mux_endpoint0_sink_payload_data; - main_maccore_ethphy_mux_source_payload_last_be <= main_maccore_ethphy_mux_endpoint0_sink_payload_last_be; - main_maccore_ethphy_mux_source_payload_error <= main_maccore_ethphy_mux_endpoint0_sink_payload_error; + maccore_ethphy_mux_source_valid <= maccore_ethphy_mux_endpoint0_sink_valid; + maccore_ethphy_mux_endpoint0_sink_ready <= maccore_ethphy_mux_source_ready; + maccore_ethphy_mux_source_first <= maccore_ethphy_mux_endpoint0_sink_first; + maccore_ethphy_mux_source_last <= maccore_ethphy_mux_endpoint0_sink_last; + maccore_ethphy_mux_source_payload_data <= maccore_ethphy_mux_endpoint0_sink_payload_data; + maccore_ethphy_mux_source_payload_last_be <= maccore_ethphy_mux_endpoint0_sink_payload_last_be; + maccore_ethphy_mux_source_payload_error <= maccore_ethphy_mux_endpoint0_sink_payload_error; end 1'd1: begin - main_maccore_ethphy_mux_source_valid <= main_maccore_ethphy_mux_endpoint1_sink_valid; - main_maccore_ethphy_mux_endpoint1_sink_ready <= main_maccore_ethphy_mux_source_ready; - main_maccore_ethphy_mux_source_first <= main_maccore_ethphy_mux_endpoint1_sink_first; - main_maccore_ethphy_mux_source_last <= main_maccore_ethphy_mux_endpoint1_sink_last; - main_maccore_ethphy_mux_source_payload_data <= main_maccore_ethphy_mux_endpoint1_sink_payload_data; - main_maccore_ethphy_mux_source_payload_last_be <= main_maccore_ethphy_mux_endpoint1_sink_payload_last_be; - main_maccore_ethphy_mux_source_payload_error <= main_maccore_ethphy_mux_endpoint1_sink_payload_error; + maccore_ethphy_mux_source_valid <= maccore_ethphy_mux_endpoint1_sink_valid; + maccore_ethphy_mux_endpoint1_sink_ready <= maccore_ethphy_mux_source_ready; + maccore_ethphy_mux_source_first <= maccore_ethphy_mux_endpoint1_sink_first; + maccore_ethphy_mux_source_last <= maccore_ethphy_mux_endpoint1_sink_last; + maccore_ethphy_mux_source_payload_data <= maccore_ethphy_mux_endpoint1_sink_payload_data; + maccore_ethphy_mux_source_payload_last_be <= maccore_ethphy_mux_endpoint1_sink_payload_last_be; + maccore_ethphy_mux_source_payload_error <= maccore_ethphy_mux_endpoint1_sink_payload_error; end endcase end -assign gmii_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_sink_valid = main_source_source_valid; -assign main_source_source_ready = main_sink_ready; -assign main_sink_first = main_source_source_first; -assign main_sink_last = main_source_source_last; -assign main_sink_payload_data = main_source_source_payload_data; -assign main_sink_payload_last_be = main_source_source_payload_last_be; -assign main_sink_payload_error = main_source_source_payload_error; -assign main_sink_sink_valid = main_source_valid; -assign main_source_ready = main_sink_sink_ready; -assign main_sink_sink_first = main_source_first; -assign main_sink_sink_last = main_source_last; -assign main_sink_sink_payload_data = main_source_payload_data; -assign main_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_sink_sink_payload_error = main_source_payload_error; -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +assign gmii_mdc = maccore_ethphy__w_storage[0]; +assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1]; +assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2]; +assign core_sink_valid = wishbone_interface_source_valid; +assign wishbone_interface_source_ready = core_sink_ready; +assign core_sink_first = wishbone_interface_source_first; +assign core_sink_last = wishbone_interface_source_last; +assign core_sink_payload_data = wishbone_interface_source_payload_data; +assign core_sink_payload_last_be = wishbone_interface_source_payload_last_be; +assign core_sink_payload_error = wishbone_interface_source_payload_error; +assign wishbone_interface_sink_valid = core_source_valid; +assign core_source_ready = wishbone_interface_sink_ready; +assign wishbone_interface_sink_first = core_source_first; +assign wishbone_interface_sink_last = core_source_last; +assign wishbone_interface_sink_payload_data = core_source_payload_data; +assign wishbone_interface_sink_payload_last_be = core_source_payload_last_be; +assign wishbone_interface_sink_payload_error = core_source_payload_error; +assign core_tx_cdc_cdc_sink_valid = core_tx_cdc_sink_sink_valid; +assign core_tx_cdc_sink_sink_ready = core_tx_cdc_cdc_sink_ready; +assign core_tx_cdc_cdc_sink_first = core_tx_cdc_sink_sink_first; +assign core_tx_cdc_cdc_sink_last = core_tx_cdc_sink_sink_last; +assign core_tx_cdc_cdc_sink_payload_data = core_tx_cdc_sink_sink_payload_data; +assign core_tx_cdc_cdc_sink_payload_last_be = core_tx_cdc_sink_sink_payload_last_be; +assign core_tx_cdc_cdc_sink_payload_error = core_tx_cdc_sink_sink_payload_error; +assign core_tx_cdc_source_source_valid = core_tx_cdc_cdc_source_valid; +assign core_tx_cdc_cdc_source_ready = core_tx_cdc_source_source_ready; +assign core_tx_cdc_source_source_first = core_tx_cdc_cdc_source_first; +assign core_tx_cdc_source_source_last = core_tx_cdc_cdc_source_last; +assign core_tx_cdc_source_source_payload_data = core_tx_cdc_cdc_source_payload_data; +assign core_tx_cdc_source_source_payload_last_be = core_tx_cdc_cdc_source_payload_last_be; +assign core_tx_cdc_source_source_payload_error = core_tx_cdc_cdc_source_payload_error; +assign core_tx_cdc_cdc_asyncfifo_din = {core_tx_cdc_cdc_fifo_in_last, core_tx_cdc_cdc_fifo_in_first, core_tx_cdc_cdc_fifo_in_payload_error, core_tx_cdc_cdc_fifo_in_payload_last_be, core_tx_cdc_cdc_fifo_in_payload_data}; +assign {core_tx_cdc_cdc_fifo_out_last, core_tx_cdc_cdc_fifo_out_first, core_tx_cdc_cdc_fifo_out_payload_error, core_tx_cdc_cdc_fifo_out_payload_last_be, core_tx_cdc_cdc_fifo_out_payload_data} = core_tx_cdc_cdc_asyncfifo_dout; +assign core_tx_cdc_cdc_sink_ready = core_tx_cdc_cdc_asyncfifo_writable; +assign core_tx_cdc_cdc_asyncfifo_we = core_tx_cdc_cdc_sink_valid; +assign core_tx_cdc_cdc_fifo_in_first = core_tx_cdc_cdc_sink_first; +assign core_tx_cdc_cdc_fifo_in_last = core_tx_cdc_cdc_sink_last; +assign core_tx_cdc_cdc_fifo_in_payload_data = core_tx_cdc_cdc_sink_payload_data; +assign core_tx_cdc_cdc_fifo_in_payload_last_be = core_tx_cdc_cdc_sink_payload_last_be; +assign core_tx_cdc_cdc_fifo_in_payload_error = core_tx_cdc_cdc_sink_payload_error; +assign core_tx_cdc_cdc_source_valid = core_tx_cdc_cdc_asyncfifo_readable; +assign core_tx_cdc_cdc_source_first = core_tx_cdc_cdc_fifo_out_first; +assign core_tx_cdc_cdc_source_last = core_tx_cdc_cdc_fifo_out_last; +assign core_tx_cdc_cdc_source_payload_data = core_tx_cdc_cdc_fifo_out_payload_data; +assign core_tx_cdc_cdc_source_payload_last_be = core_tx_cdc_cdc_fifo_out_payload_last_be; +assign core_tx_cdc_cdc_source_payload_error = core_tx_cdc_cdc_fifo_out_payload_error; +assign core_tx_cdc_cdc_asyncfifo_re = core_tx_cdc_cdc_source_ready; +assign core_tx_cdc_cdc_graycounter0_ce = (core_tx_cdc_cdc_asyncfifo_writable & core_tx_cdc_cdc_asyncfifo_we); +assign core_tx_cdc_cdc_graycounter1_ce = (core_tx_cdc_cdc_asyncfifo_readable & core_tx_cdc_cdc_asyncfifo_re); +assign core_tx_cdc_cdc_asyncfifo_writable = (((core_tx_cdc_cdc_graycounter0_q[5] == core_tx_cdc_cdc_consume_wdomain[5]) | (core_tx_cdc_cdc_graycounter0_q[4] == core_tx_cdc_cdc_consume_wdomain[4])) | (core_tx_cdc_cdc_graycounter0_q[3:0] != core_tx_cdc_cdc_consume_wdomain[3:0])); +assign core_tx_cdc_cdc_asyncfifo_readable = (core_tx_cdc_cdc_graycounter1_q != core_tx_cdc_cdc_produce_rdomain); +assign core_tx_cdc_cdc_wrport_adr = core_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_tx_cdc_cdc_wrport_dat_w = core_tx_cdc_cdc_asyncfifo_din; +assign core_tx_cdc_cdc_wrport_we = core_tx_cdc_cdc_graycounter0_ce; +assign core_tx_cdc_cdc_rdport_adr = core_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_tx_cdc_cdc_asyncfifo_dout = core_tx_cdc_cdc_rdport_dat_r; always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter0_ce) begin + core_tx_cdc_cdc_graycounter0_q_next_binary <= (core_tx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + core_tx_cdc_cdc_graycounter0_q_next_binary <= core_tx_cdc_cdc_graycounter0_q_binary; end end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_tx_cdc_cdc_graycounter0_q_next = (core_tx_cdc_cdc_graycounter0_q_next_binary ^ core_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_tx_cdc_cdc_graycounter1_ce) begin + core_tx_cdc_cdc_graycounter1_q_next_binary <= (core_tx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + core_tx_cdc_cdc_graycounter1_q_next_binary <= core_tx_cdc_cdc_graycounter1_q_binary; end end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +assign core_tx_cdc_cdc_graycounter1_q_next = (core_tx_cdc_cdc_graycounter1_q_next_binary ^ core_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_tx_converter_converter_sink_valid = core_tx_converter_sink_valid; +assign core_tx_converter_converter_sink_first = core_tx_converter_sink_first; +assign core_tx_converter_converter_sink_last = core_tx_converter_sink_last; +assign core_tx_converter_sink_ready = core_tx_converter_converter_sink_ready; always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; + core_tx_converter_converter_sink_payload_data <= 40'd0; + core_tx_converter_converter_sink_payload_data[7:0] <= core_tx_converter_sink_payload_data[7:0]; + core_tx_converter_converter_sink_payload_data[8] <= core_tx_converter_sink_payload_last_be[0]; + core_tx_converter_converter_sink_payload_data[9] <= core_tx_converter_sink_payload_error[0]; + core_tx_converter_converter_sink_payload_data[17:10] <= core_tx_converter_sink_payload_data[15:8]; + core_tx_converter_converter_sink_payload_data[18] <= core_tx_converter_sink_payload_last_be[1]; + core_tx_converter_converter_sink_payload_data[19] <= core_tx_converter_sink_payload_error[1]; + core_tx_converter_converter_sink_payload_data[27:20] <= core_tx_converter_sink_payload_data[23:16]; + core_tx_converter_converter_sink_payload_data[28] <= core_tx_converter_sink_payload_last_be[2]; + core_tx_converter_converter_sink_payload_data[29] <= core_tx_converter_sink_payload_error[2]; + core_tx_converter_converter_sink_payload_data[37:30] <= core_tx_converter_sink_payload_data[31:24]; + core_tx_converter_converter_sink_payload_data[38] <= core_tx_converter_sink_payload_last_be[3]; + core_tx_converter_converter_sink_payload_data[39] <= core_tx_converter_sink_payload_error[3]; end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +assign core_tx_converter_source_valid = core_tx_converter_source_source_valid; +assign core_tx_converter_source_first = core_tx_converter_source_source_first; +assign core_tx_converter_source_last = core_tx_converter_source_source_last; +assign core_tx_converter_source_source_ready = core_tx_converter_source_ready; +assign {core_tx_converter_source_payload_error, core_tx_converter_source_payload_last_be, core_tx_converter_source_payload_data} = core_tx_converter_source_source_payload_data; +assign core_tx_converter_source_source_valid = core_tx_converter_converter_source_valid; +assign core_tx_converter_converter_source_ready = core_tx_converter_source_source_ready; +assign core_tx_converter_source_source_first = core_tx_converter_converter_source_first; +assign core_tx_converter_source_source_last = core_tx_converter_converter_source_last; +assign core_tx_converter_source_source_payload_data = core_tx_converter_converter_source_payload_data; +assign core_tx_converter_converter_first = (core_tx_converter_converter_mux == 1'd0); +assign core_tx_converter_converter_last = (core_tx_converter_converter_mux == 2'd3); +assign core_tx_converter_converter_source_valid = core_tx_converter_converter_sink_valid; +assign core_tx_converter_converter_source_first = (core_tx_converter_converter_sink_first & core_tx_converter_converter_first); +assign core_tx_converter_converter_source_last = (core_tx_converter_converter_sink_last & core_tx_converter_converter_last); +assign core_tx_converter_converter_sink_ready = (core_tx_converter_converter_last & core_tx_converter_converter_source_ready); always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) + core_tx_converter_converter_source_payload_data <= 10'd0; + case (core_tx_converter_converter_mux) 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[9:0]; end 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[19:10]; end 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[29:20]; end default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[39:30]; end endcase end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +assign core_tx_converter_converter_source_payload_valid_token_count = core_tx_converter_converter_last; +assign core_tx_last_be_last_handler_sink_valid = core_tx_last_be_sink_sink_valid; +assign core_tx_last_be_sink_sink_ready = core_tx_last_be_last_handler_sink_ready; +assign core_tx_last_be_last_handler_sink_first = core_tx_last_be_sink_sink_first; +assign core_tx_last_be_last_handler_sink_last = core_tx_last_be_sink_sink_last; +assign core_tx_last_be_last_handler_sink_payload_data = core_tx_last_be_sink_sink_payload_data; +assign core_tx_last_be_last_handler_sink_payload_last_be = core_tx_last_be_sink_sink_payload_last_be; +assign core_tx_last_be_last_handler_sink_payload_error = core_tx_last_be_sink_sink_payload_error; +assign core_tx_last_be_source_source_valid = core_tx_last_be_last_handler_source_valid; +assign core_tx_last_be_last_handler_source_ready = core_tx_last_be_source_source_ready; +assign core_tx_last_be_source_source_first = core_tx_last_be_last_handler_source_first; +assign core_tx_last_be_source_source_last = core_tx_last_be_last_handler_source_last; +assign core_tx_last_be_source_source_payload_data = core_tx_last_be_last_handler_source_payload_data; +assign core_tx_last_be_source_source_payload_last_be = core_tx_last_be_last_handler_source_payload_last_be; +assign core_tx_last_be_source_source_payload_error = core_tx_last_be_last_handler_source_payload_error; always @(*) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - main_tx_last_be_source_payload_last_be <= 1'd0; - main_tx_last_be_source_valid <= 1'd0; - builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; - case (builder_txdatapath_liteethmactxlastbe_state) + core_tx_last_be_last_handler_sink_ready <= 1'd0; + core_tx_last_be_last_handler_source_first <= 1'd0; + core_tx_last_be_last_handler_source_last <= 1'd0; + core_tx_last_be_last_handler_source_payload_data <= 8'd0; + core_tx_last_be_last_handler_source_payload_error <= 1'd0; + core_tx_last_be_last_handler_source_payload_last_be <= 1'd0; + core_tx_last_be_last_handler_source_valid <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= 1'd0; + txdatapath_liteethmactxlastbe_next_state <= txdatapath_liteethmactxlastbe_state; + case (txdatapath_liteethmactxlastbe_state) 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + core_tx_last_be_last_handler_sink_ready <= 1'd1; + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_last)) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd0; end end default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_last <= main_tx_last_be_sink_last; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin - builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + core_tx_last_be_last_handler_source_valid <= core_tx_last_be_last_handler_sink_valid; + core_tx_last_be_last_handler_sink_ready <= core_tx_last_be_last_handler_source_ready; + core_tx_last_be_last_handler_source_first <= core_tx_last_be_last_handler_sink_first; + core_tx_last_be_last_handler_source_last <= core_tx_last_be_last_handler_sink_last; + core_tx_last_be_last_handler_source_payload_data <= core_tx_last_be_last_handler_sink_payload_data; + core_tx_last_be_last_handler_source_payload_last_be <= core_tx_last_be_last_handler_sink_payload_last_be; + core_tx_last_be_last_handler_source_payload_error <= core_tx_last_be_last_handler_sink_payload_error; + core_tx_last_be_last_handler_source_last <= (core_tx_last_be_last_handler_sink_payload_last_be != 1'd0); + if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_ready)) begin + if ((core_tx_last_be_last_handler_source_last & (~core_tx_last_be_last_handler_sink_last))) begin + txdatapath_liteethmactxlastbe_next_state <= 1'd1; end end end endcase end -assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +assign core_tx_padding_counter_done = (core_tx_padding_counter >= 6'd59); always @(*) begin - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; - main_tx_padding_sink_ready <= 1'd0; - main_tx_padding_source_first <= 1'd0; - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_data <= 8'd0; - main_tx_padding_source_payload_error <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - main_tx_padding_source_valid <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; - case (builder_txdatapath_liteethmacpaddinginserter_state) + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + core_tx_padding_sink_ready <= 1'd0; + core_tx_padding_source_first <= 1'd0; + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_data <= 8'd0; + core_tx_padding_source_payload_error <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + core_tx_padding_source_valid <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= txdatapath_liteethmacpaddinginserter_state; + case (txdatapath_liteethmacpaddinginserter_state) 1'd1: begin - main_tx_padding_source_valid <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_source_payload_last_be <= 1'd1; - main_tx_padding_source_last <= 1'd1; + core_tx_padding_source_valid <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_source_payload_last_be <= 1'd1; + core_tx_padding_source_last <= 1'd1; end - main_tx_padding_source_payload_data <= 1'd0; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_counter_done) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + core_tx_padding_source_payload_data <= 1'd0; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_counter_done) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; end end end default: begin - main_tx_padding_source_valid <= main_tx_padding_sink_valid; - main_tx_padding_sink_ready <= main_tx_padding_source_ready; - main_tx_padding_source_first <= main_tx_padding_sink_first; - main_tx_padding_source_last <= main_tx_padding_sink_last; - main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; - main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; - main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; - if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; - if (main_tx_padding_sink_last) begin - if ((~main_tx_padding_counter_done)) begin - main_tx_padding_source_last <= 1'd0; - main_tx_padding_source_payload_last_be <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + core_tx_padding_source_valid <= core_tx_padding_sink_valid; + core_tx_padding_sink_ready <= core_tx_padding_source_ready; + core_tx_padding_source_first <= core_tx_padding_sink_first; + core_tx_padding_source_last <= core_tx_padding_sink_last; + core_tx_padding_source_payload_data <= core_tx_padding_sink_payload_data; + core_tx_padding_source_payload_last_be <= core_tx_padding_sink_payload_last_be; + core_tx_padding_source_payload_error <= core_tx_padding_sink_payload_error; + if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin + core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (core_tx_padding_sink_last) begin + if ((~core_tx_padding_counter_done)) begin + core_tx_padding_source_last <= 1'd0; + core_tx_padding_source_payload_last_be <= 1'd0; + txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; end else begin - if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin - main_tx_padding_source_payload_last_be <= 1'd1; + if (((core_tx_padding_counter == 6'd59) & (core_tx_padding_sink_payload_last_be < 1'd1))) begin + core_tx_padding_source_payload_last_be <= 1'd1; end else begin - main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; - main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; end end end @@ -1943,1573 +1936,1506 @@ always @(*) begin end endcase end -assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; -assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; -assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); -assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; -assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; -assign main_tx_crc_sink_first = main_tx_crc_source_source_first; -assign main_tx_crc_sink_last = main_tx_crc_source_source_last; -assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; -assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; -assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; -assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; -assign main_tx_crc_crc_prev = main_tx_crc_reg; +assign core_tx_crc_data0 = core_tx_crc_sink_payload_data; +assign core_tx_crc_be = core_tx_crc_sink_payload_last_be; +assign core_tx_crc_cnt_done = (core_tx_crc_cnt == 1'd0); +assign core_tx_crc_sink_valid = core_tx_crc_source_source_valid; +assign core_tx_crc_source_source_ready = core_tx_crc_sink_ready; +assign core_tx_crc_sink_first = core_tx_crc_source_source_first; +assign core_tx_crc_sink_last = core_tx_crc_source_source_last; +assign core_tx_crc_sink_payload_data = core_tx_crc_source_source_payload_data; +assign core_tx_crc_sink_payload_last_be = core_tx_crc_source_source_payload_last_be; +assign core_tx_crc_sink_payload_error = core_tx_crc_source_source_payload_error; +assign core_tx_crc_data1 = core_tx_crc_data0; +assign core_tx_crc_crc_prev = core_tx_crc_reg; always @(*) begin - main_tx_crc_error <= 1'd0; - main_tx_crc_value <= 32'd0; - if (main_tx_crc_be) begin - main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; - main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + core_tx_crc_error <= 1'd0; + core_tx_crc_value <= 32'd0; + if (core_tx_crc_be) begin + core_tx_crc_value <= ({core_tx_crc_crc_next[0], core_tx_crc_crc_next[1], core_tx_crc_crc_next[2], core_tx_crc_crc_next[3], core_tx_crc_crc_next[4], core_tx_crc_crc_next[5], core_tx_crc_crc_next[6], core_tx_crc_crc_next[7], core_tx_crc_crc_next[8], core_tx_crc_crc_next[9], core_tx_crc_crc_next[10], core_tx_crc_crc_next[11], core_tx_crc_crc_next[12], core_tx_crc_crc_next[13], core_tx_crc_crc_next[14], core_tx_crc_crc_next[15], core_tx_crc_crc_next[16], core_tx_crc_crc_next[17], core_tx_crc_crc_next[18], core_tx_crc_crc_next[19], core_tx_crc_crc_next[20], core_tx_crc_crc_next[21], core_tx_crc_crc_next[22], core_tx_crc_crc_next[23], core_tx_crc_crc_next[24], core_tx_crc_crc_next[25], core_tx_crc_crc_next[26], core_tx_crc_crc_next[27], core_tx_crc_crc_next[28], core_tx_crc_crc_next[29], core_tx_crc_crc_next[30], core_tx_crc_crc_next[31]} ^ 32'd4294967295); + core_tx_crc_error <= (core_tx_crc_crc_next != 32'd3338984827); end end always @(*) begin - main_tx_crc_crc_next <= 32'd0; - main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); - main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); - main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); - main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); - main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); - main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); - main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + core_tx_crc_crc_next <= 32'd0; + core_tx_crc_crc_next[0] <= (((core_tx_crc_crc_prev[24] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[1] <= (((((((core_tx_crc_crc_prev[25] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[2] <= (((((((((core_tx_crc_crc_prev[26] ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[3] <= (((((((core_tx_crc_crc_prev[27] ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[4] <= (((((((((core_tx_crc_crc_prev[28] ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[5] <= (((((((((((((core_tx_crc_crc_prev[29] ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[6] <= (((((((((((core_tx_crc_crc_prev[30] ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[7] <= (((((((((core_tx_crc_crc_prev[31] ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[8] <= ((((((((core_tx_crc_crc_prev[0] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[9] <= ((((((((core_tx_crc_crc_prev[1] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[10] <= ((((((((core_tx_crc_crc_prev[2] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[11] <= ((((((((core_tx_crc_crc_prev[3] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[12] <= ((((((((((((core_tx_crc_crc_prev[4] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[13] <= ((((((((((((core_tx_crc_crc_prev[5] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[14] <= ((((((((((core_tx_crc_crc_prev[6] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[15] <= ((((((((core_tx_crc_crc_prev[7] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[16] <= ((((((core_tx_crc_crc_prev[8] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[17] <= ((((((core_tx_crc_crc_prev[9] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[18] <= ((((((core_tx_crc_crc_prev[10] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[19] <= ((((core_tx_crc_crc_prev[11] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[20] <= ((core_tx_crc_crc_prev[12] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[21] <= ((core_tx_crc_crc_prev[13] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); + core_tx_crc_crc_next[22] <= ((core_tx_crc_crc_prev[14] ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[23] <= ((((((core_tx_crc_crc_prev[15] ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[24] <= ((((((core_tx_crc_crc_prev[16] ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[25] <= ((((core_tx_crc_crc_prev[17] ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[26] <= ((((((((core_tx_crc_crc_prev[18] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); + core_tx_crc_crc_next[27] <= ((((((((core_tx_crc_crc_prev[19] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); + core_tx_crc_crc_next[28] <= ((((((core_tx_crc_crc_prev[20] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); + core_tx_crc_crc_next[29] <= ((((((core_tx_crc_crc_prev[21] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); + core_tx_crc_crc_next[30] <= ((((core_tx_crc_crc_prev[22] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); + core_tx_crc_crc_next[31] <= ((core_tx_crc_crc_prev[23] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); end always @(*) begin - builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; - main_tx_crc_ce <= 1'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; - main_tx_crc_is_ongoing0 <= 1'd0; - main_tx_crc_is_ongoing1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; - main_tx_crc_reset <= 1'd0; - main_tx_crc_sink_ready <= 1'd0; - main_tx_crc_source_first <= 1'd0; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_data <= 8'd0; - main_tx_crc_source_payload_error <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - main_tx_crc_source_valid <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; - case (builder_txdatapath_bufferizeendpoints_state) + core_tx_crc_ce <= 1'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + core_tx_crc_is_ongoing0 <= 1'd0; + core_tx_crc_is_ongoing1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + core_tx_crc_reset <= 1'd0; + core_tx_crc_sink_ready <= 1'd0; + core_tx_crc_source_first <= 1'd0; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_data <= 8'd0; + core_tx_crc_source_payload_error <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + core_tx_crc_source_valid <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 2'd0; + txdatapath_bufferizeendpoints_next_state <= txdatapath_bufferizeendpoints_state; + case (txdatapath_bufferizeendpoints_state) 1'd1: begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); - main_tx_crc_source_valid <= main_tx_crc_sink_valid; - main_tx_crc_sink_ready <= main_tx_crc_source_ready; - main_tx_crc_source_first <= main_tx_crc_sink_first; - main_tx_crc_source_last <= main_tx_crc_sink_last; - main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; - main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; - main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; - main_tx_crc_source_last <= 1'd0; - main_tx_crc_source_payload_last_be <= 1'd0; - if (main_tx_crc_sink_last) begin - if (main_tx_crc_sink_payload_last_be) begin - main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + core_tx_crc_ce <= (core_tx_crc_sink_valid & core_tx_crc_source_ready); + core_tx_crc_source_valid <= core_tx_crc_sink_valid; + core_tx_crc_sink_ready <= core_tx_crc_source_ready; + core_tx_crc_source_first <= core_tx_crc_sink_first; + core_tx_crc_source_last <= core_tx_crc_sink_last; + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; + core_tx_crc_source_payload_last_be <= core_tx_crc_sink_payload_last_be; + core_tx_crc_source_payload_error <= core_tx_crc_sink_payload_error; + core_tx_crc_source_last <= 1'd0; + core_tx_crc_source_payload_last_be <= 1'd0; + if (core_tx_crc_sink_last) begin + if (core_tx_crc_sink_payload_last_be) begin + core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; end - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - main_tx_crc_source_last <= 1'd1; - main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + core_tx_crc_source_last <= 1'd1; + core_tx_crc_source_payload_last_be <= (core_tx_crc_sink_payload_last_be <<< -3'd3); end - end else begin - main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); end - if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin - if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (((core_tx_crc_sink_valid & core_tx_crc_sink_last) & core_tx_crc_source_ready)) begin + if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end else begin - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; - main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= core_tx_crc_value; + core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; if (1'd0) begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (core_tx_crc_sink_payload_last_be >>> 3'd4); + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end else begin - main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; - main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= core_tx_crc_sink_payload_last_be; + core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end - builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + txdatapath_bufferizeendpoints_next_state <= 2'd2; end end end 2'd2: begin - main_tx_crc_source_valid <= 1'd1; - case (main_tx_crc_cnt) + core_tx_crc_source_valid <= 1'd1; + case (core_tx_crc_cnt) 1'd0: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[31:24]; end 1'd1: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[23:16]; end 2'd2: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[15:8]; end default: begin - main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[7:0]; end endcase - if (main_tx_crc_cnt_done) begin - main_tx_crc_source_last <= 1'd1; - if (main_tx_crc_source_ready) begin - builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_tx_crc_cnt_done) begin + core_tx_crc_source_last <= 1'd1; + if (core_tx_crc_source_ready) begin + txdatapath_bufferizeendpoints_next_state <= 1'd0; end end - main_tx_crc_is_ongoing1 <= 1'd1; + core_tx_crc_is_ongoing1 <= 1'd1; end default: begin - main_tx_crc_reset <= 1'd1; - main_tx_crc_sink_ready <= 1'd1; - if (main_tx_crc_sink_valid) begin - main_tx_crc_sink_ready <= 1'd0; - builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + core_tx_crc_reset <= 1'd1; + core_tx_crc_sink_ready <= 1'd1; + if (core_tx_crc_sink_valid) begin + core_tx_crc_sink_ready <= 1'd0; + txdatapath_bufferizeendpoints_next_state <= 1'd1; end - main_tx_crc_is_ongoing0 <= 1'd1; + core_tx_crc_is_ongoing0 <= 1'd1; end endcase end -assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); -assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; -assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; -assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; -assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; -assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; -assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; -assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; -assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; -assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; -assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; -assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; -assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; -assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; -assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; -assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_ready = ((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready); +assign core_tx_crc_pipe_valid_sink_valid = core_tx_crc_sink_sink_valid; +assign core_tx_crc_sink_sink_ready = core_tx_crc_pipe_valid_sink_ready; +assign core_tx_crc_pipe_valid_sink_first = core_tx_crc_sink_sink_first; +assign core_tx_crc_pipe_valid_sink_last = core_tx_crc_sink_sink_last; +assign core_tx_crc_pipe_valid_sink_payload_data = core_tx_crc_sink_sink_payload_data; +assign core_tx_crc_pipe_valid_sink_payload_last_be = core_tx_crc_sink_sink_payload_last_be; +assign core_tx_crc_pipe_valid_sink_payload_error = core_tx_crc_sink_sink_payload_error; +assign core_tx_crc_source_source_valid = core_tx_crc_pipe_valid_source_valid; +assign core_tx_crc_pipe_valid_source_ready = core_tx_crc_source_source_ready; +assign core_tx_crc_source_source_first = core_tx_crc_pipe_valid_source_first; +assign core_tx_crc_source_source_last = core_tx_crc_pipe_valid_source_last; +assign core_tx_crc_source_source_payload_data = core_tx_crc_pipe_valid_source_payload_data; +assign core_tx_crc_source_source_payload_last_be = core_tx_crc_pipe_valid_source_payload_last_be; +assign core_tx_crc_source_source_payload_error = core_tx_crc_pipe_valid_source_payload_error; +assign core_tx_preamble_source_payload_last_be = core_tx_preamble_sink_payload_last_be; always @(*) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; - main_tx_preamble_sink_ready <= 1'd0; - main_tx_preamble_source_first <= 1'd0; - main_tx_preamble_source_last <= 1'd0; - main_tx_preamble_source_payload_data <= 8'd0; - main_tx_preamble_source_payload_error <= 1'd0; - main_tx_preamble_source_valid <= 1'd0; - main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; - builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; - case (builder_txdatapath_liteethmacpreambleinserter_state) + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + core_tx_preamble_sink_ready <= 1'd0; + core_tx_preamble_source_first <= 1'd0; + core_tx_preamble_source_last <= 1'd0; + core_tx_preamble_source_payload_data <= 8'd0; + core_tx_preamble_source_payload_error <= 1'd0; + core_tx_preamble_source_valid <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + core_tx_preamble_source_payload_data <= core_tx_preamble_sink_payload_data; + txdatapath_liteethmacpreambleinserter_next_state <= txdatapath_liteethmacpreambleinserter_state; + case (txdatapath_liteethmacpreambleinserter_state) 1'd1: begin - main_tx_preamble_source_valid <= 1'd1; - case (main_tx_preamble_count) + core_tx_preamble_source_valid <= 1'd1; + case (core_tx_preamble_count) 1'd0: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[7:0]; end 1'd1: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[15:8]; end 2'd2: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[23:16]; end 2'd3: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[31:24]; end 3'd4: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[39:32]; end 3'd5: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[47:40]; end 3'd6: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[55:48]; end default: begin - main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[63:56]; end endcase - if (main_tx_preamble_source_ready) begin - if ((main_tx_preamble_count == 3'd7)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + if (core_tx_preamble_source_ready) begin + if ((core_tx_preamble_count == 3'd7)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; end else begin - main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= (core_tx_preamble_count + 1'd1); + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; end end end 2'd2: begin - main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; - main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; - main_tx_preamble_source_first <= main_tx_preamble_sink_first; - main_tx_preamble_source_last <= main_tx_preamble_sink_last; - main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; - if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + core_tx_preamble_source_valid <= core_tx_preamble_sink_valid; + core_tx_preamble_sink_ready <= core_tx_preamble_source_ready; + core_tx_preamble_source_first <= core_tx_preamble_sink_first; + core_tx_preamble_source_last <= core_tx_preamble_sink_last; + core_tx_preamble_source_payload_error <= core_tx_preamble_sink_payload_error; + if (((core_tx_preamble_sink_valid & core_tx_preamble_sink_last) & core_tx_preamble_source_ready)) begin + txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; end end default: begin - main_tx_preamble_sink_ready <= 1'd1; - main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; - main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; - if (main_tx_preamble_sink_valid) begin - main_tx_preamble_sink_ready <= 1'd0; - builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + core_tx_preamble_sink_ready <= 1'd1; + core_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (core_tx_preamble_sink_valid) begin + core_tx_preamble_sink_ready <= 1'd0; + txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; end end endcase end always @(*) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; - main_tx_gap_sink_ready <= 1'd0; - main_tx_gap_source_first <= 1'd0; - main_tx_gap_source_last <= 1'd0; - main_tx_gap_source_payload_data <= 8'd0; - main_tx_gap_source_payload_error <= 1'd0; - main_tx_gap_source_payload_last_be <= 1'd0; - main_tx_gap_source_valid <= 1'd0; - builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; - case (builder_txdatapath_liteethmacgap_state) + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + core_tx_gap_sink_ready <= 1'd0; + core_tx_gap_source_first <= 1'd0; + core_tx_gap_source_last <= 1'd0; + core_tx_gap_source_payload_data <= 8'd0; + core_tx_gap_source_payload_error <= 1'd0; + core_tx_gap_source_payload_last_be <= 1'd0; + core_tx_gap_source_valid <= 1'd0; + txdatapath_liteethmacgap_next_state <= 1'd0; + txdatapath_liteethmacgap_next_state <= txdatapath_liteethmacgap_state; + case (txdatapath_liteethmacgap_state) 1'd1: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - if ((main_tx_gap_counter == 4'd11)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= (core_tx_gap_counter + 1'd1); + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((core_tx_gap_counter == 4'd11)) begin + txdatapath_liteethmacgap_next_state <= 1'd0; end end default: begin - main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; - main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; - main_tx_gap_source_valid <= main_tx_gap_sink_valid; - main_tx_gap_sink_ready <= main_tx_gap_source_ready; - main_tx_gap_source_first <= main_tx_gap_sink_first; - main_tx_gap_source_last <= main_tx_gap_sink_last; - main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; - main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; - main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; - if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin - builder_txdatapath_liteethmacgap_next_state <= 1'd1; + core_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + core_tx_gap_source_valid <= core_tx_gap_sink_valid; + core_tx_gap_sink_ready <= core_tx_gap_source_ready; + core_tx_gap_source_first <= core_tx_gap_sink_first; + core_tx_gap_source_last <= core_tx_gap_sink_last; + core_tx_gap_source_payload_data <= core_tx_gap_sink_payload_data; + core_tx_gap_source_payload_last_be <= core_tx_gap_sink_payload_last_be; + core_tx_gap_source_payload_error <= core_tx_gap_sink_payload_error; + if (((core_tx_gap_sink_valid & core_tx_gap_sink_last) & core_tx_gap_sink_ready)) begin + txdatapath_liteethmacgap_next_state <= 1'd1; end end endcase end -assign main_tx_cdc_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_sink_first; -assign main_tx_cdc_sink_sink_last = main_sink_last; -assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; -assign main_tx_padding_sink_first = main_tx_last_be_source_first; -assign main_tx_padding_sink_last = main_tx_last_be_source_last; -assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; -assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; -assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; -assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; -assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; -assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; -assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; -assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; -assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; -assign main_tx_preamble_sink_first = main_tx_crc_source_first; -assign main_tx_preamble_sink_last = main_tx_crc_source_last; -assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; -assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; -assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; -assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; -assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; -assign main_tx_gap_sink_first = main_tx_preamble_source_first; -assign main_tx_gap_sink_last = main_tx_preamble_source_last; -assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; -assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; -assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; -assign main_maccore_ethphy_sink_sink_valid = main_tx_gap_source_valid; -assign main_tx_gap_source_ready = main_maccore_ethphy_sink_sink_ready; -assign main_maccore_ethphy_sink_sink_first = main_tx_gap_source_first; -assign main_maccore_ethphy_sink_sink_last = main_tx_gap_source_last; -assign main_maccore_ethphy_sink_sink_payload_data = main_tx_gap_source_payload_data; -assign main_maccore_ethphy_sink_sink_payload_last_be = main_tx_gap_source_payload_last_be; -assign main_maccore_ethphy_sink_sink_payload_error = main_tx_gap_source_payload_error; -assign main_pulsesynchronizer0_i = main_rx_preamble_error; -assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; -assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; -assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +assign core_tx_cdc_sink_sink_valid = core_sink_valid; +assign core_sink_ready = core_tx_cdc_sink_sink_ready; +assign core_tx_cdc_sink_sink_first = core_sink_first; +assign core_tx_cdc_sink_sink_last = core_sink_last; +assign core_tx_cdc_sink_sink_payload_data = core_sink_payload_data; +assign core_tx_cdc_sink_sink_payload_last_be = core_sink_payload_last_be; +assign core_tx_cdc_sink_sink_payload_error = core_sink_payload_error; +assign core_tx_converter_sink_valid = core_tx_cdc_source_source_valid; +assign core_tx_cdc_source_source_ready = core_tx_converter_sink_ready; +assign core_tx_converter_sink_first = core_tx_cdc_source_source_first; +assign core_tx_converter_sink_last = core_tx_cdc_source_source_last; +assign core_tx_converter_sink_payload_data = core_tx_cdc_source_source_payload_data; +assign core_tx_converter_sink_payload_last_be = core_tx_cdc_source_source_payload_last_be; +assign core_tx_converter_sink_payload_error = core_tx_cdc_source_source_payload_error; +assign core_tx_last_be_sink_sink_valid = core_tx_converter_source_valid; +assign core_tx_converter_source_ready = core_tx_last_be_sink_sink_ready; +assign core_tx_last_be_sink_sink_first = core_tx_converter_source_first; +assign core_tx_last_be_sink_sink_last = core_tx_converter_source_last; +assign core_tx_last_be_sink_sink_payload_data = core_tx_converter_source_payload_data; +assign core_tx_last_be_sink_sink_payload_last_be = core_tx_converter_source_payload_last_be; +assign core_tx_last_be_sink_sink_payload_error = core_tx_converter_source_payload_error; +assign core_tx_padding_sink_valid = core_tx_last_be_source_source_valid; +assign core_tx_last_be_source_source_ready = core_tx_padding_sink_ready; +assign core_tx_padding_sink_first = core_tx_last_be_source_source_first; +assign core_tx_padding_sink_last = core_tx_last_be_source_source_last; +assign core_tx_padding_sink_payload_data = core_tx_last_be_source_source_payload_data; +assign core_tx_padding_sink_payload_last_be = core_tx_last_be_source_source_payload_last_be; +assign core_tx_padding_sink_payload_error = core_tx_last_be_source_source_payload_error; +assign core_tx_crc_sink_sink_valid = core_tx_padding_source_valid; +assign core_tx_padding_source_ready = core_tx_crc_sink_sink_ready; +assign core_tx_crc_sink_sink_first = core_tx_padding_source_first; +assign core_tx_crc_sink_sink_last = core_tx_padding_source_last; +assign core_tx_crc_sink_sink_payload_data = core_tx_padding_source_payload_data; +assign core_tx_crc_sink_sink_payload_last_be = core_tx_padding_source_payload_last_be; +assign core_tx_crc_sink_sink_payload_error = core_tx_padding_source_payload_error; +assign core_tx_preamble_sink_valid = core_tx_crc_source_valid; +assign core_tx_crc_source_ready = core_tx_preamble_sink_ready; +assign core_tx_preamble_sink_first = core_tx_crc_source_first; +assign core_tx_preamble_sink_last = core_tx_crc_source_last; +assign core_tx_preamble_sink_payload_data = core_tx_crc_source_payload_data; +assign core_tx_preamble_sink_payload_last_be = core_tx_crc_source_payload_last_be; +assign core_tx_preamble_sink_payload_error = core_tx_crc_source_payload_error; +assign core_tx_gap_sink_valid = core_tx_preamble_source_valid; +assign core_tx_preamble_source_ready = core_tx_gap_sink_ready; +assign core_tx_gap_sink_first = core_tx_preamble_source_first; +assign core_tx_gap_sink_last = core_tx_preamble_source_last; +assign core_tx_gap_sink_payload_data = core_tx_preamble_source_payload_data; +assign core_tx_gap_sink_payload_last_be = core_tx_preamble_source_payload_last_be; +assign core_tx_gap_sink_payload_error = core_tx_preamble_source_payload_error; +assign maccore_ethphy_sink_sink_valid = core_tx_gap_source_valid; +assign core_tx_gap_source_ready = maccore_ethphy_sink_sink_ready; +assign maccore_ethphy_sink_sink_first = core_tx_gap_source_first; +assign maccore_ethphy_sink_sink_last = core_tx_gap_source_last; +assign maccore_ethphy_sink_sink_payload_data = core_tx_gap_source_payload_data; +assign maccore_ethphy_sink_sink_payload_last_be = core_tx_gap_source_payload_last_be; +assign maccore_ethphy_sink_sink_payload_error = core_tx_gap_source_payload_error; +assign core_pulsesynchronizer0_i = core_rx_preamble_error; +assign core_pulsesynchronizer1_i = core_liteethmaccrc32checker_error; +assign core_rx_preamble_source_payload_data = core_rx_preamble_sink_payload_data; +assign core_rx_preamble_source_payload_last_be = core_rx_preamble_sink_payload_last_be; always @(*) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; - main_rx_preamble_error <= 1'd0; - main_rx_preamble_sink_ready <= 1'd0; - main_rx_preamble_source_first <= 1'd0; - main_rx_preamble_source_last <= 1'd0; - main_rx_preamble_source_payload_error <= 1'd0; - main_rx_preamble_source_valid <= 1'd0; - builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; - case (builder_rxdatapath_liteethmacpreamblechecker_state) + core_rx_preamble_error <= 1'd0; + core_rx_preamble_sink_ready <= 1'd0; + core_rx_preamble_source_first <= 1'd0; + core_rx_preamble_source_last <= 1'd0; + core_rx_preamble_source_payload_error <= 1'd0; + core_rx_preamble_source_valid <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + rxdatapath_liteethmacpreamblechecker_next_state <= rxdatapath_liteethmacpreamblechecker_state; + case (rxdatapath_liteethmacpreamblechecker_state) 1'd1: begin - main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; - main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; - main_rx_preamble_source_first <= main_rx_preamble_sink_first; - main_rx_preamble_source_last <= main_rx_preamble_sink_last; - main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; - if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + core_rx_preamble_source_valid <= core_rx_preamble_sink_valid; + core_rx_preamble_sink_ready <= core_rx_preamble_source_ready; + core_rx_preamble_source_first <= core_rx_preamble_sink_first; + core_rx_preamble_source_last <= core_rx_preamble_sink_last; + core_rx_preamble_source_payload_error <= core_rx_preamble_sink_payload_error; + if (((core_rx_preamble_source_valid & core_rx_preamble_source_last) & core_rx_preamble_source_ready)) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; end end default: begin - main_rx_preamble_sink_ready <= 1'd1; - if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin - builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + core_rx_preamble_sink_ready <= 1'd1; + if (((core_rx_preamble_sink_valid & (~core_rx_preamble_sink_last)) & (core_rx_preamble_sink_payload_data == core_rx_preamble_preamble[63:56]))) begin + rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; end - if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin - main_rx_preamble_error <= 1'd1; + if ((core_rx_preamble_sink_valid & core_rx_preamble_sink_last)) begin + core_rx_preamble_error <= 1'd1; end end endcase end -assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); -assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); -assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); -assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); -assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; -assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +assign core_pulsesynchronizer0_o = (core_pulsesynchronizer0_toggle_o ^ core_pulsesynchronizer0_toggle_o_r); +assign core_liteethmaccrc32checker_fifo_full = (core_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign core_liteethmaccrc32checker_fifo_in = (core_liteethmaccrc32checker_sink_sink_valid & ((~core_liteethmaccrc32checker_fifo_full) | core_liteethmaccrc32checker_fifo_out)); +assign core_liteethmaccrc32checker_fifo_out = (core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready); +assign core_liteethmaccrc32checker_syncfifo_sink_first = core_liteethmaccrc32checker_sink_sink_first; +assign core_liteethmaccrc32checker_syncfifo_sink_last = core_liteethmaccrc32checker_sink_sink_last; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_data = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_last_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_sink_payload_error = core_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; + core_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_sink_sink_valid; + core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_fifo_in; end always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + core_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_syncfifo_sink_ready; + core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; -assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; -assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; -assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; -assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +assign core_liteethmaccrc32checker_crc_data0 = core_liteethmaccrc32checker_sink_sink_payload_data; +assign core_liteethmaccrc32checker_crc_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; +assign core_liteethmaccrc32checker_source_source_first = core_liteethmaccrc32checker_syncfifo_source_first; +assign core_liteethmaccrc32checker_source_source_payload_data = core_liteethmaccrc32checker_syncfifo_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_valid = core_bufferizeendpoints_source_source_valid; +assign core_bufferizeendpoints_source_source_ready = core_liteethmaccrc32checker_sink_sink_ready; +assign core_liteethmaccrc32checker_sink_sink_first = core_bufferizeendpoints_source_source_first; +assign core_liteethmaccrc32checker_sink_sink_last = core_bufferizeendpoints_source_source_last; +assign core_liteethmaccrc32checker_sink_sink_payload_data = core_bufferizeendpoints_source_source_payload_data; +assign core_liteethmaccrc32checker_sink_sink_payload_last_be = core_bufferizeendpoints_source_source_payload_last_be; +assign core_liteethmaccrc32checker_sink_sink_payload_error = core_bufferizeendpoints_source_source_payload_error; +assign core_liteethmaccrc32checker_crc_data1 = core_liteethmaccrc32checker_crc_data0; +assign core_liteethmaccrc32checker_crc_crc_prev = core_liteethmaccrc32checker_crc_reg; always @(*) begin - main_liteethmaccrc32checker_crc_error0 <= 1'd0; - main_liteethmaccrc32checker_crc_value <= 32'd0; - if (main_liteethmaccrc32checker_crc_be) begin - main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; - main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + core_liteethmaccrc32checker_crc_error0 <= 1'd0; + core_liteethmaccrc32checker_crc_value <= 32'd0; + if (core_liteethmaccrc32checker_crc_be) begin + core_liteethmaccrc32checker_crc_value <= ({core_liteethmaccrc32checker_crc_crc_next[0], core_liteethmaccrc32checker_crc_crc_next[1], core_liteethmaccrc32checker_crc_crc_next[2], core_liteethmaccrc32checker_crc_crc_next[3], core_liteethmaccrc32checker_crc_crc_next[4], core_liteethmaccrc32checker_crc_crc_next[5], core_liteethmaccrc32checker_crc_crc_next[6], core_liteethmaccrc32checker_crc_crc_next[7], core_liteethmaccrc32checker_crc_crc_next[8], core_liteethmaccrc32checker_crc_crc_next[9], core_liteethmaccrc32checker_crc_crc_next[10], core_liteethmaccrc32checker_crc_crc_next[11], core_liteethmaccrc32checker_crc_crc_next[12], core_liteethmaccrc32checker_crc_crc_next[13], core_liteethmaccrc32checker_crc_crc_next[14], core_liteethmaccrc32checker_crc_crc_next[15], core_liteethmaccrc32checker_crc_crc_next[16], core_liteethmaccrc32checker_crc_crc_next[17], core_liteethmaccrc32checker_crc_crc_next[18], core_liteethmaccrc32checker_crc_crc_next[19], core_liteethmaccrc32checker_crc_crc_next[20], core_liteethmaccrc32checker_crc_crc_next[21], core_liteethmaccrc32checker_crc_crc_next[22], core_liteethmaccrc32checker_crc_crc_next[23], core_liteethmaccrc32checker_crc_crc_next[24], core_liteethmaccrc32checker_crc_crc_next[25], core_liteethmaccrc32checker_crc_crc_next[26], core_liteethmaccrc32checker_crc_crc_next[27], core_liteethmaccrc32checker_crc_crc_next[28], core_liteethmaccrc32checker_crc_crc_next[29], core_liteethmaccrc32checker_crc_crc_next[30], core_liteethmaccrc32checker_crc_crc_next[31]} ^ 32'd4294967295); + core_liteethmaccrc32checker_crc_error0 <= (core_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); end end always @(*) begin - main_liteethmaccrc32checker_crc_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next <= 32'd0; + core_liteethmaccrc32checker_crc_crc_next[0] <= (((core_liteethmaccrc32checker_crc_crc_prev[24] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[1] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[25] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[26] ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[3] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[27] ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[28] ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((core_liteethmaccrc32checker_crc_crc_prev[29] ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((core_liteethmaccrc32checker_crc_crc_prev[30] ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[31] ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[0] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[1] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[2] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[3] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[4] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[5] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((core_liteethmaccrc32checker_crc_crc_prev[6] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[7] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[16] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[8] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[17] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[9] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[18] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[10] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[19] <= ((((core_liteethmaccrc32checker_crc_crc_prev[11] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[20] <= ((core_liteethmaccrc32checker_crc_crc_prev[12] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[21] <= ((core_liteethmaccrc32checker_crc_crc_prev[13] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); + core_liteethmaccrc32checker_crc_crc_next[22] <= ((core_liteethmaccrc32checker_crc_crc_prev[14] ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[23] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[15] ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[24] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[16] ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[25] <= ((((core_liteethmaccrc32checker_crc_crc_prev[17] ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[18] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); + core_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[19] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); + core_liteethmaccrc32checker_crc_crc_next[28] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[20] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); + core_liteethmaccrc32checker_crc_crc_next[29] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[21] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); + core_liteethmaccrc32checker_crc_crc_next[30] <= ((((core_liteethmaccrc32checker_crc_crc_prev[22] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); + core_liteethmaccrc32checker_crc_crc_next[31] <= ((core_liteethmaccrc32checker_crc_crc_prev[23] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); end -assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; -assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; -assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; -assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; -assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_din = {core_liteethmaccrc32checker_syncfifo_fifo_in_last, core_liteethmaccrc32checker_syncfifo_fifo_in_first, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {core_liteethmaccrc32checker_syncfifo_fifo_out_last, core_liteethmaccrc32checker_syncfifo_fifo_out_first, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = core_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign core_liteethmaccrc32checker_syncfifo_sink_ready = core_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_we = core_liteethmaccrc32checker_syncfifo_sink_valid; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_first = core_liteethmaccrc32checker_syncfifo_sink_first; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_last = core_liteethmaccrc32checker_syncfifo_sink_last; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = core_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = core_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign core_liteethmaccrc32checker_syncfifo_source_valid = core_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign core_liteethmaccrc32checker_syncfifo_source_first = core_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign core_liteethmaccrc32checker_syncfifo_source_last = core_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign core_liteethmaccrc32checker_syncfifo_source_payload_data = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign core_liteethmaccrc32checker_syncfifo_source_payload_last_be = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign core_liteethmaccrc32checker_syncfifo_source_payload_error = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_re = core_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + core_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (core_liteethmaccrc32checker_syncfifo_replace) begin + core_liteethmaccrc32checker_syncfifo_wrport_adr <= (core_liteethmaccrc32checker_syncfifo_produce - 1'd1); end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + core_liteethmaccrc32checker_syncfifo_wrport_adr <= core_liteethmaccrc32checker_syncfifo_produce; end end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; -assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); -assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); -assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); -assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_w = core_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign core_liteethmaccrc32checker_syncfifo_wrport_we = (core_liteethmaccrc32checker_syncfifo_syncfifo_we & (core_liteethmaccrc32checker_syncfifo_syncfifo_writable | core_liteethmaccrc32checker_syncfifo_replace)); +assign core_liteethmaccrc32checker_syncfifo_do_read = (core_liteethmaccrc32checker_syncfifo_syncfifo_readable & core_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign core_liteethmaccrc32checker_syncfifo_rdport_adr = core_liteethmaccrc32checker_syncfifo_consume; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_dout = core_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign core_liteethmaccrc32checker_syncfifo_syncfifo_writable = (core_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign core_liteethmaccrc32checker_syncfifo_syncfifo_readable = (core_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - main_liteethmaccrc32checker_error <= 1'd0; - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; - main_liteethmaccrc32checker_source_source_last <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; - main_liteethmaccrc32checker_source_source_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; - case (builder_rxdatapath_bufferizeendpoints_state) + core_liteethmaccrc32checker_crc_ce <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + core_liteethmaccrc32checker_crc_reset <= 1'd0; + core_liteethmaccrc32checker_error <= 1'd0; + core_liteethmaccrc32checker_fifo_reset <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + core_liteethmaccrc32checker_source_source_last <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + core_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= 1'd0; + core_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + rxdatapath_bufferizeendpoints_next_state <= 2'd0; + core_liteethmaccrc32checker_source_source_payload_error <= core_liteethmaccrc32checker_syncfifo_source_payload_error; + rxdatapath_bufferizeendpoints_next_state <= rxdatapath_bufferizeendpoints_state; + case (rxdatapath_bufferizeendpoints_state) 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 2'd2; end end 2'd2: begin - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; - main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_fifo_out; + core_liteethmaccrc32checker_source_source_valid <= (core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_fifo_full); if (1'd1) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_sink_sink_payload_last_be; end else begin - if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; - main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + if ((core_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; + core_liteethmaccrc32checker_source_source_payload_last_be <= (core_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); end else begin - main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); - main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; - main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; - main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + core_liteethmaccrc32checker_last_be_next_value0 <= (core_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + core_liteethmaccrc32checker_crc_error1_next_value1 <= core_liteethmaccrc32checker_crc_error0; + core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; end end - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); - main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_sink_sink_payload_error | {1{(core_liteethmaccrc32checker_crc_error0 & core_liteethmaccrc32checker_sink_sink_last)}}); + core_liteethmaccrc32checker_error <= ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_last) & core_liteethmaccrc32checker_crc_error0); + if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin + core_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((core_liteethmaccrc32checker_sink_sink_last & (core_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + rxdatapath_bufferizeendpoints_next_state <= 2'd3; end else begin - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + if (core_liteethmaccrc32checker_sink_sink_last) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end end end 2'd3: begin - main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; - main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; - main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); - main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; - if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + core_liteethmaccrc32checker_source_source_valid <= core_liteethmaccrc32checker_syncfifo_source_valid; + core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_source_source_ready; + core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_syncfifo_source_last; + core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_syncfifo_source_payload_error | {1{core_liteethmaccrc32checker_crc_error1}}); + core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_last_be; + if ((core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready)) begin + rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + core_liteethmaccrc32checker_crc_reset <= 1'd1; + core_liteethmaccrc32checker_fifo_reset <= 1'd1; + rxdatapath_bufferizeendpoints_next_state <= 1'd1; end endcase end -assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); -assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; -assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; -assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; -assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; -assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; -assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; -assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; -assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; -assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; -assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; -assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; -assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; -assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; -assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; -assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); -assign main_rx_padding_source_valid = main_rx_padding_sink_valid; -assign main_rx_padding_sink_ready = main_rx_padding_source_ready; -assign main_rx_padding_source_first = main_rx_padding_sink_first; -assign main_rx_padding_source_last = main_rx_padding_sink_last; -assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; -assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; -assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; -assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; -assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; -assign main_rx_last_be_source_first = main_rx_last_be_sink_first; -assign main_rx_last_be_source_last = main_rx_last_be_sink_last; -assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; -assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +assign core_bufferizeendpoints_pipe_valid_sink_ready = ((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready); +assign core_bufferizeendpoints_pipe_valid_sink_valid = core_bufferizeendpoints_sink_sink_valid; +assign core_bufferizeendpoints_sink_sink_ready = core_bufferizeendpoints_pipe_valid_sink_ready; +assign core_bufferizeendpoints_pipe_valid_sink_first = core_bufferizeendpoints_sink_sink_first; +assign core_bufferizeendpoints_pipe_valid_sink_last = core_bufferizeendpoints_sink_sink_last; +assign core_bufferizeendpoints_pipe_valid_sink_payload_data = core_bufferizeendpoints_sink_sink_payload_data; +assign core_bufferizeendpoints_pipe_valid_sink_payload_last_be = core_bufferizeendpoints_sink_sink_payload_last_be; +assign core_bufferizeendpoints_pipe_valid_sink_payload_error = core_bufferizeendpoints_sink_sink_payload_error; +assign core_bufferizeendpoints_source_source_valid = core_bufferizeendpoints_pipe_valid_source_valid; +assign core_bufferizeendpoints_pipe_valid_source_ready = core_bufferizeendpoints_source_source_ready; +assign core_bufferizeendpoints_source_source_first = core_bufferizeendpoints_pipe_valid_source_first; +assign core_bufferizeendpoints_source_source_last = core_bufferizeendpoints_pipe_valid_source_last; +assign core_bufferizeendpoints_source_source_payload_data = core_bufferizeendpoints_pipe_valid_source_payload_data; +assign core_bufferizeendpoints_source_source_payload_last_be = core_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign core_bufferizeendpoints_source_source_payload_error = core_bufferizeendpoints_pipe_valid_source_payload_error; +assign core_pulsesynchronizer1_o = (core_pulsesynchronizer1_toggle_o ^ core_pulsesynchronizer1_toggle_o_r); +assign core_rx_padding_source_valid = core_rx_padding_sink_valid; +assign core_rx_padding_sink_ready = core_rx_padding_source_ready; +assign core_rx_padding_source_first = core_rx_padding_sink_first; +assign core_rx_padding_source_last = core_rx_padding_sink_last; +assign core_rx_padding_source_payload_data = core_rx_padding_sink_payload_data; +assign core_rx_padding_source_payload_last_be = core_rx_padding_sink_payload_last_be; +assign core_rx_padding_source_payload_error = core_rx_padding_sink_payload_error; +assign core_rx_last_be_source_valid = core_rx_last_be_sink_valid; +assign core_rx_last_be_sink_ready = core_rx_last_be_source_ready; +assign core_rx_last_be_source_first = core_rx_last_be_sink_first; +assign core_rx_last_be_source_last = core_rx_last_be_sink_last; +assign core_rx_last_be_source_payload_data = core_rx_last_be_sink_payload_data; +assign core_rx_last_be_source_payload_error = core_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + core_rx_last_be_source_payload_last_be <= 1'd0; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_payload_last_be; if (1'd1) begin - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_last; end end -assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; -assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; -assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; -assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; -assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; -assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; -assign main_rx_converter_source_first = main_rx_converter_source_source_first; -assign main_rx_converter_source_last = main_rx_converter_source_source_last; -assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +assign core_rx_converter_converter_sink_valid = core_rx_converter_sink_valid; +assign core_rx_converter_converter_sink_first = core_rx_converter_sink_first; +assign core_rx_converter_converter_sink_last = core_rx_converter_sink_last; +assign core_rx_converter_sink_ready = core_rx_converter_converter_sink_ready; +assign core_rx_converter_converter_sink_payload_data = {core_rx_converter_sink_payload_error, core_rx_converter_sink_payload_last_be, core_rx_converter_sink_payload_data}; +assign core_rx_converter_source_valid = core_rx_converter_source_source_valid; +assign core_rx_converter_source_first = core_rx_converter_source_source_first; +assign core_rx_converter_source_last = core_rx_converter_source_source_last; +assign core_rx_converter_source_source_ready = core_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + core_rx_converter_source_payload_data <= 32'd0; + core_rx_converter_source_payload_data[7:0] <= core_rx_converter_source_source_payload_data[7:0]; + core_rx_converter_source_payload_data[15:8] <= core_rx_converter_source_source_payload_data[17:10]; + core_rx_converter_source_payload_data[23:16] <= core_rx_converter_source_source_payload_data[27:20]; + core_rx_converter_source_payload_data[31:24] <= core_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + core_rx_converter_source_payload_last_be <= 4'd0; + core_rx_converter_source_payload_last_be[0] <= core_rx_converter_source_source_payload_data[8]; + core_rx_converter_source_payload_last_be[1] <= core_rx_converter_source_source_payload_data[18]; + core_rx_converter_source_payload_last_be[2] <= core_rx_converter_source_source_payload_data[28]; + core_rx_converter_source_payload_last_be[3] <= core_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + core_rx_converter_source_payload_error <= 4'd0; + core_rx_converter_source_payload_error[0] <= core_rx_converter_source_source_payload_data[9]; + core_rx_converter_source_payload_error[1] <= core_rx_converter_source_source_payload_data[19]; + core_rx_converter_source_payload_error[2] <= core_rx_converter_source_source_payload_data[29]; + core_rx_converter_source_payload_error[3] <= core_rx_converter_source_source_payload_data[39]; end -assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; -assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; -assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; -assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; -assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; -assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); -assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; -assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; -assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; -assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; -assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; -assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; -assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; -assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; -assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; -assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; -assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; -assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; -assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; -assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; -assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; -assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; -assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; -assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; -assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; -assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; -assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; -assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; -assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; -assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; -assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; -assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; -assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; -assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; -assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; -assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; -assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; -assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); -assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); -assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); -assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); -assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; -assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; -assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +assign core_rx_converter_source_source_valid = core_rx_converter_converter_source_valid; +assign core_rx_converter_converter_source_ready = core_rx_converter_source_source_ready; +assign core_rx_converter_source_source_first = core_rx_converter_converter_source_first; +assign core_rx_converter_source_source_last = core_rx_converter_converter_source_last; +assign core_rx_converter_source_source_payload_data = core_rx_converter_converter_source_payload_data; +assign core_rx_converter_converter_sink_ready = ((~core_rx_converter_converter_strobe_all) | core_rx_converter_converter_source_ready); +assign core_rx_converter_converter_source_valid = core_rx_converter_converter_strobe_all; +assign core_rx_converter_converter_load_part = (core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready); +assign core_rx_cdc_cdc_sink_valid = core_rx_cdc_sink_sink_valid; +assign core_rx_cdc_sink_sink_ready = core_rx_cdc_cdc_sink_ready; +assign core_rx_cdc_cdc_sink_first = core_rx_cdc_sink_sink_first; +assign core_rx_cdc_cdc_sink_last = core_rx_cdc_sink_sink_last; +assign core_rx_cdc_cdc_sink_payload_data = core_rx_cdc_sink_sink_payload_data; +assign core_rx_cdc_cdc_sink_payload_last_be = core_rx_cdc_sink_sink_payload_last_be; +assign core_rx_cdc_cdc_sink_payload_error = core_rx_cdc_sink_sink_payload_error; +assign core_rx_cdc_source_source_valid = core_rx_cdc_cdc_source_valid; +assign core_rx_cdc_cdc_source_ready = core_rx_cdc_source_source_ready; +assign core_rx_cdc_source_source_first = core_rx_cdc_cdc_source_first; +assign core_rx_cdc_source_source_last = core_rx_cdc_cdc_source_last; +assign core_rx_cdc_source_source_payload_data = core_rx_cdc_cdc_source_payload_data; +assign core_rx_cdc_source_source_payload_last_be = core_rx_cdc_cdc_source_payload_last_be; +assign core_rx_cdc_source_source_payload_error = core_rx_cdc_cdc_source_payload_error; +assign core_rx_cdc_cdc_asyncfifo_din = {core_rx_cdc_cdc_fifo_in_last, core_rx_cdc_cdc_fifo_in_first, core_rx_cdc_cdc_fifo_in_payload_error, core_rx_cdc_cdc_fifo_in_payload_last_be, core_rx_cdc_cdc_fifo_in_payload_data}; +assign {core_rx_cdc_cdc_fifo_out_last, core_rx_cdc_cdc_fifo_out_first, core_rx_cdc_cdc_fifo_out_payload_error, core_rx_cdc_cdc_fifo_out_payload_last_be, core_rx_cdc_cdc_fifo_out_payload_data} = core_rx_cdc_cdc_asyncfifo_dout; +assign core_rx_cdc_cdc_sink_ready = core_rx_cdc_cdc_asyncfifo_writable; +assign core_rx_cdc_cdc_asyncfifo_we = core_rx_cdc_cdc_sink_valid; +assign core_rx_cdc_cdc_fifo_in_first = core_rx_cdc_cdc_sink_first; +assign core_rx_cdc_cdc_fifo_in_last = core_rx_cdc_cdc_sink_last; +assign core_rx_cdc_cdc_fifo_in_payload_data = core_rx_cdc_cdc_sink_payload_data; +assign core_rx_cdc_cdc_fifo_in_payload_last_be = core_rx_cdc_cdc_sink_payload_last_be; +assign core_rx_cdc_cdc_fifo_in_payload_error = core_rx_cdc_cdc_sink_payload_error; +assign core_rx_cdc_cdc_source_valid = core_rx_cdc_cdc_asyncfifo_readable; +assign core_rx_cdc_cdc_source_first = core_rx_cdc_cdc_fifo_out_first; +assign core_rx_cdc_cdc_source_last = core_rx_cdc_cdc_fifo_out_last; +assign core_rx_cdc_cdc_source_payload_data = core_rx_cdc_cdc_fifo_out_payload_data; +assign core_rx_cdc_cdc_source_payload_last_be = core_rx_cdc_cdc_fifo_out_payload_last_be; +assign core_rx_cdc_cdc_source_payload_error = core_rx_cdc_cdc_fifo_out_payload_error; +assign core_rx_cdc_cdc_asyncfifo_re = core_rx_cdc_cdc_source_ready; +assign core_rx_cdc_cdc_graycounter0_ce = (core_rx_cdc_cdc_asyncfifo_writable & core_rx_cdc_cdc_asyncfifo_we); +assign core_rx_cdc_cdc_graycounter1_ce = (core_rx_cdc_cdc_asyncfifo_readable & core_rx_cdc_cdc_asyncfifo_re); +assign core_rx_cdc_cdc_asyncfifo_writable = (((core_rx_cdc_cdc_graycounter0_q[5] == core_rx_cdc_cdc_consume_wdomain[5]) | (core_rx_cdc_cdc_graycounter0_q[4] == core_rx_cdc_cdc_consume_wdomain[4])) | (core_rx_cdc_cdc_graycounter0_q[3:0] != core_rx_cdc_cdc_consume_wdomain[3:0])); +assign core_rx_cdc_cdc_asyncfifo_readable = (core_rx_cdc_cdc_graycounter1_q != core_rx_cdc_cdc_produce_rdomain); +assign core_rx_cdc_cdc_wrport_adr = core_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign core_rx_cdc_cdc_wrport_dat_w = core_rx_cdc_cdc_asyncfifo_din; +assign core_rx_cdc_cdc_wrport_we = core_rx_cdc_cdc_graycounter0_ce; +assign core_rx_cdc_cdc_rdport_adr = core_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign core_rx_cdc_cdc_asyncfifo_dout = core_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter0_ce) begin + core_rx_cdc_cdc_graycounter0_q_next_binary <= (core_rx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + core_rx_cdc_cdc_graycounter0_q_next_binary <= core_rx_cdc_cdc_graycounter0_q_binary; end end -assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +assign core_rx_cdc_cdc_graycounter0_q_next = (core_rx_cdc_cdc_graycounter0_q_next_binary ^ core_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + core_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (core_rx_cdc_cdc_graycounter1_ce) begin + core_rx_cdc_cdc_graycounter1_q_next_binary <= (core_rx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + core_rx_cdc_cdc_graycounter1_q_next_binary <= core_rx_cdc_cdc_graycounter1_q_binary; end end -assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_source_valid; -assign main_maccore_ethphy_source_source_ready = main_rx_preamble_sink_ready; -assign main_rx_preamble_sink_first = main_maccore_ethphy_source_source_first; -assign main_rx_preamble_sink_last = main_maccore_ethphy_source_source_last; -assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_source_payload_data; -assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_source_payload_last_be; -assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_source_payload_error; -assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; -assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; -assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; -assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; -assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; -assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; -assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; -assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; -assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; -assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_rx_padding_source_first; -assign main_rx_last_be_sink_last = main_rx_padding_source_last; -assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; -assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; -assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; -assign main_rx_converter_sink_first = main_rx_last_be_source_first; -assign main_rx_converter_sink_last = main_rx_last_be_source_last; -assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; -assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; -assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; -assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; -assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; -assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; -assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; -assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; -assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; -assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_source_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_source_ready; -assign main_source_first = main_rx_cdc_source_source_first; -assign main_source_last = main_rx_cdc_source_source_last; -assign main_source_payload_data = main_rx_cdc_source_source_payload_data; -assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_source_payload_error = main_rx_cdc_source_source_payload_error; -assign main_sram0_sink_valid = main_sink_sink_valid; -assign main_sink_sink_ready = main_sram1_sink_ready; -assign main_sram2_sink_first = main_sink_sink_first; -assign main_sram3_sink_last = main_sink_sink_last; -assign main_sram4_sink_payload_data = main_sink_sink_payload_data; -assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; -assign main_sram6_sink_payload_error = main_sink_sink_payload_error; -assign main_source_source_valid = main_sram83_source_valid; -assign main_sram84_source_ready = main_source_source_ready; -assign main_source_source_first = main_sram85_source_first; -assign main_source_source_last = main_sram86_source_last; -assign main_source_source_payload_data = main_sram87_source_payload_data; -assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; -assign main_source_source_payload_error = main_sram89_source_payload_error; +assign core_rx_cdc_cdc_graycounter1_q_next = (core_rx_cdc_cdc_graycounter1_q_next_binary ^ core_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign core_rx_preamble_sink_valid = maccore_ethphy_source_source_valid; +assign maccore_ethphy_source_source_ready = core_rx_preamble_sink_ready; +assign core_rx_preamble_sink_first = maccore_ethphy_source_source_first; +assign core_rx_preamble_sink_last = maccore_ethphy_source_source_last; +assign core_rx_preamble_sink_payload_data = maccore_ethphy_source_source_payload_data; +assign core_rx_preamble_sink_payload_last_be = maccore_ethphy_source_source_payload_last_be; +assign core_rx_preamble_sink_payload_error = maccore_ethphy_source_source_payload_error; +assign core_bufferizeendpoints_sink_sink_valid = core_rx_preamble_source_valid; +assign core_rx_preamble_source_ready = core_bufferizeendpoints_sink_sink_ready; +assign core_bufferizeendpoints_sink_sink_first = core_rx_preamble_source_first; +assign core_bufferizeendpoints_sink_sink_last = core_rx_preamble_source_last; +assign core_bufferizeendpoints_sink_sink_payload_data = core_rx_preamble_source_payload_data; +assign core_bufferizeendpoints_sink_sink_payload_last_be = core_rx_preamble_source_payload_last_be; +assign core_bufferizeendpoints_sink_sink_payload_error = core_rx_preamble_source_payload_error; +assign core_rx_padding_sink_valid = core_liteethmaccrc32checker_source_source_valid; +assign core_liteethmaccrc32checker_source_source_ready = core_rx_padding_sink_ready; +assign core_rx_padding_sink_first = core_liteethmaccrc32checker_source_source_first; +assign core_rx_padding_sink_last = core_liteethmaccrc32checker_source_source_last; +assign core_rx_padding_sink_payload_data = core_liteethmaccrc32checker_source_source_payload_data; +assign core_rx_padding_sink_payload_last_be = core_liteethmaccrc32checker_source_source_payload_last_be; +assign core_rx_padding_sink_payload_error = core_liteethmaccrc32checker_source_source_payload_error; +assign core_rx_last_be_sink_valid = core_rx_padding_source_valid; +assign core_rx_padding_source_ready = core_rx_last_be_sink_ready; +assign core_rx_last_be_sink_first = core_rx_padding_source_first; +assign core_rx_last_be_sink_last = core_rx_padding_source_last; +assign core_rx_last_be_sink_payload_data = core_rx_padding_source_payload_data; +assign core_rx_last_be_sink_payload_last_be = core_rx_padding_source_payload_last_be; +assign core_rx_last_be_sink_payload_error = core_rx_padding_source_payload_error; +assign core_rx_converter_sink_valid = core_rx_last_be_source_valid; +assign core_rx_last_be_source_ready = core_rx_converter_sink_ready; +assign core_rx_converter_sink_first = core_rx_last_be_source_first; +assign core_rx_converter_sink_last = core_rx_last_be_source_last; +assign core_rx_converter_sink_payload_data = core_rx_last_be_source_payload_data; +assign core_rx_converter_sink_payload_last_be = core_rx_last_be_source_payload_last_be; +assign core_rx_converter_sink_payload_error = core_rx_last_be_source_payload_error; +assign core_rx_cdc_sink_sink_valid = core_rx_converter_source_valid; +assign core_rx_converter_source_ready = core_rx_cdc_sink_sink_ready; +assign core_rx_cdc_sink_sink_first = core_rx_converter_source_first; +assign core_rx_cdc_sink_sink_last = core_rx_converter_source_last; +assign core_rx_cdc_sink_sink_payload_data = core_rx_converter_source_payload_data; +assign core_rx_cdc_sink_sink_payload_last_be = core_rx_converter_source_payload_last_be; +assign core_rx_cdc_sink_sink_payload_error = core_rx_converter_source_payload_error; +assign core_source_valid = core_rx_cdc_source_source_valid; +assign core_rx_cdc_source_source_ready = core_source_ready; +assign core_source_first = core_rx_cdc_source_source_first; +assign core_source_last = core_rx_cdc_source_source_last; +assign core_source_payload_data = core_rx_cdc_source_source_payload_data; +assign core_source_payload_last_be = core_rx_cdc_source_source_payload_last_be; +assign core_source_payload_error = core_rx_cdc_source_source_payload_error; +assign wishbone_interface_writer_sink_sink_valid = wishbone_interface_sink_valid; +assign wishbone_interface_sink_ready = wishbone_interface_writer_sink_sink_ready; +assign wishbone_interface_writer_sink_sink_first = wishbone_interface_sink_first; +assign wishbone_interface_writer_sink_sink_last = wishbone_interface_sink_last; +assign wishbone_interface_writer_sink_sink_payload_data = wishbone_interface_sink_payload_data; +assign wishbone_interface_writer_sink_sink_payload_last_be = wishbone_interface_sink_payload_last_be; +assign wishbone_interface_writer_sink_sink_payload_error = wishbone_interface_sink_payload_error; +assign wishbone_interface_source_valid = wishbone_interface_reader_source_source_valid; +assign wishbone_interface_reader_source_source_ready = wishbone_interface_source_ready; +assign wishbone_interface_source_first = wishbone_interface_reader_source_source_first; +assign wishbone_interface_source_last = wishbone_interface_reader_source_source_last; +assign wishbone_interface_source_payload_data = wishbone_interface_reader_source_source_payload_data; +assign wishbone_interface_source_payload_last_be = wishbone_interface_reader_source_source_payload_last_be; +assign wishbone_interface_source_payload_error = wishbone_interface_reader_source_source_payload_error; always @(*) begin - main_length_inc <= 4'd0; - case (main_sram5_sink_payload_last_be) + wishbone_interface_writer_length_inc <= 4'd0; + case (wishbone_interface_writer_sink_sink_payload_last_be) 1'd1: begin - main_length_inc <= 1'd1; + wishbone_interface_writer_length_inc <= 1'd1; end 2'd2: begin - main_length_inc <= 2'd2; + wishbone_interface_writer_length_inc <= 2'd2; end 3'd4: begin - main_length_inc <= 2'd3; + wishbone_interface_writer_length_inc <= 2'd3; end 4'd8: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end 5'd16: begin - main_length_inc <= 3'd5; + wishbone_interface_writer_length_inc <= 3'd5; end 6'd32: begin - main_length_inc <= 3'd6; + wishbone_interface_writer_length_inc <= 3'd6; end 7'd64: begin - main_length_inc <= 3'd7; + wishbone_interface_writer_length_inc <= 3'd7; end default: begin - main_length_inc <= 3'd4; + wishbone_interface_writer_length_inc <= 3'd4; end endcase end -assign main_sram44_source_ready = main_sram20_clear; -assign main_sram19_trigger = main_sram43_source_valid; -assign main_sram7_status = main_sram47_source_payload_slot; -assign main_sram10_status = main_sram48_source_payload_length; -assign main_wr_data = main_sram4_sink_payload_data; +assign wishbone_interface_writer_stat_fifo_source_ready = wishbone_interface_writer_available_clear; +assign wishbone_interface_writer_available_trigger = wishbone_interface_writer_stat_fifo_source_valid; +assign wishbone_interface_writer_slot_status = wishbone_interface_writer_stat_fifo_source_payload_slot; +assign wishbone_interface_writer_length_status = wishbone_interface_writer_stat_fifo_source_payload_length; +assign wishbone_interface_writer_wr_data = wishbone_interface_writer_sink_sink_payload_data; always @(*) begin - main_sram75_adr <= 9'd0; - main_sram77_we <= 1'd0; - main_sram78_dat_w <= 32'd0; - main_sram79_adr <= 9'd0; - main_sram81_we <= 1'd0; - main_sram82_dat_w <= 32'd0; - case (main_slot) + wishbone_interface_writer_memory0_adr <= 9'd0; + wishbone_interface_writer_memory0_dat_w <= 32'd0; + wishbone_interface_writer_memory0_we <= 1'd0; + wishbone_interface_writer_memory1_adr <= 9'd0; + wishbone_interface_writer_memory1_dat_w <= 32'd0; + wishbone_interface_writer_memory1_we <= 1'd0; + case (wishbone_interface_writer_slot) 1'd0: begin - main_sram75_adr <= main_sram35_length[10:2]; - main_sram78_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram77_we <= 1'd1; + wishbone_interface_writer_memory0_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory0_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory0_we <= 1'd1; end end 1'd1: begin - main_sram79_adr <= main_sram35_length[10:2]; - main_sram82_dat_w <= main_wr_data; - if ((main_sram0_sink_valid & main_write)) begin - main_sram81_we <= 1'd1; + wishbone_interface_writer_memory1_adr <= wishbone_interface_writer_length[10:2]; + wishbone_interface_writer_memory1_dat_w <= wishbone_interface_writer_wr_data; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin + wishbone_interface_writer_memory1_we <= 1'd1; end end endcase end -assign main_sram21_available = main_sram17_status; -assign main_sram25_available = main_sram18_pending; +assign wishbone_interface_writer_available0 = wishbone_interface_writer_available_status; +assign wishbone_interface_writer_available1 = wishbone_interface_writer_available_pending; always @(*) begin - main_sram20_clear <= 1'd0; - if ((main_sram28_re & main_sram29_r)) begin - main_sram20_clear <= 1'd1; + wishbone_interface_writer_available_clear <= 1'd0; + if ((wishbone_interface_writer_pending_re & wishbone_interface_writer_pending_r)) begin + wishbone_interface_writer_available_clear <= 1'd1; end end -assign main_sram16_irq = (main_sram26_status & main_sram31_storage); -assign main_sram17_status = main_sram19_trigger; -assign main_sram18_pending = main_sram19_trigger; -assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; -assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; -assign main_sram38_sink_ready = main_sram50_writable; -assign main_sram49_we = main_sram37_sink_valid; -assign main_sram68_fifo_in_first = main_sram39_sink_first; -assign main_sram69_fifo_in_last = main_sram40_sink_last; -assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; -assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; -assign main_sram43_source_valid = main_sram52_readable; -assign main_sram45_source_first = main_sram72_fifo_out_first; -assign main_sram46_source_last = main_sram73_fifo_out_last; -assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; -assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; -assign main_sram51_re = main_sram44_source_ready; +assign wishbone_interface_writer_irq = (wishbone_interface_writer_pending_status & wishbone_interface_writer_enable_storage); +assign wishbone_interface_writer_available_status = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_available_pending = wishbone_interface_writer_available_trigger; +assign wishbone_interface_writer_stat_fifo_syncfifo_din = {wishbone_interface_writer_stat_fifo_fifo_in_last, wishbone_interface_writer_stat_fifo_fifo_in_first, wishbone_interface_writer_stat_fifo_fifo_in_payload_length, wishbone_interface_writer_stat_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_writer_stat_fifo_fifo_out_last, wishbone_interface_writer_stat_fifo_fifo_out_first, wishbone_interface_writer_stat_fifo_fifo_out_payload_length, wishbone_interface_writer_stat_fifo_fifo_out_payload_slot} = wishbone_interface_writer_stat_fifo_syncfifo_dout; +assign wishbone_interface_writer_stat_fifo_sink_ready = wishbone_interface_writer_stat_fifo_syncfifo_writable; +assign wishbone_interface_writer_stat_fifo_syncfifo_we = wishbone_interface_writer_stat_fifo_sink_valid; +assign wishbone_interface_writer_stat_fifo_fifo_in_first = wishbone_interface_writer_stat_fifo_sink_first; +assign wishbone_interface_writer_stat_fifo_fifo_in_last = wishbone_interface_writer_stat_fifo_sink_last; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_slot = wishbone_interface_writer_stat_fifo_sink_payload_slot; +assign wishbone_interface_writer_stat_fifo_fifo_in_payload_length = wishbone_interface_writer_stat_fifo_sink_payload_length; +assign wishbone_interface_writer_stat_fifo_source_valid = wishbone_interface_writer_stat_fifo_syncfifo_readable; +assign wishbone_interface_writer_stat_fifo_source_first = wishbone_interface_writer_stat_fifo_fifo_out_first; +assign wishbone_interface_writer_stat_fifo_source_last = wishbone_interface_writer_stat_fifo_fifo_out_last; +assign wishbone_interface_writer_stat_fifo_source_payload_slot = wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; +assign wishbone_interface_writer_stat_fifo_source_payload_length = wishbone_interface_writer_stat_fifo_fifo_out_payload_length; +assign wishbone_interface_writer_stat_fifo_syncfifo_re = wishbone_interface_writer_stat_fifo_source_ready; always @(*) begin - main_sram59_adr <= 1'd0; - if (main_sram56_replace) begin - main_sram59_adr <= (main_sram57_produce - 1'd1); + wishbone_interface_writer_stat_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_writer_stat_fifo_replace) begin + wishbone_interface_writer_stat_fifo_wrport_adr <= (wishbone_interface_writer_stat_fifo_produce - 1'd1); end else begin - main_sram59_adr <= main_sram57_produce; + wishbone_interface_writer_stat_fifo_wrport_adr <= wishbone_interface_writer_stat_fifo_produce; end end -assign main_sram62_dat_w = main_sram53_din; -assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); -assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); -assign main_sram64_adr = main_sram58_consume; -assign main_sram54_dout = main_sram65_dat_r; -assign main_sram50_writable = (main_sram55_level != 2'd2); -assign main_sram52_readable = (main_sram55_level != 1'd0); +assign wishbone_interface_writer_stat_fifo_wrport_dat_w = wishbone_interface_writer_stat_fifo_syncfifo_din; +assign wishbone_interface_writer_stat_fifo_wrport_we = (wishbone_interface_writer_stat_fifo_syncfifo_we & (wishbone_interface_writer_stat_fifo_syncfifo_writable | wishbone_interface_writer_stat_fifo_replace)); +assign wishbone_interface_writer_stat_fifo_do_read = (wishbone_interface_writer_stat_fifo_syncfifo_readable & wishbone_interface_writer_stat_fifo_syncfifo_re); +assign wishbone_interface_writer_stat_fifo_rdport_adr = wishbone_interface_writer_stat_fifo_consume; +assign wishbone_interface_writer_stat_fifo_syncfifo_dout = wishbone_interface_writer_stat_fifo_rdport_dat_r; +assign wishbone_interface_writer_stat_fifo_syncfifo_writable = (wishbone_interface_writer_stat_fifo_level != 2'd2); +assign wishbone_interface_writer_stat_fifo_syncfifo_readable = (wishbone_interface_writer_stat_fifo_level != 1'd0); always @(*) begin - builder_liteethmacsramwriter_next_state <= 3'd0; - main_slot_liteethmacsramwriter_next_value <= 1'd0; - main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; - main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; - main_sram37_sink_valid <= 1'd0; - main_sram41_sink_payload_slot <= 1'd0; - main_sram42_sink_payload_length <= 11'd0; - main_write <= 1'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) + liteethmacsramwriter_next_state <= 3'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= 32'd0; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 11'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= 1'd0; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_payload_length <= 11'd0; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd0; + wishbone_interface_writer_write <= 1'd0; + liteethmacsramwriter_next_state <= liteethmacsramwriter_state; + case (liteethmacsramwriter_state) 1'd1: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end 2'd2: begin - if ((main_sram0_sink_valid & main_sram3_sink_last)) begin - if ((main_sram5_sink_payload_last_be != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin + if ((wishbone_interface_writer_sink_sink_payload_last_be != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end end end 2'd3: begin - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end 3'd4: begin - main_sram37_sink_valid <= 1'd1; - main_sram41_sink_payload_slot <= main_slot; - main_sram42_sink_payload_length <= main_sram35_length; - main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); - main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; + wishbone_interface_writer_stat_fifo_sink_valid <= 1'd1; + wishbone_interface_writer_stat_fifo_sink_payload_slot <= wishbone_interface_writer_slot; + wishbone_interface_writer_stat_fifo_sink_payload_length <= wishbone_interface_writer_length; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= (wishbone_interface_writer_slot + 1'd1); + wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 1'd0; end default: begin - if (main_sram0_sink_valid) begin - if (main_sram38_sink_ready) begin - main_write <= 1'd1; - main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); - main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; - if ((main_sram35_length >= 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 1'd1; + if (wishbone_interface_writer_sink_sink_valid) begin + if (wishbone_interface_writer_stat_fifo_sink_ready) begin + wishbone_interface_writer_write <= 1'd1; + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= (wishbone_interface_writer_length + wishbone_interface_writer_length_inc); + wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((wishbone_interface_writer_length >= 11'd1530)) begin + liteethmacsramwriter_next_state <= 1'd1; end - if (main_sram3_sink_last) begin - if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; + if (wishbone_interface_writer_sink_sink_last) begin + if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin + liteethmacsramwriter_next_state <= 2'd3; end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; + liteethmacsramwriter_next_state <= 3'd4; end end end else begin - main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); - main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd2; + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= (wishbone_interface_writer_errors_status + 1'd1); + wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + liteethmacsramwriter_next_state <= 2'd2; end end end endcase end -assign main_sram123_sink_valid = main_start_re; -assign main_sram127_sink_payload_slot = main_sram100_storage; -assign main_sram128_sink_payload_length = main_sram102_storage; -assign main_sram94_status = main_sram124_sink_ready; -assign main_sram97_status = main_sram141_level; +assign wishbone_interface_reader_cmd_fifo_sink_valid = wishbone_interface_reader_start_re; +assign wishbone_interface_reader_cmd_fifo_sink_payload_slot = wishbone_interface_reader_slot_storage; +assign wishbone_interface_reader_cmd_fifo_sink_payload_length = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_ready_status = wishbone_interface_reader_cmd_fifo_sink_ready; +assign wishbone_interface_reader_level_status = wishbone_interface_reader_cmd_fifo_level; always @(*) begin - main_sram88_source_payload_last_be <= 4'd0; - if (main_sram86_source_last) begin - case (main_sram134_source_payload_length[1:0]) + wishbone_interface_reader_source_source_payload_last_be <= 4'd0; + if (wishbone_interface_reader_source_source_last) begin + case (wishbone_interface_reader_cmd_fifo_source_payload_length[1:0]) 1'd1: begin - main_sram88_source_payload_last_be <= 1'd1; + wishbone_interface_reader_source_source_payload_last_be <= 1'd1; end 2'd2: begin - main_sram88_source_payload_last_be <= 2'd2; + wishbone_interface_reader_source_source_payload_last_be <= 2'd2; end 2'd3: begin - main_sram88_source_payload_last_be <= 3'd4; + wishbone_interface_reader_source_source_payload_last_be <= 3'd4; end 3'd4: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end 3'd5: begin - main_sram88_source_payload_last_be <= 5'd16; + wishbone_interface_reader_source_source_payload_last_be <= 5'd16; end 3'd6: begin - main_sram88_source_payload_last_be <= 6'd32; + wishbone_interface_reader_source_source_payload_last_be <= 6'd32; end 3'd7: begin - main_sram88_source_payload_last_be <= 7'd64; + wishbone_interface_reader_source_source_payload_last_be <= 7'd64; end default: begin - main_sram88_source_payload_last_be <= 4'd8; + wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end endcase end end -assign main_sram163_re = main_read; -assign main_sram161_adr = main_sram122_length[10:2]; -assign main_sram166_re = main_read; -assign main_sram164_adr = main_sram122_length[10:2]; +assign wishbone_interface_reader_memory0_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory0_adr = wishbone_interface_reader_length[10:2]; +assign wishbone_interface_reader_memory1_re = wishbone_interface_reader_read; +assign wishbone_interface_reader_memory1_adr = wishbone_interface_reader_length[10:2]; always @(*) begin - main_rd_data <= 32'd0; - case (main_sram133_source_payload_slot) + wishbone_interface_reader_rd_data <= 32'd0; + case (wishbone_interface_reader_cmd_fifo_source_payload_slot) 1'd0: begin - main_rd_data <= main_sram162_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory0_dat_r; end 1'd1: begin - main_rd_data <= main_sram165_dat_r; + wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory1_dat_r; end endcase end -assign main_sram87_source_payload_data = main_rd_data; -assign main_sram109_event0 = main_sram105_status; -assign main_sram113_event0 = main_sram106_pending; +assign wishbone_interface_reader_source_source_payload_data = wishbone_interface_reader_rd_data; +assign wishbone_interface_reader_event00 = wishbone_interface_reader_eventsourcepulse_status; +assign wishbone_interface_reader_event01 = wishbone_interface_reader_eventsourcepulse_pending; always @(*) begin - main_sram108_clear <= 1'd0; - if ((main_sram116_re & main_sram117_r)) begin - main_sram108_clear <= 1'd1; + wishbone_interface_reader_eventsourcepulse_clear <= 1'd0; + if ((wishbone_interface_reader_pending_re & wishbone_interface_reader_pending_r)) begin + wishbone_interface_reader_eventsourcepulse_clear <= 1'd1; end end -assign main_sram104_irq = (main_sram114_status & main_sram119_storage); -assign main_sram105_status = 1'd0; -assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; -assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; -assign main_sram124_sink_ready = main_sram136_writable; -assign main_sram135_we = main_sram123_sink_valid; -assign main_sram154_fifo_in_first = main_sram125_sink_first; -assign main_sram155_fifo_in_last = main_sram126_sink_last; -assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; -assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; -assign main_sram129_source_valid = main_sram138_readable; -assign main_sram131_source_first = main_sram158_fifo_out_first; -assign main_sram132_source_last = main_sram159_fifo_out_last; -assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; -assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; -assign main_sram137_re = main_sram130_source_ready; +assign wishbone_interface_reader_irq = (wishbone_interface_reader_pending_status & wishbone_interface_reader_enable_storage); +assign wishbone_interface_reader_eventsourcepulse_status = 1'd0; +assign wishbone_interface_reader_cmd_fifo_syncfifo_din = {wishbone_interface_reader_cmd_fifo_fifo_in_last, wishbone_interface_reader_cmd_fifo_fifo_in_first, wishbone_interface_reader_cmd_fifo_fifo_in_payload_length, wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot}; +assign {wishbone_interface_reader_cmd_fifo_fifo_out_last, wishbone_interface_reader_cmd_fifo_fifo_out_first, wishbone_interface_reader_cmd_fifo_fifo_out_payload_length, wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot} = wishbone_interface_reader_cmd_fifo_syncfifo_dout; +assign wishbone_interface_reader_cmd_fifo_sink_ready = wishbone_interface_reader_cmd_fifo_syncfifo_writable; +assign wishbone_interface_reader_cmd_fifo_syncfifo_we = wishbone_interface_reader_cmd_fifo_sink_valid; +assign wishbone_interface_reader_cmd_fifo_fifo_in_first = wishbone_interface_reader_cmd_fifo_sink_first; +assign wishbone_interface_reader_cmd_fifo_fifo_in_last = wishbone_interface_reader_cmd_fifo_sink_last; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot = wishbone_interface_reader_cmd_fifo_sink_payload_slot; +assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_length = wishbone_interface_reader_cmd_fifo_sink_payload_length; +assign wishbone_interface_reader_cmd_fifo_source_valid = wishbone_interface_reader_cmd_fifo_syncfifo_readable; +assign wishbone_interface_reader_cmd_fifo_source_first = wishbone_interface_reader_cmd_fifo_fifo_out_first; +assign wishbone_interface_reader_cmd_fifo_source_last = wishbone_interface_reader_cmd_fifo_fifo_out_last; +assign wishbone_interface_reader_cmd_fifo_source_payload_slot = wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; +assign wishbone_interface_reader_cmd_fifo_source_payload_length = wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; +assign wishbone_interface_reader_cmd_fifo_syncfifo_re = wishbone_interface_reader_cmd_fifo_source_ready; always @(*) begin - main_sram145_adr <= 1'd0; - if (main_sram142_replace) begin - main_sram145_adr <= (main_sram143_produce - 1'd1); + wishbone_interface_reader_cmd_fifo_wrport_adr <= 1'd0; + if (wishbone_interface_reader_cmd_fifo_replace) begin + wishbone_interface_reader_cmd_fifo_wrport_adr <= (wishbone_interface_reader_cmd_fifo_produce - 1'd1); end else begin - main_sram145_adr <= main_sram143_produce; + wishbone_interface_reader_cmd_fifo_wrport_adr <= wishbone_interface_reader_cmd_fifo_produce; end end -assign main_sram148_dat_w = main_sram139_din; -assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); -assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); -assign main_sram150_adr = main_sram144_consume; -assign main_sram140_dout = main_sram151_dat_r; -assign main_sram136_writable = (main_sram141_level != 2'd2); -assign main_sram138_readable = (main_sram141_level != 1'd0); +assign wishbone_interface_reader_cmd_fifo_wrport_dat_w = wishbone_interface_reader_cmd_fifo_syncfifo_din; +assign wishbone_interface_reader_cmd_fifo_wrport_we = (wishbone_interface_reader_cmd_fifo_syncfifo_we & (wishbone_interface_reader_cmd_fifo_syncfifo_writable | wishbone_interface_reader_cmd_fifo_replace)); +assign wishbone_interface_reader_cmd_fifo_do_read = (wishbone_interface_reader_cmd_fifo_syncfifo_readable & wishbone_interface_reader_cmd_fifo_syncfifo_re); +assign wishbone_interface_reader_cmd_fifo_rdport_adr = wishbone_interface_reader_cmd_fifo_consume; +assign wishbone_interface_reader_cmd_fifo_syncfifo_dout = wishbone_interface_reader_cmd_fifo_rdport_dat_r; +assign wishbone_interface_reader_cmd_fifo_syncfifo_writable = (wishbone_interface_reader_cmd_fifo_level != 2'd2); +assign wishbone_interface_reader_cmd_fifo_syncfifo_readable = (wishbone_interface_reader_cmd_fifo_level != 1'd0); always @(*) begin - builder_liteethmacsramreader_next_state <= 2'd0; - main_read <= 1'd0; - main_sram107_trigger <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value <= 11'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; - main_sram130_source_ready <= 1'd0; - main_sram83_source_valid <= 1'd0; - main_sram86_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) + liteethmacsramreader_next_state <= 2'd0; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd0; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 11'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd0; + wishbone_interface_reader_read <= 1'd0; + wishbone_interface_reader_source_source_last <= 1'd0; + wishbone_interface_reader_source_source_valid <= 1'd0; + liteethmacsramreader_next_state <= liteethmacsramreader_state; + case (liteethmacsramreader_state) 1'd1: begin - main_sram83_source_valid <= 1'd1; - main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); - if (main_sram84_source_ready) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - if (main_sram86_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; + wishbone_interface_reader_source_source_valid <= 1'd1; + wishbone_interface_reader_source_source_last <= (wishbone_interface_reader_length >= wishbone_interface_reader_cmd_fifo_source_payload_length); + if (wishbone_interface_reader_source_source_ready) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= (wishbone_interface_reader_length + 3'd4); + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (wishbone_interface_reader_source_source_last) begin + liteethmacsramreader_next_state <= 2'd2; end end end 2'd2: begin - main_sram122_length_liteethmacsramreader_next_value <= 1'd0; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - main_sram107_trigger <= 1'd1; - main_sram130_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 1'd0; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + wishbone_interface_reader_eventsourcepulse_trigger <= 1'd1; + wishbone_interface_reader_cmd_fifo_source_ready <= 1'd1; + liteethmacsramreader_next_state <= 1'd0; end default: begin - if (main_sram129_source_valid) begin - main_read <= 1'd1; - main_sram122_length_liteethmacsramreader_next_value <= 3'd4; - main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; + if (wishbone_interface_reader_cmd_fifo_source_valid) begin + wishbone_interface_reader_read <= 1'd1; + wishbone_interface_reader_length_liteethmacsramreader_next_value <= 3'd4; + wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; + liteethmacsramreader_next_state <= 1'd1; end end endcase end -assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); -assign main_sram0_adr = main_interface0_adr[8:0]; -assign main_interface0_dat_r = main_sram0_dat_r; -assign main_sram1_adr = main_interface1_adr[8:0]; -assign main_interface1_dat_r = main_sram1_dat_r; +assign wishbone_interface_ev_irq = (wishbone_interface_writer_irq | wishbone_interface_reader_irq); +assign wishbone_interface_sram0_adr = wishbone_interface_interface0_adr[8:0]; +assign wishbone_interface_interface0_dat_r = wishbone_interface_sram0_dat_r; +assign wishbone_interface_sram1_adr = wishbone_interface_interface1_adr[8:0]; +assign wishbone_interface_interface1_dat_r = wishbone_interface_sram1_dat_r; always @(*) begin - main_sram2_we <= 4'd0; - main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); - main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); - main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); - main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); + wishbone_interface_decoder0_slave_sel <= 2'd0; + wishbone_interface_decoder0_slave_sel[0] <= (wishbone_interface_bus_rx_adr[9] == 1'd0); + wishbone_interface_decoder0_slave_sel[1] <= (wishbone_interface_bus_rx_adr[9] == 1'd1); end -assign main_sram2_adr = main_interface2_adr[8:0]; -assign main_interface2_dat_r = main_sram2_dat_r; -assign main_sram2_dat_w = main_interface2_dat_w; +assign wishbone_interface_interface0_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface0_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface0_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface0_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface0_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface0_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface0_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface1_adr = wishbone_interface_bus_rx_adr; +assign wishbone_interface_interface1_dat_w = wishbone_interface_bus_rx_dat_w; +assign wishbone_interface_interface1_sel = wishbone_interface_bus_rx_sel; +assign wishbone_interface_interface1_stb = wishbone_interface_bus_rx_stb; +assign wishbone_interface_interface1_we = wishbone_interface_bus_rx_we; +assign wishbone_interface_interface1_cti = wishbone_interface_bus_rx_cti; +assign wishbone_interface_interface1_bte = wishbone_interface_bus_rx_bte; +assign wishbone_interface_interface0_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[0]); +assign wishbone_interface_interface1_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[1]); +assign wishbone_interface_bus_rx_ack = (wishbone_interface_interface0_ack | wishbone_interface_interface1_ack); +assign wishbone_interface_bus_rx_err = (wishbone_interface_interface0_err | wishbone_interface_interface1_err); +assign wishbone_interface_bus_rx_dat_r = (({32{wishbone_interface_decoder0_slave_sel_r[0]}} & wishbone_interface_interface0_dat_r) | ({32{wishbone_interface_decoder0_slave_sel_r[1]}} & wishbone_interface_interface1_dat_r)); always @(*) begin - main_sram3_we <= 4'd0; - main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); - main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); - main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); - main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); + wishbone_interface_sram2_we <= 4'd0; + wishbone_interface_sram2_we[0] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[0]); + wishbone_interface_sram2_we[1] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[1]); + wishbone_interface_sram2_we[2] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[2]); + wishbone_interface_sram2_we[3] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[3]); end -assign main_sram3_adr = main_interface3_adr[8:0]; -assign main_interface3_dat_r = main_sram3_dat_r; -assign main_sram3_dat_w = main_interface3_dat_w; +assign wishbone_interface_sram2_adr = wishbone_interface_interface2_adr[8:0]; +assign wishbone_interface_interface2_dat_r = wishbone_interface_sram2_dat_r; +assign wishbone_interface_sram2_dat_w = wishbone_interface_interface2_dat_w; always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); + wishbone_interface_sram3_we <= 4'd0; + wishbone_interface_sram3_we[0] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[0]); + wishbone_interface_sram3_we[1] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[1]); + wishbone_interface_sram3_we[2] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[2]); + wishbone_interface_sram3_we[3] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[3]); end -assign main_interface0_adr = main_bus_adr; -assign main_interface0_dat_w = main_bus_dat_w; -assign main_interface0_sel = main_bus_sel; -assign main_interface0_stb = main_bus_stb; -assign main_interface0_we = main_bus_we; -assign main_interface0_cti = main_bus_cti; -assign main_interface0_bte = main_bus_bte; -assign main_interface1_adr = main_bus_adr; -assign main_interface1_dat_w = main_bus_dat_w; -assign main_interface1_sel = main_bus_sel; -assign main_interface1_stb = main_bus_stb; -assign main_interface1_we = main_bus_we; -assign main_interface1_cti = main_bus_cti; -assign main_interface1_bte = main_bus_bte; -assign main_interface2_adr = main_bus_adr; -assign main_interface2_dat_w = main_bus_dat_w; -assign main_interface2_sel = main_bus_sel; -assign main_interface2_stb = main_bus_stb; -assign main_interface2_we = main_bus_we; -assign main_interface2_cti = main_bus_cti; -assign main_interface2_bte = main_bus_bte; -assign main_interface3_adr = main_bus_adr; -assign main_interface3_dat_w = main_bus_dat_w; -assign main_interface3_sel = main_bus_sel; -assign main_interface3_stb = main_bus_stb; -assign main_interface3_we = main_bus_we; -assign main_interface3_cti = main_bus_cti; -assign main_interface3_bte = main_bus_bte; -assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); -assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); -assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); -assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); -assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +assign wishbone_interface_sram3_adr = wishbone_interface_interface3_adr[8:0]; +assign wishbone_interface_interface3_dat_r = wishbone_interface_sram3_dat_r; +assign wishbone_interface_sram3_dat_w = wishbone_interface_interface3_dat_w; always @(*) begin - builder_interface0_ack <= 1'd0; - builder_interface0_dat_r <= 32'd0; - builder_interface1_adr <= 14'd0; - builder_interface1_dat_w <= 32'd0; - builder_interface1_we <= 1'd0; - builder_wishbone2csr_next_state <= 1'd0; - builder_wishbone2csr_next_state <= builder_wishbone2csr_state; - case (builder_wishbone2csr_state) + wishbone_interface_decoder1_slave_sel <= 2'd0; + wishbone_interface_decoder1_slave_sel[0] <= (wishbone_interface_bus_tx_adr[9] == 1'd0); + wishbone_interface_decoder1_slave_sel[1] <= (wishbone_interface_bus_tx_adr[9] == 1'd1); +end +assign wishbone_interface_interface2_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface2_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface2_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface2_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface2_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface2_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface2_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface3_adr = wishbone_interface_bus_tx_adr; +assign wishbone_interface_interface3_dat_w = wishbone_interface_bus_tx_dat_w; +assign wishbone_interface_interface3_sel = wishbone_interface_bus_tx_sel; +assign wishbone_interface_interface3_stb = wishbone_interface_bus_tx_stb; +assign wishbone_interface_interface3_we = wishbone_interface_bus_tx_we; +assign wishbone_interface_interface3_cti = wishbone_interface_bus_tx_cti; +assign wishbone_interface_interface3_bte = wishbone_interface_bus_tx_bte; +assign wishbone_interface_interface2_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[0]); +assign wishbone_interface_interface3_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[1]); +assign wishbone_interface_bus_tx_ack = (wishbone_interface_interface2_ack | wishbone_interface_interface3_ack); +assign wishbone_interface_bus_tx_err = (wishbone_interface_interface2_err | wishbone_interface_interface3_err); +assign wishbone_interface_bus_tx_dat_r = (({32{wishbone_interface_decoder1_slave_sel_r[0]}} & wishbone_interface_interface2_dat_r) | ({32{wishbone_interface_decoder1_slave_sel_r[1]}} & wishbone_interface_interface3_dat_r)); +always @(*) begin + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; + interface1_we <= 1'd0; + wishbone2csr_next_state <= 1'd0; + wishbone2csr_next_state <= wishbone2csr_state; + case (wishbone2csr_state) 1'd1: begin - builder_interface0_ack <= 1'd1; - builder_interface0_dat_r <= builder_interface1_dat_r; - builder_wishbone2csr_next_state <= 1'd0; + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + wishbone2csr_next_state <= 1'd0; end default: begin - builder_interface1_dat_w <= builder_interface0_dat_w; - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr <= builder_interface0_adr[29:0]; - builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); - builder_wishbone2csr_next_state <= 1'd1; + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + wishbone2csr_next_state <= 1'd1; end end endcase end -assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); -assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_re <= 1'd0; - builder_csrbank0_reset0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= interface0_bank_bus_re; end end -assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank0_scratch0_re <= 1'd0; - builder_csrbank0_scratch0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + maccore_maccore_soc_rst <= 1'd0; + if (maccore_maccore_reset_re) begin + maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0]; end end -assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; -assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; -assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; -assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; -assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; -assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); -assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1]; +assign csrbank0_reset0_w = maccore_maccore_reset_storage; +assign csrbank0_scratch0_w = maccore_maccore_scratch_storage; +assign csrbank0_bus_errors_w = maccore_maccore_bus_errors_status; +assign maccore_maccore_bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 2'd2); +assign csrbank1_sram_writer_slot_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_re <= 1'd0; - builder_csrbank1_sram_writer_slot_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_slot_re <= 1'd0; + csrbank1_sram_writer_slot_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_sram_writer_slot_re <= interface1_bank_bus_we; + csrbank1_sram_writer_slot_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_writer_length_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_length_re <= 1'd0; + csrbank1_sram_writer_length_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_sram_writer_length_re <= interface1_bank_bus_we; + csrbank1_sram_writer_length_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_sram_writer_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_sram_writer_errors_re <= 1'd0; - builder_csrbank1_sram_writer_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_errors_re <= 1'd0; + csrbank1_sram_writer_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_sram_writer_errors_re <= interface1_bank_bus_we; + csrbank1_sram_writer_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_status_re <= 1'd0; + csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_sram_writer_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_pending_re <= 1'd0; + csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_sram_writer_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_writer_ev_enable0_re <= 1'd0; + csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_sram_writer_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_writer_ev_enable0_we <= interface1_bank_bus_re; end end -assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +assign wishbone_interface_reader_start_r = interface1_bank_bus_dat_w[0]; always @(*) begin - main_start_re <= 1'd0; - main_start_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_start_re <= builder_interface1_bank_bus_we; - main_start_we <= (~builder_interface1_bank_bus_we); + wishbone_interface_reader_start_re <= 1'd0; + wishbone_interface_reader_start_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + wishbone_interface_reader_start_re <= interface1_bank_bus_we; + wishbone_interface_reader_start_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ready_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_re <= 1'd0; - builder_csrbank1_sram_reader_ready_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ready_re <= 1'd0; + csrbank1_sram_reader_ready_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_sram_reader_ready_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ready_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +assign csrbank1_sram_reader_level_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_re <= 1'd0; - builder_csrbank1_sram_reader_level_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_level_re <= 1'd0; + csrbank1_sram_reader_level_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + csrbank1_sram_reader_level_re <= interface1_bank_bus_we; + csrbank1_sram_reader_level_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_slot0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_slot0_re <= 1'd0; + csrbank1_sram_reader_slot0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_sram_reader_slot0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_slot0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +assign csrbank1_sram_reader_length0_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_re <= 1'd0; - builder_csrbank1_sram_reader_length0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_length0_re <= 1'd0; + csrbank1_sram_reader_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_sram_reader_length0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_length0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_status_re <= 1'd0; + csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_sram_reader_ev_status_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_status_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_pending_re <= 1'd0; + csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_sram_reader_ev_pending_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_pending_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_sram_reader_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + csrbank1_sram_reader_ev_enable0_re <= 1'd0; + csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_sram_reader_ev_enable0_re <= interface1_bank_bus_we; + csrbank1_sram_reader_ev_enable0_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +assign csrbank1_preamble_crc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_re <= 1'd0; - builder_csrbank1_preamble_crc_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + csrbank1_preamble_crc_re <= 1'd0; + csrbank1_preamble_crc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + csrbank1_preamble_crc_re <= interface1_bank_bus_we; + csrbank1_preamble_crc_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_rx_datapath_preamble_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_rx_datapath_preamble_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_preamble_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +assign csrbank1_rx_datapath_crc_errors_r = interface1_bank_bus_dat_w; always @(*) begin - builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; - builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + csrbank1_rx_datapath_crc_errors_re <= 1'd0; + csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_rx_datapath_crc_errors_re <= interface1_bank_bus_we; + csrbank1_rx_datapath_crc_errors_we <= interface1_bank_bus_re; end end -assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; -assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; -assign main_sram11_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; -assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; -always @(*) begin - main_sram22_status <= 1'd0; - main_sram22_status <= main_sram21_available; -end -assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; -assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; -always @(*) begin - main_sram26_status <= 1'd0; - main_sram26_status <= main_sram25_available; -end -assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; -assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_sram30_available = main_sram31_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; -assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; -assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; -assign main_sram98_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; -assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; -always @(*) begin - main_sram110_status <= 1'd0; - main_sram110_status <= main_sram109_event0; -end -assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; -assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; -always @(*) begin - main_sram114_status <= 1'd0; - main_sram114_status <= main_sram113_event0; -end -assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; -assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_sram118_event0 = main_sram119_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; -assign builder_csrbank1_preamble_crc_w = main_status; -assign main_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; -assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; -assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); -assign builder_csrbank2_mode_detection_mode_r = builder_interface2_bank_bus_dat_w[0]; +assign csrbank1_sram_writer_slot_w = wishbone_interface_writer_slot_status; +assign wishbone_interface_writer_slot_we = csrbank1_sram_writer_slot_we; +assign csrbank1_sram_writer_length_w = wishbone_interface_writer_length_status; +assign wishbone_interface_writer_length_we = csrbank1_sram_writer_length_we; +assign csrbank1_sram_writer_errors_w = wishbone_interface_writer_errors_status; +assign wishbone_interface_writer_errors_we = csrbank1_sram_writer_errors_we; +assign wishbone_interface_writer_status_status = wishbone_interface_writer_available0; +assign csrbank1_sram_writer_ev_status_w = wishbone_interface_writer_status_status; +assign wishbone_interface_writer_status_we = csrbank1_sram_writer_ev_status_we; +assign wishbone_interface_writer_pending_status = wishbone_interface_writer_available1; +assign csrbank1_sram_writer_ev_pending_w = wishbone_interface_writer_pending_status; +assign wishbone_interface_writer_pending_we = csrbank1_sram_writer_ev_pending_we; +assign wishbone_interface_writer_available2 = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_writer_ev_enable0_w = wishbone_interface_writer_enable_storage; +assign csrbank1_sram_reader_ready_w = wishbone_interface_reader_ready_status; +assign wishbone_interface_reader_ready_we = csrbank1_sram_reader_ready_we; +assign csrbank1_sram_reader_level_w = wishbone_interface_reader_level_status; +assign wishbone_interface_reader_level_we = csrbank1_sram_reader_level_we; +assign csrbank1_sram_reader_slot0_w = wishbone_interface_reader_slot_storage; +assign csrbank1_sram_reader_length0_w = wishbone_interface_reader_length_storage; +assign wishbone_interface_reader_status_status = wishbone_interface_reader_event00; +assign csrbank1_sram_reader_ev_status_w = wishbone_interface_reader_status_status; +assign wishbone_interface_reader_status_we = csrbank1_sram_reader_ev_status_we; +assign wishbone_interface_reader_pending_status = wishbone_interface_reader_event01; +assign csrbank1_sram_reader_ev_pending_w = wishbone_interface_reader_pending_status; +assign wishbone_interface_reader_pending_we = csrbank1_sram_reader_ev_pending_we; +assign wishbone_interface_reader_event02 = wishbone_interface_reader_enable_storage; +assign csrbank1_sram_reader_ev_enable0_w = wishbone_interface_reader_enable_storage; +assign csrbank1_preamble_crc_w = core_status; +assign core_we = csrbank1_preamble_crc_we; +assign csrbank1_rx_datapath_preamble_errors_w = core_preamble_errors_status; +assign core_preamble_errors_we = csrbank1_rx_datapath_preamble_errors_we; +assign csrbank1_rx_datapath_crc_errors_w = core_crc_errors_status; +assign core_crc_errors_we = csrbank1_rx_datapath_crc_errors_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); +assign csrbank2_mode_detection_mode_r = interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mode_detection_mode_re <= 1'd0; - builder_csrbank2_mode_detection_mode_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_mode_detection_mode_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mode_detection_mode_we <= (~builder_interface2_bank_bus_we); + csrbank2_mode_detection_mode_re <= 1'd0; + csrbank2_mode_detection_mode_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_mode_detection_mode_re <= interface2_bank_bus_we; + csrbank2_mode_detection_mode_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +assign csrbank2_crg_reset0_r = interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_crg_reset0_re <= 1'd0; - builder_csrbank2_crg_reset0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + csrbank2_crg_reset0_re <= 1'd0; + csrbank2_crg_reset0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_crg_reset0_re <= interface2_bank_bus_we; + csrbank2_crg_reset0_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +assign csrbank2_mdio_w0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_re <= 1'd0; - builder_csrbank2_mdio_w0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + csrbank2_mdio_w0_re <= 1'd0; + csrbank2_mdio_w0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_mdio_w0_re <= interface2_bank_bus_we; + csrbank2_mdio_w0_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +assign csrbank2_mdio_r_r = interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + csrbank2_mdio_r_re <= 1'd0; + csrbank2_mdio_r_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_mdio_r_re <= interface2_bank_bus_we; + csrbank2_mdio_r_we <= interface2_bank_bus_re; end end -assign builder_csrbank2_mode_detection_mode_w = main_maccore_ethphy_mode_status; -assign main_maccore_ethphy_mode_we = builder_csrbank2_mode_detection_mode_we; -assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; -assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; -assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; -assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; -assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_adr = builder_interface1_adr; -assign builder_we = builder_interface1_we; -assign builder_dat_w = builder_interface1_dat_w; -assign builder_interface1_dat_r = builder_dat_r; -assign builder_interface0_bank_bus_adr = builder_adr; -assign builder_interface1_bank_bus_adr = builder_adr; -assign builder_interface2_bank_bus_adr = builder_adr; -assign builder_interface0_bank_bus_we = builder_we; -assign builder_interface1_bank_bus_we = builder_we; -assign builder_interface2_bank_bus_we = builder_we; -assign builder_interface0_bank_bus_dat_w = builder_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_dat_w; -assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); -assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); -assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; -assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); -assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +assign csrbank2_mode_detection_mode_w = maccore_ethphy_mode_status; +assign maccore_ethphy_mode_we = csrbank2_mode_detection_mode_we; +assign csrbank2_crg_reset0_w = maccore_ethphy_reset_storage; +assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0]; +assign maccore_ethphy_oe = maccore_ethphy__w_storage[1]; +assign maccore_ethphy_w = maccore_ethphy__w_storage[2]; +assign csrbank2_mdio_w0_w = maccore_ethphy__w_storage; +assign csrbank2_mdio_r_w = maccore_ethphy__r_status; +assign maccore_ethphy__r_we = csrbank2_mdio_r_we; +assign adr = interface1_adr; +assign re = interface1_re; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - builder_self0 <= 30'd0; - case (builder_grant) + self0 <= 30'd0; + case (grant) default: begin - builder_self0 <= main_wb_bus_adr; + self0 <= wb_bus_adr; end endcase end always @(*) begin - builder_self1 <= 32'd0; - case (builder_grant) + self1 <= 32'd0; + case (grant) default: begin - builder_self1 <= main_wb_bus_dat_w; + self1 <= wb_bus_dat_w; end endcase end always @(*) begin - builder_self2 <= 4'd0; - case (builder_grant) + self2 <= 4'd0; + case (grant) default: begin - builder_self2 <= main_wb_bus_sel; + self2 <= wb_bus_sel; end endcase end always @(*) begin - builder_self3 <= 1'd0; - case (builder_grant) + self3 <= 1'd0; + case (grant) default: begin - builder_self3 <= main_wb_bus_cyc; + self3 <= wb_bus_cyc; end endcase end always @(*) begin - builder_self4 <= 1'd0; - case (builder_grant) + self4 <= 1'd0; + case (grant) default: begin - builder_self4 <= main_wb_bus_stb; + self4 <= wb_bus_stb; end endcase end always @(*) begin - builder_self5 <= 1'd0; - case (builder_grant) + self5 <= 1'd0; + case (grant) default: begin - builder_self5 <= main_wb_bus_we; + self5 <= wb_bus_we; end endcase end always @(*) begin - builder_self6 <= 3'd0; - case (builder_grant) + self6 <= 3'd0; + case (grant) default: begin - builder_self6 <= main_wb_bus_cti; + self6 <= wb_bus_cti; end endcase end always @(*) begin - builder_self7 <= 2'd0; - case (builder_grant) + self7 <= 2'd0; + case (grant) default: begin - builder_self7 <= main_wb_bus_bte; + self7 <= wb_bus_bte; end endcase end -assign main_maccore_ethphy_toggle_o = builder_xilinxmultiregimpl01; +assign maccore_ethphy_toggle_o = xilinxmultiregimpl01; always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl11; + maccore_ethphy__r_status <= 1'd0; + maccore_ethphy__r_status <= maccore_ethphy_r; + maccore_ethphy__r_status <= xilinxmultiregimpl11; end -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl21; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl31; -assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl41; -assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl51; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl61; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl71; +assign core_tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl21; +assign core_tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl31; +assign core_pulsesynchronizer0_toggle_o = xilinxmultiregimpl41; +assign core_pulsesynchronizer1_toggle_o = xilinxmultiregimpl51; +assign core_rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl61; +assign core_rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl71; //------------------------------------------------------------------------------ @@ -3517,624 +3443,624 @@ assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl71; //------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_eth_counter <= (main_maccore_ethphy_eth_counter + 1'd1); - if (main_maccore_ethphy_i) begin - main_maccore_ethphy_toggle_i <= (~main_maccore_ethphy_toggle_i); + maccore_ethphy_eth_counter <= (maccore_ethphy_eth_counter + 1'd1); + if (maccore_ethphy_i) begin + maccore_ethphy_toggle_i <= (~maccore_ethphy_toggle_i); end - main_maccore_ethphy_pads_d_rx_dv <= gmii_rx_dv; - main_maccore_ethphy_pads_d_rx_data <= gmii_rx_data; - main_maccore_ethphy_gmii_rx_dv_d <= main_maccore_ethphy_pads_d_rx_dv; - main_maccore_ethphy_gmii_rx_source_valid <= main_maccore_ethphy_pads_d_rx_dv; - main_maccore_ethphy_gmii_rx_source_payload_data <= main_maccore_ethphy_pads_d_rx_data; - main_maccore_ethphy_mii_rx_reset <= (~main_maccore_ethphy_pads_d_rx_dv); - main_maccore_ethphy_mii_rx_converter_sink_valid <= 1'd1; - main_maccore_ethphy_mii_rx_converter_sink_payload_data <= main_maccore_ethphy_pads_d_rx_data; - if (main_maccore_ethphy_mii_rx_converter_source_ready) begin - main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + maccore_ethphy_pads_d_rx_dv <= gmii_rx_dv; + maccore_ethphy_pads_d_rx_data <= gmii_rx_data; + maccore_ethphy_gmii_rx_dv_d <= maccore_ethphy_pads_d_rx_dv; + maccore_ethphy_gmii_rx_source_valid <= maccore_ethphy_pads_d_rx_dv; + maccore_ethphy_gmii_rx_source_payload_data <= maccore_ethphy_pads_d_rx_data; + maccore_ethphy_mii_rx_reset <= (~maccore_ethphy_pads_d_rx_dv); + maccore_ethphy_mii_rx_converter_sink_valid <= 1'd1; + maccore_ethphy_mii_rx_converter_sink_payload_data <= maccore_ethphy_pads_d_rx_data; + if (maccore_ethphy_mii_rx_converter_source_ready) begin + maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; end - if (main_maccore_ethphy_mii_rx_converter_load_part) begin - if (((main_maccore_ethphy_mii_rx_converter_demux == 1'd1) | main_maccore_ethphy_mii_rx_converter_sink_last)) begin - main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; - main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd1; + if (maccore_ethphy_mii_rx_converter_load_part) begin + if (((maccore_ethphy_mii_rx_converter_demux == 1'd1) | maccore_ethphy_mii_rx_converter_sink_last)) begin + maccore_ethphy_mii_rx_converter_demux <= 1'd0; + maccore_ethphy_mii_rx_converter_strobe_all <= 1'd1; end else begin - main_maccore_ethphy_mii_rx_converter_demux <= (main_maccore_ethphy_mii_rx_converter_demux + 1'd1); + maccore_ethphy_mii_rx_converter_demux <= (maccore_ethphy_mii_rx_converter_demux + 1'd1); end end - if ((main_maccore_ethphy_mii_rx_converter_source_valid & main_maccore_ethphy_mii_rx_converter_source_ready)) begin - if ((main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready)) begin - main_maccore_ethphy_mii_rx_converter_source_first <= main_maccore_ethphy_mii_rx_converter_sink_first; - main_maccore_ethphy_mii_rx_converter_source_last <= main_maccore_ethphy_mii_rx_converter_sink_last; + if ((maccore_ethphy_mii_rx_converter_source_valid & maccore_ethphy_mii_rx_converter_source_ready)) begin + if ((maccore_ethphy_mii_rx_converter_sink_valid & maccore_ethphy_mii_rx_converter_sink_ready)) begin + maccore_ethphy_mii_rx_converter_source_first <= maccore_ethphy_mii_rx_converter_sink_first; + maccore_ethphy_mii_rx_converter_source_last <= maccore_ethphy_mii_rx_converter_sink_last; end else begin - main_maccore_ethphy_mii_rx_converter_source_first <= 1'd0; - main_maccore_ethphy_mii_rx_converter_source_last <= 1'd0; + maccore_ethphy_mii_rx_converter_source_first <= 1'd0; + maccore_ethphy_mii_rx_converter_source_last <= 1'd0; end end else begin - if ((main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready)) begin - main_maccore_ethphy_mii_rx_converter_source_first <= (main_maccore_ethphy_mii_rx_converter_sink_first | main_maccore_ethphy_mii_rx_converter_source_first); - main_maccore_ethphy_mii_rx_converter_source_last <= (main_maccore_ethphy_mii_rx_converter_sink_last | main_maccore_ethphy_mii_rx_converter_source_last); + if ((maccore_ethphy_mii_rx_converter_sink_valid & maccore_ethphy_mii_rx_converter_sink_ready)) begin + maccore_ethphy_mii_rx_converter_source_first <= (maccore_ethphy_mii_rx_converter_sink_first | maccore_ethphy_mii_rx_converter_source_first); + maccore_ethphy_mii_rx_converter_source_last <= (maccore_ethphy_mii_rx_converter_sink_last | maccore_ethphy_mii_rx_converter_source_last); end end - if (main_maccore_ethphy_mii_rx_converter_load_part) begin - case (main_maccore_ethphy_mii_rx_converter_demux) + if (maccore_ethphy_mii_rx_converter_load_part) begin + case (maccore_ethphy_mii_rx_converter_demux) 1'd0: begin - main_maccore_ethphy_mii_rx_converter_source_payload_data[3:0] <= main_maccore_ethphy_mii_rx_converter_sink_payload_data; + maccore_ethphy_mii_rx_converter_source_payload_data[3:0] <= maccore_ethphy_mii_rx_converter_sink_payload_data; end 1'd1: begin - main_maccore_ethphy_mii_rx_converter_source_payload_data[7:4] <= main_maccore_ethphy_mii_rx_converter_sink_payload_data; + maccore_ethphy_mii_rx_converter_source_payload_data[7:4] <= maccore_ethphy_mii_rx_converter_sink_payload_data; end endcase end - if (main_maccore_ethphy_mii_rx_converter_load_part) begin - main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= (main_maccore_ethphy_mii_rx_converter_demux + 1'd1); + if (maccore_ethphy_mii_rx_converter_load_part) begin + maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= (maccore_ethphy_mii_rx_converter_demux + 1'd1); end - if (main_maccore_ethphy_mii_rx_reset) begin - main_maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; - main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + if (maccore_ethphy_mii_rx_reset) begin + maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; + maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; + maccore_ethphy_mii_rx_converter_demux <= 1'd0; + maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; end - builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; - if (main_pulsesynchronizer0_i) begin - main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + rxdatapath_liteethmacpreamblechecker_state <= rxdatapath_liteethmacpreamblechecker_next_state; + if (core_pulsesynchronizer0_i) begin + core_pulsesynchronizer0_toggle_i <= (~core_pulsesynchronizer0_toggle_i); end - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + if (core_liteethmaccrc32checker_crc_ce) begin + core_liteethmaccrc32checker_crc_reg <= core_liteethmaccrc32checker_crc_crc_next; end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + if (core_liteethmaccrc32checker_crc_reset) begin + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((core_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_produce <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + core_liteethmaccrc32checker_syncfifo_produce <= (core_liteethmaccrc32checker_syncfifo_produce + 1'd1); end end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + if ((core_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + core_liteethmaccrc32checker_syncfifo_consume <= 1'd0; end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + core_liteethmaccrc32checker_syncfifo_consume <= (core_liteethmaccrc32checker_syncfifo_consume + 1'd1); end end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~core_liteethmaccrc32checker_syncfifo_do_read)) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level + 1'd1); end end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + if (core_liteethmaccrc32checker_syncfifo_do_read) begin + core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level - 1'd1); end end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + if (core_liteethmaccrc32checker_fifo_reset) begin + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; end - builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; - if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin - main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + rxdatapath_bufferizeendpoints_state <= rxdatapath_bufferizeendpoints_next_state; + if (core_liteethmaccrc32checker_last_be_next_value_ce0) begin + core_liteethmaccrc32checker_last_be <= core_liteethmaccrc32checker_last_be_next_value0; end - if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin - main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + if (core_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + core_liteethmaccrc32checker_crc_error1 <= core_liteethmaccrc32checker_crc_error1_next_value1; end - if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin - main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; - main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; - main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; - main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; - main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + if (((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready)) begin + core_bufferizeendpoints_pipe_valid_source_valid <= core_bufferizeendpoints_pipe_valid_sink_valid; + core_bufferizeendpoints_pipe_valid_source_first <= core_bufferizeendpoints_pipe_valid_sink_first; + core_bufferizeendpoints_pipe_valid_source_last <= core_bufferizeendpoints_pipe_valid_sink_last; + core_bufferizeendpoints_pipe_valid_source_payload_data <= core_bufferizeendpoints_pipe_valid_sink_payload_data; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= core_bufferizeendpoints_pipe_valid_sink_payload_last_be; + core_bufferizeendpoints_pipe_valid_source_payload_error <= core_bufferizeendpoints_pipe_valid_sink_payload_error; end - if (main_pulsesynchronizer1_i) begin - main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + if (core_pulsesynchronizer1_i) begin + core_pulsesynchronizer1_toggle_i <= (~core_pulsesynchronizer1_toggle_i); end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; + if (core_rx_converter_converter_source_ready) begin + core_rx_converter_converter_strobe_all <= 1'd0; end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; + if (core_rx_converter_converter_load_part) begin + if (((core_rx_converter_converter_demux == 2'd3) | core_rx_converter_converter_sink_last)) begin + core_rx_converter_converter_demux <= 1'd0; + core_rx_converter_converter_strobe_all <= 1'd1; end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + core_rx_converter_converter_demux <= (core_rx_converter_converter_demux + 1'd1); end end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + if ((core_rx_converter_converter_source_valid & core_rx_converter_converter_source_ready)) begin + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= core_rx_converter_converter_sink_first; + core_rx_converter_converter_source_last <= core_rx_converter_converter_sink_last; end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; + core_rx_converter_converter_source_first <= 1'd0; + core_rx_converter_converter_source_last <= 1'd0; end end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin + core_rx_converter_converter_source_first <= (core_rx_converter_converter_sink_first | core_rx_converter_converter_source_first); + core_rx_converter_converter_source_last <= (core_rx_converter_converter_sink_last | core_rx_converter_converter_source_last); end end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) + if (core_rx_converter_converter_load_part) begin + case (core_rx_converter_converter_demux) 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[9:0] <= core_rx_converter_converter_sink_payload_data; end 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[19:10] <= core_rx_converter_converter_sink_payload_data; end 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[29:20] <= core_rx_converter_converter_sink_payload_data; end 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + core_rx_converter_converter_source_payload_data[39:30] <= core_rx_converter_converter_sink_payload_data; end endcase end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + if (core_rx_converter_converter_load_part) begin + core_rx_converter_converter_source_payload_valid_token_count <= (core_rx_converter_converter_demux + 1'd1); end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + core_rx_cdc_cdc_graycounter0_q_binary <= core_rx_cdc_cdc_graycounter0_q_next_binary; + core_rx_cdc_cdc_graycounter0_q <= core_rx_cdc_cdc_graycounter0_q_next; if (eth_rx_rst) begin - main_maccore_ethphy_gmii_rx_source_valid <= 1'd0; - main_maccore_ethphy_gmii_rx_source_payload_data <= 8'd0; - main_maccore_ethphy_gmii_rx_dv_d <= 1'd0; - main_maccore_ethphy_mii_rx_converter_sink_valid <= 1'd0; - main_maccore_ethphy_mii_rx_converter_sink_payload_data <= 4'd0; - main_maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; - main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; - main_maccore_ethphy_mii_rx_reset <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_liteethmaccrc32checker_last_be <= 1'd0; - main_liteethmaccrc32checker_crc_error1 <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; - main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; - main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; - builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + maccore_ethphy_gmii_rx_source_valid <= 1'd0; + maccore_ethphy_gmii_rx_source_payload_data <= 8'd0; + maccore_ethphy_gmii_rx_dv_d <= 1'd0; + maccore_ethphy_mii_rx_converter_sink_valid <= 1'd0; + maccore_ethphy_mii_rx_converter_sink_payload_data <= 4'd0; + maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; + maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; + maccore_ethphy_mii_rx_converter_demux <= 1'd0; + maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + maccore_ethphy_mii_rx_reset <= 1'd0; + core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + core_liteethmaccrc32checker_syncfifo_level <= 3'd0; + core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + core_liteethmaccrc32checker_last_be <= 1'd0; + core_liteethmaccrc32checker_crc_error1 <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + core_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + core_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + core_rx_converter_converter_source_payload_data <= 40'd0; + core_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + core_rx_converter_converter_demux <= 2'd0; + core_rx_converter_converter_strobe_all <= 1'd0; + core_rx_cdc_cdc_graycounter0_q <= 6'd0; + core_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + rxdatapath_bufferizeendpoints_state <= 2'd0; end - builder_xilinxmultiregimpl70 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl71 <= builder_xilinxmultiregimpl70; + xilinxmultiregimpl70 <= core_rx_cdc_cdc_graycounter1_q; + xilinxmultiregimpl71 <= xilinxmultiregimpl70; end always @(posedge eth_tx_clk) begin - if ((main_maccore_ethphy_mode0 == 1'd1)) begin - gmii_tx_en <= main_maccore_ethphy_mii_tx_pads_tx_en; - gmii_tx_data <= main_maccore_ethphy_mii_tx_pads_tx_data; + if ((maccore_ethphy_mode0 == 1'd1)) begin + gmii_tx_en <= maccore_ethphy_mii_tx_pads_tx_en; + gmii_tx_data <= maccore_ethphy_mii_tx_pads_tx_data; end else begin - gmii_tx_en <= main_maccore_ethphy_gmii_tx_pads_tx_en; - gmii_tx_data <= main_maccore_ethphy_gmii_tx_pads_tx_data; + gmii_tx_en <= maccore_ethphy_gmii_tx_pads_tx_en; + gmii_tx_data <= maccore_ethphy_gmii_tx_pads_tx_data; end - main_maccore_ethphy_gmii_tx_pads_tx_er <= 1'd0; - main_maccore_ethphy_gmii_tx_pads_tx_en <= main_maccore_ethphy_gmii_tx_sink_valid; - main_maccore_ethphy_gmii_tx_pads_tx_data <= main_maccore_ethphy_gmii_tx_sink_payload_data; - main_maccore_ethphy_gmii_tx_sink_ready <= 1'd1; - main_maccore_ethphy_mii_tx_pads_tx_er <= 1'd0; - main_maccore_ethphy_mii_tx_pads_tx_en <= main_maccore_ethphy_mii_tx_source_source_valid; - main_maccore_ethphy_mii_tx_pads_tx_data <= main_maccore_ethphy_mii_tx_source_source_payload_data; - if ((main_maccore_ethphy_mii_tx_converter_source_valid & main_maccore_ethphy_mii_tx_converter_source_ready)) begin - if (main_maccore_ethphy_mii_tx_converter_last) begin - main_maccore_ethphy_mii_tx_converter_mux <= 1'd0; + maccore_ethphy_gmii_tx_pads_tx_er <= 1'd0; + maccore_ethphy_gmii_tx_pads_tx_en <= maccore_ethphy_gmii_tx_sink_valid; + maccore_ethphy_gmii_tx_pads_tx_data <= maccore_ethphy_gmii_tx_sink_payload_data; + maccore_ethphy_gmii_tx_sink_ready <= 1'd1; + maccore_ethphy_mii_tx_pads_tx_er <= 1'd0; + maccore_ethphy_mii_tx_pads_tx_en <= maccore_ethphy_mii_tx_source_source_valid; + maccore_ethphy_mii_tx_pads_tx_data <= maccore_ethphy_mii_tx_source_source_payload_data; + if ((maccore_ethphy_mii_tx_converter_source_valid & maccore_ethphy_mii_tx_converter_source_ready)) begin + if (maccore_ethphy_mii_tx_converter_last) begin + maccore_ethphy_mii_tx_converter_mux <= 1'd0; end else begin - main_maccore_ethphy_mii_tx_converter_mux <= (main_maccore_ethphy_mii_tx_converter_mux + 1'd1); + maccore_ethphy_mii_tx_converter_mux <= (maccore_ethphy_mii_tx_converter_mux + 1'd1); end end - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= core_tx_cdc_cdc_graycounter1_q_next_binary; + core_tx_cdc_cdc_graycounter1_q <= core_tx_cdc_cdc_graycounter1_q_next; + if ((core_tx_converter_converter_source_valid & core_tx_converter_converter_source_ready)) begin + if (core_tx_converter_converter_last) begin + core_tx_converter_converter_mux <= 1'd0; end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + core_tx_converter_converter_mux <= (core_tx_converter_converter_mux + 1'd1); end end - builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; - builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; - if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin - main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + txdatapath_liteethmactxlastbe_state <= txdatapath_liteethmactxlastbe_next_state; + txdatapath_liteethmacpaddinginserter_state <= txdatapath_liteethmacpaddinginserter_next_state; + if (core_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + core_tx_padding_counter <= core_tx_padding_counter_clockdomainsrenamer0_next_value; end - if (main_tx_crc_is_ongoing0) begin - main_tx_crc_cnt <= 2'd3; + if (core_tx_crc_is_ongoing0) begin + core_tx_crc_cnt <= 2'd3; end else begin - if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin - main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + if ((core_tx_crc_is_ongoing1 & (~core_tx_crc_cnt_done))) begin + core_tx_crc_cnt <= (core_tx_crc_cnt - core_tx_crc_source_ready); end end - if (main_tx_crc_ce) begin - main_tx_crc_reg <= main_tx_crc_crc_next; + if (core_tx_crc_ce) begin + core_tx_crc_reg <= core_tx_crc_crc_next; end - if (main_tx_crc_reset) begin - main_tx_crc_reg <= 32'd4294967295; + if (core_tx_crc_reset) begin + core_tx_crc_reg <= 32'd4294967295; end - builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; - if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin - main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + txdatapath_bufferizeendpoints_state <= txdatapath_bufferizeendpoints_next_state; + if (core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + core_tx_crc_crc_packet <= core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; end - if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin - main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + if (core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + core_tx_crc_last_be <= core_tx_crc_last_be_clockdomainsrenamer1_next_value1; end - if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin - main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; - main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; - main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; - main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; - main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; - main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + if (((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready)) begin + core_tx_crc_pipe_valid_source_valid <= core_tx_crc_pipe_valid_sink_valid; + core_tx_crc_pipe_valid_source_first <= core_tx_crc_pipe_valid_sink_first; + core_tx_crc_pipe_valid_source_last <= core_tx_crc_pipe_valid_sink_last; + core_tx_crc_pipe_valid_source_payload_data <= core_tx_crc_pipe_valid_sink_payload_data; + core_tx_crc_pipe_valid_source_payload_last_be <= core_tx_crc_pipe_valid_sink_payload_last_be; + core_tx_crc_pipe_valid_source_payload_error <= core_tx_crc_pipe_valid_sink_payload_error; end - builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; - if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin - main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + txdatapath_liteethmacpreambleinserter_state <= txdatapath_liteethmacpreambleinserter_next_state; + if (core_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + core_tx_preamble_count <= core_tx_preamble_count_clockdomainsrenamer2_next_value; end - builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; - if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin - main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + txdatapath_liteethmacgap_state <= txdatapath_liteethmacgap_next_state; + if (core_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + core_tx_gap_counter <= core_tx_gap_counter_clockdomainsrenamer3_next_value; end if (eth_tx_rst) begin - main_maccore_ethphy_gmii_tx_sink_ready <= 1'd0; - main_maccore_ethphy_mii_tx_converter_mux <= 1'd0; - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_padding_counter <= 16'd0; - main_tx_crc_crc_packet <= 32'd0; - main_tx_crc_last_be <= 1'd0; - main_tx_crc_reg <= 32'd4294967295; - main_tx_crc_cnt <= 2'd3; - main_tx_crc_pipe_valid_source_valid <= 1'd0; - main_tx_crc_pipe_valid_source_payload_data <= 8'd0; - main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; - main_tx_crc_pipe_valid_source_payload_error <= 1'd0; - builder_txdatapath_liteethmactxlastbe_state <= 1'd0; - builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; - builder_txdatapath_bufferizeendpoints_state <= 2'd0; - builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; - builder_txdatapath_liteethmacgap_state <= 1'd0; + maccore_ethphy_gmii_tx_sink_ready <= 1'd0; + maccore_ethphy_mii_tx_converter_mux <= 1'd0; + core_tx_cdc_cdc_graycounter1_q <= 6'd0; + core_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + core_tx_converter_converter_mux <= 2'd0; + core_tx_padding_counter <= 16'd0; + core_tx_crc_reg <= 32'd4294967295; + core_tx_crc_cnt <= 2'd3; + core_tx_crc_pipe_valid_source_valid <= 1'd0; + core_tx_crc_pipe_valid_source_payload_data <= 8'd0; + core_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + core_tx_crc_pipe_valid_source_payload_error <= 1'd0; + txdatapath_liteethmactxlastbe_state <= 1'd0; + txdatapath_liteethmacpaddinginserter_state <= 1'd0; + txdatapath_bufferizeendpoints_state <= 2'd0; + txdatapath_liteethmacpreambleinserter_state <= 2'd0; + txdatapath_liteethmacgap_state <= 1'd0; end - builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; + xilinxmultiregimpl20 <= core_tx_cdc_cdc_graycounter0_q; + xilinxmultiregimpl21 <= xilinxmultiregimpl20; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); end end else begin - builder_count <= 20'd1000000; + count <= 20'd1000000; end - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + if ((maccore_maccore_bus_errors != 32'd4294967295)) begin + if (maccore_maccore_bus_error) begin + maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1); end end - if (main_maccore_ethphy_update_mode) begin - main_maccore_ethphy_mode0 <= main_maccore_ethphy_mode1; + if (maccore_ethphy_update_mode) begin + maccore_ethphy_mode0 <= maccore_ethphy_mode1; end - if (main_maccore_ethphy_sys_counter_reset) begin - main_maccore_ethphy_sys_counter <= 1'd0; + if (maccore_ethphy_sys_counter_reset) begin + maccore_ethphy_sys_counter <= 1'd0; end else begin - if (main_maccore_ethphy_sys_counter_ce) begin - main_maccore_ethphy_sys_counter <= (main_maccore_ethphy_sys_counter + 1'd1); + if (maccore_ethphy_sys_counter_ce) begin + maccore_ethphy_sys_counter <= (maccore_ethphy_sys_counter + 1'd1); end end - main_maccore_ethphy_toggle_o_r <= main_maccore_ethphy_toggle_o; - builder_liteethphygmiimii_state <= builder_liteethphygmiimii_next_state; - if (main_maccore_ethphy_counter_ce) begin - main_maccore_ethphy_counter <= (main_maccore_ethphy_counter + 1'd1); + maccore_ethphy_toggle_o_r <= maccore_ethphy_toggle_o; + liteethphygmiimii_state <= liteethphygmiimii_next_state; + if (maccore_ethphy_counter_ce) begin + maccore_ethphy_counter <= (maccore_ethphy_counter + 1'd1); end - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - if (main_pulsesynchronizer0_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + core_tx_cdc_cdc_graycounter0_q_binary <= core_tx_cdc_cdc_graycounter0_q_next_binary; + core_tx_cdc_cdc_graycounter0_q <= core_tx_cdc_cdc_graycounter0_q_next; + if (core_pulsesynchronizer0_o) begin + core_preamble_errors_status <= (core_preamble_errors_status + 1'd1); end - if (main_pulsesynchronizer1_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); + if (core_pulsesynchronizer1_o) begin + core_crc_errors_status <= (core_crc_errors_status + 1'd1); end - main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; - main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - main_sram57_produce <= (main_sram57_produce + 1'd1); + core_pulsesynchronizer0_toggle_o_r <= core_pulsesynchronizer0_toggle_o; + core_pulsesynchronizer1_toggle_o_r <= core_pulsesynchronizer1_toggle_o; + core_rx_cdc_cdc_graycounter1_q_binary <= core_rx_cdc_cdc_graycounter1_q_next_binary; + core_rx_cdc_cdc_graycounter1_q <= core_rx_cdc_cdc_graycounter1_q_next; + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + wishbone_interface_writer_stat_fifo_produce <= (wishbone_interface_writer_stat_fifo_produce + 1'd1); end - if (main_sram63_do_read) begin - main_sram58_consume <= (main_sram58_consume + 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_consume <= (wishbone_interface_writer_stat_fifo_consume + 1'd1); end - if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin - if ((~main_sram63_do_read)) begin - main_sram55_level <= (main_sram55_level + 1'd1); + if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin + if ((~wishbone_interface_writer_stat_fifo_do_read)) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level + 1'd1); end end else begin - if (main_sram63_do_read) begin - main_sram55_level <= (main_sram55_level - 1'd1); + if (wishbone_interface_writer_stat_fifo_do_read) begin + wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level - 1'd1); end end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin - main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + liteethmacsramwriter_state <= liteethmacsramwriter_next_state; + if (wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce) begin + wishbone_interface_writer_length <= wishbone_interface_writer_length_liteethmacsramwriter_t_next_value; end - if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin - main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + if (wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce) begin + wishbone_interface_writer_errors_status <= wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value; end - if (main_slot_liteethmacsramwriter_next_value_ce) begin - main_slot <= main_slot_liteethmacsramwriter_next_value; + if (wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce) begin + wishbone_interface_writer_slot <= wishbone_interface_writer_slot_liteethmacsramwriter_next_value; end - if (main_sram108_clear) begin - main_sram106_pending <= 1'd0; + if (wishbone_interface_reader_eventsourcepulse_clear) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; end - if (main_sram107_trigger) begin - main_sram106_pending <= 1'd1; + if (wishbone_interface_reader_eventsourcepulse_trigger) begin + wishbone_interface_reader_eventsourcepulse_pending <= 1'd1; end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - main_sram143_produce <= (main_sram143_produce + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + wishbone_interface_reader_cmd_fifo_produce <= (wishbone_interface_reader_cmd_fifo_produce + 1'd1); end - if (main_sram149_do_read) begin - main_sram144_consume <= (main_sram144_consume + 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_consume <= (wishbone_interface_reader_cmd_fifo_consume + 1'd1); end - if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin - if ((~main_sram149_do_read)) begin - main_sram141_level <= (main_sram141_level + 1'd1); + if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin + if ((~wishbone_interface_reader_cmd_fifo_do_read)) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level + 1'd1); end end else begin - if (main_sram149_do_read) begin - main_sram141_level <= (main_sram141_level - 1'd1); + if (wishbone_interface_reader_cmd_fifo_do_read) begin + wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level - 1'd1); end end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_sram122_length_liteethmacsramreader_next_value_ce) begin - main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + liteethmacsramreader_state <= liteethmacsramreader_next_state; + if (wishbone_interface_reader_length_liteethmacsramreader_next_value_ce) begin + wishbone_interface_reader_length <= wishbone_interface_reader_length_liteethmacsramreader_next_value; end - main_interface0_ack <= 1'd0; - if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin - main_interface0_ack <= 1'd1; + wishbone_interface_interface0_ack <= 1'd0; + if (((wishbone_interface_interface0_cyc & wishbone_interface_interface0_stb) & ((~wishbone_interface_interface0_ack) | wishbone_interface_sram0_adr_burst))) begin + wishbone_interface_interface0_ack <= 1'd1; end - main_interface1_ack <= 1'd0; - if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin - main_interface1_ack <= 1'd1; + wishbone_interface_interface1_ack <= 1'd0; + if (((wishbone_interface_interface1_cyc & wishbone_interface_interface1_stb) & ((~wishbone_interface_interface1_ack) | wishbone_interface_sram1_adr_burst))) begin + wishbone_interface_interface1_ack <= 1'd1; end - main_interface2_ack <= 1'd0; - if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin - main_interface2_ack <= 1'd1; + wishbone_interface_decoder0_slave_sel_r <= wishbone_interface_decoder0_slave_sel; + wishbone_interface_interface2_ack <= 1'd0; + if (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & ((~wishbone_interface_interface2_ack) | wishbone_interface_sram2_adr_burst))) begin + wishbone_interface_interface2_ack <= 1'd1; end - main_interface3_ack <= 1'd0; - if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin - main_interface3_ack <= 1'd1; + wishbone_interface_interface3_ack <= 1'd0; + if (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & ((~wishbone_interface_interface3_ack) | wishbone_interface_sram3_adr_burst))) begin + wishbone_interface_interface3_ack <= 1'd1; end - main_slave_sel_r <= main_slave_sel; - builder_wishbone2csr_state <= builder_wishbone2csr_next_state; - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) + wishbone_interface_decoder1_slave_sel_r <= wishbone_interface_decoder1_slave_sel; + wishbone2csr_state <= wishbone2csr_next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + interface0_bank_bus_dat_r <= csrbank0_reset0_w; end 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; end 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; end endcase end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + if (csrbank0_reset0_re) begin + maccore_maccore_reset_storage <= csrbank0_reset0_r; end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + maccore_maccore_reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + maccore_maccore_scratch_storage <= csrbank0_scratch0_r; end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) + maccore_maccore_scratch_re <= csrbank0_scratch0_re; + maccore_maccore_bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_slot_w; end 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_length_w; end 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_errors_w; end 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_status_w; end 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_pending_w; end 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_enable0_w; end 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_start_w; + interface1_bank_bus_dat_r <= wishbone_interface_reader_start_w; end 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ready_w; end 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_level_w; end 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_slot0_w; end 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_length0_w; end 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_status_w; end 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_pending_w; end 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_enable0_w; end 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + interface1_bank_bus_dat_r <= csrbank1_preamble_crc_w; end 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_preamble_errors_w; end 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + interface1_bank_bus_dat_r <= csrbank1_rx_datapath_crc_errors_w; end endcase end - main_sram9_re <= builder_csrbank1_sram_writer_slot_re; - main_sram12_re <= builder_csrbank1_sram_writer_length_re; - main_sram15_re <= builder_csrbank1_sram_writer_errors_re; - main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + wishbone_interface_writer_slot_re <= csrbank1_sram_writer_slot_re; + wishbone_interface_writer_length_re <= csrbank1_sram_writer_length_re; + wishbone_interface_writer_errors_re <= csrbank1_sram_writer_errors_re; + wishbone_interface_writer_status_re <= csrbank1_sram_writer_ev_status_re; + if (csrbank1_sram_writer_ev_pending_re) begin + wishbone_interface_writer_pending_r <= csrbank1_sram_writer_ev_pending_r; end - main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + wishbone_interface_writer_pending_re <= csrbank1_sram_writer_ev_pending_re; + if (csrbank1_sram_writer_ev_enable0_re) begin + wishbone_interface_writer_enable_storage <= csrbank1_sram_writer_ev_enable0_r; end - main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_sram96_re <= builder_csrbank1_sram_reader_ready_re; - main_sram99_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + wishbone_interface_writer_enable_re <= csrbank1_sram_writer_ev_enable0_re; + wishbone_interface_reader_ready_re <= csrbank1_sram_reader_ready_re; + wishbone_interface_reader_level_re <= csrbank1_sram_reader_level_re; + if (csrbank1_sram_reader_slot0_re) begin + wishbone_interface_reader_slot_storage <= csrbank1_sram_reader_slot0_r; end - main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + wishbone_interface_reader_slot_re <= csrbank1_sram_reader_slot0_re; + if (csrbank1_sram_reader_length0_re) begin + wishbone_interface_reader_length_storage <= csrbank1_sram_reader_length0_r; end - main_sram103_re <= builder_csrbank1_sram_reader_length0_re; - main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + wishbone_interface_reader_length_re <= csrbank1_sram_reader_length0_re; + wishbone_interface_reader_status_re <= csrbank1_sram_reader_ev_status_re; + if (csrbank1_sram_reader_ev_pending_re) begin + wishbone_interface_reader_pending_r <= csrbank1_sram_reader_ev_pending_r; end - main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + wishbone_interface_reader_pending_re <= csrbank1_sram_reader_ev_pending_re; + if (csrbank1_sram_reader_ev_enable0_re) begin + wishbone_interface_reader_enable_storage <= csrbank1_sram_reader_ev_enable0_r; end - main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) + wishbone_interface_reader_enable_re <= csrbank1_sram_reader_ev_enable0_re; + core_re <= csrbank1_preamble_crc_re; + core_preamble_errors_re <= csrbank1_rx_datapath_preamble_errors_re; + core_crc_errors_re <= csrbank1_rx_datapath_crc_errors_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mode_detection_mode_w; + interface2_bank_bus_dat_r <= csrbank2_mode_detection_mode_w; end 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + interface2_bank_bus_dat_r <= csrbank2_crg_reset0_w; end 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_w0_w; end 2'd3: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + interface2_bank_bus_dat_r <= csrbank2_mdio_r_w; end endcase end - main_maccore_ethphy_mode_re <= builder_csrbank2_mode_detection_mode_re; - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + maccore_ethphy_mode_re <= csrbank2_mode_detection_mode_re; + if (csrbank2_crg_reset0_re) begin + maccore_ethphy_reset_storage <= csrbank2_crg_reset0_r; end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + maccore_ethphy_reset_re <= csrbank2_crg_reset0_re; + if (csrbank2_mdio_w0_re) begin + maccore_ethphy__w_storage <= csrbank2_mdio_w0_r; end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + maccore_ethphy__w_re <= csrbank2_mdio_w0_re; + maccore_ethphy__r_re <= csrbank2_mdio_r_re; if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_mode0 <= 1'd0; - main_maccore_ethphy_mode_re <= 1'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy_counter <= 9'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_sram9_re <= 1'd0; - main_sram12_re <= 1'd0; - main_sram13_status <= 32'd0; - main_sram15_re <= 1'd0; - main_sram24_re <= 1'd0; - main_sram28_re <= 1'd0; - main_sram29_r <= 1'd0; - main_sram31_storage <= 1'd0; - main_sram32_re <= 1'd0; - main_slot <= 1'd0; - main_sram35_length <= 11'd0; - main_sram55_level <= 2'd0; - main_sram57_produce <= 1'd0; - main_sram58_consume <= 1'd0; - main_sram96_re <= 1'd0; - main_sram99_re <= 1'd0; - main_sram101_re <= 1'd0; - main_sram103_re <= 1'd0; - main_sram106_pending <= 1'd0; - main_sram112_re <= 1'd0; - main_sram116_re <= 1'd0; - main_sram117_r <= 1'd0; - main_sram119_storage <= 1'd0; - main_sram120_re <= 1'd0; - main_sram122_length <= 11'd0; - main_sram141_level <= 2'd0; - main_sram143_produce <= 1'd0; - main_sram144_consume <= 1'd0; - main_interface0_ack <= 1'd0; - main_interface1_ack <= 1'd0; - main_interface2_ack <= 1'd0; - main_interface3_ack <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_liteethphygmiimii_state <= 2'd0; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_wishbone2csr_state <= 1'd0; + maccore_maccore_reset_storage <= 2'd0; + maccore_maccore_reset_re <= 1'd0; + maccore_maccore_scratch_storage <= 32'd305419896; + maccore_maccore_scratch_re <= 1'd0; + maccore_maccore_bus_errors_re <= 1'd0; + maccore_maccore_bus_errors <= 32'd0; + maccore_ethphy_mode0 <= 1'd0; + maccore_ethphy_mode_re <= 1'd0; + maccore_ethphy_reset_storage <= 1'd0; + maccore_ethphy_reset_re <= 1'd0; + maccore_ethphy_counter <= 9'd0; + maccore_ethphy__w_storage <= 3'd0; + maccore_ethphy__w_re <= 1'd0; + maccore_ethphy__r_re <= 1'd0; + core_re <= 1'd0; + core_tx_cdc_cdc_graycounter0_q <= 6'd0; + core_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + core_preamble_errors_status <= 32'd0; + core_preamble_errors_re <= 1'd0; + core_crc_errors_status <= 32'd0; + core_crc_errors_re <= 1'd0; + core_rx_cdc_cdc_graycounter1_q <= 6'd0; + core_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + wishbone_interface_writer_slot_re <= 1'd0; + wishbone_interface_writer_length_re <= 1'd0; + wishbone_interface_writer_errors_status <= 32'd0; + wishbone_interface_writer_errors_re <= 1'd0; + wishbone_interface_writer_status_re <= 1'd0; + wishbone_interface_writer_pending_re <= 1'd0; + wishbone_interface_writer_pending_r <= 1'd0; + wishbone_interface_writer_enable_storage <= 1'd0; + wishbone_interface_writer_enable_re <= 1'd0; + wishbone_interface_writer_slot <= 1'd0; + wishbone_interface_writer_length <= 11'd0; + wishbone_interface_writer_stat_fifo_level <= 2'd0; + wishbone_interface_writer_stat_fifo_produce <= 1'd0; + wishbone_interface_writer_stat_fifo_consume <= 1'd0; + wishbone_interface_reader_ready_re <= 1'd0; + wishbone_interface_reader_level_re <= 1'd0; + wishbone_interface_reader_slot_re <= 1'd0; + wishbone_interface_reader_length_re <= 1'd0; + wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; + wishbone_interface_reader_status_re <= 1'd0; + wishbone_interface_reader_pending_re <= 1'd0; + wishbone_interface_reader_pending_r <= 1'd0; + wishbone_interface_reader_enable_storage <= 1'd0; + wishbone_interface_reader_enable_re <= 1'd0; + wishbone_interface_reader_length <= 11'd0; + wishbone_interface_reader_cmd_fifo_level <= 2'd0; + wishbone_interface_reader_cmd_fifo_produce <= 1'd0; + wishbone_interface_reader_cmd_fifo_consume <= 1'd0; + wishbone_interface_interface0_ack <= 1'd0; + wishbone_interface_interface1_ack <= 1'd0; + wishbone_interface_decoder0_slave_sel_r <= 2'd0; + wishbone_interface_interface2_ack <= 1'd0; + wishbone_interface_interface3_ack <= 1'd0; + wishbone_interface_decoder1_slave_sel_r <= 2'd0; + slave_sel_r <= 3'd0; + count <= 20'd1000000; + liteethphygmiimii_state <= 2'd0; + liteethmacsramwriter_state <= 3'd0; + liteethmacsramreader_state <= 2'd0; + wishbone2csr_state <= 1'd0; end - builder_xilinxmultiregimpl00 <= main_maccore_ethphy_toggle_i; - builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; - builder_xilinxmultiregimpl10 <= main_maccore_ethphy_data_r; - builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; - builder_xilinxmultiregimpl30 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; - builder_xilinxmultiregimpl40 <= main_pulsesynchronizer0_toggle_i; - builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; - builder_xilinxmultiregimpl50 <= main_pulsesynchronizer1_toggle_i; - builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; - builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; + xilinxmultiregimpl00 <= maccore_ethphy_toggle_i; + xilinxmultiregimpl01 <= xilinxmultiregimpl00; + xilinxmultiregimpl10 <= maccore_ethphy_data_r; + xilinxmultiregimpl11 <= xilinxmultiregimpl10; + xilinxmultiregimpl30 <= core_tx_cdc_cdc_graycounter1_q; + xilinxmultiregimpl31 <= xilinxmultiregimpl30; + xilinxmultiregimpl40 <= core_pulsesynchronizer0_toggle_i; + xilinxmultiregimpl41 <= xilinxmultiregimpl40; + xilinxmultiregimpl50 <= core_pulsesynchronizer1_toggle_i; + xilinxmultiregimpl51 <= xilinxmultiregimpl50; + xilinxmultiregimpl60 <= core_rx_cdc_cdc_graycounter0_q; + xilinxmultiregimpl61 <= xilinxmultiregimpl60; end @@ -4158,14 +4084,14 @@ BUFG BUFG( //------------------------------------------------------------------------------ BUFG BUFG_1( // Inputs. - .I (main_maccore_ethphy_eth_tx_clk), + .I (maccore_ethphy_eth_tx_clk), // Outputs. .O (eth_tx_clk) ); -assign gmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = gmii_mdio; +assign gmii_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz; +assign maccore_ethphy_data_r = gmii_mdio; //------------------------------------------------------------------------------ // Memory storage: 32-words x 42-bit @@ -4176,15 +4102,15 @@ reg [41:0] storage[0:31]; reg [41:0] storage_dat0; reg [41:0] storage_dat1; always @(posedge sys_clk) begin - if (main_tx_cdc_cdc_wrport_we) - storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; + if (core_tx_cdc_cdc_wrport_we) + storage[core_tx_cdc_cdc_wrport_adr] <= core_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[core_tx_cdc_cdc_wrport_adr]; end always @(posedge eth_tx_clk) begin - storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; + storage_dat1 <= storage[core_tx_cdc_cdc_rdport_adr]; end -assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; -assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; +assign core_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign core_tx_cdc_cdc_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ @@ -4195,14 +4121,14 @@ assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; reg [11:0] storage_1[0:4]; reg [11:0] storage_1_dat0; always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; + if (core_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr] <= core_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr]; end always @(posedge eth_rx_clk) begin end -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; +assign core_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign core_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[core_liteethmaccrc32checker_syncfifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4214,15 +4140,15 @@ reg [41:0] storage_2[0:31]; reg [41:0] storage_2_dat0; reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin - if (main_rx_cdc_cdc_wrport_we) - storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; + if (core_rx_cdc_cdc_wrport_we) + storage_2[core_rx_cdc_cdc_wrport_adr] <= core_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[core_rx_cdc_cdc_wrport_adr]; end always @(posedge sys_clk) begin - storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; + storage_2_dat1 <= storage_2[core_rx_cdc_cdc_rdport_adr]; end -assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; +assign core_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign core_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; //------------------------------------------------------------------------------ @@ -4233,14 +4159,14 @@ assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; reg [13:0] storage_3[0:1]; reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_sram61_we) - storage_3[main_sram59_adr] <= main_sram62_dat_w; - storage_3_dat0 <= storage_3[main_sram59_adr]; + if (wishbone_interface_writer_stat_fifo_wrport_we) + storage_3[wishbone_interface_writer_stat_fifo_wrport_adr] <= wishbone_interface_writer_stat_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[wishbone_interface_writer_stat_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram60_dat_r = storage_3_dat0; -assign main_sram65_dat_r = storage_3[main_sram64_adr]; +assign wishbone_interface_writer_stat_fifo_wrport_dat_r = storage_3_dat0; +assign wishbone_interface_writer_stat_fifo_rdport_dat_r = storage_3[wishbone_interface_writer_stat_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4252,15 +4178,15 @@ reg [31:0] mem[0:382]; reg [8:0] mem_adr0; reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_sram77_we) - mem[main_sram75_adr] <= main_sram78_dat_w; - mem_adr0 <= main_sram75_adr; + if (wishbone_interface_writer_memory0_we) + mem[wishbone_interface_writer_memory0_adr] <= wishbone_interface_writer_memory0_dat_w; + mem_adr0 <= wishbone_interface_writer_memory0_adr; end always @(posedge sys_clk) begin - mem_dat1 <= mem[main_sram0_adr]; + mem_dat1 <= mem[wishbone_interface_sram0_adr]; end -assign main_sram76_dat_r = mem[mem_adr0]; -assign main_sram0_dat_r = mem_dat1; +assign wishbone_interface_writer_memory0_dat_r = mem[mem_adr0]; +assign wishbone_interface_sram0_dat_r = mem_dat1; //------------------------------------------------------------------------------ @@ -4272,15 +4198,15 @@ reg [31:0] mem_1[0:382]; reg [8:0] mem_1_adr0; reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_sram81_we) - mem_1[main_sram79_adr] <= main_sram82_dat_w; - mem_1_adr0 <= main_sram79_adr; + if (wishbone_interface_writer_memory1_we) + mem_1[wishbone_interface_writer_memory1_adr] <= wishbone_interface_writer_memory1_dat_w; + mem_1_adr0 <= wishbone_interface_writer_memory1_adr; end always @(posedge sys_clk) begin - mem_1_dat1 <= mem_1[main_sram1_adr]; + mem_1_dat1 <= mem_1[wishbone_interface_sram1_adr]; end -assign main_sram80_dat_r = mem_1[mem_1_adr0]; -assign main_sram1_dat_r = mem_1_dat1; +assign wishbone_interface_writer_memory1_dat_r = mem_1[mem_1_adr0]; +assign wishbone_interface_sram1_dat_r = mem_1_dat1; //------------------------------------------------------------------------------ @@ -4291,14 +4217,14 @@ assign main_sram1_dat_r = mem_1_dat1; reg [13:0] storage_4[0:1]; reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_sram147_we) - storage_4[main_sram145_adr] <= main_sram148_dat_w; - storage_4_dat0 <= storage_4[main_sram145_adr]; + if (wishbone_interface_reader_cmd_fifo_wrport_we) + storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr] <= wishbone_interface_reader_cmd_fifo_wrport_dat_w; + storage_4_dat0 <= storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr]; end always @(posedge sys_clk) begin end -assign main_sram146_dat_r = storage_4_dat0; -assign main_sram151_dat_r = storage_4[main_sram150_adr]; +assign wishbone_interface_reader_cmd_fifo_wrport_dat_r = storage_4_dat0; +assign wishbone_interface_reader_cmd_fifo_rdport_dat_r = storage_4[wishbone_interface_reader_cmd_fifo_rdport_adr]; //------------------------------------------------------------------------------ @@ -4310,22 +4236,22 @@ reg [31:0] mem_2[0:382]; reg [31:0] mem_2_dat0; reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - if (main_sram163_re) - mem_2_dat0 <= mem_2[main_sram161_adr]; + if (wishbone_interface_reader_memory0_re) + mem_2_dat0 <= mem_2[wishbone_interface_reader_memory0_adr]; end always @(posedge sys_clk) begin - if (main_sram2_we[0]) - mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; - if (main_sram2_we[1]) - mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; - if (main_sram2_we[2]) - mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; - if (main_sram2_we[3]) - mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; - mem_2_adr1 <= main_sram2_adr; + if (wishbone_interface_sram2_we[0]) + mem_2[wishbone_interface_sram2_adr][7:0] <= wishbone_interface_sram2_dat_w[7:0]; + if (wishbone_interface_sram2_we[1]) + mem_2[wishbone_interface_sram2_adr][15:8] <= wishbone_interface_sram2_dat_w[15:8]; + if (wishbone_interface_sram2_we[2]) + mem_2[wishbone_interface_sram2_adr][23:16] <= wishbone_interface_sram2_dat_w[23:16]; + if (wishbone_interface_sram2_we[3]) + mem_2[wishbone_interface_sram2_adr][31:24] <= wishbone_interface_sram2_dat_w[31:24]; + mem_2_adr1 <= wishbone_interface_sram2_adr; end -assign main_sram162_dat_r = mem_2_dat0; -assign main_sram2_dat_r = mem_2[mem_2_adr1]; +assign wishbone_interface_reader_memory0_dat_r = mem_2_dat0; +assign wishbone_interface_sram2_dat_r = mem_2[mem_2_adr1]; //------------------------------------------------------------------------------ @@ -4337,22 +4263,22 @@ reg [31:0] mem_3[0:382]; reg [31:0] mem_3_dat0; reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - if (main_sram166_re) - mem_3_dat0 <= mem_3[main_sram164_adr]; + if (wishbone_interface_reader_memory1_re) + mem_3_dat0 <= mem_3[wishbone_interface_reader_memory1_adr]; end always @(posedge sys_clk) begin - if (main_sram3_we[0]) - mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; - if (main_sram3_we[1]) - mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; - if (main_sram3_we[2]) - mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; - if (main_sram3_we[3]) - mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; - mem_3_adr1 <= main_sram3_adr; + if (wishbone_interface_sram3_we[0]) + mem_3[wishbone_interface_sram3_adr][7:0] <= wishbone_interface_sram3_dat_w[7:0]; + if (wishbone_interface_sram3_we[1]) + mem_3[wishbone_interface_sram3_adr][15:8] <= wishbone_interface_sram3_dat_w[15:8]; + if (wishbone_interface_sram3_we[2]) + mem_3[wishbone_interface_sram3_adr][23:16] <= wishbone_interface_sram3_dat_w[23:16]; + if (wishbone_interface_sram3_we[3]) + mem_3[wishbone_interface_sram3_adr][31:24] <= wishbone_interface_sram3_dat_w[31:24]; + mem_3_adr1 <= wishbone_interface_sram3_adr; end -assign main_sram165_dat_r = mem_3_dat0; -assign main_sram3_dat_r = mem_3[mem_3_adr1]; +assign wishbone_interface_reader_memory1_dat_r = mem_3_dat0; +assign wishbone_interface_sram3_dat_r = mem_3[mem_3_adr1]; //------------------------------------------------------------------------------ @@ -4366,7 +4292,7 @@ ODDR #( .C (eth_tx_clk), .CE (1'd1), .D1 (1'd1), - .D2 ((main_maccore_ethphy_mode0 == 1'd1)), + .D2 ((maccore_ethphy_mode0 == 1'd1)), .R (1'd0), .S (1'd0), @@ -4386,10 +4312,10 @@ FDPE #( .C (eth_tx_clk), .CE (1'd1), .D (1'd0), - .PRE (main_maccore_ethphy_reset0), + .PRE (maccore_ethphy_reset0), // Outputs. - .Q (builder_rst_meta0) + .Q (rst_meta0) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4403,8 +4329,8 @@ FDPE #( // Inputs. .C (eth_tx_clk), .CE (1'd1), - .D (builder_rst_meta0), - .PRE (main_maccore_ethphy_reset0), + .D (rst_meta0), + .PRE (maccore_ethphy_reset0), // Outputs. .Q (eth_tx_rst) @@ -4422,10 +4348,10 @@ FDPE #( .C (eth_rx_clk), .CE (1'd1), .D (1'd0), - .PRE (main_maccore_ethphy_reset0), + .PRE (maccore_ethphy_reset0), // Outputs. - .Q (builder_rst_meta1) + .Q (rst_meta1) ); (* ars_ff2 = "true", async_reg = "true" *) @@ -4439,8 +4365,8 @@ FDPE #( // Inputs. .C (eth_rx_clk), .CE (1'd1), - .D (builder_rst_meta1), - .PRE (main_maccore_ethphy_reset0), + .D (rst_meta1), + .PRE (maccore_ethphy_reset0), // Outputs. .Q (eth_rx_rst) @@ -4449,5 +4375,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-05 17:38:50. +// Auto-Generated by LiteX on 2025-02-15 16:17:45. //------------------------------------------------------------------------------ From 3fb0a9ed26a7d863803542dc1f64bec5ca0b182d Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 15 Feb 2025 19:55:15 +1100 Subject: [PATCH 2/3] litedram: Update generated code Signed-off-by: Paul Mackerras --- .../acorn-cle-215/litedram_core.init | 1773 ++++++------ .../generated/acorn-cle-215/litedram_core.v | 2321 +++++++-------- litedram/generated/arty/litedram_core.init | 1773 ++++++------ litedram/generated/arty/litedram_core.v | 2005 ++++++------- litedram/generated/ecpix-5/litedram_core.init | 1052 +++---- litedram/generated/ecpix-5/litedram_core.v | 1447 +++++----- .../generated/genesys2/litedram_core.init | 2498 +++++++++-------- litedram/generated/genesys2/litedram_core.v | 1819 ++++++------ .../generated/nexys-video/litedram_core.init | 1773 ++++++------ .../generated/nexys-video/litedram_core.v | 2109 +++++++------- .../orangecrab-85-0.2/litedram_core.init | 2154 +++++++------- .../orangecrab-85-0.2/litedram_core.v | 1449 +++++----- litedram/generated/sim/litedram_core.init | 1559 +++++----- litedram/generated/sim/litedram_core.v | 1775 ++++++------ .../generated/wukong-v2/litedram_core.init | 1773 ++++++------ litedram/generated/wukong-v2/litedram_core.v | 2005 ++++++------- 16 files changed, 14841 insertions(+), 14444 deletions(-) diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init index 0573632..843a495 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.init +++ b/litedram/generated/acorn-cle-215/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3920000039406004 +3920000239406004 7c0004ac654ac000 -600000007d2057aa +4e8000207d2057aa +0000000000000000 +3940600400000000 +654ac00039200000 +7d2057aa7c0004ac 6000000060000000 6000000060000000 -000000004e800020 +4e80002060000000 0000000000000000 -3842adc83c4c0001 +3c4c000100000000 +7c0802a63842aea4 +f821ffc148002885 +3ba000053bc06000 +4bffff8567dec000 +7fa0f7aa7c0004ac +7fe0f6aa7c0004ac +73ff00014bffff95 +382100404082ffe4 +000000004800289c +0000038001000000 +3842ae503c4c0001 fbe1fff87c0802a6 f821ff51f8010010 f8a100e0f88100d8 @@ -525,11 +540,11 @@ f8a100e0f88100d8 38610020f8c100e8 f8e100f038c100d8 f9210100f90100f8 -48002175f9410108 +480021b9f9410108 7c7f1b7860000000 -48001bc538610020 +48001c1538610020 382100b060000000 -480027e87fe3fb78 +480028447fe3fb78 0100000000000000 4e80002000000180 0000000000000000 @@ -537,273 +552,284 @@ f9210100f90100f8 4e8000204c00012c 0000000000000000 3c4c000100000000 -7c0802a63842ad2c -480027217d600026 -f821fed191610008 -6000000048001bc1 -38637a983c62ffff -3c80c0004bffff41 -7c0004ac78840020 +7c0802a63842adb4 +480027797d600026 +f821fec191610008 +6000000048001c11 +38637a683c62ffff +388000034bffff41 +7c0004ac7884f000 3c62ffff7c8026ea -38637ab83be00008 +38637a883be00008 4bffff1d67ffc000 -38637ad83c62ffff +38637aa83c62ffff 7c0004ac4bffff11 73e900017fe0feea 3c62ffff41820010 -4bfffef538637af0 +4bfffef538637ac0 4e00000073e90002 3c62ffff41820010 -4bfffedd38637af8 +4bfffedd38637ac8 4d80000073e90004 3c62ffff41820010 -4bfffec538637b00 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+5529063e3928ffd0 +4181fd7028090009 +3b7b00017b690020 +990900207d214a14 +3b0000084bfffd5c +3a8000204bfffd54 +4bfffbc03b410041 +3bde0001995e0000 +fbc100607d1d4378 +000000004bfffa44 +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1853,14 +1879,18 @@ e8010010ebc1fff0 696c62616e652020 004441555120676e 006e6f7263694d20 +0000004953534920 +696c62616e655b20 +5d6461757120676e +0000000000000000 4920646175715b20 005d65646f6d204f 414c462049505320 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1921,15 +1951,13 @@ e8010010ebc1fff0 000000000000207c 203a747365622020 302562202c64256d -6000000000206432 +0000000000206432 76656c2064616552 000a3a676e696c65 696c616974696e49 52445320676e697a 3025783040204d41 000a2e2e2e786c38 -000000540000002a -6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 @@ -1971,11 +1999,12 @@ e8010010ebc1fff0 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v index 6125302..ea9fd89 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.v +++ b/litedram/generated/acorn-cle-215/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:09 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:45 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -83,15 +83,15 @@ LiteDRAMCore │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [FDCE] +│ │ └─── [PLLE2_ADV] +│ │ └─── [BUFG] │ │ └─── [BUFG] │ │ └─── [BUFG] │ │ └─── [BUFG] -│ │ └─── [PLLE2_ADV] -│ │ └─── [FDCE] -│ │ └─── [FDCE] │ └─── idelayctrl (S7IDELAYCTRL) │ │ └─── [IDELAYCTRL] └─── ddrphy (A7DDRPHY) @@ -136,103 +136,103 @@ LiteDRAMCore │ └─── bitslip_35* (BitSlip) │ └─── tappeddelayline_2* (TappedDelayLine) │ └─── tappeddelayline_3* (TappedDelayLine) -│ └─── [IDELAYE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [OBUFDS] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [IDELAYE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] │ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [ISERDESE2] -│ └─── [IOBUFDS] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IOBUFDS] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] +│ └─── [OBUFDS] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) @@ -545,6 +545,7 @@ wire [29:0] builder_interface0_adr; wire [13:0] builder_interface0_bank_bus_adr; reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_re; wire builder_interface0_bank_bus_we; wire [1:0] builder_interface0_bte; wire [2:0] builder_interface0_cti; @@ -561,17 +562,22 @@ reg builder_interface1_adr_next_value_ce1 = 1'd0; wire [13:0] builder_interface1_bank_bus_adr; reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_re; wire builder_interface1_bank_bus_we; wire [31:0] builder_interface1_dat_r; reg [31:0] builder_interface1_dat_w = 32'd0; reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_re = 1'd0; +reg builder_interface1_re_next_value2 = 1'd0; +reg builder_interface1_re_next_value_ce2 = 1'd0; reg builder_interface1_we = 1'd0; -reg builder_interface1_we_next_value2 = 1'd0; -reg builder_interface1_we_next_value_ce2 = 1'd0; +reg builder_interface1_we_next_value3 = 1'd0; +reg builder_interface1_we_next_value_ce3 = 1'd0; wire [13:0] builder_interface2_bank_bus_adr; reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_re; wire builder_interface2_bank_bus_we; reg builder_locked0 = 1'd0; reg builder_locked1 = 1'd0; @@ -596,6 +602,7 @@ reg builder_new_master_wdata_ready0 = 1'd0; reg builder_new_master_wdata_ready1 = 1'd0; reg [1:0] builder_next_state = 2'd0; wire builder_pll_fb; +wire builder_re; reg [1:0] builder_refresher_next_state = 2'd0; reg [1:0] builder_refresher_state = 2'd0; wire builder_reset0; @@ -702,14 +709,14 @@ reg builder_t_self3 = 1'd0; reg builder_t_self4 = 1'd0; reg builder_t_self5 = 1'd0; wire builder_we; -wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1; wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2; wire builder_xilinxasyncresetsynchronizerimpl2_expr; wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_expr; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; @@ -1897,9 +1904,9 @@ reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; wire [15:0] main_litedramcore_csr_dfi_p0_address; wire [2:0] main_litedramcore_csr_dfi_p0_bank; reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +wire main_litedramcore_csr_dfi_p0_cke; reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +wire main_litedramcore_csr_dfi_p0_odt; reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; wire main_litedramcore_csr_dfi_p0_rddata_en; @@ -1913,9 +1920,9 @@ reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; wire [15:0] main_litedramcore_csr_dfi_p1_address; wire [2:0] main_litedramcore_csr_dfi_p1_bank; reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +wire main_litedramcore_csr_dfi_p1_cke; reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +wire main_litedramcore_csr_dfi_p1_odt; reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; wire main_litedramcore_csr_dfi_p1_rddata_en; @@ -1929,9 +1936,9 @@ reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; wire [15:0] main_litedramcore_csr_dfi_p2_address; wire [2:0] main_litedramcore_csr_dfi_p2_bank; reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +wire main_litedramcore_csr_dfi_p2_cke; reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +wire main_litedramcore_csr_dfi_p2_odt; reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; wire main_litedramcore_csr_dfi_p2_rddata_en; @@ -1945,9 +1952,9 @@ reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; wire [15:0] main_litedramcore_csr_dfi_p3_address; wire [2:0] main_litedramcore_csr_dfi_p3_bank; reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +wire main_litedramcore_csr_dfi_p3_cke; reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +wire main_litedramcore_csr_dfi_p3_odt; reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; wire main_litedramcore_csr_dfi_p3_rddata_en; @@ -3865,42 +3872,6 @@ assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_ assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en; assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata; assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid; -always @(*) begin - main_litedramcore_master_p3_ras_n <= 1'd1; - if (main_litedramcore_sel) begin - if (main_litedramcore_ext_dfi_sel) begin - main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; - end else begin - main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; - end - end else begin - main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - main_litedramcore_master_p3_we_n <= 1'd1; - if (main_litedramcore_sel) begin - if (main_litedramcore_ext_dfi_sel) begin - main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; - end else begin - main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; - end - end else begin - main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - main_litedramcore_master_p3_cke <= 1'd0; - if (main_litedramcore_sel) begin - if (main_litedramcore_ext_dfi_sel) begin - main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; - end else begin - main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; - end - end else begin - main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; - end -end always @(*) begin main_litedramcore_master_p3_odt <= 1'd0; if (main_litedramcore_sel) begin @@ -4766,41 +4737,61 @@ always @(*) begin end end always @(*) begin - main_litedramcore_csr_dfi_p0_cke <= 1'd0; - main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_cke <= 1'd0; - main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_cke <= 1'd0; - main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_cke <= 1'd0; - main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p0_odt <= 1'd0; - main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_odt <= 1'd0; - main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; + main_litedramcore_master_p3_ras_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_ext_dfi_p3_ras_n; + end else begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n; + end + end else begin + main_litedramcore_master_p3_ras_n <= main_litedramcore_csr_dfi_p3_ras_n; + end end always @(*) begin - main_litedramcore_csr_dfi_p2_odt <= 1'd0; - main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; + main_litedramcore_master_p3_we_n <= 1'd1; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_we_n <= main_litedramcore_ext_dfi_p3_we_n; + end else begin + main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n; + end + end else begin + main_litedramcore_master_p3_we_n <= main_litedramcore_csr_dfi_p3_we_n; + end end always @(*) begin - main_litedramcore_csr_dfi_p3_odt <= 1'd0; - main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; + main_litedramcore_master_p3_cke <= 1'd0; + if (main_litedramcore_sel) begin + if (main_litedramcore_ext_dfi_sel) begin + main_litedramcore_master_p3_cke <= main_litedramcore_ext_dfi_p3_cke; + end else begin + main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke; + end + end else begin + main_litedramcore_master_p3_cke <= main_litedramcore_csr_dfi_p3_cke; + end end +assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt; assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); + end else begin + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4833,20 +4824,20 @@ always @(*) begin main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); - end else begin - main_litedramcore_csr_dfi_p0_we_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); + end else begin + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4879,20 +4870,20 @@ always @(*) begin main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); - end else begin - main_litedramcore_csr_dfi_p1_we_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); + end else begin + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4925,20 +4916,20 @@ always @(*) begin main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); - end else begin - main_litedramcore_csr_dfi_p2_we_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); + end else begin + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4971,14 +4962,6 @@ always @(*) begin main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); - end else begin - main_litedramcore_csr_dfi_p3_we_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); @@ -5086,22 +5069,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; - case (builder_refresher_state) - 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) @@ -5168,6 +5135,22 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; @@ -5308,78 +5291,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_source_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_source_source_payload_we) begin - main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5739,6 +5651,77 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; @@ -5878,82 +5861,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_source_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_source_source_payload_we) begin - main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_source_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) @@ -6310,45 +6217,121 @@ always @(*) begin end endcase end -assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; -assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; -assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; -assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; -assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; -assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; -assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; -assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; -assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; -assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; -assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); -assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); -assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[22:7]); -assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; -always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; - if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin - main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7]; - end else begin - main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); - end -end -assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); -assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); -assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); always @(*) begin - main_litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin - if ((main_litedramcore_bankmachine2_source_payload_addr[22:7] != main_litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin - main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin end - end -end -assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; -assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; -assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; -assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; -assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; -assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); +assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[22:7]); +assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + main_litedramcore_bankmachine2_cmd_payload_a <= 16'd0; + if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin + main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_source_source_payload_addr[22:7]; + end else begin + main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write); +assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open); +always @(*) begin + main_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((main_litedramcore_bankmachine2_source_valid & main_litedramcore_bankmachine2_source_source_valid)) begin + if ((main_litedramcore_bankmachine2_source_payload_addr[22:7] != main_litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin + main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign main_litedramcore_bankmachine2_syncfifo2_din = {main_litedramcore_bankmachine2_fifo_in_last, main_litedramcore_bankmachine2_fifo_in_first, main_litedramcore_bankmachine2_fifo_in_payload_addr, main_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign {main_litedramcore_bankmachine2_fifo_out_last, main_litedramcore_bankmachine2_fifo_out_first, main_litedramcore_bankmachine2_fifo_out_payload_addr, main_litedramcore_bankmachine2_fifo_out_payload_we} = main_litedramcore_bankmachine2_syncfifo2_dout; +assign main_litedramcore_bankmachine2_sink_ready = main_litedramcore_bankmachine2_syncfifo2_writable; assign main_litedramcore_bankmachine2_syncfifo2_we = main_litedramcore_bankmachine2_sink_valid; assign main_litedramcore_bankmachine2_fifo_in_first = main_litedramcore_bankmachine2_sink_first; assign main_litedramcore_bankmachine2_fifo_in_last = main_litedramcore_bankmachine2_sink_last; @@ -6450,7 +6433,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_row_open <= 1'd0; + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6458,7 +6441,7 @@ always @(*) begin end 2'd3: begin if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_open <= 1'd1; + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6476,19 +6459,13 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6506,7 +6483,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_source_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6517,41 +6494,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_row_close <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -6569,9 +6523,12 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6593,7 +6550,10 @@ always @(*) begin if (main_litedramcore_bankmachine2_source_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6604,21 +6564,22 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6633,12 +6594,9 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6661,8 +6619,8 @@ always @(*) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin if (main_litedramcore_bankmachine2_source_source_payload_we) begin - main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6674,22 +6632,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6700,11 +6651,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6729,8 +6695,8 @@ always @(*) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; end else begin - main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6742,7 +6708,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6767,8 +6733,8 @@ always @(*) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin if (main_litedramcore_bankmachine2_source_source_payload_we) begin - main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6780,7 +6746,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6789,6 +6755,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6799,32 +6768,49 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_source_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_source_source_payload_we) begin - main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine2_row_open <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; end end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end endcase end always @(*) begin - main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6842,10 +6828,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_source_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; - end + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6856,18 +6839,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine2_twtpcon_ready) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -7020,32 +7003,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (builder_bankmachine3_state) @@ -7360,15 +7317,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine3_row_open <= 1'd0; + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_open <= 1'd1; + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7382,22 +7342,57 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + main_litedramcore_bankmachine3_row_close <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_row_open <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; + main_litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -7411,34 +7406,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_source_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine3_row_close <= 1'd0; + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin - main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7522,146 +7505,75 @@ assign main_litedramcore_bankmachine4_pipe_valid_sink_valid = main_litedramcore_ assign main_litedramcore_bankmachine4_sink_sink_ready = main_litedramcore_bankmachine4_pipe_valid_sink_ready; assign main_litedramcore_bankmachine4_pipe_valid_sink_first = main_litedramcore_bankmachine4_sink_sink_first; assign main_litedramcore_bankmachine4_pipe_valid_sink_last = main_litedramcore_bankmachine4_sink_sink_last; -assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; -assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; -assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; -assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; -assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; -assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; -assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; -assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; -always @(*) begin - builder_bankmachine4_next_state <= 4'd0; - builder_bankmachine4_next_state <= builder_bankmachine4_state; - case (builder_bankmachine4_state) - 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - if (main_litedramcore_bankmachine4_cmd_ready) begin - builder_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - builder_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - if (main_litedramcore_bankmachine4_cmd_ready) begin - builder_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~main_litedramcore_bankmachine4_refresh_req)) begin - builder_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - builder_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - builder_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - builder_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - builder_bankmachine4_next_state <= 1'd0; - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - builder_bankmachine4_next_state <= 3'd4; - end else begin - if (main_litedramcore_bankmachine4_source_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin - builder_bankmachine4_next_state <= 2'd2; - end - end else begin - builder_bankmachine4_next_state <= 1'd1; - end - end else begin - builder_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_we = main_litedramcore_bankmachine4_sink_sink_payload_we; +assign main_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine4_sink_sink_payload_addr; +assign main_litedramcore_bankmachine4_source_source_valid = main_litedramcore_bankmachine4_pipe_valid_source_valid; +assign main_litedramcore_bankmachine4_pipe_valid_source_ready = main_litedramcore_bankmachine4_source_source_ready; +assign main_litedramcore_bankmachine4_source_source_first = main_litedramcore_bankmachine4_pipe_valid_source_first; +assign main_litedramcore_bankmachine4_source_source_last = main_litedramcore_bankmachine4_pipe_valid_source_last; +assign main_litedramcore_bankmachine4_source_source_payload_we = main_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine4_source_source_payload_addr = main_litedramcore_bankmachine4_pipe_valid_source_payload_addr; always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + builder_bankmachine4_next_state <= 4'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; case (builder_bankmachine4_state) 1'd1: begin if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + if (main_litedramcore_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine4_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine4_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine4_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine4_next_state <= 1'd0; end default: begin if (main_litedramcore_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; end else begin if (main_litedramcore_bankmachine4_source_source_valid) begin if (main_litedramcore_bankmachine4_row_opened) begin if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_source_source_payload_we) begin - main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin + if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; end end else begin + builder_bankmachine4_next_state <= 1'd1; end end else begin + builder_bankmachine4_next_state <= 2'd3; end end end end endcase end -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (builder_bankmachine4_state) @@ -8023,6 +7935,77 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; @@ -8083,155 +8066,79 @@ always @(*) begin end assign main_litedramcore_bankmachine5_wrport_dat_w = main_litedramcore_bankmachine5_syncfifo5_din; assign main_litedramcore_bankmachine5_wrport_we = (main_litedramcore_bankmachine5_syncfifo5_we & (main_litedramcore_bankmachine5_syncfifo5_writable | main_litedramcore_bankmachine5_replace)); -assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); -assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; -assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; -assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); -assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); -assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); -assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; -assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; -assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; -assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; -assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; -assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; -assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; -assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; -assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; -assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; -assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; -assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; -always @(*) begin - builder_bankmachine5_next_state <= 4'd0; - builder_bankmachine5_next_state <= builder_bankmachine5_state; - case (builder_bankmachine5_state) - 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - if (main_litedramcore_bankmachine5_cmd_ready) begin - builder_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - builder_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - if (main_litedramcore_bankmachine5_cmd_ready) begin - builder_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~main_litedramcore_bankmachine5_refresh_req)) begin - builder_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - builder_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - builder_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - builder_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - builder_bankmachine5_next_state <= 1'd0; - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - builder_bankmachine5_next_state <= 3'd4; - end else begin - if (main_litedramcore_bankmachine5_source_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin - builder_bankmachine5_next_state <= 2'd2; - end - end else begin - builder_bankmachine5_next_state <= 1'd1; - end - end else begin - builder_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_source_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_source_source_payload_we) begin - main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end +assign main_litedramcore_bankmachine5_do_read = (main_litedramcore_bankmachine5_syncfifo5_readable & main_litedramcore_bankmachine5_syncfifo5_re); +assign main_litedramcore_bankmachine5_rdport_adr = main_litedramcore_bankmachine5_consume; +assign main_litedramcore_bankmachine5_syncfifo5_dout = main_litedramcore_bankmachine5_rdport_dat_r; +assign main_litedramcore_bankmachine5_syncfifo5_writable = (main_litedramcore_bankmachine5_level != 5'd16); +assign main_litedramcore_bankmachine5_syncfifo5_readable = (main_litedramcore_bankmachine5_level != 1'd0); +assign main_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~main_litedramcore_bankmachine5_pipe_valid_source_valid) | main_litedramcore_bankmachine5_pipe_valid_source_ready); +assign main_litedramcore_bankmachine5_pipe_valid_sink_valid = main_litedramcore_bankmachine5_sink_sink_valid; +assign main_litedramcore_bankmachine5_sink_sink_ready = main_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign main_litedramcore_bankmachine5_pipe_valid_sink_first = main_litedramcore_bankmachine5_sink_sink_first; +assign main_litedramcore_bankmachine5_pipe_valid_sink_last = main_litedramcore_bankmachine5_sink_sink_last; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_we = main_litedramcore_bankmachine5_sink_sink_payload_we; +assign main_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine5_sink_sink_payload_addr; +assign main_litedramcore_bankmachine5_source_source_valid = main_litedramcore_bankmachine5_pipe_valid_source_valid; +assign main_litedramcore_bankmachine5_pipe_valid_source_ready = main_litedramcore_bankmachine5_source_source_ready; +assign main_litedramcore_bankmachine5_source_source_first = main_litedramcore_bankmachine5_pipe_valid_source_first; +assign main_litedramcore_bankmachine5_source_source_last = main_litedramcore_bankmachine5_pipe_valid_source_last; +assign main_litedramcore_bankmachine5_source_source_payload_we = main_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine5_source_source_payload_addr = main_litedramcore_bankmachine5_pipe_valid_source_payload_addr; always @(*) begin - main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + builder_bankmachine5_next_state <= 4'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; case (builder_bankmachine5_state) 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end + end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin if (main_litedramcore_bankmachine5_source_source_valid) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end @@ -8594,6 +8501,82 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; @@ -8734,7 +8717,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_row_open <= 1'd0; + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -8742,7 +8725,7 @@ always @(*) begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_open <= 1'd1; + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8760,19 +8743,13 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8790,7 +8767,7 @@ always @(*) begin if (main_litedramcore_bankmachine6_source_source_valid) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8801,41 +8778,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_row_close <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -8853,9 +8807,12 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8877,7 +8834,10 @@ always @(*) begin if (main_litedramcore_bankmachine6_source_source_valid) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -8888,21 +8848,22 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8917,12 +8878,9 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -8945,8 +8903,8 @@ always @(*) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin if (main_litedramcore_bankmachine6_source_source_payload_we) begin - main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8958,22 +8916,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8984,11 +8935,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -9013,8 +8979,8 @@ always @(*) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; end else begin - main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9026,7 +8992,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -9051,8 +9017,8 @@ always @(*) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin if (main_litedramcore_bankmachine6_source_source_payload_we) begin - main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -9064,13 +9030,42 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -9083,32 +9078,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_source_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_source_source_payload_we) begin - main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9126,10 +9112,7 @@ always @(*) begin if (main_litedramcore_bankmachine6_source_source_valid) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; - end + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9140,18 +9123,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine6_twtpcon_ready) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9304,32 +9287,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) @@ -9644,15 +9601,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_row_open <= 1'd0; + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_open <= 1'd1; + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9666,22 +9626,57 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + main_litedramcore_bankmachine7_row_close <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine7_row_open <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + main_litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin @@ -9695,34 +9690,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_close <= 1'd0; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9899,151 +9882,86 @@ always @(*) begin main_litedramcore_choose_req_cmd_payload_cas <= builder_t_self3; end end -always @(*) begin - main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (main_litedramcore_choose_req_cmd_valid) begin - main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; - end -end -always @(*) begin - main_litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (main_litedramcore_choose_req_cmd_valid) begin - main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; - end -end -assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); -assign main_litedramcore_dfi_p0_reset_n = 1'd1; -assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; -assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; -assign main_litedramcore_dfi_p1_reset_n = 1'd1; -assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; -assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; -assign main_litedramcore_dfi_p2_reset_n = 1'd1; -assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; -assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; -assign main_litedramcore_dfi_p3_reset_n = 1'd1; -assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; -assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; -assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); -always @(*) begin - builder_multiplexer_next_state <= 4'd0; - builder_multiplexer_next_state <= builder_multiplexer_state; - case (builder_multiplexer_state) - 1'd1: begin - if (main_litedramcore_read_available) begin - if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin - builder_multiplexer_next_state <= 2'd3; - end - end - if (main_litedramcore_go_to_refresh) begin - builder_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (main_litedramcore_cmd_last) begin - builder_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (main_litedramcore_twtrcon_ready) begin - builder_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - builder_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - builder_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - builder_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - builder_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - builder_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - builder_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - builder_multiplexer_next_state <= 1'd1; - end - default: begin - if (main_litedramcore_write_available) begin - if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin - builder_multiplexer_next_state <= 3'd4; - end - end - if (main_litedramcore_go_to_refresh) begin - builder_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end - end - endcase +always @(*) begin + main_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_ras <= builder_t_self4; + end end always @(*) begin - main_litedramcore_en1 <= 1'd0; + main_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (main_litedramcore_choose_req_cmd_valid) begin + main_litedramcore_choose_req_cmd_payload_we <= builder_t_self5; + end +end +assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid)); +assign main_litedramcore_dfi_p0_reset_n = 1'd1; +assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer4}}; +assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer5}}; +assign main_litedramcore_dfi_p1_reset_n = 1'd1; +assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer6}}; +assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer7}}; +assign main_litedramcore_dfi_p2_reset_n = 1'd1; +assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer8}}; +assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer9}}; +assign main_litedramcore_dfi_p3_reset_n = 1'd1; +assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer10}}; +assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer11}}; +assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]); +always @(*) begin + builder_multiplexer_next_state <= 4'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_en1 <= 1'd1; + if (main_litedramcore_read_available) begin + if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; + end + end + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; + end end 2'd2: begin + if (main_litedramcore_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; + end end 2'd3: begin + if (main_litedramcore_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; + end end 3'd4: begin + builder_multiplexer_next_state <= 3'd5; end 3'd5: begin + builder_multiplexer_next_state <= 3'd6; end 3'd6: begin + builder_multiplexer_next_state <= 3'd7; end 3'd7: begin + builder_multiplexer_next_state <= 4'd8; end 4'd8: begin + builder_multiplexer_next_state <= 4'd9; end 4'd9: begin + builder_multiplexer_next_state <= 4'd10; end 4'd10: begin + builder_multiplexer_next_state <= 1'd1; end default: begin + if (main_litedramcore_write_available) begin + if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; + end + end + if (main_litedramcore_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; + end end endcase end @@ -10394,6 +10312,71 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_choose_req_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end + end + endcase +end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; @@ -10486,26 +10469,26 @@ always @(*) begin endcase end always @(*) begin - builder_interface0_dat_r <= 32'd0; + builder_interface1_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin end 2'd2: begin - builder_interface0_dat_r <= builder_interface1_dat_r; end default: begin + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - builder_interface1_dat_w_next_value0 <= 32'd0; + builder_interface0_ack <= 1'd0; case (builder_state) 1'd1: begin end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end @@ -10531,93 +10514,123 @@ always @(*) begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; + builder_interface1_adr_next_value1 <= builder_interface0_adr; end end endcase end always @(*) begin - builder_interface0_ack <= 1'd0; + builder_interface1_adr_next_value_ce1 <= 1'd0; case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - builder_interface0_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - builder_interface1_adr_next_value_ce1 <= 1'd0; + builder_interface1_re_next_value2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + builder_interface1_re_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_re_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_re_next_value_ce2 <= 1'd1; end end endcase end always @(*) begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_we_next_value3 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_we_next_value3 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); end end endcase end always @(*) begin - builder_interface1_we_next_value_ce2 <= 1'd0; + builder_interface1_we_next_value_ce3 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value_ce3 <= 1'd1; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value_ce3 <= 1'd1; end end endcase end +always @(*) begin + builder_interface0_dat_r <= 32'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_interface0_dat_r <= builder_interface1_dat_r; + end + default: begin + end + endcase +end assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; + builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re; end end always @(*) begin - builder_csrbank0_init_done0_we <= 1'd0; + builder_csrbank0_init_done0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re; end end assign builder_csrbank0_init_done0_w = main_init_done_storage; @@ -10625,15 +10638,15 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; @@ -10646,79 +10659,79 @@ end always @(*) begin builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wlevel_strobe_re <= 1'd0; + main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_wlevel_strobe_we <= 1'd0; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -10729,61 +10742,61 @@ always @(*) begin end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -10793,11 +10806,11 @@ always @(*) begin end end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; -assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; -assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage; assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; -assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; -assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin @@ -10809,14 +10822,14 @@ end always @(*) begin builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10827,22 +10840,22 @@ always @(*) begin end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10861,14 +10874,14 @@ end always @(*) begin builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10877,7 +10890,7 @@ always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin @@ -10887,7 +10900,7 @@ end always @(*) begin builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; @@ -10900,7 +10913,7 @@ end always @(*) begin builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; @@ -10913,14 +10926,14 @@ end always @(*) begin main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[15:0]; always @(*) begin builder_csrbank2_dfii_pi1_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10939,10 +10952,10 @@ end always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin @@ -10952,14 +10965,14 @@ end always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10978,20 +10991,20 @@ end always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[15:0]; @@ -11004,14 +11017,14 @@ end always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11020,7 +11033,7 @@ always @(*) begin builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin @@ -11030,14 +11043,14 @@ end always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11050,7 +11063,7 @@ assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[ always @(*) begin builder_csrbank2_dfii_pi3_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11061,15 +11074,15 @@ always @(*) begin end assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[15:0]; @@ -11082,14 +11095,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11098,11 +11111,11 @@ always @(*) begin builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11111,7 +11124,7 @@ always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin @@ -11121,14 +11134,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; -assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage; assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; @@ -11137,11 +11150,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; -assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[15:0]; -assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status; assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; @@ -11151,11 +11164,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; -assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[15:0]; -assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status; assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; @@ -11165,11 +11178,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; -assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[15:0]; -assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status; assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; @@ -11179,19 +11192,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; -assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[15:0]; -assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status; assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_adr = builder_interface1_adr; +assign builder_re = builder_interface1_re; assign builder_we = builder_interface1_we; assign builder_dat_w = builder_interface1_dat_w; assign builder_interface1_dat_r = builder_dat_r; assign builder_interface0_bank_bus_adr = builder_adr; assign builder_interface1_bank_bus_adr = builder_adr; assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_re = builder_re; +assign builder_interface1_bank_bus_re = builder_re; +assign builder_interface2_bank_bus_re = builder_re; assign builder_interface0_bank_bus_we = builder_we; assign builder_interface1_bank_bus_we = builder_we; assign builder_interface2_bank_bus_we = builder_we; @@ -11917,16 +11934,16 @@ always @(*) begin builder_self0 <= 3'd0; case (main_litedramcore_steerer0) 1'd0: begin - builder_self0 <= main_litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12036,16 +12053,16 @@ always @(*) begin builder_self7 <= 3'd0; case (main_litedramcore_steerer1) 1'd0: begin - builder_self7 <= main_litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12155,16 +12172,16 @@ always @(*) begin builder_self14 <= 3'd0; case (main_litedramcore_steerer2) 1'd0: begin - builder_self14 <= main_litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12274,16 +12291,16 @@ always @(*) begin builder_self21 <= 3'd0; case (main_litedramcore_steerer3) 1'd0: begin - builder_self21 <= main_litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12389,10 +12406,10 @@ always @(*) begin end endcase end -assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); //------------------------------------------------------------------------------ @@ -13991,8 +14008,11 @@ always @(posedge sys_clk) begin if (builder_interface1_adr_next_value_ce1) begin builder_interface1_adr <= builder_interface1_adr_next_value1; end - if (builder_interface1_we_next_value_ce2) begin - builder_interface1_we <= builder_interface1_we_next_value2; + if (builder_interface1_re_next_value_ce2) begin + builder_interface1_re <= builder_interface1_re_next_value2; + end + if (builder_interface1_we_next_value_ce3) begin + builder_interface1_we <= builder_interface1_we_next_value3; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin @@ -14062,11 +14082,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; if (builder_csrbank1_dly_sel0_re) begin - main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; + main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r; end main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; if (builder_csrbank1_half_sys8x_taps0_re) begin - main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r; end main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; if (builder_csrbank1_wlevel_en0_re) begin @@ -14074,11 +14094,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; if (builder_csrbank1_rdphase0_re) begin - main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r; end main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; if (builder_csrbank1_wrphase0_re) begin - main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r; end main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; builder_interface2_bank_bus_dat_r <= 1'd0; @@ -14162,74 +14182,74 @@ always @(posedge sys_clk) begin endcase end if (builder_csrbank2_dfii_control0_re) begin - main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + main_litedramcore_storage <= builder_csrbank2_dfii_control0_r; end main_litedramcore_re <= builder_csrbank2_dfii_control0_re; if (builder_csrbank2_dfii_pi0_command0_re) begin - main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; + main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[15:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin - main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin - main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[15:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin - main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin - main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[15:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin - main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin - main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[15:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin - main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; @@ -14502,6 +14522,7 @@ always @(posedge sys_clk) begin main_init_done_re <= 1'd0; main_init_error_storage <= 1'd0; main_init_error_re <= 1'd0; + builder_interface1_re <= 1'd0; builder_interface1_we <= 1'd0; builder_refresher_state <= 2'd0; builder_bankmachine0_state <= 4'd0; @@ -17513,7 +17534,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) @@ -17531,7 +17552,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (iodelay_rst) @@ -17549,7 +17570,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) @@ -17567,7 +17588,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (sys_rst) @@ -17585,7 +17606,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) @@ -17603,7 +17624,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) @@ -17621,7 +17642,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) @@ -17639,7 +17660,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) @@ -17648,5 +17669,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:09. +// Auto-Generated by LiteX on 2025-02-15 19:54:45. //------------------------------------------------------------------------------ diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 0573632..843a495 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3920000039406004 +3920000239406004 7c0004ac654ac000 -600000007d2057aa +4e8000207d2057aa +0000000000000000 +3940600400000000 +654ac00039200000 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e8010010ebc1fff0 696c62616e652020 004441555120676e 006e6f7263694d20 +0000004953534920 +696c62616e655b20 +5d6461757120676e +0000000000000000 4920646175715b20 005d65646f6d204f 414c462049505320 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1921,15 +1951,13 @@ e8010010ebc1fff0 000000000000207c 203a747365622020 302562202c64256d -6000000000206432 +0000000000206432 76656c2064616552 000a3a676e696c65 696c616974696e49 52445320676e697a 3025783040204d41 000a2e2e2e786c38 -000000540000002a -6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 @@ -1971,11 +1999,12 @@ e8010010ebc1fff0 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 21cfb28..b70854e 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:05 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:38 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -79,19 +79,19 @@ LiteDRAMCore └─── cpu (CPUNone) └─── crg (LiteDRAMS7DDRPHYCRG) │ └─── pll (S7PLL) -│ │ └─── [BUFG] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] -│ │ └─── [BUFG] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [PLLE2_ADV] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] │ └─── idelayctrl (S7IDELAYCTRL) │ │ └─── [IDELAYCTRL] └─── ddrphy (A7DDRPHY) @@ -136,85 +136,72 @@ LiteDRAMCore │ └─── bitslip_35* (BitSlip) │ └─── tappeddelayline_2* (TappedDelayLine) │ └─── tappeddelayline_3* (TappedDelayLine) -│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] │ └─── [IOBUF] -│ └─── [IDELAYE2] -│ └─── [OSERDESE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [IOBUFDS] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [IOBUFDS] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] +│ └─── [IDELAYE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] @@ -222,16 +209,29 @@ LiteDRAMCore │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] │ └─── [OBUFDS] │ └─── [OSERDESE2] -│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) │ │ └─── pi0 (PhaseInjector) @@ -543,6 +543,7 @@ wire [29:0] builder_interface0_adr; wire [13:0] builder_interface0_bank_bus_adr; reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_re; wire builder_interface0_bank_bus_we; wire [1:0] builder_interface0_bte; wire [2:0] builder_interface0_cti; @@ -559,17 +560,22 @@ reg builder_interface1_adr_next_value_ce1 = 1'd0; wire [13:0] builder_interface1_bank_bus_adr; reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_re; wire builder_interface1_bank_bus_we; wire [31:0] builder_interface1_dat_r; reg [31:0] builder_interface1_dat_w = 32'd0; reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_re = 1'd0; +reg builder_interface1_re_next_value2 = 1'd0; +reg builder_interface1_re_next_value_ce2 = 1'd0; reg builder_interface1_we = 1'd0; -reg builder_interface1_we_next_value2 = 1'd0; -reg builder_interface1_we_next_value_ce2 = 1'd0; +reg builder_interface1_we_next_value3 = 1'd0; +reg builder_interface1_we_next_value_ce3 = 1'd0; wire [13:0] builder_interface2_bank_bus_adr; reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_re; wire builder_interface2_bank_bus_we; reg builder_locked0 = 1'd0; reg builder_locked1 = 1'd0; @@ -594,6 +600,7 @@ reg builder_new_master_wdata_ready0 = 1'd0; reg builder_new_master_wdata_ready1 = 1'd0; reg [1:0] builder_next_state = 2'd0; wire builder_pll_fb; +wire builder_re; reg [1:0] builder_refresher_next_state = 2'd0; reg [1:0] builder_refresher_state = 2'd0; wire builder_reset0; @@ -700,14 +707,14 @@ reg builder_t_self3 = 1'd0; reg builder_t_self4 = 1'd0; reg builder_t_self5 = 1'd0; wire builder_we; -wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1; wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2; wire builder_xilinxasyncresetsynchronizerimpl2_expr; wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_expr; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; @@ -1895,9 +1902,9 @@ reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p0_address; wire [2:0] main_litedramcore_csr_dfi_p0_bank; reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +wire main_litedramcore_csr_dfi_p0_cke; reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +wire main_litedramcore_csr_dfi_p0_odt; reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; wire main_litedramcore_csr_dfi_p0_rddata_en; @@ -1911,9 +1918,9 @@ reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p1_address; wire [2:0] main_litedramcore_csr_dfi_p1_bank; reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +wire main_litedramcore_csr_dfi_p1_cke; reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +wire main_litedramcore_csr_dfi_p1_odt; reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; wire main_litedramcore_csr_dfi_p1_rddata_en; @@ -1927,9 +1934,9 @@ reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p2_address; wire [2:0] main_litedramcore_csr_dfi_p2_bank; reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +wire main_litedramcore_csr_dfi_p2_cke; reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +wire main_litedramcore_csr_dfi_p2_odt; reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; wire main_litedramcore_csr_dfi_p2_rddata_en; @@ -1943,9 +1950,9 @@ reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p3_address; wire [2:0] main_litedramcore_csr_dfi_p3_bank; reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +wire main_litedramcore_csr_dfi_p3_cke; reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +wire main_litedramcore_csr_dfi_p3_odt; reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; wire main_litedramcore_csr_dfi_p3_rddata_en; @@ -4763,42 +4770,26 @@ always @(*) begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_cke <= 1'd0; - main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_cke <= 1'd0; - main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_cke <= 1'd0; - main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_cke <= 1'd0; - main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p0_odt <= 1'd0; - main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_odt <= 1'd0; - main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_odt <= 1'd0; - main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_odt <= 1'd0; - main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; -end +assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt; assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p0_we_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4831,20 +4822,20 @@ always @(*) begin main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p1_we_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4877,20 +4868,20 @@ always @(*) begin main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p2_we_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4923,20 +4914,20 @@ always @(*) begin main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p3_we_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4969,14 +4960,6 @@ always @(*) begin main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); @@ -5085,82 +5068,82 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) 1'd1: begin - main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase end always @(*) begin - main_litedramcore_zqcs_executer_start <= 1'd0; + main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) 1'd1: begin end 2'd2: begin if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin - main_litedramcore_zqcs_executer_start <= 1'd1; end else begin + main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase end always @(*) begin - main_litedramcore_cmd_last <= 1'd0; + main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - if (main_litedramcore_sequencer_done0) begin - if (main_litedramcore_wants_zqcs) begin - end else begin - main_litedramcore_cmd_last <= 1'd1; - end - end end 2'd3: begin - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase end always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_valid <= 1'd0; + end + end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end @@ -5306,7 +5289,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5331,8 +5314,8 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_source_source_payload_we) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5344,7 +5327,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5353,6 +5336,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5363,32 +5349,20 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_source_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_source_source_payload_we) begin - main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -5401,78 +5375,11 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_source_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine0_twtpcon_ready) begin - main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_row_open <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin @@ -5737,6 +5644,82 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; @@ -5876,125 +5859,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_row_open <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_source_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_row_close <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) @@ -6308,17 +6172,136 @@ always @(*) begin end endcase end -assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; -assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; -assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; -assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; -assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; -assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; -assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; -assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; -assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; -assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; -assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +always @(*) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; @@ -6447,32 +6430,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) @@ -6879,6 +6836,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; @@ -7018,76 +7001,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_source_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if (main_litedramcore_bankmachine3_source_source_payload_we) begin - main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -7297,33 +7210,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine3_row_open <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin @@ -7389,6 +7276,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) @@ -7450,6 +7363,76 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; @@ -7589,82 +7572,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_source_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_source_source_payload_we) begin - main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_source_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_source_source_payload_we) begin - main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) @@ -8021,6 +7928,82 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; @@ -8105,180 +8088,61 @@ always @(*) begin case (builder_bankmachine5_state) 1'd1: begin if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - if (main_litedramcore_bankmachine5_cmd_ready) begin - builder_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - builder_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - if (main_litedramcore_bankmachine5_cmd_ready) begin - builder_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~main_litedramcore_bankmachine5_refresh_req)) begin - builder_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - builder_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - builder_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - builder_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - builder_bankmachine5_next_state <= 1'd0; - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - builder_bankmachine5_next_state <= 3'd4; - end else begin - if (main_litedramcore_bankmachine5_source_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin - builder_bankmachine5_next_state <= 2'd2; - end - end else begin - builder_bankmachine5_next_state <= 1'd1; - end - end else begin - builder_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine5_twtpcon_ready) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_row_open <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin if (main_litedramcore_bankmachine5_source_source_valid) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; + end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end end endcase end -always @(*) begin - main_litedramcore_bankmachine5_row_close <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -8592,6 +8456,125 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; @@ -8731,32 +8714,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) @@ -9163,6 +9120,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; @@ -9303,21 +9286,22 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9332,12 +9316,9 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9360,8 +9341,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9373,22 +9354,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9399,11 +9373,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9428,8 +9417,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9441,7 +9430,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9466,8 +9455,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9479,7 +9468,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9488,6 +9477,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9498,32 +9490,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9541,10 +9524,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_source_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; - end + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9555,18 +9535,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine7_twtpcon_ready) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9607,18 +9587,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9632,34 +9609,19 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_close <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9670,19 +9632,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9700,9 +9677,12 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9724,7 +9704,10 @@ always @(*) begin if (main_litedramcore_bankmachine7_source_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -10328,10 +10311,14 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_en1 <= 1'd0; + main_litedramcore_choose_req_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_en1 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10352,18 +10339,19 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end endcase end always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; + main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10384,11 +10372,6 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end end endcase end @@ -10493,64 +10476,82 @@ always @(*) begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; + builder_interface1_adr_next_value1 <= builder_interface0_adr; end end endcase end always @(*) begin - builder_interface0_ack <= 1'd0; + builder_interface1_adr_next_value_ce1 <= 1'd0; case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - builder_interface0_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - builder_interface1_adr_next_value_ce1 <= 1'd0; + builder_interface1_re_next_value2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + builder_interface1_re_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_re_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_re_next_value_ce2 <= 1'd1; end end endcase end always @(*) begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_we_next_value3 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_we_next_value3 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); end end endcase end always @(*) begin - builder_interface1_we_next_value_ce2 <= 1'd0; + builder_interface1_we_next_value_ce3 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value_ce3 <= 1'd1; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value_ce3 <= 1'd1; end end endcase @@ -10579,6 +10580,18 @@ always @(*) begin end endcase end +always @(*) begin + builder_interface0_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_interface0_ack <= 1'd1; + end + default: begin + end + endcase +end always @(*) begin builder_interface1_dat_w_next_value_ce0 <= 1'd0; case (builder_state) @@ -10596,7 +10609,7 @@ assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re; end end always @(*) begin @@ -10607,15 +10620,15 @@ always @(*) begin end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re; end end assign builder_csrbank0_init_done0_w = main_init_done_storage; @@ -10623,41 +10636,41 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; @@ -10670,53 +10683,53 @@ end always @(*) begin builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wlevel_strobe_re <= 1'd0; + main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_wlevel_strobe_we <= 1'd0; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -10727,75 +10740,75 @@ always @(*) begin end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; -assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; -assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage; assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; -assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; -assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin @@ -10807,14 +10820,14 @@ end always @(*) begin builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10825,15 +10838,15 @@ always @(*) begin end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0]; @@ -10846,14 +10859,14 @@ end always @(*) begin builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10862,11 +10875,11 @@ always @(*) begin builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10875,7 +10888,7 @@ always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin @@ -10885,14 +10898,14 @@ end always @(*) begin builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10903,22 +10916,22 @@ always @(*) begin end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin builder_csrbank2_dfii_pi1_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10937,14 +10950,14 @@ end always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10953,7 +10966,7 @@ always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin @@ -10963,7 +10976,7 @@ end always @(*) begin builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; @@ -10976,27 +10989,27 @@ end always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11015,10 +11028,10 @@ end always @(*) begin builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin @@ -11028,14 +11041,14 @@ end always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11054,7 +11067,7 @@ end always @(*) begin builder_csrbank2_dfii_pi3_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; @@ -11067,7 +11080,7 @@ end always @(*) begin main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0]; @@ -11080,14 +11093,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11096,7 +11109,7 @@ always @(*) begin builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin @@ -11106,14 +11119,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11126,7 +11139,7 @@ assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; -assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage; assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; @@ -11135,11 +11148,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; -assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0]; -assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status; assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; @@ -11149,11 +11162,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; -assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0]; -assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status; assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; @@ -11163,11 +11176,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; -assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0]; -assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status; assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; @@ -11177,19 +11190,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; -assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0]; -assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status; assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_adr = builder_interface1_adr; +assign builder_re = builder_interface1_re; assign builder_we = builder_interface1_we; assign builder_dat_w = builder_interface1_dat_w; assign builder_interface1_dat_r = builder_dat_r; assign builder_interface0_bank_bus_adr = builder_adr; assign builder_interface1_bank_bus_adr = builder_adr; assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_re = builder_re; +assign builder_interface1_bank_bus_re = builder_re; +assign builder_interface2_bank_bus_re = builder_re; assign builder_interface0_bank_bus_we = builder_we; assign builder_interface1_bank_bus_we = builder_we; assign builder_interface2_bank_bus_we = builder_we; @@ -11915,16 +11932,16 @@ always @(*) begin builder_self0 <= 3'd0; case (main_litedramcore_steerer0) 1'd0: begin - builder_self0 <= main_litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12034,16 +12051,16 @@ always @(*) begin builder_self7 <= 3'd0; case (main_litedramcore_steerer1) 1'd0: begin - builder_self7 <= main_litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12153,16 +12170,16 @@ always @(*) begin builder_self14 <= 3'd0; case (main_litedramcore_steerer2) 1'd0: begin - builder_self14 <= main_litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12272,16 +12289,16 @@ always @(*) begin builder_self21 <= 3'd0; case (main_litedramcore_steerer3) 1'd0: begin - builder_self21 <= main_litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12387,10 +12404,10 @@ always @(*) begin end endcase end -assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); //------------------------------------------------------------------------------ @@ -13989,8 +14006,11 @@ always @(posedge sys_clk) begin if (builder_interface1_adr_next_value_ce1) begin builder_interface1_adr <= builder_interface1_adr_next_value1; end - if (builder_interface1_we_next_value_ce2) begin - builder_interface1_we <= builder_interface1_we_next_value2; + if (builder_interface1_re_next_value_ce2) begin + builder_interface1_re <= builder_interface1_re_next_value2; + end + if (builder_interface1_we_next_value_ce3) begin + builder_interface1_we <= builder_interface1_we_next_value3; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin @@ -14060,11 +14080,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; if (builder_csrbank1_dly_sel0_re) begin - main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; + main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r; end main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; if (builder_csrbank1_half_sys8x_taps0_re) begin - main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r; end main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; if (builder_csrbank1_wlevel_en0_re) begin @@ -14072,11 +14092,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; if (builder_csrbank1_rdphase0_re) begin - main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r; end main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; if (builder_csrbank1_wrphase0_re) begin - main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r; end main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; builder_interface2_bank_bus_dat_r <= 1'd0; @@ -14160,74 +14180,74 @@ always @(posedge sys_clk) begin endcase end if (builder_csrbank2_dfii_control0_re) begin - main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + main_litedramcore_storage <= builder_csrbank2_dfii_control0_r; end main_litedramcore_re <= builder_csrbank2_dfii_control0_re; if (builder_csrbank2_dfii_pi0_command0_re) begin - main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; + main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin - main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin - main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin - main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin - main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin - main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin - main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin - main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; @@ -14500,6 +14520,7 @@ always @(posedge sys_clk) begin main_init_done_re <= 1'd0; main_init_error_storage <= 1'd0; main_init_error_re <= 1'd0; + builder_interface1_re <= 1'd0; builder_interface1_we <= 1'd0; builder_refresher_state <= 2'd0; builder_bankmachine0_state <= 4'd0; @@ -17453,7 +17474,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) @@ -17471,7 +17492,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (iodelay_rst) @@ -17489,7 +17510,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) @@ -17507,7 +17528,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (sys_rst) @@ -17525,7 +17546,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) @@ -17543,7 +17564,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) @@ -17561,7 +17582,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) @@ -17579,7 +17600,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) @@ -17588,5 +17609,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:06. +// Auto-Generated by LiteX on 2025-02-15 19:54:38. //------------------------------------------------------------------------------ diff --git a/litedram/generated/ecpix-5/litedram_core.init b/litedram/generated/ecpix-5/litedram_core.init index ecf50a2..130d4d6 100644 --- a/litedram/generated/ecpix-5/litedram_core.init +++ b/litedram/generated/ecpix-5/litedram_core.init @@ -523,14 +523,14 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842ada4 -f821ffc148002809 +f821ffc148002815 3ba000053bc06000 4bffff8567dec000 7fa0f7aa7c0004ac 7fe0f6aa7c0004ac 73ff00014bffff95 382100404082ffe4 -0000000048002820 +000000004800282c 0000038001000000 3842ad503c4c0001 fbe1fff87c0802a6 @@ -540,11 +540,11 @@ f8a100e0f88100d8 38610020f8c100e8 f8e100f038c100d8 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+eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1874,8 +1875,8 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1936,15 +1937,13 @@ e8010010ebc1fff0 000000000000207c 203a747365622020 302562202c64256d -6000000000206432 +0000000000206432 76656c2064616552 000a3a676e696c65 696c616974696e49 52445320676e697a 3025783040204d41 000a2e2e2e786c38 -000000540000002a -6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 @@ -1986,11 +1985,12 @@ e8010010ebc1fff0 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/ecpix-5/litedram_core.v b/litedram/generated/ecpix-5/litedram_core.v index bc80a1b..21f8c69 100644 --- a/litedram/generated/ecpix-5/litedram_core.v +++ b/litedram/generated/ecpix-5/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : LFE5UM5G-85F-8BG554I -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 18:06:24 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:51 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -80,9 +80,9 @@ LiteDRAMCore └─── crg (LiteDRAMECP5DDRPHYCRG) │ └─── pll (ECP5PLL) │ │ └─── [EHXPLLL] +│ └─── [ECLKSYNCB] │ └─── [CLKDIVF] │ └─── [ECLKBRIDGECS] -│ └─── [ECLKSYNCB] └─── ddrphy (ECP5DDRPHY) │ └─── init (ECP5DDRPHYInit) │ │ └─── [DDRDLLA] @@ -105,128 +105,128 @@ LiteDRAMCore │ └─── tappeddelayline_0* (TappedDelayLine) │ └─── tappeddelayline_1* (TappedDelayLine) │ └─── [DELAYG] -│ └─── [TSHX2DQA] │ └─── [ODDRX2F] -│ └─── [TSHX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [ODDRX2F] │ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [ODDRX2F] -│ └─── [ODDRX2DQSB] -│ └─── [TSHX2DQA] │ └─── [DELAYG] │ └─── [DELAYG] -│ └─── [TSHX2DQA] │ └─── [DELAYG] │ └─── [ODDRX2F] │ └─── [ODDRX2F] -│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [TSHX2DQA] -│ └─── [ODDRX2DQA] -│ └─── [ODDRX2DQA] │ └─── [ODDRX2F] +│ └─── [DELAYG] │ └─── [ODDRX2F] -│ └─── [ODDRX2DQA] -│ └─── [ODDRX2DQA] │ └─── [DELAYG] -│ └─── [DQSBUFM] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [TSHX2DQA] │ └─── [ODDRX2F] -│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [DELAYG] │ └─── [ODDRX2F] -│ └─── [IDDRX2DQA] -│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [IDDRX2DQA] -│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] │ └─── [DELAYG] +│ └─── [DQSBUFM] +│ └─── [ODDRX2DQSB] │ └─── [TSHX2DQSA] -│ └─── [IDDRX2DQA] -│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [ODDRX2DQA] │ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [IDDRX2DQA] │ └─── [DELAYG] │ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [DQSBUFM] -│ └─── [DELAYG] -│ └─── [TSHX2DQSA] │ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [DELAYG] │ └─── [ODDRX2DQA] -│ └─── [TSHX2DQA] -│ └─── [IDDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] │ └─── [DELAYG] -│ └─── [ODDRX2F] -│ └─── [DELAYG] -│ └─── [ODDRX2F] -│ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] -│ └─── [DELAYG] │ └─── [ODDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [TSHX2DQA] -│ └─── [DELAYG] │ └─── [DELAYG] -│ └─── [ODDRX2DQA] -│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [ODDRX2DQA] -│ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQSB] +│ └─── [DQSBUFM] +│ └─── [TSHX2DQSA] │ └─── [ODDRX2DQA] │ └─── [ODDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [IDDRX2DQA] -│ └─── [IDDRX2DQA] -│ └─── [IDDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] -│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] │ └─── [DELAYG] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] -│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] │ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [ODDRX2DQSB] -│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [TSHX2DQA] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] │ └─── [DELAYG] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) @@ -364,32 +364,32 @@ LiteDRAMCore │ │ └─── csrstorage_8* (CSRStorage) │ │ └─── csrstatus_1* (CSRStatus) └─── csr_interconnect (InterconnectShared) -└─── [FD1S3BX] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] -└─── [FD1S3BX] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] -└─── [FD1S3BX] └─── [TRELLIS_IO] -└─── [FD1S3BX] └─── [TRELLIS_IO] -└─── [FD1S3BX] └─── [TRELLIS_IO] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] * : Generated name. []: BlackBox. */ @@ -864,6 +864,7 @@ wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire [2:0] interface0_cti; @@ -880,17 +881,22 @@ reg interface1_adr_next_value_ce1 = 1'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; reg [31:0] interface1_dat_w_next_value0 = 32'd0; reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_re = 1'd0; +reg interface1_re_next_value2 = 1'd0; +reg interface1_re_next_value_ce2 = 1'd0; reg interface1_we = 1'd0; -reg interface1_we_next_value2 = 1'd0; -reg interface1_we_next_value_ce2 = 1'd0; +reg interface1_we_next_value3 = 1'd0; +reg interface1_we_next_value_ce3 = 1'd0; wire [13:0] interface2_bank_bus_adr; reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; wire interface2_bank_bus_we; wire latticeecp5asyncresetsynchronizerimpl0_expr; wire latticeecp5asyncresetsynchronizerimpl0_rst1; @@ -1733,9 +1739,9 @@ reg litedramcore_csr_dfi_p0_act_n = 1'd1; wire [14:0] litedramcore_csr_dfi_p0_address; wire [2:0] litedramcore_csr_dfi_p0_bank; reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cke = 1'd0; +wire litedramcore_csr_dfi_p0_cke; reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_odt = 1'd0; +wire litedramcore_csr_dfi_p0_odt; reg litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; wire litedramcore_csr_dfi_p0_rddata_en; @@ -1749,9 +1755,9 @@ reg litedramcore_csr_dfi_p1_act_n = 1'd1; wire [14:0] litedramcore_csr_dfi_p1_address; wire [2:0] litedramcore_csr_dfi_p1_bank; reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cke = 1'd0; +wire litedramcore_csr_dfi_p1_cke; reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_odt = 1'd0; +wire litedramcore_csr_dfi_p1_odt; reg litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; wire litedramcore_csr_dfi_p1_rddata_en; @@ -2115,6 +2121,7 @@ reg multiregimpl0 = 1'd0; reg multiregimpl1 = 1'd0; reg [1:0] next_state = 2'd0; wire por_clk; +wire re; reg rhs_self0 = 1'd0; reg [14:0] rhs_self1 = 15'd0; reg rhs_self10 = 1'd0; @@ -2951,59 +2958,6 @@ assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - if (1'd0) begin - litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}}; - end - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end always @(*) begin litedramcore_master_p0_cke <= 1'd0; if (litedramcore_sel) begin @@ -3331,6 +3285,20 @@ always @(*) begin end else begin end end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end always @(*) begin litedramcore_csr_dfi_p0_rddata <= 64'd0; if (litedramcore_sel) begin @@ -3402,23 +3370,58 @@ always @(*) begin end end always @(*) begin - litedramcore_csr_dfi_p0_cke <= 1'd0; - litedramcore_csr_dfi_p0_cke <= litedramcore_cke; -end -always @(*) begin - litedramcore_csr_dfi_p1_cke <= 1'd0; - litedramcore_csr_dfi_p1_cke <= litedramcore_cke; + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + if (1'd0) begin + litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}}; + end + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end end always @(*) begin - litedramcore_csr_dfi_p0_odt <= 1'd0; - litedramcore_csr_dfi_p0_odt <= litedramcore_odt; + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end end always @(*) begin - litedramcore_csr_dfi_p1_odt <= 1'd0; - litedramcore_csr_dfi_p1_odt <= litedramcore_odt; + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end end +assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; +assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; +assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; +assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; +always @(*) begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end +end always @(*) begin litedramcore_csr_dfi_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin @@ -3451,20 +3454,20 @@ always @(*) begin litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end -always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end -end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end +end always @(*) begin litedramcore_csr_dfi_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin @@ -3497,14 +3500,6 @@ always @(*) begin litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end -always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end -end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); @@ -3612,22 +3607,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_cmd_valid <= 1'd0; case (litedramcore_refresher_state) @@ -3694,6 +3673,22 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; @@ -3827,66 +3822,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine0_state) @@ -4207,6 +4142,66 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; @@ -4340,40 +4335,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (litedramcore_bankmachine1_state) @@ -4396,28 +4357,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine1_cmd_valid <= 1'd0; case (litedramcore_bankmachine1_state) @@ -4477,6 +4416,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine1_state) @@ -4720,6 +4681,40 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; @@ -4853,28 +4848,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine2_state) @@ -5233,6 +5206,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; @@ -5366,37 +5361,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine3_state) @@ -5746,6 +5710,37 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; @@ -5879,66 +5874,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine4_state) @@ -6187,7 +6122,69 @@ always @(*) begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6198,21 +6195,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6223,12 +6221,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6247,8 +6242,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6392,40 +6387,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (litedramcore_bankmachine5_state) @@ -6772,6 +6733,40 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; @@ -6905,28 +6900,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine6_state) @@ -7042,28 +7015,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine6_state) @@ -7248,6 +7199,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; case (litedramcore_bankmachine6_state) @@ -7285,6 +7258,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; @@ -7418,37 +7413,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine7_state) @@ -7798,6 +7762,37 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); @@ -8048,19 +8043,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer0 <= 2'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_steerer0 <= 1'd0; if (1'd0) begin - litedramcore_steerer0 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer0 <= 1'd1; + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin - litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -8086,29 +8077,23 @@ always @(*) begin end 4'd14: begin end - 4'd15: begin - end - default: begin - litedramcore_steerer0 <= 1'd0; - if (1'd1) begin - litedramcore_steerer0 <= 2'd2; - end + 4'd15: begin + end + default: begin if (1'd0) begin - litedramcore_steerer0 <= 1'd1; + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_steerer1 <= 2'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_steerer1 <= 1'd0; - if (1'd1) begin - litedramcore_steerer1 <= 2'd2; - end if (1'd0) begin - litedramcore_steerer1 <= 1'd1; + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end 2'd2: begin @@ -8140,24 +8125,17 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_steerer1 <= 1'd0; if (1'd0) begin - litedramcore_steerer1 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer1 <= 1'd1; + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end 2'd2: begin end @@ -8188,10 +8166,7 @@ always @(*) begin 4'd15: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_choose_req_want_reads <= 1'd1; end endcase end @@ -8234,13 +8209,10 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -8271,15 +8243,11 @@ always @(*) begin 4'd15: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_en0 <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin end @@ -8312,15 +8280,19 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -8351,13 +8323,19 @@ always @(*) begin 4'd15: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_en1 <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -8388,21 +8366,23 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_steerer0 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin + litedramcore_steerer0 <= 1'd0; if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + litedramcore_steerer0 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer0 <= 1'd1; end end 2'd2: begin + litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -8431,19 +8411,27 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_steerer0 <= 1'd0; + if (1'd1) begin + litedramcore_steerer0 <= 2'd2; + end if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_steerer1 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_steerer1 <= 1'd0; + if (1'd1) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer1 <= 1'd1; + end end 2'd2: begin end @@ -8474,6 +8462,13 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_steerer1 <= 1'd0; + if (1'd0) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer1 <= 1'd1; + end end endcase end @@ -8569,138 +8564,168 @@ always @(*) begin endcase end always @(*) begin - interface0_ack <= 1'd0; + interface1_adr_next_value1 <= 14'd0; case (state) 1'd1: begin + interface1_adr_next_value1 <= 1'd0; end 2'd2: begin - interface0_ack <= 1'd1; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value1 <= interface0_adr; + end end endcase end always @(*) begin - interface0_dat_r <= 32'd0; + interface1_adr_next_value_ce1 <= 1'd0; case (state) 1'd1: begin + interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - interface0_dat_r <= interface1_dat_r; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - interface1_dat_w_next_value0 <= 32'd0; + interface1_re_next_value2 <= 1'd0; case (state) 1'd1: begin + interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin - interface1_dat_w_next_value0 <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0)); + end end endcase end always @(*) begin - interface1_dat_w_next_value_ce0 <= 1'd0; + interface1_re_next_value_ce2 <= 1'd0; case (state) 1'd1: begin + interface1_re_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - interface1_dat_w_next_value_ce0 <= 1'd1; + if ((interface0_cyc & interface0_stb)) begin + interface1_re_next_value_ce2 <= 1'd1; + end end endcase end always @(*) begin - interface1_adr_next_value1 <= 14'd0; + interface1_we_next_value3 <= 1'd0; case (state) 1'd1: begin - interface1_adr_next_value1 <= 1'd0; + interface1_we_next_value3 <= 1'd0; end 2'd2: begin end default: begin if ((interface0_cyc & interface0_stb)) begin - interface1_adr_next_value1 <= interface0_adr[29:0]; + interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0)); end end endcase end always @(*) begin - interface1_adr_next_value_ce1 <= 1'd0; + interface1_we_next_value_ce3 <= 1'd0; case (state) 1'd1: begin - interface1_adr_next_value_ce1 <= 1'd1; + interface1_we_next_value_ce3 <= 1'd1; end 2'd2: begin end default: begin if ((interface0_cyc & interface0_stb)) begin - interface1_adr_next_value_ce1 <= 1'd1; + interface1_we_next_value_ce3 <= 1'd1; end end endcase end always @(*) begin - interface1_we_next_value2 <= 1'd0; + interface0_dat_r <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + interface0_dat_r <= interface1_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + interface0_ack <= 1'd0; case (state) 1'd1: begin - interface1_we_next_value2 <= 1'd0; end 2'd2: begin + interface0_ack <= 1'd1; end default: begin - if ((interface0_cyc & interface0_stb)) begin - interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0)); - end end endcase end always @(*) begin - interface1_we_next_value_ce2 <= 1'd0; + interface1_dat_w_next_value0 <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + interface1_dat_w_next_value0 <= interface0_dat_w; + end + endcase +end +always @(*) begin + interface1_dat_w_next_value_ce0 <= 1'd0; case (state) 1'd1: begin - interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - if ((interface0_cyc & interface0_stb)) begin - interface1_we_next_value_ce2 <= 1'd1; - end + interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; + csrbank0_init_done0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + csrbank0_init_done0_we <= interface0_bank_bus_re; end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; + csrbank0_init_done0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + csrbank0_init_done0_re <= interface0_bank_bus_we; end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; + csrbank0_init_error0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + csrbank0_init_error0_re <= interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; + csrbank0_init_error0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + csrbank0_init_error0_we <= interface0_bank_bus_re; end end assign csrbank0_init_done0_w = init_done_storage; @@ -8708,54 +8733,54 @@ assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; + csrbank1_dly_sel0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + csrbank1_dly_sel0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; + csrbank1_dly_sel0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + csrbank1_dly_sel0_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_rst_we <= 1'd0; + ddrphy_rdly_dq_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; end end always @(*) begin - ddrphy_rdly_dq_rst_re <= 1'd0; + ddrphy_rdly_dq_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + ddrphy_rdly_dq_rst_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_inc_we <= 1'd0; + ddrphy_rdly_dq_inc_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; end end always @(*) begin - ddrphy_rdly_dq_inc_re <= 1'd0; + ddrphy_rdly_dq_inc_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + ddrphy_rdly_dq_inc_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; end end always @(*) begin - ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + ddrphy_rdly_dq_bitslip_rst_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; @@ -8768,20 +8793,20 @@ end always @(*) begin ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_bitslip_we <= interface1_bank_bus_re; end end assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_burstdet_clr_re <= 1'd0; + ddrphy_burstdet_clr_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - ddrphy_burstdet_clr_re <= interface1_bank_bus_we; + ddrphy_burstdet_clr_we <= interface1_bank_bus_re; end end always @(*) begin - ddrphy_burstdet_clr_we <= 1'd0; + ddrphy_burstdet_clr_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we); + ddrphy_burstdet_clr_re <= interface1_bank_bus_we; end end assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; @@ -8794,11 +8819,11 @@ end always @(*) begin csrbank1_burstdet_seen_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); + csrbank1_burstdet_seen_we <= interface1_bank_bus_re; end end -assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0]; -assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0]; +assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage; +assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status; assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; @@ -8811,46 +8836,46 @@ end always @(*) begin csrbank2_dfii_control0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_control0_we <= interface2_bank_bus_re; end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; + csrbank2_dfii_pi0_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; + csrbank2_dfii_pi0_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_command0_we <= interface2_bank_bus_re; end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; + litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + litedramcore_phaseinjector0_command_issue_we <= interface2_bank_bus_re; end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; + litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; + csrbank2_dfii_pi0_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_address0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; + csrbank2_dfii_pi0_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; @@ -8863,14 +8888,14 @@ end always @(*) begin csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_baddress0_we <= interface2_bank_bus_re; end end -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_dfii_pi0_wrdata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_wrdata1_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8879,37 +8904,37 @@ always @(*) begin csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi0_rddata1_we <= 1'd0; + csrbank2_dfii_pi0_rddata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_rddata1_re <= 1'd0; + csrbank2_dfii_pi0_rddata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata1_we <= interface2_bank_bus_re; end end -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_dfii_pi0_rddata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_rddata0_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8920,22 +8945,22 @@ always @(*) begin end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; + csrbank2_dfii_pi1_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_command0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; + csrbank2_dfii_pi1_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + litedramcore_phaseinjector1_command_issue_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8954,14 +8979,14 @@ end always @(*) begin csrbank2_dfii_pi1_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_address0_we <= interface2_bank_bus_re; end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_baddress0_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8970,37 +8995,37 @@ always @(*) begin csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata1_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata0_we <= interface2_bank_bus_re; end end -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_dfii_pi1_rddata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_rddata1_we <= interface2_bank_bus_re; end end always @(*) begin @@ -9009,24 +9034,24 @@ always @(*) begin csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi1_rddata0_re <= 1'd0; + csrbank2_dfii_pi1_rddata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi1_rddata0_we <= 1'd0; + csrbank2_dfii_pi1_rddata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; assign litedramcore_odt = litedramcore_storage[2]; assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; +assign csrbank2_dfii_control0_w = litedramcore_storage; assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; @@ -9035,9 +9060,9 @@ assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_c assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6]; assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage; +assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage; assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32]; @@ -9051,21 +9076,25 @@ assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_c assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6]; assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage; +assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage; assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we; assign adr = interface1_adr; +assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface2_bank_bus_we = we; @@ -9791,16 +9820,16 @@ always @(*) begin self0 <= 3'd0; case (litedramcore_steerer0) 1'd0: begin - self0 <= litedramcore_nop_ba[2:0]; + self0 <= litedramcore_nop_ba; end 1'd1: begin - self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self0 <= litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + self0 <= litedramcore_choose_req_cmd_payload_ba; end default: begin - self0 <= litedramcore_cmd_payload_ba[2:0]; + self0 <= litedramcore_cmd_payload_ba; end endcase end @@ -9910,16 +9939,16 @@ always @(*) begin self7 <= 3'd0; case (litedramcore_steerer1) 1'd0: begin - self7 <= litedramcore_nop_ba[2:0]; + self7 <= litedramcore_nop_ba; end 1'd1: begin - self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self7 <= litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + self7 <= litedramcore_choose_req_cmd_payload_ba; end default: begin - self7 <= litedramcore_cmd_payload_ba[2:0]; + self7 <= litedramcore_cmd_payload_ba; end endcase end @@ -11727,8 +11756,11 @@ always @(posedge sys_clk) begin if (interface1_adr_next_value_ce1) begin interface1_adr <= interface1_adr_next_value1; end - if (interface1_we_next_value_ce2) begin - interface1_we <= interface1_we_next_value2; + if (interface1_re_next_value_ce2) begin + interface1_re <= interface1_re_next_value2; + end + if (interface1_we_next_value_ce3) begin + interface1_we <= interface1_we_next_value3; end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin @@ -11776,7 +11808,7 @@ always @(posedge sys_clk) begin endcase end if (csrbank1_dly_sel0_re) begin - ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + ddrphy_dly_sel_storage <= csrbank1_dly_sel0_r; end ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re; @@ -11837,19 +11869,19 @@ always @(posedge sys_clk) begin endcase end if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + litedramcore_storage <= csrbank2_dfii_control0_r; end litedramcore_re <= csrbank2_dfii_control0_re; if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r; + litedramcore_phaseinjector0_command_storage <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + litedramcore_phaseinjector0_baddress_storage <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; if (csrbank2_dfii_pi0_wrdata1_re) begin @@ -11861,15 +11893,15 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r; + litedramcore_phaseinjector1_command_storage <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + litedramcore_phaseinjector1_baddress_storage <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; if (csrbank2_dfii_pi1_wrdata1_re) begin @@ -12151,6 +12183,7 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; + interface1_re <= 1'd0; interface1_we <= 1'd0; litedramcore_refresher_state <= 2'd0; litedramcore_bankmachine0_state <= 3'd0; @@ -14965,5 +14998,5 @@ TRELLIS_IO #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 18:06:24. +// Auto-Generated by LiteX on 2025-02-15 19:54:52. //------------------------------------------------------------------------------ diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init index 33ac9e8..f7d487f 100644 --- a/litedram/generated/genesys2/litedram_core.init +++ b/litedram/generated/genesys2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3920000039406004 +3920000239406004 7c0004ac654ac000 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3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v index b6d2e37..fd058f4 100644 --- a/litedram/generated/genesys2/litedram_core.v +++ b/litedram/generated/genesys2/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:08 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:43 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -80,18 +80,18 @@ LiteDRAMCore └─── crg (LiteDRAMS7DDRPHYCRG) │ └─── pll (S7PLL) │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [PLLE2_ADV] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] │ └─── idelayctrl (S7IDELAYCTRL) │ │ └─── [IDELAYCTRL] └─── ddrphy (K7DDRPHY) @@ -172,239 +172,239 @@ LiteDRAMCore │ └─── bitslip_71* (BitSlip) │ └─── tappeddelayline_2* (TappedDelayLine) │ └─── tappeddelayline_3* (TappedDelayLine) -│ └─── [ODELAYE2] -│ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [ODELAYE2] │ └─── [ISERDESE2] │ └─── [ODELAYE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [OSERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [OSERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [ODELAYE2] -│ └─── [ISERDESE2] -│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] │ └─── [IDELAYE2] -│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [OSERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [OSERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [ODELAYE2] +│ └─── [IOBUFDS] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [IOBUFDS] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] +│ └─── [IOBUFDS] │ └─── [OSERDESE2] │ └─── [ODELAYE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [ODELAYE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [IOBUFDS] -│ └─── [IDELAYE2] -│ └─── [ISERDESE2] -│ └─── [ISERDESE2] │ └─── [ODELAYE2] │ └─── [ODELAYE2] │ └─── [IDELAYE2] -│ └─── [IDELAYE2] -│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [IDELAYE2] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [IOBUF] -│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] │ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [ISERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [ODELAYE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] │ └─── [IDELAYE2] -│ └─── [IDELAYE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [OSERDESE2] -│ └─── [IOBUF] +│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [IOBUF] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [IOBUFDS] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] -│ └─── [ODELAYE2] │ └─── [ISERDESE2] -│ └─── [OBUFDS] -│ └─── [ODELAYE2] │ └─── [ODELAYE2] -│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] -│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] -│ └─── [IOBUF] +│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [ODELAYE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [ODELAYE2] │ └─── [ODELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [OSERDESE2] │ └─── [ODELAYE2] -│ └─── [ISERDESE2] -│ └─── [ODELAYE2] -│ └─── [ISERDESE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] -│ └─── [IOBUFDS] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [ODELAYE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [ODELAYE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] │ └─── [ODELAYE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [OSERDESE2] │ └─── [ODELAYE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [OSERDESE2] │ └─── [ODELAYE2] -│ └─── [ISERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] │ └─── [ODELAYE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] -│ └─── [IOBUF] │ └─── [ODELAYE2] -│ └─── [IOBUF] +│ └─── [IOBUFDS] │ └─── [OSERDESE2] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [ODELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] │ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUFDS] +│ └─── [ODELAYE2] +│ └─── [OBUFDS] +│ └─── [ODELAYE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) │ │ └─── pi0 (PhaseInjector) @@ -748,6 +748,7 @@ wire [29:0] builder_interface0_adr; wire [13:0] builder_interface0_bank_bus_adr; reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_re; wire builder_interface0_bank_bus_we; wire [1:0] builder_interface0_bte; wire [2:0] builder_interface0_cti; @@ -764,17 +765,22 @@ reg builder_interface1_adr_next_value_ce1 = 1'd0; wire [13:0] builder_interface1_bank_bus_adr; reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_re; wire builder_interface1_bank_bus_we; wire [31:0] builder_interface1_dat_r; reg [31:0] builder_interface1_dat_w = 32'd0; reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_re = 1'd0; +reg builder_interface1_re_next_value2 = 1'd0; +reg builder_interface1_re_next_value_ce2 = 1'd0; reg builder_interface1_we = 1'd0; -reg builder_interface1_we_next_value2 = 1'd0; -reg builder_interface1_we_next_value_ce2 = 1'd0; +reg builder_interface1_we_next_value3 = 1'd0; +reg builder_interface1_we_next_value_ce3 = 1'd0; wire [13:0] builder_interface2_bank_bus_adr; reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_re; wire builder_interface2_bank_bus_we; reg builder_locked0 = 1'd0; reg builder_locked1 = 1'd0; @@ -799,6 +805,7 @@ reg builder_new_master_wdata_ready0 = 1'd0; reg builder_new_master_wdata_ready1 = 1'd0; reg [1:0] builder_next_state = 2'd0; wire builder_pll_fb; +wire builder_re; reg [1:0] builder_refresher_next_state = 2'd0; reg [1:0] builder_refresher_state = 2'd0; wire builder_reset0; @@ -905,14 +912,14 @@ reg builder_t_self3 = 1'd0; reg builder_t_self4 = 1'd0; reg builder_t_self5 = 1'd0; wire builder_we; -wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1; wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2; wire builder_xilinxasyncresetsynchronizerimpl2_expr; wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_expr; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; @@ -2383,9 +2390,9 @@ reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p0_address; wire [2:0] main_litedramcore_csr_dfi_p0_bank; reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +wire main_litedramcore_csr_dfi_p0_cke; reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +wire main_litedramcore_csr_dfi_p0_odt; reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [63:0] main_litedramcore_csr_dfi_p0_rddata = 64'd0; wire main_litedramcore_csr_dfi_p0_rddata_en; @@ -2399,9 +2406,9 @@ reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p1_address; wire [2:0] main_litedramcore_csr_dfi_p1_bank; reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +wire main_litedramcore_csr_dfi_p1_cke; reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +wire main_litedramcore_csr_dfi_p1_odt; reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [63:0] main_litedramcore_csr_dfi_p1_rddata = 64'd0; wire main_litedramcore_csr_dfi_p1_rddata_en; @@ -2415,9 +2422,9 @@ reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p2_address; wire [2:0] main_litedramcore_csr_dfi_p2_bank; reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +wire main_litedramcore_csr_dfi_p2_cke; reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +wire main_litedramcore_csr_dfi_p2_odt; reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; reg [63:0] main_litedramcore_csr_dfi_p2_rddata = 64'd0; wire main_litedramcore_csr_dfi_p2_rddata_en; @@ -2431,9 +2438,9 @@ reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p3_address; wire [2:0] main_litedramcore_csr_dfi_p3_bank; reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +wire main_litedramcore_csr_dfi_p3_cke; reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +wire main_litedramcore_csr_dfi_p3_odt; reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; reg [63:0] main_litedramcore_csr_dfi_p3_rddata = 64'd0; wire main_litedramcore_csr_dfi_p3_rddata_en; @@ -6423,42 +6430,26 @@ always @(*) begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_cke <= 1'd0; - main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_cke <= 1'd0; - main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_cke <= 1'd0; - main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_cke <= 1'd0; - main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p0_odt <= 1'd0; - main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_odt <= 1'd0; - main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_odt <= 1'd0; - main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_odt <= 1'd0; - main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; -end +assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt; assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); + end else begin + main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p0_cs_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -6491,20 +6482,20 @@ always @(*) begin main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_csr_dfi_p0_cas_n <= (~main_litedramcore_phaseinjector0_csrfield_cas); - end else begin - main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); + end else begin + main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p1_cs_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -6537,14 +6528,6 @@ always @(*) begin main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_csr_dfi_p1_cas_n <= (~main_litedramcore_phaseinjector1_csrfield_cas); - end else begin - main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); @@ -6552,10 +6535,18 @@ assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin - if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin - main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; + main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); + end else begin + main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + if (main_litedramcore_phaseinjector2_csrfield_cs_top) begin + main_litedramcore_csr_dfi_p2_cs_n <= 2'd2; end else begin if (main_litedramcore_phaseinjector2_csrfield_cs_bottom) begin main_litedramcore_csr_dfi_p2_cs_n <= 1'd1; @@ -6583,20 +6574,20 @@ always @(*) begin main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_csr_dfi_p2_cas_n <= (~main_litedramcore_phaseinjector2_csrfield_cas); - end else begin - main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); + end else begin + main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p3_cs_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -6629,14 +6620,6 @@ always @(*) begin main_litedramcore_csr_dfi_p3_we_n <= 1'd1; end end -always @(*) begin - main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_csr_dfi_p3_cas_n <= (~main_litedramcore_phaseinjector3_csrfield_cas); - end else begin - main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); @@ -6744,22 +6727,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; - case (builder_refresher_state) - 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) @@ -6826,6 +6793,22 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_sequencer_start0 <= 1'd0; + case (builder_refresher_state) + 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine0_sink_valid = main_litedramcore_bankmachine0_req_valid; assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_sink_ready; assign main_litedramcore_bankmachine0_sink_payload_we = main_litedramcore_bankmachine0_req_we; @@ -6965,74 +6948,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_source_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (builder_bankmachine0_state) @@ -7397,6 +7312,74 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; @@ -7537,7 +7520,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end @@ -7546,6 +7529,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7556,37 +7542,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_source_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - if (main_litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine1_row_open <= 1'd0; case (builder_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end end 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7667,32 +7638,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine1_row_open <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) @@ -7968,6 +7913,44 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + if (main_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; @@ -8107,32 +8090,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine2_row_close <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) @@ -8294,6 +8251,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) @@ -8447,18 +8430,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin - if (main_litedramcore_bankmachine2_twtpcon_ready) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8473,15 +8456,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_row_open <= 1'd0; + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_open <= 1'd1; + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8495,25 +8481,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -8524,18 +8519,6 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_source_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end @@ -8665,48 +8648,13 @@ always @(*) begin if (main_litedramcore_bankmachine3_row_opened) begin if (main_litedramcore_bankmachine3_row_hit) begin if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin - builder_bankmachine3_next_state <= 2'd2; - end - end else begin - builder_bankmachine3_next_state <= 1'd1; - end - end else begin - builder_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_source_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + builder_bankmachine3_next_state <= 2'd2; + end end else begin + builder_bankmachine3_next_state <= 1'd1; end end else begin + builder_bankmachine3_next_state <= 2'd3; end end end @@ -9110,6 +9058,41 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; @@ -9249,74 +9232,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine4_trccon_ready) begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_source_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (builder_bankmachine4_state) @@ -9681,6 +9596,74 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine4_trccon_ready) begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; @@ -9821,7 +9804,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -9830,6 +9813,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9840,37 +9826,22 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_source_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if (main_litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine5_row_open <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; + end end 3'd4: begin - if (main_litedramcore_bankmachine5_twtpcon_ready) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9951,32 +9922,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine5_row_open <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -10119,12 +10064,35 @@ always @(*) begin 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin end 3'd4: begin - main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10135,11 +10103,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + if (main_litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -10164,8 +10147,8 @@ always @(*) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin if (main_litedramcore_bankmachine5_source_source_payload_we) begin + main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin - main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10177,7 +10160,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -10202,7 +10185,7 @@ always @(*) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin if (main_litedramcore_bankmachine5_source_source_payload_we) begin - main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin end end else begin @@ -10215,7 +10198,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (builder_bankmachine5_state) 1'd1: begin end @@ -10240,8 +10223,8 @@ always @(*) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin if (main_litedramcore_bankmachine5_source_source_payload_we) begin - main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready; end else begin + main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -10391,32 +10374,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine6_row_close <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) @@ -10757,15 +10714,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_row_open <= 1'd0; + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_open <= 1'd1; + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin @@ -10779,22 +10739,57 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + main_litedramcore_bankmachine6_row_close <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + main_litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -10808,18 +10803,6 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_source_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end @@ -10962,41 +10945,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (builder_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) @@ -11394,6 +11342,41 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (builder_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_nphases = (main_k7ddrphy_rdphase_storage - 1'd1); assign main_litedramcore_rdphase = (main_k7ddrphy_wrphase_storage - 1'd1); assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))); @@ -11640,34 +11623,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_en1 <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - main_litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_steerer0 <= 2'd0; case (builder_multiplexer_state) @@ -11987,6 +11942,34 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_en1 <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + main_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) @@ -12096,24 +12079,24 @@ assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == assign main_user_port_wdata_ready = builder_new_master_wdata_ready1; assign main_user_port_rdata_valid = builder_new_master_rdata_valid8; always @(*) begin - main_litedramcore_interface_wdata_we <= 32'd0; + main_litedramcore_interface_wdata <= 256'd0; case ({builder_new_master_wdata_ready1}) 1'd1: begin - main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; + main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; end default: begin - main_litedramcore_interface_wdata_we <= 1'd0; + main_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - main_litedramcore_interface_wdata <= 256'd0; + main_litedramcore_interface_wdata_we <= 32'd0; case ({builder_new_master_wdata_ready1}) 1'd1: begin - main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data; + main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we; end default: begin - main_litedramcore_interface_wdata <= 1'd0; + main_litedramcore_interface_wdata_we <= 1'd0; end endcase end @@ -12144,97 +12127,112 @@ always @(*) begin endcase end always @(*) begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface0_ack <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value2 <= 1'd0; end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); - end end endcase end always @(*) begin - builder_interface1_we_next_value_ce2 <= 1'd0; + builder_interface1_dat_w_next_value0 <= 32'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value_ce2 <= 1'd1; - end + builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; end endcase end always @(*) begin - builder_interface0_ack <= 1'd0; + builder_interface1_dat_w_next_value_ce0 <= 1'd0; case (builder_state) 1'd1: begin end 2'd2: begin - builder_interface0_ack <= 1'd1; end default: begin + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - builder_interface1_dat_w_next_value0 <= 32'd0; + builder_interface1_adr_next_value1 <= 14'd0; case (builder_state) 1'd1: begin + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - builder_interface1_dat_w_next_value0 <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr; + end end endcase end always @(*) begin - builder_interface1_dat_w_next_value_ce0 <= 1'd0; + builder_interface1_adr_next_value_ce1 <= 1'd0; case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin - builder_interface1_dat_w_next_value_ce0 <= 1'd1; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - builder_interface1_adr_next_value1 <= 14'd0; + builder_interface1_re_next_value2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_adr_next_value1 <= 1'd0; + builder_interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; + builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0)); end end endcase end always @(*) begin - builder_interface1_adr_next_value_ce1 <= 1'd0; + builder_interface1_re_next_value_ce2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_interface1_we_next_value3 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_we_next_value3 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); end end endcase @@ -12251,6 +12249,21 @@ always @(*) begin end endcase end +always @(*) begin + builder_interface1_we_next_value_ce3 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_we_next_value_ce3 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce3 <= 1'd1; + end + end + endcase +end assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin @@ -12262,20 +12275,20 @@ end always @(*) begin builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re; end end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re; end end always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end assign builder_csrbank0_init_done0_w = main_init_done_storage; @@ -12283,48 +12296,48 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[3:0]; always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -12335,22 +12348,22 @@ always @(*) begin end assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_wlevel_strobe_re <= 1'd0; + main_k7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_k7ddrphy_wlevel_strobe_we <= 1'd0; + main_k7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end assign main_k7ddrphy_cdly_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_k7ddrphy_cdly_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_k7ddrphy_cdly_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_cdly_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -12361,41 +12374,41 @@ always @(*) begin end assign main_k7ddrphy_cdly_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_cdly_inc_we <= 1'd0; + main_k7ddrphy_cdly_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_k7ddrphy_cdly_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_k7ddrphy_cdly_inc_re <= 1'd0; + main_k7ddrphy_cdly_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_k7ddrphy_cdly_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_cdly_inc_we <= builder_interface1_bank_bus_re; end end assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_rdly_dq_rst_we <= 1'd0; + main_k7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_k7ddrphy_rdly_dq_rst_re <= 1'd0; + main_k7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re; end end assign main_k7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_rdly_dq_inc_we <= 1'd0; + main_k7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_k7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_k7ddrphy_rdly_dq_inc_re <= 1'd0; + main_k7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_k7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re; end end assign main_k7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; @@ -12408,53 +12421,53 @@ end always @(*) begin main_k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_k7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end assign main_k7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_k7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_k7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_k7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_wdly_dq_rst_re <= 1'd0; + main_k7ddrphy_wdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_k7ddrphy_wdly_dq_rst_we <= 1'd0; + main_k7ddrphy_wdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we; end end assign main_k7ddrphy_wdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_wdly_dq_inc_re <= 1'd0; + main_k7ddrphy_wdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_inc_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_k7ddrphy_wdly_dq_inc_we <= 1'd0; + main_k7ddrphy_wdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - main_k7ddrphy_wdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_inc_re <= builder_interface1_bank_bus_we; end end assign main_k7ddrphy_wdly_dqs_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_k7ddrphy_wdly_dqs_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - main_k7ddrphy_wdly_dqs_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dqs_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -12465,75 +12478,75 @@ always @(*) begin end assign main_k7ddrphy_wdly_dqs_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_wdly_dqs_inc_we <= 1'd0; + main_k7ddrphy_wdly_dqs_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - main_k7ddrphy_wdly_dqs_inc_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_k7ddrphy_wdly_dqs_inc_re <= 1'd0; + main_k7ddrphy_wdly_dqs_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - main_k7ddrphy_wdly_dqs_inc_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dqs_inc_we <= builder_interface1_bank_bus_re; end end assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end assign main_k7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - main_k7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_k7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_k7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - main_k7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_k7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_rst0_w = main_k7ddrphy_rst_storage; -assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0]; -assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_k7ddrphy_half_sys8x_taps_storage; assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage; -assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0]; -assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage; +assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin @@ -12545,14 +12558,14 @@ end always @(*) begin builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12563,48 +12576,48 @@ always @(*) begin end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi0_address0_we <= 1'd0; + builder_csrbank2_dfii_pi0_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - builder_csrbank2_dfii_pi0_address0_re <= 1'd0; + builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; + builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata1_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12613,7 +12626,7 @@ always @(*) begin builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin @@ -12623,27 +12636,27 @@ end always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; + builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi0_rddata1_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0; + builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12654,48 +12667,48 @@ always @(*) begin end assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - builder_csrbank2_dfii_pi1_command0_we <= 1'd0; + builder_csrbank2_dfii_pi1_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - builder_csrbank2_dfii_pi1_command0_re <= 1'd0; + builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin - builder_csrbank2_dfii_pi1_address0_re <= 1'd0; + builder_csrbank2_dfii_pi1_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi1_address0_we <= 1'd0; + builder_csrbank2_dfii_pi1_address0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12704,7 +12717,7 @@ always @(*) begin builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin @@ -12714,36 +12727,36 @@ end always @(*) begin builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata1_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; + builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; end end always @(*) begin - builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0; + builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi1_rddata1_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin @@ -12753,40 +12766,40 @@ end always @(*) begin builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin - builder_csrbank2_dfii_pi2_command0_re <= 1'd0; + builder_csrbank2_dfii_pi2_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi2_command0_we <= 1'd0; + builder_csrbank2_dfii_pi2_command0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we; end end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12805,36 +12818,36 @@ end always @(*) begin builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata1_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin @@ -12844,27 +12857,27 @@ end always @(*) begin builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata1_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; + builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi2_rddata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0; + builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi3_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12877,7 +12890,7 @@ assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_ban always @(*) begin main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12896,36 +12909,36 @@ end always @(*) begin builder_csrbank2_dfii_pi3_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; + builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin - builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; + builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; end end always @(*) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin - builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_wrdata1_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin @@ -12935,14 +12948,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin - builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata1_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -12951,24 +12964,24 @@ always @(*) begin builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; + builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; end end always @(*) begin - builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0; + builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin - builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_dfii_pi3_rddata0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; -assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage; assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; @@ -12977,9 +12990,9 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; -assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0]; -assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage; assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[63:32]; assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[63:32]; @@ -12993,9 +13006,9 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; -assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0]; -assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage; assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[63:32]; assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[63:32]; @@ -13009,9 +13022,9 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; -assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0]; -assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage; assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[63:32]; assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[63:32]; @@ -13025,21 +13038,25 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; -assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0]; -assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage; assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[63:32]; assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[63:32]; assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we; assign builder_adr = builder_interface1_adr; +assign builder_re = builder_interface1_re; assign builder_we = builder_interface1_we; assign builder_dat_w = builder_interface1_dat_w; assign builder_interface1_dat_r = builder_dat_r; assign builder_interface0_bank_bus_adr = builder_adr; assign builder_interface1_bank_bus_adr = builder_adr; assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_re = builder_re; +assign builder_interface1_bank_bus_re = builder_re; +assign builder_interface2_bank_bus_re = builder_re; assign builder_interface0_bank_bus_we = builder_we; assign builder_interface1_bank_bus_we = builder_we; assign builder_interface2_bank_bus_we = builder_we; @@ -13765,16 +13782,16 @@ always @(*) begin builder_self0 <= 3'd0; case (main_litedramcore_steerer0) 1'd0: begin - builder_self0 <= main_litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -13884,16 +13901,16 @@ always @(*) begin builder_self7 <= 3'd0; case (main_litedramcore_steerer1) 1'd0: begin - builder_self7 <= main_litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -14003,16 +14020,16 @@ always @(*) begin builder_self14 <= 3'd0; case (main_litedramcore_steerer2) 1'd0: begin - builder_self14 <= main_litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -14122,16 +14139,16 @@ always @(*) begin builder_self21 <= 3'd0; case (main_litedramcore_steerer3) 1'd0: begin - builder_self21 <= main_litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -14237,10 +14254,10 @@ always @(*) begin end endcase end -assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); //------------------------------------------------------------------------------ @@ -16090,8 +16107,11 @@ always @(posedge sys_clk) begin if (builder_interface1_adr_next_value_ce1) begin builder_interface1_adr <= builder_interface1_adr_next_value1; end - if (builder_interface1_we_next_value_ce2) begin - builder_interface1_we <= builder_interface1_we_next_value2; + if (builder_interface1_re_next_value_ce2) begin + builder_interface1_re <= builder_interface1_re_next_value2; + end + if (builder_interface1_we_next_value_ce3) begin + builder_interface1_we <= builder_interface1_we_next_value3; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin @@ -16179,11 +16199,11 @@ always @(posedge sys_clk) begin end main_k7ddrphy_rst_re <= builder_csrbank1_rst0_re; if (builder_csrbank1_dly_sel0_re) begin - main_k7ddrphy_dly_sel_storage[3:0] <= builder_csrbank1_dly_sel0_r; + main_k7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r; end main_k7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; if (builder_csrbank1_half_sys8x_taps0_re) begin - main_k7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; + main_k7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r; end main_k7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; if (builder_csrbank1_wlevel_en0_re) begin @@ -16191,11 +16211,11 @@ always @(posedge sys_clk) begin end main_k7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; if (builder_csrbank1_rdphase0_re) begin - main_k7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + main_k7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r; end main_k7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; if (builder_csrbank1_wrphase0_re) begin - main_k7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + main_k7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r; end main_k7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; builder_interface2_bank_bus_dat_r <= 1'd0; @@ -16303,19 +16323,19 @@ always @(posedge sys_clk) begin endcase end if (builder_csrbank2_dfii_control0_re) begin - main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + main_litedramcore_storage <= builder_csrbank2_dfii_control0_r; end main_litedramcore_re <= builder_csrbank2_dfii_control0_re; if (builder_csrbank2_dfii_pi0_command0_re) begin - main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; + main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin - main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; if (builder_csrbank2_dfii_pi0_wrdata1_re) begin @@ -16327,15 +16347,15 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re; if (builder_csrbank2_dfii_pi1_command0_re) begin - main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin - main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; if (builder_csrbank2_dfii_pi1_wrdata1_re) begin @@ -16347,15 +16367,15 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re; if (builder_csrbank2_dfii_pi2_command0_re) begin - main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin - main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; if (builder_csrbank2_dfii_pi2_wrdata1_re) begin @@ -16367,15 +16387,15 @@ always @(posedge sys_clk) begin main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re; if (builder_csrbank2_dfii_pi3_command0_re) begin - main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin - main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; if (builder_csrbank2_dfii_pi3_wrdata1_re) begin @@ -16690,6 +16710,7 @@ always @(posedge sys_clk) begin main_init_done_re <= 1'd0; main_init_error_storage <= 1'd0; main_init_error_re <= 1'd0; + builder_interface1_re <= 1'd0; builder_interface1_we <= 1'd0; builder_refresher_state <= 2'd0; builder_bankmachine0_state <= 4'd0; @@ -23218,7 +23239,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) @@ -23236,7 +23257,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (iodelay_rst) @@ -23254,7 +23275,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) @@ -23272,7 +23293,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (sys_rst) @@ -23290,7 +23311,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) @@ -23308,7 +23329,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) @@ -23326,7 +23347,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) @@ -23344,7 +23365,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) @@ -23353,5 +23374,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:08. +// Auto-Generated by LiteX on 2025-02-15 19:54:43. //------------------------------------------------------------------------------ diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 0573632..843a495 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ 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+eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1853,14 +1879,18 @@ e8010010ebc1fff0 696c62616e652020 004441555120676e 006e6f7263694d20 +0000004953534920 +696c62616e655b20 +5d6461757120676e +0000000000000000 4920646175715b20 005d65646f6d204f 414c462049505320 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1921,15 +1951,13 @@ e8010010ebc1fff0 000000000000207c 203a747365622020 302562202c64256d -6000000000206432 +0000000000206432 76656c2064616552 000a3a676e696c65 696c616974696e49 52445320676e697a 3025783040204d41 000a2e2e2e786c38 -000000540000002a -6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 @@ -1971,11 +1999,12 @@ e8010010ebc1fff0 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index bab09c2..f8000fe 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:06 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:40 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -81,17 +81,17 @@ LiteDRAMCore │ └─── pll (S7PLL) │ │ └─── [FDCE] │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] -│ │ └─── [BUFG] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [PLLE2_ADV] │ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [BUFG] │ └─── idelayctrl (S7IDELAYCTRL) │ │ └─── [IDELAYCTRL] └─── ddrphy (A7DDRPHY) @@ -136,103 +136,103 @@ LiteDRAMCore │ └─── bitslip_35* (BitSlip) │ └─── tappeddelayline_2* (TappedDelayLine) │ └─── tappeddelayline_3* (TappedDelayLine) +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [IOBUFDS] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [IDELAYE2] -│ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [OBUFDS] -│ └─── [OSERDESE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] -│ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [OSERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [IOBUFDS] -│ └─── [IOBUF] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] +│ └─── [IOBUFDS] +│ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [IDELAYE2] │ └─── [ISERDESE2] -│ └─── [OSERDESE2] -│ └─── [IOBUF] +│ └─── [IDELAYE2] │ └─── [IDELAYE2] │ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [ISERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] │ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OBUFDS] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] +│ └─── [OSERDESE2] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) │ │ └─── pi0 (PhaseInjector) @@ -544,6 +544,7 @@ wire [29:0] builder_interface0_adr; wire [13:0] builder_interface0_bank_bus_adr; reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_re; wire builder_interface0_bank_bus_we; wire [1:0] builder_interface0_bte; wire [2:0] builder_interface0_cti; @@ -560,17 +561,22 @@ reg builder_interface1_adr_next_value_ce1 = 1'd0; wire [13:0] builder_interface1_bank_bus_adr; reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_re; wire builder_interface1_bank_bus_we; wire [31:0] builder_interface1_dat_r; reg [31:0] builder_interface1_dat_w = 32'd0; reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_re = 1'd0; +reg builder_interface1_re_next_value2 = 1'd0; +reg builder_interface1_re_next_value_ce2 = 1'd0; reg builder_interface1_we = 1'd0; -reg builder_interface1_we_next_value2 = 1'd0; -reg builder_interface1_we_next_value_ce2 = 1'd0; +reg builder_interface1_we_next_value3 = 1'd0; +reg builder_interface1_we_next_value_ce3 = 1'd0; wire [13:0] builder_interface2_bank_bus_adr; reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_re; wire builder_interface2_bank_bus_we; reg builder_locked0 = 1'd0; reg builder_locked1 = 1'd0; @@ -595,6 +601,7 @@ reg builder_new_master_wdata_ready0 = 1'd0; reg builder_new_master_wdata_ready1 = 1'd0; reg [1:0] builder_next_state = 2'd0; wire builder_pll_fb; +wire builder_re; reg [1:0] builder_refresher_next_state = 2'd0; reg [1:0] builder_refresher_state = 2'd0; wire builder_reset0; @@ -701,14 +708,14 @@ reg builder_t_self3 = 1'd0; reg builder_t_self4 = 1'd0; reg builder_t_self5 = 1'd0; wire builder_we; -wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1; wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2; wire builder_xilinxasyncresetsynchronizerimpl2_expr; wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_expr; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; @@ -1896,9 +1903,9 @@ reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p0_address; wire [2:0] main_litedramcore_csr_dfi_p0_bank; reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +wire main_litedramcore_csr_dfi_p0_cke; reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +wire main_litedramcore_csr_dfi_p0_odt; reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; wire main_litedramcore_csr_dfi_p0_rddata_en; @@ -1912,9 +1919,9 @@ reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p1_address; wire [2:0] main_litedramcore_csr_dfi_p1_bank; reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +wire main_litedramcore_csr_dfi_p1_cke; reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +wire main_litedramcore_csr_dfi_p1_odt; reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; wire main_litedramcore_csr_dfi_p1_rddata_en; @@ -1928,9 +1935,9 @@ reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p2_address; wire [2:0] main_litedramcore_csr_dfi_p2_bank; reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +wire main_litedramcore_csr_dfi_p2_cke; reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +wire main_litedramcore_csr_dfi_p2_odt; reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; wire main_litedramcore_csr_dfi_p2_rddata_en; @@ -1944,9 +1951,9 @@ reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; wire [14:0] main_litedramcore_csr_dfi_p3_address; wire [2:0] main_litedramcore_csr_dfi_p3_bank; reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +wire main_litedramcore_csr_dfi_p3_cke; reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +wire main_litedramcore_csr_dfi_p3_odt; reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; wire main_litedramcore_csr_dfi_p3_rddata_en; @@ -4764,58 +4771,18 @@ always @(*) begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_cke <= 1'd0; - main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_cke <= 1'd0; - main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_cke <= 1'd0; - main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_cke <= 1'd0; - main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p0_odt <= 1'd0; - main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_odt <= 1'd0; - main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_odt <= 1'd0; - main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_odt <= 1'd0; - main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; -end +assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt; assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; -always @(*) begin - main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end -end -always @(*) begin - main_litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); - end else begin - main_litedramcore_csr_dfi_p0_we_n <= 1'd1; - end -end always @(*) begin main_litedramcore_csr_dfi_p0_cas_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4840,28 +4807,28 @@ always @(*) begin main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end -assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; -assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; -assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); -assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); -assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; -assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); end else begin - main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end always @(*) begin - main_litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_we_n <= (~main_litedramcore_phaseinjector0_csrfield_we); end else begin - main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + main_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; +assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); +assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); +assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; +assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin main_litedramcore_csr_dfi_p1_cas_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4886,28 +4853,28 @@ always @(*) begin main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end -assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; -assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; -assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); -assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); -assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; -assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); end else begin - main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end always @(*) begin - main_litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_we_n <= (~main_litedramcore_phaseinjector1_csrfield_we); end else begin - main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + main_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; +assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); +assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); +assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; +assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin main_litedramcore_csr_dfi_p2_cas_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4932,28 +4899,28 @@ always @(*) begin main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end -assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; -assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; -assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); -assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); -assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; -assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); end else begin - main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end always @(*) begin - main_litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_we_n <= (~main_litedramcore_phaseinjector2_csrfield_we); end else begin - main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + main_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end +assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; +assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); +assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); +assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; +assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin main_litedramcore_csr_dfi_p3_cas_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4978,6 +4945,22 @@ always @(*) begin main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end +always @(*) begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end +end +always @(*) begin + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_we_n <= (~main_litedramcore_phaseinjector3_csrfield_we); + end else begin + main_litedramcore_csr_dfi_p3_we_n <= 1'd1; + end +end assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); @@ -5306,32 +5289,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine0_row_close <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - main_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine0_state) @@ -5738,23 +5695,49 @@ always @(*) begin end endcase end -assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; -assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; -assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; -assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; -assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; -assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; -assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; -assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; -assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; -assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; -assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); -assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); -assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]); -assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin + main_litedramcore_bankmachine0_row_close <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; +assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; +assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; +assign main_litedramcore_bankmachine1_sink_payload_addr = main_litedramcore_bankmachine1_req_addr; +assign main_litedramcore_bankmachine1_sink_sink_valid = main_litedramcore_bankmachine1_source_valid; +assign main_litedramcore_bankmachine1_source_ready = main_litedramcore_bankmachine1_sink_sink_ready; +assign main_litedramcore_bankmachine1_sink_sink_first = main_litedramcore_bankmachine1_source_first; +assign main_litedramcore_bankmachine1_sink_sink_last = main_litedramcore_bankmachine1_source_last; +assign main_litedramcore_bankmachine1_sink_sink_payload_we = main_litedramcore_bankmachine1_source_payload_we; +assign main_litedramcore_bankmachine1_sink_sink_payload_addr = main_litedramcore_bankmachine1_source_payload_addr; +assign main_litedramcore_bankmachine1_source_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid); +assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_source_valid | main_litedramcore_bankmachine1_source_source_valid); +assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_source_source_payload_addr[21:7]); +assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_source_source_payload_addr[21:7]; end else begin main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); @@ -5877,70 +5860,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_source_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (builder_bankmachine1_state) @@ -6309,6 +6228,70 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; @@ -6449,22 +6432,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6475,11 +6451,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6505,7 +6496,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_row_hit) begin if (main_litedramcore_bankmachine2_source_source_payload_we) begin end else begin - main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6517,7 +6508,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6526,6 +6517,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine2_twtpcon_ready) begin + main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6536,32 +6530,20 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_source_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_source_source_payload_we) begin - main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine2_row_open <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_open <= 1'd1; + end end 3'd4: begin end @@ -6574,32 +6556,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_source_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_source_source_payload_we) begin - main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_valid <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6617,10 +6590,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_source_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - if (main_litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready; - end + main_litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6631,18 +6601,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine2_row_close <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine2_twtpcon_ready) begin - main_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6657,7 +6627,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_row_open <= 1'd0; + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin end @@ -6665,7 +6635,7 @@ always @(*) begin end 2'd3: begin if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_open <= 1'd1; + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6683,19 +6653,13 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -6713,7 +6677,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_source_source_valid) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_valid <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6724,18 +6688,21 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_row_close <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6750,16 +6717,16 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -6772,19 +6739,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin + if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6795,35 +6784,17 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine2_source_source_valid) begin - if (main_litedramcore_bankmachine2_row_opened) begin - if (main_litedramcore_bankmachine2_row_hit) begin - main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -6836,16 +6807,28 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine2_source_source_valid) begin + if (main_litedramcore_bankmachine2_row_opened) begin + if (main_litedramcore_bankmachine2_row_hit) begin + if (main_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (builder_bankmachine2_state) 1'd1: begin - if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin - main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6868,7 +6851,7 @@ always @(*) begin if (main_litedramcore_bankmachine2_row_opened) begin if (main_litedramcore_bankmachine2_row_hit) begin if (main_litedramcore_bankmachine2_source_source_payload_we) begin - main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -6952,160 +6935,70 @@ assign main_litedramcore_bankmachine3_pipe_valid_sink_first = main_litedramcore_ assign main_litedramcore_bankmachine3_pipe_valid_sink_last = main_litedramcore_bankmachine3_sink_sink_last; assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_we = main_litedramcore_bankmachine3_sink_sink_payload_we; assign main_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = main_litedramcore_bankmachine3_sink_sink_payload_addr; -assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; -assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; -assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; -assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; -assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; -assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; -always @(*) begin - builder_bankmachine3_next_state <= 4'd0; - builder_bankmachine3_next_state <= builder_bankmachine3_state; - case (builder_bankmachine3_state) - 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - if (main_litedramcore_bankmachine3_cmd_ready) begin - builder_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - builder_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - if (main_litedramcore_bankmachine3_cmd_ready) begin - builder_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~main_litedramcore_bankmachine3_refresh_req)) begin - builder_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - builder_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - builder_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - builder_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - builder_bankmachine3_next_state <= 1'd0; - end - default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - builder_bankmachine3_next_state <= 3'd4; - end else begin - if (main_litedramcore_bankmachine3_source_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin - builder_bankmachine3_next_state <= 2'd2; - end - end else begin - builder_bankmachine3_next_state <= 1'd1; - end - end else begin - builder_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_source_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if (main_litedramcore_bankmachine3_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine3_twtpcon_ready) begin - main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end +assign main_litedramcore_bankmachine3_source_source_valid = main_litedramcore_bankmachine3_pipe_valid_source_valid; +assign main_litedramcore_bankmachine3_pipe_valid_source_ready = main_litedramcore_bankmachine3_source_source_ready; +assign main_litedramcore_bankmachine3_source_source_first = main_litedramcore_bankmachine3_pipe_valid_source_first; +assign main_litedramcore_bankmachine3_source_source_last = main_litedramcore_bankmachine3_pipe_valid_source_last; +assign main_litedramcore_bankmachine3_source_source_payload_we = main_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign main_litedramcore_bankmachine3_source_source_payload_addr = main_litedramcore_bankmachine3_pipe_valid_source_payload_addr; always @(*) begin - main_litedramcore_bankmachine3_row_open <= 1'd0; + builder_bankmachine3_next_state <= 4'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; case (builder_bankmachine3_state) 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + end end 2'd2: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end end 2'd3: begin if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_open <= 1'd1; + if (main_litedramcore_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine3_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine3_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine3_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine3_next_state <= 1'd0; end default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end + end else begin + builder_bankmachine3_next_state <= 1'd1; + end + end else begin + builder_bankmachine3_next_state <= 2'd3; + end + end + end end endcase end @@ -7176,6 +7069,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) @@ -7451,6 +7370,70 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine3_twtpcon_ready) begin + main_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; @@ -7651,32 +7634,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine4_row_close <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (builder_bankmachine4_state) @@ -8022,6 +7979,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine4_row_close <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; @@ -8153,75 +8136,11 @@ always @(*) begin end else begin builder_bankmachine5_next_state <= 1'd1; end - end else begin - builder_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine5_source_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + end else begin + builder_bankmachine5_next_state <= 2'd3; + end + end + end end endcase end @@ -8593,6 +8512,70 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; @@ -8733,22 +8716,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8759,11 +8735,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -8789,7 +8780,7 @@ always @(*) begin if (main_litedramcore_bankmachine6_row_hit) begin if (main_litedramcore_bankmachine6_source_source_payload_we) begin end else begin - main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -8801,7 +8792,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -8810,6 +8801,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine6_twtpcon_ready) begin + main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8820,32 +8814,20 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_source_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_source_source_payload_we) begin - main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine6_row_open <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_open <= 1'd1; + end end 3'd4: begin end @@ -8858,32 +8840,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_source_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_source_source_payload_we) begin - main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_valid <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -8901,10 +8874,7 @@ always @(*) begin if (main_litedramcore_bankmachine6_source_source_valid) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin - if (main_litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready; - end + main_litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -8915,18 +8885,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine6_row_close <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine6_twtpcon_ready) begin - main_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -8941,7 +8911,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_row_open <= 1'd0; + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin end @@ -8949,7 +8919,7 @@ always @(*) begin end 2'd3: begin if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_open <= 1'd1; + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -8967,19 +8937,13 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8997,7 +8961,7 @@ always @(*) begin if (main_litedramcore_bankmachine6_source_source_valid) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_valid <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -9008,18 +8972,21 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_row_close <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 3'd4: begin - main_litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9034,16 +9001,16 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9056,19 +9023,41 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin + if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9079,35 +9068,17 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine6_source_source_valid) begin - if (main_litedramcore_bankmachine6_row_opened) begin - if (main_litedramcore_bankmachine6_row_hit) begin - main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 3'd4: begin end @@ -9120,16 +9091,28 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine6_source_source_valid) begin + if (main_litedramcore_bankmachine6_row_opened) begin + if (main_litedramcore_bankmachine6_row_hit) begin + if (main_litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (builder_bankmachine6_state) 1'd1: begin - if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin - main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9152,7 +9135,7 @@ always @(*) begin if (main_litedramcore_bankmachine6_row_opened) begin if (main_litedramcore_bankmachine6_row_hit) begin if (main_litedramcore_bankmachine6_source_source_payload_we) begin - main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin end end else begin @@ -9304,13 +9287,19 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9328,10 +9317,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_source_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; - end + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9342,18 +9328,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine7_twtpcon_ready) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9394,18 +9380,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9419,34 +9402,19 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_close <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9457,19 +9425,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9487,9 +9470,12 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9511,7 +9497,10 @@ always @(*) begin if (main_litedramcore_bankmachine7_source_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -9522,21 +9511,22 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9551,12 +9541,9 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9579,8 +9566,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9592,22 +9579,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9618,11 +9598,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9647,8 +9642,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9660,7 +9655,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9685,8 +9680,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9698,7 +9693,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9707,6 +9702,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9717,21 +9715,6 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end @@ -9981,97 +9964,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_en0 <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - main_litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - main_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - main_litedramcore_choose_req_want_reads <= 1'd0; - case (builder_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - main_litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end always @(*) begin main_litedramcore_choose_req_want_writes <= 1'd0; case (builder_multiplexer_state) @@ -10101,13 +9993,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; + main_litedramcore_steerer3 <= 2'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; + end + if ((main_litedramcore_rdphase == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end 2'd2: begin @@ -10129,19 +10023,25 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + main_litedramcore_steerer3 <= 1'd0; + if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin + main_litedramcore_steerer3 <= 2'd2; + end + if ((main_litedramcore_nphases == 2'd3)) begin + main_litedramcore_steerer3 <= 1'd1; end end endcase end always @(*) begin - main_litedramcore_en1 <= 1'd0; + main_litedramcore_choose_req_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_en1 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10162,20 +10062,19 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end endcase end always @(*) begin - main_litedramcore_steerer3 <= 2'd0; + main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_steerer3 <= 1'd0; - if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin - main_litedramcore_steerer3 <= 2'd2; - end - if ((main_litedramcore_rdphase == 2'd3)) begin - main_litedramcore_steerer3 <= 1'd1; - end + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10196,13 +10095,6 @@ always @(*) begin 4'd10: begin end default: begin - main_litedramcore_steerer3 <= 1'd0; - if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin - main_litedramcore_steerer3 <= 2'd2; - end - if ((main_litedramcore_nphases == 2'd3)) begin - main_litedramcore_steerer3 <= 1'd1; - end end endcase end @@ -10393,6 +10285,97 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_en0 <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + main_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + main_litedramcore_choose_req_want_reads <= 1'd0; + case (builder_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + main_litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)}; assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock)); assign main_litedramcore_interface_bank0_addr = builder_rhs_self12; @@ -10484,6 +10467,36 @@ always @(*) begin end endcase end +always @(*) begin + builder_interface1_we_next_value3 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_we_next_value3 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + builder_interface1_we_next_value_ce3 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_we_next_value_ce3 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_we_next_value_ce3 <= 1'd1; + end + end + endcase +end always @(*) begin builder_interface0_dat_r <= 32'd0; case (builder_state) @@ -10509,41 +10522,41 @@ always @(*) begin endcase end always @(*) begin - builder_interface1_dat_w_next_value_ce0 <= 1'd0; + builder_interface0_ack <= 1'd0; case (builder_state) 1'd1: begin end 2'd2: begin + builder_interface0_ack <= 1'd1; end default: begin - builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - builder_interface1_adr_next_value1 <= 14'd0; + builder_interface1_dat_w_next_value_ce0 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; - end + builder_interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - builder_interface0_ack <= 1'd0; + builder_interface1_adr_next_value1 <= 14'd0; case (builder_state) 1'd1: begin + builder_interface1_adr_next_value1 <= 1'd0; end 2'd2: begin - builder_interface0_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value1 <= builder_interface0_adr; + end end endcase end @@ -10563,31 +10576,31 @@ always @(*) begin endcase end always @(*) begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_re_next_value2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0)); end end endcase end always @(*) begin - builder_interface1_we_next_value_ce2 <= 1'd0; + builder_interface1_re_next_value_ce2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_re_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_re_next_value_ce2 <= 1'd1; end end endcase @@ -10595,28 +10608,28 @@ end assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_done0_we <= 1'd0; + builder_csrbank0_init_done0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - builder_csrbank0_init_done0_re <= 1'd0; + builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re; end end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re; end end always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end assign builder_csrbank0_init_done0_w = main_init_done_storage; @@ -10624,28 +10637,28 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; @@ -10658,66 +10671,66 @@ end always @(*) begin builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_wlevel_en0_re <= 1'd0; + builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_wlevel_en0_we <= 1'd0; + builder_csrbank1_wlevel_en0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wlevel_strobe_re <= 1'd0; + main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_wlevel_strobe_we <= 1'd0; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -10728,81 +10741,81 @@ always @(*) begin end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; -assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; -assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage; assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; -assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; -assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10821,27 +10834,27 @@ end always @(*) begin builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10854,7 +10867,7 @@ assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w always @(*) begin builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10863,7 +10876,7 @@ always @(*) begin builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin @@ -10873,14 +10886,14 @@ end always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10893,7 +10906,7 @@ assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[ always @(*) begin builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10904,15 +10917,15 @@ always @(*) begin end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[14:0]; @@ -10925,14 +10938,14 @@ end always @(*) begin builder_csrbank2_dfii_pi1_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10941,7 +10954,7 @@ always @(*) begin builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin @@ -10951,10 +10964,10 @@ end always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin @@ -10964,14 +10977,14 @@ end always @(*) begin builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10990,7 +11003,7 @@ end always @(*) begin main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[14:0]; @@ -11003,7 +11016,7 @@ end always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; @@ -11016,14 +11029,14 @@ end always @(*) begin builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11032,7 +11045,7 @@ always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin @@ -11042,7 +11055,7 @@ end always @(*) begin builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[7:0]; @@ -11055,27 +11068,27 @@ end always @(*) begin builder_csrbank2_dfii_pi3_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector3_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[14:0]; always @(*) begin builder_csrbank2_dfii_pi3_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11094,14 +11107,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11110,11 +11123,11 @@ always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11127,7 +11140,7 @@ assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; -assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage; assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; @@ -11136,11 +11149,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; -assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[14:0]; -assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status; assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; @@ -11150,11 +11163,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; -assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[14:0]; -assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status; assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; @@ -11164,11 +11177,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; -assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[14:0]; -assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status; assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; @@ -11178,19 +11191,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; -assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[14:0]; -assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status; assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_adr = builder_interface1_adr; +assign builder_re = builder_interface1_re; assign builder_we = builder_interface1_we; assign builder_dat_w = builder_interface1_dat_w; assign builder_interface1_dat_r = builder_dat_r; assign builder_interface0_bank_bus_adr = builder_adr; assign builder_interface1_bank_bus_adr = builder_adr; assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_re = builder_re; +assign builder_interface1_bank_bus_re = builder_re; +assign builder_interface2_bank_bus_re = builder_re; assign builder_interface0_bank_bus_we = builder_we; assign builder_interface1_bank_bus_we = builder_we; assign builder_interface2_bank_bus_we = builder_we; @@ -11916,16 +11933,16 @@ always @(*) begin builder_self0 <= 3'd0; case (main_litedramcore_steerer0) 1'd0: begin - builder_self0 <= main_litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12035,16 +12052,16 @@ always @(*) begin builder_self7 <= 3'd0; case (main_litedramcore_steerer1) 1'd0: begin - builder_self7 <= main_litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12154,16 +12171,16 @@ always @(*) begin builder_self14 <= 3'd0; case (main_litedramcore_steerer2) 1'd0: begin - builder_self14 <= main_litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12273,16 +12290,16 @@ always @(*) begin builder_self21 <= 3'd0; case (main_litedramcore_steerer3) 1'd0: begin - builder_self21 <= main_litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12388,10 +12405,10 @@ always @(*) begin end endcase end -assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); //------------------------------------------------------------------------------ @@ -13990,8 +14007,11 @@ always @(posedge sys_clk) begin if (builder_interface1_adr_next_value_ce1) begin builder_interface1_adr <= builder_interface1_adr_next_value1; end - if (builder_interface1_we_next_value_ce2) begin - builder_interface1_we <= builder_interface1_we_next_value2; + if (builder_interface1_re_next_value_ce2) begin + builder_interface1_re <= builder_interface1_re_next_value2; + end + if (builder_interface1_we_next_value_ce3) begin + builder_interface1_we <= builder_interface1_we_next_value3; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin @@ -14061,11 +14081,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; if (builder_csrbank1_dly_sel0_re) begin - main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; + main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r; end main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; if (builder_csrbank1_half_sys8x_taps0_re) begin - main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r; end main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; if (builder_csrbank1_wlevel_en0_re) begin @@ -14073,11 +14093,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; if (builder_csrbank1_rdphase0_re) begin - main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r; end main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; if (builder_csrbank1_wrphase0_re) begin - main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r; end main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; builder_interface2_bank_bus_dat_r <= 1'd0; @@ -14161,74 +14181,74 @@ always @(posedge sys_clk) begin endcase end if (builder_csrbank2_dfii_control0_re) begin - main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + main_litedramcore_storage <= builder_csrbank2_dfii_control0_r; end main_litedramcore_re <= builder_csrbank2_dfii_control0_re; if (builder_csrbank2_dfii_pi0_command0_re) begin - main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; + main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[14:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin - main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin - main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[14:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin - main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin - main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[14:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin - main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin - main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[14:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin - main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; @@ -14501,6 +14521,7 @@ always @(posedge sys_clk) begin main_init_done_re <= 1'd0; main_init_error_storage <= 1'd0; main_init_error_re <= 1'd0; + builder_interface1_re <= 1'd0; builder_interface1_we <= 1'd0; builder_refresher_state <= 2'd0; builder_bankmachine0_state <= 4'd0; @@ -17483,7 +17504,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) @@ -17501,7 +17522,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (iodelay_rst) @@ -17519,7 +17540,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) @@ -17537,7 +17558,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (sys_rst) @@ -17555,7 +17576,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) @@ -17573,7 +17594,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) @@ -17591,7 +17612,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) @@ -17609,7 +17630,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) @@ -17618,5 +17639,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:07. +// Auto-Generated by LiteX on 2025-02-15 19:54:41. //------------------------------------------------------------------------------ diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init index 51e4b9f..e9bf793 100644 --- a/litedram/generated/orangecrab-85-0.2/litedram_core.init +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3920000039406004 +3920000239406004 7c0004ac654ac000 -600000007d2057aa +4e8000207d2057aa +0000000000000000 +3940600400000000 +654ac00039200000 +7d2057aa7c0004ac 6000000060000000 6000000060000000 -000000004e800020 +4e80002060000000 0000000000000000 -3842acc83c4c0001 +3c4c000100000000 +7c0802a63842ada4 +f821ffc148002815 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+3a8000204bfffd54 +4bfffbc03b410041 +3bde0001995e0000 +fbc100607d1d4378 +000000004bfffa44 0000128001000000 f9e1ff78f9c1ff70 fa21ff88fa01ff80 @@ -1838,14 +1865,18 @@ ebe1fff8e8010010 696c62616e652020 004441555120676e 006e6f7263694d20 +0000004953534920 +696c62616e655b20 +5d6461757120676e +0000000000000000 4920646175715b20 005d65646f6d204f 414c462049505320 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1906,15 +1937,13 @@ ebe1fff8e8010010 000000000000207c 203a747365622020 302562202c64256d -6000000000206432 +0000000000206432 76656c2064616552 000a3a676e696c65 696c616974696e49 52445320676e697a 3025783040204d41 000a2e2e2e786c38 -000000540000002a -6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 @@ -1956,11 +1985,12 @@ ebe1fff8e8010010 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v index f5dc552..7a77cab 100644 --- a/litedram/generated/orangecrab-85-0.2/litedram_core.v +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : LFE5U-85F-8MG285C -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:11 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:49 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -104,129 +104,129 @@ LiteDRAMCore │ └─── bitslip_15* (BitSlip) │ └─── tappeddelayline_0* (TappedDelayLine) │ └─── tappeddelayline_1* (TappedDelayLine) -│ └─── [TSHX2DQA] +│ └─── [DELAYG] │ └─── [ODDRX2F] -│ └─── [TSHX2DQA] │ └─── [DELAYG] │ └─── [ODDRX2F] +│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [DELAYG] │ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [TSHX2DQA] -│ └─── [TSHX2DQA] -│ └─── [ODDRX2DQSB] │ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [DELAYG] -│ └─── [TSHX2DQA] -│ └─── [ODDRX2DQA] │ └─── [ODDRX2F] -│ └─── [TSHX2DQA] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [DELAYG] -│ └─── [TSHX2DQA] -│ └─── [ODDRX2DQA] │ └─── [ODDRX2F] -│ └─── [ODDRX2DQA] -│ └─── [ODDRX2DQA] -│ └─── [ODDRX2DQA] +│ └─── [DELAYG] │ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [ODDRX2DQA] -│ └─── [IDDRX2DQA] -│ └─── [ODDRX2DQA] │ └─── [ODDRX2F] +│ └─── [DELAYG] │ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [IDDRX2DQA] -│ └─── [TSHX2DQSA] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [IDDRX2DQA] -│ └─── [IDDRX2DQA] -│ └─── [ODDRX2DQA] -│ └─── [IDDRX2DQA] +│ └─── [ODDRX2F] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [IDDRX2DQA] │ └─── [DQSBUFM] +│ └─── [ODDRX2DQSB] +│ └─── [TSHX2DQSA] +│ └─── [ODDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2DQA] +│ └─── [ODDRX2F] │ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [DELAYG] │ └─── [ODDRX2F] +│ └─── [DELAYG] │ └─── [ODDRX2F] -│ └─── [ODDRX2DQA] -│ └─── [TSHX2DQA] │ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [TSHX2DQSA] -│ └─── [DELAYG] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] │ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] -│ └─── [TSHX2DQA] -│ └─── [ODDRX2F] -│ └─── [DELAYG] -│ └─── [DELAYG] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] -│ └─── [ODDRX2F] -│ └─── [TSHX2DQA] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] +│ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [ODDRX2F] │ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] +│ └─── [IDDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQSB] +│ └─── [DQSBUFM] +│ └─── [TSHX2DQSA] │ └─── [ODDRX2DQA] │ └─── [ODDRX2DQA] +│ └─── [DELAYG] +│ └─── [IDDRX2DQA] │ └─── [TSHX2DQA] -│ └─── [ODDRX2F] │ └─── [ODDRX2DQA] +│ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [ODDRX2F] +│ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] │ └─── [DELAYG] -│ └─── [ODDRX2F] -│ └─── [DELAYG] -│ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [IDDRX2DQA] -│ └─── [DELAYG] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] │ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] │ └─── [ODDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] │ └─── [DELAYG] -│ └─── [ODDRX2F] -│ └─── [DELAYG] -│ └─── [ODDRX2DQSB] │ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] │ └─── [IDDRX2DQA] -│ └─── [ODDRX2F] -│ └─── [ODDRX2F] -│ └─── [DELAYG] │ └─── [TSHX2DQA] -│ └─── [DQSBUFM] -│ └─── [IDDRX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [IDDRX2DQA] +│ └─── [TSHX2DQA] +│ └─── [ODDRX2DQA] │ └─── [DELAYG] +│ └─── [TSHX2DQA] │ └─── [DELAYG] +│ └─── [ODDRX2F] │ └─── [DELAYG] │ └─── [DELAYG] +│ └─── [ODDRX2F] +│ └─── [ODDRX2F] │ └─── [DELAYG] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) @@ -364,32 +364,32 @@ LiteDRAMCore │ │ └─── csrstorage_8* (CSRStorage) │ │ └─── csrstatus_1* (CSRStatus) └─── csr_interconnect (InterconnectShared) -└─── [FD1S3BX] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] -└─── [FD1S3BX] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] -└─── [FD1S3BX] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] -└─── [FD1S3BX] └─── [TRELLIS_IO] -└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [FD1S3BX] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] └─── [TRELLIS_IO] +└─── [FD1S3BX] +└─── [FD1S3BX] * : Generated name. []: BlackBox. */ @@ -864,6 +864,7 @@ wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire [2:0] interface0_cti; @@ -880,17 +881,22 @@ reg interface1_adr_next_value_ce1 = 1'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; reg [31:0] interface1_dat_w_next_value0 = 32'd0; reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_re = 1'd0; +reg interface1_re_next_value2 = 1'd0; +reg interface1_re_next_value_ce2 = 1'd0; reg interface1_we = 1'd0; -reg interface1_we_next_value2 = 1'd0; -reg interface1_we_next_value_ce2 = 1'd0; +reg interface1_we_next_value3 = 1'd0; +reg interface1_we_next_value_ce3 = 1'd0; wire [13:0] interface2_bank_bus_adr; reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; wire interface2_bank_bus_we; wire latticeecp5asyncresetsynchronizerimpl0_expr; wire latticeecp5asyncresetsynchronizerimpl0_rst1; @@ -1733,9 +1739,9 @@ reg litedramcore_csr_dfi_p0_act_n = 1'd1; wire [14:0] litedramcore_csr_dfi_p0_address; wire [2:0] litedramcore_csr_dfi_p0_bank; reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cke = 1'd0; +wire litedramcore_csr_dfi_p0_cke; reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_odt = 1'd0; +wire litedramcore_csr_dfi_p0_odt; reg litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; wire litedramcore_csr_dfi_p0_rddata_en; @@ -1749,9 +1755,9 @@ reg litedramcore_csr_dfi_p1_act_n = 1'd1; wire [14:0] litedramcore_csr_dfi_p1_address; wire [2:0] litedramcore_csr_dfi_p1_bank; reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cke = 1'd0; +wire litedramcore_csr_dfi_p1_cke; reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_odt = 1'd0; +wire litedramcore_csr_dfi_p1_odt; reg litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; wire litedramcore_csr_dfi_p1_rddata_en; @@ -2115,6 +2121,7 @@ reg multiregimpl0 = 1'd0; reg multiregimpl1 = 1'd0; reg [1:0] next_state = 2'd0; wire por_clk; +wire re; reg rhs_self0 = 1'd0; reg [14:0] rhs_self1 = 15'd0; reg rhs_self10 = 1'd0; @@ -2951,59 +2958,6 @@ assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - if (1'd0) begin - litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}}; - end - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end always @(*) begin litedramcore_master_p0_cke <= 1'd0; if (litedramcore_sel) begin @@ -3331,6 +3285,20 @@ always @(*) begin end else begin end end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end always @(*) begin litedramcore_csr_dfi_p0_rddata <= 64'd0; if (litedramcore_sel) begin @@ -3402,23 +3370,58 @@ always @(*) begin end end always @(*) begin - litedramcore_csr_dfi_p0_cke <= 1'd0; - litedramcore_csr_dfi_p0_cke <= litedramcore_cke; -end -always @(*) begin - litedramcore_csr_dfi_p1_cke <= 1'd0; - litedramcore_csr_dfi_p1_cke <= litedramcore_cke; + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + if (1'd0) begin + litedramcore_master_p0_cs_n <= {2{litedramcore_slave_p0_cs_n}}; + end + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end end always @(*) begin - litedramcore_csr_dfi_p0_odt <= 1'd0; - litedramcore_csr_dfi_p0_odt <= litedramcore_odt; + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end end always @(*) begin - litedramcore_csr_dfi_p1_odt <= 1'd0; - litedramcore_csr_dfi_p1_odt <= litedramcore_odt; + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end end +assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; +assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; +assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; +assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; +always @(*) begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end +end always @(*) begin litedramcore_csr_dfi_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin @@ -3451,20 +3454,20 @@ always @(*) begin litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end -always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end -end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end +end always @(*) begin litedramcore_csr_dfi_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin @@ -3497,14 +3500,6 @@ always @(*) begin litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end -always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end -end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); @@ -3612,22 +3607,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_cmd_valid <= 1'd0; case (litedramcore_refresher_state) @@ -3694,6 +3673,22 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; @@ -3827,66 +3822,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_source_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_source_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine0_state) @@ -4207,6 +4142,66 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; @@ -4340,40 +4335,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_source_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_source_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (litedramcore_bankmachine1_state) @@ -4396,28 +4357,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine1_cmd_valid <= 1'd0; case (litedramcore_bankmachine1_state) @@ -4477,6 +4416,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine1_state) @@ -4720,6 +4681,40 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; @@ -4853,28 +4848,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine2_state) @@ -5233,6 +5206,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; @@ -5366,37 +5361,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_source_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine3_state) @@ -5746,6 +5710,37 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; @@ -5879,66 +5874,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_source_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_source_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine4_state) @@ -6187,7 +6122,69 @@ always @(*) begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -6198,21 +6195,22 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6223,12 +6221,9 @@ always @(*) begin endcase end always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6247,8 +6242,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6392,40 +6387,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_source_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_source_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (litedramcore_bankmachine5_state) @@ -6772,6 +6733,40 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; @@ -6905,28 +6900,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine6_state) @@ -7042,28 +7015,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine6_state) @@ -7248,6 +7199,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; case (litedramcore_bankmachine6_state) @@ -7285,6 +7258,28 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; @@ -7418,37 +7413,6 @@ always @(*) begin end endcase end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_source_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine7_state) @@ -7798,6 +7762,37 @@ always @(*) begin end endcase end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); @@ -8048,19 +8043,15 @@ always @(*) begin endcase end always @(*) begin - litedramcore_steerer0 <= 2'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_steerer0 <= 1'd0; if (1'd0) begin - litedramcore_steerer0 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer0 <= 1'd1; + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin - litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -8086,29 +8077,23 @@ always @(*) begin end 4'd14: begin end - 4'd15: begin - end - default: begin - litedramcore_steerer0 <= 1'd0; - if (1'd1) begin - litedramcore_steerer0 <= 2'd2; - end + 4'd15: begin + end + default: begin if (1'd0) begin - litedramcore_steerer0 <= 1'd1; + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase end always @(*) begin - litedramcore_steerer1 <= 2'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_steerer1 <= 1'd0; - if (1'd1) begin - litedramcore_steerer1 <= 2'd2; - end if (1'd0) begin - litedramcore_steerer1 <= 1'd1; + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end 2'd2: begin @@ -8140,24 +8125,17 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_steerer1 <= 1'd0; if (1'd0) begin - litedramcore_steerer1 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer1 <= 1'd1; + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end endcase end always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end 2'd2: begin end @@ -8188,10 +8166,7 @@ always @(*) begin 4'd15: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_choose_req_want_reads <= 1'd1; end endcase end @@ -8234,13 +8209,10 @@ always @(*) begin endcase end always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -8271,15 +8243,11 @@ always @(*) begin 4'd15: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase end always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_en0 <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin end @@ -8312,15 +8280,19 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; + litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -8351,13 +8323,19 @@ always @(*) begin 4'd15: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase end always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_en1 <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -8388,21 +8366,23 @@ always @(*) begin 4'd15: begin end default: begin - litedramcore_en0 <= 1'd1; end endcase end always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_steerer0 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin + litedramcore_steerer0 <= 1'd0; if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + litedramcore_steerer0 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer0 <= 1'd1; end end 2'd2: begin + litedramcore_steerer0 <= 2'd3; end 2'd3: begin end @@ -8431,19 +8411,27 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_steerer0 <= 1'd0; + if (1'd1) begin + litedramcore_steerer0 <= 2'd2; + end if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + litedramcore_steerer0 <= 1'd1; end end endcase end always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_steerer1 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_steerer1 <= 1'd0; + if (1'd1) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer1 <= 1'd1; + end end 2'd2: begin end @@ -8474,6 +8462,13 @@ always @(*) begin 4'd15: begin end default: begin + litedramcore_steerer1 <= 1'd0; + if (1'd0) begin + litedramcore_steerer1 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer1 <= 1'd1; + end end endcase end @@ -8569,138 +8564,168 @@ always @(*) begin endcase end always @(*) begin - interface0_ack <= 1'd0; + interface1_adr_next_value1 <= 14'd0; case (state) 1'd1: begin + interface1_adr_next_value1 <= 1'd0; end 2'd2: begin - interface0_ack <= 1'd1; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value1 <= interface0_adr; + end end endcase end always @(*) begin - interface0_dat_r <= 32'd0; + interface1_adr_next_value_ce1 <= 1'd0; case (state) 1'd1: begin + interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - interface0_dat_r <= interface1_dat_r; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - interface1_dat_w_next_value0 <= 32'd0; + interface1_re_next_value2 <= 1'd0; case (state) 1'd1: begin + interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin - interface1_dat_w_next_value0 <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0)); + end end endcase end always @(*) begin - interface1_dat_w_next_value_ce0 <= 1'd0; + interface1_re_next_value_ce2 <= 1'd0; case (state) 1'd1: begin + interface1_re_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - interface1_dat_w_next_value_ce0 <= 1'd1; + if ((interface0_cyc & interface0_stb)) begin + interface1_re_next_value_ce2 <= 1'd1; + end end endcase end always @(*) begin - interface1_adr_next_value1 <= 14'd0; + interface1_we_next_value3 <= 1'd0; case (state) 1'd1: begin - interface1_adr_next_value1 <= 1'd0; + interface1_we_next_value3 <= 1'd0; end 2'd2: begin end default: begin if ((interface0_cyc & interface0_stb)) begin - interface1_adr_next_value1 <= interface0_adr[29:0]; + interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0)); end end endcase end always @(*) begin - interface1_adr_next_value_ce1 <= 1'd0; + interface1_we_next_value_ce3 <= 1'd0; case (state) 1'd1: begin - interface1_adr_next_value_ce1 <= 1'd1; + interface1_we_next_value_ce3 <= 1'd1; end 2'd2: begin end default: begin if ((interface0_cyc & interface0_stb)) begin - interface1_adr_next_value_ce1 <= 1'd1; + interface1_we_next_value_ce3 <= 1'd1; end end endcase end always @(*) begin - interface1_we_next_value2 <= 1'd0; + interface0_dat_r <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + interface0_dat_r <= interface1_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + interface0_ack <= 1'd0; case (state) 1'd1: begin - interface1_we_next_value2 <= 1'd0; end 2'd2: begin + interface0_ack <= 1'd1; end default: begin - if ((interface0_cyc & interface0_stb)) begin - interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0)); - end end endcase end always @(*) begin - interface1_we_next_value_ce2 <= 1'd0; + interface1_dat_w_next_value0 <= 32'd0; + case (state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + interface1_dat_w_next_value0 <= interface0_dat_w; + end + endcase +end +always @(*) begin + interface1_dat_w_next_value_ce0 <= 1'd0; case (state) 1'd1: begin - interface1_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin - if ((interface0_cyc & interface0_stb)) begin - interface1_we_next_value_ce2 <= 1'd1; - end + interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; + csrbank0_init_done0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; + csrbank0_init_done0_we <= interface0_bank_bus_re; end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; + csrbank0_init_done0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + csrbank0_init_done0_re <= interface0_bank_bus_we; end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; + csrbank0_init_error0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + csrbank0_init_error0_re <= interface0_bank_bus_we; end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; + csrbank0_init_error0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + csrbank0_init_error0_we <= interface0_bank_bus_re; end end assign csrbank0_init_done0_w = init_done_storage; @@ -8708,54 +8733,54 @@ assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; + csrbank1_dly_sel0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + csrbank1_dly_sel0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; + csrbank1_dly_sel0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; + csrbank1_dly_sel0_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_rst_we <= 1'd0; + ddrphy_rdly_dq_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; end end always @(*) begin - ddrphy_rdly_dq_rst_re <= 1'd0; + ddrphy_rdly_dq_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + ddrphy_rdly_dq_rst_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_inc_we <= 1'd0; + ddrphy_rdly_dq_inc_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; end end always @(*) begin - ddrphy_rdly_dq_inc_re <= 1'd0; + ddrphy_rdly_dq_inc_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + ddrphy_rdly_dq_inc_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; end end always @(*) begin - ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + ddrphy_rdly_dq_bitslip_rst_we <= interface1_bank_bus_re; end end assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; @@ -8768,20 +8793,20 @@ end always @(*) begin ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + ddrphy_rdly_dq_bitslip_we <= interface1_bank_bus_re; end end assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_burstdet_clr_re <= 1'd0; + ddrphy_burstdet_clr_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - ddrphy_burstdet_clr_re <= interface1_bank_bus_we; + ddrphy_burstdet_clr_we <= interface1_bank_bus_re; end end always @(*) begin - ddrphy_burstdet_clr_we <= 1'd0; + ddrphy_burstdet_clr_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we); + ddrphy_burstdet_clr_re <= interface1_bank_bus_we; end end assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; @@ -8794,11 +8819,11 @@ end always @(*) begin csrbank1_burstdet_seen_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); + csrbank1_burstdet_seen_we <= interface1_bank_bus_re; end end -assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0]; -assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0]; +assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage; +assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status; assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; @@ -8811,46 +8836,46 @@ end always @(*) begin csrbank2_dfii_control0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_control0_we <= interface2_bank_bus_re; end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; + csrbank2_dfii_pi0_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; + csrbank2_dfii_pi0_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_command0_we <= interface2_bank_bus_re; end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; + litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + litedramcore_phaseinjector0_command_issue_we <= interface2_bank_bus_re; end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; + litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; + csrbank2_dfii_pi0_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_address0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; + csrbank2_dfii_pi0_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; @@ -8863,14 +8888,14 @@ end always @(*) begin csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_baddress0_we <= interface2_bank_bus_re; end end -assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_dfii_pi0_wrdata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_wrdata1_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8879,37 +8904,37 @@ always @(*) begin csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_wrdata0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi0_rddata1_we <= 1'd0; + csrbank2_dfii_pi0_rddata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi0_rddata1_re <= 1'd0; + csrbank2_dfii_pi0_rddata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi0_rddata1_we <= interface2_bank_bus_re; end end -assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_dfii_pi0_rddata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi0_rddata0_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8920,22 +8945,22 @@ always @(*) begin end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[7:0]; always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; + csrbank2_dfii_pi1_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_command0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; + csrbank2_dfii_pi1_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + litedramcore_phaseinjector1_command_issue_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8954,14 +8979,14 @@ end always @(*) begin csrbank2_dfii_pi1_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_address0_we <= interface2_bank_bus_re; end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_baddress0_we <= interface2_bank_bus_re; end end always @(*) begin @@ -8970,37 +8995,37 @@ always @(*) begin csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata1_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_wrdata0_we <= interface2_bank_bus_re; end end -assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_dfii_pi1_rddata1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_rddata1_we <= interface2_bank_bus_re; end end always @(*) begin @@ -9009,24 +9034,24 @@ always @(*) begin csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; end end -assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w; always @(*) begin - csrbank2_dfii_pi1_rddata0_re <= 1'd0; + csrbank2_dfii_pi1_rddata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + csrbank2_dfii_pi1_rddata0_we <= interface2_bank_bus_re; end end always @(*) begin - csrbank2_dfii_pi1_rddata0_we <= 1'd0; + csrbank2_dfii_pi1_rddata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; assign litedramcore_odt = litedramcore_storage[2]; assign litedramcore_reset_n = litedramcore_storage[3]; -assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; +assign csrbank2_dfii_control0_w = litedramcore_storage; assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; @@ -9035,9 +9060,9 @@ assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_c assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; assign litedramcore_phaseinjector0_csrfield_cs_top = litedramcore_phaseinjector0_command_storage[6]; assign litedramcore_phaseinjector0_csrfield_cs_bottom = litedramcore_phaseinjector0_command_storage[7]; -assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[7:0]; -assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; -assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage; +assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage; +assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage; assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[63:32]; assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_rddata_status[63:32]; @@ -9051,21 +9076,25 @@ assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_c assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; assign litedramcore_phaseinjector1_csrfield_cs_top = litedramcore_phaseinjector1_command_storage[6]; assign litedramcore_phaseinjector1_csrfield_cs_bottom = litedramcore_phaseinjector1_command_storage[7]; -assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[7:0]; -assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[14:0]; -assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage; +assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage; +assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage; assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[63:32]; assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_rddata_status[63:32]; assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_rddata_status[31:0]; assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata0_we; assign adr = interface1_adr; +assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface2_bank_bus_we = we; @@ -9791,16 +9820,16 @@ always @(*) begin self0 <= 3'd0; case (litedramcore_steerer0) 1'd0: begin - self0 <= litedramcore_nop_ba[2:0]; + self0 <= litedramcore_nop_ba; end 1'd1: begin - self0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self0 <= litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + self0 <= litedramcore_choose_req_cmd_payload_ba; end default: begin - self0 <= litedramcore_cmd_payload_ba[2:0]; + self0 <= litedramcore_cmd_payload_ba; end endcase end @@ -9910,16 +9939,16 @@ always @(*) begin self7 <= 3'd0; case (litedramcore_steerer1) 1'd0: begin - self7 <= litedramcore_nop_ba[2:0]; + self7 <= litedramcore_nop_ba; end 1'd1: begin - self7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self7 <= litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + self7 <= litedramcore_choose_req_cmd_payload_ba; end default: begin - self7 <= litedramcore_cmd_payload_ba[2:0]; + self7 <= litedramcore_cmd_payload_ba; end endcase end @@ -11727,8 +11756,11 @@ always @(posedge sys_clk) begin if (interface1_adr_next_value_ce1) begin interface1_adr <= interface1_adr_next_value1; end - if (interface1_we_next_value_ce2) begin - interface1_we <= interface1_we_next_value2; + if (interface1_re_next_value_ce2) begin + interface1_re <= interface1_re_next_value2; + end + if (interface1_we_next_value_ce3) begin + interface1_we <= interface1_we_next_value3; end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin @@ -11776,7 +11808,7 @@ always @(posedge sys_clk) begin endcase end if (csrbank1_dly_sel0_re) begin - ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + ddrphy_dly_sel_storage <= csrbank1_dly_sel0_r; end ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re; @@ -11837,19 +11869,19 @@ always @(posedge sys_clk) begin endcase end if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + litedramcore_storage <= csrbank2_dfii_control0_r; end litedramcore_re <= csrbank2_dfii_control0_re; if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[7:0] <= csrbank2_dfii_pi0_command0_r; + litedramcore_phaseinjector0_command_storage <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + litedramcore_phaseinjector0_address_storage <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + litedramcore_phaseinjector0_baddress_storage <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; if (csrbank2_dfii_pi0_wrdata1_re) begin @@ -11861,15 +11893,15 @@ always @(posedge sys_clk) begin litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[7:0] <= csrbank2_dfii_pi1_command0_r; + litedramcore_phaseinjector1_command_storage <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + litedramcore_phaseinjector1_address_storage <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + litedramcore_phaseinjector1_baddress_storage <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; if (csrbank2_dfii_pi1_wrdata1_re) begin @@ -12151,6 +12183,7 @@ always @(posedge sys_clk) begin init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; + interface1_re <= 1'd0; interface1_we <= 1'd0; litedramcore_refresher_state <= 2'd0; litedramcore_bankmachine0_state <= 3'd0; @@ -14965,5 +14998,5 @@ TRELLIS_IO #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:11. +// Auto-Generated by LiteX on 2025-02-15 19:54:49. //------------------------------------------------------------------------------ diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index 7cf9fda..7f8070d 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3920000039406004 +3920000239406004 7c0004ac654ac000 -600000007d2057aa +4e8000207d2057aa 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+4bfffd5c99090020 +4bfffd543b000008 +3b4100413a800020 +995e00004bfffbc0 +7d1d43783bde0001 +4bfffa44fbc10060 0100000000000000 f9c1ff7000001280 fa01ff80f9e1ff78 @@ -1517,14 +1544,18 @@ e8010010ebc1fff0 696c62616e652020 004441555120676e 006e6f7263694d20 +0000004953534920 +696c62616e655b20 +5d6461757120676e +0000000000000000 4920646175715b20 005d65646f6d204f 414c462049505320 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1619,7 +1650,7 @@ e8010010ebc1fff0 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index 4b6cea9..f54a078 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:12 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:53 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -346,6 +346,7 @@ wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire [2:0] interface0_cti; @@ -362,14 +363,18 @@ reg interface1_adr_next_value_ce1 = 1'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; reg [31:0] interface1_dat_w_next_value0 = 32'd0; reg interface1_dat_w_next_value_ce0 = 1'd0; +reg interface1_re = 1'd0; +reg interface1_re_next_value2 = 1'd0; +reg interface1_re_next_value_ce2 = 1'd0; reg interface1_we = 1'd0; -reg interface1_we_next_value2 = 1'd0; -reg interface1_we_next_value_ce2 = 1'd0; +reg interface1_we_next_value3 = 1'd0; +reg interface1_we_next_value_ce3 = 1'd0; reg locked0 = 1'd0; reg locked1 = 1'd0; reg locked2 = 1'd0; @@ -393,6 +398,7 @@ reg new_master_wdata_ready0 = 1'd0; reg new_master_wdata_ready1 = 1'd0; reg [1:0] next_state = 2'd0; wire por_clk; +wire re; reg [1:0] refresher_next_state = 2'd0; reg [1:0] refresher_state = 2'd0; reg rhs_self0 = 1'd0; @@ -1646,9 +1652,9 @@ reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1; wire [13:0] soc_litedramcore_csr_dfi_p0_address; wire [2:0] soc_litedramcore_csr_dfi_p0_bank; reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_cke = 1'd0; +wire soc_litedramcore_csr_dfi_p0_cke; reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_odt = 1'd0; +wire soc_litedramcore_csr_dfi_p0_odt; reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0; wire soc_litedramcore_csr_dfi_p0_rddata_en; @@ -1662,9 +1668,9 @@ reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1; wire [13:0] soc_litedramcore_csr_dfi_p1_address; wire [2:0] soc_litedramcore_csr_dfi_p1_bank; reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_cke = 1'd0; +wire soc_litedramcore_csr_dfi_p1_cke; reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_odt = 1'd0; +wire soc_litedramcore_csr_dfi_p1_odt; reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0; wire soc_litedramcore_csr_dfi_p1_rddata_en; @@ -1678,9 +1684,9 @@ reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1; wire [13:0] soc_litedramcore_csr_dfi_p2_address; wire [2:0] soc_litedramcore_csr_dfi_p2_bank; reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_cke = 1'd0; +wire soc_litedramcore_csr_dfi_p2_cke; reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_odt = 1'd0; +wire soc_litedramcore_csr_dfi_p2_odt; reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0; wire soc_litedramcore_csr_dfi_p2_rddata_en; @@ -1694,9 +1700,9 @@ reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1; wire [13:0] soc_litedramcore_csr_dfi_p3_address; wire [2:0] soc_litedramcore_csr_dfi_p3_bank; reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_cke = 1'd0; +wire soc_litedramcore_csr_dfi_p3_cke; reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_odt = 1'd0; +wire soc_litedramcore_csr_dfi_p3_odt; reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0; wire soc_litedramcore_csr_dfi_p3_rddata_en; @@ -2267,36 +2273,36 @@ always @(*) begin soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel0_activate_row <= 14'd0; + soc_ddrphy_bankmodel0_activate <= 1'd0; case (soc_ddrphy_activates0) 1'd1: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end always @(*) begin - soc_ddrphy_bankmodel0_activate <= 1'd0; + soc_ddrphy_bankmodel0_activate_row <= 14'd0; case (soc_ddrphy_activates0) 1'd1: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2377,36 +2383,36 @@ always @(*) begin soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel0_read <= 1'd0; + soc_ddrphy_bankmodel0_read_col <= 10'd0; case (soc_ddrphy_reads0) 1'd1: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0); + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel0_read_col <= 10'd0; + soc_ddrphy_bankmodel0_read <= 1'd0; case (soc_ddrphy_reads0) 1'd1: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0); end 2'd2: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0); end 3'd4: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0); end 4'd8: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0); end endcase end @@ -2483,36 +2489,36 @@ always @(*) begin soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write1 <= 1'd0; + soc_ddrphy_bank_write_col1 <= 10'd0; case (soc_ddrphy_writes1) 1'd1: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bank_write_col1 <= 10'd0; + soc_ddrphy_bank_write1 <= 1'd0; case (soc_ddrphy_writes1) 1'd1: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end @@ -2528,36 +2534,36 @@ always @(*) begin soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel1_read_col <= 10'd0; + soc_ddrphy_bankmodel1_read <= 1'd0; case (soc_ddrphy_reads1) 1'd1: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1); end 2'd2: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1); end 3'd4: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1); end 4'd8: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1); end endcase end always @(*) begin - soc_ddrphy_bankmodel1_read <= 1'd0; + soc_ddrphy_bankmodel1_read_col <= 10'd0; case (soc_ddrphy_reads1) 1'd1: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1); + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2569,36 +2575,36 @@ always @(*) begin soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel2_activate <= 1'd0; + soc_ddrphy_bankmodel2_activate_row <= 14'd0; case (soc_ddrphy_activates2) 1'd1: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel2_activate_row <= 14'd0; + soc_ddrphy_bankmodel2_activate <= 1'd0; case (soc_ddrphy_activates2) 1'd1: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end @@ -2634,36 +2640,36 @@ always @(*) begin soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write_col2 <= 10'd0; + soc_ddrphy_bank_write2 <= 1'd0; case (soc_ddrphy_writes2) 1'd1: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2); end 2'd2: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2); end 3'd4: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2); end 4'd8: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2); end endcase end always @(*) begin - soc_ddrphy_bank_write2 <= 1'd0; + soc_ddrphy_bank_write_col2 <= 10'd0; case (soc_ddrphy_writes2) 1'd1: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2); + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -2720,36 +2726,36 @@ always @(*) begin soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel3_activate_row <= 14'd0; + soc_ddrphy_bankmodel3_activate <= 1'd0; case (soc_ddrphy_activates3) 1'd1: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3); end 2'd2: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3); end 3'd4: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3); end 4'd8: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3); end endcase end always @(*) begin - soc_ddrphy_bankmodel3_activate <= 1'd0; + soc_ddrphy_bankmodel3_activate_row <= 14'd0; case (soc_ddrphy_activates3) 1'd1: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3); + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end @@ -3087,36 +3093,36 @@ always @(*) begin soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write5 <= 1'd0; + soc_ddrphy_bank_write_col5 <= 10'd0; case (soc_ddrphy_writes5) 1'd1: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bank_write_col5 <= 10'd0; + soc_ddrphy_bank_write5 <= 1'd0; case (soc_ddrphy_writes5) 1'd1: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end @@ -3132,36 +3138,36 @@ always @(*) begin soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel5_read <= 1'd0; + soc_ddrphy_bankmodel5_read_col <= 10'd0; case (soc_ddrphy_reads5) 1'd1: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5); + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel5_read_col <= 10'd0; + soc_ddrphy_bankmodel5_read <= 1'd0; case (soc_ddrphy_reads5) 1'd1: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5); end 2'd2: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5); end 3'd4: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5); end 4'd8: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5); end endcase end @@ -3238,36 +3244,36 @@ always @(*) begin soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write; end always @(*) begin - soc_ddrphy_bank_write_col6 <= 10'd0; + soc_ddrphy_bank_write6 <= 1'd0; case (soc_ddrphy_writes6) 1'd1: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - soc_ddrphy_bank_write6 <= 1'd0; + soc_ddrphy_bank_write_col6 <= 10'd0; case (soc_ddrphy_writes6) 1'd1: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address; end endcase end @@ -3283,36 +3289,36 @@ always @(*) begin soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read; end always @(*) begin - soc_ddrphy_bankmodel6_read_col <= 10'd0; + soc_ddrphy_bankmodel6_read <= 1'd0; case (soc_ddrphy_reads6) 1'd1: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6); end 2'd2: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6); end 3'd4: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6); end 4'd8: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6); end endcase end always @(*) begin - soc_ddrphy_bankmodel6_read <= 1'd0; + soc_ddrphy_bankmodel6_read_col <= 10'd0; case (soc_ddrphy_reads6) 1'd1: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6); + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address; end endcase end @@ -3324,36 +3330,36 @@ always @(*) begin soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate; end always @(*) begin - soc_ddrphy_bankmodel7_activate <= 1'd0; + soc_ddrphy_bankmodel7_activate_row <= 14'd0; case (soc_ddrphy_activates7) 1'd1: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address; end 2'd2: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address; end 3'd4: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address; end 4'd8: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7); + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address; end endcase end always @(*) begin - soc_ddrphy_bankmodel7_activate_row <= 14'd0; + soc_ddrphy_bankmodel7_activate <= 1'd0; case (soc_ddrphy_activates7) 1'd1: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address; + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7); end 2'd2: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address; + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7); end 3'd4: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address; + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7); end 4'd8: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address; + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7); end endcase end @@ -3478,15 +3484,15 @@ assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rd assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; always @(*) begin - soc_ddrphy_dfiphasemodel0_precharge <= 1'd0; + soc_ddrphy_dfiphasemodel0_activate <= 1'd0; if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin - soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n); + soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel0_activate <= 1'd0; + soc_ddrphy_dfiphasemodel0_precharge <= 1'd0; if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin - soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n; + soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n); end end always @(*) begin @@ -3514,15 +3520,15 @@ always @(*) begin end end always @(*) begin - soc_ddrphy_dfiphasemodel1_write <= 1'd0; + soc_ddrphy_dfiphasemodel1_read <= 1'd0; if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin - soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n); + soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel1_read <= 1'd0; + soc_ddrphy_dfiphasemodel1_write <= 1'd0; if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin - soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n; + soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n); end end always @(*) begin @@ -3538,27 +3544,27 @@ always @(*) begin end end always @(*) begin - soc_ddrphy_dfiphasemodel2_read <= 1'd0; + soc_ddrphy_dfiphasemodel2_write <= 1'd0; if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin - soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n; + soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel2_write <= 1'd0; + soc_ddrphy_dfiphasemodel2_read <= 1'd0; if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin - soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n); + soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n; end end always @(*) begin - soc_ddrphy_dfiphasemodel3_activate <= 1'd0; + soc_ddrphy_dfiphasemodel3_precharge <= 1'd0; if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin - soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n; + soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n); end end always @(*) begin - soc_ddrphy_dfiphasemodel3_precharge <= 1'd0; + soc_ddrphy_dfiphasemodel3_activate <= 1'd0; if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin - soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n); + soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n; end end always @(*) begin @@ -3615,14 +3621,6 @@ always @(*) begin end assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; -always @(*) begin - soc_ddrphy_bankmodel1_read_data <= 128'd0; - if (soc_ddrphy_bankmodel1_active) begin - if (soc_ddrphy_bankmodel1_read) begin - soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r; - end - end -end always @(*) begin soc_ddrphy_bankmodel1_write_port_adr <= 21'd0; if (soc_ddrphy_bankmodel1_active) begin @@ -3653,6 +3651,14 @@ always @(*) begin end end end +always @(*) begin + soc_ddrphy_bankmodel1_read_data <= 128'd0; + if (soc_ddrphy_bankmodel1_active) begin + if (soc_ddrphy_bankmodel1_read) begin + soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r; + end + end +end assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; always @(*) begin @@ -3695,12 +3701,6 @@ always @(*) begin end assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; -always @(*) begin - soc_ddrphy_bankmodel3_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel3_active) begin - soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr; - end -end always @(*) begin soc_ddrphy_bankmodel3_write_port_we <= 16'd0; if (soc_ddrphy_bankmodel3_active) begin @@ -3733,24 +3733,14 @@ always @(*) begin end end end -assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; -assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; -always @(*) begin - soc_ddrphy_bankmodel4_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel4_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); - end else begin - soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write; - end - end -end always @(*) begin - soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel4_active) begin - soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data; + soc_ddrphy_bankmodel3_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr; end end +assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; +assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; always @(*) begin soc_ddrphy_bankmodel4_read_port_adr <= 21'd0; if (soc_ddrphy_bankmodel4_active) begin @@ -3773,16 +3763,24 @@ always @(*) begin soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr; end end -assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; -assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin - soc_ddrphy_bankmodel5_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel5_active) begin - if (soc_ddrphy_bankmodel5_read) begin - soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr; + soc_ddrphy_bankmodel4_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel4_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); + end else begin + soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write; end end end +always @(*) begin + soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data; + end +end +assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; +assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin soc_ddrphy_bankmodel5_read_data <= 128'd0; if (soc_ddrphy_bankmodel5_active) begin @@ -3813,6 +3811,14 @@ always @(*) begin soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data; end end +always @(*) begin + soc_ddrphy_bankmodel5_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel5_active) begin + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr; + end + end +end assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; always @(*) begin @@ -4921,42 +4927,26 @@ always @(*) begin end else begin end end -always @(*) begin - soc_litedramcore_csr_dfi_p0_cke <= 1'd0; - soc_litedramcore_csr_dfi_p0_cke <= soc_litedramcore_cke; -end -always @(*) begin - soc_litedramcore_csr_dfi_p1_cke <= 1'd0; - soc_litedramcore_csr_dfi_p1_cke <= soc_litedramcore_cke; -end -always @(*) begin - soc_litedramcore_csr_dfi_p2_cke <= 1'd0; - soc_litedramcore_csr_dfi_p2_cke <= soc_litedramcore_cke; -end -always @(*) begin - soc_litedramcore_csr_dfi_p3_cke <= 1'd0; - soc_litedramcore_csr_dfi_p3_cke <= soc_litedramcore_cke; -end -always @(*) begin - soc_litedramcore_csr_dfi_p0_odt <= 1'd0; - soc_litedramcore_csr_dfi_p0_odt <= soc_litedramcore_odt; -end -always @(*) begin - soc_litedramcore_csr_dfi_p1_odt <= 1'd0; - soc_litedramcore_csr_dfi_p1_odt <= soc_litedramcore_odt; -end -always @(*) begin - soc_litedramcore_csr_dfi_p2_odt <= 1'd0; - soc_litedramcore_csr_dfi_p2_odt <= soc_litedramcore_odt; -end -always @(*) begin - soc_litedramcore_csr_dfi_p3_odt <= 1'd0; - soc_litedramcore_csr_dfi_p3_odt <= soc_litedramcore_odt; -end +assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p2_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p3_cke = soc_litedramcore_cke; +assign soc_litedramcore_csr_dfi_p0_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p1_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p2_odt = soc_litedramcore_odt; +assign soc_litedramcore_csr_dfi_p3_odt = soc_litedramcore_odt; assign soc_litedramcore_csr_dfi_p0_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n; +always @(*) begin + soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end +end always @(*) begin soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector0_command_issue_re) begin @@ -4989,20 +4979,20 @@ always @(*) begin soc_litedramcore_csr_dfi_p0_we_n <= 1'd1; end end -always @(*) begin - soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end -end assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage; assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; assign soc_litedramcore_csr_dfi_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_wren); assign soc_litedramcore_csr_dfi_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_csrfield_rden); assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end +end always @(*) begin soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector1_command_issue_re) begin @@ -5035,20 +5025,20 @@ always @(*) begin soc_litedramcore_csr_dfi_p1_we_n <= 1'd1; end end -always @(*) begin - soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end -end assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage; assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; assign soc_litedramcore_csr_dfi_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_wren); assign soc_litedramcore_csr_dfi_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_csrfield_rden); assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +always @(*) begin + soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end +end always @(*) begin soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector2_command_issue_re) begin @@ -5081,20 +5071,20 @@ always @(*) begin soc_litedramcore_csr_dfi_p2_we_n <= 1'd1; end end -always @(*) begin - soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end -end assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage; assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; assign soc_litedramcore_csr_dfi_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_wren); assign soc_litedramcore_csr_dfi_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_csrfield_rden); assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +always @(*) begin + soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end +end always @(*) begin soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1; if (soc_litedramcore_phaseinjector3_command_issue_re) begin @@ -5127,14 +5117,6 @@ always @(*) begin soc_litedramcore_csr_dfi_p3_we_n <= 1'd1; end end -always @(*) begin - soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end -end assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage; assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; assign soc_litedramcore_csr_dfi_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_csrfield_wren); @@ -5463,32 +5445,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (bankmachine0_state) @@ -5855,21 +5811,59 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; + soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end end 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5880,18 +5874,6 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_source_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end @@ -6034,41 +6016,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_source_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (bankmachine1_state) @@ -6466,6 +6413,41 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid; assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready; assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we; @@ -6605,74 +6587,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_source_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_source_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (bankmachine2_state) @@ -7037,6 +6951,74 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid; assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready; assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we; @@ -7177,7 +7159,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7186,6 +7168,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7196,37 +7181,22 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_source_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_source_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine3_row_open <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_open <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7307,32 +7277,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (bankmachine3_state) @@ -7608,6 +7552,44 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign soc_litedramcore_bankmachine4_sink_valid = soc_litedramcore_bankmachine4_req_valid; assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_sink_ready; assign soc_litedramcore_bankmachine4_sink_payload_we = soc_litedramcore_bankmachine4_req_we; @@ -7747,32 +7729,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (bankmachine4_state) - 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) @@ -8179,6 +8135,32 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine4_row_close <= 1'd0; + case (bankmachine4_state) + 1'd1: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid; assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready; assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we; @@ -8318,41 +8300,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_source_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (bankmachine5_state) @@ -8750,6 +8697,41 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid; assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready; assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we; @@ -8822,135 +8804,67 @@ assign soc_litedramcore_bankmachine6_pipe_valid_sink_first = soc_litedramcore_ba assign soc_litedramcore_bankmachine6_pipe_valid_sink_last = soc_litedramcore_bankmachine6_sink_sink_last; assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine6_sink_sink_payload_we; assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine6_sink_sink_payload_addr; -assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid; -assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready; -assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first; -assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last; -assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we; -assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr; -always @(*) begin - bankmachine6_next_state <= 4'd0; - bankmachine6_next_state <= bankmachine6_state; - case (bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - bankmachine6_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - bankmachine6_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine6_source_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - bankmachine6_next_state <= 2'd2; - end - end else begin - bankmachine6_next_state <= 1'd1; - end - end else begin - bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end +assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready; +assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first; +assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last; +assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr; always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + bankmachine6_next_state <= 4'd0; + bankmachine6_next_state <= bankmachine6_state; case (bankmachine6_state) 1'd1: begin if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (soc_litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state <= 3'd5; + end end end 2'd2: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + bankmachine6_next_state <= 3'd5; + end end 2'd3: begin if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (soc_litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state <= 3'd7; + end end end 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin + if ((~soc_litedramcore_bankmachine6_refresh_req)) begin + bankmachine6_next_state <= 1'd0; + end end 3'd5: begin + bankmachine6_next_state <= 3'd6; end 3'd6: begin + bankmachine6_next_state <= 2'd3; end 3'd7: begin + bankmachine6_next_state <= 4'd8; end 4'd8: begin + bankmachine6_next_state <= 1'd0; end default: begin if (soc_litedramcore_bankmachine6_refresh_req) begin + bankmachine6_next_state <= 3'd4; end else begin if (soc_litedramcore_bankmachine6_source_source_valid) begin if (soc_litedramcore_bankmachine6_row_opened) begin if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_source_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin + bankmachine6_next_state <= 2'd2; end end else begin + bankmachine6_next_state <= 1'd1; end end else begin + bankmachine6_next_state <= 2'd3; end end end @@ -9321,6 +9235,74 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign soc_litedramcore_bankmachine7_sink_valid = soc_litedramcore_bankmachine7_req_valid; assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_sink_ready; assign soc_litedramcore_bankmachine7_sink_payload_we = soc_litedramcore_bankmachine7_req_we; @@ -9461,7 +9443,7 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9470,6 +9452,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9480,37 +9465,22 @@ always @(*) begin 4'd8: begin end default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_source_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + soc_litedramcore_bankmachine7_row_open <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9591,32 +9561,6 @@ always @(*) begin end endcase end -always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (bankmachine7_state) @@ -9892,6 +9836,44 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready); @@ -10141,43 +10123,10 @@ always @(*) begin case (multiplexer_state) 1'd1: begin if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); - end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); - end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; - end - end - endcase -end -always @(*) begin - soc_litedramcore_en1 <= 1'd0; - case (multiplexer_state) - 1'd1: begin - soc_litedramcore_en1 <= 1'd1; + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10198,20 +10147,19 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end end endcase end always @(*) begin - soc_litedramcore_steerer3 <= 2'd0; + soc_litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - soc_litedramcore_steerer3 <= 1'd0; - if (1'd1) begin - soc_litedramcore_steerer3 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer3 <= 1'd1; - end + soc_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10232,13 +10180,6 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_steerer3 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer3 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer3 <= 1'd1; - end end endcase end @@ -10402,9 +10343,16 @@ always @(*) begin endcase end always @(*) begin - soc_litedramcore_en0 <= 1'd0; + soc_litedramcore_steerer3 <= 2'd0; case (multiplexer_state) 1'd1: begin + soc_litedramcore_steerer3 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer3 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer3 <= 1'd1; + end end 2'd2: begin end @@ -10425,17 +10373,22 @@ always @(*) begin 4'd10: begin end default: begin - soc_litedramcore_en0 <= 1'd1; + soc_litedramcore_steerer3 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer3 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer3 <= 1'd1; + end end endcase end always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; + soc_litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10454,6 +10407,7 @@ always @(*) begin 4'd10: begin end default: begin + soc_litedramcore_en0 <= 1'd1; end endcase end @@ -10520,6 +10474,34 @@ always @(*) begin end endcase end +always @(*) begin + soc_litedramcore_cmd_ready <= 1'd0; + case (multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end always @(*) begin soc_litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) @@ -10592,24 +10574,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & assign soc_user_port_wdata_ready = new_master_wdata_ready1; assign soc_user_port_rdata_valid = new_master_rdata_valid8; always @(*) begin - soc_litedramcore_interface_wdata_we <= 16'd0; + soc_litedramcore_interface_wdata <= 128'd0; case ({new_master_wdata_ready1}) 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; + soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; end default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; + soc_litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin - soc_litedramcore_interface_wdata <= 128'd0; + soc_litedramcore_interface_wdata_we <= 16'd0; case ({new_master_wdata_ready1}) 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; + soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; end default: begin - soc_litedramcore_interface_wdata <= 1'd0; + soc_litedramcore_interface_wdata_we <= 1'd0; end endcase end @@ -10639,6 +10621,36 @@ always @(*) begin end endcase end +always @(*) begin + interface1_we_next_value3 <= 1'd0; + case (state) + 1'd1: begin + interface1_we_next_value3 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value3 <= (interface0_we & (interface0_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + interface1_we_next_value_ce3 <= 1'd0; + case (state) + 1'd1: begin + interface1_we_next_value_ce3 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_we_next_value_ce3 <= 1'd1; + end + end + endcase +end always @(*) begin interface1_dat_w_next_value0 <= 32'd0; case (state) @@ -10652,98 +10664,98 @@ always @(*) begin endcase end always @(*) begin - interface1_dat_w_next_value_ce0 <= 1'd0; + interface0_ack <= 1'd0; case (state) 1'd1: begin end 2'd2: begin + interface0_ack <= 1'd1; end default: begin - interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - interface1_adr_next_value1 <= 14'd0; + interface1_dat_w_next_value_ce0 <= 1'd0; case (state) 1'd1: begin - interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin - if ((interface0_cyc & interface0_stb)) begin - interface1_adr_next_value1 <= interface0_adr[29:0]; - end + interface1_dat_w_next_value_ce0 <= 1'd1; end endcase end always @(*) begin - interface1_adr_next_value_ce1 <= 1'd0; + interface0_dat_r <= 32'd0; case (state) 1'd1: begin - interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin + interface0_dat_r <= interface1_dat_r; end default: begin - if ((interface0_cyc & interface0_stb)) begin - interface1_adr_next_value_ce1 <= 1'd1; - end end endcase end always @(*) begin - interface1_we_next_value2 <= 1'd0; + interface1_adr_next_value1 <= 14'd0; case (state) 1'd1: begin - interface1_we_next_value2 <= 1'd0; + interface1_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin if ((interface0_cyc & interface0_stb)) begin - interface1_we_next_value2 <= (interface0_we & (interface0_sel != 1'd0)); + interface1_adr_next_value1 <= interface0_adr; end end endcase end always @(*) begin - interface1_we_next_value_ce2 <= 1'd0; + interface1_adr_next_value_ce1 <= 1'd0; case (state) 1'd1: begin - interface1_we_next_value_ce2 <= 1'd1; + interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin if ((interface0_cyc & interface0_stb)) begin - interface1_we_next_value_ce2 <= 1'd1; + interface1_adr_next_value_ce1 <= 1'd1; end end endcase end always @(*) begin - interface0_dat_r <= 32'd0; + interface1_re_next_value2 <= 1'd0; case (state) 1'd1: begin + interface1_re_next_value2 <= 1'd0; end 2'd2: begin - interface0_dat_r <= interface1_dat_r; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_re_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0)); + end end endcase end always @(*) begin - interface0_ack <= 1'd0; + interface1_re_next_value_ce2 <= 1'd0; case (state) 1'd1: begin + interface1_re_next_value_ce2 <= 1'd1; end 2'd2: begin - interface0_ack <= 1'd1; end default: begin + if ((interface0_cyc & interface0_stb)) begin + interface1_re_next_value_ce2 <= 1'd1; + end end endcase end @@ -10758,20 +10770,20 @@ end always @(*) begin csrbank0_init_done0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); + csrbank0_init_done0_we <= interface0_bank_bus_re; end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; + csrbank0_init_error0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; + csrbank0_init_error0_we <= interface0_bank_bus_re; end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; + csrbank0_init_error0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); + csrbank0_init_error0_re <= interface0_bank_bus_we; end end assign csrbank0_init_done0_w = soc_init_done_storage; @@ -10779,61 +10791,61 @@ assign csrbank0_init_error0_w = soc_init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; always @(*) begin - csrbank1_dfii_control0_re <= 1'd0; + csrbank1_dfii_control0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_re <= interface1_bank_bus_we; + csrbank1_dfii_control0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_control0_we <= 1'd0; + csrbank1_dfii_control0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_control0_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - csrbank1_dfii_pi0_command0_we <= 1'd0; + csrbank1_dfii_pi0_command0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi0_command0_re <= 1'd0; + csrbank1_dfii_pi0_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_command0_we <= interface1_bank_bus_re; end end assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; + soc_litedramcore_phaseinjector0_command_issue_we <= interface1_bank_bus_re; end end always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi0_address0_re <= 1'd0; + csrbank1_dfii_pi0_address0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_address0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi0_address0_we <= 1'd0; + csrbank1_dfii_pi0_address0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin csrbank1_dfii_pi0_baddress0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_baddress0_we <= interface1_bank_bus_re; end end always @(*) begin @@ -10842,37 +10854,37 @@ always @(*) begin csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w; always @(*) begin - csrbank1_dfii_pi0_wrdata0_we <= 1'd0; + csrbank1_dfii_pi0_wrdata0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi0_wrdata0_re <= 1'd0; + csrbank1_dfii_pi0_wrdata0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_wrdata0_we <= interface1_bank_bus_re; end end -assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w; always @(*) begin - csrbank1_dfii_pi0_rddata_re <= 1'd0; + csrbank1_dfii_pi0_rddata_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; + csrbank1_dfii_pi0_rddata_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi0_rddata_we <= 1'd0; + csrbank1_dfii_pi0_rddata_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin csrbank1_dfii_pi1_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_command0_we <= interface1_bank_bus_re; end end always @(*) begin @@ -10883,57 +10895,57 @@ always @(*) begin end assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; end end always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; + soc_litedramcore_phaseinjector1_command_issue_we <= interface1_bank_bus_re; end end assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi1_address0_we <= 1'd0; + csrbank1_dfii_pi1_address0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi1_address0_re <= 1'd0; + csrbank1_dfii_pi1_address0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi1_address0_we <= interface1_bank_bus_re; end end assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi1_baddress0_re <= 1'd0; + csrbank1_dfii_pi1_baddress0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi1_baddress0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi1_baddress0_we <= 1'd0; + csrbank1_dfii_pi1_baddress0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w; always @(*) begin - csrbank1_dfii_pi1_wrdata0_we <= 1'd0; + csrbank1_dfii_pi1_wrdata0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi1_wrdata0_re <= 1'd0; + csrbank1_dfii_pi1_wrdata0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi1_wrdata0_we <= interface1_bank_bus_re; end end -assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dfii_pi1_rddata_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin @@ -10943,46 +10955,46 @@ end always @(*) begin csrbank1_dfii_pi1_rddata_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi1_rddata_we <= interface1_bank_bus_re; end end assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[7:0]; always @(*) begin - csrbank1_dfii_pi2_command0_re <= 1'd0; + csrbank1_dfii_pi2_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_command0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi2_command0_we <= 1'd0; + csrbank1_dfii_pi2_command0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; end end assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we; + soc_litedramcore_phaseinjector2_command_issue_we <= interface1_bank_bus_re; end end always @(*) begin - soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi2_address0_we <= 1'd0; + csrbank1_dfii_pi2_address0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_address0_re <= 1'd0; + csrbank1_dfii_pi2_address0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_address0_we <= interface1_bank_bus_re; end end assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; @@ -10995,33 +11007,33 @@ end always @(*) begin csrbank1_dfii_pi2_baddress0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_baddress0_we <= interface1_bank_bus_re; end end -assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w; always @(*) begin - csrbank1_dfii_pi2_wrdata0_re <= 1'd0; + csrbank1_dfii_pi2_wrdata0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_wrdata0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi2_wrdata0_we <= 1'd0; + csrbank1_dfii_pi2_wrdata0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w; always @(*) begin - csrbank1_dfii_pi2_rddata_we <= 1'd0; + csrbank1_dfii_pi2_rddata_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi2_rddata_re <= 1'd0; + csrbank1_dfii_pi2_rddata_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; + csrbank1_dfii_pi2_rddata_we <= interface1_bank_bus_re; end end assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[7:0]; @@ -11034,14 +11046,14 @@ end always @(*) begin csrbank1_dfii_pi3_command0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin - csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_command0_we <= interface1_bank_bus_re; end end assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin - soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we); + soc_litedramcore_phaseinjector3_command_issue_we <= interface1_bank_bus_re; end end always @(*) begin @@ -11052,48 +11064,48 @@ always @(*) begin end assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi3_address0_re <= 1'd0; + csrbank1_dfii_pi3_address0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi3_address0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi3_address0_we <= 1'd0; + csrbank1_dfii_pi3_address0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; end end assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi3_baddress0_we <= 1'd0; + csrbank1_dfii_pi3_baddress0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; end end always @(*) begin - csrbank1_dfii_pi3_baddress0_re <= 1'd0; + csrbank1_dfii_pi3_baddress0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi3_baddress0_we <= interface1_bank_bus_re; end end -assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w; always @(*) begin - csrbank1_dfii_pi3_wrdata0_re <= 1'd0; + csrbank1_dfii_pi3_wrdata0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin - csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we; + csrbank1_dfii_pi3_wrdata0_we <= interface1_bank_bus_re; end end always @(*) begin - csrbank1_dfii_pi3_wrdata0_we <= 1'd0; + csrbank1_dfii_pi3_wrdata0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin - csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we; end end -assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dfii_pi3_rddata_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin - csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we); + csrbank1_dfii_pi3_rddata_we <= interface1_bank_bus_re; end end always @(*) begin @@ -11106,7 +11118,7 @@ assign soc_litedramcore_sel = soc_litedramcore_storage[0]; assign soc_litedramcore_cke = soc_litedramcore_storage[1]; assign soc_litedramcore_odt = soc_litedramcore_storage[2]; assign soc_litedramcore_reset_n = soc_litedramcore_storage[3]; -assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0]; +assign csrbank1_dfii_control0_w = soc_litedramcore_storage; assign soc_litedramcore_phaseinjector0_csrfield_cs = soc_litedramcore_phaseinjector0_command_storage[0]; assign soc_litedramcore_phaseinjector0_csrfield_we = soc_litedramcore_phaseinjector0_command_storage[1]; assign soc_litedramcore_phaseinjector0_csrfield_cas = soc_litedramcore_phaseinjector0_command_storage[2]; @@ -11115,11 +11127,11 @@ assign soc_litedramcore_phaseinjector0_csrfield_wren = soc_litedramcore_phaseinj assign soc_litedramcore_phaseinjector0_csrfield_rden = soc_litedramcore_phaseinjector0_command_storage[5]; assign soc_litedramcore_phaseinjector0_csrfield_cs_top = soc_litedramcore_phaseinjector0_command_storage[6]; assign soc_litedramcore_phaseinjector0_csrfield_cs_bottom = soc_litedramcore_phaseinjector0_command_storage[7]; -assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[7:0]; -assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[13:0]; -assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status[31:0]; +assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage; +assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage; +assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage; +assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage; +assign csrbank1_dfii_pi0_rddata_w = soc_litedramcore_phaseinjector0_rddata_status; assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata_we; assign soc_litedramcore_phaseinjector1_csrfield_cs = soc_litedramcore_phaseinjector1_command_storage[0]; assign soc_litedramcore_phaseinjector1_csrfield_we = soc_litedramcore_phaseinjector1_command_storage[1]; @@ -11129,11 +11141,11 @@ assign soc_litedramcore_phaseinjector1_csrfield_wren = soc_litedramcore_phaseinj assign soc_litedramcore_phaseinjector1_csrfield_rden = soc_litedramcore_phaseinjector1_command_storage[5]; assign soc_litedramcore_phaseinjector1_csrfield_cs_top = soc_litedramcore_phaseinjector1_command_storage[6]; assign soc_litedramcore_phaseinjector1_csrfield_cs_bottom = soc_litedramcore_phaseinjector1_command_storage[7]; -assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[7:0]; -assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[13:0]; -assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status[31:0]; +assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage; +assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage; +assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage; +assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage; +assign csrbank1_dfii_pi1_rddata_w = soc_litedramcore_phaseinjector1_rddata_status; assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata_we; assign soc_litedramcore_phaseinjector2_csrfield_cs = soc_litedramcore_phaseinjector2_command_storage[0]; assign soc_litedramcore_phaseinjector2_csrfield_we = soc_litedramcore_phaseinjector2_command_storage[1]; @@ -11143,11 +11155,11 @@ assign soc_litedramcore_phaseinjector2_csrfield_wren = soc_litedramcore_phaseinj assign soc_litedramcore_phaseinjector2_csrfield_rden = soc_litedramcore_phaseinjector2_command_storage[5]; assign soc_litedramcore_phaseinjector2_csrfield_cs_top = soc_litedramcore_phaseinjector2_command_storage[6]; assign soc_litedramcore_phaseinjector2_csrfield_cs_bottom = soc_litedramcore_phaseinjector2_command_storage[7]; -assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[7:0]; -assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[13:0]; -assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status[31:0]; +assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage; +assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage; +assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage; +assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage; +assign csrbank1_dfii_pi2_rddata_w = soc_litedramcore_phaseinjector2_rddata_status; assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata_we; assign soc_litedramcore_phaseinjector3_csrfield_cs = soc_litedramcore_phaseinjector3_command_storage[0]; assign soc_litedramcore_phaseinjector3_csrfield_we = soc_litedramcore_phaseinjector3_command_storage[1]; @@ -11157,18 +11169,21 @@ assign soc_litedramcore_phaseinjector3_csrfield_wren = soc_litedramcore_phaseinj assign soc_litedramcore_phaseinjector3_csrfield_rden = soc_litedramcore_phaseinjector3_command_storage[5]; assign soc_litedramcore_phaseinjector3_csrfield_cs_top = soc_litedramcore_phaseinjector3_command_storage[6]; assign soc_litedramcore_phaseinjector3_csrfield_cs_bottom = soc_litedramcore_phaseinjector3_command_storage[7]; -assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[7:0]; -assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[13:0]; -assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status[31:0]; +assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage; +assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage; +assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage; +assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage; +assign csrbank1_dfii_pi3_rddata_w = soc_litedramcore_phaseinjector3_rddata_status; assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata_we; assign adr = interface1_adr; +assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface0_bank_bus_dat_w = dat_w; @@ -11908,16 +11923,16 @@ always @(*) begin self0 <= 3'd0; case (soc_litedramcore_steerer0) 1'd0: begin - self0 <= soc_litedramcore_nop_ba[2:0]; + self0 <= soc_litedramcore_nop_ba; end 1'd1: begin - self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self0 <= soc_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self0 <= soc_litedramcore_choose_req_cmd_payload_ba; end default: begin - self0 <= soc_litedramcore_cmd_payload_ba[2:0]; + self0 <= soc_litedramcore_cmd_payload_ba; end endcase end @@ -12027,16 +12042,16 @@ always @(*) begin self7 <= 3'd0; case (soc_litedramcore_steerer1) 1'd0: begin - self7 <= soc_litedramcore_nop_ba[2:0]; + self7 <= soc_litedramcore_nop_ba; end 1'd1: begin - self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self7 <= soc_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self7 <= soc_litedramcore_choose_req_cmd_payload_ba; end default: begin - self7 <= soc_litedramcore_cmd_payload_ba[2:0]; + self7 <= soc_litedramcore_cmd_payload_ba; end endcase end @@ -12146,16 +12161,16 @@ always @(*) begin self14 <= 3'd0; case (soc_litedramcore_steerer2) 1'd0: begin - self14 <= soc_litedramcore_nop_ba[2:0]; + self14 <= soc_litedramcore_nop_ba; end 1'd1: begin - self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self14 <= soc_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self14 <= soc_litedramcore_choose_req_cmd_payload_ba; end default: begin - self14 <= soc_litedramcore_cmd_payload_ba[2:0]; + self14 <= soc_litedramcore_cmd_payload_ba; end endcase end @@ -12265,16 +12280,16 @@ always @(*) begin self21 <= 3'd0; case (soc_litedramcore_steerer3) 1'd0: begin - self21 <= soc_litedramcore_nop_ba[2:0]; + self21 <= soc_litedramcore_nop_ba; end 1'd1: begin - self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + self21 <= soc_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - self21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + self21 <= soc_litedramcore_choose_req_cmd_payload_ba; end default: begin - self21 <= soc_litedramcore_cmd_payload_ba[2:0]; + self21 <= soc_litedramcore_cmd_payload_ba; end endcase end @@ -13798,8 +13813,11 @@ always @(posedge sys_clk) begin if (interface1_adr_next_value_ce1) begin interface1_adr <= interface1_adr_next_value1; end - if (interface1_we_next_value_ce2) begin - interface1_we <= interface1_we_next_value2; + if (interface1_re_next_value_ce2) begin + interface1_re <= interface1_re_next_value2; + end + if (interface1_we_next_value_ce3) begin + interface1_we <= interface1_we_next_value3; end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin @@ -13901,74 +13919,74 @@ always @(posedge sys_clk) begin endcase end if (csrbank1_dfii_control0_re) begin - soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r; + soc_litedramcore_storage <= csrbank1_dfii_control0_r; end soc_litedramcore_re <= csrbank1_dfii_control0_re; if (csrbank1_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[7:0] <= csrbank1_dfii_pi0_command0_r; + soc_litedramcore_phaseinjector0_command_storage <= csrbank1_dfii_pi0_command0_r; end soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; if (csrbank1_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; + soc_litedramcore_phaseinjector0_address_storage <= csrbank1_dfii_pi0_address0_r; end soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; if (csrbank1_dfii_pi0_baddress0_re) begin - soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; + soc_litedramcore_phaseinjector0_baddress_storage <= csrbank1_dfii_pi0_baddress0_r; end soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; if (csrbank1_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; + soc_litedramcore_phaseinjector0_wrdata_storage <= csrbank1_dfii_pi0_wrdata0_r; end soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re; if (csrbank1_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[7:0] <= csrbank1_dfii_pi1_command0_r; + soc_litedramcore_phaseinjector1_command_storage <= csrbank1_dfii_pi1_command0_r; end soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; if (csrbank1_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; + soc_litedramcore_phaseinjector1_address_storage <= csrbank1_dfii_pi1_address0_r; end soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; if (csrbank1_dfii_pi1_baddress0_re) begin - soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; + soc_litedramcore_phaseinjector1_baddress_storage <= csrbank1_dfii_pi1_baddress0_r; end soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; if (csrbank1_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; + soc_litedramcore_phaseinjector1_wrdata_storage <= csrbank1_dfii_pi1_wrdata0_r; end soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re; if (csrbank1_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[7:0] <= csrbank1_dfii_pi2_command0_r; + soc_litedramcore_phaseinjector2_command_storage <= csrbank1_dfii_pi2_command0_r; end soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; if (csrbank1_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; + soc_litedramcore_phaseinjector2_address_storage <= csrbank1_dfii_pi2_address0_r; end soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; if (csrbank1_dfii_pi2_baddress0_re) begin - soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; + soc_litedramcore_phaseinjector2_baddress_storage <= csrbank1_dfii_pi2_baddress0_r; end soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; if (csrbank1_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; + soc_litedramcore_phaseinjector2_wrdata_storage <= csrbank1_dfii_pi2_wrdata0_r; end soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re; if (csrbank1_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[7:0] <= csrbank1_dfii_pi3_command0_r; + soc_litedramcore_phaseinjector3_command_storage <= csrbank1_dfii_pi3_command0_r; end soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; if (csrbank1_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; + soc_litedramcore_phaseinjector3_address_storage <= csrbank1_dfii_pi3_address0_r; end soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; if (csrbank1_dfii_pi3_baddress0_re) begin - soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; + soc_litedramcore_phaseinjector3_baddress_storage <= csrbank1_dfii_pi3_baddress0_r; end soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; if (csrbank1_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; + soc_litedramcore_phaseinjector3_wrdata_storage <= csrbank1_dfii_pi3_wrdata0_r; end soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re; @@ -14225,6 +14243,7 @@ always @(posedge sys_clk) begin soc_init_done_re <= 1'd0; soc_init_error_storage <= 1'd0; soc_init_error_re <= 1'd0; + interface1_re <= 1'd0; interface1_we <= 1'd0; refresher_state <= 2'd0; bankmachine0_state <= 4'd0; @@ -14787,5 +14806,5 @@ assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_b endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:12. +// Auto-Generated by LiteX on 2025-02-15 19:54:54. //------------------------------------------------------------------------------ diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init index 0573632..843a495 100644 --- a/litedram/generated/wukong-v2/litedram_core.init +++ b/litedram/generated/wukong-v2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d4658cff00 +618c114c658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -510,14 +510,29 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3920000039406004 +3920000239406004 7c0004ac654ac000 -600000007d2057aa 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63694d206f742065 2120747461776f72 @@ -1853,14 +1879,18 @@ e8010010ebc1fff0 696c62616e652020 004441555120676e 006e6f7263694d20 +0000004953534920 +696c62616e655b20 +5d6461757120676e +0000000000000000 4920646175715b20 005d65646f6d204f 414c462049505320 203a46464f204853 7479622078257830 00000000000a7365 -3033633733313738 -0000000000000000 +3235663166316362 +0000000000000062 4d4152446574694c 6620746c69756220 6574694c206d6f72 @@ -1921,15 +1951,13 @@ e8010010ebc1fff0 000000000000207c 203a747365622020 302562202c64256d -6000000000206432 +0000000000206432 76656c2064616552 000a3a676e696c65 696c616974696e49 52445320676e697a 3025783040204d41 000a2e2e2e786c38 -000000540000002a -6000000000000024 0000000042756c25 4b756c252e756c25 0000000000004269 @@ -1971,11 +1999,12 @@ e8010010ebc1fff0 20747365746d654d 00000000000a4f4b 20747365746d654d -60000000000a4b4f +00000000000a4b4f 3736353433323130 6665646362613938 0000000000000000 -0000000000007830 +0000002a00007830 +0000002400000054 0000000000000000 00000000000000ff 000000000000ffff diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v index d66961b..25178fe 100644 --- a/litedram/generated/wukong-v2/litedram_core.v +++ b/litedram/generated/wukong-v2/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-01 10:12:10 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-15 19:54:47 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -80,18 +80,18 @@ LiteDRAMCore └─── crg (LiteDRAMS7DDRPHYCRG) │ └─── pll (S7PLL) │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] -│ │ └─── [BUFG] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] │ │ └─── [FDCE] +│ │ └─── [PLLE2_ADV] +│ │ └─── [BUFG] +│ │ └─── [BUFG] │ │ └─── [BUFG] │ │ └─── [BUFG] -│ │ └─── [PLLE2_ADV] │ └─── idelayctrl (S7IDELAYCTRL) │ │ └─── [IDELAYCTRL] └─── ddrphy (A7DDRPHY) @@ -136,102 +136,102 @@ LiteDRAMCore │ └─── bitslip_35* (BitSlip) │ └─── tappeddelayline_2* (TappedDelayLine) │ └─── tappeddelayline_3* (TappedDelayLine) -│ └─── [IOBUF] -│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [OSERDESE2] -│ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [OBUFDS] │ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUFDS] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [IOBUFDS] │ └─── [OSERDESE2] +│ └─── [IOBUFDS] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [OSERDESE2] -│ └─── [IDELAYE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [IDELAYE2] │ └─── [ISERDESE2] -│ └─── [IOBUF] │ └─── [IDELAYE2] -│ └─── [IOBUF] │ └─── [IDELAYE2] +│ └─── [IOBUF] +│ └─── [OSERDESE2] │ └─── [ISERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] │ └─── [IDELAYE2] │ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] +│ └─── [ISERDESE2] +│ └─── [IDELAYE2] +│ └─── [IOBUF] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [ISERDESE2] -│ └─── [IOBUF] +│ └─── [OBUFDS] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] │ └─── [OSERDESE2] -│ └─── [IOBUF] -│ └─── [ISERDESE2] │ └─── [OSERDESE2] -│ └─── [IDELAYE2] └─── sdram (LiteDRAMCore) │ └─── dfii (DFIInjector) │ │ └─── pi0 (PhaseInjector) @@ -543,6 +543,7 @@ wire [29:0] builder_interface0_adr; wire [13:0] builder_interface0_bank_bus_adr; reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_re; wire builder_interface0_bank_bus_we; wire [1:0] builder_interface0_bte; wire [2:0] builder_interface0_cti; @@ -559,17 +560,22 @@ reg builder_interface1_adr_next_value_ce1 = 1'd0; wire [13:0] builder_interface1_bank_bus_adr; reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_re; wire builder_interface1_bank_bus_we; wire [31:0] builder_interface1_dat_r; reg [31:0] builder_interface1_dat_w = 32'd0; reg [31:0] builder_interface1_dat_w_next_value0 = 32'd0; reg builder_interface1_dat_w_next_value_ce0 = 1'd0; +reg builder_interface1_re = 1'd0; +reg builder_interface1_re_next_value2 = 1'd0; +reg builder_interface1_re_next_value_ce2 = 1'd0; reg builder_interface1_we = 1'd0; -reg builder_interface1_we_next_value2 = 1'd0; -reg builder_interface1_we_next_value_ce2 = 1'd0; +reg builder_interface1_we_next_value3 = 1'd0; +reg builder_interface1_we_next_value_ce3 = 1'd0; wire [13:0] builder_interface2_bank_bus_adr; reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_re; wire builder_interface2_bank_bus_we; reg builder_locked0 = 1'd0; reg builder_locked1 = 1'd0; @@ -594,6 +600,7 @@ reg builder_new_master_wdata_ready0 = 1'd0; reg builder_new_master_wdata_ready1 = 1'd0; reg [1:0] builder_next_state = 2'd0; wire builder_pll_fb; +wire builder_re; reg [1:0] builder_refresher_next_state = 2'd0; reg [1:0] builder_refresher_state = 2'd0; wire builder_reset0; @@ -700,14 +707,14 @@ reg builder_t_self3 = 1'd0; reg builder_t_self4 = 1'd0; reg builder_t_self5 = 1'd0; wire builder_we; -wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0; wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl1_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl1; wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl2; wire builder_xilinxasyncresetsynchronizerimpl2_expr; wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl3_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl3; wire builder_xilinxasyncresetsynchronizerimpl3_expr; wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; wire iodelay_clk; @@ -1895,9 +1902,9 @@ reg main_litedramcore_csr_dfi_p0_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p0_address; wire [2:0] main_litedramcore_csr_dfi_p0_bank; reg main_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_cke = 1'd0; +wire main_litedramcore_csr_dfi_p0_cke; reg main_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p0_odt = 1'd0; +wire main_litedramcore_csr_dfi_p0_odt; reg main_litedramcore_csr_dfi_p0_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p0_rddata = 32'd0; wire main_litedramcore_csr_dfi_p0_rddata_en; @@ -1911,9 +1918,9 @@ reg main_litedramcore_csr_dfi_p1_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p1_address; wire [2:0] main_litedramcore_csr_dfi_p1_bank; reg main_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_cke = 1'd0; +wire main_litedramcore_csr_dfi_p1_cke; reg main_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p1_odt = 1'd0; +wire main_litedramcore_csr_dfi_p1_odt; reg main_litedramcore_csr_dfi_p1_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p1_rddata = 32'd0; wire main_litedramcore_csr_dfi_p1_rddata_en; @@ -1927,9 +1934,9 @@ reg main_litedramcore_csr_dfi_p2_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p2_address; wire [2:0] main_litedramcore_csr_dfi_p2_bank; reg main_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_cke = 1'd0; +wire main_litedramcore_csr_dfi_p2_cke; reg main_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p2_odt = 1'd0; +wire main_litedramcore_csr_dfi_p2_odt; reg main_litedramcore_csr_dfi_p2_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p2_rddata = 32'd0; wire main_litedramcore_csr_dfi_p2_rddata_en; @@ -1943,9 +1950,9 @@ reg main_litedramcore_csr_dfi_p3_act_n = 1'd1; wire [13:0] main_litedramcore_csr_dfi_p3_address; wire [2:0] main_litedramcore_csr_dfi_p3_bank; reg main_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_cke = 1'd0; +wire main_litedramcore_csr_dfi_p3_cke; reg main_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg main_litedramcore_csr_dfi_p3_odt = 1'd0; +wire main_litedramcore_csr_dfi_p3_odt; reg main_litedramcore_csr_dfi_p3_ras_n = 1'd1; reg [31:0] main_litedramcore_csr_dfi_p3_rddata = 32'd0; wire main_litedramcore_csr_dfi_p3_rddata_en; @@ -4763,42 +4770,26 @@ always @(*) begin main_litedramcore_master_p3_rddata_en <= main_litedramcore_csr_dfi_p3_rddata_en; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_cke <= 1'd0; - main_litedramcore_csr_dfi_p0_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_cke <= 1'd0; - main_litedramcore_csr_dfi_p1_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_cke <= 1'd0; - main_litedramcore_csr_dfi_p2_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_cke <= 1'd0; - main_litedramcore_csr_dfi_p3_cke <= main_litedramcore_cke; -end -always @(*) begin - main_litedramcore_csr_dfi_p0_odt <= 1'd0; - main_litedramcore_csr_dfi_p0_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p1_odt <= 1'd0; - main_litedramcore_csr_dfi_p1_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p2_odt <= 1'd0; - main_litedramcore_csr_dfi_p2_odt <= main_litedramcore_odt; -end -always @(*) begin - main_litedramcore_csr_dfi_p3_odt <= 1'd0; - main_litedramcore_csr_dfi_p3_odt <= main_litedramcore_odt; -end +assign main_litedramcore_csr_dfi_p0_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p1_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p2_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p3_cke = main_litedramcore_cke; +assign main_litedramcore_csr_dfi_p0_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p1_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p2_odt = main_litedramcore_odt; +assign main_litedramcore_csr_dfi_p3_odt = main_litedramcore_odt; assign main_litedramcore_csr_dfi_p0_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p1_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p2_reset_n = main_litedramcore_reset_n; assign main_litedramcore_csr_dfi_p3_reset_n = main_litedramcore_reset_n; +always @(*) begin + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector0_command_issue_re) begin + main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p0_we_n <= 1'd1; if (main_litedramcore_phaseinjector0_command_issue_re) begin @@ -4831,20 +4822,20 @@ always @(*) begin main_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector0_command_issue_re) begin - main_litedramcore_csr_dfi_p0_ras_n <= (~main_litedramcore_phaseinjector0_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p0_address = main_litedramcore_phaseinjector0_address_storage; assign main_litedramcore_csr_dfi_p0_bank = main_litedramcore_phaseinjector0_baddress_storage; assign main_litedramcore_csr_dfi_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_wren); assign main_litedramcore_csr_dfi_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_csrfield_rden); assign main_litedramcore_csr_dfi_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage; assign main_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector1_command_issue_re) begin + main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p1_we_n <= 1'd1; if (main_litedramcore_phaseinjector1_command_issue_re) begin @@ -4877,20 +4868,20 @@ always @(*) begin main_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector1_command_issue_re) begin - main_litedramcore_csr_dfi_p1_ras_n <= (~main_litedramcore_phaseinjector1_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p1_address = main_litedramcore_phaseinjector1_address_storage; assign main_litedramcore_csr_dfi_p1_bank = main_litedramcore_phaseinjector1_baddress_storage; assign main_litedramcore_csr_dfi_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_wren); assign main_litedramcore_csr_dfi_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_csrfield_rden); assign main_litedramcore_csr_dfi_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage; assign main_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector2_command_issue_re) begin + main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p2_we_n <= 1'd1; if (main_litedramcore_phaseinjector2_command_issue_re) begin @@ -4923,20 +4914,20 @@ always @(*) begin main_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector2_command_issue_re) begin - main_litedramcore_csr_dfi_p2_ras_n <= (~main_litedramcore_phaseinjector2_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p2_address = main_litedramcore_phaseinjector2_address_storage; assign main_litedramcore_csr_dfi_p2_bank = main_litedramcore_phaseinjector2_baddress_storage; assign main_litedramcore_csr_dfi_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_wren); assign main_litedramcore_csr_dfi_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_csrfield_rden); assign main_litedramcore_csr_dfi_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage; assign main_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; +always @(*) begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (main_litedramcore_phaseinjector3_command_issue_re) begin + main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); + end else begin + main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end +end always @(*) begin main_litedramcore_csr_dfi_p3_we_n <= 1'd1; if (main_litedramcore_phaseinjector3_command_issue_re) begin @@ -4969,14 +4960,6 @@ always @(*) begin main_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end -always @(*) begin - main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (main_litedramcore_phaseinjector3_command_issue_re) begin - main_litedramcore_csr_dfi_p3_ras_n <= (~main_litedramcore_phaseinjector3_csrfield_ras); - end else begin - main_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end -end assign main_litedramcore_csr_dfi_p3_address = main_litedramcore_phaseinjector3_address_storage; assign main_litedramcore_csr_dfi_p3_bank = main_litedramcore_phaseinjector3_baddress_storage; assign main_litedramcore_csr_dfi_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_csrfield_wren); @@ -5085,82 +5068,82 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_cmd_valid <= 1'd0; + main_litedramcore_zqcs_executer_start <= 1'd0; case (builder_refresher_state) 1'd1: begin - main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin - main_litedramcore_cmd_valid <= 1'd1; if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin + main_litedramcore_zqcs_executer_start <= 1'd1; end else begin - main_litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin - main_litedramcore_cmd_valid <= 1'd1; - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_valid <= 1'd0; - end end default: begin end endcase end always @(*) begin - main_litedramcore_zqcs_executer_start <= 1'd0; + main_litedramcore_cmd_last <= 1'd0; case (builder_refresher_state) 1'd1: begin end 2'd2: begin if (main_litedramcore_sequencer_done0) begin if (main_litedramcore_wants_zqcs) begin - main_litedramcore_zqcs_executer_start <= 1'd1; end else begin + main_litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_last <= 1'd1; + end end default: begin end endcase end always @(*) begin - main_litedramcore_cmd_last <= 1'd0; + main_litedramcore_sequencer_start0 <= 1'd0; case (builder_refresher_state) 1'd1: begin + if (main_litedramcore_cmd_ready) begin + main_litedramcore_sequencer_start0 <= 1'd1; + end end 2'd2: begin - if (main_litedramcore_sequencer_done0) begin - if (main_litedramcore_wants_zqcs) begin - end else begin - main_litedramcore_cmd_last <= 1'd1; - end - end end 2'd3: begin - if (main_litedramcore_zqcs_executer_done) begin - main_litedramcore_cmd_last <= 1'd1; - end end default: begin end endcase end always @(*) begin - main_litedramcore_sequencer_start0 <= 1'd0; + main_litedramcore_cmd_valid <= 1'd0; case (builder_refresher_state) 1'd1: begin - if (main_litedramcore_cmd_ready) begin - main_litedramcore_sequencer_start0 <= 1'd1; - end + main_litedramcore_cmd_valid <= 1'd1; end 2'd2: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_sequencer_done0) begin + if (main_litedramcore_wants_zqcs) begin + end else begin + main_litedramcore_cmd_valid <= 1'd0; + end + end end 2'd3: begin + main_litedramcore_cmd_valid <= 1'd1; + if (main_litedramcore_zqcs_executer_done) begin + main_litedramcore_cmd_valid <= 1'd0; + end end default: begin end @@ -5306,7 +5289,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5331,8 +5314,8 @@ always @(*) begin if (main_litedramcore_bankmachine0_row_opened) begin if (main_litedramcore_bankmachine0_row_hit) begin if (main_litedramcore_bankmachine0_source_source_payload_we) begin - main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -5344,7 +5327,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end @@ -5353,6 +5336,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine0_twtpcon_ready) begin + main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -5363,32 +5349,20 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_source_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_source_source_payload_we) begin - main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine0_row_open <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine0_trccon_ready) begin + main_litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -5401,78 +5375,11 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine0_source_source_valid) begin - if (main_litedramcore_bankmachine0_row_opened) begin - if (main_litedramcore_bankmachine0_row_hit) begin - if (main_litedramcore_bankmachine0_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine0_twtpcon_ready) begin - main_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_row_open <= 1'd0; - case (builder_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine0_trccon_ready) begin - main_litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine0_cmd_valid <= 1'd0; + main_litedramcore_bankmachine0_cmd_valid <= 1'd0; case (builder_bankmachine0_state) 1'd1: begin if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin @@ -5737,6 +5644,82 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (builder_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine0_source_source_valid) begin + if (main_litedramcore_bankmachine0_row_opened) begin + if (main_litedramcore_bankmachine0_row_hit) begin + if (main_litedramcore_bankmachine0_source_source_payload_we) begin + main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine1_sink_valid = main_litedramcore_bankmachine1_req_valid; assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_sink_ready; assign main_litedramcore_bankmachine1_sink_payload_we = main_litedramcore_bankmachine1_req_we; @@ -5876,125 +5859,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine1_twtpcon_ready) begin - main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_row_open <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine1_trccon_ready) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine1_source_source_valid) begin - if (main_litedramcore_bankmachine1_row_opened) begin - if (main_litedramcore_bankmachine1_row_hit) begin - main_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine1_row_close <= 1'd0; - case (builder_bankmachine1_state) - 1'd1: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine1_state) @@ -6308,17 +6172,136 @@ always @(*) begin end endcase end -assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; -assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; -assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; -assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; -assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; -assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; -assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; -assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; -assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; -assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; -assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); +always @(*) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine1_twtpcon_ready) begin + main_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_row_open <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine1_trccon_ready) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine1_source_source_valid) begin + if (main_litedramcore_bankmachine1_row_opened) begin + if (main_litedramcore_bankmachine1_row_hit) begin + main_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine1_row_close <= 1'd0; + case (builder_bankmachine1_state) + 1'd1: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign main_litedramcore_bankmachine2_sink_valid = main_litedramcore_bankmachine2_req_valid; +assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_sink_ready; +assign main_litedramcore_bankmachine2_sink_payload_we = main_litedramcore_bankmachine2_req_we; +assign main_litedramcore_bankmachine2_sink_payload_addr = main_litedramcore_bankmachine2_req_addr; +assign main_litedramcore_bankmachine2_sink_sink_valid = main_litedramcore_bankmachine2_source_valid; +assign main_litedramcore_bankmachine2_source_ready = main_litedramcore_bankmachine2_sink_sink_ready; +assign main_litedramcore_bankmachine2_sink_sink_first = main_litedramcore_bankmachine2_source_first; +assign main_litedramcore_bankmachine2_sink_sink_last = main_litedramcore_bankmachine2_source_last; +assign main_litedramcore_bankmachine2_sink_sink_payload_we = main_litedramcore_bankmachine2_source_payload_we; +assign main_litedramcore_bankmachine2_sink_sink_payload_addr = main_litedramcore_bankmachine2_source_payload_addr; +assign main_litedramcore_bankmachine2_source_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid); assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_source_valid | main_litedramcore_bankmachine2_source_source_valid); assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_source_source_payload_addr[20:7]); assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; @@ -6447,32 +6430,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine2_trccon_ready) begin - main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (builder_bankmachine2_state) @@ -6879,6 +6836,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine2_trccon_ready) begin + main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine3_sink_valid = main_litedramcore_bankmachine3_req_valid; assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_sink_ready; assign main_litedramcore_bankmachine3_sink_payload_we = main_litedramcore_bankmachine3_req_we; @@ -7018,76 +7001,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin - main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine3_source_source_valid) begin - if (main_litedramcore_bankmachine3_row_opened) begin - if (main_litedramcore_bankmachine3_row_hit) begin - if (main_litedramcore_bankmachine3_source_source_payload_we) begin - main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine3_state) @@ -7297,33 +7210,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine3_row_open <= 1'd0; - case (builder_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine3_trccon_ready) begin - main_litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine3_cmd_valid <= 1'd0; + main_litedramcore_bankmachine3_cmd_valid <= 1'd0; case (builder_bankmachine3_state) 1'd1: begin if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin @@ -7389,6 +7276,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_row_open <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end always @(*) begin main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine3_state) @@ -7450,6 +7363,76 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine3_trccon_ready) begin + main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine3_source_source_valid) begin + if (main_litedramcore_bankmachine3_row_opened) begin + if (main_litedramcore_bankmachine3_row_hit) begin + if (main_litedramcore_bankmachine3_source_source_payload_we) begin + main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine4_sink_valid = main_litedramcore_bankmachine4_req_valid; assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_sink_ready; assign main_litedramcore_bankmachine4_sink_payload_we = main_litedramcore_bankmachine4_req_we; @@ -7589,82 +7572,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_source_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_source_source_payload_we) begin - main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (builder_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (main_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine4_source_source_valid) begin - if (main_litedramcore_bankmachine4_row_opened) begin - if (main_litedramcore_bankmachine4_row_hit) begin - if (main_litedramcore_bankmachine4_source_source_payload_we) begin - main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end always @(*) begin main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (builder_bankmachine4_state) @@ -8021,6 +7928,82 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (builder_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine4_source_source_valid) begin + if (main_litedramcore_bankmachine4_row_opened) begin + if (main_litedramcore_bankmachine4_row_hit) begin + if (main_litedramcore_bankmachine4_source_source_payload_we) begin + main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end assign main_litedramcore_bankmachine5_sink_valid = main_litedramcore_bankmachine5_req_valid; assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_sink_ready; assign main_litedramcore_bankmachine5_sink_payload_we = main_litedramcore_bankmachine5_req_we; @@ -8105,180 +8088,61 @@ always @(*) begin case (builder_bankmachine5_state) 1'd1: begin if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - if (main_litedramcore_bankmachine5_cmd_ready) begin - builder_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - builder_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - if (main_litedramcore_bankmachine5_cmd_ready) begin - builder_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~main_litedramcore_bankmachine5_refresh_req)) begin - builder_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - builder_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - builder_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - builder_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - builder_bankmachine5_next_state <= 1'd0; - end - default: begin - if (main_litedramcore_bankmachine5_refresh_req) begin - builder_bankmachine5_next_state <= 3'd4; - end else begin - if (main_litedramcore_bankmachine5_source_source_valid) begin - if (main_litedramcore_bankmachine5_row_opened) begin - if (main_litedramcore_bankmachine5_row_hit) begin - if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin - builder_bankmachine5_next_state <= 2'd2; - end - end else begin - builder_bankmachine5_next_state <= 1'd1; - end - end else begin - builder_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (main_litedramcore_bankmachine5_twtpcon_ready) begin - main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_row_open <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end end end 2'd2: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end end 2'd3: begin if (main_litedramcore_bankmachine5_trccon_ready) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (main_litedramcore_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd7; + end end end 3'd4: begin + if ((~main_litedramcore_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end end 3'd5: begin + builder_bankmachine5_next_state <= 3'd6; end 3'd6: begin + builder_bankmachine5_next_state <= 2'd3; end 3'd7: begin + builder_bankmachine5_next_state <= 4'd8; end 4'd8: begin + builder_bankmachine5_next_state <= 1'd0; end default: begin if (main_litedramcore_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; end else begin if (main_litedramcore_bankmachine5_source_source_valid) begin if (main_litedramcore_bankmachine5_row_opened) begin if (main_litedramcore_bankmachine5_row_hit) begin - main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; + end end else begin + builder_bankmachine5_next_state <= 1'd1; end end else begin + builder_bankmachine5_next_state <= 2'd3; end end end end endcase end -always @(*) begin - main_litedramcore_bankmachine5_row_close <= 1'd0; - case (builder_bankmachine5_state) - 1'd1: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - main_litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine5_state) @@ -8592,6 +8456,125 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (main_litedramcore_bankmachine5_twtpcon_ready) begin + main_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_open <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine5_trccon_ready) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (main_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine5_source_source_valid) begin + if (main_litedramcore_bankmachine5_row_opened) begin + if (main_litedramcore_bankmachine5_row_hit) begin + main_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + main_litedramcore_bankmachine5_row_close <= 1'd0; + case (builder_bankmachine5_state) + 1'd1: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + main_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine6_sink_valid = main_litedramcore_bankmachine6_req_valid; assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_sink_ready; assign main_litedramcore_bankmachine6_sink_payload_we = main_litedramcore_bankmachine6_req_we; @@ -8731,32 +8714,6 @@ always @(*) begin end endcase end -always @(*) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (builder_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (main_litedramcore_bankmachine6_trccon_ready) begin - main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end always @(*) begin main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (builder_bankmachine6_state) @@ -9163,6 +9120,32 @@ always @(*) begin end endcase end +always @(*) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (builder_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (main_litedramcore_bankmachine6_trccon_ready) begin + main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end assign main_litedramcore_bankmachine7_sink_valid = main_litedramcore_bankmachine7_req_valid; assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_sink_ready; assign main_litedramcore_bankmachine7_sink_payload_we = main_litedramcore_bankmachine7_req_we; @@ -9303,21 +9286,22 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin + main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9332,12 +9316,9 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -9360,8 +9341,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin + main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9373,22 +9354,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9399,11 +9373,26 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9428,8 +9417,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; end else begin - main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9441,7 +9430,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9466,8 +9455,8 @@ always @(*) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin + main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9479,7 +9468,7 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin end @@ -9488,6 +9477,9 @@ always @(*) begin 2'd3: begin end 3'd4: begin + if (main_litedramcore_bankmachine7_twtpcon_ready) begin + main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9498,32 +9490,23 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_source_source_payload_we) begin - main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + main_litedramcore_bankmachine7_cmd_valid <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (main_litedramcore_bankmachine7_trccon_ready) begin + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9541,10 +9524,7 @@ always @(*) begin if (main_litedramcore_bankmachine7_source_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - if (main_litedramcore_bankmachine7_source_source_payload_we) begin - end else begin - main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready; - end + main_litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin @@ -9555,18 +9535,18 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + main_litedramcore_bankmachine7_row_close <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - if (main_litedramcore_bankmachine7_twtpcon_ready) begin - main_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end + main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9607,18 +9587,15 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd0; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; + main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9632,34 +9609,19 @@ always @(*) begin 4'd8: begin end default: begin - if (main_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (main_litedramcore_bankmachine7_source_source_valid) begin - if (main_litedramcore_bankmachine7_row_opened) begin - if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_close <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - main_litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9670,19 +9632,34 @@ always @(*) begin 4'd8: begin end default: begin + if (main_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (main_litedramcore_bankmachine7_source_source_valid) begin + if (main_litedramcore_bankmachine7_row_opened) begin + if (main_litedramcore_bankmachine7_row_hit) begin + main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase end always @(*) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (main_litedramcore_bankmachine7_trccon_ready) begin - main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9700,9 +9677,12 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (builder_bankmachine7_state) 1'd1: begin + if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9724,7 +9704,10 @@ always @(*) begin if (main_litedramcore_bankmachine7_source_source_valid) begin if (main_litedramcore_bankmachine7_row_opened) begin if (main_litedramcore_bankmachine7_row_hit) begin - main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + if (main_litedramcore_bankmachine7_source_source_payload_we) begin + main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end end else begin end end else begin @@ -10328,10 +10311,14 @@ always @(*) begin endcase end always @(*) begin - main_litedramcore_en1 <= 1'd0; + main_litedramcore_choose_req_cmd_ready <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - main_litedramcore_en1 <= 1'd1; + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end 2'd2: begin end @@ -10352,18 +10339,19 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); + end else begin + main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; + end end endcase end always @(*) begin - main_litedramcore_choose_req_cmd_ready <= 1'd0; + main_litedramcore_en1 <= 1'd0; case (builder_multiplexer_state) 1'd1: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end + main_litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10384,11 +10372,6 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed)); - end else begin - main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed; - end end endcase end @@ -10493,64 +10476,82 @@ always @(*) begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value1 <= builder_interface0_adr[29:0]; + builder_interface1_adr_next_value1 <= builder_interface0_adr; end end endcase end always @(*) begin - builder_interface0_ack <= 1'd0; + builder_interface1_adr_next_value_ce1 <= 1'd0; case (builder_state) 1'd1: begin + builder_interface1_adr_next_value_ce1 <= 1'd1; end 2'd2: begin - builder_interface0_ack <= 1'd1; end default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr_next_value_ce1 <= 1'd1; + end end endcase end always @(*) begin - builder_interface1_adr_next_value_ce1 <= 1'd0; + builder_interface1_re_next_value2 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_adr_next_value_ce1 <= 1'd1; + builder_interface1_re_next_value2 <= ((~builder_interface0_we) & (builder_interface0_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + builder_interface1_re_next_value_ce2 <= 1'd0; + case (builder_state) + 1'd1: begin + builder_interface1_re_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_re_next_value_ce2 <= 1'd1; end end endcase end always @(*) begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_we_next_value3 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value2 <= 1'd0; + builder_interface1_we_next_value3 <= 1'd0; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value2 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_interface1_we_next_value3 <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); end end endcase end always @(*) begin - builder_interface1_we_next_value_ce2 <= 1'd0; + builder_interface1_we_next_value_ce3 <= 1'd0; case (builder_state) 1'd1: begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value_ce3 <= 1'd1; end 2'd2: begin end default: begin if ((builder_interface0_cyc & builder_interface0_stb)) begin - builder_interface1_we_next_value_ce2 <= 1'd1; + builder_interface1_we_next_value_ce3 <= 1'd1; end end endcase @@ -10579,6 +10580,18 @@ always @(*) begin end endcase end +always @(*) begin + builder_interface0_ack <= 1'd0; + case (builder_state) + 1'd1: begin + end + 2'd2: begin + builder_interface0_ack <= 1'd1; + end + default: begin + end + endcase +end always @(*) begin builder_interface1_dat_w_next_value_ce0 <= 1'd0; case (builder_state) @@ -10596,7 +10609,7 @@ assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin builder_csrbank0_init_done0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_done0_we <= builder_interface0_bank_bus_re; end end always @(*) begin @@ -10607,15 +10620,15 @@ always @(*) begin end assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank0_init_error0_we <= 1'd0; + builder_csrbank0_init_error0_re <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we); + builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; end end always @(*) begin - builder_csrbank0_init_error0_re <= 1'd0; + builder_csrbank0_init_error0_we <= 1'd0; if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_init_error0_we <= builder_interface0_bank_bus_re; end end assign builder_csrbank0_init_done0_w = main_init_done_storage; @@ -10623,41 +10636,41 @@ assign builder_csrbank0_init_error0_w = main_init_error_storage; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_rst0_we <= 1'd0; + builder_csrbank1_rst0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_rst0_re <= 1'd0; + builder_csrbank1_rst0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rst0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_dly_sel0_re <= 1'd0; + builder_csrbank1_dly_sel0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_dly_sel0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_dly_sel0_we <= 1'd0; + builder_csrbank1_dly_sel0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0]; always @(*) begin - builder_csrbank1_half_sys8x_taps0_we <= 1'd0; + builder_csrbank1_half_sys8x_taps0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_half_sys8x_taps0_re <= 1'd0; + builder_csrbank1_half_sys8x_taps0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_half_sys8x_taps0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0]; @@ -10670,53 +10683,53 @@ end always @(*) begin builder_csrbank1_wlevel_en0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wlevel_en0_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wlevel_strobe_re <= 1'd0; + main_a7ddrphy_wlevel_strobe_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wlevel_strobe_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_wlevel_strobe_we <= 1'd0; + main_a7ddrphy_wlevel_strobe_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_rst_re <= 1'd0; + main_a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_rst_we <= 1'd0; + main_a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_inc_re <= 1'd0; + main_a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_inc_we <= builder_interface1_bank_bus_re; end end always @(*) begin - main_a7ddrphy_rdly_dq_inc_we <= 1'd0; + main_a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we; end end assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end always @(*) begin @@ -10727,75 +10740,75 @@ always @(*) begin end assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_rdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_rst_we <= builder_interface1_bank_bus_re; end end assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we); + main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; end end always @(*) begin - main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we; + main_a7ddrphy_wdly_dq_bitslip_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_rdphase0_re <= 1'd0; + builder_csrbank1_rdphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rdphase0_we <= builder_interface1_bank_bus_re; end end always @(*) begin - builder_csrbank1_rdphase0_we <= 1'd0; + builder_csrbank1_rdphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we; end end assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_wrphase0_we <= 1'd0; + builder_csrbank1_wrphase0_re <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we); + builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; end end always @(*) begin - builder_csrbank1_wrphase0_re <= 1'd0; + builder_csrbank1_wrphase0_we <= 1'd0; if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_wrphase0_we <= builder_interface1_bank_bus_re; end end assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage; -assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; -assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage; +assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage; assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage; -assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0]; -assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0]; +assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage; +assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0]; always @(*) begin @@ -10807,14 +10820,14 @@ end always @(*) begin builder_csrbank2_dfii_control0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_control0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi0_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10825,15 +10838,15 @@ always @(*) begin end assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector0_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[13:0]; @@ -10846,14 +10859,14 @@ end always @(*) begin builder_csrbank2_dfii_pi0_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10862,11 +10875,11 @@ always @(*) begin builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10875,7 +10888,7 @@ always @(*) begin builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi0_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi0_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin @@ -10885,14 +10898,14 @@ end always @(*) begin builder_csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin - builder_csrbank2_dfii_pi0_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi0_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[7:0]; always @(*) begin builder_csrbank2_dfii_pi1_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_command0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10903,22 +10916,22 @@ always @(*) begin end assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector1_command_issue_we <= builder_interface2_bank_bus_re; end end always @(*) begin - main_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin - main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we; end end assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin builder_csrbank2_dfii_pi1_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10937,14 +10950,14 @@ end always @(*) begin builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_wrdata0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -10953,7 +10966,7 @@ always @(*) begin builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi1_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi1_rddata_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin @@ -10963,7 +10976,7 @@ end always @(*) begin builder_csrbank2_dfii_pi1_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank2_dfii_pi1_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi1_rddata_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[7:0]; @@ -10976,27 +10989,27 @@ end always @(*) begin builder_csrbank2_dfii_pi2_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; end end always @(*) begin - main_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + main_litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin - main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we; + main_litedramcore_phaseinjector2_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[13:0]; always @(*) begin builder_csrbank2_dfii_pi2_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_address0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11015,10 +11028,10 @@ end always @(*) begin builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_baddress0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin @@ -11028,14 +11041,14 @@ end always @(*) begin builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin - builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi2_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi2_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin - builder_csrbank2_dfii_pi2_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi2_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11054,7 +11067,7 @@ end always @(*) begin builder_csrbank2_dfii_pi3_command0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin - builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_command0_we <= builder_interface2_bank_bus_re; end end assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0]; @@ -11067,7 +11080,7 @@ end always @(*) begin main_litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin - main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we); + main_litedramcore_phaseinjector3_command_issue_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[13:0]; @@ -11080,14 +11093,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_address0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin - builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_address0_we <= builder_interface2_bank_bus_re; end end assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin - builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_baddress0_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11096,7 +11109,7 @@ always @(*) begin builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we; end end -assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin @@ -11106,14 +11119,14 @@ end always @(*) begin builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin - builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_wrdata0_we <= builder_interface2_bank_bus_re; end end -assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w[31:0]; +assign builder_csrbank2_dfii_pi3_rddata_r = builder_interface2_bank_bus_dat_w; always @(*) begin builder_csrbank2_dfii_pi3_rddata_we <= 1'd0; if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin - builder_csrbank2_dfii_pi3_rddata_we <= (~builder_interface2_bank_bus_we); + builder_csrbank2_dfii_pi3_rddata_we <= builder_interface2_bank_bus_re; end end always @(*) begin @@ -11126,7 +11139,7 @@ assign main_litedramcore_sel = main_litedramcore_storage[0]; assign main_litedramcore_cke = main_litedramcore_storage[1]; assign main_litedramcore_odt = main_litedramcore_storage[2]; assign main_litedramcore_reset_n = main_litedramcore_storage[3]; -assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0]; +assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage; assign main_litedramcore_phaseinjector0_csrfield_cs = main_litedramcore_phaseinjector0_command_storage[0]; assign main_litedramcore_phaseinjector0_csrfield_we = main_litedramcore_phaseinjector0_command_storage[1]; assign main_litedramcore_phaseinjector0_csrfield_cas = main_litedramcore_phaseinjector0_command_storage[2]; @@ -11135,11 +11148,11 @@ assign main_litedramcore_phaseinjector0_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector0_csrfield_rden = main_litedramcore_phaseinjector0_command_storage[5]; assign main_litedramcore_phaseinjector0_csrfield_cs_top = main_litedramcore_phaseinjector0_command_storage[6]; assign main_litedramcore_phaseinjector0_csrfield_cs_bottom = main_litedramcore_phaseinjector0_command_storage[7]; -assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[7:0]; -assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[13:0]; -assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage; +assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage; +assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage; +assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage; +assign builder_csrbank2_dfii_pi0_rddata_w = main_litedramcore_phaseinjector0_rddata_status; assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata_we; assign main_litedramcore_phaseinjector1_csrfield_cs = main_litedramcore_phaseinjector1_command_storage[0]; assign main_litedramcore_phaseinjector1_csrfield_we = main_litedramcore_phaseinjector1_command_storage[1]; @@ -11149,11 +11162,11 @@ assign main_litedramcore_phaseinjector1_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector1_csrfield_rden = main_litedramcore_phaseinjector1_command_storage[5]; assign main_litedramcore_phaseinjector1_csrfield_cs_top = main_litedramcore_phaseinjector1_command_storage[6]; assign main_litedramcore_phaseinjector1_csrfield_cs_bottom = main_litedramcore_phaseinjector1_command_storage[7]; -assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[7:0]; -assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[13:0]; -assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage; +assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage; +assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage; +assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage; +assign builder_csrbank2_dfii_pi1_rddata_w = main_litedramcore_phaseinjector1_rddata_status; assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata_we; assign main_litedramcore_phaseinjector2_csrfield_cs = main_litedramcore_phaseinjector2_command_storage[0]; assign main_litedramcore_phaseinjector2_csrfield_we = main_litedramcore_phaseinjector2_command_storage[1]; @@ -11163,11 +11176,11 @@ assign main_litedramcore_phaseinjector2_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector2_csrfield_rden = main_litedramcore_phaseinjector2_command_storage[5]; assign main_litedramcore_phaseinjector2_csrfield_cs_top = main_litedramcore_phaseinjector2_command_storage[6]; assign main_litedramcore_phaseinjector2_csrfield_cs_bottom = main_litedramcore_phaseinjector2_command_storage[7]; -assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[7:0]; -assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[13:0]; -assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage; +assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage; +assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage; +assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage; +assign builder_csrbank2_dfii_pi2_rddata_w = main_litedramcore_phaseinjector2_rddata_status; assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata_we; assign main_litedramcore_phaseinjector3_csrfield_cs = main_litedramcore_phaseinjector3_command_storage[0]; assign main_litedramcore_phaseinjector3_csrfield_we = main_litedramcore_phaseinjector3_command_storage[1]; @@ -11177,19 +11190,23 @@ assign main_litedramcore_phaseinjector3_csrfield_wren = main_litedramcore_phasei assign main_litedramcore_phaseinjector3_csrfield_rden = main_litedramcore_phaseinjector3_command_storage[5]; assign main_litedramcore_phaseinjector3_csrfield_cs_top = main_litedramcore_phaseinjector3_command_storage[6]; assign main_litedramcore_phaseinjector3_csrfield_cs_bottom = main_litedramcore_phaseinjector3_command_storage[7]; -assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[7:0]; -assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[13:0]; -assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0]; -assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[31:0]; -assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status[31:0]; +assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage; +assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage; +assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage; +assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage; +assign builder_csrbank2_dfii_pi3_rddata_w = main_litedramcore_phaseinjector3_rddata_status; assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata_we; assign builder_adr = builder_interface1_adr; +assign builder_re = builder_interface1_re; assign builder_we = builder_interface1_we; assign builder_dat_w = builder_interface1_dat_w; assign builder_interface1_dat_r = builder_dat_r; assign builder_interface0_bank_bus_adr = builder_adr; assign builder_interface1_bank_bus_adr = builder_adr; assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_re = builder_re; +assign builder_interface1_bank_bus_re = builder_re; +assign builder_interface2_bank_bus_re = builder_re; assign builder_interface0_bank_bus_we = builder_we; assign builder_interface1_bank_bus_we = builder_we; assign builder_interface2_bank_bus_we = builder_we; @@ -11915,16 +11932,16 @@ always @(*) begin builder_self0 <= 3'd0; case (main_litedramcore_steerer0) 1'd0: begin - builder_self0 <= main_litedramcore_nop_ba[2:0]; + builder_self0 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self0 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self0 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12034,16 +12051,16 @@ always @(*) begin builder_self7 <= 3'd0; case (main_litedramcore_steerer1) 1'd0: begin - builder_self7 <= main_litedramcore_nop_ba[2:0]; + builder_self7 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self7 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self7 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12153,16 +12170,16 @@ always @(*) begin builder_self14 <= 3'd0; case (main_litedramcore_steerer2) 1'd0: begin - builder_self14 <= main_litedramcore_nop_ba[2:0]; + builder_self14 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self14 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self14 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12272,16 +12289,16 @@ always @(*) begin builder_self21 <= 3'd0; case (main_litedramcore_steerer3) 1'd0: begin - builder_self21 <= main_litedramcore_nop_ba[2:0]; + builder_self21 <= main_litedramcore_nop_ba; end 1'd1: begin - builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_cmd_cmd_payload_ba; end 2'd2: begin - builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_choose_req_cmd_payload_ba; end default: begin - builder_self21 <= main_litedramcore_cmd_payload_ba[2:0]; + builder_self21 <= main_litedramcore_cmd_payload_ba; end endcase end @@ -12387,10 +12404,10 @@ always @(*) begin end endcase end -assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl1_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl2_async_reset = (~main_locked); -assign builder_xilinxasyncresetsynchronizerimpl3_async_reset = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked); +assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked); //------------------------------------------------------------------------------ @@ -13989,8 +14006,11 @@ always @(posedge sys_clk) begin if (builder_interface1_adr_next_value_ce1) begin builder_interface1_adr <= builder_interface1_adr_next_value1; end - if (builder_interface1_we_next_value_ce2) begin - builder_interface1_we <= builder_interface1_we_next_value2; + if (builder_interface1_re_next_value_ce2) begin + builder_interface1_re <= builder_interface1_re_next_value2; + end + if (builder_interface1_we_next_value_ce3) begin + builder_interface1_we <= builder_interface1_we_next_value3; end builder_interface0_bank_bus_dat_r <= 1'd0; if (builder_csrbank0_sel) begin @@ -14060,11 +14080,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re; if (builder_csrbank1_dly_sel0_re) begin - main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r; + main_a7ddrphy_dly_sel_storage <= builder_csrbank1_dly_sel0_r; end main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re; if (builder_csrbank1_half_sys8x_taps0_re) begin - main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r; + main_a7ddrphy_half_sys8x_taps_storage <= builder_csrbank1_half_sys8x_taps0_r; end main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re; if (builder_csrbank1_wlevel_en0_re) begin @@ -14072,11 +14092,11 @@ always @(posedge sys_clk) begin end main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re; if (builder_csrbank1_rdphase0_re) begin - main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r; + main_a7ddrphy_rdphase_storage <= builder_csrbank1_rdphase0_r; end main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re; if (builder_csrbank1_wrphase0_re) begin - main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r; + main_a7ddrphy_wrphase_storage <= builder_csrbank1_wrphase0_r; end main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re; builder_interface2_bank_bus_dat_r <= 1'd0; @@ -14160,74 +14180,74 @@ always @(posedge sys_clk) begin endcase end if (builder_csrbank2_dfii_control0_re) begin - main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r; + main_litedramcore_storage <= builder_csrbank2_dfii_control0_r; end main_litedramcore_re <= builder_csrbank2_dfii_control0_re; if (builder_csrbank2_dfii_pi0_command0_re) begin - main_litedramcore_phaseinjector0_command_storage[7:0] <= builder_csrbank2_dfii_pi0_command0_r; + main_litedramcore_phaseinjector0_command_storage <= builder_csrbank2_dfii_pi0_command0_r; end main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re; if (builder_csrbank2_dfii_pi0_address0_re) begin - main_litedramcore_phaseinjector0_address_storage[13:0] <= builder_csrbank2_dfii_pi0_address0_r; + main_litedramcore_phaseinjector0_address_storage <= builder_csrbank2_dfii_pi0_address0_r; end main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re; if (builder_csrbank2_dfii_pi0_baddress0_re) begin - main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r; + main_litedramcore_phaseinjector0_baddress_storage <= builder_csrbank2_dfii_pi0_baddress0_r; end main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re; if (builder_csrbank2_dfii_pi0_wrdata0_re) begin - main_litedramcore_phaseinjector0_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi0_wrdata0_r; + main_litedramcore_phaseinjector0_wrdata_storage <= builder_csrbank2_dfii_pi0_wrdata0_r; end main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re; main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata_re; if (builder_csrbank2_dfii_pi1_command0_re) begin - main_litedramcore_phaseinjector1_command_storage[7:0] <= builder_csrbank2_dfii_pi1_command0_r; + main_litedramcore_phaseinjector1_command_storage <= builder_csrbank2_dfii_pi1_command0_r; end main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re; if (builder_csrbank2_dfii_pi1_address0_re) begin - main_litedramcore_phaseinjector1_address_storage[13:0] <= builder_csrbank2_dfii_pi1_address0_r; + main_litedramcore_phaseinjector1_address_storage <= builder_csrbank2_dfii_pi1_address0_r; end main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re; if (builder_csrbank2_dfii_pi1_baddress0_re) begin - main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r; + main_litedramcore_phaseinjector1_baddress_storage <= builder_csrbank2_dfii_pi1_baddress0_r; end main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re; if (builder_csrbank2_dfii_pi1_wrdata0_re) begin - main_litedramcore_phaseinjector1_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi1_wrdata0_r; + main_litedramcore_phaseinjector1_wrdata_storage <= builder_csrbank2_dfii_pi1_wrdata0_r; end main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re; main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata_re; if (builder_csrbank2_dfii_pi2_command0_re) begin - main_litedramcore_phaseinjector2_command_storage[7:0] <= builder_csrbank2_dfii_pi2_command0_r; + main_litedramcore_phaseinjector2_command_storage <= builder_csrbank2_dfii_pi2_command0_r; end main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re; if (builder_csrbank2_dfii_pi2_address0_re) begin - main_litedramcore_phaseinjector2_address_storage[13:0] <= builder_csrbank2_dfii_pi2_address0_r; + main_litedramcore_phaseinjector2_address_storage <= builder_csrbank2_dfii_pi2_address0_r; end main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re; if (builder_csrbank2_dfii_pi2_baddress0_re) begin - main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r; + main_litedramcore_phaseinjector2_baddress_storage <= builder_csrbank2_dfii_pi2_baddress0_r; end main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re; if (builder_csrbank2_dfii_pi2_wrdata0_re) begin - main_litedramcore_phaseinjector2_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi2_wrdata0_r; + main_litedramcore_phaseinjector2_wrdata_storage <= builder_csrbank2_dfii_pi2_wrdata0_r; end main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re; main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata_re; if (builder_csrbank2_dfii_pi3_command0_re) begin - main_litedramcore_phaseinjector3_command_storage[7:0] <= builder_csrbank2_dfii_pi3_command0_r; + main_litedramcore_phaseinjector3_command_storage <= builder_csrbank2_dfii_pi3_command0_r; end main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re; if (builder_csrbank2_dfii_pi3_address0_re) begin - main_litedramcore_phaseinjector3_address_storage[13:0] <= builder_csrbank2_dfii_pi3_address0_r; + main_litedramcore_phaseinjector3_address_storage <= builder_csrbank2_dfii_pi3_address0_r; end main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re; if (builder_csrbank2_dfii_pi3_baddress0_re) begin - main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r; + main_litedramcore_phaseinjector3_baddress_storage <= builder_csrbank2_dfii_pi3_baddress0_r; end main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re; if (builder_csrbank2_dfii_pi3_wrdata0_re) begin - main_litedramcore_phaseinjector3_wrdata_storage[31:0] <= builder_csrbank2_dfii_pi3_wrdata0_r; + main_litedramcore_phaseinjector3_wrdata_storage <= builder_csrbank2_dfii_pi3_wrdata0_r; end main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re; main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata_re; @@ -14500,6 +14520,7 @@ always @(posedge sys_clk) begin main_init_done_re <= 1'd0; main_init_error_storage <= 1'd0; main_init_error_re <= 1'd0; + builder_interface1_re <= 1'd0; builder_interface1_we <= 1'd0; builder_refresher_state <= 2'd0; builder_bankmachine0_state <= 4'd0; @@ -17453,7 +17474,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) @@ -17471,7 +17492,7 @@ FDPE #( .C (iodelay_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl0), // Outputs. .Q (iodelay_rst) @@ -17489,7 +17510,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) @@ -17507,7 +17528,7 @@ FDPE #( .C (sys_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl1_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl1), // Outputs. .Q (sys_rst) @@ -17525,7 +17546,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) @@ -17543,7 +17564,7 @@ FDPE #( .C (sys4x_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl2_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl2), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl2_expr) @@ -17561,7 +17582,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (1'd0), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_rst_meta) @@ -17579,7 +17600,7 @@ FDPE #( .C (sys4x_dqs_clk), .CE (1'd1), .D (builder_xilinxasyncresetsynchronizerimpl3_rst_meta), - .PRE (builder_xilinxasyncresetsynchronizerimpl3_async_reset), + .PRE (builder_xilinxasyncresetsynchronizerimpl3), // Outputs. .Q (builder_xilinxasyncresetsynchronizerimpl3_expr) @@ -17588,5 +17609,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-01 10:12:10. +// Auto-Generated by LiteX on 2025-02-15 19:54:47. //------------------------------------------------------------------------------ From 3e0888ae3524daeb3668d930a1877728750247fa Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 17 Feb 2025 09:52:07 +1100 Subject: [PATCH 3/3] litesdcard: Update generated code Signed-off-by: Paul Mackerras --- .../generated/lattice.48e6/litesdcard_core.v | 487 ++++++++++-------- .../generated/lattice.50e6/litesdcard_core.v | 487 ++++++++++-------- .../generated/xilinx.100e6/litesdcard_core.v | 401 +++++++------- 3 files changed, 775 insertions(+), 600 deletions(-) diff --git a/litesdcard/generated/lattice.48e6/litesdcard_core.v b/litesdcard/generated/lattice.48e6/litesdcard_core.v index 1fa5b17..a0b70b3 100644 --- a/litesdcard/generated/lattice.48e6/litesdcard_core.v +++ b/litesdcard/generated/lattice.48e6/litesdcard_core.v @@ -8,8 +8,8 @@ // // Filename : litesdcard_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-03 20:02:06 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-17 09:51:44 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -179,20 +179,25 @@ LiteSDCardCore │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstatus_1* (CSRStatus) └─── csr_interconnect (InterconnectShared) -└─── [IFS1P3BX] +└─── [BB] └─── [OFS1P3BX] -└─── [IFS1P3BX] +└─── [BB] └─── [OFS1P3BX] -└─── [IFS1P3BX] -└─── [IFS1P3BX] └─── [OFS1P3BX] └─── [IFS1P3BX] └─── [OFS1P3BX] └─── [OFS1P3BX] └─── [OFS1P3BX] └─── [OFS1P3BX] +└─── [BB] └─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [BB] +└─── [IFS1P3BX] +└─── [IFS1P3BX] └─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [BB] * : Generated name. []: BlackBox. */ @@ -220,15 +225,16 @@ wire card_detect_status0; wire card_detect_status1; wire card_detect_trigger; wire card_detect_we; +wire clk_i; +reg clk_i_d = 1'd0; wire clocker_ce; reg clocker_ce_delayed = 1'd0; reg clocker_ce_latched = 1'd0; wire clocker_clk0; reg clocker_clk1 = 1'd0; reg clocker_clk_d = 1'd0; -reg [1:0] clocker_clk_delay = 2'd0; wire clocker_clk_en; -reg [8:0] clocker_clks = 9'd0; +reg [9:0] clocker_count = 10'd0; reg clocker_re = 1'd0; wire clocker_stop; reg [8:0] clocker_storage = 9'd256; @@ -760,6 +766,7 @@ wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire interface0_bus_ack; @@ -785,6 +792,7 @@ reg [13:0] interface1_adr = 14'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire interface1_bus_ack; wire [31:0] interface1_bus_adr; @@ -799,28 +807,36 @@ wire interface1_bus_stb; wire interface1_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; reg interface1_we = 1'd0; wire [13:0] interface2_bank_bus_adr; reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; wire interface2_bank_bus_we; wire [13:0] interface3_bank_bus_adr; reg [31:0] interface3_bank_bus_dat_r = 32'd0; wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_re; wire interface3_bank_bus_we; wire [13:0] interface4_bank_bus_adr; reg [31:0] interface4_bank_bus_dat_r = 32'd0; wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_re; wire interface4_bank_bus_we; wire [13:0] interface5_bank_bus_adr; reg [31:0] interface5_bank_bus_dat_r = 32'd0; wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_re; wire interface5_bank_bus_we; reg mem2block_dma_clear = 1'd0; reg mem2block_dma_pending = 1'd0; wire mem2block_dma_status; wire mem2block_dma_trigger; +(* syn_no_retiming = "true" *) +reg multiregimpl = 1'd0; wire por_clk; +wire re; wire [1:0] request; reg reset_re = 1'd0; reg [1:0] reset_storage = 2'd0; @@ -898,23 +914,29 @@ wire [31:0] sdcard_block2mem_source_source_payload_data; wire sdcard_block2mem_source_source_ready; wire sdcard_block2mem_source_source_valid; wire sdcard_block2mem_start; -wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +wire [63:0] sdcard_block2mem_wishbonedmawriter_base0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base1; reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done = 1'd0; reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; -reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_status; wire sdcard_block2mem_wishbonedmawriter_done_we; +wire sdcard_block2mem_wishbonedmawriter_enable; reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; -wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length1; reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +wire sdcard_block2mem_wishbonedmawriter_loop; reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; -reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset1 = 32'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce = 1'd0; reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; -reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; -reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; wire sdcard_block2mem_wishbonedmawriter_offset_we; wire sdcard_block2mem_wishbonedmawriter_reset; @@ -1145,12 +1167,15 @@ wire [7:0] sdcard_mem2block_converter_source_source_payload_data; wire sdcard_mem2block_converter_source_source_ready; wire sdcard_mem2block_converter_source_source_valid; reg [8:0] sdcard_mem2block_count = 9'd0; -wire [31:0] sdcard_mem2block_dma_base; +wire [63:0] sdcard_mem2block_dma_base0; +wire [31:0] sdcard_mem2block_dma_base1; reg sdcard_mem2block_dma_base_re = 1'd0; reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done = 1'd0; reg sdcard_mem2block_dma_done_re = 1'd0; -reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_status; wire sdcard_mem2block_dma_done_we; +wire sdcard_mem2block_dma_enable; reg sdcard_mem2block_dma_enable_re = 1'd0; reg sdcard_mem2block_dma_enable_storage = 1'd0; reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; @@ -1186,15 +1211,18 @@ reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; wire sdcard_mem2block_dma_fifo_wrport_we; -wire [31:0] sdcard_mem2block_dma_length; +wire [31:0] sdcard_mem2block_dma_length0; +wire [31:0] sdcard_mem2block_dma_length1; reg sdcard_mem2block_dma_length_re = 1'd0; reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +wire sdcard_mem2block_dma_loop; reg sdcard_mem2block_dma_loop_re = 1'd0; reg sdcard_mem2block_dma_loop_storage = 1'd0; -reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +wire [31:0] sdcard_mem2block_dma_offset0; +reg [31:0] sdcard_mem2block_dma_offset1 = 32'd0; +reg [31:0] sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce = 1'd0; reg sdcard_mem2block_dma_offset_re = 1'd0; -reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; -reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; wire [31:0] sdcard_mem2block_dma_offset_status; wire sdcard_mem2block_dma_offset_we; wire sdcard_mem2block_dma_reset; @@ -1258,7 +1286,7 @@ wire sdpads_cmd_i; wire sdpads_cmd_o; wire sdpads_cmd_oe; wire [3:0] sdpads_data_i; -reg sdpads_data_i_ce = 1'd0; +wire sdpads_data_i_ce; wire [3:0] sdpads_data_o; wire sdpads_data_oe; reg [2:0] sdphycmdr_next_state = 3'd0; @@ -1295,7 +1323,7 @@ wire shared_err; wire [3:0] shared_sel; wire shared_stb; wire shared_we; -reg slave_sel = 1'd0; +wire slave_sel; reg slave_sel_r = 1'd0; reg soc_rst = 1'd0; wire sys_clk; @@ -1398,10 +1426,7 @@ assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); assign interface0_bus_err = (shared_err & (grant == 1'd0)); assign interface1_bus_err = (shared_err & (grant == 1'd1)); assign request = {interface1_bus_cyc, interface0_bus_cyc}; -always @(*) begin - slave_sel <= 1'd0; - slave_sel <= 1'd1; -end +assign slave_sel = 1'd1; assign wb_dma_adr_1 = shared_adr; assign wb_dma_dat_w_1 = shared_dat_w; assign wb_dma_sel_1 = shared_sel; @@ -1453,35 +1478,6 @@ assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; assign clocker_stop = (dataw_stop | datar_stop); -always @(*) begin - clocker_clk1 <= 1'd0; - case (clocker_storage) - 3'd4: begin - clocker_clk1 <= clocker_clks[1]; - end - 4'd8: begin - clocker_clk1 <= clocker_clks[2]; - end - 5'd16: begin - clocker_clk1 <= clocker_clks[3]; - end - 6'd32: begin - clocker_clk1 <= clocker_clks[4]; - end - 7'd64: begin - clocker_clk1 <= clocker_clks[5]; - end - 8'd128: begin - clocker_clk1 <= clocker_clks[6]; - end - 9'd256: begin - clocker_clk1 <= clocker_clks[7]; - end - default: begin - clocker_clk1 <= clocker_clks[0]; - end - endcase -end assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); always @(*) begin clocker_ce_latched <= 1'd0; @@ -1943,9 +1939,9 @@ assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; -assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_start = (datar_datar_pads_in_payload_data_i == 1'd0); assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); -assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i; assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; @@ -2077,6 +2073,7 @@ always @(*) begin end endcase end +assign sdpads_data_i_ce = (clk_i & (~clk_i_d)); assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; @@ -2636,35 +2633,41 @@ assign interface0_bus_sel = 4'd15; assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; -assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; -assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; -assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; -assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +assign sdcard_block2mem_wishbonedmawriter_base1 = sdcard_block2mem_wishbonedmawriter_base0[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length1 = sdcard_block2mem_wishbonedmawriter_length0[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset0 = sdcard_block2mem_wishbonedmawriter_offset1; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable); +assign sdcard_block2mem_wishbonedmawriter_base0 = sdcard_block2mem_wishbonedmawriter_base_storage; +assign sdcard_block2mem_wishbonedmawriter_length0 = sdcard_block2mem_wishbonedmawriter_length_storage; +assign sdcard_block2mem_wishbonedmawriter_enable = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign sdcard_block2mem_wishbonedmawriter_loop = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign sdcard_block2mem_wishbonedmawriter_done_status = sdcard_block2mem_wishbonedmawriter_done; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset0; always @(*) begin sdblock2memdma_next_state <= 2'd0; sdcard_block2mem_sink_sink_last1 <= 1'd0; sdcard_block2mem_sink_sink_payload_address <= 32'd0; sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; sdcard_block2mem_sink_sink_valid1 <= 1'd0; - sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd0; sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; sdblock2memdma_next_state <= sdblock2memdma_state; case (sdblock2memdma_state) 1'd1: begin sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; - sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); - sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset1 + 1'd1) == sdcard_block2mem_wishbonedmawriter_length1)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base1 + sdcard_block2mem_wishbonedmawriter_offset1); sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset1 + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; if (sdcard_block2mem_sink_sink_last1) begin - if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_wishbonedmawriter_loop) begin + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; end else begin sdblock2memdma_next_state <= 2'd2; end @@ -2672,12 +2675,12 @@ always @(*) begin end end 2'd2: begin - sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + sdcard_block2mem_wishbonedmawriter_done <= 1'd1; end default: begin sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; sdblock2memdma_next_state <= 1'd1; end endcase @@ -2723,10 +2726,16 @@ assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_sour assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; -assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; -assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; -assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; -assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_base1 = sdcard_mem2block_dma_base0[63:2]; +assign sdcard_mem2block_dma_length1 = sdcard_mem2block_dma_length0[31:2]; +assign sdcard_mem2block_dma_offset0 = sdcard_mem2block_dma_offset1; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable); +assign sdcard_mem2block_dma_base0 = sdcard_mem2block_dma_base_storage; +assign sdcard_mem2block_dma_length0 = sdcard_mem2block_dma_length_storage; +assign sdcard_mem2block_dma_enable = sdcard_mem2block_dma_enable_storage; +assign sdcard_mem2block_dma_loop = sdcard_mem2block_dma_loop_storage; +assign sdcard_mem2block_dma_done_status = sdcard_mem2block_dma_done; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset0; assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; @@ -2755,9 +2764,9 @@ assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdpor assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); always @(*) begin - sdcard_mem2block_dma_done_status <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_done <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd0; sdcard_mem2block_dma_sink_sink_last <= 1'd0; sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; sdcard_mem2block_dma_sink_sink_valid <= 1'd0; @@ -2766,15 +2775,15 @@ always @(*) begin case (sdmem2blockdma_state) 1'd1: begin sdcard_mem2block_dma_sink_sink_valid <= 1'd1; - sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); - sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset1 == (sdcard_mem2block_dma_length1 - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base1 + sdcard_mem2block_dma_offset1); if (sdcard_mem2block_dma_sink_sink_ready) begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset1 + 1'd1); + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; if (sdcard_mem2block_dma_sink_sink_last) begin - if (sdcard_mem2block_dma_loop_storage) begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_loop) begin + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; end else begin sdmem2blockdma_next_state <= 2'd2; end @@ -2782,11 +2791,11 @@ always @(*) begin end end 2'd2: begin - sdcard_mem2block_dma_done_status <= 1'd1; + sdcard_mem2block_dma_done <= 1'd1; end default: begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; sdmem2blockdma_next_state <= 1'd1; end endcase @@ -2893,6 +2902,7 @@ always @(*) begin interface0_dat_r <= 32'd0; interface1_adr <= 14'd0; interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; interface1_we <= 1'd0; wishbone2csr_next_state <= 1'd0; wishbone2csr_next_state <= wishbone2csr_state; @@ -2905,7 +2915,8 @@ always @(*) begin default: begin interface1_dat_w <= interface0_dat_w; if ((interface0_cyc & interface0_stb)) begin - interface1_adr <= interface0_adr[29:0]; + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); interface1_we <= (interface0_we & (interface0_sel != 1'd0)); wishbone2csr_next_state <= 1'd1; end @@ -2919,25 +2930,25 @@ always @(*) begin csrbank0_reset0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin csrbank0_reset0_re <= interface0_bank_bus_we; - csrbank0_reset0_we <= (~interface0_bank_bus_we); + csrbank0_reset0_we <= interface0_bank_bus_re; end end -assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_scratch0_re <= 1'd0; csrbank0_scratch0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin csrbank0_scratch0_re <= interface0_bank_bus_we; - csrbank0_scratch0_we <= (~interface0_bank_bus_we); + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_bus_errors_re <= 1'd0; csrbank0_bus_errors_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin csrbank0_bus_errors_re <= interface0_bank_bus_we; - csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin @@ -2947,36 +2958,36 @@ always @(*) begin end end assign cpu_rst = reset_storage[1]; -assign csrbank0_reset0_w = reset_storage[1:0]; -assign csrbank0_scratch0_w = scratch_storage[31:0]; -assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign csrbank0_reset0_w = reset_storage; +assign csrbank0_scratch0_w = scratch_storage; +assign csrbank0_bus_errors_w = bus_errors_status; assign bus_errors_we = csrbank0_bus_errors_we; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_base1_re <= 1'd0; csrbank1_dma_base1_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin csrbank1_dma_base1_re <= interface1_bank_bus_we; - csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + csrbank1_dma_base1_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_base0_re <= 1'd0; csrbank1_dma_base0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin csrbank1_dma_base0_re <= interface1_bank_bus_we; - csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + csrbank1_dma_base0_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_length0_re <= 1'd0; csrbank1_dma_length0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin csrbank1_dma_length0_re <= interface1_bank_bus_we; - csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + csrbank1_dma_length0_we <= interface1_bank_bus_re; end end assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; @@ -2985,7 +2996,7 @@ always @(*) begin csrbank1_dma_enable0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin csrbank1_dma_enable0_re <= interface1_bank_bus_we; - csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + csrbank1_dma_enable0_we <= interface1_bank_bus_re; end end assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; @@ -2994,7 +3005,7 @@ always @(*) begin csrbank1_dma_done_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin csrbank1_dma_done_re <= interface1_bank_bus_we; - csrbank1_dma_done_we <= (~interface1_bank_bus_we); + csrbank1_dma_done_we <= interface1_bank_bus_re; end end assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; @@ -3003,35 +3014,35 @@ always @(*) begin csrbank1_dma_loop0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin csrbank1_dma_loop0_re <= interface1_bank_bus_we; - csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + csrbank1_dma_loop0_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_offset_re <= 1'd0; csrbank1_dma_offset_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin csrbank1_dma_offset_re <= interface1_bank_bus_we; - csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + csrbank1_dma_offset_we <= interface1_bank_bus_re; end end assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; -assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage; assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; -assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status; assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_argument0_re <= 1'd0; csrbank2_cmd_argument0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin csrbank2_cmd_argument0_re <= interface2_bank_bus_we; - csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_argument0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; @@ -3040,7 +3051,7 @@ always @(*) begin csrbank2_cmd_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin csrbank2_cmd_command0_re <= interface2_bank_bus_we; - csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_command0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; @@ -3049,43 +3060,43 @@ always @(*) begin csrbank2_cmd_send0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin csrbank2_cmd_send0_re <= interface2_bank_bus_we; - csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_send0_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response3_re <= 1'd0; csrbank2_cmd_response3_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin csrbank2_cmd_response3_re <= interface2_bank_bus_we; - csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response3_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response2_re <= 1'd0; csrbank2_cmd_response2_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin csrbank2_cmd_response2_re <= interface2_bank_bus_we; - csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response2_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response1_re <= 1'd0; csrbank2_cmd_response1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin csrbank2_cmd_response1_re <= interface2_bank_bus_we; - csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response1_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response0_re <= 1'd0; csrbank2_cmd_response0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin csrbank2_cmd_response0_re <= interface2_bank_bus_we; - csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; @@ -3094,7 +3105,7 @@ always @(*) begin csrbank2_cmd_event_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin csrbank2_cmd_event_re <= interface2_bank_bus_we; - csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + csrbank2_cmd_event_we <= interface2_bank_bus_re; end end assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; @@ -3103,7 +3114,7 @@ always @(*) begin csrbank2_data_event_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin csrbank2_data_event_re <= interface2_bank_bus_we; - csrbank2_data_event_we <= (~interface2_bank_bus_we); + csrbank2_data_event_we <= interface2_bank_bus_re; end end assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; @@ -3112,23 +3123,23 @@ always @(*) begin csrbank2_block_length0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin csrbank2_block_length0_re <= interface2_bank_bus_we; - csrbank2_block_length0_we <= (~interface2_bank_bus_we); + csrbank2_block_length0_we <= interface2_bank_bus_re; end end -assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_block_count0_re <= 1'd0; csrbank2_block_count0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin csrbank2_block_count0_re <= interface2_bank_bus_we; - csrbank2_block_count0_we <= (~interface2_bank_bus_we); + csrbank2_block_count0_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage; assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; -assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage; assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; @@ -3142,7 +3153,7 @@ always @(*) begin sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; end -assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status; assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; always @(*) begin sdcard_core_data_event_status <= 4'd0; @@ -3151,10 +3162,10 @@ always @(*) begin sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; end -assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign csrbank2_data_event_w = sdcard_core_data_event_status; assign sdcard_core_data_event_we = csrbank2_data_event_we; -assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; -assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage; assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; always @(*) begin @@ -3162,7 +3173,7 @@ always @(*) begin csrbank3_status_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin csrbank3_status_re <= interface3_bank_bus_we; - csrbank3_status_we <= (~interface3_bank_bus_we); + csrbank3_status_we <= interface3_bank_bus_re; end end assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; @@ -3171,7 +3182,7 @@ always @(*) begin csrbank3_pending_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin csrbank3_pending_re <= interface3_bank_bus_we; - csrbank3_pending_we <= (~interface3_bank_bus_we); + csrbank3_pending_we <= interface3_bank_bus_re; end end assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; @@ -3180,7 +3191,7 @@ always @(*) begin csrbank3_enable0_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin csrbank3_enable0_re <= interface3_bank_bus_we; - csrbank3_enable0_we <= (~interface3_bank_bus_we); + csrbank3_enable0_we <= interface3_bank_bus_re; end end always @(*) begin @@ -3190,7 +3201,7 @@ always @(*) begin eventmanager_status_status[2] <= eventmanager_mem2block_dma0; eventmanager_status_status[3] <= eventmanager_cmd_done0; end -assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign csrbank3_status_w = eventmanager_status_status; assign eventmanager_status_we = csrbank3_status_we; always @(*) begin eventmanager_pending_status <= 4'd0; @@ -3199,39 +3210,39 @@ always @(*) begin eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; eventmanager_pending_status[3] <= eventmanager_cmd_done1; end -assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign csrbank3_pending_w = eventmanager_pending_status; assign eventmanager_pending_we = csrbank3_pending_we; assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; -assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank3_enable0_w = eventmanager_enable_storage; assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); -assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_base1_re <= 1'd0; csrbank4_dma_base1_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin csrbank4_dma_base1_re <= interface4_bank_bus_we; - csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + csrbank4_dma_base1_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_base0_re <= 1'd0; csrbank4_dma_base0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin csrbank4_dma_base0_re <= interface4_bank_bus_we; - csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + csrbank4_dma_base0_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_length0_re <= 1'd0; csrbank4_dma_length0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin csrbank4_dma_length0_re <= interface4_bank_bus_we; - csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + csrbank4_dma_length0_we <= interface4_bank_bus_re; end end assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; @@ -3240,7 +3251,7 @@ always @(*) begin csrbank4_dma_enable0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin csrbank4_dma_enable0_re <= interface4_bank_bus_we; - csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + csrbank4_dma_enable0_we <= interface4_bank_bus_re; end end assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; @@ -3249,7 +3260,7 @@ always @(*) begin csrbank4_dma_done_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin csrbank4_dma_done_re <= interface4_bank_bus_we; - csrbank4_dma_done_we <= (~interface4_bank_bus_we); + csrbank4_dma_done_we <= interface4_bank_bus_re; end end assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; @@ -3258,26 +3269,26 @@ always @(*) begin csrbank4_dma_loop0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin csrbank4_dma_loop0_re <= interface4_bank_bus_we; - csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + csrbank4_dma_loop0_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_offset_re <= 1'd0; csrbank4_dma_offset_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin csrbank4_dma_offset_re <= interface4_bank_bus_we; - csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + csrbank4_dma_offset_we <= interface4_bank_bus_re; end end assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; -assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage; assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; -assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status; assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; @@ -3286,7 +3297,7 @@ always @(*) begin csrbank5_card_detect_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin csrbank5_card_detect_re <= interface5_bank_bus_we; - csrbank5_card_detect_we <= (~interface5_bank_bus_we); + csrbank5_card_detect_we <= interface5_bank_bus_re; end end assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; @@ -3295,7 +3306,7 @@ always @(*) begin csrbank5_clocker_divider0_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin csrbank5_clocker_divider0_re <= interface5_bank_bus_we; - csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + csrbank5_clocker_divider0_we <= interface5_bank_bus_re; end end assign init_initialize_r = interface5_bank_bus_dat_w[0]; @@ -3304,7 +3315,7 @@ always @(*) begin init_initialize_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin init_initialize_re <= interface5_bank_bus_we; - init_initialize_we <= (~interface5_bank_bus_we); + init_initialize_we <= interface5_bank_bus_re; end end assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; @@ -3313,21 +3324,22 @@ always @(*) begin csrbank5_dataw_status_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin csrbank5_dataw_status_re <= interface5_bank_bus_we; - csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + csrbank5_dataw_status_we <= interface5_bank_bus_re; end end assign csrbank5_card_detect_w = card_detect_status0; assign card_detect_we = csrbank5_card_detect_we; -assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +assign csrbank5_clocker_divider0_w = clocker_storage; always @(*) begin dataw_status <= 3'd0; dataw_status[0] <= dataw_accepted0; dataw_status[1] <= dataw_crc_error0; dataw_status[2] <= dataw_write_error0; end -assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign csrbank5_dataw_status_w = dataw_status; assign dataw_we = csrbank5_dataw_status_we; assign adr = interface1_adr; +assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; @@ -3337,6 +3349,12 @@ assign interface2_bank_bus_adr = adr; assign interface3_bank_bus_adr = adr; assign interface4_bank_bus_adr = adr; assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface3_bank_bus_re = re; +assign interface4_bank_bus_re = re; +assign interface5_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface2_bank_bus_we = we; @@ -3443,6 +3461,7 @@ assign sdrio_clk_1 = sys_clk; assign sdrio_clk_2 = sys_clk; assign sdrio_clk_3 = sys_clk; assign sdrio_clk_4 = sys_clk; +assign clk_i = multiregimpl; //------------------------------------------------------------------------------ @@ -3494,7 +3513,11 @@ always @(posedge sys_clk) begin card_detect_d <= card_detect_status0; card_detect_irq <= (card_detect_status0 ^ card_detect_d); if ((~clocker_stop)) begin - clocker_clks <= (clocker_clks + 1'd1); + clocker_count <= (clocker_count + 1'd1); + if ((clocker_count >= (clocker_storage[8:1] - 1'd1))) begin + clocker_clk1 <= (~clocker_clk1); + clocker_count <= 1'd0; + end end clocker_clk_d <= clocker_clk1; if (clocker_clk_d) begin @@ -3748,8 +3771,7 @@ always @(posedge sys_clk) begin if (datar_datar_reset_sdphydatar_next_value_ce2) begin datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; end - clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; - sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + clk_i_d <= clk_i; sdcard_core_done_d <= sdcard_core_cmd_done; sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); if (sdcard_core_crc7_inserter_crc_reset) begin @@ -3915,11 +3937,11 @@ always @(posedge sys_clk) begin sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); end sdblock2memdma_state <= sdblock2memdma_next_state; - if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin - sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + if (sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset1 <= sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value; end if (sdcard_block2mem_wishbonedmawriter_reset) begin - sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset1 <= 32'd0; sdblock2memdma_state <= 2'd0; end if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin @@ -3946,11 +3968,11 @@ always @(posedge sys_clk) begin end end sdmem2blockdma_state <= sdmem2blockdma_next_state; - if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin - sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + if (sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset1 <= sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value; end if (sdcard_mem2block_dma_reset) begin - sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_dma_offset1 <= 32'd0; sdmem2blockdma_state <= 2'd0; end if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin @@ -4016,11 +4038,11 @@ always @(posedge sys_clk) begin endcase end if (csrbank0_reset0_re) begin - reset_storage[1:0] <= csrbank0_reset0_r; + reset_storage <= csrbank0_reset0_r; end reset_re <= csrbank0_reset0_re; if (csrbank0_scratch0_re) begin - scratch_storage[31:0] <= csrbank0_scratch0_r; + scratch_storage <= csrbank0_scratch0_r; end scratch_re <= csrbank0_scratch0_re; bus_errors_re <= csrbank0_bus_errors_re; @@ -4058,7 +4080,7 @@ always @(posedge sys_clk) begin end sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; if (csrbank1_dma_length0_re) begin - sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + sdcard_block2mem_wishbonedmawriter_length_storage <= csrbank1_dma_length0_r; end sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; if (csrbank1_dma_enable0_re) begin @@ -4110,11 +4132,11 @@ always @(posedge sys_clk) begin endcase end if (csrbank2_cmd_argument0_re) begin - sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + sdcard_core_cmd_argument_storage <= csrbank2_cmd_argument0_r; end sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; if (csrbank2_cmd_command0_re) begin - sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + sdcard_core_cmd_command_storage <= csrbank2_cmd_command0_r; end sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; if (csrbank2_cmd_send0_re) begin @@ -4125,11 +4147,11 @@ always @(posedge sys_clk) begin sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; sdcard_core_data_event_re <= csrbank2_data_event_re; if (csrbank2_block_length0_re) begin - sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + sdcard_core_block_length_storage <= csrbank2_block_length0_r; end sdcard_core_block_length_re <= csrbank2_block_length0_re; if (csrbank2_block_count0_re) begin - sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + sdcard_core_block_count_storage <= csrbank2_block_count0_r; end sdcard_core_block_count_re <= csrbank2_block_count0_re; interface3_bank_bus_dat_r <= 1'd0; @@ -4148,11 +4170,11 @@ always @(posedge sys_clk) begin end eventmanager_status_re <= csrbank3_status_re; if (csrbank3_pending_re) begin - eventmanager_pending_r[3:0] <= csrbank3_pending_r; + eventmanager_pending_r <= csrbank3_pending_r; end eventmanager_pending_re <= csrbank3_pending_re; if (csrbank3_enable0_re) begin - eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + eventmanager_enable_storage <= csrbank3_enable0_r; end eventmanager_enable_re <= csrbank3_enable0_re; interface4_bank_bus_dat_r <= 1'd0; @@ -4189,7 +4211,7 @@ always @(posedge sys_clk) begin end sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; if (csrbank4_dma_length0_re) begin - sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + sdcard_mem2block_dma_length_storage <= csrbank4_dma_length0_r; end sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; if (csrbank4_dma_enable0_re) begin @@ -4221,7 +4243,7 @@ always @(posedge sys_clk) begin end card_detect_re <= csrbank5_card_detect_re; if (csrbank5_clocker_divider0_re) begin - clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + clocker_storage <= csrbank5_clocker_divider0_r; end clocker_re <= csrbank5_clocker_divider0_re; dataw_re <= csrbank5_dataw_status_re; @@ -4235,7 +4257,8 @@ always @(posedge sys_clk) begin card_detect_re <= 1'd0; clocker_storage <= 9'd256; clocker_re <= 1'd0; - clocker_clks <= 9'd0; + clocker_clk1 <= 1'd0; + clocker_count <= 10'd0; clocker_clk_d <= 1'd0; clocker_ce_delayed <= 1'd0; init_count <= 8'd0; @@ -4273,8 +4296,7 @@ always @(posedge sys_clk) begin datar_datar_buf_pipe_valid_source_valid <= 1'd0; datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; datar_datar_reset <= 1'd0; - sdpads_data_i_ce <= 1'd0; - clocker_clk_delay <= 2'd0; + clk_i_d <= 1'd0; card_detect_irq <= 1'd0; card_detect_d <= 1'd0; sdcard_core_irq <= 1'd0; @@ -4319,6 +4341,7 @@ always @(posedge sys_clk) begin sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; sdcard_block2mem_converter_demux <= 2'd0; sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1 <= 32'd0; sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; @@ -4329,13 +4352,13 @@ always @(posedge sys_clk) begin sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; sdcard_block2mem_connect <= 1'd0; sdcard_block2mem_done_d <= 1'd0; sdcard_mem2block_irq <= 1'd0; sdcard_mem2block_dma_fifo_level <= 5'd0; sdcard_mem2block_dma_fifo_produce <= 4'd0; sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_offset1 <= 32'd0; sdcard_mem2block_dma_base_storage <= 64'd0; sdcard_mem2block_dma_base_re <= 1'd0; sdcard_mem2block_dma_length_storage <= 32'd0; @@ -4346,7 +4369,6 @@ always @(posedge sys_clk) begin sdcard_mem2block_dma_loop_storage <= 1'd0; sdcard_mem2block_dma_loop_re <= 1'd0; sdcard_mem2block_dma_offset_re <= 1'd0; - sdcard_mem2block_dma_offset <= 32'd0; sdcard_mem2block_converter_converter_mux <= 2'd0; sdcard_mem2block_fifo_readable <= 1'd0; sdcard_mem2block_fifo_level0 <= 10'd0; @@ -4376,6 +4398,7 @@ always @(posedge sys_clk) begin sdmem2blockdma_state <= 2'd0; wishbone2csr_state <= 1'd0; end + multiregimpl <= (~clocker_clk0); end @@ -4475,21 +4498,6 @@ OFS1P3BX OFS1P3BX( .Q (sdcard_clk) ); -assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; -assign inferedsdrtristate0__i = sdcard_cmd; - -assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; -assign inferedsdrtristate1__i = sdcard_data[0]; - -assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; -assign inferedsdrtristate2__i = sdcard_data[1]; - -assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; -assign inferedsdrtristate3__i = sdcard_data[2]; - -assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; -assign inferedsdrtristate4__i = sdcard_data[3]; - //------------------------------------------------------------------------------ // Instance OFS1P3BX_1 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4560,6 +4568,21 @@ IFS1P3BX IFS1P3BX( .Q (sdpads_cmd_i) ); +//------------------------------------------------------------------------------ +// Instance BB of BB Module. +//------------------------------------------------------------------------------ +BB BB( + // Inputs. + .I (inferedsdrtristate0__o), + .T ((~inferedsdrtristate0_oe)), + + // Outputs. + .O (inferedsdrtristate0__i), + + // InOuts. + .B (sdcard_cmd) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_5 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4588,6 +4611,21 @@ IFS1P3BX IFS1P3BX_1( .Q (sdpads_data_i[0]) ); +//------------------------------------------------------------------------------ +// Instance BB_1 of BB Module. +//------------------------------------------------------------------------------ +BB BB_1( + // Inputs. + .I (inferedsdrtristate1__o), + .T ((~inferedsdrtristate1_oe)), + + // Outputs. + .O (inferedsdrtristate1__i), + + // InOuts. + .B (sdcard_data[0]) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_6 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4616,6 +4654,21 @@ IFS1P3BX IFS1P3BX_2( .Q (sdpads_data_i[1]) ); +//------------------------------------------------------------------------------ +// Instance BB_2 of BB Module. +//------------------------------------------------------------------------------ +BB BB_2( + // Inputs. + .I (inferedsdrtristate2__o), + .T ((~inferedsdrtristate2_oe)), + + // Outputs. + .O (inferedsdrtristate2__i), + + // InOuts. + .B (sdcard_data[1]) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_7 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4644,6 +4697,21 @@ IFS1P3BX IFS1P3BX_3( .Q (sdpads_data_i[2]) ); +//------------------------------------------------------------------------------ +// Instance BB_3 of BB Module. +//------------------------------------------------------------------------------ +BB BB_3( + // Inputs. + .I (inferedsdrtristate3__o), + .T ((~inferedsdrtristate3_oe)), + + // Outputs. + .O (inferedsdrtristate3__i), + + // InOuts. + .B (sdcard_data[2]) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_8 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4672,8 +4740,23 @@ IFS1P3BX IFS1P3BX_4( .Q (sdpads_data_i[3]) ); +//------------------------------------------------------------------------------ +// Instance BB_4 of BB Module. +//------------------------------------------------------------------------------ +BB BB_4( + // Inputs. + .I (inferedsdrtristate4__o), + .T ((~inferedsdrtristate4_oe)), + + // Outputs. + .O (inferedsdrtristate4__i), + + // InOuts. + .B (sdcard_data[3]) +); + endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-03 20:02:06. +// Auto-Generated by LiteX on 2025-02-17 09:51:44. //------------------------------------------------------------------------------ diff --git a/litesdcard/generated/lattice.50e6/litesdcard_core.v b/litesdcard/generated/lattice.50e6/litesdcard_core.v index 7412820..3ff6a60 100644 --- a/litesdcard/generated/lattice.50e6/litesdcard_core.v +++ b/litesdcard/generated/lattice.50e6/litesdcard_core.v @@ -8,8 +8,8 @@ // // Filename : litesdcard_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-03 19:58:12 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-17 09:51:44 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -179,20 +179,25 @@ LiteSDCardCore │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstatus_1* (CSRStatus) └─── csr_interconnect (InterconnectShared) -└─── [IFS1P3BX] +└─── [BB] └─── [OFS1P3BX] -└─── [IFS1P3BX] +└─── [BB] └─── [OFS1P3BX] -└─── [IFS1P3BX] -└─── [IFS1P3BX] └─── [OFS1P3BX] └─── [IFS1P3BX] └─── [OFS1P3BX] └─── [OFS1P3BX] └─── [OFS1P3BX] └─── [OFS1P3BX] +└─── [BB] └─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [BB] +└─── [IFS1P3BX] +└─── [IFS1P3BX] └─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [BB] * : Generated name. []: BlackBox. */ @@ -220,15 +225,16 @@ wire card_detect_status0; wire card_detect_status1; wire card_detect_trigger; wire card_detect_we; +wire clk_i; +reg clk_i_d = 1'd0; wire clocker_ce; reg clocker_ce_delayed = 1'd0; reg clocker_ce_latched = 1'd0; wire clocker_clk0; reg clocker_clk1 = 1'd0; reg clocker_clk_d = 1'd0; -reg [1:0] clocker_clk_delay = 2'd0; wire clocker_clk_en; -reg [8:0] clocker_clks = 9'd0; +reg [9:0] clocker_count = 10'd0; reg clocker_re = 1'd0; wire clocker_stop; reg [8:0] clocker_storage = 9'd256; @@ -760,6 +766,7 @@ wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire interface0_bus_ack; @@ -785,6 +792,7 @@ reg [13:0] interface1_adr = 14'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire interface1_bus_ack; wire [31:0] interface1_bus_adr; @@ -799,28 +807,36 @@ wire interface1_bus_stb; wire interface1_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; reg interface1_we = 1'd0; wire [13:0] interface2_bank_bus_adr; reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; wire interface2_bank_bus_we; wire [13:0] interface3_bank_bus_adr; reg [31:0] interface3_bank_bus_dat_r = 32'd0; wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_re; wire interface3_bank_bus_we; wire [13:0] interface4_bank_bus_adr; reg [31:0] interface4_bank_bus_dat_r = 32'd0; wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_re; wire interface4_bank_bus_we; wire [13:0] interface5_bank_bus_adr; reg [31:0] interface5_bank_bus_dat_r = 32'd0; wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_re; wire interface5_bank_bus_we; reg mem2block_dma_clear = 1'd0; reg mem2block_dma_pending = 1'd0; wire mem2block_dma_status; wire mem2block_dma_trigger; +(* syn_no_retiming = "true" *) +reg multiregimpl = 1'd0; wire por_clk; +wire re; wire [1:0] request; reg reset_re = 1'd0; reg [1:0] reset_storage = 2'd0; @@ -898,23 +914,29 @@ wire [31:0] sdcard_block2mem_source_source_payload_data; wire sdcard_block2mem_source_source_ready; wire sdcard_block2mem_source_source_valid; wire sdcard_block2mem_start; -wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +wire [63:0] sdcard_block2mem_wishbonedmawriter_base0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base1; reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done = 1'd0; reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; -reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_status; wire sdcard_block2mem_wishbonedmawriter_done_we; +wire sdcard_block2mem_wishbonedmawriter_enable; reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; -wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length1; reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +wire sdcard_block2mem_wishbonedmawriter_loop; reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; -reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset1 = 32'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce = 1'd0; reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; -reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; -reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; wire sdcard_block2mem_wishbonedmawriter_offset_we; wire sdcard_block2mem_wishbonedmawriter_reset; @@ -1145,12 +1167,15 @@ wire [7:0] sdcard_mem2block_converter_source_source_payload_data; wire sdcard_mem2block_converter_source_source_ready; wire sdcard_mem2block_converter_source_source_valid; reg [8:0] sdcard_mem2block_count = 9'd0; -wire [31:0] sdcard_mem2block_dma_base; +wire [63:0] sdcard_mem2block_dma_base0; +wire [31:0] sdcard_mem2block_dma_base1; reg sdcard_mem2block_dma_base_re = 1'd0; reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done = 1'd0; reg sdcard_mem2block_dma_done_re = 1'd0; -reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_status; wire sdcard_mem2block_dma_done_we; +wire sdcard_mem2block_dma_enable; reg sdcard_mem2block_dma_enable_re = 1'd0; reg sdcard_mem2block_dma_enable_storage = 1'd0; reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; @@ -1186,15 +1211,18 @@ reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; wire sdcard_mem2block_dma_fifo_wrport_we; -wire [31:0] sdcard_mem2block_dma_length; +wire [31:0] sdcard_mem2block_dma_length0; +wire [31:0] sdcard_mem2block_dma_length1; reg sdcard_mem2block_dma_length_re = 1'd0; reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +wire sdcard_mem2block_dma_loop; reg sdcard_mem2block_dma_loop_re = 1'd0; reg sdcard_mem2block_dma_loop_storage = 1'd0; -reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +wire [31:0] sdcard_mem2block_dma_offset0; +reg [31:0] sdcard_mem2block_dma_offset1 = 32'd0; +reg [31:0] sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce = 1'd0; reg sdcard_mem2block_dma_offset_re = 1'd0; -reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; -reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; wire [31:0] sdcard_mem2block_dma_offset_status; wire sdcard_mem2block_dma_offset_we; wire sdcard_mem2block_dma_reset; @@ -1258,7 +1286,7 @@ wire sdpads_cmd_i; wire sdpads_cmd_o; wire sdpads_cmd_oe; wire [3:0] sdpads_data_i; -reg sdpads_data_i_ce = 1'd0; +wire sdpads_data_i_ce; wire [3:0] sdpads_data_o; wire sdpads_data_oe; reg [2:0] sdphycmdr_next_state = 3'd0; @@ -1295,7 +1323,7 @@ wire shared_err; wire [3:0] shared_sel; wire shared_stb; wire shared_we; -reg slave_sel = 1'd0; +wire slave_sel; reg slave_sel_r = 1'd0; reg soc_rst = 1'd0; wire sys_clk; @@ -1398,10 +1426,7 @@ assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); assign interface0_bus_err = (shared_err & (grant == 1'd0)); assign interface1_bus_err = (shared_err & (grant == 1'd1)); assign request = {interface1_bus_cyc, interface0_bus_cyc}; -always @(*) begin - slave_sel <= 1'd0; - slave_sel <= 1'd1; -end +assign slave_sel = 1'd1; assign wb_dma_adr_1 = shared_adr; assign wb_dma_dat_w_1 = shared_dat_w; assign wb_dma_sel_1 = shared_sel; @@ -1453,35 +1478,6 @@ assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; assign clocker_stop = (dataw_stop | datar_stop); -always @(*) begin - clocker_clk1 <= 1'd0; - case (clocker_storage) - 3'd4: begin - clocker_clk1 <= clocker_clks[1]; - end - 4'd8: begin - clocker_clk1 <= clocker_clks[2]; - end - 5'd16: begin - clocker_clk1 <= clocker_clks[3]; - end - 6'd32: begin - clocker_clk1 <= clocker_clks[4]; - end - 7'd64: begin - clocker_clk1 <= clocker_clks[5]; - end - 8'd128: begin - clocker_clk1 <= clocker_clks[6]; - end - 9'd256: begin - clocker_clk1 <= clocker_clks[7]; - end - default: begin - clocker_clk1 <= clocker_clks[0]; - end - endcase -end assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); always @(*) begin clocker_ce_latched <= 1'd0; @@ -1943,9 +1939,9 @@ assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; -assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_start = (datar_datar_pads_in_payload_data_i == 1'd0); assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); -assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i; assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; @@ -2077,6 +2073,7 @@ always @(*) begin end endcase end +assign sdpads_data_i_ce = (clk_i & (~clk_i_d)); assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; @@ -2636,35 +2633,41 @@ assign interface0_bus_sel = 4'd15; assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; -assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; -assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; -assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; -assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +assign sdcard_block2mem_wishbonedmawriter_base1 = sdcard_block2mem_wishbonedmawriter_base0[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length1 = sdcard_block2mem_wishbonedmawriter_length0[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset0 = sdcard_block2mem_wishbonedmawriter_offset1; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable); +assign sdcard_block2mem_wishbonedmawriter_base0 = sdcard_block2mem_wishbonedmawriter_base_storage; +assign sdcard_block2mem_wishbonedmawriter_length0 = sdcard_block2mem_wishbonedmawriter_length_storage; +assign sdcard_block2mem_wishbonedmawriter_enable = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign sdcard_block2mem_wishbonedmawriter_loop = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign sdcard_block2mem_wishbonedmawriter_done_status = sdcard_block2mem_wishbonedmawriter_done; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset0; always @(*) begin sdblock2memdma_next_state <= 2'd0; sdcard_block2mem_sink_sink_last1 <= 1'd0; sdcard_block2mem_sink_sink_payload_address <= 32'd0; sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; sdcard_block2mem_sink_sink_valid1 <= 1'd0; - sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd0; sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; sdblock2memdma_next_state <= sdblock2memdma_state; case (sdblock2memdma_state) 1'd1: begin sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; - sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); - sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset1 + 1'd1) == sdcard_block2mem_wishbonedmawriter_length1)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base1 + sdcard_block2mem_wishbonedmawriter_offset1); sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset1 + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; if (sdcard_block2mem_sink_sink_last1) begin - if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_wishbonedmawriter_loop) begin + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; end else begin sdblock2memdma_next_state <= 2'd2; end @@ -2672,12 +2675,12 @@ always @(*) begin end end 2'd2: begin - sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + sdcard_block2mem_wishbonedmawriter_done <= 1'd1; end default: begin sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; sdblock2memdma_next_state <= 1'd1; end endcase @@ -2723,10 +2726,16 @@ assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_sour assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; -assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; -assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; -assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; -assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_base1 = sdcard_mem2block_dma_base0[63:2]; +assign sdcard_mem2block_dma_length1 = sdcard_mem2block_dma_length0[31:2]; +assign sdcard_mem2block_dma_offset0 = sdcard_mem2block_dma_offset1; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable); +assign sdcard_mem2block_dma_base0 = sdcard_mem2block_dma_base_storage; +assign sdcard_mem2block_dma_length0 = sdcard_mem2block_dma_length_storage; +assign sdcard_mem2block_dma_enable = sdcard_mem2block_dma_enable_storage; +assign sdcard_mem2block_dma_loop = sdcard_mem2block_dma_loop_storage; +assign sdcard_mem2block_dma_done_status = sdcard_mem2block_dma_done; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset0; assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; @@ -2755,9 +2764,9 @@ assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdpor assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); always @(*) begin - sdcard_mem2block_dma_done_status <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_done <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd0; sdcard_mem2block_dma_sink_sink_last <= 1'd0; sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; sdcard_mem2block_dma_sink_sink_valid <= 1'd0; @@ -2766,15 +2775,15 @@ always @(*) begin case (sdmem2blockdma_state) 1'd1: begin sdcard_mem2block_dma_sink_sink_valid <= 1'd1; - sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); - sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset1 == (sdcard_mem2block_dma_length1 - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base1 + sdcard_mem2block_dma_offset1); if (sdcard_mem2block_dma_sink_sink_ready) begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset1 + 1'd1); + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; if (sdcard_mem2block_dma_sink_sink_last) begin - if (sdcard_mem2block_dma_loop_storage) begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_loop) begin + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; end else begin sdmem2blockdma_next_state <= 2'd2; end @@ -2782,11 +2791,11 @@ always @(*) begin end end 2'd2: begin - sdcard_mem2block_dma_done_status <= 1'd1; + sdcard_mem2block_dma_done <= 1'd1; end default: begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; sdmem2blockdma_next_state <= 1'd1; end endcase @@ -2893,6 +2902,7 @@ always @(*) begin interface0_dat_r <= 32'd0; interface1_adr <= 14'd0; interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; interface1_we <= 1'd0; wishbone2csr_next_state <= 1'd0; wishbone2csr_next_state <= wishbone2csr_state; @@ -2905,7 +2915,8 @@ always @(*) begin default: begin interface1_dat_w <= interface0_dat_w; if ((interface0_cyc & interface0_stb)) begin - interface1_adr <= interface0_adr[29:0]; + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); interface1_we <= (interface0_we & (interface0_sel != 1'd0)); wishbone2csr_next_state <= 1'd1; end @@ -2919,25 +2930,25 @@ always @(*) begin csrbank0_reset0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin csrbank0_reset0_re <= interface0_bank_bus_we; - csrbank0_reset0_we <= (~interface0_bank_bus_we); + csrbank0_reset0_we <= interface0_bank_bus_re; end end -assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_scratch0_re <= 1'd0; csrbank0_scratch0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin csrbank0_scratch0_re <= interface0_bank_bus_we; - csrbank0_scratch0_we <= (~interface0_bank_bus_we); + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_bus_errors_re <= 1'd0; csrbank0_bus_errors_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin csrbank0_bus_errors_re <= interface0_bank_bus_we; - csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin @@ -2947,36 +2958,36 @@ always @(*) begin end end assign cpu_rst = reset_storage[1]; -assign csrbank0_reset0_w = reset_storage[1:0]; -assign csrbank0_scratch0_w = scratch_storage[31:0]; -assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign csrbank0_reset0_w = reset_storage; +assign csrbank0_scratch0_w = scratch_storage; +assign csrbank0_bus_errors_w = bus_errors_status; assign bus_errors_we = csrbank0_bus_errors_we; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_base1_re <= 1'd0; csrbank1_dma_base1_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin csrbank1_dma_base1_re <= interface1_bank_bus_we; - csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + csrbank1_dma_base1_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_base0_re <= 1'd0; csrbank1_dma_base0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin csrbank1_dma_base0_re <= interface1_bank_bus_we; - csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + csrbank1_dma_base0_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_length0_re <= 1'd0; csrbank1_dma_length0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin csrbank1_dma_length0_re <= interface1_bank_bus_we; - csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + csrbank1_dma_length0_we <= interface1_bank_bus_re; end end assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; @@ -2985,7 +2996,7 @@ always @(*) begin csrbank1_dma_enable0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin csrbank1_dma_enable0_re <= interface1_bank_bus_we; - csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + csrbank1_dma_enable0_we <= interface1_bank_bus_re; end end assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; @@ -2994,7 +3005,7 @@ always @(*) begin csrbank1_dma_done_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin csrbank1_dma_done_re <= interface1_bank_bus_we; - csrbank1_dma_done_we <= (~interface1_bank_bus_we); + csrbank1_dma_done_we <= interface1_bank_bus_re; end end assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; @@ -3003,35 +3014,35 @@ always @(*) begin csrbank1_dma_loop0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin csrbank1_dma_loop0_re <= interface1_bank_bus_we; - csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + csrbank1_dma_loop0_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_offset_re <= 1'd0; csrbank1_dma_offset_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin csrbank1_dma_offset_re <= interface1_bank_bus_we; - csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + csrbank1_dma_offset_we <= interface1_bank_bus_re; end end assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; -assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage; assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; -assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status; assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_argument0_re <= 1'd0; csrbank2_cmd_argument0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin csrbank2_cmd_argument0_re <= interface2_bank_bus_we; - csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_argument0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; @@ -3040,7 +3051,7 @@ always @(*) begin csrbank2_cmd_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin csrbank2_cmd_command0_re <= interface2_bank_bus_we; - csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_command0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; @@ -3049,43 +3060,43 @@ always @(*) begin csrbank2_cmd_send0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin csrbank2_cmd_send0_re <= interface2_bank_bus_we; - csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_send0_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response3_re <= 1'd0; csrbank2_cmd_response3_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin csrbank2_cmd_response3_re <= interface2_bank_bus_we; - csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response3_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response2_re <= 1'd0; csrbank2_cmd_response2_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin csrbank2_cmd_response2_re <= interface2_bank_bus_we; - csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response2_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response1_re <= 1'd0; csrbank2_cmd_response1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin csrbank2_cmd_response1_re <= interface2_bank_bus_we; - csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response1_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response0_re <= 1'd0; csrbank2_cmd_response0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin csrbank2_cmd_response0_re <= interface2_bank_bus_we; - csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; @@ -3094,7 +3105,7 @@ always @(*) begin csrbank2_cmd_event_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin csrbank2_cmd_event_re <= interface2_bank_bus_we; - csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + csrbank2_cmd_event_we <= interface2_bank_bus_re; end end assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; @@ -3103,7 +3114,7 @@ always @(*) begin csrbank2_data_event_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin csrbank2_data_event_re <= interface2_bank_bus_we; - csrbank2_data_event_we <= (~interface2_bank_bus_we); + csrbank2_data_event_we <= interface2_bank_bus_re; end end assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; @@ -3112,23 +3123,23 @@ always @(*) begin csrbank2_block_length0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin csrbank2_block_length0_re <= interface2_bank_bus_we; - csrbank2_block_length0_we <= (~interface2_bank_bus_we); + csrbank2_block_length0_we <= interface2_bank_bus_re; end end -assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_block_count0_re <= 1'd0; csrbank2_block_count0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin csrbank2_block_count0_re <= interface2_bank_bus_we; - csrbank2_block_count0_we <= (~interface2_bank_bus_we); + csrbank2_block_count0_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage; assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; -assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage; assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; @@ -3142,7 +3153,7 @@ always @(*) begin sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; end -assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status; assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; always @(*) begin sdcard_core_data_event_status <= 4'd0; @@ -3151,10 +3162,10 @@ always @(*) begin sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; end -assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign csrbank2_data_event_w = sdcard_core_data_event_status; assign sdcard_core_data_event_we = csrbank2_data_event_we; -assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; -assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage; assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; always @(*) begin @@ -3162,7 +3173,7 @@ always @(*) begin csrbank3_status_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin csrbank3_status_re <= interface3_bank_bus_we; - csrbank3_status_we <= (~interface3_bank_bus_we); + csrbank3_status_we <= interface3_bank_bus_re; end end assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; @@ -3171,7 +3182,7 @@ always @(*) begin csrbank3_pending_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin csrbank3_pending_re <= interface3_bank_bus_we; - csrbank3_pending_we <= (~interface3_bank_bus_we); + csrbank3_pending_we <= interface3_bank_bus_re; end end assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; @@ -3180,7 +3191,7 @@ always @(*) begin csrbank3_enable0_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin csrbank3_enable0_re <= interface3_bank_bus_we; - csrbank3_enable0_we <= (~interface3_bank_bus_we); + csrbank3_enable0_we <= interface3_bank_bus_re; end end always @(*) begin @@ -3190,7 +3201,7 @@ always @(*) begin eventmanager_status_status[2] <= eventmanager_mem2block_dma0; eventmanager_status_status[3] <= eventmanager_cmd_done0; end -assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign csrbank3_status_w = eventmanager_status_status; assign eventmanager_status_we = csrbank3_status_we; always @(*) begin eventmanager_pending_status <= 4'd0; @@ -3199,39 +3210,39 @@ always @(*) begin eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; eventmanager_pending_status[3] <= eventmanager_cmd_done1; end -assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign csrbank3_pending_w = eventmanager_pending_status; assign eventmanager_pending_we = csrbank3_pending_we; assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; -assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank3_enable0_w = eventmanager_enable_storage; assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); -assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_base1_re <= 1'd0; csrbank4_dma_base1_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin csrbank4_dma_base1_re <= interface4_bank_bus_we; - csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + csrbank4_dma_base1_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_base0_re <= 1'd0; csrbank4_dma_base0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin csrbank4_dma_base0_re <= interface4_bank_bus_we; - csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + csrbank4_dma_base0_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_length0_re <= 1'd0; csrbank4_dma_length0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin csrbank4_dma_length0_re <= interface4_bank_bus_we; - csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + csrbank4_dma_length0_we <= interface4_bank_bus_re; end end assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; @@ -3240,7 +3251,7 @@ always @(*) begin csrbank4_dma_enable0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin csrbank4_dma_enable0_re <= interface4_bank_bus_we; - csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + csrbank4_dma_enable0_we <= interface4_bank_bus_re; end end assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; @@ -3249,7 +3260,7 @@ always @(*) begin csrbank4_dma_done_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin csrbank4_dma_done_re <= interface4_bank_bus_we; - csrbank4_dma_done_we <= (~interface4_bank_bus_we); + csrbank4_dma_done_we <= interface4_bank_bus_re; end end assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; @@ -3258,26 +3269,26 @@ always @(*) begin csrbank4_dma_loop0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin csrbank4_dma_loop0_re <= interface4_bank_bus_we; - csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + csrbank4_dma_loop0_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_offset_re <= 1'd0; csrbank4_dma_offset_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin csrbank4_dma_offset_re <= interface4_bank_bus_we; - csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + csrbank4_dma_offset_we <= interface4_bank_bus_re; end end assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; -assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage; assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; -assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status; assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; @@ -3286,7 +3297,7 @@ always @(*) begin csrbank5_card_detect_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin csrbank5_card_detect_re <= interface5_bank_bus_we; - csrbank5_card_detect_we <= (~interface5_bank_bus_we); + csrbank5_card_detect_we <= interface5_bank_bus_re; end end assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; @@ -3295,7 +3306,7 @@ always @(*) begin csrbank5_clocker_divider0_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin csrbank5_clocker_divider0_re <= interface5_bank_bus_we; - csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + csrbank5_clocker_divider0_we <= interface5_bank_bus_re; end end assign init_initialize_r = interface5_bank_bus_dat_w[0]; @@ -3304,7 +3315,7 @@ always @(*) begin init_initialize_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin init_initialize_re <= interface5_bank_bus_we; - init_initialize_we <= (~interface5_bank_bus_we); + init_initialize_we <= interface5_bank_bus_re; end end assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; @@ -3313,21 +3324,22 @@ always @(*) begin csrbank5_dataw_status_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin csrbank5_dataw_status_re <= interface5_bank_bus_we; - csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + csrbank5_dataw_status_we <= interface5_bank_bus_re; end end assign csrbank5_card_detect_w = card_detect_status0; assign card_detect_we = csrbank5_card_detect_we; -assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +assign csrbank5_clocker_divider0_w = clocker_storage; always @(*) begin dataw_status <= 3'd0; dataw_status[0] <= dataw_accepted0; dataw_status[1] <= dataw_crc_error0; dataw_status[2] <= dataw_write_error0; end -assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign csrbank5_dataw_status_w = dataw_status; assign dataw_we = csrbank5_dataw_status_we; assign adr = interface1_adr; +assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; @@ -3337,6 +3349,12 @@ assign interface2_bank_bus_adr = adr; assign interface3_bank_bus_adr = adr; assign interface4_bank_bus_adr = adr; assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface3_bank_bus_re = re; +assign interface4_bank_bus_re = re; +assign interface5_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface2_bank_bus_we = we; @@ -3443,6 +3461,7 @@ assign sdrio_clk_1 = sys_clk; assign sdrio_clk_2 = sys_clk; assign sdrio_clk_3 = sys_clk; assign sdrio_clk_4 = sys_clk; +assign clk_i = multiregimpl; //------------------------------------------------------------------------------ @@ -3494,7 +3513,11 @@ always @(posedge sys_clk) begin card_detect_d <= card_detect_status0; card_detect_irq <= (card_detect_status0 ^ card_detect_d); if ((~clocker_stop)) begin - clocker_clks <= (clocker_clks + 1'd1); + clocker_count <= (clocker_count + 1'd1); + if ((clocker_count >= (clocker_storage[8:1] - 1'd1))) begin + clocker_clk1 <= (~clocker_clk1); + clocker_count <= 1'd0; + end end clocker_clk_d <= clocker_clk1; if (clocker_clk_d) begin @@ -3748,8 +3771,7 @@ always @(posedge sys_clk) begin if (datar_datar_reset_sdphydatar_next_value_ce2) begin datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; end - clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; - sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + clk_i_d <= clk_i; sdcard_core_done_d <= sdcard_core_cmd_done; sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); if (sdcard_core_crc7_inserter_crc_reset) begin @@ -3915,11 +3937,11 @@ always @(posedge sys_clk) begin sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); end sdblock2memdma_state <= sdblock2memdma_next_state; - if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin - sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + if (sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset1 <= sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value; end if (sdcard_block2mem_wishbonedmawriter_reset) begin - sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset1 <= 32'd0; sdblock2memdma_state <= 2'd0; end if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin @@ -3946,11 +3968,11 @@ always @(posedge sys_clk) begin end end sdmem2blockdma_state <= sdmem2blockdma_next_state; - if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin - sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + if (sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset1 <= sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value; end if (sdcard_mem2block_dma_reset) begin - sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_dma_offset1 <= 32'd0; sdmem2blockdma_state <= 2'd0; end if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin @@ -4016,11 +4038,11 @@ always @(posedge sys_clk) begin endcase end if (csrbank0_reset0_re) begin - reset_storage[1:0] <= csrbank0_reset0_r; + reset_storage <= csrbank0_reset0_r; end reset_re <= csrbank0_reset0_re; if (csrbank0_scratch0_re) begin - scratch_storage[31:0] <= csrbank0_scratch0_r; + scratch_storage <= csrbank0_scratch0_r; end scratch_re <= csrbank0_scratch0_re; bus_errors_re <= csrbank0_bus_errors_re; @@ -4058,7 +4080,7 @@ always @(posedge sys_clk) begin end sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; if (csrbank1_dma_length0_re) begin - sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + sdcard_block2mem_wishbonedmawriter_length_storage <= csrbank1_dma_length0_r; end sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; if (csrbank1_dma_enable0_re) begin @@ -4110,11 +4132,11 @@ always @(posedge sys_clk) begin endcase end if (csrbank2_cmd_argument0_re) begin - sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + sdcard_core_cmd_argument_storage <= csrbank2_cmd_argument0_r; end sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; if (csrbank2_cmd_command0_re) begin - sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + sdcard_core_cmd_command_storage <= csrbank2_cmd_command0_r; end sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; if (csrbank2_cmd_send0_re) begin @@ -4125,11 +4147,11 @@ always @(posedge sys_clk) begin sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; sdcard_core_data_event_re <= csrbank2_data_event_re; if (csrbank2_block_length0_re) begin - sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + sdcard_core_block_length_storage <= csrbank2_block_length0_r; end sdcard_core_block_length_re <= csrbank2_block_length0_re; if (csrbank2_block_count0_re) begin - sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + sdcard_core_block_count_storage <= csrbank2_block_count0_r; end sdcard_core_block_count_re <= csrbank2_block_count0_re; interface3_bank_bus_dat_r <= 1'd0; @@ -4148,11 +4170,11 @@ always @(posedge sys_clk) begin end eventmanager_status_re <= csrbank3_status_re; if (csrbank3_pending_re) begin - eventmanager_pending_r[3:0] <= csrbank3_pending_r; + eventmanager_pending_r <= csrbank3_pending_r; end eventmanager_pending_re <= csrbank3_pending_re; if (csrbank3_enable0_re) begin - eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + eventmanager_enable_storage <= csrbank3_enable0_r; end eventmanager_enable_re <= csrbank3_enable0_re; interface4_bank_bus_dat_r <= 1'd0; @@ -4189,7 +4211,7 @@ always @(posedge sys_clk) begin end sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; if (csrbank4_dma_length0_re) begin - sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + sdcard_mem2block_dma_length_storage <= csrbank4_dma_length0_r; end sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; if (csrbank4_dma_enable0_re) begin @@ -4221,7 +4243,7 @@ always @(posedge sys_clk) begin end card_detect_re <= csrbank5_card_detect_re; if (csrbank5_clocker_divider0_re) begin - clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + clocker_storage <= csrbank5_clocker_divider0_r; end clocker_re <= csrbank5_clocker_divider0_re; dataw_re <= csrbank5_dataw_status_re; @@ -4235,7 +4257,8 @@ always @(posedge sys_clk) begin card_detect_re <= 1'd0; clocker_storage <= 9'd256; clocker_re <= 1'd0; - clocker_clks <= 9'd0; + clocker_clk1 <= 1'd0; + clocker_count <= 10'd0; clocker_clk_d <= 1'd0; clocker_ce_delayed <= 1'd0; init_count <= 8'd0; @@ -4273,8 +4296,7 @@ always @(posedge sys_clk) begin datar_datar_buf_pipe_valid_source_valid <= 1'd0; datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; datar_datar_reset <= 1'd0; - sdpads_data_i_ce <= 1'd0; - clocker_clk_delay <= 2'd0; + clk_i_d <= 1'd0; card_detect_irq <= 1'd0; card_detect_d <= 1'd0; sdcard_core_irq <= 1'd0; @@ -4319,6 +4341,7 @@ always @(posedge sys_clk) begin sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; sdcard_block2mem_converter_demux <= 2'd0; sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1 <= 32'd0; sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; @@ -4329,13 +4352,13 @@ always @(posedge sys_clk) begin sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; sdcard_block2mem_connect <= 1'd0; sdcard_block2mem_done_d <= 1'd0; sdcard_mem2block_irq <= 1'd0; sdcard_mem2block_dma_fifo_level <= 5'd0; sdcard_mem2block_dma_fifo_produce <= 4'd0; sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_offset1 <= 32'd0; sdcard_mem2block_dma_base_storage <= 64'd0; sdcard_mem2block_dma_base_re <= 1'd0; sdcard_mem2block_dma_length_storage <= 32'd0; @@ -4346,7 +4369,6 @@ always @(posedge sys_clk) begin sdcard_mem2block_dma_loop_storage <= 1'd0; sdcard_mem2block_dma_loop_re <= 1'd0; sdcard_mem2block_dma_offset_re <= 1'd0; - sdcard_mem2block_dma_offset <= 32'd0; sdcard_mem2block_converter_converter_mux <= 2'd0; sdcard_mem2block_fifo_readable <= 1'd0; sdcard_mem2block_fifo_level0 <= 10'd0; @@ -4376,6 +4398,7 @@ always @(posedge sys_clk) begin sdmem2blockdma_state <= 2'd0; wishbone2csr_state <= 1'd0; end + multiregimpl <= (~clocker_clk0); end @@ -4475,21 +4498,6 @@ OFS1P3BX OFS1P3BX( .Q (sdcard_clk) ); -assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; -assign inferedsdrtristate0__i = sdcard_cmd; - -assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; -assign inferedsdrtristate1__i = sdcard_data[0]; - -assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; -assign inferedsdrtristate2__i = sdcard_data[1]; - -assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; -assign inferedsdrtristate3__i = sdcard_data[2]; - -assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; -assign inferedsdrtristate4__i = sdcard_data[3]; - //------------------------------------------------------------------------------ // Instance OFS1P3BX_1 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4560,6 +4568,21 @@ IFS1P3BX IFS1P3BX( .Q (sdpads_cmd_i) ); +//------------------------------------------------------------------------------ +// Instance BB of BB Module. +//------------------------------------------------------------------------------ +BB BB( + // Inputs. + .I (inferedsdrtristate0__o), + .T ((~inferedsdrtristate0_oe)), + + // Outputs. + .O (inferedsdrtristate0__i), + + // InOuts. + .B (sdcard_cmd) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_5 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4588,6 +4611,21 @@ IFS1P3BX IFS1P3BX_1( .Q (sdpads_data_i[0]) ); +//------------------------------------------------------------------------------ +// Instance BB_1 of BB Module. +//------------------------------------------------------------------------------ +BB BB_1( + // Inputs. + .I (inferedsdrtristate1__o), + .T ((~inferedsdrtristate1_oe)), + + // Outputs. + .O (inferedsdrtristate1__i), + + // InOuts. + .B (sdcard_data[0]) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_6 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4616,6 +4654,21 @@ IFS1P3BX IFS1P3BX_2( .Q (sdpads_data_i[1]) ); +//------------------------------------------------------------------------------ +// Instance BB_2 of BB Module. +//------------------------------------------------------------------------------ +BB BB_2( + // Inputs. + .I (inferedsdrtristate2__o), + .T ((~inferedsdrtristate2_oe)), + + // Outputs. + .O (inferedsdrtristate2__i), + + // InOuts. + .B (sdcard_data[1]) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_7 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4644,6 +4697,21 @@ IFS1P3BX IFS1P3BX_3( .Q (sdpads_data_i[2]) ); +//------------------------------------------------------------------------------ +// Instance BB_3 of BB Module. +//------------------------------------------------------------------------------ +BB BB_3( + // Inputs. + .I (inferedsdrtristate3__o), + .T ((~inferedsdrtristate3_oe)), + + // Outputs. + .O (inferedsdrtristate3__i), + + // InOuts. + .B (sdcard_data[2]) +); + //------------------------------------------------------------------------------ // Instance OFS1P3BX_8 of OFS1P3BX Module. //------------------------------------------------------------------------------ @@ -4672,8 +4740,23 @@ IFS1P3BX IFS1P3BX_4( .Q (sdpads_data_i[3]) ); +//------------------------------------------------------------------------------ +// Instance BB_4 of BB Module. +//------------------------------------------------------------------------------ +BB BB_4( + // Inputs. + .I (inferedsdrtristate4__o), + .T ((~inferedsdrtristate4_oe)), + + // Outputs. + .O (inferedsdrtristate4__i), + + // InOuts. + .B (sdcard_data[3]) +); + endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-03 19:58:12. +// Auto-Generated by LiteX on 2025-02-17 09:51:44. //------------------------------------------------------------------------------ diff --git a/litesdcard/generated/xilinx.100e6/litesdcard_core.v b/litesdcard/generated/xilinx.100e6/litesdcard_core.v index 5266241..6c781e0 100644 --- a/litesdcard/generated/xilinx.100e6/litesdcard_core.v +++ b/litesdcard/generated/xilinx.100e6/litesdcard_core.v @@ -8,8 +8,8 @@ // // Filename : litesdcard_core.v // Device : -// LiteX sha1 : 87137c30 -// Date : 2024-04-03 20:02:06 +// LiteX sha1 : bc1f1f52b +// Date : 2025-02-17 09:51:44 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -76,7 +76,6 @@ LiteSDCardCore │ │ │ └─── waittimer_0* (WaitTimer) └─── sdcard_phy (SDPHY) │ └─── clocker (SDPHYClocker) -│ │ └─── [BUFG] │ └─── init (SDPHYInit) │ │ └─── fsm_0* (FSM) │ └─── cmdw (SDPHYCMDW) @@ -212,15 +211,16 @@ wire card_detect_status0; wire card_detect_status1; wire card_detect_trigger; wire card_detect_we; +wire clk_i; +reg clk_i_d = 1'd0; wire clocker_ce; reg clocker_ce_delayed = 1'd0; reg clocker_ce_latched = 1'd0; wire clocker_clk0; reg clocker_clk1 = 1'd0; reg clocker_clk_d = 1'd0; -reg [1:0] clocker_clk_delay = 2'd0; wire clocker_clk_en; -reg [8:0] clocker_clks = 9'd0; +reg [9:0] clocker_count = 10'd0; reg clocker_re = 1'd0; wire clocker_stop; reg [8:0] clocker_storage = 9'd256; @@ -737,6 +737,7 @@ wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire interface0_bus_ack; @@ -762,6 +763,7 @@ reg [13:0] interface1_adr = 14'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire interface1_bus_ack; wire [31:0] interface1_bus_adr; @@ -776,28 +778,34 @@ wire interface1_bus_stb; wire interface1_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; +reg interface1_re = 1'd0; reg interface1_we = 1'd0; wire [13:0] interface2_bank_bus_adr; reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_re; wire interface2_bank_bus_we; wire [13:0] interface3_bank_bus_adr; reg [31:0] interface3_bank_bus_dat_r = 32'd0; wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_re; wire interface3_bank_bus_we; wire [13:0] interface4_bank_bus_adr; reg [31:0] interface4_bank_bus_dat_r = 32'd0; wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_re; wire interface4_bank_bus_we; wire [13:0] interface5_bank_bus_adr; reg [31:0] interface5_bank_bus_dat_r = 32'd0; wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_re; wire interface5_bank_bus_we; reg mem2block_dma_clear = 1'd0; reg mem2block_dma_pending = 1'd0; wire mem2block_dma_status; wire mem2block_dma_trigger; wire por_clk; +wire re; wire [1:0] request; reg reset_re = 1'd0; reg [1:0] reset_storage = 2'd0; @@ -875,23 +883,29 @@ wire [31:0] sdcard_block2mem_source_source_payload_data; wire sdcard_block2mem_source_source_ready; wire sdcard_block2mem_source_source_valid; wire sdcard_block2mem_start; -wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +wire [63:0] sdcard_block2mem_wishbonedmawriter_base0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base1; reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done = 1'd0; reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; -reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_status; wire sdcard_block2mem_wishbonedmawriter_done_we; +wire sdcard_block2mem_wishbonedmawriter_enable; reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; -wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length1; reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +wire sdcard_block2mem_wishbonedmawriter_loop; reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; -reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset1 = 32'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce = 1'd0; reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; -reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; -reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; wire sdcard_block2mem_wishbonedmawriter_offset_we; wire sdcard_block2mem_wishbonedmawriter_reset; @@ -1122,12 +1136,15 @@ wire [7:0] sdcard_mem2block_converter_source_source_payload_data; wire sdcard_mem2block_converter_source_source_ready; wire sdcard_mem2block_converter_source_source_valid; reg [8:0] sdcard_mem2block_count = 9'd0; -wire [31:0] sdcard_mem2block_dma_base; +wire [63:0] sdcard_mem2block_dma_base0; +wire [31:0] sdcard_mem2block_dma_base1; reg sdcard_mem2block_dma_base_re = 1'd0; reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done = 1'd0; reg sdcard_mem2block_dma_done_re = 1'd0; -reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_status; wire sdcard_mem2block_dma_done_we; +wire sdcard_mem2block_dma_enable; reg sdcard_mem2block_dma_enable_re = 1'd0; reg sdcard_mem2block_dma_enable_storage = 1'd0; reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; @@ -1163,15 +1180,18 @@ reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; wire sdcard_mem2block_dma_fifo_wrport_we; -wire [31:0] sdcard_mem2block_dma_length; +wire [31:0] sdcard_mem2block_dma_length0; +wire [31:0] sdcard_mem2block_dma_length1; reg sdcard_mem2block_dma_length_re = 1'd0; reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +wire sdcard_mem2block_dma_loop; reg sdcard_mem2block_dma_loop_re = 1'd0; reg sdcard_mem2block_dma_loop_storage = 1'd0; -reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +wire [31:0] sdcard_mem2block_dma_offset0; +reg [31:0] sdcard_mem2block_dma_offset1 = 32'd0; +reg [31:0] sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce = 1'd0; reg sdcard_mem2block_dma_offset_re = 1'd0; -reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; -reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; wire [31:0] sdcard_mem2block_dma_offset_status; wire sdcard_mem2block_dma_offset_we; wire sdcard_mem2block_dma_reset; @@ -1235,7 +1255,7 @@ reg sdpads_cmd_i = 1'd0; wire sdpads_cmd_o; wire sdpads_cmd_oe; reg [3:0] sdpads_data_i = 4'd0; -reg sdpads_data_i_ce = 1'd0; +wire sdpads_data_i_ce; wire [3:0] sdpads_data_o; wire sdpads_data_oe; reg [2:0] sdphycmdr_next_state = 3'd0; @@ -1286,7 +1306,7 @@ wire shared_err; wire [3:0] shared_sel; wire shared_stb; wire shared_we; -reg slave_sel = 1'd0; +wire slave_sel; reg slave_sel_r = 1'd0; reg soc_rst = 1'd0; wire sys_clk; @@ -1317,6 +1337,9 @@ wire wb_dma_we_1; wire we; reg wishbone2csr_next_state = 1'd0; reg wishbone2csr_state = 1'd0; +wire xilinxmultiregimpl; +(* register_balancing = "no", shreg_extract = "no" *) +reg xilinxmultiregimpl_xilinxmultiregimpl = 1'd0; wire xilinxsdrtristateimpl0__i; reg xilinxsdrtristateimpl0__o = 1'd0; reg xilinxsdrtristateimpl0_oe_n = 1'd0; @@ -1404,10 +1427,7 @@ assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); assign interface0_bus_err = (shared_err & (grant == 1'd0)); assign interface1_bus_err = (shared_err & (grant == 1'd1)); assign request = {interface1_bus_cyc, interface0_bus_cyc}; -always @(*) begin - slave_sel <= 1'd0; - slave_sel <= 1'd1; -end +assign slave_sel = 1'd1; assign wb_dma_adr_1 = shared_adr; assign wb_dma_dat_w_1 = shared_dat_w; assign wb_dma_sel_1 = shared_sel; @@ -1459,35 +1479,7 @@ assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; assign clocker_stop = (dataw_stop | datar_stop); -always @(*) begin - clocker_clk1 <= 1'd0; - case (clocker_storage) - 3'd4: begin - clocker_clk1 <= clocker_clks[1]; - end - 4'd8: begin - clocker_clk1 <= clocker_clks[2]; - end - 5'd16: begin - clocker_clk1 <= clocker_clks[3]; - end - 6'd32: begin - clocker_clk1 <= clocker_clks[4]; - end - 7'd64: begin - clocker_clk1 <= clocker_clks[5]; - end - 8'd128: begin - clocker_clk1 <= clocker_clks[6]; - end - 9'd256: begin - clocker_clk1 <= clocker_clks[7]; - end - default: begin - clocker_clk1 <= clocker_clks[0]; - end - endcase -end +assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); always @(*) begin clocker_ce_latched <= 1'd0; if (clocker_clk_d) begin @@ -1948,9 +1940,9 @@ assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; -assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_start = (datar_datar_pads_in_payload_data_i == 1'd0); assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); -assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i; assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; @@ -2082,6 +2074,7 @@ always @(*) begin end endcase end +assign sdpads_data_i_ce = (clk_i & (~clk_i_d)); assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; @@ -2641,35 +2634,41 @@ assign interface0_bus_sel = 4'd15; assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; -assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; -assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; -assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; -assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +assign sdcard_block2mem_wishbonedmawriter_base1 = sdcard_block2mem_wishbonedmawriter_base0[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length1 = sdcard_block2mem_wishbonedmawriter_length0[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset0 = sdcard_block2mem_wishbonedmawriter_offset1; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable); +assign sdcard_block2mem_wishbonedmawriter_base0 = sdcard_block2mem_wishbonedmawriter_base_storage; +assign sdcard_block2mem_wishbonedmawriter_length0 = sdcard_block2mem_wishbonedmawriter_length_storage; +assign sdcard_block2mem_wishbonedmawriter_enable = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign sdcard_block2mem_wishbonedmawriter_loop = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign sdcard_block2mem_wishbonedmawriter_done_status = sdcard_block2mem_wishbonedmawriter_done; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset0; always @(*) begin sdblock2memdma_next_state <= 2'd0; sdcard_block2mem_sink_sink_last1 <= 1'd0; sdcard_block2mem_sink_sink_payload_address <= 32'd0; sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; sdcard_block2mem_sink_sink_valid1 <= 1'd0; - sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd0; sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; sdblock2memdma_next_state <= sdblock2memdma_state; case (sdblock2memdma_state) 1'd1: begin sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; - sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); - sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset1 + 1'd1) == sdcard_block2mem_wishbonedmawriter_length1)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base1 + sdcard_block2mem_wishbonedmawriter_offset1); sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset1 + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; if (sdcard_block2mem_sink_sink_last1) begin - if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_wishbonedmawriter_loop) begin + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; end else begin sdblock2memdma_next_state <= 2'd2; end @@ -2677,12 +2676,12 @@ always @(*) begin end end 2'd2: begin - sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + sdcard_block2mem_wishbonedmawriter_done <= 1'd1; end default: begin sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce <= 1'd1; sdblock2memdma_next_state <= 1'd1; end endcase @@ -2728,10 +2727,16 @@ assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_sour assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; -assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; -assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; -assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; -assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_base1 = sdcard_mem2block_dma_base0[63:2]; +assign sdcard_mem2block_dma_length1 = sdcard_mem2block_dma_length0[31:2]; +assign sdcard_mem2block_dma_offset0 = sdcard_mem2block_dma_offset1; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable); +assign sdcard_mem2block_dma_base0 = sdcard_mem2block_dma_base_storage; +assign sdcard_mem2block_dma_length0 = sdcard_mem2block_dma_length_storage; +assign sdcard_mem2block_dma_enable = sdcard_mem2block_dma_enable_storage; +assign sdcard_mem2block_dma_loop = sdcard_mem2block_dma_loop_storage; +assign sdcard_mem2block_dma_done_status = sdcard_mem2block_dma_done; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset0; assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; @@ -2760,9 +2765,9 @@ assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdpor assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); always @(*) begin - sdcard_mem2block_dma_done_status <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_done <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd0; sdcard_mem2block_dma_sink_sink_last <= 1'd0; sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; sdcard_mem2block_dma_sink_sink_valid <= 1'd0; @@ -2771,15 +2776,15 @@ always @(*) begin case (sdmem2blockdma_state) 1'd1: begin sdcard_mem2block_dma_sink_sink_valid <= 1'd1; - sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); - sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset1 == (sdcard_mem2block_dma_length1 - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base1 + sdcard_mem2block_dma_offset1); if (sdcard_mem2block_dma_sink_sink_ready) begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset1 + 1'd1); + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; if (sdcard_mem2block_dma_sink_sink_last) begin - if (sdcard_mem2block_dma_loop_storage) begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_loop) begin + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; end else begin sdmem2blockdma_next_state <= 2'd2; end @@ -2787,11 +2792,11 @@ always @(*) begin end end 2'd2: begin - sdcard_mem2block_dma_done_status <= 1'd1; + sdcard_mem2block_dma_done <= 1'd1; end default: begin - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; - sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce <= 1'd1; sdmem2blockdma_next_state <= 1'd1; end endcase @@ -2898,6 +2903,7 @@ always @(*) begin interface0_dat_r <= 32'd0; interface1_adr <= 14'd0; interface1_dat_w <= 32'd0; + interface1_re <= 1'd0; interface1_we <= 1'd0; wishbone2csr_next_state <= 1'd0; wishbone2csr_next_state <= wishbone2csr_state; @@ -2910,7 +2916,8 @@ always @(*) begin default: begin interface1_dat_w <= interface0_dat_w; if ((interface0_cyc & interface0_stb)) begin - interface1_adr <= interface0_adr[29:0]; + interface1_adr <= interface0_adr; + interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); interface1_we <= (interface0_we & (interface0_sel != 1'd0)); wishbone2csr_next_state <= 1'd1; end @@ -2924,25 +2931,25 @@ always @(*) begin csrbank0_reset0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin csrbank0_reset0_re <= interface0_bank_bus_we; - csrbank0_reset0_we <= (~interface0_bank_bus_we); + csrbank0_reset0_we <= interface0_bank_bus_re; end end -assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_scratch0_re <= 1'd0; csrbank0_scratch0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin csrbank0_scratch0_re <= interface0_bank_bus_we; - csrbank0_scratch0_we <= (~interface0_bank_bus_we); + csrbank0_scratch0_we <= interface0_bank_bus_re; end end -assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_bus_errors_re <= 1'd0; csrbank0_bus_errors_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin csrbank0_bus_errors_re <= interface0_bank_bus_we; - csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin @@ -2952,36 +2959,36 @@ always @(*) begin end end assign cpu_rst = reset_storage[1]; -assign csrbank0_reset0_w = reset_storage[1:0]; -assign csrbank0_scratch0_w = scratch_storage[31:0]; -assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign csrbank0_reset0_w = reset_storage; +assign csrbank0_scratch0_w = scratch_storage; +assign csrbank0_bus_errors_w = bus_errors_status; assign bus_errors_we = csrbank0_bus_errors_we; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); -assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_base1_re <= 1'd0; csrbank1_dma_base1_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin csrbank1_dma_base1_re <= interface1_bank_bus_we; - csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + csrbank1_dma_base1_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_base0_re <= 1'd0; csrbank1_dma_base0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin csrbank1_dma_base0_re <= interface1_bank_bus_we; - csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + csrbank1_dma_base0_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_length0_re <= 1'd0; csrbank1_dma_length0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin csrbank1_dma_length0_re <= interface1_bank_bus_we; - csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + csrbank1_dma_length0_we <= interface1_bank_bus_re; end end assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; @@ -2990,7 +2997,7 @@ always @(*) begin csrbank1_dma_enable0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin csrbank1_dma_enable0_re <= interface1_bank_bus_we; - csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + csrbank1_dma_enable0_we <= interface1_bank_bus_re; end end assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; @@ -2999,7 +3006,7 @@ always @(*) begin csrbank1_dma_done_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin csrbank1_dma_done_re <= interface1_bank_bus_we; - csrbank1_dma_done_we <= (~interface1_bank_bus_we); + csrbank1_dma_done_we <= interface1_bank_bus_re; end end assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; @@ -3008,35 +3015,35 @@ always @(*) begin csrbank1_dma_loop0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin csrbank1_dma_loop0_re <= interface1_bank_bus_we; - csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + csrbank1_dma_loop0_we <= interface1_bank_bus_re; end end -assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_dma_offset_re <= 1'd0; csrbank1_dma_offset_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin csrbank1_dma_offset_re <= interface1_bank_bus_we; - csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + csrbank1_dma_offset_we <= interface1_bank_bus_re; end end assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; -assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage; assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; -assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status; assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); -assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_argument0_re <= 1'd0; csrbank2_cmd_argument0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin csrbank2_cmd_argument0_re <= interface2_bank_bus_we; - csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_argument0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; @@ -3045,7 +3052,7 @@ always @(*) begin csrbank2_cmd_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin csrbank2_cmd_command0_re <= interface2_bank_bus_we; - csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_command0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; @@ -3054,43 +3061,43 @@ always @(*) begin csrbank2_cmd_send0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin csrbank2_cmd_send0_re <= interface2_bank_bus_we; - csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_send0_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response3_re <= 1'd0; csrbank2_cmd_response3_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin csrbank2_cmd_response3_re <= interface2_bank_bus_we; - csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response3_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response2_re <= 1'd0; csrbank2_cmd_response2_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin csrbank2_cmd_response2_re <= interface2_bank_bus_we; - csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response2_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response1_re <= 1'd0; csrbank2_cmd_response1_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin csrbank2_cmd_response1_re <= interface2_bank_bus_we; - csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response1_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_cmd_response0_re <= 1'd0; csrbank2_cmd_response0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin csrbank2_cmd_response0_re <= interface2_bank_bus_we; - csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + csrbank2_cmd_response0_we <= interface2_bank_bus_re; end end assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; @@ -3099,7 +3106,7 @@ always @(*) begin csrbank2_cmd_event_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin csrbank2_cmd_event_re <= interface2_bank_bus_we; - csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + csrbank2_cmd_event_we <= interface2_bank_bus_re; end end assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; @@ -3108,7 +3115,7 @@ always @(*) begin csrbank2_data_event_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin csrbank2_data_event_re <= interface2_bank_bus_we; - csrbank2_data_event_we <= (~interface2_bank_bus_we); + csrbank2_data_event_we <= interface2_bank_bus_re; end end assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; @@ -3117,23 +3124,23 @@ always @(*) begin csrbank2_block_length0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin csrbank2_block_length0_re <= interface2_bank_bus_we; - csrbank2_block_length0_we <= (~interface2_bank_bus_we); + csrbank2_block_length0_we <= interface2_bank_bus_re; end end -assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w; always @(*) begin csrbank2_block_count0_re <= 1'd0; csrbank2_block_count0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin csrbank2_block_count0_re <= interface2_bank_bus_we; - csrbank2_block_count0_we <= (~interface2_bank_bus_we); + csrbank2_block_count0_we <= interface2_bank_bus_re; end end -assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage; assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; -assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage; assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; @@ -3147,7 +3154,7 @@ always @(*) begin sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; end -assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status; assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; always @(*) begin sdcard_core_data_event_status <= 4'd0; @@ -3156,10 +3163,10 @@ always @(*) begin sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; end -assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign csrbank2_data_event_w = sdcard_core_data_event_status; assign sdcard_core_data_event_we = csrbank2_data_event_we; -assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; -assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage; assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; always @(*) begin @@ -3167,7 +3174,7 @@ always @(*) begin csrbank3_status_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin csrbank3_status_re <= interface3_bank_bus_we; - csrbank3_status_we <= (~interface3_bank_bus_we); + csrbank3_status_we <= interface3_bank_bus_re; end end assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; @@ -3176,7 +3183,7 @@ always @(*) begin csrbank3_pending_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin csrbank3_pending_re <= interface3_bank_bus_we; - csrbank3_pending_we <= (~interface3_bank_bus_we); + csrbank3_pending_we <= interface3_bank_bus_re; end end assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; @@ -3185,7 +3192,7 @@ always @(*) begin csrbank3_enable0_we <= 1'd0; if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin csrbank3_enable0_re <= interface3_bank_bus_we; - csrbank3_enable0_we <= (~interface3_bank_bus_we); + csrbank3_enable0_we <= interface3_bank_bus_re; end end always @(*) begin @@ -3195,7 +3202,7 @@ always @(*) begin eventmanager_status_status[2] <= eventmanager_mem2block_dma0; eventmanager_status_status[3] <= eventmanager_cmd_done0; end -assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign csrbank3_status_w = eventmanager_status_status; assign eventmanager_status_we = csrbank3_status_we; always @(*) begin eventmanager_pending_status <= 4'd0; @@ -3204,39 +3211,39 @@ always @(*) begin eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; eventmanager_pending_status[3] <= eventmanager_cmd_done1; end -assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign csrbank3_pending_w = eventmanager_pending_status; assign eventmanager_pending_we = csrbank3_pending_we; assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; -assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank3_enable0_w = eventmanager_enable_storage; assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); -assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_base1_re <= 1'd0; csrbank4_dma_base1_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin csrbank4_dma_base1_re <= interface4_bank_bus_we; - csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + csrbank4_dma_base1_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_base0_re <= 1'd0; csrbank4_dma_base0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin csrbank4_dma_base0_re <= interface4_bank_bus_we; - csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + csrbank4_dma_base0_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_length0_re <= 1'd0; csrbank4_dma_length0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin csrbank4_dma_length0_re <= interface4_bank_bus_we; - csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + csrbank4_dma_length0_we <= interface4_bank_bus_re; end end assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; @@ -3245,7 +3252,7 @@ always @(*) begin csrbank4_dma_enable0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin csrbank4_dma_enable0_re <= interface4_bank_bus_we; - csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + csrbank4_dma_enable0_we <= interface4_bank_bus_re; end end assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; @@ -3254,7 +3261,7 @@ always @(*) begin csrbank4_dma_done_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin csrbank4_dma_done_re <= interface4_bank_bus_we; - csrbank4_dma_done_we <= (~interface4_bank_bus_we); + csrbank4_dma_done_we <= interface4_bank_bus_re; end end assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; @@ -3263,26 +3270,26 @@ always @(*) begin csrbank4_dma_loop0_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin csrbank4_dma_loop0_re <= interface4_bank_bus_we; - csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + csrbank4_dma_loop0_we <= interface4_bank_bus_re; end end -assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w; always @(*) begin csrbank4_dma_offset_re <= 1'd0; csrbank4_dma_offset_we <= 1'd0; if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin csrbank4_dma_offset_re <= interface4_bank_bus_we; - csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + csrbank4_dma_offset_we <= interface4_bank_bus_re; end end assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; -assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage; assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; -assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status; assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; @@ -3291,7 +3298,7 @@ always @(*) begin csrbank5_card_detect_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin csrbank5_card_detect_re <= interface5_bank_bus_we; - csrbank5_card_detect_we <= (~interface5_bank_bus_we); + csrbank5_card_detect_we <= interface5_bank_bus_re; end end assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; @@ -3300,7 +3307,7 @@ always @(*) begin csrbank5_clocker_divider0_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin csrbank5_clocker_divider0_re <= interface5_bank_bus_we; - csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + csrbank5_clocker_divider0_we <= interface5_bank_bus_re; end end assign init_initialize_r = interface5_bank_bus_dat_w[0]; @@ -3309,7 +3316,7 @@ always @(*) begin init_initialize_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin init_initialize_re <= interface5_bank_bus_we; - init_initialize_we <= (~interface5_bank_bus_we); + init_initialize_we <= interface5_bank_bus_re; end end assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; @@ -3318,21 +3325,22 @@ always @(*) begin csrbank5_dataw_status_we <= 1'd0; if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin csrbank5_dataw_status_re <= interface5_bank_bus_we; - csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + csrbank5_dataw_status_we <= interface5_bank_bus_re; end end assign csrbank5_card_detect_w = card_detect_status0; assign card_detect_we = csrbank5_card_detect_we; -assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +assign csrbank5_clocker_divider0_w = clocker_storage; always @(*) begin dataw_status <= 3'd0; dataw_status[0] <= dataw_accepted0; dataw_status[1] <= dataw_crc_error0; dataw_status[2] <= dataw_write_error0; end -assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign csrbank5_dataw_status_w = dataw_status; assign dataw_we = csrbank5_dataw_status_we; assign adr = interface1_adr; +assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; @@ -3342,6 +3350,12 @@ assign interface2_bank_bus_adr = adr; assign interface3_bank_bus_adr = adr; assign interface4_bank_bus_adr = adr; assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_re = re; +assign interface1_bank_bus_re = re; +assign interface2_bank_bus_re = re; +assign interface3_bank_bus_re = re; +assign interface4_bank_bus_re = re; +assign interface5_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface2_bank_bus_we = we; @@ -3444,6 +3458,8 @@ always @(*) begin endcase end assign sdrio_clk = sys_clk; +assign clk_i = xilinxmultiregimpl_xilinxmultiregimpl; +assign xilinxmultiregimpl = (~clocker_clk0); assign sdrio_clk_1 = sys_clk; assign sdrio_clk_2 = sys_clk; assign sdrio_clk_3 = sys_clk; @@ -3457,11 +3473,11 @@ assign sdrio_clk_10 = sys_clk; assign sdrio_clk_11 = sys_clk; assign sdrio_clk_12 = sys_clk; assign sdrio_clk_13 = sys_clk; +assign sdrio_clk_14 = sys_clk; assign sdrio_clk_15 = sys_clk; assign sdrio_clk_16 = sys_clk; assign sdrio_clk_17 = sys_clk; assign sdrio_clk_18 = sys_clk; -assign sdrio_clk_14 = sys_clk; //------------------------------------------------------------------------------ @@ -3527,7 +3543,11 @@ always @(posedge sys_clk) begin card_detect_d <= card_detect_status0; card_detect_irq <= (card_detect_status0 ^ card_detect_d); if ((~clocker_stop)) begin - clocker_clks <= (clocker_clks + 1'd1); + clocker_count <= (clocker_count + 1'd1); + if ((clocker_count >= (clocker_storage[8:1] - 1'd1))) begin + clocker_clk1 <= (~clocker_clk1); + clocker_count <= 1'd0; + end end clocker_clk_d <= clocker_clk1; if (clocker_clk_d) begin @@ -3781,8 +3801,7 @@ always @(posedge sys_clk) begin if (datar_datar_reset_sdphydatar_next_value_ce2) begin datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; end - clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; - sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + clk_i_d <= clk_i; sdcard_core_done_d <= sdcard_core_cmd_done; sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); if (sdcard_core_crc7_inserter_crc_reset) begin @@ -3948,11 +3967,11 @@ always @(posedge sys_clk) begin sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); end sdblock2memdma_state <= sdblock2memdma_next_state; - if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin - sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + if (sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset1 <= sdcard_block2mem_wishbonedmawriter_offset1_sdblock2memdma_next_value; end if (sdcard_block2mem_wishbonedmawriter_reset) begin - sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset1 <= 32'd0; sdblock2memdma_state <= 2'd0; end if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin @@ -3979,11 +3998,11 @@ always @(posedge sys_clk) begin end end sdmem2blockdma_state <= sdmem2blockdma_next_state; - if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin - sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + if (sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset1 <= sdcard_mem2block_dma_offset1_sdmem2blockdma_next_value; end if (sdcard_mem2block_dma_reset) begin - sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_dma_offset1 <= 32'd0; sdmem2blockdma_state <= 2'd0; end if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin @@ -4049,11 +4068,11 @@ always @(posedge sys_clk) begin endcase end if (csrbank0_reset0_re) begin - reset_storage[1:0] <= csrbank0_reset0_r; + reset_storage <= csrbank0_reset0_r; end reset_re <= csrbank0_reset0_re; if (csrbank0_scratch0_re) begin - scratch_storage[31:0] <= csrbank0_scratch0_r; + scratch_storage <= csrbank0_scratch0_r; end scratch_re <= csrbank0_scratch0_re; bus_errors_re <= csrbank0_bus_errors_re; @@ -4091,7 +4110,7 @@ always @(posedge sys_clk) begin end sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; if (csrbank1_dma_length0_re) begin - sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + sdcard_block2mem_wishbonedmawriter_length_storage <= csrbank1_dma_length0_r; end sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; if (csrbank1_dma_enable0_re) begin @@ -4143,11 +4162,11 @@ always @(posedge sys_clk) begin endcase end if (csrbank2_cmd_argument0_re) begin - sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + sdcard_core_cmd_argument_storage <= csrbank2_cmd_argument0_r; end sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; if (csrbank2_cmd_command0_re) begin - sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + sdcard_core_cmd_command_storage <= csrbank2_cmd_command0_r; end sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; if (csrbank2_cmd_send0_re) begin @@ -4158,11 +4177,11 @@ always @(posedge sys_clk) begin sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; sdcard_core_data_event_re <= csrbank2_data_event_re; if (csrbank2_block_length0_re) begin - sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + sdcard_core_block_length_storage <= csrbank2_block_length0_r; end sdcard_core_block_length_re <= csrbank2_block_length0_re; if (csrbank2_block_count0_re) begin - sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + sdcard_core_block_count_storage <= csrbank2_block_count0_r; end sdcard_core_block_count_re <= csrbank2_block_count0_re; interface3_bank_bus_dat_r <= 1'd0; @@ -4181,11 +4200,11 @@ always @(posedge sys_clk) begin end eventmanager_status_re <= csrbank3_status_re; if (csrbank3_pending_re) begin - eventmanager_pending_r[3:0] <= csrbank3_pending_r; + eventmanager_pending_r <= csrbank3_pending_r; end eventmanager_pending_re <= csrbank3_pending_re; if (csrbank3_enable0_re) begin - eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + eventmanager_enable_storage <= csrbank3_enable0_r; end eventmanager_enable_re <= csrbank3_enable0_re; interface4_bank_bus_dat_r <= 1'd0; @@ -4222,7 +4241,7 @@ always @(posedge sys_clk) begin end sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; if (csrbank4_dma_length0_re) begin - sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + sdcard_mem2block_dma_length_storage <= csrbank4_dma_length0_r; end sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; if (csrbank4_dma_enable0_re) begin @@ -4254,7 +4273,7 @@ always @(posedge sys_clk) begin end card_detect_re <= csrbank5_card_detect_re; if (csrbank5_clocker_divider0_re) begin - clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + clocker_storage <= csrbank5_clocker_divider0_r; end clocker_re <= csrbank5_clocker_divider0_re; dataw_re <= csrbank5_dataw_status_re; @@ -4268,7 +4287,8 @@ always @(posedge sys_clk) begin card_detect_re <= 1'd0; clocker_storage <= 9'd256; clocker_re <= 1'd0; - clocker_clks <= 9'd0; + clocker_clk1 <= 1'd0; + clocker_count <= 10'd0; clocker_clk_d <= 1'd0; clocker_ce_delayed <= 1'd0; init_count <= 8'd0; @@ -4306,8 +4326,7 @@ always @(posedge sys_clk) begin datar_datar_buf_pipe_valid_source_valid <= 1'd0; datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; datar_datar_reset <= 1'd0; - sdpads_data_i_ce <= 1'd0; - clocker_clk_delay <= 2'd0; + clk_i_d <= 1'd0; card_detect_irq <= 1'd0; card_detect_d <= 1'd0; sdcard_core_irq <= 1'd0; @@ -4352,6 +4371,7 @@ always @(posedge sys_clk) begin sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; sdcard_block2mem_converter_demux <= 2'd0; sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset1 <= 32'd0; sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; @@ -4362,13 +4382,13 @@ always @(posedge sys_clk) begin sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; - sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; sdcard_block2mem_connect <= 1'd0; sdcard_block2mem_done_d <= 1'd0; sdcard_mem2block_irq <= 1'd0; sdcard_mem2block_dma_fifo_level <= 5'd0; sdcard_mem2block_dma_fifo_produce <= 4'd0; sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_offset1 <= 32'd0; sdcard_mem2block_dma_base_storage <= 64'd0; sdcard_mem2block_dma_base_re <= 1'd0; sdcard_mem2block_dma_length_storage <= 32'd0; @@ -4379,7 +4399,6 @@ always @(posedge sys_clk) begin sdcard_mem2block_dma_loop_storage <= 1'd0; sdcard_mem2block_dma_loop_re <= 1'd0; sdcard_mem2block_dma_offset_re <= 1'd0; - sdcard_mem2block_dma_offset <= 32'd0; sdcard_mem2block_converter_converter_mux <= 2'd0; sdcard_mem2block_fifo_readable <= 1'd0; sdcard_mem2block_fifo_level0 <= 10'd0; @@ -4409,6 +4428,7 @@ always @(posedge sys_clk) begin sdmem2blockdma_state <= 2'd0; wishbone2csr_state <= 1'd0; end + xilinxmultiregimpl_xilinxmultiregimpl <= (~clocker_clk0); end @@ -4416,17 +4436,6 @@ end // Specialized Logic //------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -// Instance BUFG of BUFG Module. -//------------------------------------------------------------------------------ -BUFG BUFG( - // Inputs. - .I ((clocker_clk1 & (~clocker_clk_d))), - - // Outputs. - .O (clocker_ce) -); - //------------------------------------------------------------------------------ // Memory storage: 8-words x 10-bit //------------------------------------------------------------------------------ @@ -4583,5 +4592,5 @@ IOBUF IOBUF_4( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2024-04-03 20:02:06. +// Auto-Generated by LiteX on 2025-02-17 09:51:44. //------------------------------------------------------------------------------