From 63295526ad7bf7011633456e60a640ee2757f9c9 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 8 Sep 2019 09:49:39 +1000 Subject: [PATCH] Add CONFIG_VOLTAGE and CFGBVS entries Remove a couple of warnings from Vivado. Signed-off-by: Anton Blanchard --- fpga/arty_a7-35.xdc | 3 +++ fpga/nexys_a7.xdc | 3 +++ 2 files changed, 6 insertions(+) diff --git a/fpga/arty_a7-35.xdc b/fpga/arty_a7-35.xdc index f8280b9..e465b39 100644 --- a/fpga/arty_a7-35.xdc +++ b/fpga/arty_a7-35.xdc @@ -5,3 +5,6 @@ set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { reset_ set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }]; + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc index b94f1bc..a657a21 100644 --- a/fpga/nexys_a7.xdc +++ b/fpga/nexys_a7.xdc @@ -5,3 +5,6 @@ set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_n] set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd] set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design]