From d2762e70e5fb519d8fcca210b366c9c8bbdd696a Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 21 Oct 2019 15:15:07 +1100 Subject: [PATCH] Add option to not flatten hierarchy Vivado by default tries to flatten the module hierarchy to improve placement and timing. However this makes debugging timing issues really hard as the net names in the timing report can be pretty bogus. This adds a generic that can be used to control attributes to stop vivado from flattening the main core components. The resulting design will have worst timing overall but it will be easier to understand what the worst timing path are and address them. Signed-off-by: Benjamin Herrenschmidt --- core.vhdl | 26 +++++++++++++++++++++++++- fpga/toplevel.vhdl | 6 ++++-- microwatt.core | 11 +++++++++++ soc.vhdl | 6 ++++-- 4 files changed, 44 insertions(+), 5 deletions(-) diff --git a/core.vhdl b/core.vhdl index 810a279..22f7dca 100644 --- a/core.vhdl +++ b/core.vhdl @@ -8,7 +8,8 @@ use work.wishbone_types.all; entity core is generic ( - SIM : boolean := false + SIM : boolean := false; + DISABLE_FLATTEN : boolean := false ); port ( clk : in std_logic; @@ -93,6 +94,29 @@ architecture behave of core is -- Debug status signal dbg_core_is_stopped: std_ulogic; + function keep_h(disable : boolean) return string is + begin + if disable then + return "yes"; + else + return "no"; + end if; + end function; + attribute keep_hierarchy : string; + attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of multiply_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of divider_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN); + attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN); begin core_rst <= dbg_core_rst or rst; diff --git a/fpga/toplevel.vhdl b/fpga/toplevel.vhdl index d73c802..38af730 100644 --- a/fpga/toplevel.vhdl +++ b/fpga/toplevel.vhdl @@ -7,7 +7,8 @@ entity toplevel is RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_INPUT : positive := 100000000; - CLK_FREQUENCY : positive := 100000000 + CLK_FREQUENCY : positive := 100000000; + DISABLE_FLATTEN_CORE : boolean := false ); port( ext_clk : in std_ulogic; @@ -62,7 +63,8 @@ begin MEMORY_SIZE => MEMORY_SIZE, RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, - SIM => false + SIM => false, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( system_clk => system_clk, diff --git a/microwatt.core b/microwatt.core index 5fb9a7a..35ada86 100644 --- a/microwatt.core +++ b/microwatt.core @@ -93,6 +93,7 @@ targets: - ram_init_file - clk_input - clk_frequency + - disable_flatten_core tools: vivado: {part : xc7a100tcsg324-1} toplevel : toplevel @@ -105,6 +106,7 @@ targets: - ram_init_file - clk_input - clk_frequency + - disable_flatten_core tools: vivado: {part : xc7a200tsbg484-1} toplevel : toplevel @@ -117,6 +119,7 @@ targets: - ram_init_file - clk_input - clk_frequency + - disable_flatten_core tools: vivado: {part : xc7a35ticsg324-1L} toplevel : toplevel @@ -129,6 +132,7 @@ targets: - ram_init_file - clk_input - clk_frequency + - disable_flatten_core tools: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel @@ -142,6 +146,7 @@ targets: - reset_low=false - clk_input=12000000 - clk_frequency + - disable_flatten_core tools: vivado: {part : xc7a35tcpg236-1} toplevel : toplevel @@ -179,3 +184,9 @@ parameters: description : Generated system clock frequency in HZ (for top-generic based boards) paramtype : generic default : 50000000 + + disable_flatten_core: + datatype : bool + description : Prevent Vivado from flattening the main core components + paramtype : generic + default : false diff --git a/soc.vhdl b/soc.vhdl index 950d0dd..b9a8215 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -17,7 +17,8 @@ entity soc is MEMORY_SIZE : positive; RAM_INIT_FILE : string; RESET_LOW : boolean; - SIM : boolean + SIM : boolean; + DISABLE_FLATTEN_CORE : boolean := false ); port( rst : in std_ulogic; @@ -76,7 +77,8 @@ begin -- Processor core processor: entity work.core generic map( - SIM => SIM + SIM => SIM, + DISABLE_FLATTEN => DISABLE_FLATTEN_CORE ) port map( clk => system_clk,