From d745995207b121e6b53a104c9ddfc8b9840693a2 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 27 Sep 2021 21:50:57 +1000 Subject: [PATCH] Introduce real_addr_t and addr_to_real() This moves REAL_ADDR_BITS out of the caches and defines a real_addr_t type for a real address, along with a addr_to_real() conversion helper. It makes the vhdl a bit more readable Signed-off-by: Benjamin Herrenschmidt --- common.vhdl | 11 +++++++++++ dcache.vhdl | 10 ++++------ icache.vhdl | 8 +++----- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/common.vhdl b/common.vhdl index 2d010ab..fb60ce3 100644 --- a/common.vhdl +++ b/common.vhdl @@ -156,6 +156,12 @@ package common is constant FPSCR_NI : integer := 63 - 61; constant FPSCR_RN : integer := 63 - 63; + -- Real addresses + -- REAL_ADDR_BITS is the number of real address bits that we store + constant REAL_ADDR_BITS : positive := 56; + subtype real_addr_t is std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t; + -- Used for tracking instruction completion and pending register writes constant TAG_COUNT : positive := 4; constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT); @@ -779,4 +785,9 @@ package body common is begin return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag; end; + + function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t is + begin + return addr(real_addr_t'range); + end; end common; diff --git a/dcache.vhdl b/dcache.vhdl index 34dbda2..489ccb5 100644 --- a/dcache.vhdl +++ b/dcache.vhdl @@ -67,8 +67,6 @@ architecture rtl of dcache is -- Bit fields counts in the address - -- REAL_ADDR_BITS is the number of real address bits that we store - constant REAL_ADDR_BITS : positive := 56; -- ROW_BITS is the number of bits to select a row constant ROW_BITS : natural := log2(BRAM_ROWS); -- ROW_LINEBITS is the number of bits to select a row within a line @@ -289,7 +287,7 @@ architecture rtl of dcache is op : op_t; valid : std_ulogic; dcbz : std_ulogic; - real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + real_addr : real_addr_t; data : std_ulogic_vector(63 downto 0); byte_sel : std_ulogic_vector(7 downto 0); hit_way : way_t; @@ -412,7 +410,7 @@ architecture rtl of dcache is signal tlb_hit : std_ulogic; signal tlb_hit_way : tlb_way_t; signal pte : tlb_pte_t; - signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + signal ra : real_addr_t; signal valid_ra : std_ulogic; signal perm_attr : perm_attr_t; signal rc_ok : std_ulogic; @@ -803,7 +801,7 @@ begin -- Cache tag RAM second read port, for snooping cache_tag_read_2 : process(clk) - variable addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + variable addr : real_addr_t; begin if rising_edge(clk) then addr := (others => '0'); @@ -830,7 +828,7 @@ begin variable s_hit : std_ulogic; variable s_tag : cache_tag_t; variable s_pte : tlb_pte_t; - variable s_ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + variable s_ra : real_addr_t; variable hit_set : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0); variable hit_way_set : hit_way_set_t; variable rel_matches : std_ulogic_vector(TLB_NUM_WAYS - 1 downto 0); diff --git a/icache.vhdl b/icache.vhdl index 298ee47..ecd0c84 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -46,8 +46,6 @@ entity icache is TLB_SIZE : positive := 64; -- L1 ITLB log_2(page_size) TLB_LG_PGSZ : positive := 12; - -- Number of real address bits that we store - REAL_ADDR_BITS : positive := 56; -- Non-zero to enable log data collection LOG_LENGTH : natural := 0 ); @@ -210,7 +208,7 @@ architecture rtl of icache is signal req_laddr : std_ulogic_vector(63 downto 0); signal tlb_req_index : tlb_index_t; - signal real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + signal real_addr : real_addr_t; signal ra_valid : std_ulogic; signal priv_fault : std_ulogic; signal access_ok : std_ulogic; @@ -468,7 +466,7 @@ begin end if; eaa_priv <= pte(3); else - real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0); + real_addr <= addr_to_real(i_in.nia); ra_valid <= '1'; eaa_priv <= '1'; end if; @@ -627,7 +625,7 @@ begin icache_miss : process(clk) variable tagset : cache_tags_set_t; variable tag : cache_tag_t; - variable snoop_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0); + variable snoop_addr : real_addr_t; variable snoop_tag : cache_tag_t; variable snoop_cache_tags : cache_tags_set_t; begin