diff --git a/core.vhdl b/core.vhdl
index f4fe302..eb0b526 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -143,6 +143,7 @@ begin
 
     icache_0: entity work.icache
         generic map(
+            SIM => SIM,
             LINE_SIZE => 64,
             NUM_LINES => 32,
 	    NUM_WAYS => 2
diff --git a/icache.vhdl b/icache.vhdl
index 20d5724..343c73a 100644
--- a/icache.vhdl
+++ b/icache.vhdl
@@ -29,6 +29,7 @@ use work.wishbone_types.all;
 
 entity icache is
     generic (
+        SIM : boolean := false;
         -- Line size in bytes
         LINE_SIZE : positive := 64;
         -- Number of lines in a set
@@ -264,6 +265,7 @@ begin
     assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
 	report "geometry bits don't add up" severity FAILURE;
 
+    sim_debug: if SIM generate
     debug: process
     begin
 	report "ROW_SIZE      = " & natural'image(ROW_SIZE);
@@ -280,6 +282,7 @@ begin
 	report "WAY_BITS      = " & natural'image(WAY_BITS);
 	wait;
     end process;
+    end generate;
 
     -- Generate a cache RAM for each way
     rams: for i in 0 to NUM_WAYS-1 generate