From caf458be377b4509ec7c779d753ebd77514fbca8 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 28 Jul 2022 09:50:26 +1000 Subject: [PATCH 01/15] Metavalue cleanup for common.vhdl This affects other files which have been included here. Signed-off-by: Michael Neuling --- common.vhdl | 35 ++++++++++++++++++----------------- core_debug.vhdl | 4 ++-- decode1.vhdl | 2 +- decode2.vhdl | 4 ++-- execute1.vhdl | 30 ++++++++++++++++++++---------- 5 files changed, 43 insertions(+), 32 deletions(-) diff --git a/common.vhdl b/common.vhdl index cc49e8f..4f8191e 100644 --- a/common.vhdl +++ b/common.vhdl @@ -115,28 +115,29 @@ package common is -- Some SPRs are stored in a pair of small RAMs in execute1 -- Even half: - subtype ramspr_index is natural range 0 to 7; - constant RAMSPR_SRR0 : ramspr_index := 0; - constant RAMSPR_HSRR0 : ramspr_index := 1; - constant RAMSPR_SPRG0 : ramspr_index := 2; - constant RAMSPR_SPRG2 : ramspr_index := 3; - constant RAMSPR_HSPRG0 : ramspr_index := 4; - constant RAMSPR_LR : ramspr_index := 5; -- must equal RAMSPR_CTR - constant RAMSPR_TAR : ramspr_index := 6; + subtype ramspr_index_range is natural range 0 to 7; + subtype ramspr_index is unsigned(2 downto 0); + constant RAMSPR_SRR0 : ramspr_index := to_unsigned(0,3); + constant RAMSPR_HSRR0 : ramspr_index := to_unsigned(1,3); + constant RAMSPR_SPRG0 : ramspr_index := to_unsigned(2,3); + constant RAMSPR_SPRG2 : ramspr_index := to_unsigned(3,3); + constant RAMSPR_HSPRG0 : ramspr_index := to_unsigned(4,3); + constant RAMSPR_LR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_CTR + constant RAMSPR_TAR : ramspr_index := to_unsigned(6,3); -- Odd half: - constant RAMSPR_SRR1 : ramspr_index := 0; - constant RAMSPR_HSRR1 : ramspr_index := 1; - constant RAMSPR_SPRG1 : ramspr_index := 2; - constant RAMSPR_SPRG3 : ramspr_index := 3; - constant RAMSPR_HSPRG1 : ramspr_index := 4; - constant RAMSPR_CTR : ramspr_index := 5; -- must equal RAMSPR_LR + constant RAMSPR_SRR1 : ramspr_index := to_unsigned(0,3); + constant RAMSPR_HSRR1 : ramspr_index := to_unsigned(1,3); + constant RAMSPR_SPRG1 : ramspr_index := to_unsigned(2,3); + constant RAMSPR_SPRG3 : ramspr_index := to_unsigned(3,3); + constant RAMSPR_HSPRG1 : ramspr_index := to_unsigned(4,3); + constant RAMSPR_CTR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_LR type ram_spr_info is record index : ramspr_index; isodd : std_ulogic; valid : std_ulogic; end record; - constant ram_spr_info_init: ram_spr_info := (index => 0, others => '0'); + constant ram_spr_info_init: ram_spr_info := (index => to_unsigned(0,3), others => '0'); subtype spr_selector is std_ulogic_vector(2 downto 0); type spr_id is record @@ -366,8 +367,8 @@ package common is result_sel => "000", sub_select => "000", repeat => '0', second => '0', spr_select => spr_id_init, spr_is_ram => '0', - ramspr_even_rdaddr => 0, ramspr_odd_rdaddr => 0, ramspr_rd_odd => '0', - ramspr_wraddr => 0, ramspr_write_even => '0', ramspr_write_odd => '0', + ramspr_even_rdaddr => (others => '0'), ramspr_odd_rdaddr => (others => '0'), ramspr_rd_odd => '0', + ramspr_wraddr => (others => '0'), ramspr_write_even => '0', ramspr_write_odd => '0', dbg_spr_access => '0', dec_ctr => '0', others => (others => '0')); diff --git a/core_debug.vhdl b/core_debug.vhdl index c060f74..c9c3f40 100644 --- a/core_debug.vhdl +++ b/core_debug.vhdl @@ -273,7 +273,7 @@ begin valid := '1'; sel := "000"; isram := '1'; - raddr := 0; + raddr := (others => '0'); odd := '0'; case gspr_index(4 downto 0) is when 5x"00" => @@ -304,7 +304,7 @@ begin when others => valid := '0'; end case; - dbg_spr_addr <= isram & sel & std_ulogic_vector(to_unsigned(raddr, 3)) & odd; + dbg_spr_addr <= isram & sel & std_ulogic_vector(raddr) & odd; spr_index_valid <= valid; end if; end process; diff --git a/decode1.vhdl b/decode1.vhdl index de9b836..e3ba256 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -530,7 +530,7 @@ architecture behaviour of decode1 is function decode_ram_spr(sprn : spr_num_t) return ram_spr_info is variable ret : ram_spr_info; begin - ret := (index => 0, isodd => '0', valid => '1'); + ret := (index => (others => '0'), isodd => '0', valid => '1'); case sprn is when SPR_LR => ret.index := RAMSPR_LR; diff --git a/decode2.vhdl b/decode2.vhdl index e24ebb5..1392aae 100644 --- a/decode2.vhdl +++ b/decode2.vhdl @@ -671,8 +671,8 @@ begin v.e.dbg_spr_access := dbg_spr_req and not v.read_rspr; if v.e.dbg_spr_access = '1' then - v.e.ramspr_even_rdaddr := to_integer(unsigned(dbg_spr_addr(3 downto 1))); - v.e.ramspr_odd_rdaddr := to_integer(unsigned(dbg_spr_addr(3 downto 1))); + v.e.ramspr_even_rdaddr := unsigned(dbg_spr_addr(3 downto 1)); + v.e.ramspr_odd_rdaddr := unsigned(dbg_spr_addr(3 downto 1)); v.e.ramspr_rd_odd := dbg_spr_addr(0); end if; diff --git a/execute1.vhdl b/execute1.vhdl index 20efef6..43e79b4 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -147,7 +147,7 @@ architecture behaviour of execute1 is taken_branch_event => '0', br_mispredict => '0', msr => 64x"0", xerc => xerc_init, xerc_valid => '0', - ramspr_wraddr => 0, ramspr_odd_data => 64x"0"); + ramspr_wraddr => (others => '0'), ramspr_odd_data => 64x"0"); type reg_stage2_type is record e : Execute1ToWritebackType; @@ -221,7 +221,7 @@ architecture behaviour of execute1 is signal irq_valid_log : std_ulogic; -- SPR-related signals - type ramspr_half_t is array(ramspr_index) of std_ulogic_vector(63 downto 0); + type ramspr_half_t is array(ramspr_index_range) of std_ulogic_vector(63 downto 0); signal even_sprs : ramspr_half_t := (others => (others => '0')); signal odd_sprs : ramspr_half_t := (others => (others => '0')); signal ramspr_even : std_ulogic_vector(63 downto 0); @@ -510,8 +510,16 @@ begin variable doit : std_ulogic; begin -- Read address mux and async RAM reading - even_rd_data := even_sprs(e_in.ramspr_even_rdaddr); - odd_rd_data := odd_sprs(e_in.ramspr_odd_rdaddr); + if is_X(e_in.ramspr_even_rdaddr) then + even_rd_data := (others => 'X'); + else + even_rd_data := even_sprs(to_integer(e_in.ramspr_even_rdaddr)); + end if; + if is_X(e_in.ramspr_even_rdaddr) then + odd_rd_data := (others => 'X'); + else + odd_rd_data := odd_sprs(to_integer(e_in.ramspr_odd_rdaddr)); + end if; -- Write address and data muxes doit := ex1.e.valid and not stage2_stall and not flush_in; @@ -559,13 +567,15 @@ begin begin if rising_edge(clk) then if ramspr_even_wr_enab = '1' then - even_sprs(ramspr_wr_addr) <= ramspr_even_wr_data; - report "writing even spr " & integer'image(ramspr_wr_addr) & " data=" & + assert not is_X(ramspr_wr_addr) report "Writing to unknown address" severity FAILURE; + even_sprs(to_integer(ramspr_wr_addr)) <= ramspr_even_wr_data; + report "writing even spr " & integer'image(to_integer(ramspr_wr_addr)) & " data=" & to_hstring(ramspr_even_wr_data); end if; if ramspr_odd_wr_enab = '1' then - odd_sprs(ramspr_wr_addr) <= ramspr_odd_wr_data; - report "writing odd spr " & integer'image(ramspr_wr_addr) & " data=" & + assert not is_X(ramspr_wr_addr) report "Writing to unknown address" severity FAILURE; + odd_sprs(to_integer(ramspr_wr_addr)) <= ramspr_odd_wr_data; + report "writing odd spr " & integer'image(to_integer(ramspr_wr_addr)) & " data=" & to_hstring(ramspr_odd_wr_data); end if; end if; @@ -1773,8 +1783,8 @@ begin variable xer : std_ulogic_vector(63 downto 0); begin if sim_dump = '1' then - report "LR " & to_hstring(even_sprs(RAMSPR_LR)); - report "CTR " & to_hstring(odd_sprs(RAMSPR_CTR)); + report "LR " & to_hstring(even_sprs(to_integer(RAMSPR_LR))); + report "CTR " & to_hstring(odd_sprs(to_integer(RAMSPR_CTR))); sim_dump_done <= '1'; else sim_dump_done <= '0'; From 7656abd7650cb8185b6f67b7ad6162bd37526684 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:29:11 +1000 Subject: [PATCH 02/15] Metavalue cleanup for helpers.vhdl Signed-off-by: Michael Neuling --- helpers.vhdl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/helpers.vhdl b/helpers.vhdl index bb69927..92c10dc 100644 --- a/helpers.vhdl +++ b/helpers.vhdl @@ -162,7 +162,9 @@ package body helpers is function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector is begin - if to_integer(unsigned(reg)) = 0 then + if is_X(reg) then + return x"XXXXXXXXXXXXXXXX"; + elsif to_integer(unsigned(reg)) = 0 then return x"0000000000000000"; else return ra; From 602ba25c7070665d2ac99e9d6de3897ae2f2c3e7 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:30:57 +1000 Subject: [PATCH 03/15] Metavalue cleanup for decoder1.vhdl Signed-off-by: Michael Neuling --- decode1.vhdl | 102 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 75 insertions(+), 27 deletions(-) diff --git a/decode1.vhdl b/decode1.vhdl index e3ba256..b2c6059 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -36,6 +36,8 @@ architecture behaviour of decode1 is constant illegal_inst : decode_rom_t := (NONE, NONE, OP_ILLEGAL, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE); + constant x_inst : decode_rom_t := + (NONE, NONE, OP_ILLEGAL, NONE, NONE, NONE, NONE, 'X', 'X', 'X', 'X', ZERO, 'X', NONE, 'X', 'X', 'X', 'X', 'X', 'X', NONE, 'X', 'X', NONE); -- If we have an FPU, then it is used for integer divisions, -- otherwise a dedicated divider in the ALU is used. @@ -664,14 +666,23 @@ begin br_offset := (others => '0'); majorop := unsigned(f_in.insn(31 downto 26)); - v.decode := major_decode_rom_array(to_integer(majorop)); - - sprn := decode_spr_num(f_in.insn); - v.spr_info := map_spr(sprn); - v.ram_spr := decode_ram_spr(sprn); + if is_X(majorop) then + v.decode := x_inst; + else + v.decode := major_decode_rom_array(to_integer(majorop)); + end if; - case to_integer(unsigned(majorop)) is - when 4 => + if is_X(f_in.insn) then + v.spr_info := (sel => "XXX", others => 'X'); + v.ram_spr := (index => (others => 'X'), others => 'X'); + else + sprn := decode_spr_num(f_in.insn); + v.spr_info := map_spr(sprn); + v.ram_spr := decode_ram_spr(sprn); + end if; + + case unsigned(majorop) is + when "000100" => -- 4 -- major opcode 4, mostly VMX/VSX stuff but also some integer ops (madd*) minor4op := f_in.insn(5 downto 0) & f_in.insn(10 downto 6); vi.override := not decode_op_4_valid(to_integer(unsigned(minor4op))); @@ -679,13 +690,17 @@ begin in3rc := '1'; may_read_rb := '1'; - when 23 => + when "010111" => -- 23 -- rlwnm[.] may_read_rb := '1'; - when 31 => + when "011111" => -- 31 -- major opcode 31, lots of things - v.decode := decode_op_31_array(to_integer(unsigned(f_in.insn(10 downto 1)))); + if is_X(f_in.insn) then + v.decode := x_inst; + else + v.decode := decode_op_31_array(to_integer(unsigned(f_in.insn(10 downto 1)))); + end if; may_read_rb := '1'; if std_match(f_in.insn(10 downto 1), "01-1010011") then @@ -705,28 +720,43 @@ begin end if; when others => end case; + -- FIXME: This is a bit fragile doing this here but sprn depends + -- on f_in.insn + if is_X(f_in.insn) then + vi.override_decode.unit := NONE; + vi.override_unit := 'X'; + vi.force_single := 'X'; + end if; end if; if HAS_FPU and std_match(f_in.insn(10 downto 1), "1----10111") then -- lower half of column 23 has FP loads and stores fprs := '1'; end if; - when 16 => + when "010000" => -- 16 -- Predict backward branches as taken, forward as untaken v.br_pred := f_in.insn(15); br_offset := resize(signed(f_in.insn(15 downto 2)), 24); - when 18 => + when "010010" => -- 18 -- Unconditional branches are always taken v.br_pred := '1'; br_offset := signed(f_in.insn(25 downto 2)); - when 19 => - vi.override := not decode_op_19_valid(to_integer(unsigned(f_in.insn(5 downto 1) & f_in.insn(10 downto 6)))); + when "010011" => -- 19 + if is_X(f_in.insn) then + vi.override := 'X'; + else + vi.override := not decode_op_19_valid(to_integer(unsigned(f_in.insn(5 downto 1) & f_in.insn(10 downto 6)))); + end if; op_19_bits := f_in.insn(5) & f_in.insn(3) & f_in.insn(2); - v.decode := decode_op_19_array(to_integer(unsigned(op_19_bits))); + if is_X(op_19_bits) then + v.decode := x_inst; + else + v.decode := decode_op_19_array(to_integer(unsigned(op_19_bits))); + end if; - when 24 => + when "011000" => -- 24 -- ori, special-case the standard NOP if std_match(f_in.insn, "01100000000000000000000000000000") then report "PPC_nop"; @@ -734,23 +764,35 @@ begin vi.override_decode := nop_instr; end if; - when 30 => - v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4 downto 1)))); + when "011110" => -- 30 + if is_X(f_in.insn) then + v.decode := x_inst; + else + v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4 downto 1)))); + end if; may_read_rb := f_in.insn(4); - when 52 | 53 | 54 | 55 => + when "110100" | "110101" | "110110" | "110111" => -- 52, 53, 54, 55 -- stfd[u] and stfs[u] if HAS_FPU then fprs := '1'; end if; - when 58 => - v.decode := decode_op_58_array(to_integer(unsigned(f_in.insn(1 downto 0)))); + when "111010" => -- 58 + if is_X(f_in.insn) then + v.decode := x_inst; + else + v.decode := decode_op_58_array(to_integer(unsigned(f_in.insn(1 downto 0)))); + end if; - when 59 => + when "111011" => -- 59 if HAS_FPU then -- floating point operations, mostly single-precision - v.decode := decode_op_59_array(to_integer(unsigned(f_in.insn(5 downto 1)))); + if is_X(f_in.insn) then + v.decode := x_inst; + else + v.decode := decode_op_59_array(to_integer(unsigned(f_in.insn(5 downto 1)))); + end if; if f_in.insn(5) = '0' and not std_match(f_in.insn(10 downto 1), "11-1001110") then vi.override := '1'; end if; @@ -760,13 +802,19 @@ begin may_read_rb := '1'; end if; - when 62 => - v.decode := decode_op_62_array(to_integer(unsigned(f_in.insn(1 downto 0)))); + when "111110" => -- 62 + if is_X(f_in.insn) then + v.decode := x_inst; + else + v.decode := decode_op_62_array(to_integer(unsigned(f_in.insn(1 downto 0)))); + end if; - when 63 => + when "111111" => -- 63 if HAS_FPU then -- floating point operations, general and double-precision - if f_in.insn(5) = '0' then + if is_X(f_in.insn) then + v.decode := x_inst; + elsif f_in.insn(5) = '0' then v.decode := decode_op_63l_array(to_integer(unsigned(f_in.insn(4 downto 1) & f_in.insn(10 downto 6)))); else v.decode := decode_op_63h_array(to_integer(unsigned(f_in.insn(4 downto 1)))); From e440db13d759584347d54178685823e84bcdb071 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:31:20 +1000 Subject: [PATCH 04/15] Metavalue cleanup for execute1.vhdl Signed-off-by: Michael Neuling --- execute1.vhdl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/execute1.vhdl b/execute1.vhdl index 43e79b4..d77b16f 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -1170,12 +1170,12 @@ begin when OP_MFMSR => when OP_MFSPR => if e_in.spr_is_ram = '1' then - if e_in.valid = '1' then + if e_in.valid = '1' and not is_X(e_in.insn) then report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) & "=" & to_hstring(alu_result); end if; elsif e_in.spr_select.valid = '1' then - if e_in.valid = '1' then + if e_in.valid = '1' and not is_X(e_in.insn) then report "MFSPR to slow SPR " & integer'image(decode_spr_num(e_in.insn)); end if; slow_op := '1'; @@ -1192,7 +1192,7 @@ begin else -- mfspr from unimplemented SPRs should be a nop in -- supervisor mode and a program interrupt for user mode - if e_in.valid = '1' then + if e_in.valid = '1' and not is_X(e_in.insn) then report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) & " invalid"; end if; @@ -1229,7 +1229,7 @@ begin end if; end if; when OP_MTSPR => - if e_in.valid = '1' then + if e_in.valid = '1' and not is_X(e_in.insn) then report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) & "=" & to_hstring(c_in); end if; From 9e134f2e2fabfd881427029ccad1d345287bc4f8 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:31:32 +1000 Subject: [PATCH 05/15] Metavalue cleanup for fetch1.vhdl Signed-off-by: Michael Neuling --- fetch1.vhdl | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/fetch1.vhdl b/fetch1.vhdl index af1dd6b..c6d26d7 100644 --- a/fetch1.vhdl +++ b/fetch1.vhdl @@ -123,15 +123,22 @@ begin raddr := unsigned(r.nia(BTC_ADDR_BITS + 1 downto 2)) + to_unsigned(2, BTC_ADDR_BITS); if advance_nia = '1' then - btc_rd_data <= btc_memory(to_integer(raddr)); - btc_rd_valid <= btc_valids(to_integer(raddr)); + if is_X(raddr) then + btc_rd_data <= (others => 'X'); + btc_rd_valid <= 'X'; + else + btc_rd_data <= btc_memory(to_integer(raddr)); + btc_rd_valid <= btc_valids(to_integer(raddr)); + end if; end if; if btc_wr = '1' then + assert not is_X(btc_wr_addr) report "Writing to unknown address" severity FAILURE; btc_memory(to_integer(unsigned(btc_wr_addr))) <= btc_wr_data; end if; if inval_btc = '1' or rst = '1' then btc_valids <= (others => '0'); elsif btc_wr = '1' then + assert not is_X(btc_wr_addr) report "Writing to unknown address" severity FAILURE; btc_valids(to_integer(unsigned(btc_wr_addr))) <= '1'; end if; end if; From 43dadca05221f8a2572d205ed5a7efe461138ca4 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:31:43 +1000 Subject: [PATCH 06/15] Metavalue cleanup for fpu.vhdl Signed-off-by: Michael Neuling --- fpu.vhdl | 38 ++++++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/fpu.vhdl b/fpu.vhdl index 2dd221e..778422e 100644 --- a/fpu.vhdl +++ b/fpu.vhdl @@ -440,6 +440,10 @@ architecture behaviour of fpu is variable result: std_ulogic_vector(63 downto 0); begin result := (others => '0'); + if is_X(shift) then + result := (others => 'X'); + return result; + end if; for i in 0 to 63 loop if i >= shift then result(63 - i) := '1'; @@ -643,7 +647,11 @@ begin addrhi := "00"; end if; addr := addrhi & r.b.mantissa(UNIT_BIT - 1 downto UNIT_BIT - 8); - inverse_est <= '1' & inverse_table(to_integer(unsigned(addr))); + if is_X(addr) then + inverse_est <= (others => 'X'); + else + inverse_est <= '1' & inverse_table(to_integer(unsigned(addr))); + end if; end if; end process; @@ -841,10 +849,14 @@ begin new_exp := r.result_exp - r.shift; exp_tiny := '0'; exp_huge := '0'; - if new_exp < min_exp then + if is_X(new_exp) or is_X(min_exp) then + exp_tiny := 'X'; + elsif new_exp < min_exp then exp_tiny := '1'; end if; - if new_exp > max_exp then + if is_X(new_exp) or is_X(min_exp) then + exp_huge := 'X'; + elsif new_exp > max_exp then exp_huge := '1'; end if; @@ -855,7 +867,9 @@ begin pcmpb_eq := '1'; end if; pcmpb_lt := '0'; - if unsigned(r.p(59 downto 4)) < unsigned(r.b.mantissa(UNIT_BIT + 1 downto DP_RBIT)) then + if is_X(r.p(59 downto 4)) or is_X(r.b.mantissa(55 downto 0)) then + pcmpb_lt := 'X'; + elsif unsigned(r.p(59 downto 4)) < unsigned(r.b.mantissa(UNIT_BIT + 1 downto DP_RBIT)) then pcmpb_lt := '1'; end if; pcmpc_eq := '0'; @@ -863,7 +877,9 @@ begin pcmpc_eq := '1'; end if; pcmpc_lt := '0'; - if unsigned(r.p) < unsigned(r.c.mantissa) then + if is_X(r.p) or is_X(r.c.mantissa) then + pcmpc_lt := 'X'; + elsif unsigned(r.p) < unsigned(r.c.mantissa) then pcmpc_lt := '1'; end if; @@ -3014,7 +3030,9 @@ begin else mshift := r.shift; end if; - if mshift < to_signed(-64, EXP_BITS) then + if is_X(mshift) then + mask := (others => 'X'); + elsif mshift < to_signed(-64, EXP_BITS) then mask := (others => '1'); elsif mshift >= to_signed(0, EXP_BITS) then mask := (others => '0'); @@ -3060,7 +3078,9 @@ begin in_b0 := not in_b0; end if; in_b <= in_b0; - if r.shift >= to_signed(-64, EXP_BITS) and r.shift <= to_signed(63, EXP_BITS) then + if is_X(r.shift) then + shift_res := (others => 'X'); + elsif r.shift >= to_signed(-64, EXP_BITS) and r.shift <= to_signed(63, EXP_BITS) then shift_res := shifter_64(r.r(63 downto 1) & (shiftin0 or r.r(0)) & (shiftin or r.s(55)) & r.s(54 downto 0), std_ulogic_vector(r.shift(6 downto 0))); @@ -3224,7 +3244,9 @@ begin v.cr_mask := num_to_fxm(0); elsif r.is_cmp = '0' then v.cr_mask := num_to_fxm(1); - else + elsif is_X(insn_bf(r.insn)) then + v.cr_mask := (others => 'X'); + else v.cr_mask := num_to_fxm(to_integer(unsigned(insn_bf(r.insn)))); end if; v.writing_cr := r.is_cmp or r.rc; From 404abefd92be06ff7c30627925cf0901e355f8f2 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:31:53 +1000 Subject: [PATCH 07/15] Metavalue cleanup for icache.vhdl Signed-off-by: Michael Neuling --- icache.vhdl | 61 +++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/icache.vhdl b/icache.vhdl index 394bc5e..9eb08c1 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -207,7 +207,6 @@ architecture rtl of icache is signal req_is_miss : std_ulogic; signal req_raddr : real_addr_t; - signal tlb_req_index : tlb_index_t; signal real_addr : real_addr_t; signal ra_valid : std_ulogic; signal priv_fault : std_ulogic; @@ -317,14 +316,15 @@ architecture rtl of icache is end; -- Simple hash for direct-mapped TLB index - function hash_ea(addr: std_ulogic_vector(63 downto 0)) return tlb_index_t is + function hash_ea(addr: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0); begin hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ) xor addr(TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto TLB_LG_PGSZ + TLB_BITS) xor addr(TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto TLB_LG_PGSZ + 2 * TLB_BITS); - return to_integer(unsigned(hash)); + return hash; end; + begin assert LINE_SIZE mod ROW_SIZE = 0; @@ -435,7 +435,9 @@ begin process(all) begin -- PLRU interface - if get_index(r.hit_nia) = i then + if is_X(r.hit_nia) then + plru_acc_en <= 'X'; + elsif get_index(r.hit_nia) = i then plru_acc_en <= r.hit_valid; else plru_acc_en <= '0'; @@ -450,15 +452,25 @@ begin itlb_lookup : process(all) variable pte : tlb_pte_t; variable ttag : tlb_tag_t; + variable tlb_req_index : std_ulogic_vector(TLB_BITS - 1 downto 0); begin - tlb_req_index <= hash_ea(i_in.nia); - pte := itlb_ptes(tlb_req_index); - ttag := itlb_tags(tlb_req_index); + tlb_req_index := hash_ea(i_in.nia); + if is_X(tlb_req_index) then + pte := (others => 'X'); + ttag := (others => 'X'); + else + pte := itlb_ptes(to_integer(unsigned(tlb_req_index))); + ttag := itlb_tags(to_integer(unsigned(tlb_req_index))); + end if; if i_in.virt_mode = '1' then real_addr <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) & i_in.nia(TLB_LG_PGSZ - 1 downto 0); if ttag = i_in.nia(63 downto TLB_LG_PGSZ + TLB_BITS) then - ra_valid <= itlb_valids(tlb_req_index); + if is_X(tlb_req_index) then + ra_valid <= 'X'; + else + ra_valid <= itlb_valids(to_integer(unsigned(tlb_req_index))); + end if; else ra_valid <= '0'; end if; @@ -476,7 +488,7 @@ begin -- iTLB update itlb_update: process(clk) - variable wr_index : tlb_index_t; + variable wr_index : std_ulogic_vector(TLB_BITS - 1 downto 0); begin if rising_edge(clk) then wr_index := hash_ea(m_in.addr); @@ -486,12 +498,14 @@ begin itlb_valids(i) <= '0'; end loop; elsif m_in.tlbie = '1' then + assert not is_X(wr_index) report "icache index invalid on write" severity FAILURE; -- clear entry regardless of hit or miss - itlb_valids(wr_index) <= '0'; + itlb_valids(to_integer(unsigned(wr_index))) <= '0'; elsif m_in.tlbld = '1' then - itlb_tags(wr_index) <= m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS); - itlb_ptes(wr_index) <= m_in.pte; - itlb_valids(wr_index) <= '1'; + assert not is_X(wr_index) report "icache index invalid on write" severity FAILURE; + itlb_tags(to_integer(unsigned(wr_index))) <= m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS); + itlb_ptes(to_integer(unsigned(wr_index))) <= m_in.pte; + itlb_valids(to_integer(unsigned(wr_index))) <= '1'; end if; ev.itlb_miss_resolved <= m_in.tlbld and not rst; end if; @@ -503,9 +517,11 @@ begin variable hit_way : way_t; begin -- Extract line, row and tag from request - req_index <= get_index(i_in.nia); - req_row <= get_row(i_in.nia); - req_tag <= get_tag(real_addr, i_in.big_endian); + if not is_X(i_in.nia) then + req_index <= get_index(i_in.nia); + req_row <= get_row(i_in.nia); + end if; + req_tag <= get_tag(real_addr, i_in.big_endian); -- Calculate address of beginning of cache row, will be -- used for cache miss processing if needed @@ -517,7 +533,11 @@ begin hit_way := 0; is_hit := '0'; for i in way_t loop - if i_in.req = '1' and + if is_X(i_in.nia) then + -- FIXME: This is fragile + -- req_index or req_row could be a metavalue + is_hit := 'X'; + elsif i_in.req = '1' and (cache_valids(req_index)(i) = '1' or (r.state = WAIT_ACK and req_index = r.store_index and @@ -556,7 +576,7 @@ begin -- some of the cache geometry information. -- if r.hit_valid = '1' then - i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way)); + i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way)); else i_out.insn <= (others => '0'); end if; @@ -592,6 +612,8 @@ begin r.hit_valid <= req_is_hit; if req_is_hit = '1' then r.hit_way <= req_hit_way; + -- this is a bit fragile but better than propogating bad values + assert not is_X(i_in.nia) report "metavalue in NIA" severity FAILURE; report "cache hit nia:" & to_hstring(i_in.nia) & " IR:" & std_ulogic'image(i_in.virt_mode) & @@ -648,6 +670,9 @@ begin snoop_addr := addr_to_real(wb_to_addr(wb_snoop_in.adr)); snoop_index <= get_index(snoop_addr); snoop_cache_tags := cache_tags(get_index(snoop_addr)); + if snoop_valid = '1' and is_X(snoop_addr) then + report "metavalue in snoop_addr" severity FAILURE; + end if; snoop_tag := get_tag(snoop_addr, '0'); snoop_hits <= (others => '0'); for i in way_t loop From 738702f2e2b7c938a97671c11e7a0a9679302255 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:32:05 +1000 Subject: [PATCH 08/15] Metavalue cleanup for loadstore1.vhdl Signed-off-by: Michael Neuling --- loadstore1.vhdl | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/loadstore1.vhdl b/loadstore1.vhdl index 0a2f088..439f124 100644 --- a/loadstore1.vhdl +++ b/loadstore1.vhdl @@ -625,8 +625,12 @@ begin byte_offset := unsigned(r1.addr0(2 downto 0)); for i in 0 to 7 loop k := (to_unsigned(i, 3) - byte_offset) xor r1.req.brev_mask; - j := to_integer(k) * 8; - store_data(i * 8 + 7 downto i * 8) <= r1.req.store_data(j + 7 downto j); + if is_X(k) then + store_data(i * 8 + 7 downto i * 8) <= (others => 'X'); + else + j := to_integer(k) * 8; + store_data(i * 8 + 7 downto i * 8) <= r1.req.store_data(j + 7 downto j); + end if; end loop; dbg_spr_rd := dbg_spr_req and not (r1.req.valid and r1.req.read_spr); @@ -757,8 +761,12 @@ begin -- load data formatting -- shift and byte-reverse data bytes for i in 0 to 7 loop - j := to_integer(r2.byte_index(i)) * 8; - data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j); + if is_X(r2.byte_index(i)) then + data_permuted(i * 8 + 7 downto i * 8) := (others => 'X'); + else + j := to_integer(r2.byte_index(i)) * 8; + data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j); + end if; end loop; -- Work out the sign bit for sign extension. @@ -779,7 +787,9 @@ begin -- trim and sign-extend for i in 0 to 7 loop - if i < to_integer(unsigned(r2.req.length)) then + if is_X(r2.req.length) then + trim_ctl(i) := "XX"; + elsif i < to_integer(unsigned(r2.req.length)) then if r2.req.dword_index = '1' then trim_ctl(i) := '1' & not r2.use_second(i); else From 5a03de4c905b7449ac89e66b1aa5039e3cf4c1c2 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:32:16 +1000 Subject: [PATCH 09/15] Metavalue cleanup for mmu.vhdl Signed-off-by: Michael Neuling --- mmu.vhdl | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/mmu.vhdl b/mmu.vhdl index d95cd3c..1774822 100644 --- a/mmu.vhdl +++ b/mmu.vhdl @@ -163,11 +163,15 @@ begin begin -- mask_count has to be >= 5 m := x"001f"; - for i in 5 to 15 loop - if i < to_integer(r.mask_size) then - m(i) := '1'; - end if; - end loop; + if is_X(r.mask_size) then + m := (others => 'X'); + else + for i in 5 to 15 loop + if i < to_integer(r.mask_size) then + m(i) := '1'; + end if; + end loop; + end if; mask <= m; end process; @@ -178,7 +182,9 @@ begin begin m := (others => '0'); for i in 0 to 43 loop - if i < to_integer(r.shift) then + if is_X(r.shift) then + m(i) := 'X'; + elsif i < to_integer(r.shift) then m(i) := '1'; end if; end loop; From 43e62dbd9e3959dd6198c59f5c5c8ccebb12cf72 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:32:37 +1000 Subject: [PATCH 10/15] Metavalue cleanup for rotator.vhdl Signed-off-by: Michael Neuling --- rotator.vhdl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/rotator.vhdl b/rotator.vhdl index 45913c9..1049e20 100644 --- a/rotator.vhdl +++ b/rotator.vhdl @@ -34,6 +34,10 @@ architecture behaviour of rotator is variable ret: std_ulogic_vector(63 downto 0); begin ret := (others => '0'); + if is_X(mask_begin) then + ret := (others => 'X'); + return ret; + end if; for i in 0 to 63 loop if i >= to_integer(unsigned(mask_begin)) then ret(63 - i) := '1'; From 7a3e5cac3b628c93b02c7b2914b2b0cb960bf234 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:32:37 +1000 Subject: [PATCH 11/15] Metavalue cleanup for pmu.vhdl Signed-off-by: Michael Neuling --- pmu.vhdl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/pmu.vhdl b/pmu.vhdl index 2967f4e..928d6c2 100644 --- a/pmu.vhdl +++ b/pmu.vhdl @@ -217,7 +217,11 @@ begin -- Check for timebase events tbdiff := p_in.tbbits and not prev_tb; - tbbit := tbdiff(3 - to_integer(unsigned(mmcr0(MMCR0_TBSEL + 1 downto MMCR0_TBSEL)))); + if is_X(mmcr0) then + tbbit := 'X'; + else + tbbit := tbdiff(3 - to_integer(unsigned(mmcr0(MMCR0_TBSEL + 1 downto MMCR0_TBSEL)))); + end if; if tbbit = '1' and mmcr0(MMCR0_TBEE) = '1' then event := '1'; end if; From 438a76dafd95c8efbb54c93c74dc1feb1e2e42a9 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 14 Jul 2022 10:32:37 +1000 Subject: [PATCH 12/15] Metavalue cleanup for register_file.vhdl Signed-off-by: Michael Neuling --- register_file.vhdl | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/register_file.vhdl b/register_file.vhdl index 753ce80..e56202a 100644 --- a/register_file.vhdl +++ b/register_file.vhdl @@ -120,9 +120,21 @@ begin b_addr(5) := '0'; c_addr(5) := '0'; end if; - data_1 <= registers(to_integer(unsigned(a_addr))); - data_2 <= registers(to_integer(unsigned(b_addr))); - data_3 <= registers(to_integer(unsigned(c_addr))); + if is_X(a_addr) then + data_1 <= (others => 'X'); + else + data_1 <= registers(to_integer(unsigned(a_addr))); + end if; + if is_X(b_addr) then + data_2 <= (others => 'X'); + else + data_2 <= registers(to_integer(unsigned(b_addr))); + end if; + if is_X(c_addr) then + data_3 <= (others => 'X'); + else + data_3 <= registers(to_integer(unsigned(c_addr))); + end if; prev_write_data <= w_in.write_data; end if; From f34b2488e4d61079b902c3961e831e55a6181e9b Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 28 Jul 2022 14:47:51 +1000 Subject: [PATCH 13/15] tests: Minor script cleanups Signed-off-by: Michael Neuling --- scripts/run_test.sh | 3 --- scripts/run_test_console.sh | 5 +---- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/scripts/run_test.sh b/scripts/run_test.sh index 185c3a6..1a032ba 100755 --- a/scripts/run_test.sh +++ b/scripts/run_test.sh @@ -25,9 +25,6 @@ ${MICROWATT_DIR}/core_tb | sed 's/.*: //' | egrep '^(GPR[0-9]|LR |CTR |XER |CR [ grep -v "^$" ${MICROWATT_DIR}/tests/${TEST}.out | sort | grep -v GPR31 > exp.out -cp test.out /tmp -cp exp.out /tmp - diff -q test.out exp.out && echo "$TEST PASS" && exit 0 echo "$TEST FAIL ********" diff --git a/scripts/run_test_console.sh b/scripts/run_test_console.sh index 1aaa2bb..01a89ec 100755 --- a/scripts/run_test_console.sh +++ b/scripts/run_test_console.sh @@ -3,7 +3,7 @@ # Runs a test and checks the console output against known good output if [ $# -ne 1 ]; then - echo "Usage: run_test.sh " + echo "Usage: run_test_console.sh " exit 1 fi @@ -29,9 +29,6 @@ grep -v "Failed to bind debug socket" test1.out > test.out cp ${MICROWATT_DIR}/tests/${TEST}.console_out exp.out -cp test.out /tmp -cp exp.out /tmp - diff -q test.out exp.out && echo "$TEST PASS" && exit 0 echo "$TEST FAIL ********" From 72fcca8e525fc93f802b8c81900f2d1fe964027c Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 28 Jul 2022 15:28:25 +1000 Subject: [PATCH 14/15] tests: Update FPU test output The following commit added two tests but didn't update the tests outputs: commit 73cc5167ec1ea591d9da43f2e392b5202f045f32 Author: Paul Mackerras Date: Mon May 9 19:18:42 2022 +1000 Use FPU for division instructions if we have an FPU This patch updates these using tests/update_console_tests Signed-off-by: Michael Neuling --- tests/test_fpu.bin | Bin 30416 -> 31088 bytes tests/test_fpu.console_out | 2 ++ 2 files changed, 2 insertions(+) diff --git a/tests/test_fpu.bin b/tests/test_fpu.bin index dee8fbd85688699b9adc077133670fe8eea299ae..3c1021b859e238987c22eaeb5a34fc5318137666 100755 GIT binary patch literal 31088 zcmeHv3v^WVx$iegAd|==AZieV9m0Wx#;$NK)d?YF4*?7TH6n_7&`wM!;Nvd5>bZkV zm<=7z2^Kk_*LuN%1{dW3wO%~6chOd4qV_bj^&Du?hWbi;H4msmt9BqE`~JTFV`k6f z1)R3twdB9n&bPnk|NFlGbN~0A5Sb-J6;=P9Ua!Wi63~dN!e+O{izn@|tTmRqamQSeuh(-9RbOCMw^Z;tphyE9$ayqPxqc z2Ub(#X+O1|w#ap+j&jb_llRP4syfp^>(A_=ooDt_WZx#cq;LM*O#%24U|)96nI1@%(=ouGcKFi{e>&h# z2mI-PKOOL=1O9ZtpAPub0e?E-Pbd88gg>3|rxX5k!kSf&M7=!T5LHNEw_*OsszxH&XZ=p<_P0*h_Cl7^vUPjs zK>jdffAQ842hRt2<~@HyLy&0STQBy(`@;LaevQ7kqxHFBp(KR40p$ z^TR3C?6%KMxkU|o<`i*!5!(e{_Wpus&#%9leNP}_=dAZvR0n2Ibzt4`>Lo6!UYY!i zt?dmX1G^7*bIV*c#cOLC&K4RyzlP4eNARD~!#q(l% zwKyASwj100lcv^^XG);W-e9%>H)-k`#+!lLc8h03wB6rkx3*FF)WB42|8h8%(Y&Q#MIZMP@j?c3_DSwfOQPN_2iz1PHoY&;9x#N!f<+!R~?{u!qC|NO2 z(!akkfB7e`=U2h@Y4A9&O>R2ewCUQ9x;I@jWnQ4g-ryaA`kLcy=(1cy&X^)L&cRe%wjC~Z#@5;+H2fm;k-$vhJJE_XfbcdZ`u#*Zq2c(}q)=z`n z-G~F@S?F(9`b=j(PIbopVErM`_bYwh-Z|^p2I~%mJlDTW=??+^qa@vQ=+08Qp}luo ztc&@l*Vy-DS1%dk%q7kyow@wcR4Q*opRny`OKp2YDN#%D{u>S!x0&0EzjGG-q;pr$ z-}OQ8YpQ;KR}cD4Y5}+Dc#+H00yo;-MYD@c)wT_=>Hi=k^v-s~W7hq^1^r`)%|-8( zHo-R+*~P=CH17$}UUK@Hmgp<@-&Xi~w%c9^UvaMJ^BlW7B)B z@gKET=rN(k!V3;t_gx?IT(4}2@sJKb5!>#RnYBb2>%}TH9IRu(RaGkmsW|nV0jm<8s*XSB5-0F3`@8&&1=} zbyvu9%LUqbz+q>TFXS11fp+p8c4piX^8D=g7nYya)A6|S=7c=87iedj!_L-QL!Pf) zpq-l>cC4i#&&iK3EUpZPoz=I6Jm0%OJB`tJehO|6dG5SGJ8K+v+F<9h3$!!cVQ1GJ zApcwupka@ZNO4D;Uw z+By7rJU_pJo#hu`hxbnFVaLK8ih1j_L9I=jOQ^?6OT>APMj3K%hId{odCqmp^Zd*E zt8-ba^g5MsPWAc%lu_;5sA4m#%Pu?f6Z@hOv9=dcc4r2WtEI&?pQ{`gQ z#QxVJx!3z3wtsa|a1-xAu!k}^mzB`vz4XCxa!=Xf+(RU-YqpKKb%NaU_{Y@-{9k!F zFf;3!B}5YoCX;2dKmI?x8sxTVv+<78#yd{CwUhT055ev=-Ft(x)AMi1pp1g?wBB4w z`9-{+?Y8aW5>-Dx_Z5QP=JX>qaSu`gA6`K2u=e^soU+c}u;=~aF=t*5qMzWoW5+8* z8-M4fJKKSaz2q$HwZ0nRN5c)JZn8YqecOxuA3Peo8g&>{)yDT(pkD>tO|>z6IPful zv|-oVUWwS;RNC%*2Kn?VN8ZyCedN6JUVALH;GJ%JfPHP)#m~wu#r}nPwcP$318f)N zkv;zTSt|qECxpAVPvqyrU*K7(qj~!T<75_1JHCCQc`}=Hf65xdn{A%DH2YwZB^bZfm%6*~`@nxaT zJXL2s_L$kg3l(kwH-LK-zFO={?czMNUx9j_RL}8ppOmzJ);YSIs0i<3u}>sl{j)Mh z@$unB&Q{@Ba%0oxtEea22#fr%Uk16_$($M}?;{sOc>j&K)6lNG2loPZ=4Lu@j+Of? z$2xaBmGfRY8@|^o-#>Kr!6e_$1dS5y|Gs_sRhLj0?R+@E&&a@+b2~F#w{srmyi3R^ z$wPbp^r!h%h2$z?S&U~7@a0THe?84PppBe^!%g@u<1o?BfARb+LlLtZePXZ7ec|5) zxKDH2r-=UiZZXHm@!pO-xwDNI0C%?OGK@2hGYfHUKZiI+kcqZgAlhdCKTj(9*_Cqq zbA0Thn-(0V%73z_P#Aq~LA#Ou?plgWQ~o`x{5vT9>-=8u$Jm4N9O1{k3%>6K?reu$ zu&>*pp)dcE=7MyGe=XLeqEXP_Ddq+|+rl3=Wwigg?6Kgt%kBv-E~^NRE}Iq{JwG!z zdQOM%ms+L;>P0RczAFEQv#;=z=LY`=-wd9`J~M{DRUJI(#D7y3e8-9ZGB^0T6Mr=| zcn~{oN9$Q}CQdODIRayN$Wn=(c2kl*zb&J?*D&-c;H zSniB-%$*+lSHcheUWmtS-IH?eLKnsOZNWYz>`9>p-m648uRPbAr5> z?Z=uyi)wo1xQ1>w?E|ebMym%cOVD=4Xh%TH1`Tr~=EABrGI9f}WnZ4f^8)9I``SFQ zPkyD8Ww_7rTETP0)u21qhpT`)=Z@jPo$JF{>?e7w>b{zF1+Nbqu|CMU>(KwQfwK+v z#Sh#7&Ndid37p3^uMg24{&vjg8EAdbXH|qfV0=A@?;Q(7p7{(mqt?Ae=ALt`&mN~0 ze$<^;7(aW=!d!s)wvE?}%6{h0v53*RPGkV*__*(J?l`BPVL$1dv)q^Sn9XRp$N6{sQr)JKDA7vBY>e)_-$-gfY|6?A!zNw;nF|EHS3dzG@8L8$9ER^F;QJBm&Z;-cP)SXQ{lVCW0mK-THsFK>o1kQ4?{oebFDm2 z--kHzo|WjkILn`m@pP_vKl-P{yf*@O`hINmUpDVU9lq}u`=^#-ITsvmDlFtZHNSso zkL?-z>n~%I{LV=7d%W_S_fNa}+Mk?f&T;;U`AW`V`~S(=*AF+%I1j(8{+O8Wn}9p> zT{BAN`>*2nqltbOoQL0gPbK=j4YX9_?j`ok?)2LiGHJhG-1v>e8$WB z?abz=cS?7UcYb%b_ZygFr(wRSXwIg4aK+aVx!(5PhaZh3#?=Vixz@e_+_~271kUTE zbDen{G|q*79%~p$<%VOO;q^8Tc%fQ%c)cwI?oqg2Z$0R%hU%;5vflc~t;4hO-Lo>W z$FIk;C9l1Fe)Ga7_QE&u4xeuwKkH<=FI2gJS}&qow4ww`{!7;mJD@hmzM&sN2= z$W@HEXJX8EVT~7OOGLq@WfORR^LZy=jUseX#TQ^4dDH_c}mrMy{c)wh)o;Ah~=lz?F{hNG_=I4rRvMuCNtV?r&j|c8i_zd6%P25OkMj#LO zIpThNU_9<8iTkSpS-8&?_u~R-xaa2)oNp9gNwW)TdN!E6=d+ME%z0c~Rwn*9-Y+c} zme|f)pE|d8zDu?955#kRVmsfZ+IdTi7jNeYs+}K>@#5_~LACSk;Qd$Ixlz3T9Jrl# zKxVLZmhWQ+Zs%KI$Jx#^Fb4lt?L2mXcE%WwMr=7YlgB#0-`wD?_TM%n{}zf?`#*8z z--35;UNWj{=FDE@f2HjnKfl+XNcj&KwBdR(t80>NIQtR5gFKl*rE zWoCEe&AaWchM7Uznpty2``WLT�Q+8UhcoF+PpIcHzDrzyYI)BGyV4D;9c7gh)I z(bsuCy$ojwW+Yea_4pa+8pB@NAjaVb!4UkE`qaZ`3OH};B*@}@KE{t-yldp)wR2%- zbIFpk@W0&?t`2z0R|Wm!a%&Ic%#Q8<2zqQk3pr!kqoCISoqtIScTd5Y`lRdf*StUF z9zV}dT4pq4FwrmEoVFfw@b=>dpOebY9^K*j?Z>3x1j~d=dB=_K)bD!i(yxwjMU6l~q6_9U$d`)__-$f7lz5{!-HSRa& zxnc|a&1oLkm?dm@_8-QX6uv`o05##+i9Ao4iqf*NI?` z_y*03^)IymV_&?t;Qh%Sxi@KpzIexwh4-xD+XIYi|2RJHzkAkxJ{#XVY0GDL$H;5y z5UiC4c>Tq>$kmYFo$?6e+$U&@9{ihuQ#oI4EEa3rBPtt4Mr{I zk_S%Un=C1JcblM3@L_*gy@dD9a{Zdt&d+4b>xk=^TE~q&wctUoNzAk0sG`RZ&|dx& z_TdlKB!@qf+J!$i`ug<4EoDvYW$}Jb#3|%EmiGRxPWz$1590GI+jhQleD7a~CKOpY*$?;$dI4!EAbTa5IV zkFZgKSgUvq)_J8ce(yRoe~lZzK{cpC(r-1fj#NA#c!s2#@P}l)Skq0kE$4R5w(*uCb2`gsD|y>iZKv}RrV^9fRR+0b9rLO7gLL;AZ8L6XL2ZNT8$4&BKW!uE4l~?U zmd)?HrT)I_jM{p9*CyM_6!$5wRIEwU{p?0bONFm|4&;>6{c4|*;q!j9YfPrU{gaHD z`*#M8Sh?*d;cS!pac;pZcW8+}_pt!)&0O@D&*_J>H<`a_^QK_kK>kHt9kD(JYpNIu z4#)nV%R|c_e8>R2mH(g^h5%IQz4>OAneSb&h)KrHix(G`NI0G0{K}il7MD=Hjo$;? z_&um;&w()yl8@~s(@q1t!zXw*|LGrxJenYl+i=h@XlNK{ zlNF6&J+ASf9b?+u3@<(7nmeL!ly{vka|F$KZ>aYYqCBt;;A(>0A{TDvLGJ04XI%4y zcb zZ~*?N;NLa?e+=d{YXJTX@b?VBUjqJ-0r(GrA02@I1o+19`j78L@XH6_9|M2&0Q^tE z-#P$)Oe#)r2H?*Czij~i67aL$>fir|!1oNme*%0T_XVQJ|1kXhuE;o9e7fOzHD<2hgk z(fVUdMBWGsat__&air@j#>;@@{;bgiW)O-|F6${?yR#4oR46eD^EOx8M5R@n)#A zZisbT&tF%>&${p1b`967wOz?V}3ul zTpC`A?K%g!0?5t43AkwEa?u|-e-9+ry99FO?Y13Y|Mc1<*9nX^j0|*i9;X4wZHJt} zawsOQdeHWO*2e8A#>$hK|2w14zEtl@iLG4Rn|}Ky`V-qY1{;eyFWd(EmhDDcoQTgM zOvA>BqM*&iJr|xQOwjU9Vr|9zBIXtEw@3W1;ZF?v&L#c&-QZdwGxm-c1iyXrjbp$0 zHIF17clEFr!p8YS+{flAo`V)ZXC9^%?b(m zFiBb_&(9owr&3z zC*``l{Vm%bUMBh5mf#JJW&rNp_Oi`<)&+{s2yBMVVktyJC-1!OIespj11>rT8cJ&X zFXx1dhMWT~$vKkL_+QQ$7cH+L=ZK3lhms=y=G}a18Rt_&Ew3TxhzsYK3+I{3>Mh?L zb;r7Rz9kpW?Z_*ayPlF1t=3=4UD74LtEOV{xBZKg<{Q? zJu_0Op`>eE>xIP;0eE4_55FYGSp>f~;S#S`;$%vAY?i{q3V-QW#ldep-7vK9bqP(O zPR4%Yb$8Lj%m4K`i5C_soF8LR3im7dUV8bH?mG0z4}YWO3Kg#H?C+z#${FO_52Fn$ z=`M!As|pp)ka4E>RV+nRFk(www?{;^Pb4VY?UXIyX(boWld@yVxIX80Ldh}(h_zSb zki@lpx4Cc8ZEcVI-!3J8Bq;eUUzgBL%HBkY>xCqu@D#=Wc%o_-g@0p0;tb`RAocZM z9hW!)08z)Sq4qB(r}}L_@kc)?RhCVLO*=kTxQajep2B;_&+^%R{ErY(RQyqUqQr4{ zf&zPAm$-^Q`ia72)J;1+|GJJ}%Ku|kLj2KSmDG>_b;^TkX-*zyM=K;Z|ul(c?aC|l(=yEXUBP&-S#Qw!{1|i$S0HT2I>ne<#-qevOI0=IEsY zhEFc32?J+7>uEmIO<*h+26XB(uJyDXr#|zwp0Fd^*;)ZQ%IX>k^|*@SdqXao?;C_) zISAkE#jg`38r&wz=^$5DS10CS0Ttg);@e8j*81$Fnh*NYXS=%e$sZ+(h_+9@R2Ka- zfv@NZ{%_kR<4_PHI-kifzTPN192ZJ2y3>E~lkI4nEY|LeKS`7nOR)RUSNw3_d?IK5 zd&eiW`lwgM)30BeuMJ!%w3K2p)b^6;8Yi6>NBe6XhL%hlk>opBv3mngr`G{%u~Sbl zL=o-LV5h(Rb096Y{g&ka`4cA}&D_fTux$%EL&hB?)~*g(pSPBxCc|Fyubz)JlzM-; z`S;^DUi%@>zm~Y^J^uhZ1d zBp9226Nqr1dNKbJ@m}++ znvZ(XmA;NbkIQ7(?>raO^Gss>as6|he|20MYLEJ{tK#X`FU?OhbN-m6RFa{#luXxn zulZN?1M9zulG@I9|&8M619lLzPz2=k63jyylcQ=0v@SboQ zdyrCS@^Em`s6%O%eW=S-Xr@_YrYU-Sf111>trwrRu!(almXhliiecGnKdi0mc{mx@ z^nT$XsiF7By`kLy=9p4$l7dDr+_6u_iJ02|YG}rBDYr%HPgcI2Go)OViI43?aYB913@Nw8EEf|lzJGH-eIJ)=^#12#^CvOx zg!(=%chvjzWslEg+zIu4T&~qS>nm3ZcQiz}L3uB;BmFz&_1`*UG*dKWIb6t%O9(2t z#=5<~Jjr_~u0s_|K$lZ4r%dc;x420|s048(*_*D$$0(I2{Q9v^Id9ohOD`2^(6Dd0 z#xl|Z3id5`w2Wr_pD7|=3id76S_V3opxl>VxsmUgfbQbVOH7V=sstG#El#;t6LKaI zkv}abNfDt7bq#T=>Q(lXoNfnUL()jxYkRWY#B(>Z1&?n~EdG-uH>f?{?2`zFG!OHolxJ$?R|0Me2p6C8Y1~YZh_=+{?8Z3xyZ|x zb)3t7fAo;-&FBADK2OK=EOn=$8dqZ9?VFdIV~R-V@RCH58!IFNS3Ic(h)9U<~=-rp_#mWrv zUdqQ%$0hA0@Am{1_FMV94E6<-qN3hYv2!#XFPM-Q^cFr()A2g!xQ#gLO_0~d0r$_# zb@9(K!U}2@=#AGhGFL&(7zjH2gIK@MZ>2mpagnxS&u?YPxFarRnUdcd%JUy>kHS(e zqU^D!JZJ=5KI0nHNLth0QXl z*V|sIsL>!PZHh;Ms0`!) delta 8185 zcmbVR4R91ywmv=io52_o2qYmtOnyjaAZQen4oP6b?~njS3MC-u#Gq^RxfT2=C+>uv zP{S*+C={>m3%;xbDiCyCg$k~5%b&2iZ{sey!SyGu7y?AiD6B#8ZCH?g-|6njbYjA8 zy{_uaJ?DJ)oO92)_uShz1K&wqXQf;sR|!#B)&Inl)#3LpdZet1$OGPe;N1t_eRugE z*_nI2#sBKgb=O;-o_%P?@5U>y)_Jjtd>a6a+MD{|mM&vJ|EiUiHK1IS<7aKB*A#*_10N+>+SLA7i zoG3d#nYNThP_^f9OpULAGG%XhcKwUFHseEd0Q6xI8WA|x(kQFsTQAo)b-{|8v>xhCwwVI9%4csT%aKM9p zQD`4B`Vi%1=d;lmbZ}`MO3;Bkk*y0F$UV+ifLK}4!6Ei!q$n2R(t0oKJ$q> zidt5_QPl5hD%$lU()Ue^;{E<@rNmHwIOYV>nVp}e#VCR;xg=8L!!gx97h=@}ecsan zt&eTUB|YU5MdTlcyTBJCzVcC3jVqU^rzn=@Ie7dX;-g8~6QW>NPZd(+3CR1t7H=k9 zBjm}k39nrWi##g=@>+4rwZc4(d@ zW|Ld=PD~cHbF33~T@34!O9OIYQ2ab)PP~chz9}G|6K^EVnP4+<@2LpL&-aVV!2UC= zVeqzqT%}>_Ox&&w0Xd~#?3gkq!NfhdDj*;G3In@wLhwRZg=0ZL-u9KqNS%{l;>NEI z$fY`Xt%-de>AprK>qX# zP06``gq7sn9FTYF?B`8vD+aSnXIGinuS1EXvr|m$+O^10AL~vy_P-|G>jLs7QIa-C z+9uAXO%u9!(v1EN|_VL0`dp9*Snfr>o zsr5eZj5mFAf&sbzzVZaZHT^Tu(f!>3u&x@lkcQY#GsiMU1-V%S!$X>O# z*h+r6wq~DPKzjzASVs8mw^LPrJoqUFZKZmRwt-IkPE}a$foE2%Pwy0Gy{gs}#4oG% zou7g^cQ7j%CF$hF6zY}tM+ALrw)U62G4vLB%N_OcBn|EnTc<9(-CI*Fr=wo6I#u0U z%qH0t7hG8ZK7RWhhASloU0~2NLCa_}hWoLe(E4Q8W=|2h_63pc@K|)ErzuI~D%>Bj zte(ATZ_>SCPq=>CNh*vbS^$xJ4{@MtI<2&=b4NN|PPTVkBI@jpry#;o8cZfcBqLEOS0~icQlVywi(Wz)^eym1N}X zsDLl~z{l^-~{_zcPseuq}ZR?s{(L(`TW-UMFA2xs@PNn&MQR%Ev^1&54ycZ=WU6^~-%c@!qI zkzJri8rce-*+^5OnCBQ_q{$I$sr+y8f+N4|rz3d}70Q^DT4>$?ZC3c<#8J{{9s+Bp zCULiOH0_gg?S38xSC*&|+S3f}vF1r)(jFJ3%?a}CkFeEu?hski^Jo2Z3>#2R&0|;r z+B}AhqG9^PNF+yF`&!_;rXwazqG!5e6n)SCFkIg*&}MxH#kmx{3>qcmIUqQQ#j|+MQ4(6v?Tu+GT znQmoxgt@@n|Gi#*Im*0%HW+lM9Ir6w(1I%g%?r-F9-QEXM$JXZHJ;pdvIQMW@Azhmn$Y@n_|(bmC(-6K z+;WZ&%yTt4r(!hBb->JHeN<%VQHCqxb$PX>s8|CaZ~l>r7!w@e{B73a+l*Mg6HAy{ zcOZY6+DX0=`Aeod8j2}XJ8-)}r-7CYS_W;W`P&dkn=cTztbZ3P@{RWD)m(5kibJ!eDj(qt!BYNE zztMhrO#(_!Cwe{+*>NeC?Dbhoopq;j@AXoJa|km5m=<7mL^k|L)by#Hmk!o>NXJCT zd3MX~+4WU8!Lk?k!%k>;Y$p*IkE*6)39##zf8_D=A#8AFucE*g;YbF7k z27SClUyRAFV|`I0{GJTVpm=4rGw<}8B(yuBVq;9TSE2_!uiywnjo~pSLw-O+-H;h` zdQA%2elha~r!uSFl2?OzRyF8-%31F%e{l17s(BzZrYXS9hR)bcbjdDNd#Sd1qYVp! zeVGLP<`|{|YXx>YHD8twRQpci9Lu<~IOUjeX~6YD$8zAv9a-(+4`c@ZVFWN8z;*z) z6RC1@wQr|^`_%|s25?V`^c$0uO@;(_H7?7N2OqWMReQZts(DDYp&?BLx&m5xc16+r zeCv-}TwIu1pq;A{9?2g!yfE>hmv=EfQ1gAqGup|h0Ur>hgE$D+XGZ#0qOJ7Tr7AvL zPPtr|#{5OmsBeG$Q1H$E2&=Cv$cFKe4~r~shMZcncD@Ea?+sBX)d!68@>%fqTOP$_ zmi{$$5d2Ry-Y?SkUJ|-)zuV zgDzf%+XjP<104W;ok5QWeH3)2LC2GV5tjwz1cQ+PzC z8gwG)+2x3UK~Dnh1AWAxCxd9(@bSlqm-3x3u2bFZ@aNNjw*lTeG(D zZ@hN7YRfMWHy5VQySM+vNbUTLqF$hqkZc3Pr)aYV0{ zH9qisF)KXjiK8md7bgqTCETpeogtNpS##&-&CAE?(C#PTgWPGsl^bO^_`t%kT?}Q~ zb(+{Ucd_CsvEz~%Z=GiBR#!cB*h?t7tj>xXPdhnvKAb~)6W^M$+%-ZLIq0mT4k~$j zJbvv~^t0BH768kIG@=sbJ+-i`KA;_<$is^ULE1$MI>kchSM7z|NsG`@dwqOsR#0o- zgMkcTLf7G{TBbRWz@tgFn?@?6;;D=D z1m@%uZM#+qoxTlMp+zTe^BzVJ~9bw!YXQDce6%Rh;*IP6VHcsGI%)#kAI)U>j3XK4$4G} zY^AhYS`=51P`Y{TxHwvHBDxeOHFl&O?{NTev?E#wT=6t}DpBkPlu#-Uzw<^RWhqEVcvS9ut5FKwf(V`5@$tSCA(oQypW; zVV`6G`o{u5UI}@8&sZbCWQJV6g1ixO59D6xLW+5|u8O0DT8ig!j@tof9|ORvsGA)) zp{k7K$By?5c*!Tkt)&^Z_()7eh~1*TbgCkQ3V_04jqam8bxAOgeHKtIvb+{7hR=yqpvb_&R_UCsp-zR;mLR##I1# z`w&pW^#RuhTp#1gObYJ|;aP;Y7rfWOYhXHQ-@?cxQ?~ud06h^23%~czx%^<4dN`JO~l9 z_+hvo?>pe-vtm5Vdm8WYA5`_Bwv$Wd+u8<}ydBYYZB)F?*53j&WAc8gy)gyw%^`5 zP7(v_TE%~@TO;0FTPZ$~CWwwTNo{XE5R`;M jtHz7>Z?%e^TRuqs_RZh)Jo~d8{`WYkc;5Rpw}}1^Q7%Z2 diff --git a/tests/test_fpu.console_out b/tests/test_fpu.console_out index ed759a5..3ec9480 100644 --- a/tests/test_fpu.console_out +++ b/tests/test_fpu.console_out @@ -21,3 +21,5 @@ test 20:PASS test 21:PASS test 22:PASS test 23:PASS +test 24:PASS +test 25:PASS From eeac86c9d8efa987e65a68dbc31541e7119a401b Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 28 Jul 2022 15:29:25 +1000 Subject: [PATCH 15/15] test: Add test for metavalues Make sure they don't increase in future Signed-off-by: Michael Neuling --- scripts/run_test_console.sh | 12 ++++++++++-- tests/test_decrementer.metavalue | 1 + tests/test_fpu.metavalue | 1 + tests/test_illegal.metavalue | 1 + tests/test_misc.metavalue | 1 + tests/test_mmu.metavalue | 1 + tests/test_modes.metavalue | 1 + tests/test_pmu.metavalue | 1 + tests/test_privileged.metavalue | 1 + tests/test_reservation.metavalue | 1 + tests/test_sc.metavalue | 1 + tests/test_spr_read.metavalue | 1 + tests/test_trace.metavalue | 1 + tests/test_xics.metavalue | 1 + tests/update_console_tests | 5 +++-- 15 files changed, 26 insertions(+), 4 deletions(-) create mode 100644 tests/test_decrementer.metavalue create mode 100644 tests/test_fpu.metavalue create mode 100644 tests/test_illegal.metavalue create mode 100644 tests/test_misc.metavalue create mode 100644 tests/test_mmu.metavalue create mode 100644 tests/test_modes.metavalue create mode 100644 tests/test_pmu.metavalue create mode 100644 tests/test_privileged.metavalue create mode 100644 tests/test_reservation.metavalue create mode 100644 tests/test_sc.metavalue create mode 100644 tests/test_spr_read.metavalue create mode 100644 tests/test_trace.metavalue create mode 100644 tests/test_xics.metavalue diff --git a/scripts/run_test_console.sh b/scripts/run_test_console.sh index 01a89ec..95c2495 100755 --- a/scripts/run_test_console.sh +++ b/scripts/run_test_console.sh @@ -23,7 +23,15 @@ cd $TMPDIR cp ${MICROWATT_DIR}/tests/${TEST}.bin main_ram.bin -${MICROWATT_DIR}/core_tb > /dev/null 2> test1.out || true +${MICROWATT_DIR}/core_tb > console.out 2> test1.out || true + +# check metavalues aren't increasing +COUNT=$(grep -c 'metavalue' console.out) +EXP=$(cat ${MICROWATT_DIR}/tests/${TEST}.metavalue) +if [[ $COUNT -gt $EXP ]] ; then + echo "$TEST FAIL ******** metavalues increased from $EXP to $COUNT" + exit 1 +fi grep -v "Failed to bind debug socket" test1.out > test.out @@ -31,5 +39,5 @@ cp ${MICROWATT_DIR}/tests/${TEST}.console_out exp.out diff -q test.out exp.out && echo "$TEST PASS" && exit 0 -echo "$TEST FAIL ********" +echo "$TEST FAIL ******** Console output changed" exit 1 diff --git a/tests/test_decrementer.metavalue b/tests/test_decrementer.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_decrementer.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_fpu.metavalue b/tests/test_fpu.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_fpu.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_illegal.metavalue b/tests/test_illegal.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_illegal.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_misc.metavalue b/tests/test_misc.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_misc.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_mmu.metavalue b/tests/test_mmu.metavalue new file mode 100644 index 0000000..a29644e --- /dev/null +++ b/tests/test_mmu.metavalue @@ -0,0 +1 @@ +144 diff --git a/tests/test_modes.metavalue b/tests/test_modes.metavalue new file mode 100644 index 0000000..492dff0 --- /dev/null +++ b/tests/test_modes.metavalue @@ -0,0 +1 @@ +152 diff --git a/tests/test_pmu.metavalue b/tests/test_pmu.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_pmu.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_privileged.metavalue b/tests/test_privileged.metavalue new file mode 100644 index 0000000..492dff0 --- /dev/null +++ b/tests/test_privileged.metavalue @@ -0,0 +1 @@ +152 diff --git a/tests/test_reservation.metavalue b/tests/test_reservation.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_reservation.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_sc.metavalue b/tests/test_sc.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_sc.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_spr_read.metavalue b/tests/test_spr_read.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_spr_read.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_trace.metavalue b/tests/test_trace.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_trace.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/test_xics.metavalue b/tests/test_xics.metavalue new file mode 100644 index 0000000..415196e --- /dev/null +++ b/tests/test_xics.metavalue @@ -0,0 +1 @@ +118 diff --git a/tests/update_console_tests b/tests/update_console_tests index b168e8d..d0613c8 100755 --- a/tests/update_console_tests +++ b/tests/update_console_tests @@ -9,6 +9,7 @@ for i in sc illegal decrementer xics privileged mmu misc modes pmu reservation t cd - cp $i/$i.bin test_$i.bin ln -s test_$i.bin main_ram.bin - ../core_tb > /dev/null 2> test_$i.console_out - rm main_ram.bin + ../core_tb > test_$i.log_out 2> test_$i.console_out + grep -c metavalue test_$i.log_out > test_$i.metavalue + rm main_ram.bin test_$i.log_out done