From df1165bdfc09354385977920d93693836ef76cf6 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 19 Sep 2019 20:35:42 +1000 Subject: [PATCH] Reformat wishbone code Signed-off-by: Anton Blanchard --- wishbone_arbiter.vhdl | 84 +++++++++++++++++++++---------------------- wishbone_types.vhdl | 36 +++++++++---------- 2 files changed, 60 insertions(+), 60 deletions(-) diff --git a/wishbone_arbiter.vhdl b/wishbone_arbiter.vhdl index c7d249a..7d5cbcd 100644 --- a/wishbone_arbiter.vhdl +++ b/wishbone_arbiter.vhdl @@ -5,53 +5,53 @@ library work; use work.wishbone_types.all; entity wishbone_arbiter is - port ( - clk : in std_ulogic; - rst : in std_ulogic; + port ( + clk : in std_ulogic; + rst : in std_ulogic; - wb1_in : in wishbone_master_out; - wb1_out : out wishbone_slave_out; + wb1_in : in wishbone_master_out; + wb1_out : out wishbone_slave_out; - wb2_in : in wishbone_master_out; - wb2_out : out wishbone_slave_out; + wb2_in : in wishbone_master_out; + wb2_out : out wishbone_slave_out; - wb_out : out wishbone_master_out; - wb_in : in wishbone_slave_out - ); + wb_out : out wishbone_master_out; + wb_in : in wishbone_slave_out + ); end wishbone_arbiter; architecture behave of wishbone_arbiter is - type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY); - signal state : wishbone_arbiter_state_t := IDLE; + type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY); + signal state : wishbone_arbiter_state_t := IDLE; begin - wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init; - wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init; - - wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init; - - wishbone_arbiter_process: process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - state <= IDLE; - else - case state is - when IDLE => - if wb1_in.cyc = '1' then - state <= WB1_BUSY; - elsif wb2_in.cyc = '1' then - state <= WB2_BUSY; - end if; - when WB1_BUSY => - if wb1_in.cyc = '0' then - state <= IDLE; - end if; - when WB2_BUSY => - if wb2_in.cyc = '0' then - state <= IDLE; - end if; - end case; - end if; - end if; - end process; + wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init; + wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init; + + wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init; + + wishbone_arbiter_process: process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + state <= IDLE; + else + case state is + when IDLE => + if wb1_in.cyc = '1' then + state <= WB1_BUSY; + elsif wb2_in.cyc = '1' then + state <= WB2_BUSY; + end if; + when WB1_BUSY => + if wb1_in.cyc = '0' then + state <= IDLE; + end if; + when WB2_BUSY => + if wb2_in.cyc = '0' then + state <= IDLE; + end if; + end case; + end if; + end if; + end process; end behave; diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl index 6055d9c..3db03aa 100644 --- a/wishbone_types.vhdl +++ b/wishbone_types.vhdl @@ -2,26 +2,26 @@ library ieee; use ieee.std_logic_1164.all; package wishbone_types is - constant wishbone_addr_bits : integer := 64; - constant wishbone_data_bits : integer := 64; + constant wishbone_addr_bits : integer := 64; + constant wishbone_data_bits : integer := 64; - subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0); - subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0); + subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0); + subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0); - type wishbone_master_out is record - adr : wishbone_addr_type; - dat : wishbone_data_type; - cyc : std_ulogic; - stb : std_ulogic; - sel : std_ulogic_vector(7 downto 0); - we : std_ulogic; - end record; - constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0')); + type wishbone_master_out is record + adr : wishbone_addr_type; + dat : wishbone_data_type; + cyc : std_ulogic; + stb : std_ulogic; + sel : std_ulogic_vector(7 downto 0); + we : std_ulogic; + end record; + constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0')); - type wishbone_slave_out is record - dat : wishbone_data_type; - ack : std_ulogic; - end record; - constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0')); + type wishbone_slave_out is record + dat : wishbone_data_type; + ack : std_ulogic; + end record; + constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0')); end package wishbone_types;