From e5a30a1358f9a7f09c36f54425749c278cfb87e5 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 23 Apr 2020 14:28:59 +1000 Subject: [PATCH] Wire up sim uart TX interrupt TX is always ready, so just always sent interrupt when enabled. No RX interrupt. Signed-off-by: Michael Neuling --- sim_uart.vhdl | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sim_uart.vhdl b/sim_uart.vhdl index 5881560..6641da5 100644 --- a/sim_uart.vhdl +++ b/sim_uart.vhdl @@ -43,6 +43,9 @@ entity pp_soc_uart is txd : out std_logic; rxd : in std_logic; + -- Interrupt signal: + irq : out std_logic; + -- Wishbone ports: wb_adr_in : in std_logic_vector(11 downto 0); wb_dat_in : in std_logic_vector( 7 downto 0); @@ -70,6 +73,10 @@ begin wb_ack_out <= wb_ack and wb_cyc_in and wb_stb_in; + -- For the sim console, the transmit buffer is always empty, so always + -- interrupt if enabled. No recieve interrupt. + irq <= irq_tx_ready_enable; + wishbone: process(clk) variable sim_tmp : std_logic_vector(63 downto 0); begin