From e60840eabcec6c2fb39fa421f9ee69a23d44a7d5 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 18 Nov 2025 22:42:37 +0000 Subject: [PATCH] FPU: Make sure FR and FI in FPSCR get reset on special-case arith instructions Arithmetic instructions where the result is determined without doing any actual computation (i.e. the input(s) are NaNs, infinities, zeroes etc.) weren't resetting FR and FI properly. This combines the two blocks that handle the r.cycle_1_ar = 1 case to fix it. Signed-off-by: Paul Mackerras --- fpu.vhdl | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/fpu.vhdl b/fpu.vhdl index 16583cb..e1bc8fd 100644 --- a/fpu.vhdl +++ b/fpu.vhdl @@ -1354,12 +1354,6 @@ begin rsgn_op := RSGN_NOP; rcls_op <= RCLS_NOP; - if r.cycle_1_ar = '1' then - v.fpscr(FPSCR_FR) := '0'; - v.fpscr(FPSCR_FI) := '0'; - v.result_class := FINITE; - end if; - case r.state is when IDLE => v.invalid := '0'; @@ -3077,6 +3071,9 @@ begin -- Handle exceptions and special cases for arithmetic operations if r.cycle_1_ar = '1' then v.fpscr := r.fpscr or scinfo.new_fpscr; + v.fpscr(FPSCR_FR) := '0'; + v.fpscr(FPSCR_FI) := '0'; + v.result_class := FINITE; invalid := scinfo.invalid; zero_divide := scinfo.zero_divide; qnan_result := scinfo.qnan_result;