From e638c3e8ae9ca95c2dc5c831eb5fd7f72b173825 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sat, 19 Oct 2019 21:22:33 +1100 Subject: [PATCH] fpga/bram: Generate stall signal This doesn't yet pipeline the block RAM, just generate a valid stall signal so it's compatible with a pipelined master Signed-off-by: Benjamin Herrenschmidt --- fpga/mw_soc_memory.vhdl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fpga/mw_soc_memory.vhdl b/fpga/mw_soc_memory.vhdl index e9ace36..af31c89 100644 --- a/fpga/mw_soc_memory.vhdl +++ b/fpga/mw_soc_memory.vhdl @@ -65,7 +65,8 @@ begin wb_adr_in <= wishbone_in.adr(log2(MEMORY_SIZE) - 1 downto 0); - wishbone_out.ack <= read_ack and wishbone_in.stb; + wishbone_out.ack <= read_ack and wishbone_in.cyc and wishbone_in.stb; + wishbone_out.stall <= '0' when wishbone_in.cyc = '0' else not wishbone_out.ack; memory_0: process(clk) begin