diff --git a/core_tb.vhdl b/core_tb.vhdl
index 90fc30c..8597e06 100644
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -19,7 +19,7 @@ begin
     soc0: entity work.soc
 	generic map(
 	    SIM => true,
-	    MEMORY_SIZE => 524288,
+	    MEMORY_SIZE => (384*1024),
 	    RAM_INIT_FILE => "main_ram.bin",
 	    RESET_LOW => false
 	    )
diff --git a/fpga/toplevel.vhdl b/fpga/toplevel.vhdl
index 38af730..a3b8282 100644
--- a/fpga/toplevel.vhdl
+++ b/fpga/toplevel.vhdl
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity toplevel is
     generic (
-	MEMORY_SIZE   : positive := 524288;
+	MEMORY_SIZE   : positive := (384*1024);
 	RAM_INIT_FILE : string   := "firmware.hex";
 	RESET_LOW     : boolean  := true;
 	CLK_INPUT     : positive := 100000000;