From f9dc3ecdc811dcc8b55ba3915b23c36b9e3d6052 Mon Sep 17 00:00:00 2001
From: Paul Mackerras <paulus@ozlabs.org>
Date: Sat, 20 Dec 2025 17:29:45 +1100
Subject: [PATCH] execute1: Correct FSCR[IC] value for prefix unavailable
 interrupt

FSCR[IC] should be set to 13 for a prefix unavailable interrupt, not 11.
To avoid this type of mistake, use the same symbols for setting IC as
for the bit numbers in the rest of FSCR.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 execute1.vhdl | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/execute1.vhdl b/execute1.vhdl
index 15d5333..03f0ce3 100644
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -1624,7 +1624,7 @@ begin
             -- misaligned prefixed instructions, which has higher priority than
             -- other facility unavailable interrupts.
             v.exception := '1';
-            v.ic := x"b";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_PREFIX, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
@@ -1666,7 +1666,7 @@ begin
             ctrl.fscr_scv = '0' then
             -- Facility unavailable for scv instruction
             v.exception := '1';
-            v.ic := x"c";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_SCV, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
@@ -1674,7 +1674,7 @@ begin
             ctrl.fscr_tar = '0' then
             -- Facility unavailable for TAR access
             v.exception := '1';
-            v.ic := x"8";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_TAR, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';
 
@@ -1682,7 +1682,7 @@ begin
             ctrl.fscr_dscr = '0' then
             -- Facility unavailable for DSCR access
             v.exception := '1';
-            v.ic := x"2";
+            v.ic := std_ulogic_vector(to_unsigned(FSCR_DSCR, 4));
             v.e.intr_vec := 16#f60#;
             v.se.write_ic := '1';