diff --git a/decode1.vhdl b/decode1.vhdl index 73f2729..a7cb442 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -103,14 +103,14 @@ architecture behaviour of decode1 is INSN_bclr => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, SPR, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE), INSN_bctar => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, SPR, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE), INSN_bperm => (ALU, NONE, OP_BPERM, NONE, RB, NONE, RS, RA, ADD, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_brh => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_brw => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_brd => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_cbcdtd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_cdtbcd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_brh => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "010", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_brw => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "010", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_brd => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "010", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_cbcdtd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, LOG, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_cdtbcd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, LOG, "101", '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_cfuged => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_cmp => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE), - INSN_cmpb => (ALU, NONE, OP_CMPB, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_cmpb => (ALU, NONE, OP_CMPB, NONE, RB, NONE, RS, RA, LOG, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_cmpeqb => (ALU, NONE, OP_CMPEQB, RA, RB, NONE, NONE, NONE, ADD, "010", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_cmpi => (ALU, NONE, OP_CMP, RA, IMM, CONST_SI, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE), INSN_cmpl => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), @@ -143,10 +143,10 @@ architecture behaviour of decode1 is INSN_divweu => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RCOE, '0', '0', '0', NONE), INSN_divwu => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RCOE, '0', '0', '0', NONE), INSN_eieio => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_eqv => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), - INSN_extsb => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), - INSN_extsh => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), - INSN_extsw => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), + INSN_eqv => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, LOG, "001", '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), + INSN_extsb => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "110", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), + INSN_extsh => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "110", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), + INSN_extsw => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "110", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), INSN_extswsli => (ALU, NONE, OP_EXTSWSLI, NONE, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), INSN_fabs => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), INSN_fadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), @@ -262,7 +262,7 @@ architecture behaviour of decode1 is INSN_mfcr => (ALU, NONE, OP_MFCR, NONE, IMM, NONE, NONE, RT, MSC, "101", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_mffs => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), INSN_mfmsr => (ALU, NONE, OP_MFMSR, NONE, IMM, NONE, NONE, RT, MSC, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '1', NONE), - INSN_mfspr => (ALU, NONE, OP_MFSPR, NONE, IMM, NONE, RS, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_mfspr => (ALU, NONE, OP_MFSPR, NONE, IMM, NONE, RS, RT, LOG, "111", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_modsd => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE), INSN_modsw => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', NONE, '0', '0', '0', NONE), INSN_modud => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), @@ -273,7 +273,7 @@ architecture behaviour of decode1 is INSN_mtfsfi => (FPU, FPU, OP_FP_MISC, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), INSN_mtmsr => (ALU, NONE, OP_MTMSRD, NONE, IMM, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '1', '0', NONE), INSN_mtmsrd => (ALU, NONE, OP_MTMSRD, NONE, IMM, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE), - INSN_mtspr => (ALU, NONE, OP_MTSPR, NONE, IMM, NONE, RS, NONE, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_mtspr => (ALU, NONE, OP_MTSPR, NONE, IMM, NONE, RS, NONE, LOG, "111", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_mulhd => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, NONE, RT, ADD, "010", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE), INSN_mulhdu => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, NONE, RT, ADD, "010", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), INSN_mulhw => (ALU, NONE, OP_MUL_H32, RA, RB, NONE, NONE, RT, ADD, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE), @@ -312,8 +312,8 @@ architecture behaviour of decode1 is INSN_popcntb => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_popcntd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_popcntw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_prtyd => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_prtyw => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_prtyd => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, LOG, "011", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_prtyw => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, LOG, "011", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), INSN_rfid => (ALU, NONE, OP_RFID, NONE, IMM, NONE, NONE, NONE, SPR, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE), INSN_rfscv => (ALU, NONE, OP_RFID, NONE, IMM, NONE, NONE, NONE, SPR, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE), INSN_rldcl => (ALU, NONE, OP_RLCL, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), @@ -390,9 +390,9 @@ architecture behaviour of decode1 is INSN_tw => (ALU, NONE, OP_TRAP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE), INSN_twi => (ALU, NONE, OP_TRAP, RA, IMM, CONST_SI, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE), INSN_wait => (ALU, NONE, OP_WAIT, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE), - INSN_xor => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), - INSN_xori => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), - INSN_xoris => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI_HI, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_xor => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, LOG, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE), + INSN_xori => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI, RS, RA, LOG, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), + INSN_xoris => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI_HI, RS, RA, LOG, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE), others => (ALU, NONE, OP_ILLEGAL, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE) ); diff --git a/decode2.vhdl b/decode2.vhdl index 653050e..3a48134 100644 --- a/decode2.vhdl +++ b/decode2.vhdl @@ -617,12 +617,6 @@ begin if op = OP_MFSPR then if d_in.ram_spr.valid = '1' then v.e.result_sel := SPR; -- ramspr_result - elsif d_in.spr_info.valid = '0' or d_in.spr_info.wonly = '1' or - d_in.spr_info.noop = '1' then - -- Privileged mfspr to invalid/unimplemented SPR numbers - -- writes the contents of RT back to RT (i.e. it's a no-op) - -- as does any mfspr from the reserved/noop SPR numbers - v.e.result_sel := LOG; -- logical_result end if; end if; v.e.privileged := d_in.decode.privileged; diff --git a/execute1.vhdl b/execute1.vhdl index 6fd41c8..8c6155a 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -496,7 +496,7 @@ begin port map ( rs => c_in, rb => b_in, - op => e_in.insn_type, + op => e_in.sub_select, invert_in => e_in.invert_a, invert_out => e_in.invert_out, is_signed => e_in.is_signed, diff --git a/logical.vhdl b/logical.vhdl index 792a896..3befa70 100644 --- a/logical.vhdl +++ b/logical.vhdl @@ -10,7 +10,7 @@ entity logical is port ( rs : in std_ulogic_vector(63 downto 0); rb : in std_ulogic_vector(63 downto 0); - op : in insn_type_t; + op : in subresult_sel_t; invert_in : in std_ulogic; invert_out : in std_ulogic; is_signed : in std_ulogic; @@ -114,7 +114,7 @@ begin end if; case op is - when OP_LOGIC => + when "000" => -- OP_LOGIC -- for now, abuse the 'is_signed' field to indicate inversion of RS rs_adj := rs; if is_signed = '1' then @@ -124,13 +124,13 @@ begin if invert_out = '1' then tmp := not tmp; end if; - when OP_XOR => + when "001" => -- OP_XOR tmp := rs xor rb; if invert_out = '1' then tmp := not tmp; end if; - when OP_BREV => + when "010" => -- OP_BREV if datalen(3) = '1' then tmp := rs( 7 downto 0) & rs(15 downto 8) & rs(23 downto 16) & rs(31 downto 24) & rs(39 downto 32) & rs(47 downto 40) & rs(55 downto 48) & rs(63 downto 56); @@ -142,11 +142,11 @@ begin rs(23 downto 16) & rs(31 downto 24) & rs( 7 downto 0) & rs(15 downto 8); end if; - when OP_PRTY => + when "011" => -- OP_PRTY tmp := parity; - when OP_CMPB => + when "100" => -- OP_CMPB tmp := ppc_cmpb(rs, rb); - when OP_BCD => + when "101" => -- OP_BCD -- invert_in is abused to indicate direction of conversion if invert_in = '0' then -- cbcdtd @@ -157,7 +157,7 @@ begin tmp := x"00" & dpd_to_bcd(rs(51 downto 42)) & dpd_to_bcd(rs(41 downto 32)) & x"00" & dpd_to_bcd(rs(19 downto 10)) & dpd_to_bcd(rs(9 downto 0)); end if; - when OP_EXTS => + when "110" => -- OP_EXTS -- note datalen is a 1-hot encoding negative := (datalen(0) and rs(7)) or (datalen(1) and rs(15)) or