Rather than having update and decode logic for each individual PLRU
as well as a register to store the current PLRU state, we now put the
PLRU state in a little RAM, which will typically use LUT RAM on FPGAs,
and have just a single copy of the logic to calculate the pseudo-LRU
way and to update the PLRU state. This logic is in the plrufn module
and is just combinatorial logic. A new module was created for this as
other parts of the system are still using plru.vhdl.
The PLRU RAM in the icache is read asynchronously in the cycle
after the cache tag matching is done. At the end of that cycle the
PLRU RAM entry is updated if the access was a cache hit, or a victim
way is calculated and stored if the access was a cache miss and
miss handling is starting in this cycle.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
