################################################################################ # clkin, reset, uart pins... ################################################################################ set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }]; set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]; set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]; ################################################################################ # LEDs ################################################################################ set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led0_n }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led1_n }]; ################################################################################ # SPI Flash ################################################################################ema set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }]; set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }]; set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }]; set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }]; set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }]; ################################################################################ # Micro SD ################################################################################ set_property -dict { PACKAGE_PIN M5 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[0] }]; set_property -dict { PACKAGE_PIN M7 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[1] }]; set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[2] }]; set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[3] }]; set_property -dict { PACKAGE_PIN J8 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_cmd }]; set_property -dict { PACKAGE_PIN L4 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }]; set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }]; # Put registers into IOBs to improve timing set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}] ################################################################################ # PMOD header J10 (high-speed, no protection resisters) ################################################################################ #set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_1 }]; #set_property -dict { PACKAGE_PIN G5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_2 }]; #set_property -dict { PACKAGE_PIN G7 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_3 }]; #set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_4 }]; #set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_7 }]; #set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_8 }]; #set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_9 }]; #set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_10 }]; ################################################################################ # PMOD header J11 (high-speed, no protection resisters) ################################################################################ #set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_1 }]; #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_2 }]; #set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_3 }]; #set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_4 }]; #set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_7 }]; #set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_8 }]; #set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_9 }]; #set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_10 }]; ################################################################################ # HDR 20X2 connector ################################################################################ ## TODO ################################################################################ # Ethernet (generated by LiteX) ################################################################################ # eth_clocks:0.tx set_property LOC M2 [get_ports {eth_clocks_tx}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}] # eth_clocks:0.gtx set_property LOC U1 [get_ports {eth_clocks_gtx}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_gtx}] # eth_clocks:0.rx set_property LOC P4 [get_ports {eth_clocks_rx}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}] # eth:0.rst_n set_property LOC R1 [get_ports {eth_rst_n}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}] # eth:0.mdio set_property LOC H1 [get_ports {eth_mdio}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}] # eth:0.mdc set_property LOC H2 [get_ports {eth_mdc}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}] # eth:0.rx_dv set_property LOC L3 [get_ports {eth_rx_dv}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}] # eth:0.rx_er set_property LOC U5 [get_ports {eth_rx_er}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}] # eth:0.rx_data set_property LOC M4 [get_ports {eth_rx_data[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}] # eth:0.rx_data set_property LOC N3 [get_ports {eth_rx_data[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}] # eth:0.rx_data set_property LOC N4 [get_ports {eth_rx_data[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}] # eth:0.rx_data set_property LOC P3 [get_ports {eth_rx_data[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}] # eth:0.rx_data set_property LOC R3 [get_ports {eth_rx_data[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[4]}] # eth:0.rx_data set_property LOC T3 [get_ports {eth_rx_data[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[5]}] # eth:0.rx_data set_property LOC T4 [get_ports {eth_rx_data[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[6]}] # eth:0.rx_data set_property LOC T5 [get_ports {eth_rx_data[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[7]}] # eth:0.tx_en set_property LOC T2 [get_ports {eth_tx_en}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}] # eth:0.tx_er set_property LOC J1 [get_ports {eth_tx_er}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_er}] # eth:0.tx_data set_property LOC R2 [get_ports {eth_tx_data[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}] # eth:0.tx_data set_property LOC P1 [get_ports {eth_tx_data[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}] # eth:0.tx_data set_property LOC N2 [get_ports {eth_tx_data[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}] # eth:0.tx_data set_property LOC N1 [get_ports {eth_tx_data[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}] # eth:0.tx_data set_property LOC M1 [get_ports {eth_tx_data[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[4]}] # eth:0.tx_data set_property LOC L2 [get_ports {eth_tx_data[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[5]}] # eth:0.tx_data set_property LOC K2 [get_ports {eth_tx_data[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[6]}] # eth:0.tx_data set_property LOC K1 [get_ports {eth_tx_data[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[7]}] # eth:0.col set_property LOC U4 [get_ports {eth_col}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}] # eth:0.crs set_property LOC U2 [get_ports {eth_crs}] set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}] ################################################################################ # DRAM (generated by LiteX) ################################################################################ # ddram:0.a set_property LOC E17 [get_ports {ddram_a[0]}] set_property SLEW FAST [get_ports {ddram_a[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}] # ddram:0.a set_property LOC G17 [get_ports {ddram_a[1]}] set_property SLEW FAST [get_ports {ddram_a[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}] # ddram:0.a set_property LOC F17 [get_ports {ddram_a[2]}] set_property SLEW FAST [get_ports {ddram_a[2]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}] # ddram:0.a set_property LOC C17 [get_ports {ddram_a[3]}] set_property SLEW FAST [get_ports {ddram_a[3]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}] # ddram:0.a set_property LOC G16 [get_ports {ddram_a[4]}] set_property SLEW FAST [get_ports {ddram_a[4]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}] # ddram:0.a set_property LOC D16 [get_ports {ddram_a[5]}] set_property SLEW FAST [get_ports {ddram_a[5]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}] # ddram:0.a set_property LOC H16 [get_ports {ddram_a[6]}] set_property SLEW FAST [get_ports {ddram_a[6]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}] # ddram:0.a set_property LOC E16 [get_ports {ddram_a[7]}] set_property SLEW FAST [get_ports {ddram_a[7]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}] # ddram:0.a set_property LOC H14 [get_ports {ddram_a[8]}] set_property SLEW FAST [get_ports {ddram_a[8]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}] # ddram:0.a set_property LOC F15 [get_ports {ddram_a[9]}] set_property SLEW FAST [get_ports {ddram_a[9]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}] # ddram:0.a set_property LOC F20 [get_ports {ddram_a[10]}] set_property SLEW FAST [get_ports {ddram_a[10]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}] # ddram:0.a set_property LOC H15 [get_ports {ddram_a[11]}] set_property SLEW FAST [get_ports {ddram_a[11]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}] # ddram:0.a set_property LOC C18 [get_ports {ddram_a[12]}] set_property SLEW FAST [get_ports {ddram_a[12]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}] # ddram:0.a set_property LOC G15 [get_ports {ddram_a[13]}] set_property SLEW FAST [get_ports {ddram_a[13]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}] # ddram:0.ba set_property LOC B17 [get_ports {ddram_ba[0]}] set_property SLEW FAST [get_ports {ddram_ba[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}] # ddram:0.ba set_property LOC D18 [get_ports {ddram_ba[1]}] set_property SLEW FAST [get_ports {ddram_ba[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}] # ddram:0.ba set_property LOC A17 [get_ports {ddram_ba[2]}] set_property SLEW FAST [get_ports {ddram_ba[2]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}] # ddram:0.ras_n set_property LOC A19 [get_ports {ddram_ras_n}] set_property SLEW FAST [get_ports {ddram_ras_n}] set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}] # ddram:0.cas_n set_property LOC B19 [get_ports {ddram_cas_n}] set_property SLEW FAST [get_ports {ddram_cas_n}] set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}] # ddram:0.we_n set_property LOC A18 [get_ports {ddram_we_n}] set_property SLEW FAST [get_ports {ddram_we_n}] set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}] # ddram:0.dm set_property LOC A22 [get_ports {ddram_dm[0]}] set_property SLEW FAST [get_ports {ddram_dm[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}] # ddram:0.dm set_property LOC C22 [get_ports {ddram_dm[1]}] set_property SLEW FAST [get_ports {ddram_dm[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}] # ddram:0.dq set_property LOC D21 [get_ports {ddram_dq[0]}] set_property SLEW FAST [get_ports {ddram_dq[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}] # ddram:0.dq set_property LOC C21 [get_ports {ddram_dq[1]}] set_property SLEW FAST [get_ports {ddram_dq[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}] # ddram:0.dq set_property LOC B22 [get_ports {ddram_dq[2]}] set_property SLEW FAST [get_ports {ddram_dq[2]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}] # ddram:0.dq set_property LOC B21 [get_ports {ddram_dq[3]}] set_property SLEW FAST [get_ports {ddram_dq[3]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}] # ddram:0.dq set_property LOC D19 [get_ports {ddram_dq[4]}] set_property SLEW FAST [get_ports {ddram_dq[4]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}] # ddram:0.dq set_property LOC E20 [get_ports {ddram_dq[5]}] set_property SLEW FAST [get_ports {ddram_dq[5]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}] # ddram:0.dq set_property LOC C19 [get_ports {ddram_dq[6]}] set_property SLEW FAST [get_ports {ddram_dq[6]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}] # ddram:0.dq set_property LOC D20 [get_ports {ddram_dq[7]}] set_property SLEW FAST [get_ports {ddram_dq[7]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}] # ddram:0.dq set_property LOC C23 [get_ports {ddram_dq[8]}] set_property SLEW FAST [get_ports {ddram_dq[8]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}] # ddram:0.dq set_property LOC D23 [get_ports {ddram_dq[9]}] set_property SLEW FAST [get_ports {ddram_dq[9]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}] # ddram:0.dq set_property LOC B24 [get_ports {ddram_dq[10]}] set_property SLEW FAST [get_ports {ddram_dq[10]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}] # ddram:0.dq set_property LOC B25 [get_ports {ddram_dq[11]}] set_property SLEW FAST [get_ports {ddram_dq[11]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}] # ddram:0.dq set_property LOC C24 [get_ports {ddram_dq[12]}] set_property SLEW FAST [get_ports {ddram_dq[12]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}] # ddram:0.dq set_property LOC C26 [get_ports {ddram_dq[13]}] set_property SLEW FAST [get_ports {ddram_dq[13]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}] # ddram:0.dq set_property LOC A25 [get_ports {ddram_dq[14]}] set_property SLEW FAST [get_ports {ddram_dq[14]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}] # ddram:0.dq set_property LOC B26 [get_ports {ddram_dq[15]}] set_property SLEW FAST [get_ports {ddram_dq[15]}] set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}] # ddram:0.dqs_p set_property LOC B20 [get_ports {ddram_dqs_p[0]}] set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}] # ddram:0.dqs_p set_property LOC A23 [get_ports {ddram_dqs_p[1]}] set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}] # ddram:0.dqs_n set_property LOC A20 [get_ports {ddram_dqs_n[0]}] set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}] # ddram:0.dqs_n set_property LOC A24 [get_ports {ddram_dqs_n[1]}] set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}] set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}] # ddram:0.clk_p set_property LOC F18 [get_ports {ddram_clk_p}] set_property SLEW FAST [get_ports {ddram_clk_p}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}] # ddram:0.clk_n set_property LOC F19 [get_ports {ddram_clk_n}] set_property SLEW FAST [get_ports {ddram_clk_n}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}] # ddram:0.cke set_property LOC E18 [get_ports {ddram_cke}] set_property SLEW FAST [get_ports {ddram_cke}] set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}] # ddram:0.odt set_property LOC G19 [get_ports {ddram_odt}] set_property SLEW FAST [get_ports {ddram_odt}] set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}] # ddram:0.reset_n set_property LOC H17 [get_ports {ddram_reset_n}] set_property SLEW FAST [get_ports {ddram_reset_n}] set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}] ################################################################################ # Design constraints and bitsteam attributes ################################################################################ set_property INTERNAL_VREF 0.675 [get_iobanks 16] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] set_property CONFIG_MODE SPIx4 [current_design] ################################################################################ # Clock constraints ################################################################################ create_clock -name sys_clk_pin -period 20.00 [get_ports { ext_clk }]; create_clock -name eth_rx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_rx_clk] create_clock -name eth_tx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_tx_clk] set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -asynchronous set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous ################################################################################ # False path constraints (from LiteX as they relate to LiteDRAM and LiteEth) ################################################################################ set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]