// ----------------------------------------------------------------------------- // Auto-Generated by: __ _ __ _ __ // / / (_) /____ | |/_/ // / /__/ / __/ -_)> < // /____/_/\__/\__/_/|_| // Build your hardware, easily! // https://github.com/enjoy-digital/litex // // Filename : litedram_core.v // Device : // LiteX sha1 : -------- // Date : 2022-10-28 19:01:23 //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Module //------------------------------------------------------------------------------ module litedram_core ( input wire clk, input wire rst, output wire pll_locked, output wire [15:0] ddram_a, output wire [2:0] ddram_ba, output wire ddram_ras_n, output wire ddram_cas_n, output wire ddram_we_n, output wire ddram_cs_n, output wire [1:0] ddram_dm, inout wire [15:0] ddram_dq, inout wire [1:0] ddram_dqs_p, inout wire [1:0] ddram_dqs_n, output wire ddram_clk_p, output wire ddram_clk_n, output wire ddram_cke, output wire ddram_odt, output wire ddram_reset_n, output wire init_done, output wire init_error, input wire [29:0] wb_ctrl_adr, input wire [31:0] wb_ctrl_dat_w, output wire [31:0] wb_ctrl_dat_r, input wire [3:0] wb_ctrl_sel, input wire wb_ctrl_cyc, input wire wb_ctrl_stb, output wire wb_ctrl_ack, input wire wb_ctrl_we, input wire [2:0] wb_ctrl_cti, input wire [1:0] wb_ctrl_bte, output wire wb_ctrl_err, output wire user_clk, output wire user_rst, input wire user_port_native_0_cmd_valid, output wire user_port_native_0_cmd_ready, input wire user_port_native_0_cmd_we, input wire [25:0] user_port_native_0_cmd_addr, input wire user_port_native_0_wdata_valid, output wire user_port_native_0_wdata_ready, input wire [15:0] user_port_native_0_wdata_we, input wire [127:0] user_port_native_0_wdata_data, output wire user_port_native_0_rdata_valid, input wire user_port_native_0_rdata_ready, output wire [127:0] user_port_native_0_rdata_data ); //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ reg rst_1 = 1'd0; wire sys_clk; wire sys_rst; wire sys4x_clk; wire sys4x_dqs_clk; wire iodelay_clk; wire iodelay_rst; wire reset; reg power_down = 1'd0; wire locked; wire clkin; wire clkout0; wire clkout_buf0; wire clkout1; wire clkout_buf1; wire clkout2; wire clkout_buf2; wire clkout3; wire clkout_buf3; reg [3:0] reset_counter = 4'd15; reg ic_reset = 1'd1; reg a7ddrphy_rst_storage = 1'd0; reg a7ddrphy_rst_re = 1'd0; reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; reg a7ddrphy_dly_sel_re = 1'd0; reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; reg a7ddrphy_half_sys8x_taps_re = 1'd0; reg a7ddrphy_wlevel_en_storage = 1'd0; reg a7ddrphy_wlevel_en_re = 1'd0; reg a7ddrphy_wlevel_strobe_re = 1'd0; wire a7ddrphy_wlevel_strobe_r; reg a7ddrphy_wlevel_strobe_we = 1'd0; reg a7ddrphy_wlevel_strobe_w = 1'd0; reg a7ddrphy_rdly_dq_rst_re = 1'd0; wire a7ddrphy_rdly_dq_rst_r; reg a7ddrphy_rdly_dq_rst_we = 1'd0; reg a7ddrphy_rdly_dq_rst_w = 1'd0; reg a7ddrphy_rdly_dq_inc_re = 1'd0; wire a7ddrphy_rdly_dq_inc_r; reg a7ddrphy_rdly_dq_inc_we = 1'd0; reg a7ddrphy_rdly_dq_inc_w = 1'd0; reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; wire a7ddrphy_rdly_dq_bitslip_rst_r; reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; wire a7ddrphy_rdly_dq_bitslip_r; reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; wire a7ddrphy_wdly_dq_bitslip_rst_r; reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; wire a7ddrphy_wdly_dq_bitslip_r; reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; reg [1:0] a7ddrphy_rdphase_storage = 2'd2; reg a7ddrphy_rdphase_re = 1'd0; reg [1:0] a7ddrphy_wrphase_storage = 2'd3; reg a7ddrphy_wrphase_re = 1'd0; wire [15:0] a7ddrphy_dfi_p0_address; wire [2:0] a7ddrphy_dfi_p0_bank; wire a7ddrphy_dfi_p0_cas_n; wire a7ddrphy_dfi_p0_cs_n; wire a7ddrphy_dfi_p0_ras_n; wire a7ddrphy_dfi_p0_we_n; wire a7ddrphy_dfi_p0_cke; wire a7ddrphy_dfi_p0_odt; wire a7ddrphy_dfi_p0_reset_n; wire a7ddrphy_dfi_p0_act_n; wire [31:0] a7ddrphy_dfi_p0_wrdata; wire a7ddrphy_dfi_p0_wrdata_en; wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; wire a7ddrphy_dfi_p0_rddata_en; reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; wire a7ddrphy_dfi_p0_rddata_valid; wire [15:0] a7ddrphy_dfi_p1_address; wire [2:0] a7ddrphy_dfi_p1_bank; wire a7ddrphy_dfi_p1_cas_n; wire a7ddrphy_dfi_p1_cs_n; wire a7ddrphy_dfi_p1_ras_n; wire a7ddrphy_dfi_p1_we_n; wire a7ddrphy_dfi_p1_cke; wire a7ddrphy_dfi_p1_odt; wire a7ddrphy_dfi_p1_reset_n; wire a7ddrphy_dfi_p1_act_n; wire [31:0] a7ddrphy_dfi_p1_wrdata; wire a7ddrphy_dfi_p1_wrdata_en; wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; wire a7ddrphy_dfi_p1_rddata_en; reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; wire a7ddrphy_dfi_p1_rddata_valid; wire [15:0] a7ddrphy_dfi_p2_address; wire [2:0] a7ddrphy_dfi_p2_bank; wire a7ddrphy_dfi_p2_cas_n; wire a7ddrphy_dfi_p2_cs_n; wire a7ddrphy_dfi_p2_ras_n; wire a7ddrphy_dfi_p2_we_n; wire a7ddrphy_dfi_p2_cke; wire a7ddrphy_dfi_p2_odt; wire a7ddrphy_dfi_p2_reset_n; wire a7ddrphy_dfi_p2_act_n; wire [31:0] a7ddrphy_dfi_p2_wrdata; wire a7ddrphy_dfi_p2_wrdata_en; wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; wire a7ddrphy_dfi_p2_rddata_en; reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; wire a7ddrphy_dfi_p2_rddata_valid; wire [15:0] a7ddrphy_dfi_p3_address; wire [2:0] a7ddrphy_dfi_p3_bank; wire a7ddrphy_dfi_p3_cas_n; wire a7ddrphy_dfi_p3_cs_n; wire a7ddrphy_dfi_p3_ras_n; wire a7ddrphy_dfi_p3_we_n; wire a7ddrphy_dfi_p3_cke; wire a7ddrphy_dfi_p3_odt; wire a7ddrphy_dfi_p3_reset_n; wire a7ddrphy_dfi_p3_act_n; wire [31:0] a7ddrphy_dfi_p3_wrdata; wire a7ddrphy_dfi_p3_wrdata_en; wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; wire a7ddrphy_dfi_p3_rddata_en; reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; wire a7ddrphy_dfi_p3_rddata_valid; wire a7ddrphy_sd_clk_se_nodelay; wire [2:0] a7ddrphy_pads_ba; reg a7ddrphy_dqs_oe = 1'd0; wire a7ddrphy_dqs_preamble; wire a7ddrphy_dqs_postamble; wire a7ddrphy_dqs_oe_delay_tappeddelayline; reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; reg a7ddrphy_dqspattern0 = 1'd0; reg a7ddrphy_dqspattern1 = 1'd0; reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; wire a7ddrphy_dqs_o_no_delay0; wire a7ddrphy_dqs_t0; reg [7:0] a7ddrphy_bitslip00 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; wire a7ddrphy0; wire a7ddrphy_dqs_o_no_delay1; wire a7ddrphy_dqs_t1; reg [7:0] a7ddrphy_bitslip10 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; wire a7ddrphy1; reg [7:0] a7ddrphy_bitslip01 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; reg [7:0] a7ddrphy_bitslip11 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; wire a7ddrphy_dq_oe; wire a7ddrphy_dq_oe_delay_tappeddelayline; reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; wire a7ddrphy_dq_o_nodelay0; wire a7ddrphy_dq_i_nodelay0; wire a7ddrphy_dq_i_delayed0; wire a7ddrphy_dq_t0; reg [7:0] a7ddrphy_bitslip02 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; wire [7:0] a7ddrphy_bitslip03; reg [7:0] a7ddrphy_bitslip04 = 8'd0; reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; wire a7ddrphy_dq_o_nodelay1; wire a7ddrphy_dq_i_nodelay1; wire a7ddrphy_dq_i_delayed1; wire a7ddrphy_dq_t1; reg [7:0] a7ddrphy_bitslip12 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; wire [7:0] a7ddrphy_bitslip13; reg [7:0] a7ddrphy_bitslip14 = 8'd0; reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; wire a7ddrphy_dq_o_nodelay2; wire a7ddrphy_dq_i_nodelay2; wire a7ddrphy_dq_i_delayed2; wire a7ddrphy_dq_t2; reg [7:0] a7ddrphy_bitslip20 = 8'd0; reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip21; reg [7:0] a7ddrphy_bitslip22 = 8'd0; reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay3; wire a7ddrphy_dq_i_nodelay3; wire a7ddrphy_dq_i_delayed3; wire a7ddrphy_dq_t3; reg [7:0] a7ddrphy_bitslip30 = 8'd0; reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip31; reg [7:0] a7ddrphy_bitslip32 = 8'd0; reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay4; wire a7ddrphy_dq_i_nodelay4; wire a7ddrphy_dq_i_delayed4; wire a7ddrphy_dq_t4; reg [7:0] a7ddrphy_bitslip40 = 8'd0; reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip41; reg [7:0] a7ddrphy_bitslip42 = 8'd0; reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay5; wire a7ddrphy_dq_i_nodelay5; wire a7ddrphy_dq_i_delayed5; wire a7ddrphy_dq_t5; reg [7:0] a7ddrphy_bitslip50 = 8'd0; reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip51; reg [7:0] a7ddrphy_bitslip52 = 8'd0; reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay6; wire a7ddrphy_dq_i_nodelay6; wire a7ddrphy_dq_i_delayed6; wire a7ddrphy_dq_t6; reg [7:0] a7ddrphy_bitslip60 = 8'd0; reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip61; reg [7:0] a7ddrphy_bitslip62 = 8'd0; reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay7; wire a7ddrphy_dq_i_nodelay7; wire a7ddrphy_dq_i_delayed7; wire a7ddrphy_dq_t7; reg [7:0] a7ddrphy_bitslip70 = 8'd0; reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip71; reg [7:0] a7ddrphy_bitslip72 = 8'd0; reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay8; wire a7ddrphy_dq_i_nodelay8; wire a7ddrphy_dq_i_delayed8; wire a7ddrphy_dq_t8; reg [7:0] a7ddrphy_bitslip80 = 8'd0; reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip81; reg [7:0] a7ddrphy_bitslip82 = 8'd0; reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay9; wire a7ddrphy_dq_i_nodelay9; wire a7ddrphy_dq_i_delayed9; wire a7ddrphy_dq_t9; reg [7:0] a7ddrphy_bitslip90 = 8'd0; reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip91; reg [7:0] a7ddrphy_bitslip92 = 8'd0; reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay10; wire a7ddrphy_dq_i_nodelay10; wire a7ddrphy_dq_i_delayed10; wire a7ddrphy_dq_t10; reg [7:0] a7ddrphy_bitslip100 = 8'd0; reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip101; reg [7:0] a7ddrphy_bitslip102 = 8'd0; reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay11; wire a7ddrphy_dq_i_nodelay11; wire a7ddrphy_dq_i_delayed11; wire a7ddrphy_dq_t11; reg [7:0] a7ddrphy_bitslip110 = 8'd0; reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip111; reg [7:0] a7ddrphy_bitslip112 = 8'd0; reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay12; wire a7ddrphy_dq_i_nodelay12; wire a7ddrphy_dq_i_delayed12; wire a7ddrphy_dq_t12; reg [7:0] a7ddrphy_bitslip120 = 8'd0; reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip121; reg [7:0] a7ddrphy_bitslip122 = 8'd0; reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay13; wire a7ddrphy_dq_i_nodelay13; wire a7ddrphy_dq_i_delayed13; wire a7ddrphy_dq_t13; reg [7:0] a7ddrphy_bitslip130 = 8'd0; reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip131; reg [7:0] a7ddrphy_bitslip132 = 8'd0; reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay14; wire a7ddrphy_dq_i_nodelay14; wire a7ddrphy_dq_i_delayed14; wire a7ddrphy_dq_t14; reg [7:0] a7ddrphy_bitslip140 = 8'd0; reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip141; reg [7:0] a7ddrphy_bitslip142 = 8'd0; reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; wire a7ddrphy_dq_o_nodelay15; wire a7ddrphy_dq_i_nodelay15; wire a7ddrphy_dq_i_delayed15; wire a7ddrphy_dq_t15; reg [7:0] a7ddrphy_bitslip150 = 8'd0; reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; wire [7:0] a7ddrphy_bitslip151; reg [7:0] a7ddrphy_bitslip152 = 8'd0; reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; wire [15:0] litedramcore_slave_p0_address; wire [2:0] litedramcore_slave_p0_bank; wire litedramcore_slave_p0_cas_n; wire litedramcore_slave_p0_cs_n; wire litedramcore_slave_p0_ras_n; wire litedramcore_slave_p0_we_n; wire litedramcore_slave_p0_cke; wire litedramcore_slave_p0_odt; wire litedramcore_slave_p0_reset_n; wire litedramcore_slave_p0_act_n; wire [31:0] litedramcore_slave_p0_wrdata; wire litedramcore_slave_p0_wrdata_en; wire [3:0] litedramcore_slave_p0_wrdata_mask; wire litedramcore_slave_p0_rddata_en; reg [31:0] litedramcore_slave_p0_rddata = 32'd0; reg litedramcore_slave_p0_rddata_valid = 1'd0; wire [15:0] litedramcore_slave_p1_address; wire [2:0] litedramcore_slave_p1_bank; wire litedramcore_slave_p1_cas_n; wire litedramcore_slave_p1_cs_n; wire litedramcore_slave_p1_ras_n; wire litedramcore_slave_p1_we_n; wire litedramcore_slave_p1_cke; wire litedramcore_slave_p1_odt; wire litedramcore_slave_p1_reset_n; wire litedramcore_slave_p1_act_n; wire [31:0] litedramcore_slave_p1_wrdata; wire litedramcore_slave_p1_wrdata_en; wire [3:0] litedramcore_slave_p1_wrdata_mask; wire litedramcore_slave_p1_rddata_en; reg [31:0] litedramcore_slave_p1_rddata = 32'd0; reg litedramcore_slave_p1_rddata_valid = 1'd0; wire [15:0] litedramcore_slave_p2_address; wire [2:0] litedramcore_slave_p2_bank; wire litedramcore_slave_p2_cas_n; wire litedramcore_slave_p2_cs_n; wire litedramcore_slave_p2_ras_n; wire litedramcore_slave_p2_we_n; wire litedramcore_slave_p2_cke; wire litedramcore_slave_p2_odt; wire litedramcore_slave_p2_reset_n; wire litedramcore_slave_p2_act_n; wire [31:0] litedramcore_slave_p2_wrdata; wire litedramcore_slave_p2_wrdata_en; wire [3:0] litedramcore_slave_p2_wrdata_mask; wire litedramcore_slave_p2_rddata_en; reg [31:0] litedramcore_slave_p2_rddata = 32'd0; reg litedramcore_slave_p2_rddata_valid = 1'd0; wire [15:0] litedramcore_slave_p3_address; wire [2:0] litedramcore_slave_p3_bank; wire litedramcore_slave_p3_cas_n; wire litedramcore_slave_p3_cs_n; wire litedramcore_slave_p3_ras_n; wire litedramcore_slave_p3_we_n; wire litedramcore_slave_p3_cke; wire litedramcore_slave_p3_odt; wire litedramcore_slave_p3_reset_n; wire litedramcore_slave_p3_act_n; wire [31:0] litedramcore_slave_p3_wrdata; wire litedramcore_slave_p3_wrdata_en; wire [3:0] litedramcore_slave_p3_wrdata_mask; wire litedramcore_slave_p3_rddata_en; reg [31:0] litedramcore_slave_p3_rddata = 32'd0; reg litedramcore_slave_p3_rddata_valid = 1'd0; reg [15:0] litedramcore_master_p0_address = 16'd0; reg [2:0] litedramcore_master_p0_bank = 3'd0; reg litedramcore_master_p0_cas_n = 1'd1; reg litedramcore_master_p0_cs_n = 1'd1; reg litedramcore_master_p0_ras_n = 1'd1; reg litedramcore_master_p0_we_n = 1'd1; reg litedramcore_master_p0_cke = 1'd0; reg litedramcore_master_p0_odt = 1'd0; reg litedramcore_master_p0_reset_n = 1'd0; reg litedramcore_master_p0_act_n = 1'd1; reg [31:0] litedramcore_master_p0_wrdata = 32'd0; reg litedramcore_master_p0_wrdata_en = 1'd0; reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; reg litedramcore_master_p0_rddata_en = 1'd0; wire [31:0] litedramcore_master_p0_rddata; wire litedramcore_master_p0_rddata_valid; reg [15:0] litedramcore_master_p1_address = 16'd0; reg [2:0] litedramcore_master_p1_bank = 3'd0; reg litedramcore_master_p1_cas_n = 1'd1; reg litedramcore_master_p1_cs_n = 1'd1; reg litedramcore_master_p1_ras_n = 1'd1; reg litedramcore_master_p1_we_n = 1'd1; reg litedramcore_master_p1_cke = 1'd0; reg litedramcore_master_p1_odt = 1'd0; reg litedramcore_master_p1_reset_n = 1'd0; reg litedramcore_master_p1_act_n = 1'd1; reg [31:0] litedramcore_master_p1_wrdata = 32'd0; reg litedramcore_master_p1_wrdata_en = 1'd0; reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; reg litedramcore_master_p1_rddata_en = 1'd0; wire [31:0] litedramcore_master_p1_rddata; wire litedramcore_master_p1_rddata_valid; reg [15:0] litedramcore_master_p2_address = 16'd0; reg [2:0] litedramcore_master_p2_bank = 3'd0; reg litedramcore_master_p2_cas_n = 1'd1; reg litedramcore_master_p2_cs_n = 1'd1; reg litedramcore_master_p2_ras_n = 1'd1; reg litedramcore_master_p2_we_n = 1'd1; reg litedramcore_master_p2_cke = 1'd0; reg litedramcore_master_p2_odt = 1'd0; reg litedramcore_master_p2_reset_n = 1'd0; reg litedramcore_master_p2_act_n = 1'd1; reg [31:0] litedramcore_master_p2_wrdata = 32'd0; reg litedramcore_master_p2_wrdata_en = 1'd0; reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; reg litedramcore_master_p2_rddata_en = 1'd0; wire [31:0] litedramcore_master_p2_rddata; wire litedramcore_master_p2_rddata_valid; reg [15:0] litedramcore_master_p3_address = 16'd0; reg [2:0] litedramcore_master_p3_bank = 3'd0; reg litedramcore_master_p3_cas_n = 1'd1; reg litedramcore_master_p3_cs_n = 1'd1; reg litedramcore_master_p3_ras_n = 1'd1; reg litedramcore_master_p3_we_n = 1'd1; reg litedramcore_master_p3_cke = 1'd0; reg litedramcore_master_p3_odt = 1'd0; reg litedramcore_master_p3_reset_n = 1'd0; reg litedramcore_master_p3_act_n = 1'd1; reg [31:0] litedramcore_master_p3_wrdata = 32'd0; reg litedramcore_master_p3_wrdata_en = 1'd0; reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; reg litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] litedramcore_master_p3_rddata; wire litedramcore_master_p3_rddata_valid; wire [15:0] litedramcore_csr_dfi_p0_address; wire [2:0] litedramcore_csr_dfi_p0_bank; reg litedramcore_csr_dfi_p0_cas_n = 1'd1; reg litedramcore_csr_dfi_p0_cs_n = 1'd1; reg litedramcore_csr_dfi_p0_ras_n = 1'd1; reg litedramcore_csr_dfi_p0_we_n = 1'd1; wire litedramcore_csr_dfi_p0_cke; wire litedramcore_csr_dfi_p0_odt; wire litedramcore_csr_dfi_p0_reset_n; reg litedramcore_csr_dfi_p0_act_n = 1'd1; wire [31:0] litedramcore_csr_dfi_p0_wrdata; wire litedramcore_csr_dfi_p0_wrdata_en; wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; wire litedramcore_csr_dfi_p0_rddata_en; reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; wire [15:0] litedramcore_csr_dfi_p1_address; wire [2:0] litedramcore_csr_dfi_p1_bank; reg litedramcore_csr_dfi_p1_cas_n = 1'd1; reg litedramcore_csr_dfi_p1_cs_n = 1'd1; reg litedramcore_csr_dfi_p1_ras_n = 1'd1; reg litedramcore_csr_dfi_p1_we_n = 1'd1; wire litedramcore_csr_dfi_p1_cke; wire litedramcore_csr_dfi_p1_odt; wire litedramcore_csr_dfi_p1_reset_n; reg litedramcore_csr_dfi_p1_act_n = 1'd1; wire [31:0] litedramcore_csr_dfi_p1_wrdata; wire litedramcore_csr_dfi_p1_wrdata_en; wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; wire litedramcore_csr_dfi_p1_rddata_en; reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; wire [15:0] litedramcore_csr_dfi_p2_address; wire [2:0] litedramcore_csr_dfi_p2_bank; reg litedramcore_csr_dfi_p2_cas_n = 1'd1; reg litedramcore_csr_dfi_p2_cs_n = 1'd1; reg litedramcore_csr_dfi_p2_ras_n = 1'd1; reg litedramcore_csr_dfi_p2_we_n = 1'd1; wire litedramcore_csr_dfi_p2_cke; wire litedramcore_csr_dfi_p2_odt; wire litedramcore_csr_dfi_p2_reset_n; reg litedramcore_csr_dfi_p2_act_n = 1'd1; wire [31:0] litedramcore_csr_dfi_p2_wrdata; wire litedramcore_csr_dfi_p2_wrdata_en; wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; wire litedramcore_csr_dfi_p2_rddata_en; reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; wire [15:0] litedramcore_csr_dfi_p3_address; wire [2:0] litedramcore_csr_dfi_p3_bank; reg litedramcore_csr_dfi_p3_cas_n = 1'd1; reg litedramcore_csr_dfi_p3_cs_n = 1'd1; reg litedramcore_csr_dfi_p3_ras_n = 1'd1; reg litedramcore_csr_dfi_p3_we_n = 1'd1; wire litedramcore_csr_dfi_p3_cke; wire litedramcore_csr_dfi_p3_odt; wire litedramcore_csr_dfi_p3_reset_n; reg litedramcore_csr_dfi_p3_act_n = 1'd1; wire [31:0] litedramcore_csr_dfi_p3_wrdata; wire litedramcore_csr_dfi_p3_wrdata_en; wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; wire litedramcore_csr_dfi_p3_rddata_en; reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; reg [15:0] litedramcore_ext_dfi_p0_address = 16'd0; reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; reg litedramcore_ext_dfi_p0_cas_n = 1'd1; reg litedramcore_ext_dfi_p0_cs_n = 1'd1; reg litedramcore_ext_dfi_p0_ras_n = 1'd1; reg litedramcore_ext_dfi_p0_we_n = 1'd1; reg litedramcore_ext_dfi_p0_cke = 1'd0; reg litedramcore_ext_dfi_p0_odt = 1'd0; reg litedramcore_ext_dfi_p0_reset_n = 1'd0; reg litedramcore_ext_dfi_p0_act_n = 1'd1; reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; reg [15:0] litedramcore_ext_dfi_p1_address = 16'd0; reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; reg litedramcore_ext_dfi_p1_cas_n = 1'd1; reg litedramcore_ext_dfi_p1_cs_n = 1'd1; reg litedramcore_ext_dfi_p1_ras_n = 1'd1; reg litedramcore_ext_dfi_p1_we_n = 1'd1; reg litedramcore_ext_dfi_p1_cke = 1'd0; reg litedramcore_ext_dfi_p1_odt = 1'd0; reg litedramcore_ext_dfi_p1_reset_n = 1'd0; reg litedramcore_ext_dfi_p1_act_n = 1'd1; reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; reg [15:0] litedramcore_ext_dfi_p2_address = 16'd0; reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; reg litedramcore_ext_dfi_p2_cas_n = 1'd1; reg litedramcore_ext_dfi_p2_cs_n = 1'd1; reg litedramcore_ext_dfi_p2_ras_n = 1'd1; reg litedramcore_ext_dfi_p2_we_n = 1'd1; reg litedramcore_ext_dfi_p2_cke = 1'd0; reg litedramcore_ext_dfi_p2_odt = 1'd0; reg litedramcore_ext_dfi_p2_reset_n = 1'd0; reg litedramcore_ext_dfi_p2_act_n = 1'd1; reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; reg [15:0] litedramcore_ext_dfi_p3_address = 16'd0; reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; reg litedramcore_ext_dfi_p3_cas_n = 1'd1; reg litedramcore_ext_dfi_p3_cs_n = 1'd1; reg litedramcore_ext_dfi_p3_ras_n = 1'd1; reg litedramcore_ext_dfi_p3_we_n = 1'd1; reg litedramcore_ext_dfi_p3_cke = 1'd0; reg litedramcore_ext_dfi_p3_odt = 1'd0; reg litedramcore_ext_dfi_p3_reset_n = 1'd0; reg litedramcore_ext_dfi_p3_act_n = 1'd1; reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; reg litedramcore_ext_dfi_sel = 1'd0; wire litedramcore_sel; wire litedramcore_cke; wire litedramcore_odt; wire litedramcore_reset_n; reg [3:0] litedramcore_storage = 4'd1; reg litedramcore_re = 1'd0; wire litedramcore_phaseinjector0_csrfield_cs; wire litedramcore_phaseinjector0_csrfield_we; wire litedramcore_phaseinjector0_csrfield_cas; wire litedramcore_phaseinjector0_csrfield_ras; wire litedramcore_phaseinjector0_csrfield_wren; wire litedramcore_phaseinjector0_csrfield_rden; reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; reg litedramcore_phaseinjector0_command_re = 1'd0; reg litedramcore_phaseinjector0_command_issue_re = 1'd0; wire litedramcore_phaseinjector0_command_issue_r; reg litedramcore_phaseinjector0_command_issue_we = 1'd0; reg litedramcore_phaseinjector0_command_issue_w = 1'd0; reg [15:0] litedramcore_phaseinjector0_address_storage = 16'd0; reg litedramcore_phaseinjector0_address_re = 1'd0; reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; reg litedramcore_phaseinjector0_baddress_re = 1'd0; reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; reg litedramcore_phaseinjector0_wrdata_re = 1'd0; reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; wire litedramcore_phaseinjector0_rddata_we; reg litedramcore_phaseinjector0_rddata_re = 1'd0; wire litedramcore_phaseinjector1_csrfield_cs; wire litedramcore_phaseinjector1_csrfield_we; wire litedramcore_phaseinjector1_csrfield_cas; wire litedramcore_phaseinjector1_csrfield_ras; wire litedramcore_phaseinjector1_csrfield_wren; wire litedramcore_phaseinjector1_csrfield_rden; reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; reg litedramcore_phaseinjector1_command_re = 1'd0; reg litedramcore_phaseinjector1_command_issue_re = 1'd0; wire litedramcore_phaseinjector1_command_issue_r; reg litedramcore_phaseinjector1_command_issue_we = 1'd0; reg litedramcore_phaseinjector1_command_issue_w = 1'd0; reg [15:0] litedramcore_phaseinjector1_address_storage = 16'd0; reg litedramcore_phaseinjector1_address_re = 1'd0; reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; reg litedramcore_phaseinjector1_baddress_re = 1'd0; reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; reg litedramcore_phaseinjector1_wrdata_re = 1'd0; reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; wire litedramcore_phaseinjector1_rddata_we; reg litedramcore_phaseinjector1_rddata_re = 1'd0; wire litedramcore_phaseinjector2_csrfield_cs; wire litedramcore_phaseinjector2_csrfield_we; wire litedramcore_phaseinjector2_csrfield_cas; wire litedramcore_phaseinjector2_csrfield_ras; wire litedramcore_phaseinjector2_csrfield_wren; wire litedramcore_phaseinjector2_csrfield_rden; reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; reg litedramcore_phaseinjector2_command_re = 1'd0; reg litedramcore_phaseinjector2_command_issue_re = 1'd0; wire litedramcore_phaseinjector2_command_issue_r; reg litedramcore_phaseinjector2_command_issue_we = 1'd0; reg litedramcore_phaseinjector2_command_issue_w = 1'd0; reg [15:0] litedramcore_phaseinjector2_address_storage = 16'd0; reg litedramcore_phaseinjector2_address_re = 1'd0; reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; reg litedramcore_phaseinjector2_baddress_re = 1'd0; reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; reg litedramcore_phaseinjector2_wrdata_re = 1'd0; reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; wire litedramcore_phaseinjector2_rddata_we; reg litedramcore_phaseinjector2_rddata_re = 1'd0; wire litedramcore_phaseinjector3_csrfield_cs; wire litedramcore_phaseinjector3_csrfield_we; wire litedramcore_phaseinjector3_csrfield_cas; wire litedramcore_phaseinjector3_csrfield_ras; wire litedramcore_phaseinjector3_csrfield_wren; wire litedramcore_phaseinjector3_csrfield_rden; reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; reg litedramcore_phaseinjector3_command_re = 1'd0; reg litedramcore_phaseinjector3_command_issue_re = 1'd0; wire litedramcore_phaseinjector3_command_issue_r; reg litedramcore_phaseinjector3_command_issue_we = 1'd0; reg litedramcore_phaseinjector3_command_issue_w = 1'd0; reg [15:0] litedramcore_phaseinjector3_address_storage = 16'd0; reg litedramcore_phaseinjector3_address_re = 1'd0; reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; reg litedramcore_phaseinjector3_baddress_re = 1'd0; reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; reg litedramcore_phaseinjector3_wrdata_re = 1'd0; reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; wire litedramcore_phaseinjector3_rddata_we; reg litedramcore_phaseinjector3_rddata_re = 1'd0; wire litedramcore_interface_bank0_valid; wire litedramcore_interface_bank0_ready; wire litedramcore_interface_bank0_we; wire [22:0] litedramcore_interface_bank0_addr; wire litedramcore_interface_bank0_lock; wire litedramcore_interface_bank0_wdata_ready; wire litedramcore_interface_bank0_rdata_valid; wire litedramcore_interface_bank1_valid; wire litedramcore_interface_bank1_ready; wire litedramcore_interface_bank1_we; wire [22:0] litedramcore_interface_bank1_addr; wire litedramcore_interface_bank1_lock; wire litedramcore_interface_bank1_wdata_ready; wire litedramcore_interface_bank1_rdata_valid; wire litedramcore_interface_bank2_valid; wire litedramcore_interface_bank2_ready; wire litedramcore_interface_bank2_we; wire [22:0] litedramcore_interface_bank2_addr; wire litedramcore_interface_bank2_lock; wire litedramcore_interface_bank2_wdata_ready; wire litedramcore_interface_bank2_rdata_valid; wire litedramcore_interface_bank3_valid; wire litedramcore_interface_bank3_ready; wire litedramcore_interface_bank3_we; wire [22:0] litedramcore_interface_bank3_addr; wire litedramcore_interface_bank3_lock; wire litedramcore_interface_bank3_wdata_ready; wire litedramcore_interface_bank3_rdata_valid; wire litedramcore_interface_bank4_valid; wire litedramcore_interface_bank4_ready; wire litedramcore_interface_bank4_we; wire [22:0] litedramcore_interface_bank4_addr; wire litedramcore_interface_bank4_lock; wire litedramcore_interface_bank4_wdata_ready; wire litedramcore_interface_bank4_rdata_valid; wire litedramcore_interface_bank5_valid; wire litedramcore_interface_bank5_ready; wire litedramcore_interface_bank5_we; wire [22:0] litedramcore_interface_bank5_addr; wire litedramcore_interface_bank5_lock; wire litedramcore_interface_bank5_wdata_ready; wire litedramcore_interface_bank5_rdata_valid; wire litedramcore_interface_bank6_valid; wire litedramcore_interface_bank6_ready; wire litedramcore_interface_bank6_we; wire [22:0] litedramcore_interface_bank6_addr; wire litedramcore_interface_bank6_lock; wire litedramcore_interface_bank6_wdata_ready; wire litedramcore_interface_bank6_rdata_valid; wire litedramcore_interface_bank7_valid; wire litedramcore_interface_bank7_ready; wire litedramcore_interface_bank7_we; wire [22:0] litedramcore_interface_bank7_addr; wire litedramcore_interface_bank7_lock; wire litedramcore_interface_bank7_wdata_ready; wire litedramcore_interface_bank7_rdata_valid; reg [127:0] litedramcore_interface_wdata = 128'd0; reg [15:0] litedramcore_interface_wdata_we = 16'd0; wire [127:0] litedramcore_interface_rdata; reg [15:0] litedramcore_dfi_p0_address = 16'd0; reg [2:0] litedramcore_dfi_p0_bank = 3'd0; reg litedramcore_dfi_p0_cas_n = 1'd1; reg litedramcore_dfi_p0_cs_n = 1'd1; reg litedramcore_dfi_p0_ras_n = 1'd1; reg litedramcore_dfi_p0_we_n = 1'd1; wire litedramcore_dfi_p0_cke; wire litedramcore_dfi_p0_odt; wire litedramcore_dfi_p0_reset_n; reg litedramcore_dfi_p0_act_n = 1'd1; wire [31:0] litedramcore_dfi_p0_wrdata; reg litedramcore_dfi_p0_wrdata_en = 1'd0; wire [3:0] litedramcore_dfi_p0_wrdata_mask; reg litedramcore_dfi_p0_rddata_en = 1'd0; wire [31:0] litedramcore_dfi_p0_rddata; wire litedramcore_dfi_p0_rddata_valid; reg [15:0] litedramcore_dfi_p1_address = 16'd0; reg [2:0] litedramcore_dfi_p1_bank = 3'd0; reg litedramcore_dfi_p1_cas_n = 1'd1; reg litedramcore_dfi_p1_cs_n = 1'd1; reg litedramcore_dfi_p1_ras_n = 1'd1; reg litedramcore_dfi_p1_we_n = 1'd1; wire litedramcore_dfi_p1_cke; wire litedramcore_dfi_p1_odt; wire litedramcore_dfi_p1_reset_n; reg litedramcore_dfi_p1_act_n = 1'd1; wire [31:0] litedramcore_dfi_p1_wrdata; reg litedramcore_dfi_p1_wrdata_en = 1'd0; wire [3:0] litedramcore_dfi_p1_wrdata_mask; reg litedramcore_dfi_p1_rddata_en = 1'd0; wire [31:0] litedramcore_dfi_p1_rddata; wire litedramcore_dfi_p1_rddata_valid; reg [15:0] litedramcore_dfi_p2_address = 16'd0; reg [2:0] litedramcore_dfi_p2_bank = 3'd0; reg litedramcore_dfi_p2_cas_n = 1'd1; reg litedramcore_dfi_p2_cs_n = 1'd1; reg litedramcore_dfi_p2_ras_n = 1'd1; reg litedramcore_dfi_p2_we_n = 1'd1; wire litedramcore_dfi_p2_cke; wire litedramcore_dfi_p2_odt; wire litedramcore_dfi_p2_reset_n; reg litedramcore_dfi_p2_act_n = 1'd1; wire [31:0] litedramcore_dfi_p2_wrdata; reg litedramcore_dfi_p2_wrdata_en = 1'd0; wire [3:0] litedramcore_dfi_p2_wrdata_mask; reg litedramcore_dfi_p2_rddata_en = 1'd0; wire [31:0] litedramcore_dfi_p2_rddata; wire litedramcore_dfi_p2_rddata_valid; reg [15:0] litedramcore_dfi_p3_address = 16'd0; reg [2:0] litedramcore_dfi_p3_bank = 3'd0; reg litedramcore_dfi_p3_cas_n = 1'd1; reg litedramcore_dfi_p3_cs_n = 1'd1; reg litedramcore_dfi_p3_ras_n = 1'd1; reg litedramcore_dfi_p3_we_n = 1'd1; wire litedramcore_dfi_p3_cke; wire litedramcore_dfi_p3_odt; wire litedramcore_dfi_p3_reset_n; reg litedramcore_dfi_p3_act_n = 1'd1; wire [31:0] litedramcore_dfi_p3_wrdata; reg litedramcore_dfi_p3_wrdata_en = 1'd0; wire [3:0] litedramcore_dfi_p3_wrdata_mask; reg litedramcore_dfi_p3_rddata_en = 1'd0; wire [31:0] litedramcore_dfi_p3_rddata; wire litedramcore_dfi_p3_rddata_valid; reg litedramcore_cmd_valid = 1'd0; reg litedramcore_cmd_ready = 1'd0; reg litedramcore_cmd_last = 1'd0; reg [15:0] litedramcore_cmd_payload_a = 16'd0; reg [2:0] litedramcore_cmd_payload_ba = 3'd0; reg litedramcore_cmd_payload_cas = 1'd0; reg litedramcore_cmd_payload_ras = 1'd0; reg litedramcore_cmd_payload_we = 1'd0; reg litedramcore_cmd_payload_is_read = 1'd0; reg litedramcore_cmd_payload_is_write = 1'd0; wire litedramcore_wants_refresh; wire litedramcore_wants_zqcs; wire litedramcore_timer_wait; wire litedramcore_timer_done0; wire [9:0] litedramcore_timer_count0; wire litedramcore_timer_done1; reg [9:0] litedramcore_timer_count1 = 10'd781; wire litedramcore_postponer_req_i; reg litedramcore_postponer_req_o = 1'd0; reg litedramcore_postponer_count = 1'd0; reg litedramcore_sequencer_start0 = 1'd0; wire litedramcore_sequencer_done0; wire litedramcore_sequencer_start1; reg litedramcore_sequencer_done1 = 1'd0; reg [6:0] litedramcore_sequencer_counter = 7'd0; reg litedramcore_sequencer_count = 1'd0; wire litedramcore_zqcs_timer_wait; wire litedramcore_zqcs_timer_done0; wire [26:0] litedramcore_zqcs_timer_count0; wire litedramcore_zqcs_timer_done1; reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; reg litedramcore_zqcs_executer_start = 1'd0; reg litedramcore_zqcs_executer_done = 1'd0; reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; wire litedramcore_bankmachine0_req_valid; wire litedramcore_bankmachine0_req_ready; wire litedramcore_bankmachine0_req_we; wire [22:0] litedramcore_bankmachine0_req_addr; wire litedramcore_bankmachine0_req_lock; reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; wire litedramcore_bankmachine0_refresh_req; reg litedramcore_bankmachine0_refresh_gnt = 1'd0; reg litedramcore_bankmachine0_cmd_valid = 1'd0; reg litedramcore_bankmachine0_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine0_auto_precharge = 1'd0; wire litedramcore_bankmachine0_sink_valid; wire litedramcore_bankmachine0_sink_ready; reg litedramcore_bankmachine0_sink_first = 1'd0; reg litedramcore_bankmachine0_sink_last = 1'd0; wire litedramcore_bankmachine0_sink_payload_we; wire [22:0] litedramcore_bankmachine0_sink_payload_addr; wire litedramcore_bankmachine0_source_valid; wire litedramcore_bankmachine0_source_ready; wire litedramcore_bankmachine0_source_first; wire litedramcore_bankmachine0_source_last; wire litedramcore_bankmachine0_source_payload_we; wire [22:0] litedramcore_bankmachine0_source_payload_addr; wire litedramcore_bankmachine0_syncfifo0_we; wire litedramcore_bankmachine0_syncfifo0_writable; wire litedramcore_bankmachine0_syncfifo0_re; wire litedramcore_bankmachine0_syncfifo0_readable; wire [25:0] litedramcore_bankmachine0_syncfifo0_din; wire [25:0] litedramcore_bankmachine0_syncfifo0_dout; reg [4:0] litedramcore_bankmachine0_level = 5'd0; reg litedramcore_bankmachine0_replace = 1'd0; reg [3:0] litedramcore_bankmachine0_produce = 4'd0; reg [3:0] litedramcore_bankmachine0_consume = 4'd0; reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine0_wrport_dat_r; wire litedramcore_bankmachine0_wrport_we; wire [25:0] litedramcore_bankmachine0_wrport_dat_w; wire litedramcore_bankmachine0_do_read; wire [3:0] litedramcore_bankmachine0_rdport_adr; wire [25:0] litedramcore_bankmachine0_rdport_dat_r; wire litedramcore_bankmachine0_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine0_fifo_in_payload_addr; wire litedramcore_bankmachine0_fifo_in_first; wire litedramcore_bankmachine0_fifo_in_last; wire litedramcore_bankmachine0_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine0_fifo_out_payload_addr; wire litedramcore_bankmachine0_fifo_out_first; wire litedramcore_bankmachine0_fifo_out_last; wire litedramcore_bankmachine0_sink_sink_valid; wire litedramcore_bankmachine0_sink_sink_ready; wire litedramcore_bankmachine0_sink_sink_first; wire litedramcore_bankmachine0_sink_sink_last; wire litedramcore_bankmachine0_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine0_sink_sink_payload_addr; wire litedramcore_bankmachine0_source_source_valid; wire litedramcore_bankmachine0_source_source_ready; wire litedramcore_bankmachine0_source_source_first; wire litedramcore_bankmachine0_source_source_last; wire litedramcore_bankmachine0_source_source_payload_we; wire [22:0] litedramcore_bankmachine0_source_source_payload_addr; wire litedramcore_bankmachine0_pipe_valid_sink_valid; wire litedramcore_bankmachine0_pipe_valid_sink_ready; wire litedramcore_bankmachine0_pipe_valid_sink_first; wire litedramcore_bankmachine0_pipe_valid_sink_last; wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine0_pipe_valid_source_ready; reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine0_row = 16'd0; reg litedramcore_bankmachine0_row_opened = 1'd0; wire litedramcore_bankmachine0_row_hit; reg litedramcore_bankmachine0_row_open = 1'd0; reg litedramcore_bankmachine0_row_close = 1'd0; reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine0_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; wire litedramcore_bankmachine0_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; wire litedramcore_bankmachine0_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; wire litedramcore_bankmachine1_req_valid; wire litedramcore_bankmachine1_req_ready; wire litedramcore_bankmachine1_req_we; wire [22:0] litedramcore_bankmachine1_req_addr; wire litedramcore_bankmachine1_req_lock; reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; wire litedramcore_bankmachine1_refresh_req; reg litedramcore_bankmachine1_refresh_gnt = 1'd0; reg litedramcore_bankmachine1_cmd_valid = 1'd0; reg litedramcore_bankmachine1_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine1_auto_precharge = 1'd0; wire litedramcore_bankmachine1_sink_valid; wire litedramcore_bankmachine1_sink_ready; reg litedramcore_bankmachine1_sink_first = 1'd0; reg litedramcore_bankmachine1_sink_last = 1'd0; wire litedramcore_bankmachine1_sink_payload_we; wire [22:0] litedramcore_bankmachine1_sink_payload_addr; wire litedramcore_bankmachine1_source_valid; wire litedramcore_bankmachine1_source_ready; wire litedramcore_bankmachine1_source_first; wire litedramcore_bankmachine1_source_last; wire litedramcore_bankmachine1_source_payload_we; wire [22:0] litedramcore_bankmachine1_source_payload_addr; wire litedramcore_bankmachine1_syncfifo1_we; wire litedramcore_bankmachine1_syncfifo1_writable; wire litedramcore_bankmachine1_syncfifo1_re; wire litedramcore_bankmachine1_syncfifo1_readable; wire [25:0] litedramcore_bankmachine1_syncfifo1_din; wire [25:0] litedramcore_bankmachine1_syncfifo1_dout; reg [4:0] litedramcore_bankmachine1_level = 5'd0; reg litedramcore_bankmachine1_replace = 1'd0; reg [3:0] litedramcore_bankmachine1_produce = 4'd0; reg [3:0] litedramcore_bankmachine1_consume = 4'd0; reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine1_wrport_dat_r; wire litedramcore_bankmachine1_wrport_we; wire [25:0] litedramcore_bankmachine1_wrport_dat_w; wire litedramcore_bankmachine1_do_read; wire [3:0] litedramcore_bankmachine1_rdport_adr; wire [25:0] litedramcore_bankmachine1_rdport_dat_r; wire litedramcore_bankmachine1_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine1_fifo_in_payload_addr; wire litedramcore_bankmachine1_fifo_in_first; wire litedramcore_bankmachine1_fifo_in_last; wire litedramcore_bankmachine1_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine1_fifo_out_payload_addr; wire litedramcore_bankmachine1_fifo_out_first; wire litedramcore_bankmachine1_fifo_out_last; wire litedramcore_bankmachine1_sink_sink_valid; wire litedramcore_bankmachine1_sink_sink_ready; wire litedramcore_bankmachine1_sink_sink_first; wire litedramcore_bankmachine1_sink_sink_last; wire litedramcore_bankmachine1_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine1_sink_sink_payload_addr; wire litedramcore_bankmachine1_source_source_valid; wire litedramcore_bankmachine1_source_source_ready; wire litedramcore_bankmachine1_source_source_first; wire litedramcore_bankmachine1_source_source_last; wire litedramcore_bankmachine1_source_source_payload_we; wire [22:0] litedramcore_bankmachine1_source_source_payload_addr; wire litedramcore_bankmachine1_pipe_valid_sink_valid; wire litedramcore_bankmachine1_pipe_valid_sink_ready; wire litedramcore_bankmachine1_pipe_valid_sink_first; wire litedramcore_bankmachine1_pipe_valid_sink_last; wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine1_pipe_valid_source_ready; reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine1_row = 16'd0; reg litedramcore_bankmachine1_row_opened = 1'd0; wire litedramcore_bankmachine1_row_hit; reg litedramcore_bankmachine1_row_open = 1'd0; reg litedramcore_bankmachine1_row_close = 1'd0; reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine1_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; wire litedramcore_bankmachine1_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; wire litedramcore_bankmachine1_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; wire litedramcore_bankmachine2_req_valid; wire litedramcore_bankmachine2_req_ready; wire litedramcore_bankmachine2_req_we; wire [22:0] litedramcore_bankmachine2_req_addr; wire litedramcore_bankmachine2_req_lock; reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; wire litedramcore_bankmachine2_refresh_req; reg litedramcore_bankmachine2_refresh_gnt = 1'd0; reg litedramcore_bankmachine2_cmd_valid = 1'd0; reg litedramcore_bankmachine2_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine2_auto_precharge = 1'd0; wire litedramcore_bankmachine2_sink_valid; wire litedramcore_bankmachine2_sink_ready; reg litedramcore_bankmachine2_sink_first = 1'd0; reg litedramcore_bankmachine2_sink_last = 1'd0; wire litedramcore_bankmachine2_sink_payload_we; wire [22:0] litedramcore_bankmachine2_sink_payload_addr; wire litedramcore_bankmachine2_source_valid; wire litedramcore_bankmachine2_source_ready; wire litedramcore_bankmachine2_source_first; wire litedramcore_bankmachine2_source_last; wire litedramcore_bankmachine2_source_payload_we; wire [22:0] litedramcore_bankmachine2_source_payload_addr; wire litedramcore_bankmachine2_syncfifo2_we; wire litedramcore_bankmachine2_syncfifo2_writable; wire litedramcore_bankmachine2_syncfifo2_re; wire litedramcore_bankmachine2_syncfifo2_readable; wire [25:0] litedramcore_bankmachine2_syncfifo2_din; wire [25:0] litedramcore_bankmachine2_syncfifo2_dout; reg [4:0] litedramcore_bankmachine2_level = 5'd0; reg litedramcore_bankmachine2_replace = 1'd0; reg [3:0] litedramcore_bankmachine2_produce = 4'd0; reg [3:0] litedramcore_bankmachine2_consume = 4'd0; reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine2_wrport_dat_r; wire litedramcore_bankmachine2_wrport_we; wire [25:0] litedramcore_bankmachine2_wrport_dat_w; wire litedramcore_bankmachine2_do_read; wire [3:0] litedramcore_bankmachine2_rdport_adr; wire [25:0] litedramcore_bankmachine2_rdport_dat_r; wire litedramcore_bankmachine2_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine2_fifo_in_payload_addr; wire litedramcore_bankmachine2_fifo_in_first; wire litedramcore_bankmachine2_fifo_in_last; wire litedramcore_bankmachine2_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine2_fifo_out_payload_addr; wire litedramcore_bankmachine2_fifo_out_first; wire litedramcore_bankmachine2_fifo_out_last; wire litedramcore_bankmachine2_sink_sink_valid; wire litedramcore_bankmachine2_sink_sink_ready; wire litedramcore_bankmachine2_sink_sink_first; wire litedramcore_bankmachine2_sink_sink_last; wire litedramcore_bankmachine2_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine2_sink_sink_payload_addr; wire litedramcore_bankmachine2_source_source_valid; wire litedramcore_bankmachine2_source_source_ready; wire litedramcore_bankmachine2_source_source_first; wire litedramcore_bankmachine2_source_source_last; wire litedramcore_bankmachine2_source_source_payload_we; wire [22:0] litedramcore_bankmachine2_source_source_payload_addr; wire litedramcore_bankmachine2_pipe_valid_sink_valid; wire litedramcore_bankmachine2_pipe_valid_sink_ready; wire litedramcore_bankmachine2_pipe_valid_sink_first; wire litedramcore_bankmachine2_pipe_valid_sink_last; wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine2_pipe_valid_source_ready; reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine2_row = 16'd0; reg litedramcore_bankmachine2_row_opened = 1'd0; wire litedramcore_bankmachine2_row_hit; reg litedramcore_bankmachine2_row_open = 1'd0; reg litedramcore_bankmachine2_row_close = 1'd0; reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine2_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; wire litedramcore_bankmachine2_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; wire litedramcore_bankmachine2_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; wire litedramcore_bankmachine3_req_valid; wire litedramcore_bankmachine3_req_ready; wire litedramcore_bankmachine3_req_we; wire [22:0] litedramcore_bankmachine3_req_addr; wire litedramcore_bankmachine3_req_lock; reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; wire litedramcore_bankmachine3_refresh_req; reg litedramcore_bankmachine3_refresh_gnt = 1'd0; reg litedramcore_bankmachine3_cmd_valid = 1'd0; reg litedramcore_bankmachine3_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine3_auto_precharge = 1'd0; wire litedramcore_bankmachine3_sink_valid; wire litedramcore_bankmachine3_sink_ready; reg litedramcore_bankmachine3_sink_first = 1'd0; reg litedramcore_bankmachine3_sink_last = 1'd0; wire litedramcore_bankmachine3_sink_payload_we; wire [22:0] litedramcore_bankmachine3_sink_payload_addr; wire litedramcore_bankmachine3_source_valid; wire litedramcore_bankmachine3_source_ready; wire litedramcore_bankmachine3_source_first; wire litedramcore_bankmachine3_source_last; wire litedramcore_bankmachine3_source_payload_we; wire [22:0] litedramcore_bankmachine3_source_payload_addr; wire litedramcore_bankmachine3_syncfifo3_we; wire litedramcore_bankmachine3_syncfifo3_writable; wire litedramcore_bankmachine3_syncfifo3_re; wire litedramcore_bankmachine3_syncfifo3_readable; wire [25:0] litedramcore_bankmachine3_syncfifo3_din; wire [25:0] litedramcore_bankmachine3_syncfifo3_dout; reg [4:0] litedramcore_bankmachine3_level = 5'd0; reg litedramcore_bankmachine3_replace = 1'd0; reg [3:0] litedramcore_bankmachine3_produce = 4'd0; reg [3:0] litedramcore_bankmachine3_consume = 4'd0; reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine3_wrport_dat_r; wire litedramcore_bankmachine3_wrport_we; wire [25:0] litedramcore_bankmachine3_wrport_dat_w; wire litedramcore_bankmachine3_do_read; wire [3:0] litedramcore_bankmachine3_rdport_adr; wire [25:0] litedramcore_bankmachine3_rdport_dat_r; wire litedramcore_bankmachine3_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine3_fifo_in_payload_addr; wire litedramcore_bankmachine3_fifo_in_first; wire litedramcore_bankmachine3_fifo_in_last; wire litedramcore_bankmachine3_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine3_fifo_out_payload_addr; wire litedramcore_bankmachine3_fifo_out_first; wire litedramcore_bankmachine3_fifo_out_last; wire litedramcore_bankmachine3_sink_sink_valid; wire litedramcore_bankmachine3_sink_sink_ready; wire litedramcore_bankmachine3_sink_sink_first; wire litedramcore_bankmachine3_sink_sink_last; wire litedramcore_bankmachine3_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine3_sink_sink_payload_addr; wire litedramcore_bankmachine3_source_source_valid; wire litedramcore_bankmachine3_source_source_ready; wire litedramcore_bankmachine3_source_source_first; wire litedramcore_bankmachine3_source_source_last; wire litedramcore_bankmachine3_source_source_payload_we; wire [22:0] litedramcore_bankmachine3_source_source_payload_addr; wire litedramcore_bankmachine3_pipe_valid_sink_valid; wire litedramcore_bankmachine3_pipe_valid_sink_ready; wire litedramcore_bankmachine3_pipe_valid_sink_first; wire litedramcore_bankmachine3_pipe_valid_sink_last; wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine3_pipe_valid_source_ready; reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine3_row = 16'd0; reg litedramcore_bankmachine3_row_opened = 1'd0; wire litedramcore_bankmachine3_row_hit; reg litedramcore_bankmachine3_row_open = 1'd0; reg litedramcore_bankmachine3_row_close = 1'd0; reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine3_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; wire litedramcore_bankmachine3_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; wire litedramcore_bankmachine3_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; wire litedramcore_bankmachine4_req_valid; wire litedramcore_bankmachine4_req_ready; wire litedramcore_bankmachine4_req_we; wire [22:0] litedramcore_bankmachine4_req_addr; wire litedramcore_bankmachine4_req_lock; reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; wire litedramcore_bankmachine4_refresh_req; reg litedramcore_bankmachine4_refresh_gnt = 1'd0; reg litedramcore_bankmachine4_cmd_valid = 1'd0; reg litedramcore_bankmachine4_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine4_auto_precharge = 1'd0; wire litedramcore_bankmachine4_sink_valid; wire litedramcore_bankmachine4_sink_ready; reg litedramcore_bankmachine4_sink_first = 1'd0; reg litedramcore_bankmachine4_sink_last = 1'd0; wire litedramcore_bankmachine4_sink_payload_we; wire [22:0] litedramcore_bankmachine4_sink_payload_addr; wire litedramcore_bankmachine4_source_valid; wire litedramcore_bankmachine4_source_ready; wire litedramcore_bankmachine4_source_first; wire litedramcore_bankmachine4_source_last; wire litedramcore_bankmachine4_source_payload_we; wire [22:0] litedramcore_bankmachine4_source_payload_addr; wire litedramcore_bankmachine4_syncfifo4_we; wire litedramcore_bankmachine4_syncfifo4_writable; wire litedramcore_bankmachine4_syncfifo4_re; wire litedramcore_bankmachine4_syncfifo4_readable; wire [25:0] litedramcore_bankmachine4_syncfifo4_din; wire [25:0] litedramcore_bankmachine4_syncfifo4_dout; reg [4:0] litedramcore_bankmachine4_level = 5'd0; reg litedramcore_bankmachine4_replace = 1'd0; reg [3:0] litedramcore_bankmachine4_produce = 4'd0; reg [3:0] litedramcore_bankmachine4_consume = 4'd0; reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine4_wrport_dat_r; wire litedramcore_bankmachine4_wrport_we; wire [25:0] litedramcore_bankmachine4_wrport_dat_w; wire litedramcore_bankmachine4_do_read; wire [3:0] litedramcore_bankmachine4_rdport_adr; wire [25:0] litedramcore_bankmachine4_rdport_dat_r; wire litedramcore_bankmachine4_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine4_fifo_in_payload_addr; wire litedramcore_bankmachine4_fifo_in_first; wire litedramcore_bankmachine4_fifo_in_last; wire litedramcore_bankmachine4_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine4_fifo_out_payload_addr; wire litedramcore_bankmachine4_fifo_out_first; wire litedramcore_bankmachine4_fifo_out_last; wire litedramcore_bankmachine4_sink_sink_valid; wire litedramcore_bankmachine4_sink_sink_ready; wire litedramcore_bankmachine4_sink_sink_first; wire litedramcore_bankmachine4_sink_sink_last; wire litedramcore_bankmachine4_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine4_sink_sink_payload_addr; wire litedramcore_bankmachine4_source_source_valid; wire litedramcore_bankmachine4_source_source_ready; wire litedramcore_bankmachine4_source_source_first; wire litedramcore_bankmachine4_source_source_last; wire litedramcore_bankmachine4_source_source_payload_we; wire [22:0] litedramcore_bankmachine4_source_source_payload_addr; wire litedramcore_bankmachine4_pipe_valid_sink_valid; wire litedramcore_bankmachine4_pipe_valid_sink_ready; wire litedramcore_bankmachine4_pipe_valid_sink_first; wire litedramcore_bankmachine4_pipe_valid_sink_last; wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine4_pipe_valid_source_ready; reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine4_row = 16'd0; reg litedramcore_bankmachine4_row_opened = 1'd0; wire litedramcore_bankmachine4_row_hit; reg litedramcore_bankmachine4_row_open = 1'd0; reg litedramcore_bankmachine4_row_close = 1'd0; reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine4_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; wire litedramcore_bankmachine4_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; wire litedramcore_bankmachine4_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; wire litedramcore_bankmachine5_req_valid; wire litedramcore_bankmachine5_req_ready; wire litedramcore_bankmachine5_req_we; wire [22:0] litedramcore_bankmachine5_req_addr; wire litedramcore_bankmachine5_req_lock; reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; wire litedramcore_bankmachine5_refresh_req; reg litedramcore_bankmachine5_refresh_gnt = 1'd0; reg litedramcore_bankmachine5_cmd_valid = 1'd0; reg litedramcore_bankmachine5_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine5_auto_precharge = 1'd0; wire litedramcore_bankmachine5_sink_valid; wire litedramcore_bankmachine5_sink_ready; reg litedramcore_bankmachine5_sink_first = 1'd0; reg litedramcore_bankmachine5_sink_last = 1'd0; wire litedramcore_bankmachine5_sink_payload_we; wire [22:0] litedramcore_bankmachine5_sink_payload_addr; wire litedramcore_bankmachine5_source_valid; wire litedramcore_bankmachine5_source_ready; wire litedramcore_bankmachine5_source_first; wire litedramcore_bankmachine5_source_last; wire litedramcore_bankmachine5_source_payload_we; wire [22:0] litedramcore_bankmachine5_source_payload_addr; wire litedramcore_bankmachine5_syncfifo5_we; wire litedramcore_bankmachine5_syncfifo5_writable; wire litedramcore_bankmachine5_syncfifo5_re; wire litedramcore_bankmachine5_syncfifo5_readable; wire [25:0] litedramcore_bankmachine5_syncfifo5_din; wire [25:0] litedramcore_bankmachine5_syncfifo5_dout; reg [4:0] litedramcore_bankmachine5_level = 5'd0; reg litedramcore_bankmachine5_replace = 1'd0; reg [3:0] litedramcore_bankmachine5_produce = 4'd0; reg [3:0] litedramcore_bankmachine5_consume = 4'd0; reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine5_wrport_dat_r; wire litedramcore_bankmachine5_wrport_we; wire [25:0] litedramcore_bankmachine5_wrport_dat_w; wire litedramcore_bankmachine5_do_read; wire [3:0] litedramcore_bankmachine5_rdport_adr; wire [25:0] litedramcore_bankmachine5_rdport_dat_r; wire litedramcore_bankmachine5_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine5_fifo_in_payload_addr; wire litedramcore_bankmachine5_fifo_in_first; wire litedramcore_bankmachine5_fifo_in_last; wire litedramcore_bankmachine5_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine5_fifo_out_payload_addr; wire litedramcore_bankmachine5_fifo_out_first; wire litedramcore_bankmachine5_fifo_out_last; wire litedramcore_bankmachine5_sink_sink_valid; wire litedramcore_bankmachine5_sink_sink_ready; wire litedramcore_bankmachine5_sink_sink_first; wire litedramcore_bankmachine5_sink_sink_last; wire litedramcore_bankmachine5_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine5_sink_sink_payload_addr; wire litedramcore_bankmachine5_source_source_valid; wire litedramcore_bankmachine5_source_source_ready; wire litedramcore_bankmachine5_source_source_first; wire litedramcore_bankmachine5_source_source_last; wire litedramcore_bankmachine5_source_source_payload_we; wire [22:0] litedramcore_bankmachine5_source_source_payload_addr; wire litedramcore_bankmachine5_pipe_valid_sink_valid; wire litedramcore_bankmachine5_pipe_valid_sink_ready; wire litedramcore_bankmachine5_pipe_valid_sink_first; wire litedramcore_bankmachine5_pipe_valid_sink_last; wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine5_pipe_valid_source_ready; reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine5_row = 16'd0; reg litedramcore_bankmachine5_row_opened = 1'd0; wire litedramcore_bankmachine5_row_hit; reg litedramcore_bankmachine5_row_open = 1'd0; reg litedramcore_bankmachine5_row_close = 1'd0; reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine5_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; wire litedramcore_bankmachine5_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; wire litedramcore_bankmachine5_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; wire litedramcore_bankmachine6_req_valid; wire litedramcore_bankmachine6_req_ready; wire litedramcore_bankmachine6_req_we; wire [22:0] litedramcore_bankmachine6_req_addr; wire litedramcore_bankmachine6_req_lock; reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; wire litedramcore_bankmachine6_refresh_req; reg litedramcore_bankmachine6_refresh_gnt = 1'd0; reg litedramcore_bankmachine6_cmd_valid = 1'd0; reg litedramcore_bankmachine6_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine6_auto_precharge = 1'd0; wire litedramcore_bankmachine6_sink_valid; wire litedramcore_bankmachine6_sink_ready; reg litedramcore_bankmachine6_sink_first = 1'd0; reg litedramcore_bankmachine6_sink_last = 1'd0; wire litedramcore_bankmachine6_sink_payload_we; wire [22:0] litedramcore_bankmachine6_sink_payload_addr; wire litedramcore_bankmachine6_source_valid; wire litedramcore_bankmachine6_source_ready; wire litedramcore_bankmachine6_source_first; wire litedramcore_bankmachine6_source_last; wire litedramcore_bankmachine6_source_payload_we; wire [22:0] litedramcore_bankmachine6_source_payload_addr; wire litedramcore_bankmachine6_syncfifo6_we; wire litedramcore_bankmachine6_syncfifo6_writable; wire litedramcore_bankmachine6_syncfifo6_re; wire litedramcore_bankmachine6_syncfifo6_readable; wire [25:0] litedramcore_bankmachine6_syncfifo6_din; wire [25:0] litedramcore_bankmachine6_syncfifo6_dout; reg [4:0] litedramcore_bankmachine6_level = 5'd0; reg litedramcore_bankmachine6_replace = 1'd0; reg [3:0] litedramcore_bankmachine6_produce = 4'd0; reg [3:0] litedramcore_bankmachine6_consume = 4'd0; reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine6_wrport_dat_r; wire litedramcore_bankmachine6_wrport_we; wire [25:0] litedramcore_bankmachine6_wrport_dat_w; wire litedramcore_bankmachine6_do_read; wire [3:0] litedramcore_bankmachine6_rdport_adr; wire [25:0] litedramcore_bankmachine6_rdport_dat_r; wire litedramcore_bankmachine6_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine6_fifo_in_payload_addr; wire litedramcore_bankmachine6_fifo_in_first; wire litedramcore_bankmachine6_fifo_in_last; wire litedramcore_bankmachine6_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine6_fifo_out_payload_addr; wire litedramcore_bankmachine6_fifo_out_first; wire litedramcore_bankmachine6_fifo_out_last; wire litedramcore_bankmachine6_sink_sink_valid; wire litedramcore_bankmachine6_sink_sink_ready; wire litedramcore_bankmachine6_sink_sink_first; wire litedramcore_bankmachine6_sink_sink_last; wire litedramcore_bankmachine6_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine6_sink_sink_payload_addr; wire litedramcore_bankmachine6_source_source_valid; wire litedramcore_bankmachine6_source_source_ready; wire litedramcore_bankmachine6_source_source_first; wire litedramcore_bankmachine6_source_source_last; wire litedramcore_bankmachine6_source_source_payload_we; wire [22:0] litedramcore_bankmachine6_source_source_payload_addr; wire litedramcore_bankmachine6_pipe_valid_sink_valid; wire litedramcore_bankmachine6_pipe_valid_sink_ready; wire litedramcore_bankmachine6_pipe_valid_sink_first; wire litedramcore_bankmachine6_pipe_valid_sink_last; wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine6_pipe_valid_source_ready; reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine6_row = 16'd0; reg litedramcore_bankmachine6_row_opened = 1'd0; wire litedramcore_bankmachine6_row_hit; reg litedramcore_bankmachine6_row_open = 1'd0; reg litedramcore_bankmachine6_row_close = 1'd0; reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine6_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; wire litedramcore_bankmachine6_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; wire litedramcore_bankmachine6_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; wire litedramcore_bankmachine7_req_valid; wire litedramcore_bankmachine7_req_ready; wire litedramcore_bankmachine7_req_we; wire [22:0] litedramcore_bankmachine7_req_addr; wire litedramcore_bankmachine7_req_lock; reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; wire litedramcore_bankmachine7_refresh_req; reg litedramcore_bankmachine7_refresh_gnt = 1'd0; reg litedramcore_bankmachine7_cmd_valid = 1'd0; reg litedramcore_bankmachine7_cmd_ready = 1'd0; reg [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0; wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; reg litedramcore_bankmachine7_auto_precharge = 1'd0; wire litedramcore_bankmachine7_sink_valid; wire litedramcore_bankmachine7_sink_ready; reg litedramcore_bankmachine7_sink_first = 1'd0; reg litedramcore_bankmachine7_sink_last = 1'd0; wire litedramcore_bankmachine7_sink_payload_we; wire [22:0] litedramcore_bankmachine7_sink_payload_addr; wire litedramcore_bankmachine7_source_valid; wire litedramcore_bankmachine7_source_ready; wire litedramcore_bankmachine7_source_first; wire litedramcore_bankmachine7_source_last; wire litedramcore_bankmachine7_source_payload_we; wire [22:0] litedramcore_bankmachine7_source_payload_addr; wire litedramcore_bankmachine7_syncfifo7_we; wire litedramcore_bankmachine7_syncfifo7_writable; wire litedramcore_bankmachine7_syncfifo7_re; wire litedramcore_bankmachine7_syncfifo7_readable; wire [25:0] litedramcore_bankmachine7_syncfifo7_din; wire [25:0] litedramcore_bankmachine7_syncfifo7_dout; reg [4:0] litedramcore_bankmachine7_level = 5'd0; reg litedramcore_bankmachine7_replace = 1'd0; reg [3:0] litedramcore_bankmachine7_produce = 4'd0; reg [3:0] litedramcore_bankmachine7_consume = 4'd0; reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; wire [25:0] litedramcore_bankmachine7_wrport_dat_r; wire litedramcore_bankmachine7_wrport_we; wire [25:0] litedramcore_bankmachine7_wrport_dat_w; wire litedramcore_bankmachine7_do_read; wire [3:0] litedramcore_bankmachine7_rdport_adr; wire [25:0] litedramcore_bankmachine7_rdport_dat_r; wire litedramcore_bankmachine7_fifo_in_payload_we; wire [22:0] litedramcore_bankmachine7_fifo_in_payload_addr; wire litedramcore_bankmachine7_fifo_in_first; wire litedramcore_bankmachine7_fifo_in_last; wire litedramcore_bankmachine7_fifo_out_payload_we; wire [22:0] litedramcore_bankmachine7_fifo_out_payload_addr; wire litedramcore_bankmachine7_fifo_out_first; wire litedramcore_bankmachine7_fifo_out_last; wire litedramcore_bankmachine7_sink_sink_valid; wire litedramcore_bankmachine7_sink_sink_ready; wire litedramcore_bankmachine7_sink_sink_first; wire litedramcore_bankmachine7_sink_sink_last; wire litedramcore_bankmachine7_sink_sink_payload_we; wire [22:0] litedramcore_bankmachine7_sink_sink_payload_addr; wire litedramcore_bankmachine7_source_source_valid; wire litedramcore_bankmachine7_source_source_ready; wire litedramcore_bankmachine7_source_source_first; wire litedramcore_bankmachine7_source_source_last; wire litedramcore_bankmachine7_source_source_payload_we; wire [22:0] litedramcore_bankmachine7_source_source_payload_addr; wire litedramcore_bankmachine7_pipe_valid_sink_valid; wire litedramcore_bankmachine7_pipe_valid_sink_ready; wire litedramcore_bankmachine7_pipe_valid_sink_first; wire litedramcore_bankmachine7_pipe_valid_sink_last; wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; wire [22:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; wire litedramcore_bankmachine7_pipe_valid_source_ready; reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; reg [22:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0; reg [15:0] litedramcore_bankmachine7_row = 16'd0; reg litedramcore_bankmachine7_row_opened = 1'd0; wire litedramcore_bankmachine7_row_hit; reg litedramcore_bankmachine7_row_open = 1'd0; reg litedramcore_bankmachine7_row_close = 1'd0; reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; wire litedramcore_bankmachine7_twtpcon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; wire litedramcore_bankmachine7_trccon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; wire litedramcore_bankmachine7_trascon_valid; (* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; wire litedramcore_ras_allowed; wire litedramcore_cas_allowed; wire [1:0] litedramcore_rdcmdphase; wire [1:0] litedramcore_wrcmdphase; reg litedramcore_choose_cmd_want_reads = 1'd0; reg litedramcore_choose_cmd_want_writes = 1'd0; reg litedramcore_choose_cmd_want_cmds = 1'd0; reg litedramcore_choose_cmd_want_activates = 1'd0; wire litedramcore_choose_cmd_cmd_valid; reg litedramcore_choose_cmd_cmd_ready = 1'd0; wire [15:0] litedramcore_choose_cmd_cmd_payload_a; wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; wire litedramcore_choose_cmd_cmd_payload_is_cmd; wire litedramcore_choose_cmd_cmd_payload_is_read; wire litedramcore_choose_cmd_cmd_payload_is_write; reg [7:0] litedramcore_choose_cmd_valids = 8'd0; wire [7:0] litedramcore_choose_cmd_request; reg [2:0] litedramcore_choose_cmd_grant = 3'd0; wire litedramcore_choose_cmd_ce; reg litedramcore_choose_req_want_reads = 1'd0; reg litedramcore_choose_req_want_writes = 1'd0; reg litedramcore_choose_req_want_cmds = 1'd0; reg litedramcore_choose_req_want_activates = 1'd0; wire litedramcore_choose_req_cmd_valid; reg litedramcore_choose_req_cmd_ready = 1'd0; wire [15:0] litedramcore_choose_req_cmd_payload_a; wire [2:0] litedramcore_choose_req_cmd_payload_ba; reg litedramcore_choose_req_cmd_payload_cas = 1'd0; reg litedramcore_choose_req_cmd_payload_ras = 1'd0; reg litedramcore_choose_req_cmd_payload_we = 1'd0; wire litedramcore_choose_req_cmd_payload_is_cmd; wire litedramcore_choose_req_cmd_payload_is_read; wire litedramcore_choose_req_cmd_payload_is_write; reg [7:0] litedramcore_choose_req_valids = 8'd0; wire [7:0] litedramcore_choose_req_request; reg [2:0] litedramcore_choose_req_grant = 3'd0; wire litedramcore_choose_req_ce; reg [15:0] litedramcore_nop_a = 16'd0; reg [2:0] litedramcore_nop_ba = 3'd0; reg [1:0] litedramcore_steerer_sel0 = 2'd0; reg [1:0] litedramcore_steerer_sel1 = 2'd0; reg [1:0] litedramcore_steerer_sel2 = 2'd0; reg [1:0] litedramcore_steerer_sel3 = 2'd0; reg litedramcore_steerer0 = 1'd1; reg litedramcore_steerer1 = 1'd1; reg litedramcore_steerer2 = 1'd1; reg litedramcore_steerer3 = 1'd1; reg litedramcore_steerer4 = 1'd1; reg litedramcore_steerer5 = 1'd1; reg litedramcore_steerer6 = 1'd1; reg litedramcore_steerer7 = 1'd1; wire litedramcore_trrdcon_valid; (* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0; reg litedramcore_trrdcon_count = 1'd0; wire litedramcore_tfawcon_valid; (* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; wire [2:0] litedramcore_tfawcon_count; reg [4:0] litedramcore_tfawcon_window = 5'd0; wire litedramcore_tccdcon_valid; (* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0; reg litedramcore_tccdcon_count = 1'd0; wire litedramcore_twtrcon_valid; (* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0; reg [2:0] litedramcore_twtrcon_count = 3'd0; wire litedramcore_read_available; wire litedramcore_write_available; reg litedramcore_en0 = 1'd0; wire litedramcore_max_time0; reg [4:0] litedramcore_time0 = 5'd0; reg litedramcore_en1 = 1'd0; wire litedramcore_max_time1; reg [3:0] litedramcore_time1 = 4'd0; wire litedramcore_go_to_refresh; reg init_done_storage = 1'd0; reg init_done_re = 1'd0; reg init_error_storage = 1'd0; reg init_error_re = 1'd0; wire [29:0] wb_bus_adr; wire [31:0] wb_bus_dat_w; wire [31:0] wb_bus_dat_r; wire [3:0] wb_bus_sel; wire wb_bus_cyc; wire wb_bus_stb; wire wb_bus_ack; wire wb_bus_we; wire [2:0] wb_bus_cti; wire [1:0] wb_bus_bte; wire wb_bus_err; wire user_enable; wire user_port_cmd_valid; wire user_port_cmd_ready; wire user_port_cmd_payload_we; wire [25:0] user_port_cmd_payload_addr; wire user_port_wdata_valid; wire user_port_wdata_ready; wire [127:0] user_port_wdata_payload_data; wire [15:0] user_port_wdata_payload_we; wire user_port_rdata_valid; wire user_port_rdata_ready; wire [127:0] user_port_rdata_payload_data; reg [13:0] litedramcore_adr = 14'd0; reg litedramcore_we = 1'd0; reg [31:0] litedramcore_dat_w = 32'd0; wire [31:0] litedramcore_dat_r; wire [29:0] litedramcore_wishbone_adr; wire [31:0] litedramcore_wishbone_dat_w; reg [31:0] litedramcore_wishbone_dat_r = 32'd0; wire [3:0] litedramcore_wishbone_sel; wire litedramcore_wishbone_cyc; wire litedramcore_wishbone_stb; reg litedramcore_wishbone_ack = 1'd0; wire litedramcore_wishbone_we; wire [2:0] litedramcore_wishbone_cti; wire [1:0] litedramcore_wishbone_bte; reg litedramcore_wishbone_err = 1'd0; wire [13:0] interface0_bank_bus_adr; wire interface0_bank_bus_we; wire [31:0] interface0_bank_bus_dat_w; reg [31:0] interface0_bank_bus_dat_r = 32'd0; reg csrbank0_init_done0_re = 1'd0; wire csrbank0_init_done0_r; reg csrbank0_init_done0_we = 1'd0; wire csrbank0_init_done0_w; reg csrbank0_init_error0_re = 1'd0; wire csrbank0_init_error0_r; reg csrbank0_init_error0_we = 1'd0; wire csrbank0_init_error0_w; wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; wire [31:0] interface1_bank_bus_dat_w; reg [31:0] interface1_bank_bus_dat_r = 32'd0; reg csrbank1_rst0_re = 1'd0; wire csrbank1_rst0_r; reg csrbank1_rst0_we = 1'd0; wire csrbank1_rst0_w; reg csrbank1_dly_sel0_re = 1'd0; wire [1:0] csrbank1_dly_sel0_r; reg csrbank1_dly_sel0_we = 1'd0; wire [1:0] csrbank1_dly_sel0_w; reg csrbank1_half_sys8x_taps0_re = 1'd0; wire [4:0] csrbank1_half_sys8x_taps0_r; reg csrbank1_half_sys8x_taps0_we = 1'd0; wire [4:0] csrbank1_half_sys8x_taps0_w; reg csrbank1_wlevel_en0_re = 1'd0; wire csrbank1_wlevel_en0_r; reg csrbank1_wlevel_en0_we = 1'd0; wire csrbank1_wlevel_en0_w; reg csrbank1_rdphase0_re = 1'd0; wire [1:0] csrbank1_rdphase0_r; reg csrbank1_rdphase0_we = 1'd0; wire [1:0] csrbank1_rdphase0_w; reg csrbank1_wrphase0_re = 1'd0; wire [1:0] csrbank1_wrphase0_r; reg csrbank1_wrphase0_we = 1'd0; wire [1:0] csrbank1_wrphase0_w; wire csrbank1_sel; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; wire [31:0] interface2_bank_bus_dat_w; reg [31:0] interface2_bank_bus_dat_r = 32'd0; reg csrbank2_dfii_control0_re = 1'd0; wire [3:0] csrbank2_dfii_control0_r; reg csrbank2_dfii_control0_we = 1'd0; wire [3:0] csrbank2_dfii_control0_w; reg csrbank2_dfii_pi0_command0_re = 1'd0; wire [5:0] csrbank2_dfii_pi0_command0_r; reg csrbank2_dfii_pi0_command0_we = 1'd0; wire [5:0] csrbank2_dfii_pi0_command0_w; reg csrbank2_dfii_pi0_address0_re = 1'd0; wire [15:0] csrbank2_dfii_pi0_address0_r; reg csrbank2_dfii_pi0_address0_we = 1'd0; wire [15:0] csrbank2_dfii_pi0_address0_w; reg csrbank2_dfii_pi0_baddress0_re = 1'd0; wire [2:0] csrbank2_dfii_pi0_baddress0_r; reg csrbank2_dfii_pi0_baddress0_we = 1'd0; wire [2:0] csrbank2_dfii_pi0_baddress0_w; reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; wire [31:0] csrbank2_dfii_pi0_wrdata0_r; reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; wire [31:0] csrbank2_dfii_pi0_wrdata0_w; reg csrbank2_dfii_pi0_rddata_re = 1'd0; wire [31:0] csrbank2_dfii_pi0_rddata_r; reg csrbank2_dfii_pi0_rddata_we = 1'd0; wire [31:0] csrbank2_dfii_pi0_rddata_w; reg csrbank2_dfii_pi1_command0_re = 1'd0; wire [5:0] csrbank2_dfii_pi1_command0_r; reg csrbank2_dfii_pi1_command0_we = 1'd0; wire [5:0] csrbank2_dfii_pi1_command0_w; reg csrbank2_dfii_pi1_address0_re = 1'd0; wire [15:0] csrbank2_dfii_pi1_address0_r; reg csrbank2_dfii_pi1_address0_we = 1'd0; wire [15:0] csrbank2_dfii_pi1_address0_w; reg csrbank2_dfii_pi1_baddress0_re = 1'd0; wire [2:0] csrbank2_dfii_pi1_baddress0_r; reg csrbank2_dfii_pi1_baddress0_we = 1'd0; wire [2:0] csrbank2_dfii_pi1_baddress0_w; reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; wire [31:0] csrbank2_dfii_pi1_wrdata0_r; reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; wire [31:0] csrbank2_dfii_pi1_wrdata0_w; reg csrbank2_dfii_pi1_rddata_re = 1'd0; wire [31:0] csrbank2_dfii_pi1_rddata_r; reg csrbank2_dfii_pi1_rddata_we = 1'd0; wire [31:0] csrbank2_dfii_pi1_rddata_w; reg csrbank2_dfii_pi2_command0_re = 1'd0; wire [5:0] csrbank2_dfii_pi2_command0_r; reg csrbank2_dfii_pi2_command0_we = 1'd0; wire [5:0] csrbank2_dfii_pi2_command0_w; reg csrbank2_dfii_pi2_address0_re = 1'd0; wire [15:0] csrbank2_dfii_pi2_address0_r; reg csrbank2_dfii_pi2_address0_we = 1'd0; wire [15:0] csrbank2_dfii_pi2_address0_w; reg csrbank2_dfii_pi2_baddress0_re = 1'd0; wire [2:0] csrbank2_dfii_pi2_baddress0_r; reg csrbank2_dfii_pi2_baddress0_we = 1'd0; wire [2:0] csrbank2_dfii_pi2_baddress0_w; reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; wire [31:0] csrbank2_dfii_pi2_wrdata0_r; reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; wire [31:0] csrbank2_dfii_pi2_wrdata0_w; reg csrbank2_dfii_pi2_rddata_re = 1'd0; wire [31:0] csrbank2_dfii_pi2_rddata_r; reg csrbank2_dfii_pi2_rddata_we = 1'd0; wire [31:0] csrbank2_dfii_pi2_rddata_w; reg csrbank2_dfii_pi3_command0_re = 1'd0; wire [5:0] csrbank2_dfii_pi3_command0_r; reg csrbank2_dfii_pi3_command0_we = 1'd0; wire [5:0] csrbank2_dfii_pi3_command0_w; reg csrbank2_dfii_pi3_address0_re = 1'd0; wire [15:0] csrbank2_dfii_pi3_address0_r; reg csrbank2_dfii_pi3_address0_we = 1'd0; wire [15:0] csrbank2_dfii_pi3_address0_w; reg csrbank2_dfii_pi3_baddress0_re = 1'd0; wire [2:0] csrbank2_dfii_pi3_baddress0_r; reg csrbank2_dfii_pi3_baddress0_we = 1'd0; wire [2:0] csrbank2_dfii_pi3_baddress0_w; reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; wire [31:0] csrbank2_dfii_pi3_wrdata0_r; reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; wire [31:0] csrbank2_dfii_pi3_wrdata0_w; reg csrbank2_dfii_pi3_rddata_re = 1'd0; wire [31:0] csrbank2_dfii_pi3_rddata_r; reg csrbank2_dfii_pi3_rddata_we = 1'd0; wire [31:0] csrbank2_dfii_pi3_rddata_w; wire csrbank2_sel; wire [13:0] csr_interconnect_adr; wire csr_interconnect_we; wire [31:0] csr_interconnect_dat_w; wire [31:0] csr_interconnect_dat_r; wire litedramcore_reset0; wire litedramcore_reset1; wire litedramcore_reset2; wire litedramcore_reset3; wire litedramcore_reset4; wire litedramcore_reset5; wire litedramcore_reset6; wire litedramcore_reset7; wire litedramcore_pll_fb; reg [1:0] litedramcore_refresher_state = 2'd0; reg [1:0] litedramcore_refresher_next_state = 2'd0; reg [3:0] litedramcore_bankmachine0_state = 4'd0; reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; reg [3:0] litedramcore_bankmachine1_state = 4'd0; reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; reg [3:0] litedramcore_bankmachine2_state = 4'd0; reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; reg [3:0] litedramcore_bankmachine3_state = 4'd0; reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; reg [3:0] litedramcore_bankmachine4_state = 4'd0; reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; reg [3:0] litedramcore_bankmachine5_state = 4'd0; reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; reg [3:0] litedramcore_bankmachine6_state = 4'd0; reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; reg [3:0] litedramcore_bankmachine7_state = 4'd0; reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; reg [3:0] litedramcore_multiplexer_state = 4'd0; reg [3:0] litedramcore_multiplexer_next_state = 4'd0; wire litedramcore_roundrobin0_request; wire litedramcore_roundrobin0_grant; wire litedramcore_roundrobin0_ce; wire litedramcore_roundrobin1_request; wire litedramcore_roundrobin1_grant; wire litedramcore_roundrobin1_ce; wire litedramcore_roundrobin2_request; wire litedramcore_roundrobin2_grant; wire litedramcore_roundrobin2_ce; wire litedramcore_roundrobin3_request; wire litedramcore_roundrobin3_grant; wire litedramcore_roundrobin3_ce; wire litedramcore_roundrobin4_request; wire litedramcore_roundrobin4_grant; wire litedramcore_roundrobin4_ce; wire litedramcore_roundrobin5_request; wire litedramcore_roundrobin5_grant; wire litedramcore_roundrobin5_ce; wire litedramcore_roundrobin6_request; wire litedramcore_roundrobin6_grant; wire litedramcore_roundrobin6_ce; wire litedramcore_roundrobin7_request; wire litedramcore_roundrobin7_grant; wire litedramcore_roundrobin7_ce; reg litedramcore_locked0 = 1'd0; reg litedramcore_locked1 = 1'd0; reg litedramcore_locked2 = 1'd0; reg litedramcore_locked3 = 1'd0; reg litedramcore_locked4 = 1'd0; reg litedramcore_locked5 = 1'd0; reg litedramcore_locked6 = 1'd0; reg litedramcore_locked7 = 1'd0; reg litedramcore_new_master_wdata_ready0 = 1'd0; reg litedramcore_new_master_wdata_ready1 = 1'd0; reg litedramcore_new_master_rdata_valid0 = 1'd0; reg litedramcore_new_master_rdata_valid1 = 1'd0; reg litedramcore_new_master_rdata_valid2 = 1'd0; reg litedramcore_new_master_rdata_valid3 = 1'd0; reg litedramcore_new_master_rdata_valid4 = 1'd0; reg litedramcore_new_master_rdata_valid5 = 1'd0; reg litedramcore_new_master_rdata_valid6 = 1'd0; reg litedramcore_new_master_rdata_valid7 = 1'd0; reg litedramcore_new_master_rdata_valid8 = 1'd0; reg [1:0] litedramcore_state = 2'd0; reg [1:0] litedramcore_next_state = 2'd0; reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; reg litedramcore_dat_w_next_value_ce0 = 1'd0; reg [13:0] litedramcore_adr_next_value1 = 14'd0; reg litedramcore_adr_next_value_ce1 = 1'd0; reg litedramcore_we_next_value2 = 1'd0; reg litedramcore_we_next_value_ce2 = 1'd0; reg rhs_array_muxed0 = 1'd0; reg [15:0] rhs_array_muxed1 = 16'd0; reg [2:0] rhs_array_muxed2 = 3'd0; reg rhs_array_muxed3 = 1'd0; reg rhs_array_muxed4 = 1'd0; reg rhs_array_muxed5 = 1'd0; reg t_array_muxed0 = 1'd0; reg t_array_muxed1 = 1'd0; reg t_array_muxed2 = 1'd0; reg rhs_array_muxed6 = 1'd0; reg [15:0] rhs_array_muxed7 = 16'd0; reg [2:0] rhs_array_muxed8 = 3'd0; reg rhs_array_muxed9 = 1'd0; reg rhs_array_muxed10 = 1'd0; reg rhs_array_muxed11 = 1'd0; reg t_array_muxed3 = 1'd0; reg t_array_muxed4 = 1'd0; reg t_array_muxed5 = 1'd0; reg [22:0] rhs_array_muxed12 = 23'd0; reg rhs_array_muxed13 = 1'd0; reg rhs_array_muxed14 = 1'd0; reg [22:0] rhs_array_muxed15 = 23'd0; reg rhs_array_muxed16 = 1'd0; reg rhs_array_muxed17 = 1'd0; reg [22:0] rhs_array_muxed18 = 23'd0; reg rhs_array_muxed19 = 1'd0; reg rhs_array_muxed20 = 1'd0; reg [22:0] rhs_array_muxed21 = 23'd0; reg rhs_array_muxed22 = 1'd0; reg rhs_array_muxed23 = 1'd0; reg [22:0] rhs_array_muxed24 = 23'd0; reg rhs_array_muxed25 = 1'd0; reg rhs_array_muxed26 = 1'd0; reg [22:0] rhs_array_muxed27 = 23'd0; reg rhs_array_muxed28 = 1'd0; reg rhs_array_muxed29 = 1'd0; reg [22:0] rhs_array_muxed30 = 23'd0; reg rhs_array_muxed31 = 1'd0; reg rhs_array_muxed32 = 1'd0; reg [22:0] rhs_array_muxed33 = 23'd0; reg rhs_array_muxed34 = 1'd0; reg rhs_array_muxed35 = 1'd0; reg [2:0] array_muxed0 = 3'd0; reg [15:0] array_muxed1 = 16'd0; reg array_muxed2 = 1'd0; reg array_muxed3 = 1'd0; reg array_muxed4 = 1'd0; reg array_muxed5 = 1'd0; reg array_muxed6 = 1'd0; reg [2:0] array_muxed7 = 3'd0; reg [15:0] array_muxed8 = 16'd0; reg array_muxed9 = 1'd0; reg array_muxed10 = 1'd0; reg array_muxed11 = 1'd0; reg array_muxed12 = 1'd0; reg array_muxed13 = 1'd0; reg [2:0] array_muxed14 = 3'd0; reg [15:0] array_muxed15 = 16'd0; reg array_muxed16 = 1'd0; reg array_muxed17 = 1'd0; reg array_muxed18 = 1'd0; reg array_muxed19 = 1'd0; reg array_muxed20 = 1'd0; reg [2:0] array_muxed21 = 3'd0; reg [15:0] array_muxed22 = 16'd0; reg array_muxed23 = 1'd0; reg array_muxed24 = 1'd0; reg array_muxed25 = 1'd0; reg array_muxed26 = 1'd0; reg array_muxed27 = 1'd0; wire xilinxasyncresetsynchronizerimpl0; wire xilinxasyncresetsynchronizerimpl0_rst_meta; wire xilinxasyncresetsynchronizerimpl1; wire xilinxasyncresetsynchronizerimpl1_rst_meta; wire xilinxasyncresetsynchronizerimpl2; wire xilinxasyncresetsynchronizerimpl2_rst_meta; wire xilinxasyncresetsynchronizerimpl2_expr; wire xilinxasyncresetsynchronizerimpl3; wire xilinxasyncresetsynchronizerimpl3_rst_meta; wire xilinxasyncresetsynchronizerimpl3_expr; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ assign init_done = init_done_storage; assign init_error = init_error_storage; assign wb_bus_adr = wb_ctrl_adr; assign wb_bus_dat_w = wb_ctrl_dat_w; assign wb_ctrl_dat_r = wb_bus_dat_r; assign wb_bus_sel = wb_ctrl_sel; assign wb_bus_cyc = wb_ctrl_cyc; assign wb_bus_stb = wb_ctrl_stb; assign wb_ctrl_ack = wb_bus_ack; assign wb_bus_we = wb_ctrl_we; assign wb_bus_cti = wb_ctrl_cti; assign wb_bus_bte = wb_ctrl_bte; assign wb_ctrl_err = wb_bus_err; assign user_clk = sys_clk; assign user_rst = sys_rst; assign user_enable = 1'd1; assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable); assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable); assign user_port_cmd_payload_we = user_port_native_0_cmd_we; assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable); assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable); assign user_port_wdata_payload_we = user_port_native_0_wdata_we; assign user_port_wdata_payload_data = user_port_native_0_wdata_data; assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable); assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable); assign user_port_native_0_rdata_data = user_port_rdata_payload_data; assign reset = (rst | rst_1); assign pll_locked = locked; assign clkin = clk; assign iodelay_clk = clkout_buf0; assign sys_clk = clkout_buf1; assign sys4x_clk = clkout_buf2; assign sys4x_dqs_clk = clkout_buf3; assign ddram_ba = a7ddrphy_pads_ba; assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); always @(*) begin a7ddrphy_dfi_p0_rddata <= 32'd0; a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; end always @(*) begin a7ddrphy_dfi_p1_rddata <= 32'd0; a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; end always @(*) begin a7ddrphy_dfi_p2_rddata <= 32'd0; a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; end always @(*) begin a7ddrphy_dfi_p3_rddata <= 32'd0; a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; end assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin a7ddrphy_dqs_oe <= 1'd0; if (a7ddrphy_wlevel_en_storage) begin a7ddrphy_dqs_oe <= 1'd1; end else begin a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; end end assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin a7ddrphy_dqspattern_o0 <= 8'd0; a7ddrphy_dqspattern_o0 <= 7'd85; if (a7ddrphy_dqspattern0) begin a7ddrphy_dqspattern_o0 <= 5'd21; end if (a7ddrphy_dqspattern1) begin a7ddrphy_dqspattern_o0 <= 7'd84; end if (a7ddrphy_wlevel_en_storage) begin a7ddrphy_dqspattern_o0 <= 1'd0; if (a7ddrphy_wlevel_strobe_re) begin a7ddrphy_dqspattern_o0 <= 1'd1; end end end always @(*) begin a7ddrphy_bitslip00 <= 8'd0; case (a7ddrphy_bitslip0_value0) 1'd0: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip10 <= 8'd0; case (a7ddrphy_bitslip1_value0) 1'd0: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip01 <= 8'd0; case (a7ddrphy_bitslip0_value1) 1'd0: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip11 <= 8'd0; case (a7ddrphy_bitslip1_value1) 1'd0: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip02 <= 8'd0; case (a7ddrphy_bitslip0_value2) 1'd0: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; end 1'd1: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; end 2'd2: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; end 2'd3: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; end 3'd4: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; end 3'd5: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; end 3'd6: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; end 3'd7: begin a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip04 <= 8'd0; case (a7ddrphy_bitslip0_value3) 1'd0: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; end 1'd1: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; end 2'd2: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; end 2'd3: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; end 3'd4: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; end 3'd5: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; end 3'd6: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; end 3'd7: begin a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip12 <= 8'd0; case (a7ddrphy_bitslip1_value2) 1'd0: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; end 1'd1: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; end 2'd2: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; end 2'd3: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; end 3'd4: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; end 3'd5: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; end 3'd6: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; end 3'd7: begin a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip14 <= 8'd0; case (a7ddrphy_bitslip1_value3) 1'd0: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; end 1'd1: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; end 2'd2: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; end 2'd3: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; end 3'd4: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; end 3'd5: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; end 3'd6: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; end 3'd7: begin a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip20 <= 8'd0; case (a7ddrphy_bitslip2_value0) 1'd0: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip22 <= 8'd0; case (a7ddrphy_bitslip2_value1) 1'd0: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip30 <= 8'd0; case (a7ddrphy_bitslip3_value0) 1'd0: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip32 <= 8'd0; case (a7ddrphy_bitslip3_value1) 1'd0: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip40 <= 8'd0; case (a7ddrphy_bitslip4_value0) 1'd0: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip42 <= 8'd0; case (a7ddrphy_bitslip4_value1) 1'd0: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip50 <= 8'd0; case (a7ddrphy_bitslip5_value0) 1'd0: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip52 <= 8'd0; case (a7ddrphy_bitslip5_value1) 1'd0: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip60 <= 8'd0; case (a7ddrphy_bitslip6_value0) 1'd0: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip62 <= 8'd0; case (a7ddrphy_bitslip6_value1) 1'd0: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip70 <= 8'd0; case (a7ddrphy_bitslip7_value0) 1'd0: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip72 <= 8'd0; case (a7ddrphy_bitslip7_value1) 1'd0: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip80 <= 8'd0; case (a7ddrphy_bitslip8_value0) 1'd0: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip82 <= 8'd0; case (a7ddrphy_bitslip8_value1) 1'd0: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip90 <= 8'd0; case (a7ddrphy_bitslip9_value0) 1'd0: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip92 <= 8'd0; case (a7ddrphy_bitslip9_value1) 1'd0: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip100 <= 8'd0; case (a7ddrphy_bitslip10_value0) 1'd0: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip102 <= 8'd0; case (a7ddrphy_bitslip10_value1) 1'd0: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip110 <= 8'd0; case (a7ddrphy_bitslip11_value0) 1'd0: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip112 <= 8'd0; case (a7ddrphy_bitslip11_value1) 1'd0: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip120 <= 8'd0; case (a7ddrphy_bitslip12_value0) 1'd0: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip122 <= 8'd0; case (a7ddrphy_bitslip12_value1) 1'd0: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip130 <= 8'd0; case (a7ddrphy_bitslip13_value0) 1'd0: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip132 <= 8'd0; case (a7ddrphy_bitslip13_value1) 1'd0: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip140 <= 8'd0; case (a7ddrphy_bitslip14_value0) 1'd0: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip142 <= 8'd0; case (a7ddrphy_bitslip14_value1) 1'd0: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip150 <= 8'd0; case (a7ddrphy_bitslip15_value0) 1'd0: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; end 1'd1: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; end 2'd2: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; end 2'd3: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; end 3'd4: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; end 3'd5: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; end 3'd6: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; end 3'd7: begin a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; end endcase end always @(*) begin a7ddrphy_bitslip152 <= 8'd0; case (a7ddrphy_bitslip15_value1) 1'd0: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; end 1'd1: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; end 2'd2: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; end 2'd3: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; end 3'd4: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; end 3'd5: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; end 3'd6: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; end 3'd7: begin a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; end endcase end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata; assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid; assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address; assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata; assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid; assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address; assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata; assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid; assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address; assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata; assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid; assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin litedramcore_master_p3_ras_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; end else begin litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; end end else begin litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; end end always @(*) begin litedramcore_master_p3_we_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; end else begin litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; end end else begin litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; end end always @(*) begin litedramcore_master_p3_cke <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; end else begin litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; end end else begin litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; end end always @(*) begin litedramcore_master_p3_odt <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; end else begin litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; end end else begin litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; end end always @(*) begin litedramcore_master_p3_reset_n <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; end else begin litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; end end else begin litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; end end always @(*) begin litedramcore_master_p3_act_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; end else begin litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; end end else begin litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; end end always @(*) begin litedramcore_master_p3_wrdata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; end else begin litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; end end else begin litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; end end always @(*) begin litedramcore_master_p3_wrdata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; end else begin litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; end end else begin litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; end end always @(*) begin litedramcore_master_p3_wrdata_mask <= 4'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; end else begin litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; end end else begin litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; end end always @(*) begin litedramcore_master_p3_rddata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; end else begin litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; end end else begin litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; end end always @(*) begin litedramcore_csr_dfi_p0_rddata <= 32'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; end end always @(*) begin litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end end always @(*) begin litedramcore_csr_dfi_p1_rddata <= 32'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; end end always @(*) begin litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end end always @(*) begin litedramcore_csr_dfi_p2_rddata <= 32'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; end end always @(*) begin litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end end always @(*) begin litedramcore_csr_dfi_p3_rddata <= 32'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; end end always @(*) begin litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; if (litedramcore_sel) begin end else begin litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end end always @(*) begin litedramcore_ext_dfi_p0_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; end else begin end end else begin end end always @(*) begin litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin end end else begin end end always @(*) begin litedramcore_ext_dfi_p1_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; end else begin end end else begin end end always @(*) begin litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end else begin end end else begin end end always @(*) begin litedramcore_ext_dfi_p2_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; end else begin end end else begin end end always @(*) begin litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end else begin end end else begin end end always @(*) begin litedramcore_slave_p0_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; end end else begin end end always @(*) begin litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end end else begin end end always @(*) begin litedramcore_ext_dfi_p3_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; end else begin end end else begin end end always @(*) begin litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end else begin end end else begin end end always @(*) begin litedramcore_slave_p1_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; end end else begin end end always @(*) begin litedramcore_slave_p1_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end end else begin end end always @(*) begin litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end end else begin end end always @(*) begin litedramcore_slave_p2_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end end else begin end end always @(*) begin litedramcore_slave_p3_rddata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; end end else begin end end always @(*) begin litedramcore_slave_p3_rddata_valid <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin end else begin litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end end else begin end end always @(*) begin litedramcore_master_p0_address <= 16'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; end else begin litedramcore_master_p0_address <= litedramcore_slave_p0_address; end end else begin litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; end end always @(*) begin litedramcore_master_p0_bank <= 3'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; end else begin litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; end end else begin litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; end end always @(*) begin litedramcore_master_p0_cas_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; end else begin litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; end end else begin litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; end end always @(*) begin litedramcore_master_p0_cs_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; end else begin litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; end end else begin litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; end end always @(*) begin litedramcore_master_p0_ras_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; end else begin litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; end end else begin litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; end end always @(*) begin litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; end else begin litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end end else begin litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; end end always @(*) begin litedramcore_master_p0_cke <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; end else begin litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; end end else begin litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; end end always @(*) begin litedramcore_master_p0_odt <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; end else begin litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; end end else begin litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; end end always @(*) begin litedramcore_master_p0_reset_n <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; end else begin litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; end end else begin litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; end end always @(*) begin litedramcore_master_p0_act_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; end else begin litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; end end else begin litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; end end always @(*) begin litedramcore_master_p0_wrdata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; end else begin litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; end end else begin litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; end end always @(*) begin litedramcore_master_p0_wrdata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; end else begin litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; end end else begin litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; end end always @(*) begin litedramcore_master_p0_wrdata_mask <= 4'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; end else begin litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; end end else begin litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; end end always @(*) begin litedramcore_master_p0_rddata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; end else begin litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; end end else begin litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; end end always @(*) begin litedramcore_master_p1_address <= 16'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; end else begin litedramcore_master_p1_address <= litedramcore_slave_p1_address; end end else begin litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; end end always @(*) begin litedramcore_master_p1_bank <= 3'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; end else begin litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; end end else begin litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; end end always @(*) begin litedramcore_master_p1_cas_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; end else begin litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; end end else begin litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; end end always @(*) begin litedramcore_master_p1_cs_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; end else begin litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; end end else begin litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; end end always @(*) begin litedramcore_master_p1_ras_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; end else begin litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; end end else begin litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; end end always @(*) begin litedramcore_master_p1_we_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; end else begin litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; end end else begin litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; end end always @(*) begin litedramcore_master_p1_cke <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; end else begin litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; end end else begin litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; end end always @(*) begin litedramcore_master_p1_odt <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; end else begin litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; end end else begin litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; end end always @(*) begin litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; end else begin litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end end else begin litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; end end always @(*) begin litedramcore_master_p1_act_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; end else begin litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; end end else begin litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; end end always @(*) begin litedramcore_master_p1_wrdata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; end else begin litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; end end else begin litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; end end always @(*) begin litedramcore_master_p1_wrdata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; end else begin litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; end end else begin litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; end end always @(*) begin litedramcore_master_p1_wrdata_mask <= 4'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; end else begin litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; end end else begin litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; end end always @(*) begin litedramcore_master_p1_rddata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; end else begin litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; end end else begin litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; end end always @(*) begin litedramcore_master_p2_address <= 16'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; end else begin litedramcore_master_p2_address <= litedramcore_slave_p2_address; end end else begin litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; end end always @(*) begin litedramcore_master_p2_bank <= 3'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; end else begin litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; end end else begin litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; end end always @(*) begin litedramcore_master_p2_cas_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; end else begin litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; end end else begin litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; end end always @(*) begin litedramcore_master_p2_cs_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; end else begin litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; end end else begin litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; end end always @(*) begin litedramcore_master_p2_ras_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; end else begin litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; end end else begin litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; end end always @(*) begin litedramcore_master_p2_we_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; end else begin litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; end end else begin litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; end end always @(*) begin litedramcore_master_p2_cke <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; end else begin litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; end end else begin litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; end end always @(*) begin litedramcore_master_p2_odt <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; end else begin litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; end end else begin litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; end end always @(*) begin litedramcore_master_p2_reset_n <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; end else begin litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; end end else begin litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; end end always @(*) begin litedramcore_master_p2_act_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; end else begin litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; end end else begin litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; end end always @(*) begin litedramcore_master_p2_wrdata <= 32'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; end else begin litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; end end else begin litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; end end always @(*) begin litedramcore_master_p2_wrdata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; end else begin litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; end end else begin litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; end end always @(*) begin litedramcore_master_p2_wrdata_mask <= 4'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; end else begin litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; end end else begin litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; end end always @(*) begin litedramcore_master_p2_rddata_en <= 1'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; end else begin litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; end end else begin litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; end end always @(*) begin litedramcore_master_p3_address <= 16'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; end else begin litedramcore_master_p3_address <= litedramcore_slave_p3_address; end end else begin litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; end end always @(*) begin litedramcore_master_p3_bank <= 3'd0; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; end else begin litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; end end else begin litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; end end always @(*) begin litedramcore_master_p3_cas_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; end else begin litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; end end else begin litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; end end always @(*) begin litedramcore_master_p3_cs_n <= 1'd1; if (litedramcore_sel) begin if (litedramcore_ext_dfi_sel) begin litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; end else begin litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; end end else begin litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; assign litedramcore_csr_dfi_p2_cke = litedramcore_cke; assign litedramcore_csr_dfi_p3_cke = litedramcore_cke; assign litedramcore_csr_dfi_p0_odt = litedramcore_odt; assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; assign litedramcore_csr_dfi_p2_odt = litedramcore_odt; assign litedramcore_csr_dfi_p3_odt = litedramcore_odt; assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin litedramcore_csr_dfi_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); end else begin litedramcore_csr_dfi_p0_cas_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p0_cs_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; end else begin litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; end end always @(*) begin litedramcore_csr_dfi_p0_ras_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); end else begin litedramcore_csr_dfi_p0_ras_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p0_we_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); end else begin litedramcore_csr_dfi_p0_we_n <= 1'd1; end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; assign litedramcore_csr_dfi_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_wren); assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_csrfield_rden); assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin litedramcore_csr_dfi_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); end else begin litedramcore_csr_dfi_p1_cas_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p1_cs_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; end else begin litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; end end always @(*) begin litedramcore_csr_dfi_p1_ras_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); end else begin litedramcore_csr_dfi_p1_ras_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p1_we_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); end else begin litedramcore_csr_dfi_p1_we_n <= 1'd1; end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; assign litedramcore_csr_dfi_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_wren); assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_csrfield_rden); assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin litedramcore_csr_dfi_p2_cas_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); end else begin litedramcore_csr_dfi_p2_cas_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p2_cs_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; end else begin litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; end end always @(*) begin litedramcore_csr_dfi_p2_ras_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); end else begin litedramcore_csr_dfi_p2_ras_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p2_we_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); end else begin litedramcore_csr_dfi_p2_we_n <= 1'd1; end end assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; assign litedramcore_csr_dfi_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_wren); assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_csrfield_rden); assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin litedramcore_csr_dfi_p3_cas_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); end else begin litedramcore_csr_dfi_p3_cas_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p3_cs_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; end else begin litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; end end always @(*) begin litedramcore_csr_dfi_p3_ras_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); end else begin litedramcore_csr_dfi_p3_ras_n <= 1'd1; end end always @(*) begin litedramcore_csr_dfi_p3_we_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); end else begin litedramcore_csr_dfi_p3_we_n <= 1'd1; end end assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; assign litedramcore_csr_dfi_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_wren); assign litedramcore_csr_dfi_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_csrfield_rden); assign litedramcore_csr_dfi_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; assign litedramcore_csr_dfi_p3_wrdata_mask = 1'd0; assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; assign litedramcore_timer_wait = (~litedramcore_timer_done0); assign litedramcore_postponer_req_i = litedramcore_timer_done0; assign litedramcore_wants_refresh = litedramcore_postponer_req_o; assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); assign litedramcore_timer_done0 = litedramcore_timer_done1; assign litedramcore_timer_count0 = litedramcore_timer_count1; assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin litedramcore_refresher_next_state <= 2'd0; litedramcore_refresher_next_state <= litedramcore_refresher_state; case (litedramcore_refresher_state) 1'd1: begin if (litedramcore_cmd_ready) begin litedramcore_refresher_next_state <= 2'd2; end end 2'd2: begin if (litedramcore_sequencer_done0) begin if (litedramcore_wants_zqcs) begin litedramcore_refresher_next_state <= 2'd3; end else begin litedramcore_refresher_next_state <= 1'd0; end end end 2'd3: begin if (litedramcore_zqcs_executer_done) begin litedramcore_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin if (litedramcore_wants_refresh) begin litedramcore_refresher_next_state <= 1'd1; end end end endcase end always @(*) begin litedramcore_cmd_valid <= 1'd0; case (litedramcore_refresher_state) 1'd1: begin litedramcore_cmd_valid <= 1'd1; end 2'd2: begin litedramcore_cmd_valid <= 1'd1; if (litedramcore_sequencer_done0) begin if (litedramcore_wants_zqcs) begin end else begin litedramcore_cmd_valid <= 1'd0; end end end 2'd3: begin litedramcore_cmd_valid <= 1'd1; if (litedramcore_zqcs_executer_done) begin litedramcore_cmd_valid <= 1'd0; end end default: begin end endcase end always @(*) begin litedramcore_zqcs_executer_start <= 1'd0; case (litedramcore_refresher_state) 1'd1: begin end 2'd2: begin if (litedramcore_sequencer_done0) begin if (litedramcore_wants_zqcs) begin litedramcore_zqcs_executer_start <= 1'd1; end else begin end end end 2'd3: begin end default: begin end endcase end always @(*) begin litedramcore_cmd_last <= 1'd0; case (litedramcore_refresher_state) 1'd1: begin end 2'd2: begin if (litedramcore_sequencer_done0) begin if (litedramcore_wants_zqcs) begin end else begin litedramcore_cmd_last <= 1'd1; end end end 2'd3: begin if (litedramcore_zqcs_executer_done) begin litedramcore_cmd_last <= 1'd1; end end default: begin end endcase end always @(*) begin litedramcore_sequencer_start0 <= 1'd0; case (litedramcore_refresher_state) 1'd1: begin if (litedramcore_cmd_ready) begin litedramcore_sequencer_start0 <= 1'd1; end end 2'd2: begin end 2'd3: begin end default: begin end endcase end assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[22:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin litedramcore_bankmachine0_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine0_row_col_n_addr_sel) begin litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin litedramcore_bankmachine0_auto_precharge <= 1'd0; if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin if ((litedramcore_bankmachine0_source_payload_addr[22:7] != litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); end end end assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; always @(*) begin litedramcore_bankmachine0_wrport_adr <= 4'd0; if (litedramcore_bankmachine0_replace) begin litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); end else begin litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; end end assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine0_next_state <= 4'd0; litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin if (litedramcore_bankmachine0_cmd_ready) begin litedramcore_bankmachine0_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin if (litedramcore_bankmachine0_cmd_ready) begin litedramcore_bankmachine0_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine0_refresh_req)) begin litedramcore_bankmachine0_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine0_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine0_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine0_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine0_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine0_refresh_req) begin litedramcore_bankmachine0_next_state <= 3'd4; end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin litedramcore_bankmachine0_next_state <= 2'd2; end end else begin litedramcore_bankmachine0_next_state <= 1'd1; end end else begin litedramcore_bankmachine0_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_source_source_payload_we) begin end else begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_source_source_payload_we) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_source_source_payload_we) begin litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_source_source_payload_we) begin end else begin litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine0_twtpcon_ready) begin litedramcore_bankmachine0_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine0_row_open <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin litedramcore_bankmachine0_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin litedramcore_bankmachine0_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin litedramcore_bankmachine0_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin end else begin if (litedramcore_bankmachine0_source_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_source_source_payload_we) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[22:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin litedramcore_bankmachine1_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine1_row_col_n_addr_sel) begin litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin litedramcore_bankmachine1_auto_precharge <= 1'd0; if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin if ((litedramcore_bankmachine1_source_payload_addr[22:7] != litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); end end end assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; always @(*) begin litedramcore_bankmachine1_wrport_adr <= 4'd0; if (litedramcore_bankmachine1_replace) begin litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); end else begin litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; end end assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine1_next_state <= 4'd0; litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin if (litedramcore_bankmachine1_cmd_ready) begin litedramcore_bankmachine1_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin litedramcore_bankmachine1_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin if (litedramcore_bankmachine1_cmd_ready) begin litedramcore_bankmachine1_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine1_refresh_req)) begin litedramcore_bankmachine1_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine1_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine1_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine1_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine1_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine1_refresh_req) begin litedramcore_bankmachine1_next_state <= 3'd4; end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin litedramcore_bankmachine1_next_state <= 2'd2; end end else begin litedramcore_bankmachine1_next_state <= 1'd1; end end else begin litedramcore_bankmachine1_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine1_refresh_gnt <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine1_twtpcon_ready) begin litedramcore_bankmachine1_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine1_row_open <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin litedramcore_bankmachine1_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine1_cmd_valid <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin litedramcore_bankmachine1_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin litedramcore_bankmachine1_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine1_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine1_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_source_source_payload_we) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_source_source_payload_we) begin end else begin litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_source_source_payload_we) begin litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_source_source_payload_we) begin litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine1_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine1_refresh_req) begin end else begin if (litedramcore_bankmachine1_source_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_source_source_payload_we) begin end else begin litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; end end else begin end end else begin end end end end endcase end assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[22:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin litedramcore_bankmachine2_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine2_row_col_n_addr_sel) begin litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin litedramcore_bankmachine2_auto_precharge <= 1'd0; if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin if ((litedramcore_bankmachine2_source_payload_addr[22:7] != litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); end end end assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; always @(*) begin litedramcore_bankmachine2_wrport_adr <= 4'd0; if (litedramcore_bankmachine2_replace) begin litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); end else begin litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; end end assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine2_next_state <= 4'd0; litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin if (litedramcore_bankmachine2_cmd_ready) begin litedramcore_bankmachine2_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin litedramcore_bankmachine2_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin if (litedramcore_bankmachine2_cmd_ready) begin litedramcore_bankmachine2_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine2_refresh_req)) begin litedramcore_bankmachine2_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine2_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine2_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine2_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine2_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine2_refresh_req) begin litedramcore_bankmachine2_next_state <= 3'd4; end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin litedramcore_bankmachine2_next_state <= 2'd2; end end else begin litedramcore_bankmachine2_next_state <= 1'd1; end end else begin litedramcore_bankmachine2_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_source_source_payload_we) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_source_source_payload_we) begin end else begin litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_source_source_payload_we) begin litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_source_source_payload_we) begin litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_source_source_payload_we) begin end else begin litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine2_twtpcon_ready) begin litedramcore_bankmachine2_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine2_row_open <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine2_cmd_valid <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin litedramcore_bankmachine2_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine2_refresh_req) begin end else begin if (litedramcore_bankmachine2_source_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine2_row_close <= 1'd0; case (litedramcore_bankmachine2_state) 1'd1: begin litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[22:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin litedramcore_bankmachine3_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine3_row_col_n_addr_sel) begin litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin litedramcore_bankmachine3_auto_precharge <= 1'd0; if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin if ((litedramcore_bankmachine3_source_payload_addr[22:7] != litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); end end end assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; always @(*) begin litedramcore_bankmachine3_wrport_adr <= 4'd0; if (litedramcore_bankmachine3_replace) begin litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); end else begin litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; end end assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine3_next_state <= 4'd0; litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin if (litedramcore_bankmachine3_cmd_ready) begin litedramcore_bankmachine3_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin litedramcore_bankmachine3_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin if (litedramcore_bankmachine3_cmd_ready) begin litedramcore_bankmachine3_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine3_refresh_req)) begin litedramcore_bankmachine3_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine3_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine3_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine3_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine3_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine3_refresh_req) begin litedramcore_bankmachine3_next_state <= 3'd4; end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin litedramcore_bankmachine3_next_state <= 2'd2; end end else begin litedramcore_bankmachine3_next_state <= 1'd1; end end else begin litedramcore_bankmachine3_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_source_source_payload_we) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_source_source_payload_we) begin end else begin litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_source_source_payload_we) begin litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_source_source_payload_we) begin litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_source_source_payload_we) begin end else begin litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine3_twtpcon_ready) begin litedramcore_bankmachine3_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine3_row_open <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin litedramcore_bankmachine3_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine3_refresh_req) begin end else begin if (litedramcore_bankmachine3_source_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin litedramcore_bankmachine3_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[22:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin litedramcore_bankmachine4_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine4_row_col_n_addr_sel) begin litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin litedramcore_bankmachine4_auto_precharge <= 1'd0; if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin if ((litedramcore_bankmachine4_source_payload_addr[22:7] != litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); end end end assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; always @(*) begin litedramcore_bankmachine4_wrport_adr <= 4'd0; if (litedramcore_bankmachine4_replace) begin litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); end else begin litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; end end assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine4_next_state <= 4'd0; litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin if (litedramcore_bankmachine4_cmd_ready) begin litedramcore_bankmachine4_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin litedramcore_bankmachine4_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin if (litedramcore_bankmachine4_cmd_ready) begin litedramcore_bankmachine4_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine4_refresh_req)) begin litedramcore_bankmachine4_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine4_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine4_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine4_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine4_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine4_refresh_req) begin litedramcore_bankmachine4_next_state <= 3'd4; end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin litedramcore_bankmachine4_next_state <= 2'd2; end end else begin litedramcore_bankmachine4_next_state <= 1'd1; end end else begin litedramcore_bankmachine4_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin end else begin litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin end else begin litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_refresh_gnt <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine4_twtpcon_ready) begin litedramcore_bankmachine4_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine4_row_open <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin litedramcore_bankmachine4_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine4_cmd_valid <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin litedramcore_bankmachine4_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_row_close <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine4_refresh_req) begin end else begin if (litedramcore_bankmachine4_source_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_source_source_payload_we) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[22:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin litedramcore_bankmachine5_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine5_row_col_n_addr_sel) begin litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin litedramcore_bankmachine5_auto_precharge <= 1'd0; if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin if ((litedramcore_bankmachine5_source_payload_addr[22:7] != litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); end end end assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; always @(*) begin litedramcore_bankmachine5_wrport_adr <= 4'd0; if (litedramcore_bankmachine5_replace) begin litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); end else begin litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; end end assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine5_next_state <= 4'd0; litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin if (litedramcore_bankmachine5_cmd_ready) begin litedramcore_bankmachine5_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin litedramcore_bankmachine5_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin if (litedramcore_bankmachine5_cmd_ready) begin litedramcore_bankmachine5_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine5_refresh_req)) begin litedramcore_bankmachine5_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine5_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine5_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine5_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine5_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine5_refresh_req) begin litedramcore_bankmachine5_next_state <= 3'd4; end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin litedramcore_bankmachine5_next_state <= 2'd2; end end else begin litedramcore_bankmachine5_next_state <= 1'd1; end end else begin litedramcore_bankmachine5_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine5_twtpcon_ready) begin litedramcore_bankmachine5_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine5_row_open <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin litedramcore_bankmachine5_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine5_cmd_valid <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin litedramcore_bankmachine5_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin litedramcore_bankmachine5_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine5_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine5_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_source_source_payload_we) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_source_source_payload_we) begin end else begin litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_source_source_payload_we) begin litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_source_source_payload_we) begin litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine5_refresh_req) begin end else begin if (litedramcore_bankmachine5_source_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_source_source_payload_we) begin end else begin litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end end else begin end end end end endcase end assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[22:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin litedramcore_bankmachine6_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine6_row_col_n_addr_sel) begin litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin litedramcore_bankmachine6_auto_precharge <= 1'd0; if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin if ((litedramcore_bankmachine6_source_payload_addr[22:7] != litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); end end end assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; always @(*) begin litedramcore_bankmachine6_wrport_adr <= 4'd0; if (litedramcore_bankmachine6_replace) begin litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); end else begin litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; end end assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine6_next_state <= 4'd0; litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin if (litedramcore_bankmachine6_cmd_ready) begin litedramcore_bankmachine6_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin litedramcore_bankmachine6_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin if (litedramcore_bankmachine6_cmd_ready) begin litedramcore_bankmachine6_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine6_refresh_req)) begin litedramcore_bankmachine6_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine6_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine6_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine6_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine6_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine6_refresh_req) begin litedramcore_bankmachine6_next_state <= 3'd4; end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin litedramcore_bankmachine6_next_state <= 2'd2; end end else begin litedramcore_bankmachine6_next_state <= 1'd1; end end else begin litedramcore_bankmachine6_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_source_source_payload_we) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_source_source_payload_we) begin end else begin litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_source_source_payload_we) begin litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_source_source_payload_we) begin litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_source_source_payload_we) begin end else begin litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine6_twtpcon_ready) begin litedramcore_bankmachine6_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine6_row_open <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin litedramcore_bankmachine6_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine6_refresh_req) begin end else begin if (litedramcore_bankmachine6_source_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; case (litedramcore_bankmachine6_state) 1'd1: begin litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[22:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin litedramcore_bankmachine7_cmd_payload_a <= 16'd0; if (litedramcore_bankmachine7_row_col_n_addr_sel) begin litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[22:7]; end else begin litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin litedramcore_bankmachine7_auto_precharge <= 1'd0; if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin if ((litedramcore_bankmachine7_source_payload_addr[22:7] != litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); end end end assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; always @(*) begin litedramcore_bankmachine7_wrport_adr <= 4'd0; if (litedramcore_bankmachine7_replace) begin litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); end else begin litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; end end assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; always @(*) begin litedramcore_bankmachine7_next_state <= 4'd0; litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin if (litedramcore_bankmachine7_cmd_ready) begin litedramcore_bankmachine7_next_state <= 3'd5; end end end 2'd2: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin litedramcore_bankmachine7_next_state <= 3'd5; end end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin if (litedramcore_bankmachine7_cmd_ready) begin litedramcore_bankmachine7_next_state <= 3'd7; end end end 3'd4: begin if ((~litedramcore_bankmachine7_refresh_req)) begin litedramcore_bankmachine7_next_state <= 1'd0; end end 3'd5: begin litedramcore_bankmachine7_next_state <= 3'd6; end 3'd6: begin litedramcore_bankmachine7_next_state <= 2'd3; end 3'd7: begin litedramcore_bankmachine7_next_state <= 4'd8; end 4'd8: begin litedramcore_bankmachine7_next_state <= 1'd0; end default: begin if (litedramcore_bankmachine7_refresh_req) begin litedramcore_bankmachine7_next_state <= 3'd4; end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin litedramcore_bankmachine7_next_state <= 2'd2; end end else begin litedramcore_bankmachine7_next_state <= 1'd1; end end else begin litedramcore_bankmachine7_next_state <= 2'd3; end end end end endcase end always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_source_source_payload_we) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end end 3'd4: begin litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_source_source_payload_we) begin end else begin litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_source_source_payload_we) begin litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_source_source_payload_we) begin litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; end else begin end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_source_source_payload_we) begin end else begin litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin if (litedramcore_bankmachine7_twtpcon_ready) begin litedramcore_bankmachine7_refresh_gnt <= 1'd1; end end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine7_row_open <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin litedramcore_bankmachine7_row_open <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin if (litedramcore_bankmachine7_refresh_req) begin end else begin if (litedramcore_bankmachine7_source_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin litedramcore_bankmachine7_cmd_valid <= 1'd1; end else begin end end else begin end end end end endcase end always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end always @(*) begin litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (litedramcore_bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end default: begin end endcase end assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin litedramcore_choose_cmd_valids <= 8'd0; litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; end end always @(*) begin litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; end end always @(*) begin litedramcore_choose_cmd_cmd_payload_we <= 1'd0; if (litedramcore_choose_cmd_cmd_valid) begin litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; end end always @(*) begin litedramcore_bankmachine0_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin litedramcore_bankmachine0_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin litedramcore_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine1_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin litedramcore_bankmachine1_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin litedramcore_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine2_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin litedramcore_bankmachine2_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin litedramcore_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine3_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin litedramcore_bankmachine3_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin litedramcore_bankmachine3_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine4_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin litedramcore_bankmachine4_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin litedramcore_bankmachine4_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine5_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin litedramcore_bankmachine5_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin litedramcore_bankmachine5_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine6_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin litedramcore_bankmachine6_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin litedramcore_bankmachine6_cmd_ready <= 1'd1; end end always @(*) begin litedramcore_bankmachine7_cmd_ready <= 1'd0; if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin litedramcore_bankmachine7_cmd_ready <= 1'd1; end if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin litedramcore_bankmachine7_cmd_ready <= 1'd1; end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin litedramcore_choose_req_valids <= 8'd0; litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin litedramcore_choose_req_cmd_payload_cas <= 1'd0; if (litedramcore_choose_req_cmd_valid) begin litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; end end always @(*) begin litedramcore_choose_req_cmd_payload_ras <= 1'd0; if (litedramcore_choose_req_cmd_valid) begin litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; end end always @(*) begin litedramcore_choose_req_cmd_payload_we <= 1'd0; if (litedramcore_choose_req_cmd_valid) begin litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; assign litedramcore_dfi_p1_reset_n = 1'd1; assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; assign litedramcore_dfi_p2_reset_n = 1'd1; assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; assign litedramcore_dfi_p3_reset_n = 1'd1; assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); always @(*) begin litedramcore_multiplexer_next_state <= 4'd0; litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; case (litedramcore_multiplexer_state) 1'd1: begin if (litedramcore_read_available) begin if (((~litedramcore_write_available) | litedramcore_max_time1)) begin litedramcore_multiplexer_next_state <= 2'd3; end end if (litedramcore_go_to_refresh) begin litedramcore_multiplexer_next_state <= 2'd2; end end 2'd2: begin if (litedramcore_cmd_last) begin litedramcore_multiplexer_next_state <= 1'd0; end end 2'd3: begin if (litedramcore_twtrcon_ready) begin litedramcore_multiplexer_next_state <= 1'd0; end end 3'd4: begin litedramcore_multiplexer_next_state <= 3'd5; end 3'd5: begin litedramcore_multiplexer_next_state <= 3'd6; end 3'd6: begin litedramcore_multiplexer_next_state <= 3'd7; end 3'd7: begin litedramcore_multiplexer_next_state <= 4'd8; end 4'd8: begin litedramcore_multiplexer_next_state <= 4'd9; end 4'd9: begin litedramcore_multiplexer_next_state <= 4'd10; end 4'd10: begin litedramcore_multiplexer_next_state <= 1'd1; end default: begin if (litedramcore_write_available) begin if (((~litedramcore_read_available) | litedramcore_max_time0)) begin litedramcore_multiplexer_next_state <= 3'd4; end end if (litedramcore_go_to_refresh) begin litedramcore_multiplexer_next_state <= 2'd2; end end endcase end always @(*) begin litedramcore_steerer_sel0 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin litedramcore_steerer_sel0 <= 1'd0; if ((a7ddrphy_wrphase_storage == 1'd0)) begin litedramcore_steerer_sel0 <= 2'd2; end if ((litedramcore_wrcmdphase == 1'd0)) begin litedramcore_steerer_sel0 <= 1'd1; end end 2'd2: begin litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin litedramcore_steerer_sel0 <= 1'd0; if ((a7ddrphy_rdphase_storage == 1'd0)) begin litedramcore_steerer_sel0 <= 2'd2; end if ((litedramcore_rdcmdphase == 1'd0)) begin litedramcore_steerer_sel0 <= 1'd1; end end endcase end always @(*) begin litedramcore_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin end 2'd2: begin litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin end endcase end always @(*) begin litedramcore_steerer_sel1 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin litedramcore_steerer_sel1 <= 1'd0; if ((a7ddrphy_wrphase_storage == 1'd1)) begin litedramcore_steerer_sel1 <= 2'd2; end if ((litedramcore_wrcmdphase == 1'd1)) begin litedramcore_steerer_sel1 <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin litedramcore_steerer_sel1 <= 1'd0; if ((a7ddrphy_rdphase_storage == 1'd1)) begin litedramcore_steerer_sel1 <= 2'd2; end if ((litedramcore_rdcmdphase == 1'd1)) begin litedramcore_steerer_sel1 <= 1'd1; end end endcase end always @(*) begin litedramcore_steerer_sel2 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin litedramcore_steerer_sel2 <= 1'd0; if ((a7ddrphy_wrphase_storage == 2'd2)) begin litedramcore_steerer_sel2 <= 2'd2; end if ((litedramcore_wrcmdphase == 2'd2)) begin litedramcore_steerer_sel2 <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin litedramcore_steerer_sel2 <= 1'd0; if ((a7ddrphy_rdphase_storage == 2'd2)) begin litedramcore_steerer_sel2 <= 2'd2; end if ((litedramcore_rdcmdphase == 2'd2)) begin litedramcore_steerer_sel2 <= 1'd1; end end endcase end always @(*) begin litedramcore_choose_cmd_want_activates <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin if (1'd0) begin end else begin litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; end end endcase end always @(*) begin litedramcore_steerer_sel3 <= 2'd0; case (litedramcore_multiplexer_state) 1'd1: begin litedramcore_steerer_sel3 <= 1'd0; if ((a7ddrphy_wrphase_storage == 2'd3)) begin litedramcore_steerer_sel3 <= 2'd2; end if ((litedramcore_wrcmdphase == 2'd3)) begin litedramcore_steerer_sel3 <= 1'd1; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin litedramcore_steerer_sel3 <= 1'd0; if ((a7ddrphy_rdphase_storage == 2'd3)) begin litedramcore_steerer_sel3 <= 2'd2; end if ((litedramcore_rdcmdphase == 2'd3)) begin litedramcore_steerer_sel3 <= 1'd1; end end endcase end always @(*) begin litedramcore_en0 <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin litedramcore_en0 <= 1'd1; end endcase end always @(*) begin litedramcore_choose_cmd_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin if (1'd0) begin end else begin litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin if (1'd0) begin end else begin litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); end end endcase end always @(*) begin litedramcore_choose_req_want_reads <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin litedramcore_choose_req_want_reads <= 1'd1; end endcase end always @(*) begin litedramcore_choose_req_want_writes <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin end endcase end always @(*) begin litedramcore_en1 <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin litedramcore_en1 <= 1'd1; end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin end endcase end always @(*) begin litedramcore_choose_req_cmd_ready <= 1'd0; case (litedramcore_multiplexer_state) 1'd1: begin if (1'd0) begin litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); end else begin litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; end end 2'd2: begin end 2'd3: begin end 3'd4: begin end 3'd5: begin end 3'd6: begin end 3'd7: begin end 4'd8: begin end 4'd9: begin end 4'd10: begin end default: begin if (1'd0) begin litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); end else begin litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; end end endcase end assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); assign litedramcore_interface_bank0_addr = rhs_array_muxed12; assign litedramcore_interface_bank0_we = rhs_array_muxed13; assign litedramcore_interface_bank0_valid = rhs_array_muxed14; assign litedramcore_roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); assign litedramcore_interface_bank1_addr = rhs_array_muxed15; assign litedramcore_interface_bank1_we = rhs_array_muxed16; assign litedramcore_interface_bank1_valid = rhs_array_muxed17; assign litedramcore_roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); assign litedramcore_interface_bank2_addr = rhs_array_muxed18; assign litedramcore_interface_bank2_we = rhs_array_muxed19; assign litedramcore_interface_bank2_valid = rhs_array_muxed20; assign litedramcore_roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); assign litedramcore_interface_bank3_addr = rhs_array_muxed21; assign litedramcore_interface_bank3_we = rhs_array_muxed22; assign litedramcore_interface_bank3_valid = rhs_array_muxed23; assign litedramcore_roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); assign litedramcore_interface_bank4_addr = rhs_array_muxed24; assign litedramcore_interface_bank4_we = rhs_array_muxed25; assign litedramcore_interface_bank4_valid = rhs_array_muxed26; assign litedramcore_roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); assign litedramcore_interface_bank5_addr = rhs_array_muxed27; assign litedramcore_interface_bank5_we = rhs_array_muxed28; assign litedramcore_interface_bank5_valid = rhs_array_muxed29; assign litedramcore_roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); assign litedramcore_interface_bank6_addr = rhs_array_muxed30; assign litedramcore_interface_bank6_we = rhs_array_muxed31; assign litedramcore_interface_bank6_valid = rhs_array_muxed32; assign litedramcore_roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); assign litedramcore_interface_bank7_addr = rhs_array_muxed33; assign litedramcore_interface_bank7_we = rhs_array_muxed34; assign litedramcore_interface_bank7_valid = rhs_array_muxed35; assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin litedramcore_interface_wdata <= 128'd0; case ({litedramcore_new_master_wdata_ready1}) 1'd1: begin litedramcore_interface_wdata <= user_port_wdata_payload_data; end default: begin litedramcore_interface_wdata <= 1'd0; end endcase end always @(*) begin litedramcore_interface_wdata_we <= 16'd0; case ({litedramcore_new_master_wdata_ready1}) 1'd1: begin litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end default: begin litedramcore_interface_wdata_we <= 1'd0; end endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; assign litedramcore_roundrobin1_grant = 1'd0; assign litedramcore_roundrobin2_grant = 1'd0; assign litedramcore_roundrobin3_grant = 1'd0; assign litedramcore_roundrobin4_grant = 1'd0; assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin litedramcore_next_state <= 2'd0; litedramcore_next_state <= litedramcore_state; case (litedramcore_state) 1'd1: begin litedramcore_next_state <= 2'd2; end 2'd2: begin litedramcore_next_state <= 1'd0; end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin litedramcore_next_state <= 1'd1; end end endcase end always @(*) begin litedramcore_adr_next_value1 <= 14'd0; case (litedramcore_state) 1'd1: begin litedramcore_adr_next_value1 <= 1'd0; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; end end endcase end always @(*) begin litedramcore_adr_next_value_ce1 <= 1'd0; case (litedramcore_state) 1'd1: begin litedramcore_adr_next_value_ce1 <= 1'd1; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin litedramcore_adr_next_value_ce1 <= 1'd1; end end endcase end always @(*) begin litedramcore_wishbone_dat_r <= 32'd0; case (litedramcore_state) 1'd1: begin end 2'd2: begin litedramcore_wishbone_dat_r <= litedramcore_dat_r; end default: begin end endcase end always @(*) begin litedramcore_we_next_value2 <= 1'd0; case (litedramcore_state) 1'd1: begin litedramcore_we_next_value2 <= 1'd0; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase end always @(*) begin litedramcore_we_next_value_ce2 <= 1'd0; case (litedramcore_state) 1'd1: begin litedramcore_we_next_value_ce2 <= 1'd1; end 2'd2: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin litedramcore_we_next_value_ce2 <= 1'd1; end end endcase end always @(*) begin litedramcore_wishbone_ack <= 1'd0; case (litedramcore_state) 1'd1: begin end 2'd2: begin litedramcore_wishbone_ack <= 1'd1; end default: begin end endcase end always @(*) begin litedramcore_dat_w_next_value0 <= 32'd0; case (litedramcore_state) 1'd1: begin end 2'd2: begin end default: begin litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; end endcase end always @(*) begin litedramcore_dat_w_next_value_ce0 <= 1'd0; case (litedramcore_state) 1'd1: begin end 2'd2: begin end default: begin litedramcore_dat_w_next_value_ce0 <= 1'd1; end endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; assign wb_bus_dat_r = litedramcore_wishbone_dat_r; assign litedramcore_wishbone_sel = wb_bus_sel; assign litedramcore_wishbone_cyc = wb_bus_cyc; assign litedramcore_wishbone_stb = wb_bus_stb; assign wb_bus_ack = litedramcore_wishbone_ack; assign litedramcore_wishbone_we = wb_bus_we; assign litedramcore_wishbone_cti = wb_bus_cti; assign litedramcore_wishbone_bte = wb_bus_bte; assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin csrbank0_init_done0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin csrbank0_init_done0_we <= (~interface0_bank_bus_we); end end always @(*) begin csrbank0_init_done0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin csrbank0_init_done0_re <= interface0_bank_bus_we; end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin csrbank0_init_error0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin csrbank0_init_error0_we <= (~interface0_bank_bus_we); end end always @(*) begin csrbank0_init_error0_re <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin csrbank0_init_error0_re <= interface0_bank_bus_we; end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_rst0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin csrbank1_rst0_we <= (~interface1_bank_bus_we); end end always @(*) begin csrbank1_rst0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin csrbank1_rst0_re <= interface1_bank_bus_we; end end assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin csrbank1_dly_sel0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin csrbank1_dly_sel0_re <= interface1_bank_bus_we; end end always @(*) begin csrbank1_dly_sel0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); end end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; always @(*) begin csrbank1_half_sys8x_taps0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); end end always @(*) begin csrbank1_half_sys8x_taps0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; end end assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_wlevel_en0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin csrbank1_wlevel_en0_re <= interface1_bank_bus_we; end end always @(*) begin csrbank1_wlevel_en0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); end end assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_wlevel_strobe_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; end end always @(*) begin a7ddrphy_wlevel_strobe_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); end end assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_rdly_dq_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; end end always @(*) begin a7ddrphy_rdly_dq_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); end end assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_rdly_dq_inc_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; end end always @(*) begin a7ddrphy_rdly_dq_inc_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); end end assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); end end always @(*) begin a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; end end assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_rdly_dq_bitslip_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); end end always @(*) begin a7ddrphy_rdly_dq_bitslip_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; end end assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); end end always @(*) begin a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; end end assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin a7ddrphy_wdly_dq_bitslip_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); end end always @(*) begin a7ddrphy_wdly_dq_bitslip_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; end end assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin csrbank1_rdphase0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin csrbank1_rdphase0_re <= interface1_bank_bus_we; end end always @(*) begin csrbank1_rdphase0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin csrbank1_rdphase0_we <= (~interface1_bank_bus_we); end end assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin csrbank1_wrphase0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin csrbank1_wrphase0_we <= (~interface1_bank_bus_we); end end always @(*) begin csrbank1_wrphase0_re <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin csrbank1_wrphase0_re <= interface1_bank_bus_we; end end assign csrbank1_rst0_w = a7ddrphy_rst_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_rdphase0_w = a7ddrphy_rdphase_storage[1:0]; assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin csrbank2_dfii_control0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin csrbank2_dfii_control0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_control0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin csrbank2_dfii_pi0_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi0_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin litedramcore_phaseinjector0_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); end end always @(*) begin litedramcore_phaseinjector0_command_issue_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin csrbank2_dfii_pi0_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi0_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_dfii_pi0_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi0_baddress0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi0_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi0_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi0_rddata_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi0_rddata_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin csrbank2_dfii_pi1_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi1_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin litedramcore_phaseinjector1_command_issue_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; end end always @(*) begin litedramcore_phaseinjector1_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin csrbank2_dfii_pi1_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi1_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_dfii_pi1_baddress0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi1_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi1_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi1_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi1_rddata_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi1_rddata_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin csrbank2_dfii_pi2_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi2_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); end end assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin litedramcore_phaseinjector2_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); end end always @(*) begin litedramcore_phaseinjector2_command_issue_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin csrbank2_dfii_pi2_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi2_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_dfii_pi2_baddress0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi2_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi2_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi2_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi2_rddata_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi2_rddata_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin csrbank2_dfii_pi3_command0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi3_command0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); end end assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin litedramcore_phaseinjector3_command_issue_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; end end always @(*) begin litedramcore_phaseinjector3_command_issue_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin csrbank2_dfii_pi3_address0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi3_address0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_dfii_pi3_baddress0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi3_baddress0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; end end assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi3_wrdata0_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; end end always @(*) begin csrbank2_dfii_pi3_wrdata0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); end end assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin csrbank2_dfii_pi3_rddata_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); end end always @(*) begin csrbank2_dfii_pi3_rddata_re <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; assign litedramcore_odt = litedramcore_storage[2]; assign litedramcore_reset_n = litedramcore_storage[3]; assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign litedramcore_phaseinjector0_csrfield_cs = litedramcore_phaseinjector0_command_storage[0]; assign litedramcore_phaseinjector0_csrfield_we = litedramcore_phaseinjector0_command_storage[1]; assign litedramcore_phaseinjector0_csrfield_cas = litedramcore_phaseinjector0_command_storage[2]; assign litedramcore_phaseinjector0_csrfield_ras = litedramcore_phaseinjector0_command_storage[3]; assign litedramcore_phaseinjector0_csrfield_wren = litedramcore_phaseinjector0_command_storage[4]; assign litedramcore_phaseinjector0_csrfield_rden = litedramcore_phaseinjector0_command_storage[5]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[15:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_rddata_status[31:0]; assign litedramcore_phaseinjector0_rddata_we = csrbank2_dfii_pi0_rddata_we; assign litedramcore_phaseinjector1_csrfield_cs = litedramcore_phaseinjector1_command_storage[0]; assign litedramcore_phaseinjector1_csrfield_we = litedramcore_phaseinjector1_command_storage[1]; assign litedramcore_phaseinjector1_csrfield_cas = litedramcore_phaseinjector1_command_storage[2]; assign litedramcore_phaseinjector1_csrfield_ras = litedramcore_phaseinjector1_command_storage[3]; assign litedramcore_phaseinjector1_csrfield_wren = litedramcore_phaseinjector1_command_storage[4]; assign litedramcore_phaseinjector1_csrfield_rden = litedramcore_phaseinjector1_command_storage[5]; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[15:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_rddata_status[31:0]; assign litedramcore_phaseinjector1_rddata_we = csrbank2_dfii_pi1_rddata_we; assign litedramcore_phaseinjector2_csrfield_cs = litedramcore_phaseinjector2_command_storage[0]; assign litedramcore_phaseinjector2_csrfield_we = litedramcore_phaseinjector2_command_storage[1]; assign litedramcore_phaseinjector2_csrfield_cas = litedramcore_phaseinjector2_command_storage[2]; assign litedramcore_phaseinjector2_csrfield_ras = litedramcore_phaseinjector2_command_storage[3]; assign litedramcore_phaseinjector2_csrfield_wren = litedramcore_phaseinjector2_command_storage[4]; assign litedramcore_phaseinjector2_csrfield_rden = litedramcore_phaseinjector2_command_storage[5]; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[15:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_rddata_status[31:0]; assign litedramcore_phaseinjector2_rddata_we = csrbank2_dfii_pi2_rddata_we; assign litedramcore_phaseinjector3_csrfield_cs = litedramcore_phaseinjector3_command_storage[0]; assign litedramcore_phaseinjector3_csrfield_we = litedramcore_phaseinjector3_command_storage[1]; assign litedramcore_phaseinjector3_csrfield_cas = litedramcore_phaseinjector3_command_storage[2]; assign litedramcore_phaseinjector3_csrfield_ras = litedramcore_phaseinjector3_command_storage[3]; assign litedramcore_phaseinjector3_csrfield_wren = litedramcore_phaseinjector3_command_storage[4]; assign litedramcore_phaseinjector3_csrfield_rden = litedramcore_phaseinjector3_command_storage[5]; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[15:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_rddata_status[31:0]; assign litedramcore_phaseinjector3_rddata_we = csrbank2_dfii_pi3_rddata_we; assign csr_interconnect_adr = litedramcore_adr; assign csr_interconnect_we = litedramcore_we; assign csr_interconnect_dat_w = litedramcore_dat_w; assign litedramcore_dat_r = csr_interconnect_dat_r; assign interface0_bank_bus_adr = csr_interconnect_adr; assign interface1_bank_bus_adr = csr_interconnect_adr; assign interface2_bank_bus_adr = csr_interconnect_adr; assign interface0_bank_bus_we = csr_interconnect_we; assign interface1_bank_bus_we = csr_interconnect_we; assign interface2_bank_bus_we = csr_interconnect_we; assign interface0_bank_bus_dat_w = csr_interconnect_dat_w; assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin rhs_array_muxed0 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; end 1'd1: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; end 2'd2: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; end 2'd3: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; end 3'd4: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; end 3'd5: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; end 3'd6: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; end default: begin rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; end endcase end always @(*) begin rhs_array_muxed1 <= 16'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed2 <= 3'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed3 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed4 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed5 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed0 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed1 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed2 <= 1'd0; case (litedramcore_choose_cmd_grant) 1'd0: begin t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed6 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; end 1'd1: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; end 2'd2: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; end 2'd3: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; end 3'd4: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; end 3'd5: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; end 3'd6: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; end default: begin rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; end endcase end always @(*) begin rhs_array_muxed7 <= 16'd0; case (litedramcore_choose_req_grant) 1'd0: begin rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; end 1'd1: begin rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; end 2'd2: begin rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; end 2'd3: begin rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; end 3'd4: begin rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; end 3'd5: begin rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; end 3'd6: begin rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; end default: begin rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed8 <= 3'd0; case (litedramcore_choose_req_grant) 1'd0: begin rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; end 1'd1: begin rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; end 2'd2: begin rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; end 2'd3: begin rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; end 3'd4: begin rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; end 3'd5: begin rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; end 3'd6: begin rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; end default: begin rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed9 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; end 1'd1: begin rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; end 2'd2: begin rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; end 2'd3: begin rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; end 3'd4: begin rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; end 3'd5: begin rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; end 3'd6: begin rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; end default: begin rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed10 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; end 1'd1: begin rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; end 2'd2: begin rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; end 2'd3: begin rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; end 3'd4: begin rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; end 3'd5: begin rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; end 3'd6: begin rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; end default: begin rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed11 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; end 2'd3: begin rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; end 3'd4: begin rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; end 3'd5: begin rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; end 3'd6: begin rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; end default: begin rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed3 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; end 1'd1: begin t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; end 2'd2: begin t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; end 2'd3: begin t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; end 3'd4: begin t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; end 3'd5: begin t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; end 3'd6: begin t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; end default: begin t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed4 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; end 1'd1: begin t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; end 2'd2: begin t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; end 2'd3: begin t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; end 3'd4: begin t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; end 3'd5: begin t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; end 3'd6: begin t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; end default: begin t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed5 <= 1'd0; case (litedramcore_choose_req_grant) 1'd0: begin t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; end 1'd1: begin t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; end 2'd2: begin t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; end 2'd3: begin t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; end 3'd4: begin t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; end 3'd5: begin t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; end 3'd6: begin t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; end default: begin t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed12 <= 23'd0; case (litedramcore_roundrobin0_grant) default: begin rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed13 <= 1'd0; case (litedramcore_roundrobin0_grant) default: begin rhs_array_muxed13 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed14 <= 1'd0; case (litedramcore_roundrobin0_grant) default: begin rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed15 <= 23'd0; case (litedramcore_roundrobin1_grant) default: begin rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed16 <= 1'd0; case (litedramcore_roundrobin1_grant) default: begin rhs_array_muxed16 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed17 <= 1'd0; case (litedramcore_roundrobin1_grant) default: begin rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed18 <= 23'd0; case (litedramcore_roundrobin2_grant) default: begin rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed19 <= 1'd0; case (litedramcore_roundrobin2_grant) default: begin rhs_array_muxed19 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed20 <= 1'd0; case (litedramcore_roundrobin2_grant) default: begin rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed21 <= 23'd0; case (litedramcore_roundrobin3_grant) default: begin rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed22 <= 1'd0; case (litedramcore_roundrobin3_grant) default: begin rhs_array_muxed22 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed23 <= 1'd0; case (litedramcore_roundrobin3_grant) default: begin rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed24 <= 23'd0; case (litedramcore_roundrobin4_grant) default: begin rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed25 <= 1'd0; case (litedramcore_roundrobin4_grant) default: begin rhs_array_muxed25 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed26 <= 1'd0; case (litedramcore_roundrobin4_grant) default: begin rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed27 <= 23'd0; case (litedramcore_roundrobin5_grant) default: begin rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed28 <= 1'd0; case (litedramcore_roundrobin5_grant) default: begin rhs_array_muxed28 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed29 <= 1'd0; case (litedramcore_roundrobin5_grant) default: begin rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed30 <= 23'd0; case (litedramcore_roundrobin6_grant) default: begin rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed31 <= 1'd0; case (litedramcore_roundrobin6_grant) default: begin rhs_array_muxed31 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed32 <= 1'd0; case (litedramcore_roundrobin6_grant) default: begin rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed33 <= 23'd0; case (litedramcore_roundrobin7_grant) default: begin rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; end endcase end always @(*) begin rhs_array_muxed34 <= 1'd0; case (litedramcore_roundrobin7_grant) default: begin rhs_array_muxed34 <= user_port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed35 <= 1'd0; case (litedramcore_roundrobin7_grant) default: begin rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); end endcase end always @(*) begin array_muxed0 <= 3'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed0 <= litedramcore_nop_ba[2:0]; end 1'd1: begin array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed1 <= 16'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed1 <= litedramcore_nop_a; end 1'd1: begin array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed1 <= litedramcore_choose_req_cmd_payload_a; end default: begin array_muxed1 <= litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed2 <= 1'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed2 <= 1'd0; end 1'd1: begin array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed3 <= 1'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed3 <= 1'd0; end 1'd1: begin array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed4 <= 1'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed4 <= 1'd0; end 1'd1: begin array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed5 <= 1'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed5 <= 1'd0; end 1'd1: begin array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed6 <= 1'd0; case (litedramcore_steerer_sel0) 1'd0: begin array_muxed6 <= 1'd0; end 1'd1: begin array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end always @(*) begin array_muxed7 <= 3'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed7 <= litedramcore_nop_ba[2:0]; end 1'd1: begin array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed8 <= 16'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed8 <= litedramcore_nop_a; end 1'd1: begin array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed8 <= litedramcore_choose_req_cmd_payload_a; end default: begin array_muxed8 <= litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed9 <= 1'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed9 <= 1'd0; end 1'd1: begin array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed10 <= 1'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed10 <= 1'd0; end 1'd1: begin array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed11 <= 1'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed11 <= 1'd0; end 1'd1: begin array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed12 <= 1'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed12 <= 1'd0; end 1'd1: begin array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed13 <= 1'd0; case (litedramcore_steerer_sel1) 1'd0: begin array_muxed13 <= 1'd0; end 1'd1: begin array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end always @(*) begin array_muxed14 <= 3'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed14 <= litedramcore_nop_ba[2:0]; end 1'd1: begin array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed15 <= 16'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed15 <= litedramcore_nop_a; end 1'd1: begin array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed15 <= litedramcore_choose_req_cmd_payload_a; end default: begin array_muxed15 <= litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed16 <= 1'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed16 <= 1'd0; end 1'd1: begin array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed17 <= 1'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed17 <= 1'd0; end 1'd1: begin array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed18 <= 1'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed18 <= 1'd0; end 1'd1: begin array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed19 <= 1'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed19 <= 1'd0; end 1'd1: begin array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed20 <= 1'd0; case (litedramcore_steerer_sel2) 1'd0: begin array_muxed20 <= 1'd0; end 1'd1: begin array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end always @(*) begin array_muxed21 <= 3'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed21 <= litedramcore_nop_ba[2:0]; end 1'd1: begin array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; end 2'd2: begin array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; end default: begin array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; end endcase end always @(*) begin array_muxed22 <= 16'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed22 <= litedramcore_nop_a; end 1'd1: begin array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; end 2'd2: begin array_muxed22 <= litedramcore_choose_req_cmd_payload_a; end default: begin array_muxed22 <= litedramcore_cmd_payload_a; end endcase end always @(*) begin array_muxed23 <= 1'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed23 <= 1'd0; end 1'd1: begin array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); end 2'd2: begin array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); end default: begin array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); end endcase end always @(*) begin array_muxed24 <= 1'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed24 <= 1'd0; end 1'd1: begin array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); end 2'd2: begin array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); end default: begin array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); end endcase end always @(*) begin array_muxed25 <= 1'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed25 <= 1'd0; end 1'd1: begin array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); end 2'd2: begin array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); end default: begin array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); end endcase end always @(*) begin array_muxed26 <= 1'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed26 <= 1'd0; end 1'd1: begin array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); end 2'd2: begin array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); end default: begin array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); end endcase end always @(*) begin array_muxed27 <= 1'd0; case (litedramcore_steerer_sel3) 1'd0: begin array_muxed27 <= 1'd0; end 1'd1: begin array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); end 2'd2: begin array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); end default: begin array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); end endcase end assign xilinxasyncresetsynchronizerimpl0 = (~locked); assign xilinxasyncresetsynchronizerimpl1 = (~locked); assign xilinxasyncresetsynchronizerimpl2 = (~locked); assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ // Synchronous Logic //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin if ((reset_counter != 1'd0)) begin reset_counter <= (reset_counter - 1'd1); end else begin ic_reset <= 1'd0; end if (iodelay_rst) begin reset_counter <= 4'd15; ic_reset <= 1'd1; end end always @(posedge sys_clk) begin a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value0 <= 3'd7; end a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value0 <= 3'd7; end a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value1 <= 3'd7; end a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value1 <= 3'd7; end a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value2 <= 3'd7; end a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip0_value3 <= 3'd7; end a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value2 <= 3'd7; end a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip1_value3 <= 3'd7; end a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip2_value0 <= 3'd7; end a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip2_value1 <= 3'd7; end a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip3_value0 <= 3'd7; end a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip3_value1 <= 3'd7; end a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip4_value0 <= 3'd7; end a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip4_value1 <= 3'd7; end a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip5_value0 <= 3'd7; end a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip5_value1 <= 3'd7; end a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip6_value0 <= 3'd7; end a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip6_value1 <= 3'd7; end a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip7_value0 <= 3'd7; end a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip7_value1 <= 3'd7; end a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip8_value0 <= 3'd7; end a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip8_value1 <= 3'd7; end a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip9_value0 <= 3'd7; end a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip9_value1 <= 3'd7; end a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip10_value0 <= 3'd7; end a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip10_value1 <= 3'd7; end a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip11_value0 <= 3'd7; end a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip11_value1 <= 3'd7; end a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip12_value0 <= 3'd7; end a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip12_value1 <= 3'd7; end a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip13_value0 <= 3'd7; end a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip13_value1 <= 3'd7; end a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip14_value0 <= 3'd7; end a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip14_value1 <= 3'd7; end a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip15_value0 <= 3'd7; end a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); end if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin a7ddrphy_bitslip15_value1 <= 3'd7; end a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; if (litedramcore_csr_dfi_p0_rddata_valid) begin litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; end if (litedramcore_csr_dfi_p1_rddata_valid) begin litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; end if (litedramcore_csr_dfi_p2_rddata_valid) begin litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; end if (litedramcore_csr_dfi_p3_rddata_valid) begin litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; end if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); end else begin litedramcore_timer_count1 <= 10'd781; end litedramcore_postponer_req_o <= 1'd0; if (litedramcore_postponer_req_i) begin litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); if ((litedramcore_postponer_count == 1'd0)) begin litedramcore_postponer_count <= 1'd0; litedramcore_postponer_req_o <= 1'd1; end end if (litedramcore_sequencer_start0) begin litedramcore_sequencer_count <= 1'd0; end else begin if (litedramcore_sequencer_done1) begin if ((litedramcore_sequencer_count != 1'd0)) begin litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); end end end litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd0; litedramcore_sequencer_done1 <= 1'd0; if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin litedramcore_cmd_payload_a <= 11'd1024; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd1; litedramcore_cmd_payload_we <= 1'd1; end if ((litedramcore_sequencer_counter == 2'd3)) begin litedramcore_cmd_payload_a <= 11'd1024; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd1; litedramcore_cmd_payload_ras <= 1'd1; litedramcore_cmd_payload_we <= 1'd0; end if ((litedramcore_sequencer_counter == 7'd73)) begin litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd0; litedramcore_sequencer_done1 <= 1'd1; end if ((litedramcore_sequencer_counter == 7'd73)) begin litedramcore_sequencer_counter <= 1'd0; end else begin if ((litedramcore_sequencer_counter != 1'd0)) begin litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); end else begin if (litedramcore_sequencer_start1) begin litedramcore_sequencer_counter <= 1'd1; end end end if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); end else begin litedramcore_zqcs_timer_count1 <= 27'd99999999; end litedramcore_zqcs_executer_done <= 1'd0; if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin litedramcore_cmd_payload_a <= 11'd1024; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd1; litedramcore_cmd_payload_we <= 1'd1; end if ((litedramcore_zqcs_executer_counter == 2'd3)) begin litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd1; end if ((litedramcore_zqcs_executer_counter == 5'd19)) begin litedramcore_cmd_payload_a <= 1'd0; litedramcore_cmd_payload_ba <= 1'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd0; litedramcore_zqcs_executer_done <= 1'd1; end if ((litedramcore_zqcs_executer_counter == 5'd19)) begin litedramcore_zqcs_executer_counter <= 1'd0; end else begin if ((litedramcore_zqcs_executer_counter != 1'd0)) begin litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); end else begin if (litedramcore_zqcs_executer_start) begin litedramcore_zqcs_executer_counter <= 1'd1; end end end litedramcore_refresher_state <= litedramcore_refresher_next_state; if (litedramcore_bankmachine0_row_close) begin litedramcore_bankmachine0_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine0_row_open) begin litedramcore_bankmachine0_row_opened <= 1'd1; litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); end if (litedramcore_bankmachine0_do_read) begin litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); end if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin if ((~litedramcore_bankmachine0_do_read)) begin litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); end end else begin if (litedramcore_bankmachine0_do_read) begin litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); end end if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine0_twtpcon_valid) begin litedramcore_bankmachine0_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine0_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine0_twtpcon_ready)) begin litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin litedramcore_bankmachine0_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine0_trccon_valid) begin litedramcore_bankmachine0_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine0_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine0_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine0_trccon_ready)) begin litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin litedramcore_bankmachine0_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine0_trascon_valid) begin litedramcore_bankmachine0_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine0_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine0_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine0_trascon_ready)) begin litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin litedramcore_bankmachine0_trascon_ready <= 1'd1; end end end litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; if (litedramcore_bankmachine1_row_close) begin litedramcore_bankmachine1_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine1_row_open) begin litedramcore_bankmachine1_row_opened <= 1'd1; litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); end if (litedramcore_bankmachine1_do_read) begin litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); end if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin if ((~litedramcore_bankmachine1_do_read)) begin litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); end end else begin if (litedramcore_bankmachine1_do_read) begin litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); end end if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine1_twtpcon_valid) begin litedramcore_bankmachine1_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine1_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine1_twtpcon_ready)) begin litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin litedramcore_bankmachine1_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine1_trccon_valid) begin litedramcore_bankmachine1_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine1_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine1_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine1_trccon_ready)) begin litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin litedramcore_bankmachine1_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine1_trascon_valid) begin litedramcore_bankmachine1_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine1_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine1_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine1_trascon_ready)) begin litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin litedramcore_bankmachine1_trascon_ready <= 1'd1; end end end litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; if (litedramcore_bankmachine2_row_close) begin litedramcore_bankmachine2_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine2_row_open) begin litedramcore_bankmachine2_row_opened <= 1'd1; litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); end if (litedramcore_bankmachine2_do_read) begin litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); end if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin if ((~litedramcore_bankmachine2_do_read)) begin litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); end end else begin if (litedramcore_bankmachine2_do_read) begin litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); end end if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine2_twtpcon_valid) begin litedramcore_bankmachine2_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine2_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine2_twtpcon_ready)) begin litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin litedramcore_bankmachine2_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine2_trccon_valid) begin litedramcore_bankmachine2_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine2_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine2_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine2_trccon_ready)) begin litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin litedramcore_bankmachine2_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine2_trascon_valid) begin litedramcore_bankmachine2_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine2_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine2_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine2_trascon_ready)) begin litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin litedramcore_bankmachine2_trascon_ready <= 1'd1; end end end litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; if (litedramcore_bankmachine3_row_close) begin litedramcore_bankmachine3_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine3_row_open) begin litedramcore_bankmachine3_row_opened <= 1'd1; litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); end if (litedramcore_bankmachine3_do_read) begin litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); end if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin if ((~litedramcore_bankmachine3_do_read)) begin litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); end end else begin if (litedramcore_bankmachine3_do_read) begin litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); end end if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine3_twtpcon_valid) begin litedramcore_bankmachine3_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine3_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine3_twtpcon_ready)) begin litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin litedramcore_bankmachine3_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine3_trccon_valid) begin litedramcore_bankmachine3_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine3_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine3_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine3_trccon_ready)) begin litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin litedramcore_bankmachine3_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine3_trascon_valid) begin litedramcore_bankmachine3_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine3_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine3_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine3_trascon_ready)) begin litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin litedramcore_bankmachine3_trascon_ready <= 1'd1; end end end litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; if (litedramcore_bankmachine4_row_close) begin litedramcore_bankmachine4_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine4_row_open) begin litedramcore_bankmachine4_row_opened <= 1'd1; litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); end if (litedramcore_bankmachine4_do_read) begin litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); end if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin if ((~litedramcore_bankmachine4_do_read)) begin litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); end end else begin if (litedramcore_bankmachine4_do_read) begin litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); end end if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine4_twtpcon_valid) begin litedramcore_bankmachine4_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine4_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine4_twtpcon_ready)) begin litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin litedramcore_bankmachine4_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine4_trccon_valid) begin litedramcore_bankmachine4_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine4_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine4_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine4_trccon_ready)) begin litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin litedramcore_bankmachine4_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine4_trascon_valid) begin litedramcore_bankmachine4_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine4_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine4_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine4_trascon_ready)) begin litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin litedramcore_bankmachine4_trascon_ready <= 1'd1; end end end litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; if (litedramcore_bankmachine5_row_close) begin litedramcore_bankmachine5_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine5_row_open) begin litedramcore_bankmachine5_row_opened <= 1'd1; litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); end if (litedramcore_bankmachine5_do_read) begin litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); end if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin if ((~litedramcore_bankmachine5_do_read)) begin litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); end end else begin if (litedramcore_bankmachine5_do_read) begin litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); end end if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine5_twtpcon_valid) begin litedramcore_bankmachine5_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine5_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine5_twtpcon_ready)) begin litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin litedramcore_bankmachine5_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine5_trccon_valid) begin litedramcore_bankmachine5_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine5_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine5_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine5_trccon_ready)) begin litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin litedramcore_bankmachine5_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine5_trascon_valid) begin litedramcore_bankmachine5_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine5_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine5_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine5_trascon_ready)) begin litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin litedramcore_bankmachine5_trascon_ready <= 1'd1; end end end litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; if (litedramcore_bankmachine6_row_close) begin litedramcore_bankmachine6_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine6_row_open) begin litedramcore_bankmachine6_row_opened <= 1'd1; litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); end if (litedramcore_bankmachine6_do_read) begin litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); end if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin if ((~litedramcore_bankmachine6_do_read)) begin litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); end end else begin if (litedramcore_bankmachine6_do_read) begin litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); end end if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine6_twtpcon_valid) begin litedramcore_bankmachine6_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine6_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine6_twtpcon_ready)) begin litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin litedramcore_bankmachine6_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine6_trccon_valid) begin litedramcore_bankmachine6_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine6_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine6_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine6_trccon_ready)) begin litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin litedramcore_bankmachine6_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine6_trascon_valid) begin litedramcore_bankmachine6_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine6_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine6_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine6_trascon_ready)) begin litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin litedramcore_bankmachine6_trascon_ready <= 1'd1; end end end litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; if (litedramcore_bankmachine7_row_close) begin litedramcore_bankmachine7_row_opened <= 1'd0; end else begin if (litedramcore_bankmachine7_row_open) begin litedramcore_bankmachine7_row_opened <= 1'd1; litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[22:7]; end end if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); end if (litedramcore_bankmachine7_do_read) begin litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); end if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin if ((~litedramcore_bankmachine7_do_read)) begin litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); end end else begin if (litedramcore_bankmachine7_do_read) begin litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); end end if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; end if (litedramcore_bankmachine7_twtpcon_valid) begin litedramcore_bankmachine7_twtpcon_count <= 3'd5; if (1'd0) begin litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end else begin litedramcore_bankmachine7_twtpcon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine7_twtpcon_ready)) begin litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin litedramcore_bankmachine7_twtpcon_ready <= 1'd1; end end end if (litedramcore_bankmachine7_trccon_valid) begin litedramcore_bankmachine7_trccon_count <= 3'd6; if (1'd0) begin litedramcore_bankmachine7_trccon_ready <= 1'd1; end else begin litedramcore_bankmachine7_trccon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine7_trccon_ready)) begin litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin litedramcore_bankmachine7_trccon_ready <= 1'd1; end end end if (litedramcore_bankmachine7_trascon_valid) begin litedramcore_bankmachine7_trascon_count <= 3'd4; if (1'd0) begin litedramcore_bankmachine7_trascon_ready <= 1'd1; end else begin litedramcore_bankmachine7_trascon_ready <= 1'd0; end end else begin if ((~litedramcore_bankmachine7_trascon_ready)) begin litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin litedramcore_bankmachine7_trascon_ready <= 1'd1; end end end litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; if ((~litedramcore_en0)) begin litedramcore_time0 <= 5'd31; end else begin if ((~litedramcore_max_time0)) begin litedramcore_time0 <= (litedramcore_time0 - 1'd1); end end if ((~litedramcore_en1)) begin litedramcore_time1 <= 4'd15; end else begin if ((~litedramcore_max_time1)) begin litedramcore_time1 <= (litedramcore_time1 - 1'd1); end end if (litedramcore_choose_cmd_ce) begin case (litedramcore_choose_cmd_grant) 1'd0: begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end else begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end else begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end else begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end else begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end else begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end else begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end end end end end end end end 1'd1: begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end else begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end else begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end else begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end else begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end else begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end else begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end end end end end end end end 2'd2: begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end else begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end else begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end else begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end else begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end else begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end else begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end end end end end end end end 2'd3: begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end else begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end else begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end else begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end else begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end else begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end else begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end end end end end end end end 3'd4: begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end else begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end else begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end else begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end else begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end else begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end else begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end end end end end end end end 3'd5: begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end else begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end else begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end else begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end else begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end else begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end else begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end end end end end end end end 3'd6: begin if (litedramcore_choose_cmd_request[7]) begin litedramcore_choose_cmd_grant <= 3'd7; end else begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end else begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end else begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end else begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end else begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end else begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end end end end end end end end 3'd7: begin if (litedramcore_choose_cmd_request[0]) begin litedramcore_choose_cmd_grant <= 1'd0; end else begin if (litedramcore_choose_cmd_request[1]) begin litedramcore_choose_cmd_grant <= 1'd1; end else begin if (litedramcore_choose_cmd_request[2]) begin litedramcore_choose_cmd_grant <= 2'd2; end else begin if (litedramcore_choose_cmd_request[3]) begin litedramcore_choose_cmd_grant <= 2'd3; end else begin if (litedramcore_choose_cmd_request[4]) begin litedramcore_choose_cmd_grant <= 3'd4; end else begin if (litedramcore_choose_cmd_request[5]) begin litedramcore_choose_cmd_grant <= 3'd5; end else begin if (litedramcore_choose_cmd_request[6]) begin litedramcore_choose_cmd_grant <= 3'd6; end end end end end end end end endcase end if (litedramcore_choose_req_ce) begin case (litedramcore_choose_req_grant) 1'd0: begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end else begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end else begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end else begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end else begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end else begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end else begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end end end end end end end end 1'd1: begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end else begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end else begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end else begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end else begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end else begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end else begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end end end end end end end end 2'd2: begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end else begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end else begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end else begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end else begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end else begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end else begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end end end end end end end end 2'd3: begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end else begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end else begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end else begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end else begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end else begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end else begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end end end end end end end end 3'd4: begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end else begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end else begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end else begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end else begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end else begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end else begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end end end end end end end end 3'd5: begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end else begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end else begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end else begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end else begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end else begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end else begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end end end end end end end end 3'd6: begin if (litedramcore_choose_req_request[7]) begin litedramcore_choose_req_grant <= 3'd7; end else begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end else begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end else begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end else begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end else begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end else begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end end end end end end end end 3'd7: begin if (litedramcore_choose_req_request[0]) begin litedramcore_choose_req_grant <= 1'd0; end else begin if (litedramcore_choose_req_request[1]) begin litedramcore_choose_req_grant <= 1'd1; end else begin if (litedramcore_choose_req_request[2]) begin litedramcore_choose_req_grant <= 2'd2; end else begin if (litedramcore_choose_req_request[3]) begin litedramcore_choose_req_grant <= 2'd3; end else begin if (litedramcore_choose_req_request[4]) begin litedramcore_choose_req_grant <= 3'd4; end else begin if (litedramcore_choose_req_request[5]) begin litedramcore_choose_req_grant <= 3'd5; end else begin if (litedramcore_choose_req_request[6]) begin litedramcore_choose_req_grant <= 3'd6; end end end end end end end end endcase end litedramcore_dfi_p0_cs_n <= 1'd0; litedramcore_dfi_p0_bank <= array_muxed0; litedramcore_dfi_p0_address <= array_muxed1; litedramcore_dfi_p0_cas_n <= (~array_muxed2); litedramcore_dfi_p0_ras_n <= (~array_muxed3); litedramcore_dfi_p0_we_n <= (~array_muxed4); litedramcore_dfi_p0_rddata_en <= array_muxed5; litedramcore_dfi_p0_wrdata_en <= array_muxed6; litedramcore_dfi_p1_cs_n <= 1'd0; litedramcore_dfi_p1_bank <= array_muxed7; litedramcore_dfi_p1_address <= array_muxed8; litedramcore_dfi_p1_cas_n <= (~array_muxed9); litedramcore_dfi_p1_ras_n <= (~array_muxed10); litedramcore_dfi_p1_we_n <= (~array_muxed11); litedramcore_dfi_p1_rddata_en <= array_muxed12; litedramcore_dfi_p1_wrdata_en <= array_muxed13; litedramcore_dfi_p2_cs_n <= 1'd0; litedramcore_dfi_p2_bank <= array_muxed14; litedramcore_dfi_p2_address <= array_muxed15; litedramcore_dfi_p2_cas_n <= (~array_muxed16); litedramcore_dfi_p2_ras_n <= (~array_muxed17); litedramcore_dfi_p2_we_n <= (~array_muxed18); litedramcore_dfi_p2_rddata_en <= array_muxed19; litedramcore_dfi_p2_wrdata_en <= array_muxed20; litedramcore_dfi_p3_cs_n <= 1'd0; litedramcore_dfi_p3_bank <= array_muxed21; litedramcore_dfi_p3_address <= array_muxed22; litedramcore_dfi_p3_cas_n <= (~array_muxed23); litedramcore_dfi_p3_ras_n <= (~array_muxed24); litedramcore_dfi_p3_we_n <= (~array_muxed25); litedramcore_dfi_p3_rddata_en <= array_muxed26; litedramcore_dfi_p3_wrdata_en <= array_muxed27; if (litedramcore_trrdcon_valid) begin litedramcore_trrdcon_count <= 1'd1; if (1'd0) begin litedramcore_trrdcon_ready <= 1'd1; end else begin litedramcore_trrdcon_ready <= 1'd0; end end else begin if ((~litedramcore_trrdcon_ready)) begin litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); if ((litedramcore_trrdcon_count == 1'd1)) begin litedramcore_trrdcon_ready <= 1'd1; end end end litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; if ((litedramcore_tfawcon_count < 3'd4)) begin if ((litedramcore_tfawcon_count == 2'd3)) begin litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); end else begin litedramcore_tfawcon_ready <= 1'd1; end end if (litedramcore_tccdcon_valid) begin litedramcore_tccdcon_count <= 1'd0; if (1'd1) begin litedramcore_tccdcon_ready <= 1'd1; end else begin litedramcore_tccdcon_ready <= 1'd0; end end else begin if ((~litedramcore_tccdcon_ready)) begin litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); if ((litedramcore_tccdcon_count == 1'd1)) begin litedramcore_tccdcon_ready <= 1'd1; end end end if (litedramcore_twtrcon_valid) begin litedramcore_twtrcon_count <= 3'd4; if (1'd0) begin litedramcore_twtrcon_ready <= 1'd1; end else begin litedramcore_twtrcon_ready <= 1'd0; end end else begin if ((~litedramcore_twtrcon_ready)) begin litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); if ((litedramcore_twtrcon_count == 1'd1)) begin litedramcore_twtrcon_ready <= 1'd1; end end end litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; litedramcore_state <= litedramcore_next_state; if (litedramcore_dat_w_next_value_ce0) begin litedramcore_dat_w <= litedramcore_dat_w_next_value0; end if (litedramcore_adr_next_value_ce1) begin litedramcore_adr <= litedramcore_adr_next_value1; end if (litedramcore_we_next_value_ce2) begin litedramcore_we <= litedramcore_we_next_value2; end interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin case (interface0_bank_bus_adr[8:0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end 1'd1: begin interface0_bank_bus_dat_r <= csrbank0_init_error0_w; end endcase end if (csrbank0_init_done0_re) begin init_done_storage <= csrbank0_init_done0_r; end init_done_re <= csrbank0_init_done0_re; if (csrbank0_init_error0_re) begin init_error_storage <= csrbank0_init_error0_r; end init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin case (interface1_bank_bus_adr[8:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_rst0_w; end 1'd1: begin interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; end 2'd2: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end 2'd3: begin interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; end 3'd4: begin interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; end 3'd5: begin interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; end 3'd6: begin interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; end 3'd7: begin interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; end 4'd8: begin interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; end 4'd9: begin interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; end 4'd10: begin interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; end 4'd11: begin interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; end 4'd12: begin interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; end endcase end if (csrbank1_rst0_re) begin a7ddrphy_rst_storage <= csrbank1_rst0_r; end a7ddrphy_rst_re <= csrbank1_rst0_re; if (csrbank1_dly_sel0_re) begin a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; end a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; if (csrbank1_half_sys8x_taps0_re) begin a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; end a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; if (csrbank1_wlevel_en0_re) begin a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; end a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; if (csrbank1_rdphase0_re) begin a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; end a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; if (csrbank1_wrphase0_re) begin a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; end a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin case (interface2_bank_bus_adr[8:0]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end 1'd1: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; end 2'd2: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; end 2'd3: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; end 3'd4: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; end 3'd5: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; end 3'd6: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; end 3'd7: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; end 4'd8: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; end 4'd9: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; end 4'd10: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; end 4'd11: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; end 4'd12: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; end 4'd13: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; end 4'd14: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; end 4'd15: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; end 5'd16: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; end 5'd17: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; end 5'd18: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; end 5'd19: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; end 5'd20: begin interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; end 5'd21: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; end 5'd22: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; end 5'd23: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; end 5'd24: begin interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; end endcase end if (csrbank2_dfii_control0_re) begin litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; end litedramcore_re <= csrbank2_dfii_control0_re; if (csrbank2_dfii_pi0_command0_re) begin litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; end litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; if (csrbank2_dfii_pi0_address0_re) begin litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r; end litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; if (csrbank2_dfii_pi0_baddress0_re) begin litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; end litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; if (csrbank2_dfii_pi0_wrdata0_re) begin litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; end litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; if (csrbank2_dfii_pi1_command0_re) begin litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; end litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; if (csrbank2_dfii_pi1_address0_re) begin litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r; end litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; if (csrbank2_dfii_pi1_baddress0_re) begin litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; end litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; if (csrbank2_dfii_pi1_wrdata0_re) begin litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; end litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; if (csrbank2_dfii_pi2_command0_re) begin litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; end litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; if (csrbank2_dfii_pi2_address0_re) begin litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r; end litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; if (csrbank2_dfii_pi2_baddress0_re) begin litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; end litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; if (csrbank2_dfii_pi2_wrdata0_re) begin litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; end litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; if (csrbank2_dfii_pi3_command0_re) begin litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; end litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; if (csrbank2_dfii_pi3_address0_re) begin litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r; end litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; if (csrbank2_dfii_pi3_baddress0_re) begin litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; end litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; if (csrbank2_dfii_pi3_wrdata0_re) begin litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; end litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; if (sys_rst) begin a7ddrphy_rst_storage <= 1'd0; a7ddrphy_rst_re <= 1'd0; a7ddrphy_dly_sel_storage <= 2'd0; a7ddrphy_dly_sel_re <= 1'd0; a7ddrphy_half_sys8x_taps_storage <= 5'd8; a7ddrphy_half_sys8x_taps_re <= 1'd0; a7ddrphy_wlevel_en_storage <= 1'd0; a7ddrphy_wlevel_en_re <= 1'd0; a7ddrphy_rdphase_storage <= 2'd2; a7ddrphy_rdphase_re <= 1'd0; a7ddrphy_wrphase_storage <= 2'd3; a7ddrphy_wrphase_re <= 1'd0; a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; a7ddrphy_dqspattern_o1 <= 8'd0; a7ddrphy_bitslip0_value0 <= 3'd7; a7ddrphy_bitslip1_value0 <= 3'd7; a7ddrphy_bitslip0_value1 <= 3'd7; a7ddrphy_bitslip1_value1 <= 3'd7; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; a7ddrphy_bitslip0_value2 <= 3'd7; a7ddrphy_bitslip0_value3 <= 3'd7; a7ddrphy_bitslip1_value2 <= 3'd7; a7ddrphy_bitslip1_value3 <= 3'd7; a7ddrphy_bitslip2_value0 <= 3'd7; a7ddrphy_bitslip2_value1 <= 3'd7; a7ddrphy_bitslip3_value0 <= 3'd7; a7ddrphy_bitslip3_value1 <= 3'd7; a7ddrphy_bitslip4_value0 <= 3'd7; a7ddrphy_bitslip4_value1 <= 3'd7; a7ddrphy_bitslip5_value0 <= 3'd7; a7ddrphy_bitslip5_value1 <= 3'd7; a7ddrphy_bitslip6_value0 <= 3'd7; a7ddrphy_bitslip6_value1 <= 3'd7; a7ddrphy_bitslip7_value0 <= 3'd7; a7ddrphy_bitslip7_value1 <= 3'd7; a7ddrphy_bitslip8_value0 <= 3'd7; a7ddrphy_bitslip8_value1 <= 3'd7; a7ddrphy_bitslip9_value0 <= 3'd7; a7ddrphy_bitslip9_value1 <= 3'd7; a7ddrphy_bitslip10_value0 <= 3'd7; a7ddrphy_bitslip10_value1 <= 3'd7; a7ddrphy_bitslip11_value0 <= 3'd7; a7ddrphy_bitslip11_value1 <= 3'd7; a7ddrphy_bitslip12_value0 <= 3'd7; a7ddrphy_bitslip12_value1 <= 3'd7; a7ddrphy_bitslip13_value0 <= 3'd7; a7ddrphy_bitslip13_value1 <= 3'd7; a7ddrphy_bitslip14_value0 <= 3'd7; a7ddrphy_bitslip14_value1 <= 3'd7; a7ddrphy_bitslip15_value0 <= 3'd7; a7ddrphy_bitslip15_value1 <= 3'd7; a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; litedramcore_storage <= 4'd1; litedramcore_re <= 1'd0; litedramcore_phaseinjector0_command_storage <= 6'd0; litedramcore_phaseinjector0_command_re <= 1'd0; litedramcore_phaseinjector0_address_re <= 1'd0; litedramcore_phaseinjector0_baddress_re <= 1'd0; litedramcore_phaseinjector0_wrdata_re <= 1'd0; litedramcore_phaseinjector0_rddata_status <= 32'd0; litedramcore_phaseinjector0_rddata_re <= 1'd0; litedramcore_phaseinjector1_command_storage <= 6'd0; litedramcore_phaseinjector1_command_re <= 1'd0; litedramcore_phaseinjector1_address_re <= 1'd0; litedramcore_phaseinjector1_baddress_re <= 1'd0; litedramcore_phaseinjector1_wrdata_re <= 1'd0; litedramcore_phaseinjector1_rddata_status <= 32'd0; litedramcore_phaseinjector1_rddata_re <= 1'd0; litedramcore_phaseinjector2_command_storage <= 6'd0; litedramcore_phaseinjector2_command_re <= 1'd0; litedramcore_phaseinjector2_address_re <= 1'd0; litedramcore_phaseinjector2_baddress_re <= 1'd0; litedramcore_phaseinjector2_wrdata_re <= 1'd0; litedramcore_phaseinjector2_rddata_status <= 32'd0; litedramcore_phaseinjector2_rddata_re <= 1'd0; litedramcore_phaseinjector3_command_storage <= 6'd0; litedramcore_phaseinjector3_command_re <= 1'd0; litedramcore_phaseinjector3_address_re <= 1'd0; litedramcore_phaseinjector3_baddress_re <= 1'd0; litedramcore_phaseinjector3_wrdata_re <= 1'd0; litedramcore_phaseinjector3_rddata_status <= 32'd0; litedramcore_phaseinjector3_rddata_re <= 1'd0; litedramcore_dfi_p0_address <= 16'd0; litedramcore_dfi_p0_bank <= 3'd0; litedramcore_dfi_p0_cas_n <= 1'd1; litedramcore_dfi_p0_cs_n <= 1'd1; litedramcore_dfi_p0_ras_n <= 1'd1; litedramcore_dfi_p0_we_n <= 1'd1; litedramcore_dfi_p0_wrdata_en <= 1'd0; litedramcore_dfi_p0_rddata_en <= 1'd0; litedramcore_dfi_p1_address <= 16'd0; litedramcore_dfi_p1_bank <= 3'd0; litedramcore_dfi_p1_cas_n <= 1'd1; litedramcore_dfi_p1_cs_n <= 1'd1; litedramcore_dfi_p1_ras_n <= 1'd1; litedramcore_dfi_p1_we_n <= 1'd1; litedramcore_dfi_p1_wrdata_en <= 1'd0; litedramcore_dfi_p1_rddata_en <= 1'd0; litedramcore_dfi_p2_address <= 16'd0; litedramcore_dfi_p2_bank <= 3'd0; litedramcore_dfi_p2_cas_n <= 1'd1; litedramcore_dfi_p2_cs_n <= 1'd1; litedramcore_dfi_p2_ras_n <= 1'd1; litedramcore_dfi_p2_we_n <= 1'd1; litedramcore_dfi_p2_wrdata_en <= 1'd0; litedramcore_dfi_p2_rddata_en <= 1'd0; litedramcore_dfi_p3_address <= 16'd0; litedramcore_dfi_p3_bank <= 3'd0; litedramcore_dfi_p3_cas_n <= 1'd1; litedramcore_dfi_p3_cs_n <= 1'd1; litedramcore_dfi_p3_ras_n <= 1'd1; litedramcore_dfi_p3_we_n <= 1'd1; litedramcore_dfi_p3_wrdata_en <= 1'd0; litedramcore_dfi_p3_rddata_en <= 1'd0; litedramcore_cmd_payload_a <= 16'd0; litedramcore_cmd_payload_ba <= 3'd0; litedramcore_cmd_payload_cas <= 1'd0; litedramcore_cmd_payload_ras <= 1'd0; litedramcore_cmd_payload_we <= 1'd0; litedramcore_timer_count1 <= 10'd781; litedramcore_postponer_req_o <= 1'd0; litedramcore_postponer_count <= 1'd0; litedramcore_sequencer_done1 <= 1'd0; litedramcore_sequencer_counter <= 7'd0; litedramcore_sequencer_count <= 1'd0; litedramcore_zqcs_timer_count1 <= 27'd99999999; litedramcore_zqcs_executer_done <= 1'd0; litedramcore_zqcs_executer_counter <= 5'd0; litedramcore_bankmachine0_level <= 5'd0; litedramcore_bankmachine0_produce <= 4'd0; litedramcore_bankmachine0_consume <= 4'd0; litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine0_row <= 16'd0; litedramcore_bankmachine0_row_opened <= 1'd0; litedramcore_bankmachine0_twtpcon_ready <= 1'd0; litedramcore_bankmachine0_twtpcon_count <= 3'd0; litedramcore_bankmachine0_trccon_ready <= 1'd0; litedramcore_bankmachine0_trccon_count <= 3'd0; litedramcore_bankmachine0_trascon_ready <= 1'd0; litedramcore_bankmachine0_trascon_count <= 3'd0; litedramcore_bankmachine1_level <= 5'd0; litedramcore_bankmachine1_produce <= 4'd0; litedramcore_bankmachine1_consume <= 4'd0; litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine1_row <= 16'd0; litedramcore_bankmachine1_row_opened <= 1'd0; litedramcore_bankmachine1_twtpcon_ready <= 1'd0; litedramcore_bankmachine1_twtpcon_count <= 3'd0; litedramcore_bankmachine1_trccon_ready <= 1'd0; litedramcore_bankmachine1_trccon_count <= 3'd0; litedramcore_bankmachine1_trascon_ready <= 1'd0; litedramcore_bankmachine1_trascon_count <= 3'd0; litedramcore_bankmachine2_level <= 5'd0; litedramcore_bankmachine2_produce <= 4'd0; litedramcore_bankmachine2_consume <= 4'd0; litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine2_row <= 16'd0; litedramcore_bankmachine2_row_opened <= 1'd0; litedramcore_bankmachine2_twtpcon_ready <= 1'd0; litedramcore_bankmachine2_twtpcon_count <= 3'd0; litedramcore_bankmachine2_trccon_ready <= 1'd0; litedramcore_bankmachine2_trccon_count <= 3'd0; litedramcore_bankmachine2_trascon_ready <= 1'd0; litedramcore_bankmachine2_trascon_count <= 3'd0; litedramcore_bankmachine3_level <= 5'd0; litedramcore_bankmachine3_produce <= 4'd0; litedramcore_bankmachine3_consume <= 4'd0; litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine3_row <= 16'd0; litedramcore_bankmachine3_row_opened <= 1'd0; litedramcore_bankmachine3_twtpcon_ready <= 1'd0; litedramcore_bankmachine3_twtpcon_count <= 3'd0; litedramcore_bankmachine3_trccon_ready <= 1'd0; litedramcore_bankmachine3_trccon_count <= 3'd0; litedramcore_bankmachine3_trascon_ready <= 1'd0; litedramcore_bankmachine3_trascon_count <= 3'd0; litedramcore_bankmachine4_level <= 5'd0; litedramcore_bankmachine4_produce <= 4'd0; litedramcore_bankmachine4_consume <= 4'd0; litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine4_row <= 16'd0; litedramcore_bankmachine4_row_opened <= 1'd0; litedramcore_bankmachine4_twtpcon_ready <= 1'd0; litedramcore_bankmachine4_twtpcon_count <= 3'd0; litedramcore_bankmachine4_trccon_ready <= 1'd0; litedramcore_bankmachine4_trccon_count <= 3'd0; litedramcore_bankmachine4_trascon_ready <= 1'd0; litedramcore_bankmachine4_trascon_count <= 3'd0; litedramcore_bankmachine5_level <= 5'd0; litedramcore_bankmachine5_produce <= 4'd0; litedramcore_bankmachine5_consume <= 4'd0; litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine5_row <= 16'd0; litedramcore_bankmachine5_row_opened <= 1'd0; litedramcore_bankmachine5_twtpcon_ready <= 1'd0; litedramcore_bankmachine5_twtpcon_count <= 3'd0; litedramcore_bankmachine5_trccon_ready <= 1'd0; litedramcore_bankmachine5_trccon_count <= 3'd0; litedramcore_bankmachine5_trascon_ready <= 1'd0; litedramcore_bankmachine5_trascon_count <= 3'd0; litedramcore_bankmachine6_level <= 5'd0; litedramcore_bankmachine6_produce <= 4'd0; litedramcore_bankmachine6_consume <= 4'd0; litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine6_row <= 16'd0; litedramcore_bankmachine6_row_opened <= 1'd0; litedramcore_bankmachine6_twtpcon_ready <= 1'd0; litedramcore_bankmachine6_twtpcon_count <= 3'd0; litedramcore_bankmachine6_trccon_ready <= 1'd0; litedramcore_bankmachine6_trccon_count <= 3'd0; litedramcore_bankmachine6_trascon_ready <= 1'd0; litedramcore_bankmachine6_trascon_count <= 3'd0; litedramcore_bankmachine7_level <= 5'd0; litedramcore_bankmachine7_produce <= 4'd0; litedramcore_bankmachine7_consume <= 4'd0; litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0; litedramcore_bankmachine7_row <= 16'd0; litedramcore_bankmachine7_row_opened <= 1'd0; litedramcore_bankmachine7_twtpcon_ready <= 1'd0; litedramcore_bankmachine7_twtpcon_count <= 3'd0; litedramcore_bankmachine7_trccon_ready <= 1'd0; litedramcore_bankmachine7_trccon_count <= 3'd0; litedramcore_bankmachine7_trascon_ready <= 1'd0; litedramcore_bankmachine7_trascon_count <= 3'd0; litedramcore_choose_cmd_grant <= 3'd0; litedramcore_choose_req_grant <= 3'd0; litedramcore_trrdcon_ready <= 1'd0; litedramcore_trrdcon_count <= 1'd0; litedramcore_tfawcon_ready <= 1'd1; litedramcore_tfawcon_window <= 5'd0; litedramcore_tccdcon_ready <= 1'd0; litedramcore_tccdcon_count <= 1'd0; litedramcore_twtrcon_ready <= 1'd0; litedramcore_twtrcon_count <= 3'd0; litedramcore_time0 <= 5'd0; litedramcore_time1 <= 4'd0; init_done_storage <= 1'd0; init_done_re <= 1'd0; init_error_storage <= 1'd0; init_error_re <= 1'd0; litedramcore_we <= 1'd0; litedramcore_refresher_state <= 2'd0; litedramcore_bankmachine0_state <= 4'd0; litedramcore_bankmachine1_state <= 4'd0; litedramcore_bankmachine2_state <= 4'd0; litedramcore_bankmachine3_state <= 4'd0; litedramcore_bankmachine4_state <= 4'd0; litedramcore_bankmachine5_state <= 4'd0; litedramcore_bankmachine6_state <= 4'd0; litedramcore_bankmachine7_state <= 4'd0; litedramcore_multiplexer_state <= 4'd0; litedramcore_new_master_wdata_ready0 <= 1'd0; litedramcore_new_master_wdata_ready1 <= 1'd0; litedramcore_new_master_rdata_valid0 <= 1'd0; litedramcore_new_master_rdata_valid1 <= 1'd0; litedramcore_new_master_rdata_valid2 <= 1'd0; litedramcore_new_master_rdata_valid3 <= 1'd0; litedramcore_new_master_rdata_valid4 <= 1'd0; litedramcore_new_master_rdata_valid5 <= 1'd0; litedramcore_new_master_rdata_valid6 <= 1'd0; litedramcore_new_master_rdata_valid7 <= 1'd0; litedramcore_new_master_rdata_valid8 <= 1'd0; litedramcore_state <= 2'd0; end end //------------------------------------------------------------------------------ // Specialized Logic //------------------------------------------------------------------------------ BUFG BUFG( .I(clkout0), .O(clkout_buf0) ); BUFG BUFG_1( .I(clkout1), .O(clkout_buf1) ); BUFG BUFG_2( .I(clkout2), .O(clkout_buf2) ); BUFG BUFG_3( .I(clkout3), .O(clkout_buf3) ); IDELAYCTRL IDELAYCTRL( .REFCLK(iodelay_clk), .RST(ic_reset) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(1'd0), .D2(1'd1), .D3(1'd0), .D4(1'd1), .D5(1'd0), .D6(1'd1), .D7(1'd0), .D8(1'd1), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(a7ddrphy_sd_clk_se_nodelay) ); OBUFDS OBUFDS( .I(a7ddrphy_sd_clk_se_nodelay), .O(ddram_clk_p), .OB(ddram_clk_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_1 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_reset_n), .D2(a7ddrphy_dfi_p0_reset_n), .D3(a7ddrphy_dfi_p1_reset_n), .D4(a7ddrphy_dfi_p1_reset_n), .D5(a7ddrphy_dfi_p2_reset_n), .D6(a7ddrphy_dfi_p2_reset_n), .D7(a7ddrphy_dfi_p3_reset_n), .D8(a7ddrphy_dfi_p3_reset_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_reset_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_2 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_cs_n), .D2(a7ddrphy_dfi_p0_cs_n), .D3(a7ddrphy_dfi_p1_cs_n), .D4(a7ddrphy_dfi_p1_cs_n), .D5(a7ddrphy_dfi_p2_cs_n), .D6(a7ddrphy_dfi_p2_cs_n), .D7(a7ddrphy_dfi_p3_cs_n), .D8(a7ddrphy_dfi_p3_cs_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_cs_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_3 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[0]), .D2(a7ddrphy_dfi_p0_address[0]), .D3(a7ddrphy_dfi_p1_address[0]), .D4(a7ddrphy_dfi_p1_address[0]), .D5(a7ddrphy_dfi_p2_address[0]), .D6(a7ddrphy_dfi_p2_address[0]), .D7(a7ddrphy_dfi_p3_address[0]), .D8(a7ddrphy_dfi_p3_address[0]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_4 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[1]), .D2(a7ddrphy_dfi_p0_address[1]), .D3(a7ddrphy_dfi_p1_address[1]), .D4(a7ddrphy_dfi_p1_address[1]), .D5(a7ddrphy_dfi_p2_address[1]), .D6(a7ddrphy_dfi_p2_address[1]), .D7(a7ddrphy_dfi_p3_address[1]), .D8(a7ddrphy_dfi_p3_address[1]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_5 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[2]), .D2(a7ddrphy_dfi_p0_address[2]), .D3(a7ddrphy_dfi_p1_address[2]), .D4(a7ddrphy_dfi_p1_address[2]), .D5(a7ddrphy_dfi_p2_address[2]), .D6(a7ddrphy_dfi_p2_address[2]), .D7(a7ddrphy_dfi_p3_address[2]), .D8(a7ddrphy_dfi_p3_address[2]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[2]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_6 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[3]), .D2(a7ddrphy_dfi_p0_address[3]), .D3(a7ddrphy_dfi_p1_address[3]), .D4(a7ddrphy_dfi_p1_address[3]), .D5(a7ddrphy_dfi_p2_address[3]), .D6(a7ddrphy_dfi_p2_address[3]), .D7(a7ddrphy_dfi_p3_address[3]), .D8(a7ddrphy_dfi_p3_address[3]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[3]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_7 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[4]), .D2(a7ddrphy_dfi_p0_address[4]), .D3(a7ddrphy_dfi_p1_address[4]), .D4(a7ddrphy_dfi_p1_address[4]), .D5(a7ddrphy_dfi_p2_address[4]), .D6(a7ddrphy_dfi_p2_address[4]), .D7(a7ddrphy_dfi_p3_address[4]), .D8(a7ddrphy_dfi_p3_address[4]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[4]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_8 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[5]), .D2(a7ddrphy_dfi_p0_address[5]), .D3(a7ddrphy_dfi_p1_address[5]), .D4(a7ddrphy_dfi_p1_address[5]), .D5(a7ddrphy_dfi_p2_address[5]), .D6(a7ddrphy_dfi_p2_address[5]), .D7(a7ddrphy_dfi_p3_address[5]), .D8(a7ddrphy_dfi_p3_address[5]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[5]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_9 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[6]), .D2(a7ddrphy_dfi_p0_address[6]), .D3(a7ddrphy_dfi_p1_address[6]), .D4(a7ddrphy_dfi_p1_address[6]), .D5(a7ddrphy_dfi_p2_address[6]), .D6(a7ddrphy_dfi_p2_address[6]), .D7(a7ddrphy_dfi_p3_address[6]), .D8(a7ddrphy_dfi_p3_address[6]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[6]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_10 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[7]), .D2(a7ddrphy_dfi_p0_address[7]), .D3(a7ddrphy_dfi_p1_address[7]), .D4(a7ddrphy_dfi_p1_address[7]), .D5(a7ddrphy_dfi_p2_address[7]), .D6(a7ddrphy_dfi_p2_address[7]), .D7(a7ddrphy_dfi_p3_address[7]), .D8(a7ddrphy_dfi_p3_address[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[7]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_11 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[8]), .D2(a7ddrphy_dfi_p0_address[8]), .D3(a7ddrphy_dfi_p1_address[8]), .D4(a7ddrphy_dfi_p1_address[8]), .D5(a7ddrphy_dfi_p2_address[8]), .D6(a7ddrphy_dfi_p2_address[8]), .D7(a7ddrphy_dfi_p3_address[8]), .D8(a7ddrphy_dfi_p3_address[8]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[8]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_12 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[9]), .D2(a7ddrphy_dfi_p0_address[9]), .D3(a7ddrphy_dfi_p1_address[9]), .D4(a7ddrphy_dfi_p1_address[9]), .D5(a7ddrphy_dfi_p2_address[9]), .D6(a7ddrphy_dfi_p2_address[9]), .D7(a7ddrphy_dfi_p3_address[9]), .D8(a7ddrphy_dfi_p3_address[9]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[9]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_13 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[10]), .D2(a7ddrphy_dfi_p0_address[10]), .D3(a7ddrphy_dfi_p1_address[10]), .D4(a7ddrphy_dfi_p1_address[10]), .D5(a7ddrphy_dfi_p2_address[10]), .D6(a7ddrphy_dfi_p2_address[10]), .D7(a7ddrphy_dfi_p3_address[10]), .D8(a7ddrphy_dfi_p3_address[10]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[10]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_14 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[11]), .D2(a7ddrphy_dfi_p0_address[11]), .D3(a7ddrphy_dfi_p1_address[11]), .D4(a7ddrphy_dfi_p1_address[11]), .D5(a7ddrphy_dfi_p2_address[11]), .D6(a7ddrphy_dfi_p2_address[11]), .D7(a7ddrphy_dfi_p3_address[11]), .D8(a7ddrphy_dfi_p3_address[11]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[11]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_15 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[12]), .D2(a7ddrphy_dfi_p0_address[12]), .D3(a7ddrphy_dfi_p1_address[12]), .D4(a7ddrphy_dfi_p1_address[12]), .D5(a7ddrphy_dfi_p2_address[12]), .D6(a7ddrphy_dfi_p2_address[12]), .D7(a7ddrphy_dfi_p3_address[12]), .D8(a7ddrphy_dfi_p3_address[12]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[12]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_16 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[13]), .D2(a7ddrphy_dfi_p0_address[13]), .D3(a7ddrphy_dfi_p1_address[13]), .D4(a7ddrphy_dfi_p1_address[13]), .D5(a7ddrphy_dfi_p2_address[13]), .D6(a7ddrphy_dfi_p2_address[13]), .D7(a7ddrphy_dfi_p3_address[13]), .D8(a7ddrphy_dfi_p3_address[13]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[13]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_17 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[14]), .D2(a7ddrphy_dfi_p0_address[14]), .D3(a7ddrphy_dfi_p1_address[14]), .D4(a7ddrphy_dfi_p1_address[14]), .D5(a7ddrphy_dfi_p2_address[14]), .D6(a7ddrphy_dfi_p2_address[14]), .D7(a7ddrphy_dfi_p3_address[14]), .D8(a7ddrphy_dfi_p3_address[14]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[14]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_18 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_address[15]), .D2(a7ddrphy_dfi_p0_address[15]), .D3(a7ddrphy_dfi_p1_address[15]), .D4(a7ddrphy_dfi_p1_address[15]), .D5(a7ddrphy_dfi_p2_address[15]), .D6(a7ddrphy_dfi_p2_address[15]), .D7(a7ddrphy_dfi_p3_address[15]), .D8(a7ddrphy_dfi_p3_address[15]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_a[15]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_19 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_bank[0]), .D2(a7ddrphy_dfi_p0_bank[0]), .D3(a7ddrphy_dfi_p1_bank[0]), .D4(a7ddrphy_dfi_p1_bank[0]), .D5(a7ddrphy_dfi_p2_bank[0]), .D6(a7ddrphy_dfi_p2_bank[0]), .D7(a7ddrphy_dfi_p3_bank[0]), .D8(a7ddrphy_dfi_p3_bank[0]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(a7ddrphy_pads_ba[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_20 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_bank[1]), .D2(a7ddrphy_dfi_p0_bank[1]), .D3(a7ddrphy_dfi_p1_bank[1]), .D4(a7ddrphy_dfi_p1_bank[1]), .D5(a7ddrphy_dfi_p2_bank[1]), .D6(a7ddrphy_dfi_p2_bank[1]), .D7(a7ddrphy_dfi_p3_bank[1]), .D8(a7ddrphy_dfi_p3_bank[1]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(a7ddrphy_pads_ba[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_21 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_bank[2]), .D2(a7ddrphy_dfi_p0_bank[2]), .D3(a7ddrphy_dfi_p1_bank[2]), .D4(a7ddrphy_dfi_p1_bank[2]), .D5(a7ddrphy_dfi_p2_bank[2]), .D6(a7ddrphy_dfi_p2_bank[2]), .D7(a7ddrphy_dfi_p3_bank[2]), .D8(a7ddrphy_dfi_p3_bank[2]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(a7ddrphy_pads_ba[2]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_22 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_ras_n), .D2(a7ddrphy_dfi_p0_ras_n), .D3(a7ddrphy_dfi_p1_ras_n), .D4(a7ddrphy_dfi_p1_ras_n), .D5(a7ddrphy_dfi_p2_ras_n), .D6(a7ddrphy_dfi_p2_ras_n), .D7(a7ddrphy_dfi_p3_ras_n), .D8(a7ddrphy_dfi_p3_ras_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_ras_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_23 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_cas_n), .D2(a7ddrphy_dfi_p0_cas_n), .D3(a7ddrphy_dfi_p1_cas_n), .D4(a7ddrphy_dfi_p1_cas_n), .D5(a7ddrphy_dfi_p2_cas_n), .D6(a7ddrphy_dfi_p2_cas_n), .D7(a7ddrphy_dfi_p3_cas_n), .D8(a7ddrphy_dfi_p3_cas_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_cas_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_24 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_we_n), .D2(a7ddrphy_dfi_p0_we_n), .D3(a7ddrphy_dfi_p1_we_n), .D4(a7ddrphy_dfi_p1_we_n), .D5(a7ddrphy_dfi_p2_we_n), .D6(a7ddrphy_dfi_p2_we_n), .D7(a7ddrphy_dfi_p3_we_n), .D8(a7ddrphy_dfi_p3_we_n), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_we_n) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_25 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_cke), .D2(a7ddrphy_dfi_p0_cke), .D3(a7ddrphy_dfi_p1_cke), .D4(a7ddrphy_dfi_p1_cke), .D5(a7ddrphy_dfi_p2_cke), .D6(a7ddrphy_dfi_p2_cke), .D7(a7ddrphy_dfi_p3_cke), .D8(a7ddrphy_dfi_p3_cke), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_cke) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_26 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_dfi_p0_odt), .D2(a7ddrphy_dfi_p0_odt), .D3(a7ddrphy_dfi_p1_odt), .D4(a7ddrphy_dfi_p1_odt), .D5(a7ddrphy_dfi_p2_odt), .D6(a7ddrphy_dfi_p2_odt), .D7(a7ddrphy_dfi_p3_odt), .D8(a7ddrphy_dfi_p3_odt), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_odt) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_27 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip00[0]), .D2(a7ddrphy_bitslip00[1]), .D3(a7ddrphy_bitslip00[2]), .D4(a7ddrphy_bitslip00[3]), .D5(a7ddrphy_bitslip00[4]), .D6(a7ddrphy_bitslip00[5]), .D7(a7ddrphy_bitslip00[6]), .D8(a7ddrphy_bitslip00[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OFB(a7ddrphy0), .OQ(a7ddrphy_dqs_o_no_delay0), .TQ(a7ddrphy_dqs_t0) ); IOBUFDS IOBUFDS( .I(a7ddrphy_dqs_o_no_delay0), .T(a7ddrphy_dqs_t0), .IO(ddram_dqs_p[0]), .IOB(ddram_dqs_n[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_28 ( .CLK(sys4x_dqs_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip10[0]), .D2(a7ddrphy_bitslip10[1]), .D3(a7ddrphy_bitslip10[2]), .D4(a7ddrphy_bitslip10[3]), .D5(a7ddrphy_bitslip10[4]), .D6(a7ddrphy_bitslip10[5]), .D7(a7ddrphy_bitslip10[6]), .D8(a7ddrphy_bitslip10[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OFB(a7ddrphy1), .OQ(a7ddrphy_dqs_o_no_delay1), .TQ(a7ddrphy_dqs_t1) ); IOBUFDS IOBUFDS_1( .I(a7ddrphy_dqs_o_no_delay1), .T(a7ddrphy_dqs_t1), .IO(ddram_dqs_p[1]), .IOB(ddram_dqs_n[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_29 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip01[0]), .D2(a7ddrphy_bitslip01[1]), .D3(a7ddrphy_bitslip01[2]), .D4(a7ddrphy_bitslip01[3]), .D5(a7ddrphy_bitslip01[4]), .D6(a7ddrphy_bitslip01[5]), .D7(a7ddrphy_bitslip01[6]), .D8(a7ddrphy_bitslip01[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_dm[0]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_30 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip11[0]), .D2(a7ddrphy_bitslip11[1]), .D3(a7ddrphy_bitslip11[2]), .D4(a7ddrphy_bitslip11[3]), .D5(a7ddrphy_bitslip11[4]), .D6(a7ddrphy_bitslip11[5]), .D7(a7ddrphy_bitslip11[6]), .D8(a7ddrphy_bitslip11[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .OQ(ddram_dm[1]) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_31 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip02[0]), .D2(a7ddrphy_bitslip02[1]), .D3(a7ddrphy_bitslip02[2]), .D4(a7ddrphy_bitslip02[3]), .D5(a7ddrphy_bitslip02[4]), .D6(a7ddrphy_bitslip02[5]), .D7(a7ddrphy_bitslip02[6]), .D8(a7ddrphy_bitslip02[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay0), .TQ(a7ddrphy_dq_t0) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed0), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip03[7]), .Q2(a7ddrphy_bitslip03[6]), .Q3(a7ddrphy_bitslip03[5]), .Q4(a7ddrphy_bitslip03[4]), .Q5(a7ddrphy_bitslip03[3]), .Q6(a7ddrphy_bitslip03[2]), .Q7(a7ddrphy_bitslip03[1]), .Q8(a7ddrphy_bitslip03[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay0), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed0) ); IOBUF IOBUF( .I(a7ddrphy_dq_o_nodelay0), .T(a7ddrphy_dq_t0), .IO(ddram_dq[0]), .O(a7ddrphy_dq_i_nodelay0) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_32 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip12[0]), .D2(a7ddrphy_bitslip12[1]), .D3(a7ddrphy_bitslip12[2]), .D4(a7ddrphy_bitslip12[3]), .D5(a7ddrphy_bitslip12[4]), .D6(a7ddrphy_bitslip12[5]), .D7(a7ddrphy_bitslip12[6]), .D8(a7ddrphy_bitslip12[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay1), .TQ(a7ddrphy_dq_t1) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_1 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed1), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip13[7]), .Q2(a7ddrphy_bitslip13[6]), .Q3(a7ddrphy_bitslip13[5]), .Q4(a7ddrphy_bitslip13[4]), .Q5(a7ddrphy_bitslip13[3]), .Q6(a7ddrphy_bitslip13[2]), .Q7(a7ddrphy_bitslip13[1]), .Q8(a7ddrphy_bitslip13[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_1 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay1), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed1) ); IOBUF IOBUF_1( .I(a7ddrphy_dq_o_nodelay1), .T(a7ddrphy_dq_t1), .IO(ddram_dq[1]), .O(a7ddrphy_dq_i_nodelay1) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_33 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip20[0]), .D2(a7ddrphy_bitslip20[1]), .D3(a7ddrphy_bitslip20[2]), .D4(a7ddrphy_bitslip20[3]), .D5(a7ddrphy_bitslip20[4]), .D6(a7ddrphy_bitslip20[5]), .D7(a7ddrphy_bitslip20[6]), .D8(a7ddrphy_bitslip20[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay2), .TQ(a7ddrphy_dq_t2) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_2 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed2), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip21[7]), .Q2(a7ddrphy_bitslip21[6]), .Q3(a7ddrphy_bitslip21[5]), .Q4(a7ddrphy_bitslip21[4]), .Q5(a7ddrphy_bitslip21[3]), .Q6(a7ddrphy_bitslip21[2]), .Q7(a7ddrphy_bitslip21[1]), .Q8(a7ddrphy_bitslip21[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_2 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay2), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed2) ); IOBUF IOBUF_2( .I(a7ddrphy_dq_o_nodelay2), .T(a7ddrphy_dq_t2), .IO(ddram_dq[2]), .O(a7ddrphy_dq_i_nodelay2) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_34 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip30[0]), .D2(a7ddrphy_bitslip30[1]), .D3(a7ddrphy_bitslip30[2]), .D4(a7ddrphy_bitslip30[3]), .D5(a7ddrphy_bitslip30[4]), .D6(a7ddrphy_bitslip30[5]), .D7(a7ddrphy_bitslip30[6]), .D8(a7ddrphy_bitslip30[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay3), .TQ(a7ddrphy_dq_t3) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_3 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed3), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip31[7]), .Q2(a7ddrphy_bitslip31[6]), .Q3(a7ddrphy_bitslip31[5]), .Q4(a7ddrphy_bitslip31[4]), .Q5(a7ddrphy_bitslip31[3]), .Q6(a7ddrphy_bitslip31[2]), .Q7(a7ddrphy_bitslip31[1]), .Q8(a7ddrphy_bitslip31[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_3 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay3), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed3) ); IOBUF IOBUF_3( .I(a7ddrphy_dq_o_nodelay3), .T(a7ddrphy_dq_t3), .IO(ddram_dq[3]), .O(a7ddrphy_dq_i_nodelay3) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_35 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip40[0]), .D2(a7ddrphy_bitslip40[1]), .D3(a7ddrphy_bitslip40[2]), .D4(a7ddrphy_bitslip40[3]), .D5(a7ddrphy_bitslip40[4]), .D6(a7ddrphy_bitslip40[5]), .D7(a7ddrphy_bitslip40[6]), .D8(a7ddrphy_bitslip40[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay4), .TQ(a7ddrphy_dq_t4) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_4 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed4), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip41[7]), .Q2(a7ddrphy_bitslip41[6]), .Q3(a7ddrphy_bitslip41[5]), .Q4(a7ddrphy_bitslip41[4]), .Q5(a7ddrphy_bitslip41[3]), .Q6(a7ddrphy_bitslip41[2]), .Q7(a7ddrphy_bitslip41[1]), .Q8(a7ddrphy_bitslip41[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_4 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay4), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed4) ); IOBUF IOBUF_4( .I(a7ddrphy_dq_o_nodelay4), .T(a7ddrphy_dq_t4), .IO(ddram_dq[4]), .O(a7ddrphy_dq_i_nodelay4) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_36 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip50[0]), .D2(a7ddrphy_bitslip50[1]), .D3(a7ddrphy_bitslip50[2]), .D4(a7ddrphy_bitslip50[3]), .D5(a7ddrphy_bitslip50[4]), .D6(a7ddrphy_bitslip50[5]), .D7(a7ddrphy_bitslip50[6]), .D8(a7ddrphy_bitslip50[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay5), .TQ(a7ddrphy_dq_t5) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_5 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed5), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip51[7]), .Q2(a7ddrphy_bitslip51[6]), .Q3(a7ddrphy_bitslip51[5]), .Q4(a7ddrphy_bitslip51[4]), .Q5(a7ddrphy_bitslip51[3]), .Q6(a7ddrphy_bitslip51[2]), .Q7(a7ddrphy_bitslip51[1]), .Q8(a7ddrphy_bitslip51[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_5 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay5), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed5) ); IOBUF IOBUF_5( .I(a7ddrphy_dq_o_nodelay5), .T(a7ddrphy_dq_t5), .IO(ddram_dq[5]), .O(a7ddrphy_dq_i_nodelay5) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_37 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip60[0]), .D2(a7ddrphy_bitslip60[1]), .D3(a7ddrphy_bitslip60[2]), .D4(a7ddrphy_bitslip60[3]), .D5(a7ddrphy_bitslip60[4]), .D6(a7ddrphy_bitslip60[5]), .D7(a7ddrphy_bitslip60[6]), .D8(a7ddrphy_bitslip60[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay6), .TQ(a7ddrphy_dq_t6) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_6 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed6), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip61[7]), .Q2(a7ddrphy_bitslip61[6]), .Q3(a7ddrphy_bitslip61[5]), .Q4(a7ddrphy_bitslip61[4]), .Q5(a7ddrphy_bitslip61[3]), .Q6(a7ddrphy_bitslip61[2]), .Q7(a7ddrphy_bitslip61[1]), .Q8(a7ddrphy_bitslip61[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_6 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay6), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed6) ); IOBUF IOBUF_6( .I(a7ddrphy_dq_o_nodelay6), .T(a7ddrphy_dq_t6), .IO(ddram_dq[6]), .O(a7ddrphy_dq_i_nodelay6) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_38 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip70[0]), .D2(a7ddrphy_bitslip70[1]), .D3(a7ddrphy_bitslip70[2]), .D4(a7ddrphy_bitslip70[3]), .D5(a7ddrphy_bitslip70[4]), .D6(a7ddrphy_bitslip70[5]), .D7(a7ddrphy_bitslip70[6]), .D8(a7ddrphy_bitslip70[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay7), .TQ(a7ddrphy_dq_t7) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_7 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed7), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip71[7]), .Q2(a7ddrphy_bitslip71[6]), .Q3(a7ddrphy_bitslip71[5]), .Q4(a7ddrphy_bitslip71[4]), .Q5(a7ddrphy_bitslip71[3]), .Q6(a7ddrphy_bitslip71[2]), .Q7(a7ddrphy_bitslip71[1]), .Q8(a7ddrphy_bitslip71[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_7 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay7), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed7) ); IOBUF IOBUF_7( .I(a7ddrphy_dq_o_nodelay7), .T(a7ddrphy_dq_t7), .IO(ddram_dq[7]), .O(a7ddrphy_dq_i_nodelay7) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_39 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip80[0]), .D2(a7ddrphy_bitslip80[1]), .D3(a7ddrphy_bitslip80[2]), .D4(a7ddrphy_bitslip80[3]), .D5(a7ddrphy_bitslip80[4]), .D6(a7ddrphy_bitslip80[5]), .D7(a7ddrphy_bitslip80[6]), .D8(a7ddrphy_bitslip80[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay8), .TQ(a7ddrphy_dq_t8) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_8 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed8), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip81[7]), .Q2(a7ddrphy_bitslip81[6]), .Q3(a7ddrphy_bitslip81[5]), .Q4(a7ddrphy_bitslip81[4]), .Q5(a7ddrphy_bitslip81[3]), .Q6(a7ddrphy_bitslip81[2]), .Q7(a7ddrphy_bitslip81[1]), .Q8(a7ddrphy_bitslip81[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_8 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay8), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed8) ); IOBUF IOBUF_8( .I(a7ddrphy_dq_o_nodelay8), .T(a7ddrphy_dq_t8), .IO(ddram_dq[8]), .O(a7ddrphy_dq_i_nodelay8) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_40 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip90[0]), .D2(a7ddrphy_bitslip90[1]), .D3(a7ddrphy_bitslip90[2]), .D4(a7ddrphy_bitslip90[3]), .D5(a7ddrphy_bitslip90[4]), .D6(a7ddrphy_bitslip90[5]), .D7(a7ddrphy_bitslip90[6]), .D8(a7ddrphy_bitslip90[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay9), .TQ(a7ddrphy_dq_t9) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_9 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed9), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip91[7]), .Q2(a7ddrphy_bitslip91[6]), .Q3(a7ddrphy_bitslip91[5]), .Q4(a7ddrphy_bitslip91[4]), .Q5(a7ddrphy_bitslip91[3]), .Q6(a7ddrphy_bitslip91[2]), .Q7(a7ddrphy_bitslip91[1]), .Q8(a7ddrphy_bitslip91[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_9 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay9), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed9) ); IOBUF IOBUF_9( .I(a7ddrphy_dq_o_nodelay9), .T(a7ddrphy_dq_t9), .IO(ddram_dq[9]), .O(a7ddrphy_dq_i_nodelay9) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_41 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip100[0]), .D2(a7ddrphy_bitslip100[1]), .D3(a7ddrphy_bitslip100[2]), .D4(a7ddrphy_bitslip100[3]), .D5(a7ddrphy_bitslip100[4]), .D6(a7ddrphy_bitslip100[5]), .D7(a7ddrphy_bitslip100[6]), .D8(a7ddrphy_bitslip100[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay10), .TQ(a7ddrphy_dq_t10) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_10 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed10), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip101[7]), .Q2(a7ddrphy_bitslip101[6]), .Q3(a7ddrphy_bitslip101[5]), .Q4(a7ddrphy_bitslip101[4]), .Q5(a7ddrphy_bitslip101[3]), .Q6(a7ddrphy_bitslip101[2]), .Q7(a7ddrphy_bitslip101[1]), .Q8(a7ddrphy_bitslip101[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_10 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay10), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed10) ); IOBUF IOBUF_10( .I(a7ddrphy_dq_o_nodelay10), .T(a7ddrphy_dq_t10), .IO(ddram_dq[10]), .O(a7ddrphy_dq_i_nodelay10) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_42 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip110[0]), .D2(a7ddrphy_bitslip110[1]), .D3(a7ddrphy_bitslip110[2]), .D4(a7ddrphy_bitslip110[3]), .D5(a7ddrphy_bitslip110[4]), .D6(a7ddrphy_bitslip110[5]), .D7(a7ddrphy_bitslip110[6]), .D8(a7ddrphy_bitslip110[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay11), .TQ(a7ddrphy_dq_t11) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_11 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed11), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip111[7]), .Q2(a7ddrphy_bitslip111[6]), .Q3(a7ddrphy_bitslip111[5]), .Q4(a7ddrphy_bitslip111[4]), .Q5(a7ddrphy_bitslip111[3]), .Q6(a7ddrphy_bitslip111[2]), .Q7(a7ddrphy_bitslip111[1]), .Q8(a7ddrphy_bitslip111[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_11 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay11), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed11) ); IOBUF IOBUF_11( .I(a7ddrphy_dq_o_nodelay11), .T(a7ddrphy_dq_t11), .IO(ddram_dq[11]), .O(a7ddrphy_dq_i_nodelay11) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_43 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip120[0]), .D2(a7ddrphy_bitslip120[1]), .D3(a7ddrphy_bitslip120[2]), .D4(a7ddrphy_bitslip120[3]), .D5(a7ddrphy_bitslip120[4]), .D6(a7ddrphy_bitslip120[5]), .D7(a7ddrphy_bitslip120[6]), .D8(a7ddrphy_bitslip120[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay12), .TQ(a7ddrphy_dq_t12) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_12 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed12), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip121[7]), .Q2(a7ddrphy_bitslip121[6]), .Q3(a7ddrphy_bitslip121[5]), .Q4(a7ddrphy_bitslip121[4]), .Q5(a7ddrphy_bitslip121[3]), .Q6(a7ddrphy_bitslip121[2]), .Q7(a7ddrphy_bitslip121[1]), .Q8(a7ddrphy_bitslip121[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_12 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay12), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed12) ); IOBUF IOBUF_12( .I(a7ddrphy_dq_o_nodelay12), .T(a7ddrphy_dq_t12), .IO(ddram_dq[12]), .O(a7ddrphy_dq_i_nodelay12) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_44 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip130[0]), .D2(a7ddrphy_bitslip130[1]), .D3(a7ddrphy_bitslip130[2]), .D4(a7ddrphy_bitslip130[3]), .D5(a7ddrphy_bitslip130[4]), .D6(a7ddrphy_bitslip130[5]), .D7(a7ddrphy_bitslip130[6]), .D8(a7ddrphy_bitslip130[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay13), .TQ(a7ddrphy_dq_t13) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_13 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed13), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip131[7]), .Q2(a7ddrphy_bitslip131[6]), .Q3(a7ddrphy_bitslip131[5]), .Q4(a7ddrphy_bitslip131[4]), .Q5(a7ddrphy_bitslip131[3]), .Q6(a7ddrphy_bitslip131[2]), .Q7(a7ddrphy_bitslip131[1]), .Q8(a7ddrphy_bitslip131[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_13 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay13), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed13) ); IOBUF IOBUF_13( .I(a7ddrphy_dq_o_nodelay13), .T(a7ddrphy_dq_t13), .IO(ddram_dq[13]), .O(a7ddrphy_dq_i_nodelay13) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_45 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip140[0]), .D2(a7ddrphy_bitslip140[1]), .D3(a7ddrphy_bitslip140[2]), .D4(a7ddrphy_bitslip140[3]), .D5(a7ddrphy_bitslip140[4]), .D6(a7ddrphy_bitslip140[5]), .D7(a7ddrphy_bitslip140[6]), .D8(a7ddrphy_bitslip140[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay14), .TQ(a7ddrphy_dq_t14) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_14 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed14), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip141[7]), .Q2(a7ddrphy_bitslip141[6]), .Q3(a7ddrphy_bitslip141[5]), .Q4(a7ddrphy_bitslip141[4]), .Q5(a7ddrphy_bitslip141[3]), .Q6(a7ddrphy_bitslip141[2]), .Q7(a7ddrphy_bitslip141[1]), .Q8(a7ddrphy_bitslip141[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_14 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay14), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed14) ); IOBUF IOBUF_14( .I(a7ddrphy_dq_o_nodelay14), .T(a7ddrphy_dq_t14), .IO(ddram_dq[14]), .O(a7ddrphy_dq_i_nodelay14) ); OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(4'd8), .SERDES_MODE("MASTER"), .TRISTATE_WIDTH(1'd1) ) OSERDESE2_46 ( .CLK(sys4x_clk), .CLKDIV(sys_clk), .D1(a7ddrphy_bitslip150[0]), .D2(a7ddrphy_bitslip150[1]), .D3(a7ddrphy_bitslip150[2]), .D4(a7ddrphy_bitslip150[3]), .D5(a7ddrphy_bitslip150[4]), .D6(a7ddrphy_bitslip150[5]), .D7(a7ddrphy_bitslip150[6]), .D8(a7ddrphy_bitslip150[7]), .OCE(1'd1), .RST((sys_rst | a7ddrphy_rst_storage)), .T1((~a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)), .TCE(1'd1), .OQ(a7ddrphy_dq_o_nodelay15), .TQ(a7ddrphy_dq_t15) ); ISERDESE2 #( .DATA_RATE("DDR"), .DATA_WIDTH(4'd8), .INTERFACE_TYPE("NETWORKING"), .IOBDELAY("IFD"), .NUM_CE(1'd1), .SERDES_MODE("MASTER") ) ISERDESE2_15 ( .BITSLIP(1'd0), .CE1(1'd1), .CLK(sys4x_clk), .CLKB((~sys4x_clk)), .CLKDIV(sys_clk), .DDLY(a7ddrphy_dq_i_delayed15), .RST((sys_rst | a7ddrphy_rst_storage)), .Q1(a7ddrphy_bitslip151[7]), .Q2(a7ddrphy_bitslip151[6]), .Q3(a7ddrphy_bitslip151[5]), .Q4(a7ddrphy_bitslip151[4]), .Q5(a7ddrphy_bitslip151[3]), .Q6(a7ddrphy_bitslip151[2]), .Q7(a7ddrphy_bitslip151[1]), .Q8(a7ddrphy_bitslip151[0]) ); IDELAYE2 #( .CINVCTRL_SEL("FALSE"), .DELAY_SRC("IDATAIN"), .HIGH_PERFORMANCE_MODE("TRUE"), .IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(1'd0), .PIPE_SEL("FALSE"), .REFCLK_FREQUENCY(200.0), .SIGNAL_PATTERN("DATA") ) IDELAYE2_15 ( .C(sys_clk), .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)), .IDATAIN(a7ddrphy_dq_i_nodelay15), .INC(1'd1), .LD(((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re) | a7ddrphy_rst_storage)), .LDPIPEEN(1'd0), .DATAOUT(a7ddrphy_dq_i_delayed15) ); IOBUF IOBUF_15( .I(a7ddrphy_dq_o_nodelay15), .T(a7ddrphy_dq_t15), .IO(ddram_dq[15]), .O(a7ddrphy_dq_i_nodelay15) ); //------------------------------------------------------------------------------ // Memory storage: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage[0:15]; reg [25:0] storage_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine0_wrport_we) storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_1: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_1[0:15]; reg [25:0] storage_1_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine1_wrport_we) storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_2: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_2[0:15]; reg [25:0] storage_2_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine2_wrport_we) storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_3: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_3[0:15]; reg [25:0] storage_3_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine3_wrport_we) storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_4: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_4[0:15]; reg [25:0] storage_4_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine4_wrport_we) storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_5: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_5[0:15]; reg [25:0] storage_5_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine5_wrport_we) storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_6: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_6[0:15]; reg [25:0] storage_6_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine6_wrport_we) storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_7: 16-words x 26-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 26 // Port 1 | Read: Async | Write: ---- | reg [25:0] storage_7[0:15]; reg [25:0] storage_7_dat0; always @(posedge sys_clk) begin if (litedramcore_bankmachine7_wrport_we) storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; FDCE FDCE( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(reset), .Q(litedramcore_reset0) ); FDCE FDCE_1( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset0), .Q(litedramcore_reset1) ); FDCE FDCE_2( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset1), .Q(litedramcore_reset2) ); FDCE FDCE_3( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset2), .Q(litedramcore_reset3) ); FDCE FDCE_4( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset3), .Q(litedramcore_reset4) ); FDCE FDCE_5( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset4), .Q(litedramcore_reset5) ); FDCE FDCE_6( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset5), .Q(litedramcore_reset6) ); FDCE FDCE_7( .C(clkin), .CE(1'd1), .CLR(1'd0), .D(litedramcore_reset6), .Q(litedramcore_reset7) ); PLLE2_ADV #( .CLKFBOUT_MULT(4'd8), .CLKIN1_PERIOD(5.0), .CLKOUT0_DIVIDE(4'd8), .CLKOUT0_PHASE(1'd0), .CLKOUT1_DIVIDE(5'd16), .CLKOUT1_PHASE(1'd0), .CLKOUT2_DIVIDE(3'd4), .CLKOUT2_PHASE(1'd0), .CLKOUT3_DIVIDE(3'd4), .CLKOUT3_PHASE(7'd90), .DIVCLK_DIVIDE(1'd1), .REF_JITTER1(0.01), .STARTUP_WAIT("FALSE") ) PLLE2_ADV ( .CLKFBIN(litedramcore_pll_fb), .CLKIN1(clkin), .PWRDWN(power_down), .RST(litedramcore_reset7), .CLKFBOUT(litedramcore_pll_fb), .CLKOUT0(clkout0), .CLKOUT1(clkout1), .CLKOUT2(clkout2), .CLKOUT3(clkout3), .LOCKED(locked) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE ( .C(iodelay_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl0), .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(iodelay_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl0_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl0), .Q(iodelay_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl1), .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl1_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl1), .Q(sys_rst) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl2), .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl2_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl2), .Q(xilinxasyncresetsynchronizerimpl2_expr) ); (* ars_ff1 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), .CE(1'd1), .D(1'd0), .PRE(xilinxasyncresetsynchronizerimpl3), .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); (* ars_ff2 = "true", async_reg = "true" *) FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(sys4x_dqs_clk), .CE(1'd1), .D(xilinxasyncresetsynchronizerimpl3_rst_meta), .PRE(xilinxasyncresetsynchronizerimpl3), .Q(xilinxasyncresetsynchronizerimpl3_expr) ); endmodule // ----------------------------------------------------------------------------- // Auto-Generated by LiteX on 2022-10-28 19:01:23. //------------------------------------------------------------------------------