// ----------------------------------------------------------------------------- // Auto-Generated by: __ _ __ _ __ // / / (_) /____ | |/_/ // / /__/ / __/ -_)> < // /____/_/\__/\__/_/|_| // Build your hardware, easily! // https://github.com/enjoy-digital/litex // // Filename : liteeth_core.v // Device : xc7 // LiteX sha1 : bc1f1f52b // Date : 2025-02-15 16:17:45 //------------------------------------------------------------------------------ `timescale 1ns / 1ps //------------------------------------------------------------------------------ // Module //------------------------------------------------------------------------------ module liteeth_core ( output wire gmii_clocks_gtx, input wire gmii_clocks_rx, input wire gmii_clocks_tx, input wire gmii_col, input wire gmii_crs, input wire gmii_int_n, output wire gmii_mdc, inout wire gmii_mdio, output wire gmii_rst_n, input wire [7:0] gmii_rx_data, input wire gmii_rx_dv, input wire gmii_rx_er, output reg [7:0] gmii_tx_data, output reg gmii_tx_en, output wire gmii_tx_er, output wire interrupt, input wire sys_clock, input wire sys_reset, output wire wishbone_ack, input wire [29:0] wishbone_adr, input wire [1:0] wishbone_bte, input wire [2:0] wishbone_cti, input wire wishbone_cyc, output wire [31:0] wishbone_dat_r, input wire [31:0] wishbone_dat_w, output wire wishbone_err, input wire [3:0] wishbone_sel, input wire wishbone_stb, input wire wishbone_we ); //------------------------------------------------------------------------------ // Hierarchy //------------------------------------------------------------------------------ /* MACCore └─── bus (SoCBusHandler) │ └─── _interconnect (InterconnectShared) │ │ └─── arbiter (Arbiter) │ │ │ └─── rr (RoundRobin) │ │ └─── decoder (Decoder) │ │ └─── timeout (Timeout) │ │ │ └─── waittimer_0* (WaitTimer) └─── csr (SoCCSRHandler) └─── irq (SoCIRQHandler) └─── ctrl (SoCController) └─── cpu (CPUNone) └─── crg (CRG) └─── ethphy (LiteEthPHYGMIIMII) │ └─── mode_detection (LiteEthGMIIMIIModeDetection) │ │ └─── eth_ps (PulseSynchronizer) │ │ └─── fsm (FSM) │ └─── crg (LiteEthPHYGMIICRG) │ │ └─── hw_reset (LiteEthPHYHWReset) │ │ └─── [BUFG] │ │ └─── [BUFG] │ └─── tx (LiteEthPHYGMIIMIITX) │ │ └─── liteethphygmiitx_0* (LiteEthPHYGMIITX) │ │ └─── liteethphymiitx_0* (LiteEthPHYMIITX) │ │ │ └─── converter (Converter) │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ └─── demultiplexer_0* (Demultiplexer) │ └─── rx (LiteEthPHYGMIIMIIRX) │ │ └─── gmii_rx (LiteEthPHYGMIIRX) │ │ └─── mii_rx (LiteEthPHYMIIRX) │ │ │ └─── converter_0* (Converter) │ │ │ │ └─── _upconverter_0* (_UpConverter) │ │ └─── mux (Multiplexer) │ └─── mdio (LiteEthPHYMDIO) └─── ethmac (LiteEthMAC) │ └─── core (LiteEthMACCore) │ │ └─── tx_datapath (TXDatapath) │ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) │ │ │ │ └─── asyncfifo_0* (AsyncFIFO) │ │ │ │ │ └─── fifo (AsyncFIFO) │ │ │ │ │ │ └─── graycounter_0* (GrayCounter) │ │ │ │ │ │ └─── graycounter_1* (GrayCounter) │ │ │ └─── strideconverter_0* (StrideConverter) │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _downconverter_0* (_DownConverter) │ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) │ │ │ │ └─── last_handler (LiteEthLastHandler) │ │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) │ │ │ │ └─── crc (LiteEthMACCRC32) │ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) │ │ │ │ └─── fsm (FSM) │ │ │ │ └─── buffer_0* (Buffer) │ │ │ │ │ └─── pipe_valid (PipeValid) │ │ │ │ │ └─── pipeline (Pipeline) │ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) │ │ │ │ └─── fsm (FSM) │ │ │ └─── liteethmacgap_0* (LiteEthMACGap) │ │ │ │ └─── fsm (FSM) │ │ │ └─── pipeline_0* (Pipeline) │ │ └─── rx_datapath (RXDatapath) │ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) │ │ │ │ └─── fsm (FSM) │ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) │ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) │ │ │ │ └─── crc (LiteEthMACCRC32) │ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── fsm (FSM) │ │ │ │ └─── buffer_0* (Buffer) │ │ │ │ │ └─── pipe_valid (PipeValid) │ │ │ │ │ └─── pipeline (Pipeline) │ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) │ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) │ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) │ │ │ └─── strideconverter_0* (StrideConverter) │ │ │ │ └─── converter_0* (Converter) │ │ │ │ │ └─── _upconverter_0* (_UpConverter) │ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) │ │ │ │ └─── asyncfifo_0* (AsyncFIFO) │ │ │ │ │ └─── fifo (AsyncFIFO) │ │ │ │ │ │ └─── graycounter_0* (GrayCounter) │ │ │ │ │ │ └─── graycounter_1* (GrayCounter) │ │ │ └─── pipeline_0* (Pipeline) │ └─── interface (LiteEthMACWishboneInterface) │ │ └─── sram (LiteEthMACSRAM) │ │ │ └─── writer (LiteEthMACSRAMWriter) │ │ │ │ └─── ev (EventManager) │ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) │ │ │ │ └─── stat_fifo (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── fsm (FSM) │ │ │ └─── reader (LiteEthMACSRAMReader) │ │ │ │ └─── ev (EventManager) │ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) │ │ │ │ └─── syncfifo_0* (SyncFIFO) │ │ │ │ │ └─── fifo (SyncFIFO) │ │ │ │ └─── fsm (FSM) │ │ │ └─── ev (SharedIRQ) │ │ └─── sram_0* (SRAM) │ │ └─── sram_1* (SRAM) │ │ └─── decoder_0* (Decoder) │ │ └─── sram_2* (SRAM) │ │ └─── sram_3* (SRAM) │ │ └─── decoder_1* (Decoder) │ └─── ev (SharedIRQ) └─── csr_bridge (Wishbone2CSR) │ └─── fsm (FSM) └─── csr_bankarray (CSRBankArray) │ └─── csrbank_0* (CSRBank) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstatus_0* (CSRStatus) │ └─── csrbank_1* (CSRBank) │ │ └─── csrstatus_0* (CSRStatus) │ │ └─── csrstatus_1* (CSRStatus) │ │ └─── csrstatus_2* (CSRStatus) │ │ └─── csrstatus_3* (CSRStatus) │ │ └─── csrstatus_4* (CSRStatus) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstatus_5* (CSRStatus) │ │ └─── csrstatus_6* (CSRStatus) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstorage_2* (CSRStorage) │ │ └─── csrstatus_7* (CSRStatus) │ │ └─── csrstatus_8* (CSRStatus) │ │ └─── csrstorage_3* (CSRStorage) │ │ └─── csrstatus_9* (CSRStatus) │ │ └─── csrstatus_10* (CSRStatus) │ │ └─── csrstatus_11* (CSRStatus) │ └─── csrbank_2* (CSRBank) │ │ └─── csrstatus_0* (CSRStatus) │ │ └─── csrstorage_0* (CSRStorage) │ │ └─── csrstorage_1* (CSRStorage) │ │ └─── csrstatus_1* (CSRStatus) └─── csr_interconnect (InterconnectShared) └─── [FDPE] └─── [FDPE] └─── [FDPE] └─── [FDPE] └─── [ODDR] * : Generated name. []: BlackBox. */ //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ wire [13:0] adr; wire core_bufferizeendpoints_pipe_valid_sink_first; wire core_bufferizeendpoints_pipe_valid_sink_last; wire [7:0] core_bufferizeendpoints_pipe_valid_sink_payload_data; wire core_bufferizeendpoints_pipe_valid_sink_payload_error; wire core_bufferizeendpoints_pipe_valid_sink_payload_last_be; wire core_bufferizeendpoints_pipe_valid_sink_ready; wire core_bufferizeendpoints_pipe_valid_sink_valid; reg core_bufferizeendpoints_pipe_valid_source_first = 1'd0; reg core_bufferizeendpoints_pipe_valid_source_last = 1'd0; reg [7:0] core_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; reg core_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; reg core_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; wire core_bufferizeendpoints_pipe_valid_source_ready; reg core_bufferizeendpoints_pipe_valid_source_valid = 1'd0; wire core_bufferizeendpoints_sink_sink_first; wire core_bufferizeendpoints_sink_sink_last; wire [7:0] core_bufferizeendpoints_sink_sink_payload_data; wire core_bufferizeendpoints_sink_sink_payload_error; wire core_bufferizeendpoints_sink_sink_payload_last_be; wire core_bufferizeendpoints_sink_sink_ready; wire core_bufferizeendpoints_sink_sink_valid; wire core_bufferizeendpoints_source_source_first; wire core_bufferizeendpoints_source_source_last; wire [7:0] core_bufferizeendpoints_source_source_payload_data; wire core_bufferizeendpoints_source_source_payload_error; wire core_bufferizeendpoints_source_source_payload_last_be; wire core_bufferizeendpoints_source_source_ready; wire core_bufferizeendpoints_source_source_valid; reg core_crc_errors_re = 1'd0; reg [31:0] core_crc_errors_status = 32'd0; wire core_crc_errors_we; wire core_liteethmaccrc32checker_crc_be; reg core_liteethmaccrc32checker_crc_ce = 1'd0; reg [31:0] core_liteethmaccrc32checker_crc_crc_next = 32'd0; wire [31:0] core_liteethmaccrc32checker_crc_crc_prev; wire [7:0] core_liteethmaccrc32checker_crc_data0; wire [7:0] core_liteethmaccrc32checker_crc_data1; reg core_liteethmaccrc32checker_crc_error0 = 1'd0; reg core_liteethmaccrc32checker_crc_error1 = 1'd0; reg core_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; reg core_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; reg [31:0] core_liteethmaccrc32checker_crc_reg = 32'd4294967295; reg core_liteethmaccrc32checker_crc_reset = 1'd0; reg [31:0] core_liteethmaccrc32checker_crc_value = 32'd0; reg core_liteethmaccrc32checker_error = 1'd0; wire core_liteethmaccrc32checker_fifo_full; wire core_liteethmaccrc32checker_fifo_in; wire core_liteethmaccrc32checker_fifo_out; reg core_liteethmaccrc32checker_fifo_reset = 1'd0; reg core_liteethmaccrc32checker_last_be = 1'd0; reg core_liteethmaccrc32checker_last_be_next_value0 = 1'd0; reg core_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; wire core_liteethmaccrc32checker_sink_sink_first; wire core_liteethmaccrc32checker_sink_sink_last; wire [7:0] core_liteethmaccrc32checker_sink_sink_payload_data; wire core_liteethmaccrc32checker_sink_sink_payload_error; wire core_liteethmaccrc32checker_sink_sink_payload_last_be; reg core_liteethmaccrc32checker_sink_sink_ready = 1'd0; wire core_liteethmaccrc32checker_sink_sink_valid; wire core_liteethmaccrc32checker_source_source_first; reg core_liteethmaccrc32checker_source_source_last = 1'd0; wire [7:0] core_liteethmaccrc32checker_source_source_payload_data; reg core_liteethmaccrc32checker_source_source_payload_error = 1'd0; reg core_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; wire core_liteethmaccrc32checker_source_source_ready; reg core_liteethmaccrc32checker_source_source_valid = 1'd0; reg [2:0] core_liteethmaccrc32checker_syncfifo_consume = 3'd0; wire core_liteethmaccrc32checker_syncfifo_do_read; wire core_liteethmaccrc32checker_syncfifo_fifo_in_first; wire core_liteethmaccrc32checker_syncfifo_fifo_in_last; wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; wire core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; wire core_liteethmaccrc32checker_syncfifo_fifo_out_first; wire core_liteethmaccrc32checker_syncfifo_fifo_out_last; wire [7:0] core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; wire core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; reg [2:0] core_liteethmaccrc32checker_syncfifo_level = 3'd0; reg [2:0] core_liteethmaccrc32checker_syncfifo_produce = 3'd0; wire [2:0] core_liteethmaccrc32checker_syncfifo_rdport_adr; wire [11:0] core_liteethmaccrc32checker_syncfifo_rdport_dat_r; reg core_liteethmaccrc32checker_syncfifo_replace = 1'd0; wire core_liteethmaccrc32checker_syncfifo_sink_first; wire core_liteethmaccrc32checker_syncfifo_sink_last; wire [7:0] core_liteethmaccrc32checker_syncfifo_sink_payload_data; wire core_liteethmaccrc32checker_syncfifo_sink_payload_error; wire core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; wire core_liteethmaccrc32checker_syncfifo_sink_ready; reg core_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; wire core_liteethmaccrc32checker_syncfifo_source_first; wire core_liteethmaccrc32checker_syncfifo_source_last; wire [7:0] core_liteethmaccrc32checker_syncfifo_source_payload_data; wire core_liteethmaccrc32checker_syncfifo_source_payload_error; wire core_liteethmaccrc32checker_syncfifo_source_payload_last_be; reg core_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; wire core_liteethmaccrc32checker_syncfifo_source_valid; wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_din; wire [11:0] core_liteethmaccrc32checker_syncfifo_syncfifo_dout; wire core_liteethmaccrc32checker_syncfifo_syncfifo_re; wire core_liteethmaccrc32checker_syncfifo_syncfifo_readable; wire core_liteethmaccrc32checker_syncfifo_syncfifo_we; wire core_liteethmaccrc32checker_syncfifo_syncfifo_writable; reg [2:0] core_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_r; wire [11:0] core_liteethmaccrc32checker_syncfifo_wrport_dat_w; wire core_liteethmaccrc32checker_syncfifo_wrport_we; reg core_preamble_errors_re = 1'd0; reg [31:0] core_preamble_errors_status = 32'd0; wire core_preamble_errors_we; wire core_pulsesynchronizer0_i; wire core_pulsesynchronizer0_o; reg core_pulsesynchronizer0_toggle_i = 1'd0; wire core_pulsesynchronizer0_toggle_o; reg core_pulsesynchronizer0_toggle_o_r = 1'd0; wire core_pulsesynchronizer1_i; wire core_pulsesynchronizer1_o; reg core_pulsesynchronizer1_toggle_i = 1'd0; wire core_pulsesynchronizer1_toggle_o; reg core_pulsesynchronizer1_toggle_o_r = 1'd0; reg core_re = 1'd0; wire [41:0] core_rx_cdc_cdc_asyncfifo_din; wire [41:0] core_rx_cdc_cdc_asyncfifo_dout; wire core_rx_cdc_cdc_asyncfifo_re; wire core_rx_cdc_cdc_asyncfifo_readable; wire core_rx_cdc_cdc_asyncfifo_we; wire core_rx_cdc_cdc_asyncfifo_writable; wire [5:0] core_rx_cdc_cdc_consume_wdomain; wire core_rx_cdc_cdc_fifo_in_first; wire core_rx_cdc_cdc_fifo_in_last; wire [31:0] core_rx_cdc_cdc_fifo_in_payload_data; wire [3:0] core_rx_cdc_cdc_fifo_in_payload_error; wire [3:0] core_rx_cdc_cdc_fifo_in_payload_last_be; wire core_rx_cdc_cdc_fifo_out_first; wire core_rx_cdc_cdc_fifo_out_last; wire [31:0] core_rx_cdc_cdc_fifo_out_payload_data; wire [3:0] core_rx_cdc_cdc_fifo_out_payload_error; wire [3:0] core_rx_cdc_cdc_fifo_out_payload_last_be; wire core_rx_cdc_cdc_graycounter0_ce; (* dont_touch = "true" *) reg [5:0] core_rx_cdc_cdc_graycounter0_q = 6'd0; reg [5:0] core_rx_cdc_cdc_graycounter0_q_binary = 6'd0; wire [5:0] core_rx_cdc_cdc_graycounter0_q_next; reg [5:0] core_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; wire core_rx_cdc_cdc_graycounter1_ce; (* dont_touch = "true" *) reg [5:0] core_rx_cdc_cdc_graycounter1_q = 6'd0; reg [5:0] core_rx_cdc_cdc_graycounter1_q_binary = 6'd0; wire [5:0] core_rx_cdc_cdc_graycounter1_q_next; reg [5:0] core_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; wire [5:0] core_rx_cdc_cdc_produce_rdomain; wire [4:0] core_rx_cdc_cdc_rdport_adr; wire [41:0] core_rx_cdc_cdc_rdport_dat_r; wire core_rx_cdc_cdc_sink_first; wire core_rx_cdc_cdc_sink_last; wire [31:0] core_rx_cdc_cdc_sink_payload_data; wire [3:0] core_rx_cdc_cdc_sink_payload_error; wire [3:0] core_rx_cdc_cdc_sink_payload_last_be; wire core_rx_cdc_cdc_sink_ready; wire core_rx_cdc_cdc_sink_valid; wire core_rx_cdc_cdc_source_first; wire core_rx_cdc_cdc_source_last; wire [31:0] core_rx_cdc_cdc_source_payload_data; wire [3:0] core_rx_cdc_cdc_source_payload_error; wire [3:0] core_rx_cdc_cdc_source_payload_last_be; wire core_rx_cdc_cdc_source_ready; wire core_rx_cdc_cdc_source_valid; wire [4:0] core_rx_cdc_cdc_wrport_adr; wire [41:0] core_rx_cdc_cdc_wrport_dat_r; wire [41:0] core_rx_cdc_cdc_wrport_dat_w; wire core_rx_cdc_cdc_wrport_we; wire core_rx_cdc_sink_sink_first; wire core_rx_cdc_sink_sink_last; wire [31:0] core_rx_cdc_sink_sink_payload_data; wire [3:0] core_rx_cdc_sink_sink_payload_error; wire [3:0] core_rx_cdc_sink_sink_payload_last_be; wire core_rx_cdc_sink_sink_ready; wire core_rx_cdc_sink_sink_valid; wire core_rx_cdc_source_source_first; wire core_rx_cdc_source_source_last; wire [31:0] core_rx_cdc_source_source_payload_data; wire [3:0] core_rx_cdc_source_source_payload_error; wire [3:0] core_rx_cdc_source_source_payload_last_be; wire core_rx_cdc_source_source_ready; wire core_rx_cdc_source_source_valid; reg [1:0] core_rx_converter_converter_demux = 2'd0; wire core_rx_converter_converter_load_part; wire core_rx_converter_converter_sink_first; wire core_rx_converter_converter_sink_last; wire [9:0] core_rx_converter_converter_sink_payload_data; wire core_rx_converter_converter_sink_ready; wire core_rx_converter_converter_sink_valid; reg core_rx_converter_converter_source_first = 1'd0; reg core_rx_converter_converter_source_last = 1'd0; reg [39:0] core_rx_converter_converter_source_payload_data = 40'd0; reg [2:0] core_rx_converter_converter_source_payload_valid_token_count = 3'd0; wire core_rx_converter_converter_source_ready; wire core_rx_converter_converter_source_valid; reg core_rx_converter_converter_strobe_all = 1'd0; wire core_rx_converter_sink_first; wire core_rx_converter_sink_last; wire [7:0] core_rx_converter_sink_payload_data; wire core_rx_converter_sink_payload_error; wire core_rx_converter_sink_payload_last_be; wire core_rx_converter_sink_ready; wire core_rx_converter_sink_valid; wire core_rx_converter_source_first; wire core_rx_converter_source_last; reg [31:0] core_rx_converter_source_payload_data = 32'd0; reg [3:0] core_rx_converter_source_payload_error = 4'd0; reg [3:0] core_rx_converter_source_payload_last_be = 4'd0; wire core_rx_converter_source_ready; wire core_rx_converter_source_source_first; wire core_rx_converter_source_source_last; wire [39:0] core_rx_converter_source_source_payload_data; wire core_rx_converter_source_source_ready; wire core_rx_converter_source_source_valid; wire core_rx_converter_source_valid; wire core_rx_last_be_sink_first; wire core_rx_last_be_sink_last; wire [7:0] core_rx_last_be_sink_payload_data; wire core_rx_last_be_sink_payload_error; wire core_rx_last_be_sink_payload_last_be; wire core_rx_last_be_sink_ready; wire core_rx_last_be_sink_valid; wire core_rx_last_be_source_first; wire core_rx_last_be_source_last; wire [7:0] core_rx_last_be_source_payload_data; wire core_rx_last_be_source_payload_error; reg core_rx_last_be_source_payload_last_be = 1'd0; wire core_rx_last_be_source_ready; wire core_rx_last_be_source_valid; wire core_rx_padding_sink_first; wire core_rx_padding_sink_last; wire [7:0] core_rx_padding_sink_payload_data; wire core_rx_padding_sink_payload_error; wire core_rx_padding_sink_payload_last_be; wire core_rx_padding_sink_ready; wire core_rx_padding_sink_valid; wire core_rx_padding_source_first; wire core_rx_padding_source_last; wire [7:0] core_rx_padding_source_payload_data; wire core_rx_padding_source_payload_error; wire core_rx_padding_source_payload_last_be; wire core_rx_padding_source_ready; wire core_rx_padding_source_valid; reg core_rx_preamble_error = 1'd0; reg [63:0] core_rx_preamble_preamble = 64'd15372286728091293013; wire core_rx_preamble_sink_first; wire core_rx_preamble_sink_last; wire [7:0] core_rx_preamble_sink_payload_data; wire core_rx_preamble_sink_payload_error; wire core_rx_preamble_sink_payload_last_be; reg core_rx_preamble_sink_ready = 1'd0; wire core_rx_preamble_sink_valid; reg core_rx_preamble_source_first = 1'd0; reg core_rx_preamble_source_last = 1'd0; wire [7:0] core_rx_preamble_source_payload_data; reg core_rx_preamble_source_payload_error = 1'd0; wire core_rx_preamble_source_payload_last_be; wire core_rx_preamble_source_ready; reg core_rx_preamble_source_valid = 1'd0; wire core_sink_first; wire core_sink_last; wire [31:0] core_sink_payload_data; wire [3:0] core_sink_payload_error; wire [3:0] core_sink_payload_last_be; wire core_sink_ready; wire core_sink_valid; wire core_source_first; wire core_source_last; wire [31:0] core_source_payload_data; wire [3:0] core_source_payload_error; wire [3:0] core_source_payload_last_be; wire core_source_ready; wire core_source_valid; reg core_status = 1'd1; wire [41:0] core_tx_cdc_cdc_asyncfifo_din; wire [41:0] core_tx_cdc_cdc_asyncfifo_dout; wire core_tx_cdc_cdc_asyncfifo_re; wire core_tx_cdc_cdc_asyncfifo_readable; wire core_tx_cdc_cdc_asyncfifo_we; wire core_tx_cdc_cdc_asyncfifo_writable; wire [5:0] core_tx_cdc_cdc_consume_wdomain; wire core_tx_cdc_cdc_fifo_in_first; wire core_tx_cdc_cdc_fifo_in_last; wire [31:0] core_tx_cdc_cdc_fifo_in_payload_data; wire [3:0] core_tx_cdc_cdc_fifo_in_payload_error; wire [3:0] core_tx_cdc_cdc_fifo_in_payload_last_be; wire core_tx_cdc_cdc_fifo_out_first; wire core_tx_cdc_cdc_fifo_out_last; wire [31:0] core_tx_cdc_cdc_fifo_out_payload_data; wire [3:0] core_tx_cdc_cdc_fifo_out_payload_error; wire [3:0] core_tx_cdc_cdc_fifo_out_payload_last_be; wire core_tx_cdc_cdc_graycounter0_ce; (* dont_touch = "true" *) reg [5:0] core_tx_cdc_cdc_graycounter0_q = 6'd0; reg [5:0] core_tx_cdc_cdc_graycounter0_q_binary = 6'd0; wire [5:0] core_tx_cdc_cdc_graycounter0_q_next; reg [5:0] core_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; wire core_tx_cdc_cdc_graycounter1_ce; (* dont_touch = "true" *) reg [5:0] core_tx_cdc_cdc_graycounter1_q = 6'd0; reg [5:0] core_tx_cdc_cdc_graycounter1_q_binary = 6'd0; wire [5:0] core_tx_cdc_cdc_graycounter1_q_next; reg [5:0] core_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; wire [5:0] core_tx_cdc_cdc_produce_rdomain; wire [4:0] core_tx_cdc_cdc_rdport_adr; wire [41:0] core_tx_cdc_cdc_rdport_dat_r; wire core_tx_cdc_cdc_sink_first; wire core_tx_cdc_cdc_sink_last; wire [31:0] core_tx_cdc_cdc_sink_payload_data; wire [3:0] core_tx_cdc_cdc_sink_payload_error; wire [3:0] core_tx_cdc_cdc_sink_payload_last_be; wire core_tx_cdc_cdc_sink_ready; wire core_tx_cdc_cdc_sink_valid; wire core_tx_cdc_cdc_source_first; wire core_tx_cdc_cdc_source_last; wire [31:0] core_tx_cdc_cdc_source_payload_data; wire [3:0] core_tx_cdc_cdc_source_payload_error; wire [3:0] core_tx_cdc_cdc_source_payload_last_be; wire core_tx_cdc_cdc_source_ready; wire core_tx_cdc_cdc_source_valid; wire [4:0] core_tx_cdc_cdc_wrport_adr; wire [41:0] core_tx_cdc_cdc_wrport_dat_r; wire [41:0] core_tx_cdc_cdc_wrport_dat_w; wire core_tx_cdc_cdc_wrport_we; wire core_tx_cdc_sink_sink_first; wire core_tx_cdc_sink_sink_last; wire [31:0] core_tx_cdc_sink_sink_payload_data; wire [3:0] core_tx_cdc_sink_sink_payload_error; wire [3:0] core_tx_cdc_sink_sink_payload_last_be; wire core_tx_cdc_sink_sink_ready; wire core_tx_cdc_sink_sink_valid; wire core_tx_cdc_source_source_first; wire core_tx_cdc_source_source_last; wire [31:0] core_tx_cdc_source_source_payload_data; wire [3:0] core_tx_cdc_source_source_payload_error; wire [3:0] core_tx_cdc_source_source_payload_last_be; wire core_tx_cdc_source_source_ready; wire core_tx_cdc_source_source_valid; wire core_tx_converter_converter_first; wire core_tx_converter_converter_last; reg [1:0] core_tx_converter_converter_mux = 2'd0; wire core_tx_converter_converter_sink_first; wire core_tx_converter_converter_sink_last; reg [39:0] core_tx_converter_converter_sink_payload_data = 40'd0; wire core_tx_converter_converter_sink_ready; wire core_tx_converter_converter_sink_valid; wire core_tx_converter_converter_source_first; wire core_tx_converter_converter_source_last; reg [9:0] core_tx_converter_converter_source_payload_data = 10'd0; wire core_tx_converter_converter_source_payload_valid_token_count; wire core_tx_converter_converter_source_ready; wire core_tx_converter_converter_source_valid; wire core_tx_converter_sink_first; wire core_tx_converter_sink_last; wire [31:0] core_tx_converter_sink_payload_data; wire [3:0] core_tx_converter_sink_payload_error; wire [3:0] core_tx_converter_sink_payload_last_be; wire core_tx_converter_sink_ready; wire core_tx_converter_sink_valid; wire core_tx_converter_source_first; wire core_tx_converter_source_last; wire [7:0] core_tx_converter_source_payload_data; wire core_tx_converter_source_payload_error; wire core_tx_converter_source_payload_last_be; wire core_tx_converter_source_ready; wire core_tx_converter_source_source_first; wire core_tx_converter_source_source_last; wire [9:0] core_tx_converter_source_source_payload_data; wire core_tx_converter_source_source_ready; wire core_tx_converter_source_source_valid; wire core_tx_converter_source_valid; wire core_tx_crc_be; reg core_tx_crc_ce = 1'd0; reg [1:0] core_tx_crc_cnt = 2'd3; wire core_tx_crc_cnt_done; reg [31:0] core_tx_crc_crc_next = 32'd0; reg [31:0] core_tx_crc_crc_packet = 32'd0; reg [31:0] core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; reg core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; wire [31:0] core_tx_crc_crc_prev; wire [7:0] core_tx_crc_data0; wire [7:0] core_tx_crc_data1; reg core_tx_crc_error = 1'd0; reg core_tx_crc_is_ongoing0 = 1'd0; reg core_tx_crc_is_ongoing1 = 1'd0; reg core_tx_crc_last_be = 1'd0; reg core_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; reg core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; wire core_tx_crc_pipe_valid_sink_first; wire core_tx_crc_pipe_valid_sink_last; wire [7:0] core_tx_crc_pipe_valid_sink_payload_data; wire core_tx_crc_pipe_valid_sink_payload_error; wire core_tx_crc_pipe_valid_sink_payload_last_be; wire core_tx_crc_pipe_valid_sink_ready; wire core_tx_crc_pipe_valid_sink_valid; reg core_tx_crc_pipe_valid_source_first = 1'd0; reg core_tx_crc_pipe_valid_source_last = 1'd0; reg [7:0] core_tx_crc_pipe_valid_source_payload_data = 8'd0; reg core_tx_crc_pipe_valid_source_payload_error = 1'd0; reg core_tx_crc_pipe_valid_source_payload_last_be = 1'd0; wire core_tx_crc_pipe_valid_source_ready; reg core_tx_crc_pipe_valid_source_valid = 1'd0; reg [31:0] core_tx_crc_reg = 32'd4294967295; reg core_tx_crc_reset = 1'd0; wire core_tx_crc_sink_first; wire core_tx_crc_sink_last; wire [7:0] core_tx_crc_sink_payload_data; wire core_tx_crc_sink_payload_error; wire core_tx_crc_sink_payload_last_be; reg core_tx_crc_sink_ready = 1'd0; wire core_tx_crc_sink_sink_first; wire core_tx_crc_sink_sink_last; wire [7:0] core_tx_crc_sink_sink_payload_data; wire core_tx_crc_sink_sink_payload_error; wire core_tx_crc_sink_sink_payload_last_be; wire core_tx_crc_sink_sink_ready; wire core_tx_crc_sink_sink_valid; wire core_tx_crc_sink_valid; reg core_tx_crc_source_first = 1'd0; reg core_tx_crc_source_last = 1'd0; reg [7:0] core_tx_crc_source_payload_data = 8'd0; reg core_tx_crc_source_payload_error = 1'd0; reg core_tx_crc_source_payload_last_be = 1'd0; wire core_tx_crc_source_ready; wire core_tx_crc_source_source_first; wire core_tx_crc_source_source_last; wire [7:0] core_tx_crc_source_source_payload_data; wire core_tx_crc_source_source_payload_error; wire core_tx_crc_source_source_payload_last_be; wire core_tx_crc_source_source_ready; wire core_tx_crc_source_source_valid; reg core_tx_crc_source_valid = 1'd0; reg [31:0] core_tx_crc_value = 32'd0; reg [3:0] core_tx_gap_counter = 4'd0; reg [3:0] core_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; reg core_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; wire core_tx_gap_sink_first; wire core_tx_gap_sink_last; wire [7:0] core_tx_gap_sink_payload_data; wire core_tx_gap_sink_payload_error; wire core_tx_gap_sink_payload_last_be; reg core_tx_gap_sink_ready = 1'd0; wire core_tx_gap_sink_valid; reg core_tx_gap_source_first = 1'd0; reg core_tx_gap_source_last = 1'd0; reg [7:0] core_tx_gap_source_payload_data = 8'd0; reg core_tx_gap_source_payload_error = 1'd0; reg core_tx_gap_source_payload_last_be = 1'd0; wire core_tx_gap_source_ready; reg core_tx_gap_source_valid = 1'd0; wire core_tx_last_be_last_handler_sink_first; wire core_tx_last_be_last_handler_sink_last; wire [7:0] core_tx_last_be_last_handler_sink_payload_data; wire core_tx_last_be_last_handler_sink_payload_error; wire core_tx_last_be_last_handler_sink_payload_last_be; reg core_tx_last_be_last_handler_sink_ready = 1'd0; wire core_tx_last_be_last_handler_sink_valid; reg core_tx_last_be_last_handler_source_first = 1'd0; reg core_tx_last_be_last_handler_source_last = 1'd0; reg [7:0] core_tx_last_be_last_handler_source_payload_data = 8'd0; reg core_tx_last_be_last_handler_source_payload_error = 1'd0; reg core_tx_last_be_last_handler_source_payload_last_be = 1'd0; wire core_tx_last_be_last_handler_source_ready; reg core_tx_last_be_last_handler_source_valid = 1'd0; wire core_tx_last_be_sink_sink_first; wire core_tx_last_be_sink_sink_last; wire [7:0] core_tx_last_be_sink_sink_payload_data; wire core_tx_last_be_sink_sink_payload_error; wire core_tx_last_be_sink_sink_payload_last_be; wire core_tx_last_be_sink_sink_ready; wire core_tx_last_be_sink_sink_valid; wire core_tx_last_be_source_source_first; wire core_tx_last_be_source_source_last; wire [7:0] core_tx_last_be_source_source_payload_data; wire core_tx_last_be_source_source_payload_error; wire core_tx_last_be_source_source_payload_last_be; wire core_tx_last_be_source_source_ready; wire core_tx_last_be_source_source_valid; reg [15:0] core_tx_padding_counter = 16'd0; reg [15:0] core_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; reg core_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; wire core_tx_padding_counter_done; wire core_tx_padding_sink_first; wire core_tx_padding_sink_last; wire [7:0] core_tx_padding_sink_payload_data; wire core_tx_padding_sink_payload_error; wire core_tx_padding_sink_payload_last_be; reg core_tx_padding_sink_ready = 1'd0; wire core_tx_padding_sink_valid; reg core_tx_padding_source_first = 1'd0; reg core_tx_padding_source_last = 1'd0; reg [7:0] core_tx_padding_source_payload_data = 8'd0; reg core_tx_padding_source_payload_error = 1'd0; reg core_tx_padding_source_payload_last_be = 1'd0; wire core_tx_padding_source_ready; reg core_tx_padding_source_valid = 1'd0; reg [2:0] core_tx_preamble_count = 3'd0; reg [2:0] core_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; reg core_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; reg [63:0] core_tx_preamble_preamble = 64'd15372286728091293013; wire core_tx_preamble_sink_first; wire core_tx_preamble_sink_last; wire [7:0] core_tx_preamble_sink_payload_data; wire core_tx_preamble_sink_payload_error; wire core_tx_preamble_sink_payload_last_be; reg core_tx_preamble_sink_ready = 1'd0; wire core_tx_preamble_sink_valid; reg core_tx_preamble_source_first = 1'd0; reg core_tx_preamble_source_last = 1'd0; reg [7:0] core_tx_preamble_source_payload_data = 8'd0; reg core_tx_preamble_source_payload_error = 1'd0; wire core_tx_preamble_source_payload_last_be; wire core_tx_preamble_source_ready; reg core_tx_preamble_source_valid = 1'd0; wire core_we; reg [19:0] count = 20'd1000000; wire [31:0] csrbank0_bus_errors_r; reg csrbank0_bus_errors_re = 1'd0; wire [31:0] csrbank0_bus_errors_w; reg csrbank0_bus_errors_we = 1'd0; wire [1:0] csrbank0_reset0_r; reg csrbank0_reset0_re = 1'd0; wire [1:0] csrbank0_reset0_w; reg csrbank0_reset0_we = 1'd0; wire [31:0] csrbank0_scratch0_r; reg csrbank0_scratch0_re = 1'd0; wire [31:0] csrbank0_scratch0_w; reg csrbank0_scratch0_we = 1'd0; wire csrbank0_sel; wire csrbank1_preamble_crc_r; reg csrbank1_preamble_crc_re = 1'd0; wire csrbank1_preamble_crc_w; reg csrbank1_preamble_crc_we = 1'd0; wire [31:0] csrbank1_rx_datapath_crc_errors_r; reg csrbank1_rx_datapath_crc_errors_re = 1'd0; wire [31:0] csrbank1_rx_datapath_crc_errors_w; reg csrbank1_rx_datapath_crc_errors_we = 1'd0; wire [31:0] csrbank1_rx_datapath_preamble_errors_r; reg csrbank1_rx_datapath_preamble_errors_re = 1'd0; wire [31:0] csrbank1_rx_datapath_preamble_errors_w; reg csrbank1_rx_datapath_preamble_errors_we = 1'd0; wire csrbank1_sel; wire csrbank1_sram_reader_ev_enable0_r; reg csrbank1_sram_reader_ev_enable0_re = 1'd0; wire csrbank1_sram_reader_ev_enable0_w; reg csrbank1_sram_reader_ev_enable0_we = 1'd0; wire csrbank1_sram_reader_ev_pending_r; reg csrbank1_sram_reader_ev_pending_re = 1'd0; wire csrbank1_sram_reader_ev_pending_w; reg csrbank1_sram_reader_ev_pending_we = 1'd0; wire csrbank1_sram_reader_ev_status_r; reg csrbank1_sram_reader_ev_status_re = 1'd0; wire csrbank1_sram_reader_ev_status_w; reg csrbank1_sram_reader_ev_status_we = 1'd0; wire [10:0] csrbank1_sram_reader_length0_r; reg csrbank1_sram_reader_length0_re = 1'd0; wire [10:0] csrbank1_sram_reader_length0_w; reg csrbank1_sram_reader_length0_we = 1'd0; wire [1:0] csrbank1_sram_reader_level_r; reg csrbank1_sram_reader_level_re = 1'd0; wire [1:0] csrbank1_sram_reader_level_w; reg csrbank1_sram_reader_level_we = 1'd0; wire csrbank1_sram_reader_ready_r; reg csrbank1_sram_reader_ready_re = 1'd0; wire csrbank1_sram_reader_ready_w; reg csrbank1_sram_reader_ready_we = 1'd0; wire csrbank1_sram_reader_slot0_r; reg csrbank1_sram_reader_slot0_re = 1'd0; wire csrbank1_sram_reader_slot0_w; reg csrbank1_sram_reader_slot0_we = 1'd0; wire [31:0] csrbank1_sram_writer_errors_r; reg csrbank1_sram_writer_errors_re = 1'd0; wire [31:0] csrbank1_sram_writer_errors_w; reg csrbank1_sram_writer_errors_we = 1'd0; wire csrbank1_sram_writer_ev_enable0_r; reg csrbank1_sram_writer_ev_enable0_re = 1'd0; wire csrbank1_sram_writer_ev_enable0_w; reg csrbank1_sram_writer_ev_enable0_we = 1'd0; wire csrbank1_sram_writer_ev_pending_r; reg csrbank1_sram_writer_ev_pending_re = 1'd0; wire csrbank1_sram_writer_ev_pending_w; reg csrbank1_sram_writer_ev_pending_we = 1'd0; wire csrbank1_sram_writer_ev_status_r; reg csrbank1_sram_writer_ev_status_re = 1'd0; wire csrbank1_sram_writer_ev_status_w; reg csrbank1_sram_writer_ev_status_we = 1'd0; wire [10:0] csrbank1_sram_writer_length_r; reg csrbank1_sram_writer_length_re = 1'd0; wire [10:0] csrbank1_sram_writer_length_w; reg csrbank1_sram_writer_length_we = 1'd0; wire csrbank1_sram_writer_slot_r; reg csrbank1_sram_writer_slot_re = 1'd0; wire csrbank1_sram_writer_slot_w; reg csrbank1_sram_writer_slot_we = 1'd0; wire csrbank2_crg_reset0_r; reg csrbank2_crg_reset0_re = 1'd0; wire csrbank2_crg_reset0_w; reg csrbank2_crg_reset0_we = 1'd0; wire csrbank2_mdio_r_r; reg csrbank2_mdio_r_re = 1'd0; wire csrbank2_mdio_r_w; reg csrbank2_mdio_r_we = 1'd0; wire [2:0] csrbank2_mdio_w0_r; reg csrbank2_mdio_w0_re = 1'd0; wire [2:0] csrbank2_mdio_w0_w; reg csrbank2_mdio_w0_we = 1'd0; wire csrbank2_mode_detection_mode_r; reg csrbank2_mode_detection_mode_re = 1'd0; wire csrbank2_mode_detection_mode_w; reg csrbank2_mode_detection_mode_we = 1'd0; wire csrbank2_sel; wire [31:0] dat_r; wire [31:0] dat_w; wire done; reg error = 1'd0; (* dont_touch = "true" *) wire eth_rx_clk; wire eth_rx_rst; (* dont_touch = "true" *) wire eth_tx_clk; wire eth_tx_rst; wire grant; reg interface0_ack = 1'd0; wire [29:0] interface0_adr; wire [13:0] interface0_bank_bus_adr; reg [31:0] interface0_bank_bus_dat_r = 32'd0; wire [31:0] interface0_bank_bus_dat_w; wire interface0_bank_bus_re; wire interface0_bank_bus_we; wire [1:0] interface0_bte; wire [2:0] interface0_cti; wire interface0_cyc; reg [31:0] interface0_dat_r = 32'd0; wire [31:0] interface0_dat_w; reg interface0_err = 1'd0; wire [3:0] interface0_sel; wire interface0_stb; wire interface0_we; reg [13:0] interface1_adr = 14'd0; wire [13:0] interface1_bank_bus_adr; reg [31:0] interface1_bank_bus_dat_r = 32'd0; wire [31:0] interface1_bank_bus_dat_w; wire interface1_bank_bus_re; wire interface1_bank_bus_we; wire [31:0] interface1_dat_r; reg [31:0] interface1_dat_w = 32'd0; reg interface1_re = 1'd0; reg interface1_we = 1'd0; wire [13:0] interface2_bank_bus_adr; reg [31:0] interface2_bank_bus_dat_r = 32'd0; wire [31:0] interface2_bank_bus_dat_w; wire interface2_bank_bus_re; wire interface2_bank_bus_we; reg [1:0] liteethmacsramreader_next_state = 2'd0; reg [1:0] liteethmacsramreader_state = 2'd0; reg [2:0] liteethmacsramwriter_next_state = 3'd0; reg [2:0] liteethmacsramwriter_state = 3'd0; reg [1:0] liteethphygmiimii_next_state = 2'd0; reg [1:0] liteethphygmiimii_state = 2'd0; reg maccore_ethphy__r_re = 1'd0; reg maccore_ethphy__r_status = 1'd0; wire maccore_ethphy__r_we; reg maccore_ethphy__w_re = 1'd0; reg [2:0] maccore_ethphy__w_storage = 3'd0; reg [8:0] maccore_ethphy_counter = 9'd0; wire maccore_ethphy_counter_ce; wire maccore_ethphy_counter_done; wire maccore_ethphy_data_oe; wire maccore_ethphy_data_r; wire maccore_ethphy_data_w; reg maccore_ethphy_demux_endpoint0_source_first = 1'd0; reg maccore_ethphy_demux_endpoint0_source_last = 1'd0; reg [7:0] maccore_ethphy_demux_endpoint0_source_payload_data = 8'd0; reg maccore_ethphy_demux_endpoint0_source_payload_error = 1'd0; reg maccore_ethphy_demux_endpoint0_source_payload_last_be = 1'd0; wire maccore_ethphy_demux_endpoint0_source_ready; reg maccore_ethphy_demux_endpoint0_source_valid = 1'd0; reg maccore_ethphy_demux_endpoint1_source_first = 1'd0; reg maccore_ethphy_demux_endpoint1_source_last = 1'd0; reg [7:0] maccore_ethphy_demux_endpoint1_source_payload_data = 8'd0; reg maccore_ethphy_demux_endpoint1_source_payload_error = 1'd0; reg maccore_ethphy_demux_endpoint1_source_payload_last_be = 1'd0; wire maccore_ethphy_demux_endpoint1_source_ready; reg maccore_ethphy_demux_endpoint1_source_valid = 1'd0; wire maccore_ethphy_demux_sel; wire maccore_ethphy_demux_sink_first; wire maccore_ethphy_demux_sink_last; wire [7:0] maccore_ethphy_demux_sink_payload_data; wire maccore_ethphy_demux_sink_payload_error; wire maccore_ethphy_demux_sink_payload_last_be; reg maccore_ethphy_demux_sink_ready = 1'd0; wire maccore_ethphy_demux_sink_valid; reg [9:0] maccore_ethphy_eth_counter = 10'd0; wire maccore_ethphy_eth_tick; reg maccore_ethphy_eth_tx_clk = 1'd0; reg maccore_ethphy_gmii_rx_dv_d = 1'd0; reg maccore_ethphy_gmii_rx_source_first = 1'd0; wire maccore_ethphy_gmii_rx_source_last; reg [7:0] maccore_ethphy_gmii_rx_source_payload_data = 8'd0; reg maccore_ethphy_gmii_rx_source_payload_error = 1'd0; reg maccore_ethphy_gmii_rx_source_payload_last_be = 1'd0; wire maccore_ethphy_gmii_rx_source_ready; reg maccore_ethphy_gmii_rx_source_valid = 1'd0; reg [7:0] maccore_ethphy_gmii_tx_pads_tx_data = 8'd0; reg maccore_ethphy_gmii_tx_pads_tx_en = 1'd0; reg maccore_ethphy_gmii_tx_pads_tx_er = 1'd0; wire maccore_ethphy_gmii_tx_sink_first; wire maccore_ethphy_gmii_tx_sink_last; wire [7:0] maccore_ethphy_gmii_tx_sink_payload_data; wire maccore_ethphy_gmii_tx_sink_payload_error; wire maccore_ethphy_gmii_tx_sink_payload_last_be; reg maccore_ethphy_gmii_tx_sink_ready = 1'd0; wire maccore_ethphy_gmii_tx_sink_valid; wire maccore_ethphy_i; wire maccore_ethphy_mdc; reg maccore_ethphy_mii_rx_converter_demux = 1'd0; wire maccore_ethphy_mii_rx_converter_load_part; reg maccore_ethphy_mii_rx_converter_sink_first = 1'd0; wire maccore_ethphy_mii_rx_converter_sink_last; reg [3:0] maccore_ethphy_mii_rx_converter_sink_payload_data = 4'd0; wire maccore_ethphy_mii_rx_converter_sink_ready; reg maccore_ethphy_mii_rx_converter_sink_valid = 1'd0; reg maccore_ethphy_mii_rx_converter_source_first = 1'd0; reg maccore_ethphy_mii_rx_converter_source_last = 1'd0; reg [7:0] maccore_ethphy_mii_rx_converter_source_payload_data = 8'd0; reg [1:0] maccore_ethphy_mii_rx_converter_source_payload_valid_token_count = 2'd0; wire maccore_ethphy_mii_rx_converter_source_ready; wire maccore_ethphy_mii_rx_converter_source_valid; reg maccore_ethphy_mii_rx_converter_strobe_all = 1'd0; reg maccore_ethphy_mii_rx_reset = 1'd0; wire maccore_ethphy_mii_rx_source_first; wire maccore_ethphy_mii_rx_source_last; wire [7:0] maccore_ethphy_mii_rx_source_payload_data; reg maccore_ethphy_mii_rx_source_payload_error = 1'd0; reg maccore_ethphy_mii_rx_source_payload_last_be = 1'd0; wire maccore_ethphy_mii_rx_source_ready; wire maccore_ethphy_mii_rx_source_source_first; wire maccore_ethphy_mii_rx_source_source_last; wire [7:0] maccore_ethphy_mii_rx_source_source_payload_data; wire maccore_ethphy_mii_rx_source_source_ready; wire maccore_ethphy_mii_rx_source_source_valid; wire maccore_ethphy_mii_rx_source_valid; wire maccore_ethphy_mii_tx_converter_first; wire maccore_ethphy_mii_tx_converter_last; reg maccore_ethphy_mii_tx_converter_mux = 1'd0; reg maccore_ethphy_mii_tx_converter_sink_first = 1'd0; reg maccore_ethphy_mii_tx_converter_sink_last = 1'd0; wire [7:0] maccore_ethphy_mii_tx_converter_sink_payload_data; wire maccore_ethphy_mii_tx_converter_sink_ready; wire maccore_ethphy_mii_tx_converter_sink_valid; wire maccore_ethphy_mii_tx_converter_source_first; wire maccore_ethphy_mii_tx_converter_source_last; reg [3:0] maccore_ethphy_mii_tx_converter_source_payload_data = 4'd0; wire maccore_ethphy_mii_tx_converter_source_payload_valid_token_count; wire maccore_ethphy_mii_tx_converter_source_ready; wire maccore_ethphy_mii_tx_converter_source_valid; reg [7:0] maccore_ethphy_mii_tx_pads_tx_data = 8'd0; reg maccore_ethphy_mii_tx_pads_tx_en = 1'd0; reg maccore_ethphy_mii_tx_pads_tx_er = 1'd0; wire maccore_ethphy_mii_tx_sink_first; wire maccore_ethphy_mii_tx_sink_last; wire [7:0] maccore_ethphy_mii_tx_sink_payload_data; wire maccore_ethphy_mii_tx_sink_payload_error; wire maccore_ethphy_mii_tx_sink_payload_last_be; wire maccore_ethphy_mii_tx_sink_ready; wire maccore_ethphy_mii_tx_sink_valid; wire maccore_ethphy_mii_tx_source_source_first; wire maccore_ethphy_mii_tx_source_source_last; wire [3:0] maccore_ethphy_mii_tx_source_source_payload_data; wire maccore_ethphy_mii_tx_source_source_ready; wire maccore_ethphy_mii_tx_source_source_valid; reg maccore_ethphy_mode0 = 1'd0; reg maccore_ethphy_mode1 = 1'd0; reg maccore_ethphy_mode_re = 1'd0; wire maccore_ethphy_mode_status; wire maccore_ethphy_mode_we; wire maccore_ethphy_mux_endpoint0_sink_first; wire maccore_ethphy_mux_endpoint0_sink_last; wire [7:0] maccore_ethphy_mux_endpoint0_sink_payload_data; wire maccore_ethphy_mux_endpoint0_sink_payload_error; wire maccore_ethphy_mux_endpoint0_sink_payload_last_be; reg maccore_ethphy_mux_endpoint0_sink_ready = 1'd0; wire maccore_ethphy_mux_endpoint0_sink_valid; wire maccore_ethphy_mux_endpoint1_sink_first; wire maccore_ethphy_mux_endpoint1_sink_last; wire [7:0] maccore_ethphy_mux_endpoint1_sink_payload_data; wire maccore_ethphy_mux_endpoint1_sink_payload_error; wire maccore_ethphy_mux_endpoint1_sink_payload_last_be; reg maccore_ethphy_mux_endpoint1_sink_ready = 1'd0; wire maccore_ethphy_mux_endpoint1_sink_valid; wire maccore_ethphy_mux_sel; reg maccore_ethphy_mux_source_first = 1'd0; reg maccore_ethphy_mux_source_last = 1'd0; reg [7:0] maccore_ethphy_mux_source_payload_data = 8'd0; reg maccore_ethphy_mux_source_payload_error = 1'd0; reg maccore_ethphy_mux_source_payload_last_be = 1'd0; wire maccore_ethphy_mux_source_ready; reg maccore_ethphy_mux_source_valid = 1'd0; wire maccore_ethphy_o; wire maccore_ethphy_oe; reg [7:0] maccore_ethphy_pads_d_rx_data = 8'd0; reg maccore_ethphy_pads_d_rx_dv = 1'd0; reg maccore_ethphy_r = 1'd0; wire maccore_ethphy_reset0; wire maccore_ethphy_reset1; reg maccore_ethphy_reset_re = 1'd0; reg maccore_ethphy_reset_storage = 1'd0; wire maccore_ethphy_sink_sink_first; wire maccore_ethphy_sink_sink_last; wire [7:0] maccore_ethphy_sink_sink_payload_data; wire maccore_ethphy_sink_sink_payload_error; wire maccore_ethphy_sink_sink_payload_last_be; wire maccore_ethphy_sink_sink_ready; wire maccore_ethphy_sink_sink_valid; wire maccore_ethphy_source_source_first; wire maccore_ethphy_source_source_last; wire [7:0] maccore_ethphy_source_source_payload_data; wire maccore_ethphy_source_source_payload_error; wire maccore_ethphy_source_source_payload_last_be; wire maccore_ethphy_source_source_ready; wire maccore_ethphy_source_source_valid; reg [23:0] maccore_ethphy_sys_counter = 24'd0; reg maccore_ethphy_sys_counter_ce = 1'd0; reg maccore_ethphy_sys_counter_reset = 1'd0; wire maccore_ethphy_sys_tick; reg maccore_ethphy_toggle_i = 1'd0; wire maccore_ethphy_toggle_o; reg maccore_ethphy_toggle_o_r = 1'd0; reg maccore_ethphy_update_mode = 1'd0; wire maccore_ethphy_w; reg maccore_int_rst = 1'd1; wire maccore_maccore_bus_error; reg [31:0] maccore_maccore_bus_errors = 32'd0; reg maccore_maccore_bus_errors_re = 1'd0; wire [31:0] maccore_maccore_bus_errors_status; wire maccore_maccore_bus_errors_we; wire maccore_maccore_cpu_rst; reg maccore_maccore_reset_re = 1'd0; reg [1:0] maccore_maccore_reset_storage = 2'd0; reg maccore_maccore_scratch_re = 1'd0; reg [31:0] maccore_maccore_scratch_storage = 32'd305419896; reg maccore_maccore_soc_rst = 1'd0; wire por_clk; wire re; wire request; wire rst_meta0; wire rst_meta1; reg [1:0] rxdatapath_bufferizeendpoints_next_state = 2'd0; reg [1:0] rxdatapath_bufferizeendpoints_state = 2'd0; reg rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; reg rxdatapath_liteethmacpreamblechecker_state = 1'd0; reg [29:0] self0 = 30'd0; reg [31:0] self1 = 32'd0; reg [3:0] self2 = 4'd0; reg self3 = 1'd0; reg self4 = 1'd0; reg self5 = 1'd0; reg [2:0] self6 = 3'd0; reg [1:0] self7 = 2'd0; reg shared_ack = 1'd0; wire [29:0] shared_adr; wire [1:0] shared_bte; wire [2:0] shared_cti; wire shared_cyc; reg [31:0] shared_dat_r = 32'd0; wire [31:0] shared_dat_w; wire shared_err; wire [3:0] shared_sel; wire shared_stb; wire shared_we; reg [2:0] slave_sel = 3'd0; reg [2:0] slave_sel_r = 3'd0; (* dont_touch = "true" *) wire sys_clk; wire sys_rst; reg [1:0] txdatapath_bufferizeendpoints_next_state = 2'd0; reg [1:0] txdatapath_bufferizeendpoints_state = 2'd0; reg txdatapath_liteethmacgap_next_state = 1'd0; reg txdatapath_liteethmacgap_state = 1'd0; reg txdatapath_liteethmacpaddinginserter_next_state = 1'd0; reg txdatapath_liteethmacpaddinginserter_state = 1'd0; reg [1:0] txdatapath_liteethmacpreambleinserter_next_state = 2'd0; reg [1:0] txdatapath_liteethmacpreambleinserter_state = 2'd0; reg txdatapath_liteethmactxlastbe_next_state = 1'd0; reg txdatapath_liteethmactxlastbe_state = 1'd0; wire wait_1; wire wb_bus_ack; wire [29:0] wb_bus_adr; wire [1:0] wb_bus_bte; wire [2:0] wb_bus_cti; wire wb_bus_cyc; wire [31:0] wb_bus_dat_r; wire [31:0] wb_bus_dat_w; wire wb_bus_err; wire [3:0] wb_bus_sel; wire wb_bus_stb; wire wb_bus_we; wire we; reg wishbone2csr_next_state = 1'd0; reg wishbone2csr_state = 1'd0; wire wishbone_interface_bus_rx_ack; wire [29:0] wishbone_interface_bus_rx_adr; wire [1:0] wishbone_interface_bus_rx_bte; wire [2:0] wishbone_interface_bus_rx_cti; wire wishbone_interface_bus_rx_cyc; wire [31:0] wishbone_interface_bus_rx_dat_r; wire [31:0] wishbone_interface_bus_rx_dat_w; wire wishbone_interface_bus_rx_err; wire [3:0] wishbone_interface_bus_rx_sel; wire wishbone_interface_bus_rx_stb; wire wishbone_interface_bus_rx_we; wire wishbone_interface_bus_tx_ack; wire [29:0] wishbone_interface_bus_tx_adr; wire [1:0] wishbone_interface_bus_tx_bte; wire [2:0] wishbone_interface_bus_tx_cti; wire wishbone_interface_bus_tx_cyc; wire [31:0] wishbone_interface_bus_tx_dat_r; wire [31:0] wishbone_interface_bus_tx_dat_w; wire wishbone_interface_bus_tx_err; wire [3:0] wishbone_interface_bus_tx_sel; wire wishbone_interface_bus_tx_stb; wire wishbone_interface_bus_tx_we; reg [1:0] wishbone_interface_decoder0_slave_sel = 2'd0; reg [1:0] wishbone_interface_decoder0_slave_sel_r = 2'd0; reg [1:0] wishbone_interface_decoder1_slave_sel = 2'd0; reg [1:0] wishbone_interface_decoder1_slave_sel_r = 2'd0; wire wishbone_interface_ev_irq; reg wishbone_interface_interface0_ack = 1'd0; wire [29:0] wishbone_interface_interface0_adr; wire [1:0] wishbone_interface_interface0_bte; wire [2:0] wishbone_interface_interface0_cti; wire wishbone_interface_interface0_cyc; wire [31:0] wishbone_interface_interface0_dat_r; wire [31:0] wishbone_interface_interface0_dat_w; reg wishbone_interface_interface0_err = 1'd0; wire [3:0] wishbone_interface_interface0_sel; wire wishbone_interface_interface0_stb; wire wishbone_interface_interface0_we; reg wishbone_interface_interface1_ack = 1'd0; wire [29:0] wishbone_interface_interface1_adr; wire [1:0] wishbone_interface_interface1_bte; wire [2:0] wishbone_interface_interface1_cti; wire wishbone_interface_interface1_cyc; wire [31:0] wishbone_interface_interface1_dat_r; wire [31:0] wishbone_interface_interface1_dat_w; reg wishbone_interface_interface1_err = 1'd0; wire [3:0] wishbone_interface_interface1_sel; wire wishbone_interface_interface1_stb; wire wishbone_interface_interface1_we; reg wishbone_interface_interface2_ack = 1'd0; wire [29:0] wishbone_interface_interface2_adr; wire [1:0] wishbone_interface_interface2_bte; wire [2:0] wishbone_interface_interface2_cti; wire wishbone_interface_interface2_cyc; wire [31:0] wishbone_interface_interface2_dat_r; wire [31:0] wishbone_interface_interface2_dat_w; reg wishbone_interface_interface2_err = 1'd0; wire [3:0] wishbone_interface_interface2_sel; wire wishbone_interface_interface2_stb; wire wishbone_interface_interface2_we; reg wishbone_interface_interface3_ack = 1'd0; wire [29:0] wishbone_interface_interface3_adr; wire [1:0] wishbone_interface_interface3_bte; wire [2:0] wishbone_interface_interface3_cti; wire wishbone_interface_interface3_cyc; wire [31:0] wishbone_interface_interface3_dat_r; wire [31:0] wishbone_interface_interface3_dat_w; reg wishbone_interface_interface3_err = 1'd0; wire [3:0] wishbone_interface_interface3_sel; wire wishbone_interface_interface3_stb; wire wishbone_interface_interface3_we; reg wishbone_interface_reader_cmd_fifo_consume = 1'd0; wire wishbone_interface_reader_cmd_fifo_do_read; wire wishbone_interface_reader_cmd_fifo_fifo_in_first; wire wishbone_interface_reader_cmd_fifo_fifo_in_last; wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_in_payload_length; wire wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot; wire wishbone_interface_reader_cmd_fifo_fifo_out_first; wire wishbone_interface_reader_cmd_fifo_fifo_out_last; wire [10:0] wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; wire wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; reg [1:0] wishbone_interface_reader_cmd_fifo_level = 2'd0; reg wishbone_interface_reader_cmd_fifo_produce = 1'd0; wire wishbone_interface_reader_cmd_fifo_rdport_adr; wire [13:0] wishbone_interface_reader_cmd_fifo_rdport_dat_r; reg wishbone_interface_reader_cmd_fifo_replace = 1'd0; reg wishbone_interface_reader_cmd_fifo_sink_first = 1'd0; reg wishbone_interface_reader_cmd_fifo_sink_last = 1'd0; wire [10:0] wishbone_interface_reader_cmd_fifo_sink_payload_length; wire wishbone_interface_reader_cmd_fifo_sink_payload_slot; wire wishbone_interface_reader_cmd_fifo_sink_ready; wire wishbone_interface_reader_cmd_fifo_sink_valid; wire wishbone_interface_reader_cmd_fifo_source_first; wire wishbone_interface_reader_cmd_fifo_source_last; wire [10:0] wishbone_interface_reader_cmd_fifo_source_payload_length; wire wishbone_interface_reader_cmd_fifo_source_payload_slot; reg wishbone_interface_reader_cmd_fifo_source_ready = 1'd0; wire wishbone_interface_reader_cmd_fifo_source_valid; wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_din; wire [13:0] wishbone_interface_reader_cmd_fifo_syncfifo_dout; wire wishbone_interface_reader_cmd_fifo_syncfifo_re; wire wishbone_interface_reader_cmd_fifo_syncfifo_readable; wire wishbone_interface_reader_cmd_fifo_syncfifo_we; wire wishbone_interface_reader_cmd_fifo_syncfifo_writable; reg wishbone_interface_reader_cmd_fifo_wrport_adr = 1'd0; wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_r; wire [13:0] wishbone_interface_reader_cmd_fifo_wrport_dat_w; wire wishbone_interface_reader_cmd_fifo_wrport_we; reg wishbone_interface_reader_enable_re = 1'd0; reg wishbone_interface_reader_enable_storage = 1'd0; wire wishbone_interface_reader_event00; wire wishbone_interface_reader_event01; wire wishbone_interface_reader_event02; reg wishbone_interface_reader_eventsourcepulse_clear = 1'd0; reg wishbone_interface_reader_eventsourcepulse_pending = 1'd0; wire wishbone_interface_reader_eventsourcepulse_status; reg wishbone_interface_reader_eventsourcepulse_trigger = 1'd0; wire wishbone_interface_reader_irq; reg [10:0] wishbone_interface_reader_length = 11'd0; reg [10:0] wishbone_interface_reader_length_liteethmacsramreader_next_value = 11'd0; reg wishbone_interface_reader_length_liteethmacsramreader_next_value_ce = 1'd0; reg wishbone_interface_reader_length_re = 1'd0; reg [10:0] wishbone_interface_reader_length_storage = 11'd0; reg wishbone_interface_reader_level_re = 1'd0; wire [1:0] wishbone_interface_reader_level_status; wire wishbone_interface_reader_level_we; wire [8:0] wishbone_interface_reader_memory0_adr; wire [31:0] wishbone_interface_reader_memory0_dat_r; wire wishbone_interface_reader_memory0_re; wire [8:0] wishbone_interface_reader_memory1_adr; wire [31:0] wishbone_interface_reader_memory1_dat_r; wire wishbone_interface_reader_memory1_re; reg wishbone_interface_reader_pending_r = 1'd0; reg wishbone_interface_reader_pending_re = 1'd0; wire wishbone_interface_reader_pending_status; wire wishbone_interface_reader_pending_we; reg [31:0] wishbone_interface_reader_rd_data = 32'd0; reg wishbone_interface_reader_read = 1'd0; reg wishbone_interface_reader_ready_re = 1'd0; wire wishbone_interface_reader_ready_status; wire wishbone_interface_reader_ready_we; reg wishbone_interface_reader_slot_re = 1'd0; reg wishbone_interface_reader_slot_storage = 1'd0; reg wishbone_interface_reader_source_source_first = 1'd0; reg wishbone_interface_reader_source_source_last = 1'd0; wire [31:0] wishbone_interface_reader_source_source_payload_data; reg [3:0] wishbone_interface_reader_source_source_payload_error = 4'd0; reg [3:0] wishbone_interface_reader_source_source_payload_last_be = 4'd0; wire wishbone_interface_reader_source_source_ready; reg wishbone_interface_reader_source_source_valid = 1'd0; wire wishbone_interface_reader_start_r; reg wishbone_interface_reader_start_re = 1'd0; reg wishbone_interface_reader_start_w = 1'd0; reg wishbone_interface_reader_start_we = 1'd0; reg wishbone_interface_reader_status_re = 1'd0; wire wishbone_interface_reader_status_status; wire wishbone_interface_reader_status_we; wire wishbone_interface_sink_first; wire wishbone_interface_sink_last; wire [31:0] wishbone_interface_sink_payload_data; wire [3:0] wishbone_interface_sink_payload_error; wire [3:0] wishbone_interface_sink_payload_last_be; wire wishbone_interface_sink_ready; wire wishbone_interface_sink_valid; wire wishbone_interface_source_first; wire wishbone_interface_source_last; wire [31:0] wishbone_interface_source_payload_data; wire [3:0] wishbone_interface_source_payload_error; wire [3:0] wishbone_interface_source_payload_last_be; wire wishbone_interface_source_ready; wire wishbone_interface_source_valid; wire [8:0] wishbone_interface_sram0_adr; reg wishbone_interface_sram0_adr_burst = 1'd0; wire [31:0] wishbone_interface_sram0_dat_r; wire [8:0] wishbone_interface_sram1_adr; reg wishbone_interface_sram1_adr_burst = 1'd0; wire [31:0] wishbone_interface_sram1_dat_r; wire [8:0] wishbone_interface_sram2_adr; reg wishbone_interface_sram2_adr_burst = 1'd0; wire [31:0] wishbone_interface_sram2_dat_r; wire [31:0] wishbone_interface_sram2_dat_w; reg [3:0] wishbone_interface_sram2_we = 4'd0; wire [8:0] wishbone_interface_sram3_adr; reg wishbone_interface_sram3_adr_burst = 1'd0; wire [31:0] wishbone_interface_sram3_dat_r; wire [31:0] wishbone_interface_sram3_dat_w; reg [3:0] wishbone_interface_sram3_we = 4'd0; wire wishbone_interface_writer_available0; wire wishbone_interface_writer_available1; wire wishbone_interface_writer_available2; reg wishbone_interface_writer_available_clear = 1'd0; wire wishbone_interface_writer_available_pending; wire wishbone_interface_writer_available_status; wire wishbone_interface_writer_available_trigger; reg wishbone_interface_writer_enable_re = 1'd0; reg wishbone_interface_writer_enable_storage = 1'd0; reg wishbone_interface_writer_errors_re = 1'd0; reg [31:0] wishbone_interface_writer_errors_status = 32'd0; reg [31:0] wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value = 32'd0; reg wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce = 1'd0; wire wishbone_interface_writer_errors_we; wire wishbone_interface_writer_irq; reg [10:0] wishbone_interface_writer_length = 11'd0; reg [3:0] wishbone_interface_writer_length_inc = 4'd0; reg [10:0] wishbone_interface_writer_length_liteethmacsramwriter_t_next_value = 11'd0; reg wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce = 1'd0; reg wishbone_interface_writer_length_re = 1'd0; wire [10:0] wishbone_interface_writer_length_status; wire wishbone_interface_writer_length_we; reg [8:0] wishbone_interface_writer_memory0_adr = 9'd0; wire [31:0] wishbone_interface_writer_memory0_dat_r; reg [31:0] wishbone_interface_writer_memory0_dat_w = 32'd0; reg wishbone_interface_writer_memory0_we = 1'd0; reg [8:0] wishbone_interface_writer_memory1_adr = 9'd0; wire [31:0] wishbone_interface_writer_memory1_dat_r; reg [31:0] wishbone_interface_writer_memory1_dat_w = 32'd0; reg wishbone_interface_writer_memory1_we = 1'd0; reg wishbone_interface_writer_pending_r = 1'd0; reg wishbone_interface_writer_pending_re = 1'd0; wire wishbone_interface_writer_pending_status; wire wishbone_interface_writer_pending_we; wire wishbone_interface_writer_sink_sink_first; wire wishbone_interface_writer_sink_sink_last; wire [31:0] wishbone_interface_writer_sink_sink_payload_data; wire [3:0] wishbone_interface_writer_sink_sink_payload_error; wire [3:0] wishbone_interface_writer_sink_sink_payload_last_be; reg wishbone_interface_writer_sink_sink_ready = 1'd1; wire wishbone_interface_writer_sink_sink_valid; reg wishbone_interface_writer_slot = 1'd0; reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value = 1'd0; reg wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce = 1'd0; reg wishbone_interface_writer_slot_re = 1'd0; wire wishbone_interface_writer_slot_status; wire wishbone_interface_writer_slot_we; reg wishbone_interface_writer_stat_fifo_consume = 1'd0; wire wishbone_interface_writer_stat_fifo_do_read; wire wishbone_interface_writer_stat_fifo_fifo_in_first; wire wishbone_interface_writer_stat_fifo_fifo_in_last; wire [10:0] wishbone_interface_writer_stat_fifo_fifo_in_payload_length; wire wishbone_interface_writer_stat_fifo_fifo_in_payload_slot; wire wishbone_interface_writer_stat_fifo_fifo_out_first; wire wishbone_interface_writer_stat_fifo_fifo_out_last; wire [10:0] wishbone_interface_writer_stat_fifo_fifo_out_payload_length; wire wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; reg [1:0] wishbone_interface_writer_stat_fifo_level = 2'd0; reg wishbone_interface_writer_stat_fifo_produce = 1'd0; wire wishbone_interface_writer_stat_fifo_rdport_adr; wire [13:0] wishbone_interface_writer_stat_fifo_rdport_dat_r; reg wishbone_interface_writer_stat_fifo_replace = 1'd0; reg wishbone_interface_writer_stat_fifo_sink_first = 1'd0; reg wishbone_interface_writer_stat_fifo_sink_last = 1'd0; reg [10:0] wishbone_interface_writer_stat_fifo_sink_payload_length = 11'd0; reg wishbone_interface_writer_stat_fifo_sink_payload_slot = 1'd0; wire wishbone_interface_writer_stat_fifo_sink_ready; reg wishbone_interface_writer_stat_fifo_sink_valid = 1'd0; wire wishbone_interface_writer_stat_fifo_source_first; wire wishbone_interface_writer_stat_fifo_source_last; wire [10:0] wishbone_interface_writer_stat_fifo_source_payload_length; wire wishbone_interface_writer_stat_fifo_source_payload_slot; wire wishbone_interface_writer_stat_fifo_source_ready; wire wishbone_interface_writer_stat_fifo_source_valid; wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_din; wire [13:0] wishbone_interface_writer_stat_fifo_syncfifo_dout; wire wishbone_interface_writer_stat_fifo_syncfifo_re; wire wishbone_interface_writer_stat_fifo_syncfifo_readable; wire wishbone_interface_writer_stat_fifo_syncfifo_we; wire wishbone_interface_writer_stat_fifo_syncfifo_writable; reg wishbone_interface_writer_stat_fifo_wrport_adr = 1'd0; wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_r; wire [13:0] wishbone_interface_writer_stat_fifo_wrport_dat_w; wire wishbone_interface_writer_stat_fifo_wrport_we; reg wishbone_interface_writer_status_re = 1'd0; wire wishbone_interface_writer_status_status; wire wishbone_interface_writer_status_we; wire [31:0] wishbone_interface_writer_wr_data; reg wishbone_interface_writer_write = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl00 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl01 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl10 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl11 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl20 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl21 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl30 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl31 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl40 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl41 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl50 = 1'd0; (* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl51 = 1'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl60 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl61 = 6'd0; (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl70 = 6'd0; (* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl71 = 6'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ assign wb_bus_adr = wishbone_adr; assign wb_bus_dat_w = wishbone_dat_w; assign wishbone_dat_r = wb_bus_dat_r; assign wb_bus_sel = wishbone_sel; assign wb_bus_cyc = wishbone_cyc; assign wb_bus_stb = wishbone_stb; assign wishbone_ack = wb_bus_ack; assign wb_bus_we = wishbone_we; assign wb_bus_cti = wishbone_cti; assign wb_bus_bte = wishbone_bte; assign wishbone_err = wb_bus_err; assign interrupt = wishbone_interface_ev_irq; assign maccore_maccore_bus_error = error; assign shared_adr = self0; assign shared_dat_w = self1; assign shared_sel = self2; assign shared_cyc = self3; assign shared_stb = self4; assign shared_we = self5; assign shared_cti = self6; assign shared_bte = self7; assign wb_bus_dat_r = shared_dat_r; assign wb_bus_ack = (shared_ack & (grant == 1'd0)); assign wb_bus_err = (shared_err & (grant == 1'd0)); assign request = {wb_bus_cyc}; assign grant = 1'd0; always @(*) begin slave_sel <= 3'd0; slave_sel[0] <= (shared_adr[29:10] == 5'd16); slave_sel[1] <= (shared_adr[29:10] == 5'd17); slave_sel[2] <= (shared_adr[29:14] == 1'd0); end assign wishbone_interface_bus_rx_adr = shared_adr; assign wishbone_interface_bus_rx_dat_w = shared_dat_w; assign wishbone_interface_bus_rx_sel = shared_sel; assign wishbone_interface_bus_rx_stb = shared_stb; assign wishbone_interface_bus_rx_we = shared_we; assign wishbone_interface_bus_rx_cti = shared_cti; assign wishbone_interface_bus_rx_bte = shared_bte; assign wishbone_interface_bus_tx_adr = shared_adr; assign wishbone_interface_bus_tx_dat_w = shared_dat_w; assign wishbone_interface_bus_tx_sel = shared_sel; assign wishbone_interface_bus_tx_stb = shared_stb; assign wishbone_interface_bus_tx_we = shared_we; assign wishbone_interface_bus_tx_cti = shared_cti; assign wishbone_interface_bus_tx_bte = shared_bte; assign interface0_adr = shared_adr; assign interface0_dat_w = shared_dat_w; assign interface0_sel = shared_sel; assign interface0_stb = shared_stb; assign interface0_we = shared_we; assign interface0_cti = shared_cti; assign interface0_bte = shared_bte; assign wishbone_interface_bus_rx_cyc = (shared_cyc & slave_sel[0]); assign wishbone_interface_bus_tx_cyc = (shared_cyc & slave_sel[1]); assign interface0_cyc = (shared_cyc & slave_sel[2]); assign shared_err = ((wishbone_interface_bus_rx_err | wishbone_interface_bus_tx_err) | interface0_err); assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); always @(*) begin error <= 1'd0; shared_ack <= 1'd0; shared_dat_r <= 32'd0; shared_ack <= ((wishbone_interface_bus_rx_ack | wishbone_interface_bus_tx_ack) | interface0_ack); shared_dat_r <= ((({32{slave_sel_r[0]}} & wishbone_interface_bus_rx_dat_r) | ({32{slave_sel_r[1]}} & wishbone_interface_bus_tx_dat_r)) | ({32{slave_sel_r[2]}} & interface0_dat_r)); if (done) begin shared_dat_r <= 32'd4294967295; shared_ack <= 1'd1; error <= 1'd1; end end assign done = (count == 1'd0); assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; assign sys_rst = maccore_int_rst; assign maccore_ethphy_mode_status = maccore_ethphy_mode0; assign maccore_ethphy_eth_tick = (maccore_ethphy_eth_counter == 1'd0); assign maccore_ethphy_i = maccore_ethphy_eth_tick; assign maccore_ethphy_sys_tick = maccore_ethphy_o; assign maccore_ethphy_o = (maccore_ethphy_toggle_o ^ maccore_ethphy_toggle_o_r); always @(*) begin liteethphygmiimii_next_state <= 2'd0; maccore_ethphy_mode1 <= 1'd0; maccore_ethphy_sys_counter_ce <= 1'd0; maccore_ethphy_sys_counter_reset <= 1'd0; maccore_ethphy_update_mode <= 1'd0; liteethphygmiimii_next_state <= liteethphygmiimii_state; case (liteethphygmiimii_state) 1'd1: begin maccore_ethphy_sys_counter_ce <= 1'd1; if (maccore_ethphy_sys_tick) begin liteethphygmiimii_next_state <= 2'd2; end end 2'd2: begin maccore_ethphy_update_mode <= 1'd1; if ((maccore_ethphy_sys_counter > 10'd860)) begin maccore_ethphy_mode1 <= 1'd1; end else begin maccore_ethphy_mode1 <= 1'd0; end liteethphygmiimii_next_state <= 1'd0; end default: begin maccore_ethphy_sys_counter_reset <= 1'd1; if (maccore_ethphy_sys_tick) begin liteethphygmiimii_next_state <= 1'd1; end end endcase end always @(*) begin maccore_ethphy_eth_tx_clk <= 1'd0; if ((maccore_ethphy_mode0 == 1'd1)) begin maccore_ethphy_eth_tx_clk <= gmii_clocks_tx; end else begin maccore_ethphy_eth_tx_clk <= gmii_clocks_rx; end end assign maccore_ethphy_reset0 = (maccore_ethphy_reset_storage | maccore_ethphy_reset1); assign gmii_rst_n = (~maccore_ethphy_reset0); assign maccore_ethphy_counter_done = (maccore_ethphy_counter == 9'd256); assign maccore_ethphy_counter_ce = (~maccore_ethphy_counter_done); assign maccore_ethphy_reset1 = (~maccore_ethphy_counter_done); assign maccore_ethphy_demux_sel = (maccore_ethphy_mode0 == 1'd1); assign maccore_ethphy_demux_sink_valid = maccore_ethphy_sink_sink_valid; assign maccore_ethphy_sink_sink_ready = maccore_ethphy_demux_sink_ready; assign maccore_ethphy_demux_sink_first = maccore_ethphy_sink_sink_first; assign maccore_ethphy_demux_sink_last = maccore_ethphy_sink_sink_last; assign maccore_ethphy_demux_sink_payload_data = maccore_ethphy_sink_sink_payload_data; assign maccore_ethphy_demux_sink_payload_last_be = maccore_ethphy_sink_sink_payload_last_be; assign maccore_ethphy_demux_sink_payload_error = maccore_ethphy_sink_sink_payload_error; assign maccore_ethphy_gmii_tx_sink_valid = maccore_ethphy_demux_endpoint0_source_valid; assign maccore_ethphy_demux_endpoint0_source_ready = maccore_ethphy_gmii_tx_sink_ready; assign maccore_ethphy_gmii_tx_sink_first = maccore_ethphy_demux_endpoint0_source_first; assign maccore_ethphy_gmii_tx_sink_last = maccore_ethphy_demux_endpoint0_source_last; assign maccore_ethphy_gmii_tx_sink_payload_data = maccore_ethphy_demux_endpoint0_source_payload_data; assign maccore_ethphy_gmii_tx_sink_payload_last_be = maccore_ethphy_demux_endpoint0_source_payload_last_be; assign maccore_ethphy_gmii_tx_sink_payload_error = maccore_ethphy_demux_endpoint0_source_payload_error; assign maccore_ethphy_mii_tx_sink_valid = maccore_ethphy_demux_endpoint1_source_valid; assign maccore_ethphy_demux_endpoint1_source_ready = maccore_ethphy_mii_tx_sink_ready; assign maccore_ethphy_mii_tx_sink_first = maccore_ethphy_demux_endpoint1_source_first; assign maccore_ethphy_mii_tx_sink_last = maccore_ethphy_demux_endpoint1_source_last; assign maccore_ethphy_mii_tx_sink_payload_data = maccore_ethphy_demux_endpoint1_source_payload_data; assign maccore_ethphy_mii_tx_sink_payload_last_be = maccore_ethphy_demux_endpoint1_source_payload_last_be; assign maccore_ethphy_mii_tx_sink_payload_error = maccore_ethphy_demux_endpoint1_source_payload_error; assign gmii_tx_er = 1'd0; assign maccore_ethphy_mii_tx_converter_sink_valid = maccore_ethphy_mii_tx_sink_valid; assign maccore_ethphy_mii_tx_converter_sink_payload_data = maccore_ethphy_mii_tx_sink_payload_data; assign maccore_ethphy_mii_tx_sink_ready = maccore_ethphy_mii_tx_converter_sink_ready; assign maccore_ethphy_mii_tx_source_source_ready = 1'd1; assign maccore_ethphy_mii_tx_source_source_valid = maccore_ethphy_mii_tx_converter_source_valid; assign maccore_ethphy_mii_tx_converter_source_ready = maccore_ethphy_mii_tx_source_source_ready; assign maccore_ethphy_mii_tx_source_source_first = maccore_ethphy_mii_tx_converter_source_first; assign maccore_ethphy_mii_tx_source_source_last = maccore_ethphy_mii_tx_converter_source_last; assign maccore_ethphy_mii_tx_source_source_payload_data = maccore_ethphy_mii_tx_converter_source_payload_data; assign maccore_ethphy_mii_tx_converter_first = (maccore_ethphy_mii_tx_converter_mux == 1'd0); assign maccore_ethphy_mii_tx_converter_last = (maccore_ethphy_mii_tx_converter_mux == 1'd1); assign maccore_ethphy_mii_tx_converter_source_valid = maccore_ethphy_mii_tx_converter_sink_valid; assign maccore_ethphy_mii_tx_converter_source_first = (maccore_ethphy_mii_tx_converter_sink_first & maccore_ethphy_mii_tx_converter_first); assign maccore_ethphy_mii_tx_converter_source_last = (maccore_ethphy_mii_tx_converter_sink_last & maccore_ethphy_mii_tx_converter_last); assign maccore_ethphy_mii_tx_converter_sink_ready = (maccore_ethphy_mii_tx_converter_last & maccore_ethphy_mii_tx_converter_source_ready); always @(*) begin maccore_ethphy_mii_tx_converter_source_payload_data <= 4'd0; case (maccore_ethphy_mii_tx_converter_mux) 1'd0: begin maccore_ethphy_mii_tx_converter_source_payload_data <= maccore_ethphy_mii_tx_converter_sink_payload_data[3:0]; end default: begin maccore_ethphy_mii_tx_converter_source_payload_data <= maccore_ethphy_mii_tx_converter_sink_payload_data[7:4]; end endcase end assign maccore_ethphy_mii_tx_converter_source_payload_valid_token_count = maccore_ethphy_mii_tx_converter_last; always @(*) begin maccore_ethphy_demux_endpoint0_source_first <= 1'd0; maccore_ethphy_demux_endpoint0_source_last <= 1'd0; maccore_ethphy_demux_endpoint0_source_payload_data <= 8'd0; maccore_ethphy_demux_endpoint0_source_payload_error <= 1'd0; maccore_ethphy_demux_endpoint0_source_payload_last_be <= 1'd0; maccore_ethphy_demux_endpoint0_source_valid <= 1'd0; maccore_ethphy_demux_endpoint1_source_first <= 1'd0; maccore_ethphy_demux_endpoint1_source_last <= 1'd0; maccore_ethphy_demux_endpoint1_source_payload_data <= 8'd0; maccore_ethphy_demux_endpoint1_source_payload_error <= 1'd0; maccore_ethphy_demux_endpoint1_source_payload_last_be <= 1'd0; maccore_ethphy_demux_endpoint1_source_valid <= 1'd0; maccore_ethphy_demux_sink_ready <= 1'd0; case (maccore_ethphy_demux_sel) 1'd0: begin maccore_ethphy_demux_endpoint0_source_valid <= maccore_ethphy_demux_sink_valid; maccore_ethphy_demux_sink_ready <= maccore_ethphy_demux_endpoint0_source_ready; maccore_ethphy_demux_endpoint0_source_first <= maccore_ethphy_demux_sink_first; maccore_ethphy_demux_endpoint0_source_last <= maccore_ethphy_demux_sink_last; maccore_ethphy_demux_endpoint0_source_payload_data <= maccore_ethphy_demux_sink_payload_data; maccore_ethphy_demux_endpoint0_source_payload_last_be <= maccore_ethphy_demux_sink_payload_last_be; maccore_ethphy_demux_endpoint0_source_payload_error <= maccore_ethphy_demux_sink_payload_error; end 1'd1: begin maccore_ethphy_demux_endpoint1_source_valid <= maccore_ethphy_demux_sink_valid; maccore_ethphy_demux_sink_ready <= maccore_ethphy_demux_endpoint1_source_ready; maccore_ethphy_demux_endpoint1_source_first <= maccore_ethphy_demux_sink_first; maccore_ethphy_demux_endpoint1_source_last <= maccore_ethphy_demux_sink_last; maccore_ethphy_demux_endpoint1_source_payload_data <= maccore_ethphy_demux_sink_payload_data; maccore_ethphy_demux_endpoint1_source_payload_last_be <= maccore_ethphy_demux_sink_payload_last_be; maccore_ethphy_demux_endpoint1_source_payload_error <= maccore_ethphy_demux_sink_payload_error; end endcase end assign maccore_ethphy_mux_sel = (maccore_ethphy_mode0 == 1'd1); assign maccore_ethphy_mux_endpoint0_sink_valid = maccore_ethphy_gmii_rx_source_valid; assign maccore_ethphy_gmii_rx_source_ready = maccore_ethphy_mux_endpoint0_sink_ready; assign maccore_ethphy_mux_endpoint0_sink_first = maccore_ethphy_gmii_rx_source_first; assign maccore_ethphy_mux_endpoint0_sink_last = maccore_ethphy_gmii_rx_source_last; assign maccore_ethphy_mux_endpoint0_sink_payload_data = maccore_ethphy_gmii_rx_source_payload_data; assign maccore_ethphy_mux_endpoint0_sink_payload_last_be = maccore_ethphy_gmii_rx_source_payload_last_be; assign maccore_ethphy_mux_endpoint0_sink_payload_error = maccore_ethphy_gmii_rx_source_payload_error; assign maccore_ethphy_mux_endpoint1_sink_valid = maccore_ethphy_mii_rx_source_valid; assign maccore_ethphy_mii_rx_source_ready = maccore_ethphy_mux_endpoint1_sink_ready; assign maccore_ethphy_mux_endpoint1_sink_first = maccore_ethphy_mii_rx_source_first; assign maccore_ethphy_mux_endpoint1_sink_last = maccore_ethphy_mii_rx_source_last; assign maccore_ethphy_mux_endpoint1_sink_payload_data = maccore_ethphy_mii_rx_source_payload_data; assign maccore_ethphy_mux_endpoint1_sink_payload_last_be = maccore_ethphy_mii_rx_source_payload_last_be; assign maccore_ethphy_mux_endpoint1_sink_payload_error = maccore_ethphy_mii_rx_source_payload_error; assign maccore_ethphy_source_source_valid = maccore_ethphy_mux_source_valid; assign maccore_ethphy_mux_source_ready = maccore_ethphy_source_source_ready; assign maccore_ethphy_source_source_first = maccore_ethphy_mux_source_first; assign maccore_ethphy_source_source_last = maccore_ethphy_mux_source_last; assign maccore_ethphy_source_source_payload_data = maccore_ethphy_mux_source_payload_data; assign maccore_ethphy_source_source_payload_last_be = maccore_ethphy_mux_source_payload_last_be; assign maccore_ethphy_source_source_payload_error = maccore_ethphy_mux_source_payload_error; assign maccore_ethphy_gmii_rx_source_last = ((~maccore_ethphy_pads_d_rx_dv) & maccore_ethphy_gmii_rx_dv_d); assign maccore_ethphy_mii_rx_converter_sink_last = (~maccore_ethphy_pads_d_rx_dv); assign maccore_ethphy_mii_rx_source_valid = maccore_ethphy_mii_rx_source_source_valid; assign maccore_ethphy_mii_rx_source_source_ready = maccore_ethphy_mii_rx_source_ready; assign maccore_ethphy_mii_rx_source_first = maccore_ethphy_mii_rx_source_source_first; assign maccore_ethphy_mii_rx_source_last = maccore_ethphy_mii_rx_source_source_last; assign maccore_ethphy_mii_rx_source_payload_data = maccore_ethphy_mii_rx_source_source_payload_data; assign maccore_ethphy_mii_rx_source_source_valid = maccore_ethphy_mii_rx_converter_source_valid; assign maccore_ethphy_mii_rx_converter_source_ready = maccore_ethphy_mii_rx_source_source_ready; assign maccore_ethphy_mii_rx_source_source_first = maccore_ethphy_mii_rx_converter_source_first; assign maccore_ethphy_mii_rx_source_source_last = maccore_ethphy_mii_rx_converter_source_last; assign maccore_ethphy_mii_rx_source_source_payload_data = maccore_ethphy_mii_rx_converter_source_payload_data; assign maccore_ethphy_mii_rx_converter_sink_ready = ((~maccore_ethphy_mii_rx_converter_strobe_all) | maccore_ethphy_mii_rx_converter_source_ready); assign maccore_ethphy_mii_rx_converter_source_valid = maccore_ethphy_mii_rx_converter_strobe_all; assign maccore_ethphy_mii_rx_converter_load_part = (maccore_ethphy_mii_rx_converter_sink_valid & maccore_ethphy_mii_rx_converter_sink_ready); always @(*) begin maccore_ethphy_mux_endpoint0_sink_ready <= 1'd0; maccore_ethphy_mux_endpoint1_sink_ready <= 1'd0; maccore_ethphy_mux_source_first <= 1'd0; maccore_ethphy_mux_source_last <= 1'd0; maccore_ethphy_mux_source_payload_data <= 8'd0; maccore_ethphy_mux_source_payload_error <= 1'd0; maccore_ethphy_mux_source_payload_last_be <= 1'd0; maccore_ethphy_mux_source_valid <= 1'd0; case (maccore_ethphy_mux_sel) 1'd0: begin maccore_ethphy_mux_source_valid <= maccore_ethphy_mux_endpoint0_sink_valid; maccore_ethphy_mux_endpoint0_sink_ready <= maccore_ethphy_mux_source_ready; maccore_ethphy_mux_source_first <= maccore_ethphy_mux_endpoint0_sink_first; maccore_ethphy_mux_source_last <= maccore_ethphy_mux_endpoint0_sink_last; maccore_ethphy_mux_source_payload_data <= maccore_ethphy_mux_endpoint0_sink_payload_data; maccore_ethphy_mux_source_payload_last_be <= maccore_ethphy_mux_endpoint0_sink_payload_last_be; maccore_ethphy_mux_source_payload_error <= maccore_ethphy_mux_endpoint0_sink_payload_error; end 1'd1: begin maccore_ethphy_mux_source_valid <= maccore_ethphy_mux_endpoint1_sink_valid; maccore_ethphy_mux_endpoint1_sink_ready <= maccore_ethphy_mux_source_ready; maccore_ethphy_mux_source_first <= maccore_ethphy_mux_endpoint1_sink_first; maccore_ethphy_mux_source_last <= maccore_ethphy_mux_endpoint1_sink_last; maccore_ethphy_mux_source_payload_data <= maccore_ethphy_mux_endpoint1_sink_payload_data; maccore_ethphy_mux_source_payload_last_be <= maccore_ethphy_mux_endpoint1_sink_payload_last_be; maccore_ethphy_mux_source_payload_error <= maccore_ethphy_mux_endpoint1_sink_payload_error; end endcase end assign gmii_mdc = maccore_ethphy__w_storage[0]; assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1]; assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2]; assign core_sink_valid = wishbone_interface_source_valid; assign wishbone_interface_source_ready = core_sink_ready; assign core_sink_first = wishbone_interface_source_first; assign core_sink_last = wishbone_interface_source_last; assign core_sink_payload_data = wishbone_interface_source_payload_data; assign core_sink_payload_last_be = wishbone_interface_source_payload_last_be; assign core_sink_payload_error = wishbone_interface_source_payload_error; assign wishbone_interface_sink_valid = core_source_valid; assign core_source_ready = wishbone_interface_sink_ready; assign wishbone_interface_sink_first = core_source_first; assign wishbone_interface_sink_last = core_source_last; assign wishbone_interface_sink_payload_data = core_source_payload_data; assign wishbone_interface_sink_payload_last_be = core_source_payload_last_be; assign wishbone_interface_sink_payload_error = core_source_payload_error; assign core_tx_cdc_cdc_sink_valid = core_tx_cdc_sink_sink_valid; assign core_tx_cdc_sink_sink_ready = core_tx_cdc_cdc_sink_ready; assign core_tx_cdc_cdc_sink_first = core_tx_cdc_sink_sink_first; assign core_tx_cdc_cdc_sink_last = core_tx_cdc_sink_sink_last; assign core_tx_cdc_cdc_sink_payload_data = core_tx_cdc_sink_sink_payload_data; assign core_tx_cdc_cdc_sink_payload_last_be = core_tx_cdc_sink_sink_payload_last_be; assign core_tx_cdc_cdc_sink_payload_error = core_tx_cdc_sink_sink_payload_error; assign core_tx_cdc_source_source_valid = core_tx_cdc_cdc_source_valid; assign core_tx_cdc_cdc_source_ready = core_tx_cdc_source_source_ready; assign core_tx_cdc_source_source_first = core_tx_cdc_cdc_source_first; assign core_tx_cdc_source_source_last = core_tx_cdc_cdc_source_last; assign core_tx_cdc_source_source_payload_data = core_tx_cdc_cdc_source_payload_data; assign core_tx_cdc_source_source_payload_last_be = core_tx_cdc_cdc_source_payload_last_be; assign core_tx_cdc_source_source_payload_error = core_tx_cdc_cdc_source_payload_error; assign core_tx_cdc_cdc_asyncfifo_din = {core_tx_cdc_cdc_fifo_in_last, core_tx_cdc_cdc_fifo_in_first, core_tx_cdc_cdc_fifo_in_payload_error, core_tx_cdc_cdc_fifo_in_payload_last_be, core_tx_cdc_cdc_fifo_in_payload_data}; assign {core_tx_cdc_cdc_fifo_out_last, core_tx_cdc_cdc_fifo_out_first, core_tx_cdc_cdc_fifo_out_payload_error, core_tx_cdc_cdc_fifo_out_payload_last_be, core_tx_cdc_cdc_fifo_out_payload_data} = core_tx_cdc_cdc_asyncfifo_dout; assign core_tx_cdc_cdc_sink_ready = core_tx_cdc_cdc_asyncfifo_writable; assign core_tx_cdc_cdc_asyncfifo_we = core_tx_cdc_cdc_sink_valid; assign core_tx_cdc_cdc_fifo_in_first = core_tx_cdc_cdc_sink_first; assign core_tx_cdc_cdc_fifo_in_last = core_tx_cdc_cdc_sink_last; assign core_tx_cdc_cdc_fifo_in_payload_data = core_tx_cdc_cdc_sink_payload_data; assign core_tx_cdc_cdc_fifo_in_payload_last_be = core_tx_cdc_cdc_sink_payload_last_be; assign core_tx_cdc_cdc_fifo_in_payload_error = core_tx_cdc_cdc_sink_payload_error; assign core_tx_cdc_cdc_source_valid = core_tx_cdc_cdc_asyncfifo_readable; assign core_tx_cdc_cdc_source_first = core_tx_cdc_cdc_fifo_out_first; assign core_tx_cdc_cdc_source_last = core_tx_cdc_cdc_fifo_out_last; assign core_tx_cdc_cdc_source_payload_data = core_tx_cdc_cdc_fifo_out_payload_data; assign core_tx_cdc_cdc_source_payload_last_be = core_tx_cdc_cdc_fifo_out_payload_last_be; assign core_tx_cdc_cdc_source_payload_error = core_tx_cdc_cdc_fifo_out_payload_error; assign core_tx_cdc_cdc_asyncfifo_re = core_tx_cdc_cdc_source_ready; assign core_tx_cdc_cdc_graycounter0_ce = (core_tx_cdc_cdc_asyncfifo_writable & core_tx_cdc_cdc_asyncfifo_we); assign core_tx_cdc_cdc_graycounter1_ce = (core_tx_cdc_cdc_asyncfifo_readable & core_tx_cdc_cdc_asyncfifo_re); assign core_tx_cdc_cdc_asyncfifo_writable = (((core_tx_cdc_cdc_graycounter0_q[5] == core_tx_cdc_cdc_consume_wdomain[5]) | (core_tx_cdc_cdc_graycounter0_q[4] == core_tx_cdc_cdc_consume_wdomain[4])) | (core_tx_cdc_cdc_graycounter0_q[3:0] != core_tx_cdc_cdc_consume_wdomain[3:0])); assign core_tx_cdc_cdc_asyncfifo_readable = (core_tx_cdc_cdc_graycounter1_q != core_tx_cdc_cdc_produce_rdomain); assign core_tx_cdc_cdc_wrport_adr = core_tx_cdc_cdc_graycounter0_q_binary[4:0]; assign core_tx_cdc_cdc_wrport_dat_w = core_tx_cdc_cdc_asyncfifo_din; assign core_tx_cdc_cdc_wrport_we = core_tx_cdc_cdc_graycounter0_ce; assign core_tx_cdc_cdc_rdport_adr = core_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign core_tx_cdc_cdc_asyncfifo_dout = core_tx_cdc_cdc_rdport_dat_r; always @(*) begin core_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; if (core_tx_cdc_cdc_graycounter0_ce) begin core_tx_cdc_cdc_graycounter0_q_next_binary <= (core_tx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin core_tx_cdc_cdc_graycounter0_q_next_binary <= core_tx_cdc_cdc_graycounter0_q_binary; end end assign core_tx_cdc_cdc_graycounter0_q_next = (core_tx_cdc_cdc_graycounter0_q_next_binary ^ core_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin core_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; if (core_tx_cdc_cdc_graycounter1_ce) begin core_tx_cdc_cdc_graycounter1_q_next_binary <= (core_tx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin core_tx_cdc_cdc_graycounter1_q_next_binary <= core_tx_cdc_cdc_graycounter1_q_binary; end end assign core_tx_cdc_cdc_graycounter1_q_next = (core_tx_cdc_cdc_graycounter1_q_next_binary ^ core_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign core_tx_converter_converter_sink_valid = core_tx_converter_sink_valid; assign core_tx_converter_converter_sink_first = core_tx_converter_sink_first; assign core_tx_converter_converter_sink_last = core_tx_converter_sink_last; assign core_tx_converter_sink_ready = core_tx_converter_converter_sink_ready; always @(*) begin core_tx_converter_converter_sink_payload_data <= 40'd0; core_tx_converter_converter_sink_payload_data[7:0] <= core_tx_converter_sink_payload_data[7:0]; core_tx_converter_converter_sink_payload_data[8] <= core_tx_converter_sink_payload_last_be[0]; core_tx_converter_converter_sink_payload_data[9] <= core_tx_converter_sink_payload_error[0]; core_tx_converter_converter_sink_payload_data[17:10] <= core_tx_converter_sink_payload_data[15:8]; core_tx_converter_converter_sink_payload_data[18] <= core_tx_converter_sink_payload_last_be[1]; core_tx_converter_converter_sink_payload_data[19] <= core_tx_converter_sink_payload_error[1]; core_tx_converter_converter_sink_payload_data[27:20] <= core_tx_converter_sink_payload_data[23:16]; core_tx_converter_converter_sink_payload_data[28] <= core_tx_converter_sink_payload_last_be[2]; core_tx_converter_converter_sink_payload_data[29] <= core_tx_converter_sink_payload_error[2]; core_tx_converter_converter_sink_payload_data[37:30] <= core_tx_converter_sink_payload_data[31:24]; core_tx_converter_converter_sink_payload_data[38] <= core_tx_converter_sink_payload_last_be[3]; core_tx_converter_converter_sink_payload_data[39] <= core_tx_converter_sink_payload_error[3]; end assign core_tx_converter_source_valid = core_tx_converter_source_source_valid; assign core_tx_converter_source_first = core_tx_converter_source_source_first; assign core_tx_converter_source_last = core_tx_converter_source_source_last; assign core_tx_converter_source_source_ready = core_tx_converter_source_ready; assign {core_tx_converter_source_payload_error, core_tx_converter_source_payload_last_be, core_tx_converter_source_payload_data} = core_tx_converter_source_source_payload_data; assign core_tx_converter_source_source_valid = core_tx_converter_converter_source_valid; assign core_tx_converter_converter_source_ready = core_tx_converter_source_source_ready; assign core_tx_converter_source_source_first = core_tx_converter_converter_source_first; assign core_tx_converter_source_source_last = core_tx_converter_converter_source_last; assign core_tx_converter_source_source_payload_data = core_tx_converter_converter_source_payload_data; assign core_tx_converter_converter_first = (core_tx_converter_converter_mux == 1'd0); assign core_tx_converter_converter_last = (core_tx_converter_converter_mux == 2'd3); assign core_tx_converter_converter_source_valid = core_tx_converter_converter_sink_valid; assign core_tx_converter_converter_source_first = (core_tx_converter_converter_sink_first & core_tx_converter_converter_first); assign core_tx_converter_converter_source_last = (core_tx_converter_converter_sink_last & core_tx_converter_converter_last); assign core_tx_converter_converter_sink_ready = (core_tx_converter_converter_last & core_tx_converter_converter_source_ready); always @(*) begin core_tx_converter_converter_source_payload_data <= 10'd0; case (core_tx_converter_converter_mux) 1'd0: begin core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[9:0]; end 1'd1: begin core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[19:10]; end 2'd2: begin core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[29:20]; end default: begin core_tx_converter_converter_source_payload_data <= core_tx_converter_converter_sink_payload_data[39:30]; end endcase end assign core_tx_converter_converter_source_payload_valid_token_count = core_tx_converter_converter_last; assign core_tx_last_be_last_handler_sink_valid = core_tx_last_be_sink_sink_valid; assign core_tx_last_be_sink_sink_ready = core_tx_last_be_last_handler_sink_ready; assign core_tx_last_be_last_handler_sink_first = core_tx_last_be_sink_sink_first; assign core_tx_last_be_last_handler_sink_last = core_tx_last_be_sink_sink_last; assign core_tx_last_be_last_handler_sink_payload_data = core_tx_last_be_sink_sink_payload_data; assign core_tx_last_be_last_handler_sink_payload_last_be = core_tx_last_be_sink_sink_payload_last_be; assign core_tx_last_be_last_handler_sink_payload_error = core_tx_last_be_sink_sink_payload_error; assign core_tx_last_be_source_source_valid = core_tx_last_be_last_handler_source_valid; assign core_tx_last_be_last_handler_source_ready = core_tx_last_be_source_source_ready; assign core_tx_last_be_source_source_first = core_tx_last_be_last_handler_source_first; assign core_tx_last_be_source_source_last = core_tx_last_be_last_handler_source_last; assign core_tx_last_be_source_source_payload_data = core_tx_last_be_last_handler_source_payload_data; assign core_tx_last_be_source_source_payload_last_be = core_tx_last_be_last_handler_source_payload_last_be; assign core_tx_last_be_source_source_payload_error = core_tx_last_be_last_handler_source_payload_error; always @(*) begin core_tx_last_be_last_handler_sink_ready <= 1'd0; core_tx_last_be_last_handler_source_first <= 1'd0; core_tx_last_be_last_handler_source_last <= 1'd0; core_tx_last_be_last_handler_source_payload_data <= 8'd0; core_tx_last_be_last_handler_source_payload_error <= 1'd0; core_tx_last_be_last_handler_source_payload_last_be <= 1'd0; core_tx_last_be_last_handler_source_valid <= 1'd0; txdatapath_liteethmactxlastbe_next_state <= 1'd0; txdatapath_liteethmactxlastbe_next_state <= txdatapath_liteethmactxlastbe_state; case (txdatapath_liteethmactxlastbe_state) 1'd1: begin core_tx_last_be_last_handler_sink_ready <= 1'd1; if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_last)) begin txdatapath_liteethmactxlastbe_next_state <= 1'd0; end end default: begin core_tx_last_be_last_handler_source_valid <= core_tx_last_be_last_handler_sink_valid; core_tx_last_be_last_handler_sink_ready <= core_tx_last_be_last_handler_source_ready; core_tx_last_be_last_handler_source_first <= core_tx_last_be_last_handler_sink_first; core_tx_last_be_last_handler_source_last <= core_tx_last_be_last_handler_sink_last; core_tx_last_be_last_handler_source_payload_data <= core_tx_last_be_last_handler_sink_payload_data; core_tx_last_be_last_handler_source_payload_last_be <= core_tx_last_be_last_handler_sink_payload_last_be; core_tx_last_be_last_handler_source_payload_error <= core_tx_last_be_last_handler_sink_payload_error; core_tx_last_be_last_handler_source_last <= (core_tx_last_be_last_handler_sink_payload_last_be != 1'd0); if ((core_tx_last_be_last_handler_sink_valid & core_tx_last_be_last_handler_sink_ready)) begin if ((core_tx_last_be_last_handler_source_last & (~core_tx_last_be_last_handler_sink_last))) begin txdatapath_liteethmactxlastbe_next_state <= 1'd1; end end end endcase end assign core_tx_padding_counter_done = (core_tx_padding_counter >= 6'd59); always @(*) begin core_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; core_tx_padding_sink_ready <= 1'd0; core_tx_padding_source_first <= 1'd0; core_tx_padding_source_last <= 1'd0; core_tx_padding_source_payload_data <= 8'd0; core_tx_padding_source_payload_error <= 1'd0; core_tx_padding_source_payload_last_be <= 1'd0; core_tx_padding_source_valid <= 1'd0; txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; txdatapath_liteethmacpaddinginserter_next_state <= txdatapath_liteethmacpaddinginserter_state; case (txdatapath_liteethmacpaddinginserter_state) 1'd1: begin core_tx_padding_source_valid <= 1'd1; if (core_tx_padding_counter_done) begin core_tx_padding_source_payload_last_be <= 1'd1; core_tx_padding_source_last <= 1'd1; end core_tx_padding_source_payload_data <= 1'd0; if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; if (core_tx_padding_counter_done) begin core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; end end end default: begin core_tx_padding_source_valid <= core_tx_padding_sink_valid; core_tx_padding_sink_ready <= core_tx_padding_source_ready; core_tx_padding_source_first <= core_tx_padding_sink_first; core_tx_padding_source_last <= core_tx_padding_sink_last; core_tx_padding_source_payload_data <= core_tx_padding_sink_payload_data; core_tx_padding_source_payload_last_be <= core_tx_padding_sink_payload_last_be; core_tx_padding_source_payload_error <= core_tx_padding_sink_payload_error; if ((core_tx_padding_source_valid & core_tx_padding_source_ready)) begin core_tx_padding_counter_clockdomainsrenamer0_next_value <= (core_tx_padding_counter + 1'd1); core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; if (core_tx_padding_sink_last) begin if ((~core_tx_padding_counter_done)) begin core_tx_padding_source_last <= 1'd0; core_tx_padding_source_payload_last_be <= 1'd0; txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; end else begin if (((core_tx_padding_counter == 6'd59) & (core_tx_padding_sink_payload_last_be < 1'd1))) begin core_tx_padding_source_payload_last_be <= 1'd1; end else begin core_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; core_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; end end end end end endcase end assign core_tx_crc_data0 = core_tx_crc_sink_payload_data; assign core_tx_crc_be = core_tx_crc_sink_payload_last_be; assign core_tx_crc_cnt_done = (core_tx_crc_cnt == 1'd0); assign core_tx_crc_sink_valid = core_tx_crc_source_source_valid; assign core_tx_crc_source_source_ready = core_tx_crc_sink_ready; assign core_tx_crc_sink_first = core_tx_crc_source_source_first; assign core_tx_crc_sink_last = core_tx_crc_source_source_last; assign core_tx_crc_sink_payload_data = core_tx_crc_source_source_payload_data; assign core_tx_crc_sink_payload_last_be = core_tx_crc_source_source_payload_last_be; assign core_tx_crc_sink_payload_error = core_tx_crc_source_source_payload_error; assign core_tx_crc_data1 = core_tx_crc_data0; assign core_tx_crc_crc_prev = core_tx_crc_reg; always @(*) begin core_tx_crc_error <= 1'd0; core_tx_crc_value <= 32'd0; if (core_tx_crc_be) begin core_tx_crc_value <= ({core_tx_crc_crc_next[0], core_tx_crc_crc_next[1], core_tx_crc_crc_next[2], core_tx_crc_crc_next[3], core_tx_crc_crc_next[4], core_tx_crc_crc_next[5], core_tx_crc_crc_next[6], core_tx_crc_crc_next[7], core_tx_crc_crc_next[8], core_tx_crc_crc_next[9], core_tx_crc_crc_next[10], core_tx_crc_crc_next[11], core_tx_crc_crc_next[12], core_tx_crc_crc_next[13], core_tx_crc_crc_next[14], core_tx_crc_crc_next[15], core_tx_crc_crc_next[16], core_tx_crc_crc_next[17], core_tx_crc_crc_next[18], core_tx_crc_crc_next[19], core_tx_crc_crc_next[20], core_tx_crc_crc_next[21], core_tx_crc_crc_next[22], core_tx_crc_crc_next[23], core_tx_crc_crc_next[24], core_tx_crc_crc_next[25], core_tx_crc_crc_next[26], core_tx_crc_crc_next[27], core_tx_crc_crc_next[28], core_tx_crc_crc_next[29], core_tx_crc_crc_next[30], core_tx_crc_crc_next[31]} ^ 32'd4294967295); core_tx_crc_error <= (core_tx_crc_crc_next != 32'd3338984827); end end always @(*) begin core_tx_crc_crc_next <= 32'd0; core_tx_crc_crc_next[0] <= (((core_tx_crc_crc_prev[24] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[1] <= (((((((core_tx_crc_crc_prev[25] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[2] <= (((((((((core_tx_crc_crc_prev[26] ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[3] <= (((((((core_tx_crc_crc_prev[27] ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[4] <= (((((((((core_tx_crc_crc_prev[28] ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[5] <= (((((((((((((core_tx_crc_crc_prev[29] ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[6] <= (((((((((((core_tx_crc_crc_prev[30] ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[7] <= (((((((((core_tx_crc_crc_prev[31] ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[8] <= ((((((((core_tx_crc_crc_prev[0] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[9] <= ((((((((core_tx_crc_crc_prev[1] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[10] <= ((((((((core_tx_crc_crc_prev[2] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[11] <= ((((((((core_tx_crc_crc_prev[3] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[12] <= ((((((((((((core_tx_crc_crc_prev[4] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[13] <= ((((((((((((core_tx_crc_crc_prev[5] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[14] <= ((((((((((core_tx_crc_crc_prev[6] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); core_tx_crc_crc_next[15] <= ((((((((core_tx_crc_crc_prev[7] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); core_tx_crc_crc_next[16] <= ((((((core_tx_crc_crc_prev[8] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[17] <= ((((((core_tx_crc_crc_prev[9] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[18] <= ((((((core_tx_crc_crc_prev[10] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); core_tx_crc_crc_next[19] <= ((((core_tx_crc_crc_prev[11] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); core_tx_crc_crc_next[20] <= ((core_tx_crc_crc_prev[12] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); core_tx_crc_crc_next[21] <= ((core_tx_crc_crc_prev[13] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); core_tx_crc_crc_next[22] <= ((core_tx_crc_crc_prev[14] ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[23] <= ((((((core_tx_crc_crc_prev[15] ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_data1[6]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[24] <= ((((((core_tx_crc_crc_prev[16] ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[25] <= ((((core_tx_crc_crc_prev[17] ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); core_tx_crc_crc_next[26] <= ((((((((core_tx_crc_crc_prev[18] ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]) ^ core_tx_crc_crc_prev[24]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_data1[7]); core_tx_crc_crc_next[27] <= ((((((((core_tx_crc_crc_prev[19] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]) ^ core_tx_crc_crc_prev[25]) ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_data1[6]); core_tx_crc_crc_next[28] <= ((((((core_tx_crc_crc_prev[20] ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]) ^ core_tx_crc_crc_prev[26]) ^ core_tx_crc_data1[5]); core_tx_crc_crc_next[29] <= ((((((core_tx_crc_crc_prev[21] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[30]) ^ core_tx_crc_data1[1]) ^ core_tx_crc_crc_prev[27]) ^ core_tx_crc_data1[4]); core_tx_crc_crc_next[30] <= ((((core_tx_crc_crc_prev[22] ^ core_tx_crc_crc_prev[31]) ^ core_tx_crc_data1[0]) ^ core_tx_crc_crc_prev[28]) ^ core_tx_crc_data1[3]); core_tx_crc_crc_next[31] <= ((core_tx_crc_crc_prev[23] ^ core_tx_crc_crc_prev[29]) ^ core_tx_crc_data1[2]); end always @(*) begin core_tx_crc_ce <= 1'd0; core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; core_tx_crc_is_ongoing0 <= 1'd0; core_tx_crc_is_ongoing1 <= 1'd0; core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; core_tx_crc_reset <= 1'd0; core_tx_crc_sink_ready <= 1'd0; core_tx_crc_source_first <= 1'd0; core_tx_crc_source_last <= 1'd0; core_tx_crc_source_payload_data <= 8'd0; core_tx_crc_source_payload_error <= 1'd0; core_tx_crc_source_payload_last_be <= 1'd0; core_tx_crc_source_valid <= 1'd0; txdatapath_bufferizeendpoints_next_state <= 2'd0; txdatapath_bufferizeendpoints_next_state <= txdatapath_bufferizeendpoints_state; case (txdatapath_bufferizeendpoints_state) 1'd1: begin core_tx_crc_ce <= (core_tx_crc_sink_valid & core_tx_crc_source_ready); core_tx_crc_source_valid <= core_tx_crc_sink_valid; core_tx_crc_sink_ready <= core_tx_crc_source_ready; core_tx_crc_source_first <= core_tx_crc_sink_first; core_tx_crc_source_last <= core_tx_crc_sink_last; core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; core_tx_crc_source_payload_last_be <= core_tx_crc_sink_payload_last_be; core_tx_crc_source_payload_error <= core_tx_crc_sink_payload_error; core_tx_crc_source_last <= 1'd0; core_tx_crc_source_payload_last_be <= 1'd0; if (core_tx_crc_sink_last) begin if (core_tx_crc_sink_payload_last_be) begin core_tx_crc_source_payload_data <= core_tx_crc_sink_payload_data; end if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin core_tx_crc_source_last <= 1'd1; core_tx_crc_source_payload_last_be <= (core_tx_crc_sink_payload_last_be <<< -3'd3); end end if (((core_tx_crc_sink_valid & core_tx_crc_sink_last) & core_tx_crc_source_ready)) begin if ((1'd0 & (core_tx_crc_sink_payload_last_be <= 4'd15))) begin txdatapath_bufferizeendpoints_next_state <= 1'd0; end else begin core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= core_tx_crc_value; core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; if (1'd0) begin core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (core_tx_crc_sink_payload_last_be >>> 3'd4); core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end else begin core_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= core_tx_crc_sink_payload_last_be; core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; end txdatapath_bufferizeendpoints_next_state <= 2'd2; end end end 2'd2: begin core_tx_crc_source_valid <= 1'd1; case (core_tx_crc_cnt) 1'd0: begin core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[31:24]; end 1'd1: begin core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[23:16]; end 2'd2: begin core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[15:8]; end default: begin core_tx_crc_source_payload_data <= core_tx_crc_crc_packet[7:0]; end endcase if (core_tx_crc_cnt_done) begin core_tx_crc_source_last <= 1'd1; if (core_tx_crc_source_ready) begin txdatapath_bufferizeendpoints_next_state <= 1'd0; end end core_tx_crc_is_ongoing1 <= 1'd1; end default: begin core_tx_crc_reset <= 1'd1; core_tx_crc_sink_ready <= 1'd1; if (core_tx_crc_sink_valid) begin core_tx_crc_sink_ready <= 1'd0; txdatapath_bufferizeendpoints_next_state <= 1'd1; end core_tx_crc_is_ongoing0 <= 1'd1; end endcase end assign core_tx_crc_pipe_valid_sink_ready = ((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready); assign core_tx_crc_pipe_valid_sink_valid = core_tx_crc_sink_sink_valid; assign core_tx_crc_sink_sink_ready = core_tx_crc_pipe_valid_sink_ready; assign core_tx_crc_pipe_valid_sink_first = core_tx_crc_sink_sink_first; assign core_tx_crc_pipe_valid_sink_last = core_tx_crc_sink_sink_last; assign core_tx_crc_pipe_valid_sink_payload_data = core_tx_crc_sink_sink_payload_data; assign core_tx_crc_pipe_valid_sink_payload_last_be = core_tx_crc_sink_sink_payload_last_be; assign core_tx_crc_pipe_valid_sink_payload_error = core_tx_crc_sink_sink_payload_error; assign core_tx_crc_source_source_valid = core_tx_crc_pipe_valid_source_valid; assign core_tx_crc_pipe_valid_source_ready = core_tx_crc_source_source_ready; assign core_tx_crc_source_source_first = core_tx_crc_pipe_valid_source_first; assign core_tx_crc_source_source_last = core_tx_crc_pipe_valid_source_last; assign core_tx_crc_source_source_payload_data = core_tx_crc_pipe_valid_source_payload_data; assign core_tx_crc_source_source_payload_last_be = core_tx_crc_pipe_valid_source_payload_last_be; assign core_tx_crc_source_source_payload_error = core_tx_crc_pipe_valid_source_payload_error; assign core_tx_preamble_source_payload_last_be = core_tx_preamble_sink_payload_last_be; always @(*) begin core_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; core_tx_preamble_sink_ready <= 1'd0; core_tx_preamble_source_first <= 1'd0; core_tx_preamble_source_last <= 1'd0; core_tx_preamble_source_payload_data <= 8'd0; core_tx_preamble_source_payload_error <= 1'd0; core_tx_preamble_source_valid <= 1'd0; txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; core_tx_preamble_source_payload_data <= core_tx_preamble_sink_payload_data; txdatapath_liteethmacpreambleinserter_next_state <= txdatapath_liteethmacpreambleinserter_state; case (txdatapath_liteethmacpreambleinserter_state) 1'd1: begin core_tx_preamble_source_valid <= 1'd1; case (core_tx_preamble_count) 1'd0: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[7:0]; end 1'd1: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[15:8]; end 2'd2: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[23:16]; end 2'd3: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[31:24]; end 3'd4: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[39:32]; end 3'd5: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[47:40]; end 3'd6: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[55:48]; end default: begin core_tx_preamble_source_payload_data <= core_tx_preamble_preamble[63:56]; end endcase if (core_tx_preamble_source_ready) begin if ((core_tx_preamble_count == 3'd7)) begin txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; end else begin core_tx_preamble_count_clockdomainsrenamer2_next_value <= (core_tx_preamble_count + 1'd1); core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; end end end 2'd2: begin core_tx_preamble_source_valid <= core_tx_preamble_sink_valid; core_tx_preamble_sink_ready <= core_tx_preamble_source_ready; core_tx_preamble_source_first <= core_tx_preamble_sink_first; core_tx_preamble_source_last <= core_tx_preamble_sink_last; core_tx_preamble_source_payload_error <= core_tx_preamble_sink_payload_error; if (((core_tx_preamble_sink_valid & core_tx_preamble_sink_last) & core_tx_preamble_source_ready)) begin txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; end end default: begin core_tx_preamble_sink_ready <= 1'd1; core_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; core_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; if (core_tx_preamble_sink_valid) begin core_tx_preamble_sink_ready <= 1'd0; txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; end end endcase end always @(*) begin core_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; core_tx_gap_sink_ready <= 1'd0; core_tx_gap_source_first <= 1'd0; core_tx_gap_source_last <= 1'd0; core_tx_gap_source_payload_data <= 8'd0; core_tx_gap_source_payload_error <= 1'd0; core_tx_gap_source_payload_last_be <= 1'd0; core_tx_gap_source_valid <= 1'd0; txdatapath_liteethmacgap_next_state <= 1'd0; txdatapath_liteethmacgap_next_state <= txdatapath_liteethmacgap_state; case (txdatapath_liteethmacgap_state) 1'd1: begin core_tx_gap_counter_clockdomainsrenamer3_next_value <= (core_tx_gap_counter + 1'd1); core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; if ((core_tx_gap_counter == 4'd11)) begin txdatapath_liteethmacgap_next_state <= 1'd0; end end default: begin core_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; core_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; core_tx_gap_source_valid <= core_tx_gap_sink_valid; core_tx_gap_sink_ready <= core_tx_gap_source_ready; core_tx_gap_source_first <= core_tx_gap_sink_first; core_tx_gap_source_last <= core_tx_gap_sink_last; core_tx_gap_source_payload_data <= core_tx_gap_sink_payload_data; core_tx_gap_source_payload_last_be <= core_tx_gap_sink_payload_last_be; core_tx_gap_source_payload_error <= core_tx_gap_sink_payload_error; if (((core_tx_gap_sink_valid & core_tx_gap_sink_last) & core_tx_gap_sink_ready)) begin txdatapath_liteethmacgap_next_state <= 1'd1; end end endcase end assign core_tx_cdc_sink_sink_valid = core_sink_valid; assign core_sink_ready = core_tx_cdc_sink_sink_ready; assign core_tx_cdc_sink_sink_first = core_sink_first; assign core_tx_cdc_sink_sink_last = core_sink_last; assign core_tx_cdc_sink_sink_payload_data = core_sink_payload_data; assign core_tx_cdc_sink_sink_payload_last_be = core_sink_payload_last_be; assign core_tx_cdc_sink_sink_payload_error = core_sink_payload_error; assign core_tx_converter_sink_valid = core_tx_cdc_source_source_valid; assign core_tx_cdc_source_source_ready = core_tx_converter_sink_ready; assign core_tx_converter_sink_first = core_tx_cdc_source_source_first; assign core_tx_converter_sink_last = core_tx_cdc_source_source_last; assign core_tx_converter_sink_payload_data = core_tx_cdc_source_source_payload_data; assign core_tx_converter_sink_payload_last_be = core_tx_cdc_source_source_payload_last_be; assign core_tx_converter_sink_payload_error = core_tx_cdc_source_source_payload_error; assign core_tx_last_be_sink_sink_valid = core_tx_converter_source_valid; assign core_tx_converter_source_ready = core_tx_last_be_sink_sink_ready; assign core_tx_last_be_sink_sink_first = core_tx_converter_source_first; assign core_tx_last_be_sink_sink_last = core_tx_converter_source_last; assign core_tx_last_be_sink_sink_payload_data = core_tx_converter_source_payload_data; assign core_tx_last_be_sink_sink_payload_last_be = core_tx_converter_source_payload_last_be; assign core_tx_last_be_sink_sink_payload_error = core_tx_converter_source_payload_error; assign core_tx_padding_sink_valid = core_tx_last_be_source_source_valid; assign core_tx_last_be_source_source_ready = core_tx_padding_sink_ready; assign core_tx_padding_sink_first = core_tx_last_be_source_source_first; assign core_tx_padding_sink_last = core_tx_last_be_source_source_last; assign core_tx_padding_sink_payload_data = core_tx_last_be_source_source_payload_data; assign core_tx_padding_sink_payload_last_be = core_tx_last_be_source_source_payload_last_be; assign core_tx_padding_sink_payload_error = core_tx_last_be_source_source_payload_error; assign core_tx_crc_sink_sink_valid = core_tx_padding_source_valid; assign core_tx_padding_source_ready = core_tx_crc_sink_sink_ready; assign core_tx_crc_sink_sink_first = core_tx_padding_source_first; assign core_tx_crc_sink_sink_last = core_tx_padding_source_last; assign core_tx_crc_sink_sink_payload_data = core_tx_padding_source_payload_data; assign core_tx_crc_sink_sink_payload_last_be = core_tx_padding_source_payload_last_be; assign core_tx_crc_sink_sink_payload_error = core_tx_padding_source_payload_error; assign core_tx_preamble_sink_valid = core_tx_crc_source_valid; assign core_tx_crc_source_ready = core_tx_preamble_sink_ready; assign core_tx_preamble_sink_first = core_tx_crc_source_first; assign core_tx_preamble_sink_last = core_tx_crc_source_last; assign core_tx_preamble_sink_payload_data = core_tx_crc_source_payload_data; assign core_tx_preamble_sink_payload_last_be = core_tx_crc_source_payload_last_be; assign core_tx_preamble_sink_payload_error = core_tx_crc_source_payload_error; assign core_tx_gap_sink_valid = core_tx_preamble_source_valid; assign core_tx_preamble_source_ready = core_tx_gap_sink_ready; assign core_tx_gap_sink_first = core_tx_preamble_source_first; assign core_tx_gap_sink_last = core_tx_preamble_source_last; assign core_tx_gap_sink_payload_data = core_tx_preamble_source_payload_data; assign core_tx_gap_sink_payload_last_be = core_tx_preamble_source_payload_last_be; assign core_tx_gap_sink_payload_error = core_tx_preamble_source_payload_error; assign maccore_ethphy_sink_sink_valid = core_tx_gap_source_valid; assign core_tx_gap_source_ready = maccore_ethphy_sink_sink_ready; assign maccore_ethphy_sink_sink_first = core_tx_gap_source_first; assign maccore_ethphy_sink_sink_last = core_tx_gap_source_last; assign maccore_ethphy_sink_sink_payload_data = core_tx_gap_source_payload_data; assign maccore_ethphy_sink_sink_payload_last_be = core_tx_gap_source_payload_last_be; assign maccore_ethphy_sink_sink_payload_error = core_tx_gap_source_payload_error; assign core_pulsesynchronizer0_i = core_rx_preamble_error; assign core_pulsesynchronizer1_i = core_liteethmaccrc32checker_error; assign core_rx_preamble_source_payload_data = core_rx_preamble_sink_payload_data; assign core_rx_preamble_source_payload_last_be = core_rx_preamble_sink_payload_last_be; always @(*) begin core_rx_preamble_error <= 1'd0; core_rx_preamble_sink_ready <= 1'd0; core_rx_preamble_source_first <= 1'd0; core_rx_preamble_source_last <= 1'd0; core_rx_preamble_source_payload_error <= 1'd0; core_rx_preamble_source_valid <= 1'd0; rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; rxdatapath_liteethmacpreamblechecker_next_state <= rxdatapath_liteethmacpreamblechecker_state; case (rxdatapath_liteethmacpreamblechecker_state) 1'd1: begin core_rx_preamble_source_valid <= core_rx_preamble_sink_valid; core_rx_preamble_sink_ready <= core_rx_preamble_source_ready; core_rx_preamble_source_first <= core_rx_preamble_sink_first; core_rx_preamble_source_last <= core_rx_preamble_sink_last; core_rx_preamble_source_payload_error <= core_rx_preamble_sink_payload_error; if (((core_rx_preamble_source_valid & core_rx_preamble_source_last) & core_rx_preamble_source_ready)) begin rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; end end default: begin core_rx_preamble_sink_ready <= 1'd1; if (((core_rx_preamble_sink_valid & (~core_rx_preamble_sink_last)) & (core_rx_preamble_sink_payload_data == core_rx_preamble_preamble[63:56]))) begin rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; end if ((core_rx_preamble_sink_valid & core_rx_preamble_sink_last)) begin core_rx_preamble_error <= 1'd1; end end endcase end assign core_pulsesynchronizer0_o = (core_pulsesynchronizer0_toggle_o ^ core_pulsesynchronizer0_toggle_o_r); assign core_liteethmaccrc32checker_fifo_full = (core_liteethmaccrc32checker_syncfifo_level == 3'd4); assign core_liteethmaccrc32checker_fifo_in = (core_liteethmaccrc32checker_sink_sink_valid & ((~core_liteethmaccrc32checker_fifo_full) | core_liteethmaccrc32checker_fifo_out)); assign core_liteethmaccrc32checker_fifo_out = (core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready); assign core_liteethmaccrc32checker_syncfifo_sink_first = core_liteethmaccrc32checker_sink_sink_first; assign core_liteethmaccrc32checker_syncfifo_sink_last = core_liteethmaccrc32checker_sink_sink_last; assign core_liteethmaccrc32checker_syncfifo_sink_payload_data = core_liteethmaccrc32checker_sink_sink_payload_data; assign core_liteethmaccrc32checker_syncfifo_sink_payload_last_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; assign core_liteethmaccrc32checker_syncfifo_sink_payload_error = core_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin core_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_sink_sink_valid; core_liteethmaccrc32checker_syncfifo_sink_valid <= core_liteethmaccrc32checker_fifo_in; end always @(*) begin core_liteethmaccrc32checker_sink_sink_ready <= 1'd0; core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_syncfifo_sink_ready; core_liteethmaccrc32checker_sink_sink_ready <= core_liteethmaccrc32checker_fifo_in; end assign core_liteethmaccrc32checker_crc_data0 = core_liteethmaccrc32checker_sink_sink_payload_data; assign core_liteethmaccrc32checker_crc_be = core_liteethmaccrc32checker_sink_sink_payload_last_be; assign core_liteethmaccrc32checker_source_source_first = core_liteethmaccrc32checker_syncfifo_source_first; assign core_liteethmaccrc32checker_source_source_payload_data = core_liteethmaccrc32checker_syncfifo_source_payload_data; assign core_liteethmaccrc32checker_sink_sink_valid = core_bufferizeendpoints_source_source_valid; assign core_bufferizeendpoints_source_source_ready = core_liteethmaccrc32checker_sink_sink_ready; assign core_liteethmaccrc32checker_sink_sink_first = core_bufferizeendpoints_source_source_first; assign core_liteethmaccrc32checker_sink_sink_last = core_bufferizeendpoints_source_source_last; assign core_liteethmaccrc32checker_sink_sink_payload_data = core_bufferizeendpoints_source_source_payload_data; assign core_liteethmaccrc32checker_sink_sink_payload_last_be = core_bufferizeendpoints_source_source_payload_last_be; assign core_liteethmaccrc32checker_sink_sink_payload_error = core_bufferizeendpoints_source_source_payload_error; assign core_liteethmaccrc32checker_crc_data1 = core_liteethmaccrc32checker_crc_data0; assign core_liteethmaccrc32checker_crc_crc_prev = core_liteethmaccrc32checker_crc_reg; always @(*) begin core_liteethmaccrc32checker_crc_error0 <= 1'd0; core_liteethmaccrc32checker_crc_value <= 32'd0; if (core_liteethmaccrc32checker_crc_be) begin core_liteethmaccrc32checker_crc_value <= ({core_liteethmaccrc32checker_crc_crc_next[0], core_liteethmaccrc32checker_crc_crc_next[1], core_liteethmaccrc32checker_crc_crc_next[2], core_liteethmaccrc32checker_crc_crc_next[3], core_liteethmaccrc32checker_crc_crc_next[4], core_liteethmaccrc32checker_crc_crc_next[5], core_liteethmaccrc32checker_crc_crc_next[6], core_liteethmaccrc32checker_crc_crc_next[7], core_liteethmaccrc32checker_crc_crc_next[8], core_liteethmaccrc32checker_crc_crc_next[9], core_liteethmaccrc32checker_crc_crc_next[10], core_liteethmaccrc32checker_crc_crc_next[11], core_liteethmaccrc32checker_crc_crc_next[12], core_liteethmaccrc32checker_crc_crc_next[13], core_liteethmaccrc32checker_crc_crc_next[14], core_liteethmaccrc32checker_crc_crc_next[15], core_liteethmaccrc32checker_crc_crc_next[16], core_liteethmaccrc32checker_crc_crc_next[17], core_liteethmaccrc32checker_crc_crc_next[18], core_liteethmaccrc32checker_crc_crc_next[19], core_liteethmaccrc32checker_crc_crc_next[20], core_liteethmaccrc32checker_crc_crc_next[21], core_liteethmaccrc32checker_crc_crc_next[22], core_liteethmaccrc32checker_crc_crc_next[23], core_liteethmaccrc32checker_crc_crc_next[24], core_liteethmaccrc32checker_crc_crc_next[25], core_liteethmaccrc32checker_crc_crc_next[26], core_liteethmaccrc32checker_crc_crc_next[27], core_liteethmaccrc32checker_crc_crc_next[28], core_liteethmaccrc32checker_crc_crc_next[29], core_liteethmaccrc32checker_crc_crc_next[30], core_liteethmaccrc32checker_crc_crc_next[31]} ^ 32'd4294967295); core_liteethmaccrc32checker_crc_error0 <= (core_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); end end always @(*) begin core_liteethmaccrc32checker_crc_crc_next <= 32'd0; core_liteethmaccrc32checker_crc_crc_next[0] <= (((core_liteethmaccrc32checker_crc_crc_prev[24] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[1] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[25] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[26] ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[3] <= (((((((core_liteethmaccrc32checker_crc_crc_prev[27] ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[28] ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((core_liteethmaccrc32checker_crc_crc_prev[29] ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((core_liteethmaccrc32checker_crc_crc_prev[30] ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((core_liteethmaccrc32checker_crc_crc_prev[31] ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[0] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[1] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[2] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[3] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[4] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((core_liteethmaccrc32checker_crc_crc_prev[5] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((core_liteethmaccrc32checker_crc_crc_prev[6] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); core_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[7] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); core_liteethmaccrc32checker_crc_crc_next[16] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[8] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[17] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[9] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[18] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[10] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); core_liteethmaccrc32checker_crc_crc_next[19] <= ((((core_liteethmaccrc32checker_crc_crc_prev[11] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); core_liteethmaccrc32checker_crc_crc_next[20] <= ((core_liteethmaccrc32checker_crc_crc_prev[12] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); core_liteethmaccrc32checker_crc_crc_next[21] <= ((core_liteethmaccrc32checker_crc_crc_prev[13] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); core_liteethmaccrc32checker_crc_crc_next[22] <= ((core_liteethmaccrc32checker_crc_crc_prev[14] ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[23] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[15] ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_data1[6]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[24] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[16] ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[25] <= ((((core_liteethmaccrc32checker_crc_crc_prev[17] ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); core_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[18] ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]) ^ core_liteethmaccrc32checker_crc_crc_prev[24]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_data1[7]); core_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((core_liteethmaccrc32checker_crc_crc_prev[19] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]) ^ core_liteethmaccrc32checker_crc_crc_prev[25]) ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_data1[6]); core_liteethmaccrc32checker_crc_crc_next[28] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[20] ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]) ^ core_liteethmaccrc32checker_crc_crc_prev[26]) ^ core_liteethmaccrc32checker_crc_data1[5]); core_liteethmaccrc32checker_crc_crc_next[29] <= ((((((core_liteethmaccrc32checker_crc_crc_prev[21] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[30]) ^ core_liteethmaccrc32checker_crc_data1[1]) ^ core_liteethmaccrc32checker_crc_crc_prev[27]) ^ core_liteethmaccrc32checker_crc_data1[4]); core_liteethmaccrc32checker_crc_crc_next[30] <= ((((core_liteethmaccrc32checker_crc_crc_prev[22] ^ core_liteethmaccrc32checker_crc_crc_prev[31]) ^ core_liteethmaccrc32checker_crc_data1[0]) ^ core_liteethmaccrc32checker_crc_crc_prev[28]) ^ core_liteethmaccrc32checker_crc_data1[3]); core_liteethmaccrc32checker_crc_crc_next[31] <= ((core_liteethmaccrc32checker_crc_crc_prev[23] ^ core_liteethmaccrc32checker_crc_crc_prev[29]) ^ core_liteethmaccrc32checker_crc_data1[2]); end assign core_liteethmaccrc32checker_syncfifo_syncfifo_din = {core_liteethmaccrc32checker_syncfifo_fifo_in_last, core_liteethmaccrc32checker_syncfifo_fifo_in_first, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; assign {core_liteethmaccrc32checker_syncfifo_fifo_out_last, core_liteethmaccrc32checker_syncfifo_fifo_out_first, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = core_liteethmaccrc32checker_syncfifo_syncfifo_dout; assign core_liteethmaccrc32checker_syncfifo_sink_ready = core_liteethmaccrc32checker_syncfifo_syncfifo_writable; assign core_liteethmaccrc32checker_syncfifo_syncfifo_we = core_liteethmaccrc32checker_syncfifo_sink_valid; assign core_liteethmaccrc32checker_syncfifo_fifo_in_first = core_liteethmaccrc32checker_syncfifo_sink_first; assign core_liteethmaccrc32checker_syncfifo_fifo_in_last = core_liteethmaccrc32checker_syncfifo_sink_last; assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = core_liteethmaccrc32checker_syncfifo_sink_payload_data; assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = core_liteethmaccrc32checker_syncfifo_sink_payload_last_be; assign core_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = core_liteethmaccrc32checker_syncfifo_sink_payload_error; assign core_liteethmaccrc32checker_syncfifo_source_valid = core_liteethmaccrc32checker_syncfifo_syncfifo_readable; assign core_liteethmaccrc32checker_syncfifo_source_first = core_liteethmaccrc32checker_syncfifo_fifo_out_first; assign core_liteethmaccrc32checker_syncfifo_source_last = core_liteethmaccrc32checker_syncfifo_fifo_out_last; assign core_liteethmaccrc32checker_syncfifo_source_payload_data = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; assign core_liteethmaccrc32checker_syncfifo_source_payload_last_be = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; assign core_liteethmaccrc32checker_syncfifo_source_payload_error = core_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; assign core_liteethmaccrc32checker_syncfifo_syncfifo_re = core_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin core_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; if (core_liteethmaccrc32checker_syncfifo_replace) begin core_liteethmaccrc32checker_syncfifo_wrport_adr <= (core_liteethmaccrc32checker_syncfifo_produce - 1'd1); end else begin core_liteethmaccrc32checker_syncfifo_wrport_adr <= core_liteethmaccrc32checker_syncfifo_produce; end end assign core_liteethmaccrc32checker_syncfifo_wrport_dat_w = core_liteethmaccrc32checker_syncfifo_syncfifo_din; assign core_liteethmaccrc32checker_syncfifo_wrport_we = (core_liteethmaccrc32checker_syncfifo_syncfifo_we & (core_liteethmaccrc32checker_syncfifo_syncfifo_writable | core_liteethmaccrc32checker_syncfifo_replace)); assign core_liteethmaccrc32checker_syncfifo_do_read = (core_liteethmaccrc32checker_syncfifo_syncfifo_readable & core_liteethmaccrc32checker_syncfifo_syncfifo_re); assign core_liteethmaccrc32checker_syncfifo_rdport_adr = core_liteethmaccrc32checker_syncfifo_consume; assign core_liteethmaccrc32checker_syncfifo_syncfifo_dout = core_liteethmaccrc32checker_syncfifo_rdport_dat_r; assign core_liteethmaccrc32checker_syncfifo_syncfifo_writable = (core_liteethmaccrc32checker_syncfifo_level != 3'd5); assign core_liteethmaccrc32checker_syncfifo_syncfifo_readable = (core_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin core_liteethmaccrc32checker_crc_ce <= 1'd0; core_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; core_liteethmaccrc32checker_crc_reset <= 1'd0; core_liteethmaccrc32checker_error <= 1'd0; core_liteethmaccrc32checker_fifo_reset <= 1'd0; core_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; core_liteethmaccrc32checker_source_source_last <= 1'd0; core_liteethmaccrc32checker_source_source_payload_error <= 1'd0; core_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; core_liteethmaccrc32checker_source_source_valid <= 1'd0; core_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; rxdatapath_bufferizeendpoints_next_state <= 2'd0; core_liteethmaccrc32checker_source_source_payload_error <= core_liteethmaccrc32checker_syncfifo_source_payload_error; rxdatapath_bufferizeendpoints_next_state <= rxdatapath_bufferizeendpoints_state; case (rxdatapath_bufferizeendpoints_state) 1'd1: begin if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin core_liteethmaccrc32checker_crc_ce <= 1'd1; rxdatapath_bufferizeendpoints_next_state <= 2'd2; end end 2'd2: begin core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_fifo_out; core_liteethmaccrc32checker_source_source_valid <= (core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_fifo_full); if (1'd1) begin core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_sink_sink_payload_last_be; end else begin if ((core_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_sink_sink_last; core_liteethmaccrc32checker_source_source_payload_last_be <= (core_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); end else begin core_liteethmaccrc32checker_last_be_next_value0 <= (core_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); core_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; core_liteethmaccrc32checker_crc_error1_next_value1 <= core_liteethmaccrc32checker_crc_error0; core_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; end end core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_sink_sink_payload_error | {1{(core_liteethmaccrc32checker_crc_error0 & core_liteethmaccrc32checker_sink_sink_last)}}); core_liteethmaccrc32checker_error <= ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_last) & core_liteethmaccrc32checker_crc_error0); if ((core_liteethmaccrc32checker_sink_sink_valid & core_liteethmaccrc32checker_sink_sink_ready)) begin core_liteethmaccrc32checker_crc_ce <= 1'd1; if ((core_liteethmaccrc32checker_sink_sink_last & (core_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin rxdatapath_bufferizeendpoints_next_state <= 2'd3; end else begin if (core_liteethmaccrc32checker_sink_sink_last) begin rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end end end 2'd3: begin core_liteethmaccrc32checker_source_source_valid <= core_liteethmaccrc32checker_syncfifo_source_valid; core_liteethmaccrc32checker_syncfifo_source_ready <= core_liteethmaccrc32checker_source_source_ready; core_liteethmaccrc32checker_source_source_last <= core_liteethmaccrc32checker_syncfifo_source_last; core_liteethmaccrc32checker_source_source_payload_error <= (core_liteethmaccrc32checker_syncfifo_source_payload_error | {1{core_liteethmaccrc32checker_crc_error1}}); core_liteethmaccrc32checker_source_source_payload_last_be <= core_liteethmaccrc32checker_last_be; if ((core_liteethmaccrc32checker_source_source_valid & core_liteethmaccrc32checker_source_source_ready)) begin rxdatapath_bufferizeendpoints_next_state <= 1'd0; end end default: begin core_liteethmaccrc32checker_crc_reset <= 1'd1; core_liteethmaccrc32checker_fifo_reset <= 1'd1; rxdatapath_bufferizeendpoints_next_state <= 1'd1; end endcase end assign core_bufferizeendpoints_pipe_valid_sink_ready = ((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready); assign core_bufferizeendpoints_pipe_valid_sink_valid = core_bufferizeendpoints_sink_sink_valid; assign core_bufferizeendpoints_sink_sink_ready = core_bufferizeendpoints_pipe_valid_sink_ready; assign core_bufferizeendpoints_pipe_valid_sink_first = core_bufferizeendpoints_sink_sink_first; assign core_bufferizeendpoints_pipe_valid_sink_last = core_bufferizeendpoints_sink_sink_last; assign core_bufferizeendpoints_pipe_valid_sink_payload_data = core_bufferizeendpoints_sink_sink_payload_data; assign core_bufferizeendpoints_pipe_valid_sink_payload_last_be = core_bufferizeendpoints_sink_sink_payload_last_be; assign core_bufferizeendpoints_pipe_valid_sink_payload_error = core_bufferizeendpoints_sink_sink_payload_error; assign core_bufferizeendpoints_source_source_valid = core_bufferizeendpoints_pipe_valid_source_valid; assign core_bufferizeendpoints_pipe_valid_source_ready = core_bufferizeendpoints_source_source_ready; assign core_bufferizeendpoints_source_source_first = core_bufferizeendpoints_pipe_valid_source_first; assign core_bufferizeendpoints_source_source_last = core_bufferizeendpoints_pipe_valid_source_last; assign core_bufferizeendpoints_source_source_payload_data = core_bufferizeendpoints_pipe_valid_source_payload_data; assign core_bufferizeendpoints_source_source_payload_last_be = core_bufferizeendpoints_pipe_valid_source_payload_last_be; assign core_bufferizeendpoints_source_source_payload_error = core_bufferizeendpoints_pipe_valid_source_payload_error; assign core_pulsesynchronizer1_o = (core_pulsesynchronizer1_toggle_o ^ core_pulsesynchronizer1_toggle_o_r); assign core_rx_padding_source_valid = core_rx_padding_sink_valid; assign core_rx_padding_sink_ready = core_rx_padding_source_ready; assign core_rx_padding_source_first = core_rx_padding_sink_first; assign core_rx_padding_source_last = core_rx_padding_sink_last; assign core_rx_padding_source_payload_data = core_rx_padding_sink_payload_data; assign core_rx_padding_source_payload_last_be = core_rx_padding_sink_payload_last_be; assign core_rx_padding_source_payload_error = core_rx_padding_sink_payload_error; assign core_rx_last_be_source_valid = core_rx_last_be_sink_valid; assign core_rx_last_be_sink_ready = core_rx_last_be_source_ready; assign core_rx_last_be_source_first = core_rx_last_be_sink_first; assign core_rx_last_be_source_last = core_rx_last_be_sink_last; assign core_rx_last_be_source_payload_data = core_rx_last_be_sink_payload_data; assign core_rx_last_be_source_payload_error = core_rx_last_be_sink_payload_error; always @(*) begin core_rx_last_be_source_payload_last_be <= 1'd0; core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_payload_last_be; if (1'd1) begin core_rx_last_be_source_payload_last_be <= core_rx_last_be_sink_last; end end assign core_rx_converter_converter_sink_valid = core_rx_converter_sink_valid; assign core_rx_converter_converter_sink_first = core_rx_converter_sink_first; assign core_rx_converter_converter_sink_last = core_rx_converter_sink_last; assign core_rx_converter_sink_ready = core_rx_converter_converter_sink_ready; assign core_rx_converter_converter_sink_payload_data = {core_rx_converter_sink_payload_error, core_rx_converter_sink_payload_last_be, core_rx_converter_sink_payload_data}; assign core_rx_converter_source_valid = core_rx_converter_source_source_valid; assign core_rx_converter_source_first = core_rx_converter_source_source_first; assign core_rx_converter_source_last = core_rx_converter_source_source_last; assign core_rx_converter_source_source_ready = core_rx_converter_source_ready; always @(*) begin core_rx_converter_source_payload_data <= 32'd0; core_rx_converter_source_payload_data[7:0] <= core_rx_converter_source_source_payload_data[7:0]; core_rx_converter_source_payload_data[15:8] <= core_rx_converter_source_source_payload_data[17:10]; core_rx_converter_source_payload_data[23:16] <= core_rx_converter_source_source_payload_data[27:20]; core_rx_converter_source_payload_data[31:24] <= core_rx_converter_source_source_payload_data[37:30]; end always @(*) begin core_rx_converter_source_payload_last_be <= 4'd0; core_rx_converter_source_payload_last_be[0] <= core_rx_converter_source_source_payload_data[8]; core_rx_converter_source_payload_last_be[1] <= core_rx_converter_source_source_payload_data[18]; core_rx_converter_source_payload_last_be[2] <= core_rx_converter_source_source_payload_data[28]; core_rx_converter_source_payload_last_be[3] <= core_rx_converter_source_source_payload_data[38]; end always @(*) begin core_rx_converter_source_payload_error <= 4'd0; core_rx_converter_source_payload_error[0] <= core_rx_converter_source_source_payload_data[9]; core_rx_converter_source_payload_error[1] <= core_rx_converter_source_source_payload_data[19]; core_rx_converter_source_payload_error[2] <= core_rx_converter_source_source_payload_data[29]; core_rx_converter_source_payload_error[3] <= core_rx_converter_source_source_payload_data[39]; end assign core_rx_converter_source_source_valid = core_rx_converter_converter_source_valid; assign core_rx_converter_converter_source_ready = core_rx_converter_source_source_ready; assign core_rx_converter_source_source_first = core_rx_converter_converter_source_first; assign core_rx_converter_source_source_last = core_rx_converter_converter_source_last; assign core_rx_converter_source_source_payload_data = core_rx_converter_converter_source_payload_data; assign core_rx_converter_converter_sink_ready = ((~core_rx_converter_converter_strobe_all) | core_rx_converter_converter_source_ready); assign core_rx_converter_converter_source_valid = core_rx_converter_converter_strobe_all; assign core_rx_converter_converter_load_part = (core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready); assign core_rx_cdc_cdc_sink_valid = core_rx_cdc_sink_sink_valid; assign core_rx_cdc_sink_sink_ready = core_rx_cdc_cdc_sink_ready; assign core_rx_cdc_cdc_sink_first = core_rx_cdc_sink_sink_first; assign core_rx_cdc_cdc_sink_last = core_rx_cdc_sink_sink_last; assign core_rx_cdc_cdc_sink_payload_data = core_rx_cdc_sink_sink_payload_data; assign core_rx_cdc_cdc_sink_payload_last_be = core_rx_cdc_sink_sink_payload_last_be; assign core_rx_cdc_cdc_sink_payload_error = core_rx_cdc_sink_sink_payload_error; assign core_rx_cdc_source_source_valid = core_rx_cdc_cdc_source_valid; assign core_rx_cdc_cdc_source_ready = core_rx_cdc_source_source_ready; assign core_rx_cdc_source_source_first = core_rx_cdc_cdc_source_first; assign core_rx_cdc_source_source_last = core_rx_cdc_cdc_source_last; assign core_rx_cdc_source_source_payload_data = core_rx_cdc_cdc_source_payload_data; assign core_rx_cdc_source_source_payload_last_be = core_rx_cdc_cdc_source_payload_last_be; assign core_rx_cdc_source_source_payload_error = core_rx_cdc_cdc_source_payload_error; assign core_rx_cdc_cdc_asyncfifo_din = {core_rx_cdc_cdc_fifo_in_last, core_rx_cdc_cdc_fifo_in_first, core_rx_cdc_cdc_fifo_in_payload_error, core_rx_cdc_cdc_fifo_in_payload_last_be, core_rx_cdc_cdc_fifo_in_payload_data}; assign {core_rx_cdc_cdc_fifo_out_last, core_rx_cdc_cdc_fifo_out_first, core_rx_cdc_cdc_fifo_out_payload_error, core_rx_cdc_cdc_fifo_out_payload_last_be, core_rx_cdc_cdc_fifo_out_payload_data} = core_rx_cdc_cdc_asyncfifo_dout; assign core_rx_cdc_cdc_sink_ready = core_rx_cdc_cdc_asyncfifo_writable; assign core_rx_cdc_cdc_asyncfifo_we = core_rx_cdc_cdc_sink_valid; assign core_rx_cdc_cdc_fifo_in_first = core_rx_cdc_cdc_sink_first; assign core_rx_cdc_cdc_fifo_in_last = core_rx_cdc_cdc_sink_last; assign core_rx_cdc_cdc_fifo_in_payload_data = core_rx_cdc_cdc_sink_payload_data; assign core_rx_cdc_cdc_fifo_in_payload_last_be = core_rx_cdc_cdc_sink_payload_last_be; assign core_rx_cdc_cdc_fifo_in_payload_error = core_rx_cdc_cdc_sink_payload_error; assign core_rx_cdc_cdc_source_valid = core_rx_cdc_cdc_asyncfifo_readable; assign core_rx_cdc_cdc_source_first = core_rx_cdc_cdc_fifo_out_first; assign core_rx_cdc_cdc_source_last = core_rx_cdc_cdc_fifo_out_last; assign core_rx_cdc_cdc_source_payload_data = core_rx_cdc_cdc_fifo_out_payload_data; assign core_rx_cdc_cdc_source_payload_last_be = core_rx_cdc_cdc_fifo_out_payload_last_be; assign core_rx_cdc_cdc_source_payload_error = core_rx_cdc_cdc_fifo_out_payload_error; assign core_rx_cdc_cdc_asyncfifo_re = core_rx_cdc_cdc_source_ready; assign core_rx_cdc_cdc_graycounter0_ce = (core_rx_cdc_cdc_asyncfifo_writable & core_rx_cdc_cdc_asyncfifo_we); assign core_rx_cdc_cdc_graycounter1_ce = (core_rx_cdc_cdc_asyncfifo_readable & core_rx_cdc_cdc_asyncfifo_re); assign core_rx_cdc_cdc_asyncfifo_writable = (((core_rx_cdc_cdc_graycounter0_q[5] == core_rx_cdc_cdc_consume_wdomain[5]) | (core_rx_cdc_cdc_graycounter0_q[4] == core_rx_cdc_cdc_consume_wdomain[4])) | (core_rx_cdc_cdc_graycounter0_q[3:0] != core_rx_cdc_cdc_consume_wdomain[3:0])); assign core_rx_cdc_cdc_asyncfifo_readable = (core_rx_cdc_cdc_graycounter1_q != core_rx_cdc_cdc_produce_rdomain); assign core_rx_cdc_cdc_wrport_adr = core_rx_cdc_cdc_graycounter0_q_binary[4:0]; assign core_rx_cdc_cdc_wrport_dat_w = core_rx_cdc_cdc_asyncfifo_din; assign core_rx_cdc_cdc_wrport_we = core_rx_cdc_cdc_graycounter0_ce; assign core_rx_cdc_cdc_rdport_adr = core_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign core_rx_cdc_cdc_asyncfifo_dout = core_rx_cdc_cdc_rdport_dat_r; always @(*) begin core_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; if (core_rx_cdc_cdc_graycounter0_ce) begin core_rx_cdc_cdc_graycounter0_q_next_binary <= (core_rx_cdc_cdc_graycounter0_q_binary + 1'd1); end else begin core_rx_cdc_cdc_graycounter0_q_next_binary <= core_rx_cdc_cdc_graycounter0_q_binary; end end assign core_rx_cdc_cdc_graycounter0_q_next = (core_rx_cdc_cdc_graycounter0_q_next_binary ^ core_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin core_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; if (core_rx_cdc_cdc_graycounter1_ce) begin core_rx_cdc_cdc_graycounter1_q_next_binary <= (core_rx_cdc_cdc_graycounter1_q_binary + 1'd1); end else begin core_rx_cdc_cdc_graycounter1_q_next_binary <= core_rx_cdc_cdc_graycounter1_q_binary; end end assign core_rx_cdc_cdc_graycounter1_q_next = (core_rx_cdc_cdc_graycounter1_q_next_binary ^ core_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign core_rx_preamble_sink_valid = maccore_ethphy_source_source_valid; assign maccore_ethphy_source_source_ready = core_rx_preamble_sink_ready; assign core_rx_preamble_sink_first = maccore_ethphy_source_source_first; assign core_rx_preamble_sink_last = maccore_ethphy_source_source_last; assign core_rx_preamble_sink_payload_data = maccore_ethphy_source_source_payload_data; assign core_rx_preamble_sink_payload_last_be = maccore_ethphy_source_source_payload_last_be; assign core_rx_preamble_sink_payload_error = maccore_ethphy_source_source_payload_error; assign core_bufferizeendpoints_sink_sink_valid = core_rx_preamble_source_valid; assign core_rx_preamble_source_ready = core_bufferizeendpoints_sink_sink_ready; assign core_bufferizeendpoints_sink_sink_first = core_rx_preamble_source_first; assign core_bufferizeendpoints_sink_sink_last = core_rx_preamble_source_last; assign core_bufferizeendpoints_sink_sink_payload_data = core_rx_preamble_source_payload_data; assign core_bufferizeendpoints_sink_sink_payload_last_be = core_rx_preamble_source_payload_last_be; assign core_bufferizeendpoints_sink_sink_payload_error = core_rx_preamble_source_payload_error; assign core_rx_padding_sink_valid = core_liteethmaccrc32checker_source_source_valid; assign core_liteethmaccrc32checker_source_source_ready = core_rx_padding_sink_ready; assign core_rx_padding_sink_first = core_liteethmaccrc32checker_source_source_first; assign core_rx_padding_sink_last = core_liteethmaccrc32checker_source_source_last; assign core_rx_padding_sink_payload_data = core_liteethmaccrc32checker_source_source_payload_data; assign core_rx_padding_sink_payload_last_be = core_liteethmaccrc32checker_source_source_payload_last_be; assign core_rx_padding_sink_payload_error = core_liteethmaccrc32checker_source_source_payload_error; assign core_rx_last_be_sink_valid = core_rx_padding_source_valid; assign core_rx_padding_source_ready = core_rx_last_be_sink_ready; assign core_rx_last_be_sink_first = core_rx_padding_source_first; assign core_rx_last_be_sink_last = core_rx_padding_source_last; assign core_rx_last_be_sink_payload_data = core_rx_padding_source_payload_data; assign core_rx_last_be_sink_payload_last_be = core_rx_padding_source_payload_last_be; assign core_rx_last_be_sink_payload_error = core_rx_padding_source_payload_error; assign core_rx_converter_sink_valid = core_rx_last_be_source_valid; assign core_rx_last_be_source_ready = core_rx_converter_sink_ready; assign core_rx_converter_sink_first = core_rx_last_be_source_first; assign core_rx_converter_sink_last = core_rx_last_be_source_last; assign core_rx_converter_sink_payload_data = core_rx_last_be_source_payload_data; assign core_rx_converter_sink_payload_last_be = core_rx_last_be_source_payload_last_be; assign core_rx_converter_sink_payload_error = core_rx_last_be_source_payload_error; assign core_rx_cdc_sink_sink_valid = core_rx_converter_source_valid; assign core_rx_converter_source_ready = core_rx_cdc_sink_sink_ready; assign core_rx_cdc_sink_sink_first = core_rx_converter_source_first; assign core_rx_cdc_sink_sink_last = core_rx_converter_source_last; assign core_rx_cdc_sink_sink_payload_data = core_rx_converter_source_payload_data; assign core_rx_cdc_sink_sink_payload_last_be = core_rx_converter_source_payload_last_be; assign core_rx_cdc_sink_sink_payload_error = core_rx_converter_source_payload_error; assign core_source_valid = core_rx_cdc_source_source_valid; assign core_rx_cdc_source_source_ready = core_source_ready; assign core_source_first = core_rx_cdc_source_source_first; assign core_source_last = core_rx_cdc_source_source_last; assign core_source_payload_data = core_rx_cdc_source_source_payload_data; assign core_source_payload_last_be = core_rx_cdc_source_source_payload_last_be; assign core_source_payload_error = core_rx_cdc_source_source_payload_error; assign wishbone_interface_writer_sink_sink_valid = wishbone_interface_sink_valid; assign wishbone_interface_sink_ready = wishbone_interface_writer_sink_sink_ready; assign wishbone_interface_writer_sink_sink_first = wishbone_interface_sink_first; assign wishbone_interface_writer_sink_sink_last = wishbone_interface_sink_last; assign wishbone_interface_writer_sink_sink_payload_data = wishbone_interface_sink_payload_data; assign wishbone_interface_writer_sink_sink_payload_last_be = wishbone_interface_sink_payload_last_be; assign wishbone_interface_writer_sink_sink_payload_error = wishbone_interface_sink_payload_error; assign wishbone_interface_source_valid = wishbone_interface_reader_source_source_valid; assign wishbone_interface_reader_source_source_ready = wishbone_interface_source_ready; assign wishbone_interface_source_first = wishbone_interface_reader_source_source_first; assign wishbone_interface_source_last = wishbone_interface_reader_source_source_last; assign wishbone_interface_source_payload_data = wishbone_interface_reader_source_source_payload_data; assign wishbone_interface_source_payload_last_be = wishbone_interface_reader_source_source_payload_last_be; assign wishbone_interface_source_payload_error = wishbone_interface_reader_source_source_payload_error; always @(*) begin wishbone_interface_writer_length_inc <= 4'd0; case (wishbone_interface_writer_sink_sink_payload_last_be) 1'd1: begin wishbone_interface_writer_length_inc <= 1'd1; end 2'd2: begin wishbone_interface_writer_length_inc <= 2'd2; end 3'd4: begin wishbone_interface_writer_length_inc <= 2'd3; end 4'd8: begin wishbone_interface_writer_length_inc <= 3'd4; end 5'd16: begin wishbone_interface_writer_length_inc <= 3'd5; end 6'd32: begin wishbone_interface_writer_length_inc <= 3'd6; end 7'd64: begin wishbone_interface_writer_length_inc <= 3'd7; end default: begin wishbone_interface_writer_length_inc <= 3'd4; end endcase end assign wishbone_interface_writer_stat_fifo_source_ready = wishbone_interface_writer_available_clear; assign wishbone_interface_writer_available_trigger = wishbone_interface_writer_stat_fifo_source_valid; assign wishbone_interface_writer_slot_status = wishbone_interface_writer_stat_fifo_source_payload_slot; assign wishbone_interface_writer_length_status = wishbone_interface_writer_stat_fifo_source_payload_length; assign wishbone_interface_writer_wr_data = wishbone_interface_writer_sink_sink_payload_data; always @(*) begin wishbone_interface_writer_memory0_adr <= 9'd0; wishbone_interface_writer_memory0_dat_w <= 32'd0; wishbone_interface_writer_memory0_we <= 1'd0; wishbone_interface_writer_memory1_adr <= 9'd0; wishbone_interface_writer_memory1_dat_w <= 32'd0; wishbone_interface_writer_memory1_we <= 1'd0; case (wishbone_interface_writer_slot) 1'd0: begin wishbone_interface_writer_memory0_adr <= wishbone_interface_writer_length[10:2]; wishbone_interface_writer_memory0_dat_w <= wishbone_interface_writer_wr_data; if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin wishbone_interface_writer_memory0_we <= 1'd1; end end 1'd1: begin wishbone_interface_writer_memory1_adr <= wishbone_interface_writer_length[10:2]; wishbone_interface_writer_memory1_dat_w <= wishbone_interface_writer_wr_data; if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_write)) begin wishbone_interface_writer_memory1_we <= 1'd1; end end endcase end assign wishbone_interface_writer_available0 = wishbone_interface_writer_available_status; assign wishbone_interface_writer_available1 = wishbone_interface_writer_available_pending; always @(*) begin wishbone_interface_writer_available_clear <= 1'd0; if ((wishbone_interface_writer_pending_re & wishbone_interface_writer_pending_r)) begin wishbone_interface_writer_available_clear <= 1'd1; end end assign wishbone_interface_writer_irq = (wishbone_interface_writer_pending_status & wishbone_interface_writer_enable_storage); assign wishbone_interface_writer_available_status = wishbone_interface_writer_available_trigger; assign wishbone_interface_writer_available_pending = wishbone_interface_writer_available_trigger; assign wishbone_interface_writer_stat_fifo_syncfifo_din = {wishbone_interface_writer_stat_fifo_fifo_in_last, wishbone_interface_writer_stat_fifo_fifo_in_first, wishbone_interface_writer_stat_fifo_fifo_in_payload_length, wishbone_interface_writer_stat_fifo_fifo_in_payload_slot}; assign {wishbone_interface_writer_stat_fifo_fifo_out_last, wishbone_interface_writer_stat_fifo_fifo_out_first, wishbone_interface_writer_stat_fifo_fifo_out_payload_length, wishbone_interface_writer_stat_fifo_fifo_out_payload_slot} = wishbone_interface_writer_stat_fifo_syncfifo_dout; assign wishbone_interface_writer_stat_fifo_sink_ready = wishbone_interface_writer_stat_fifo_syncfifo_writable; assign wishbone_interface_writer_stat_fifo_syncfifo_we = wishbone_interface_writer_stat_fifo_sink_valid; assign wishbone_interface_writer_stat_fifo_fifo_in_first = wishbone_interface_writer_stat_fifo_sink_first; assign wishbone_interface_writer_stat_fifo_fifo_in_last = wishbone_interface_writer_stat_fifo_sink_last; assign wishbone_interface_writer_stat_fifo_fifo_in_payload_slot = wishbone_interface_writer_stat_fifo_sink_payload_slot; assign wishbone_interface_writer_stat_fifo_fifo_in_payload_length = wishbone_interface_writer_stat_fifo_sink_payload_length; assign wishbone_interface_writer_stat_fifo_source_valid = wishbone_interface_writer_stat_fifo_syncfifo_readable; assign wishbone_interface_writer_stat_fifo_source_first = wishbone_interface_writer_stat_fifo_fifo_out_first; assign wishbone_interface_writer_stat_fifo_source_last = wishbone_interface_writer_stat_fifo_fifo_out_last; assign wishbone_interface_writer_stat_fifo_source_payload_slot = wishbone_interface_writer_stat_fifo_fifo_out_payload_slot; assign wishbone_interface_writer_stat_fifo_source_payload_length = wishbone_interface_writer_stat_fifo_fifo_out_payload_length; assign wishbone_interface_writer_stat_fifo_syncfifo_re = wishbone_interface_writer_stat_fifo_source_ready; always @(*) begin wishbone_interface_writer_stat_fifo_wrport_adr <= 1'd0; if (wishbone_interface_writer_stat_fifo_replace) begin wishbone_interface_writer_stat_fifo_wrport_adr <= (wishbone_interface_writer_stat_fifo_produce - 1'd1); end else begin wishbone_interface_writer_stat_fifo_wrport_adr <= wishbone_interface_writer_stat_fifo_produce; end end assign wishbone_interface_writer_stat_fifo_wrport_dat_w = wishbone_interface_writer_stat_fifo_syncfifo_din; assign wishbone_interface_writer_stat_fifo_wrport_we = (wishbone_interface_writer_stat_fifo_syncfifo_we & (wishbone_interface_writer_stat_fifo_syncfifo_writable | wishbone_interface_writer_stat_fifo_replace)); assign wishbone_interface_writer_stat_fifo_do_read = (wishbone_interface_writer_stat_fifo_syncfifo_readable & wishbone_interface_writer_stat_fifo_syncfifo_re); assign wishbone_interface_writer_stat_fifo_rdport_adr = wishbone_interface_writer_stat_fifo_consume; assign wishbone_interface_writer_stat_fifo_syncfifo_dout = wishbone_interface_writer_stat_fifo_rdport_dat_r; assign wishbone_interface_writer_stat_fifo_syncfifo_writable = (wishbone_interface_writer_stat_fifo_level != 2'd2); assign wishbone_interface_writer_stat_fifo_syncfifo_readable = (wishbone_interface_writer_stat_fifo_level != 1'd0); always @(*) begin liteethmacsramwriter_next_state <= 3'd0; wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= 32'd0; wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 11'd0; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= 1'd0; wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd0; wishbone_interface_writer_stat_fifo_sink_payload_length <= 11'd0; wishbone_interface_writer_stat_fifo_sink_payload_slot <= 1'd0; wishbone_interface_writer_stat_fifo_sink_valid <= 1'd0; wishbone_interface_writer_write <= 1'd0; liteethmacsramwriter_next_state <= liteethmacsramwriter_state; case (liteethmacsramwriter_state) 1'd1: begin if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin liteethmacsramwriter_next_state <= 2'd3; end else begin liteethmacsramwriter_next_state <= 3'd4; end end end 2'd2: begin if ((wishbone_interface_writer_sink_sink_valid & wishbone_interface_writer_sink_sink_last)) begin if ((wishbone_interface_writer_sink_sink_payload_last_be != 1'd0)) begin liteethmacsramwriter_next_state <= 2'd3; end else begin wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; liteethmacsramwriter_next_state <= 1'd0; end end end 2'd3: begin wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; liteethmacsramwriter_next_state <= 1'd0; end 3'd4: begin wishbone_interface_writer_stat_fifo_sink_valid <= 1'd1; wishbone_interface_writer_stat_fifo_sink_payload_slot <= wishbone_interface_writer_slot; wishbone_interface_writer_stat_fifo_sink_payload_length <= wishbone_interface_writer_length; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= 1'd0; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; wishbone_interface_writer_slot_liteethmacsramwriter_next_value <= (wishbone_interface_writer_slot + 1'd1); wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce <= 1'd1; liteethmacsramwriter_next_state <= 1'd0; end default: begin if (wishbone_interface_writer_sink_sink_valid) begin if (wishbone_interface_writer_stat_fifo_sink_ready) begin wishbone_interface_writer_write <= 1'd1; wishbone_interface_writer_length_liteethmacsramwriter_t_next_value <= (wishbone_interface_writer_length + wishbone_interface_writer_length_inc); wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; if ((wishbone_interface_writer_length >= 11'd1530)) begin liteethmacsramwriter_next_state <= 1'd1; end if (wishbone_interface_writer_sink_sink_last) begin if (((wishbone_interface_writer_sink_sink_payload_error & wishbone_interface_writer_sink_sink_payload_last_be) != 1'd0)) begin liteethmacsramwriter_next_state <= 2'd3; end else begin liteethmacsramwriter_next_state <= 3'd4; end end end else begin wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value <= (wishbone_interface_writer_errors_status + 1'd1); wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; liteethmacsramwriter_next_state <= 2'd2; end end end endcase end assign wishbone_interface_reader_cmd_fifo_sink_valid = wishbone_interface_reader_start_re; assign wishbone_interface_reader_cmd_fifo_sink_payload_slot = wishbone_interface_reader_slot_storage; assign wishbone_interface_reader_cmd_fifo_sink_payload_length = wishbone_interface_reader_length_storage; assign wishbone_interface_reader_ready_status = wishbone_interface_reader_cmd_fifo_sink_ready; assign wishbone_interface_reader_level_status = wishbone_interface_reader_cmd_fifo_level; always @(*) begin wishbone_interface_reader_source_source_payload_last_be <= 4'd0; if (wishbone_interface_reader_source_source_last) begin case (wishbone_interface_reader_cmd_fifo_source_payload_length[1:0]) 1'd1: begin wishbone_interface_reader_source_source_payload_last_be <= 1'd1; end 2'd2: begin wishbone_interface_reader_source_source_payload_last_be <= 2'd2; end 2'd3: begin wishbone_interface_reader_source_source_payload_last_be <= 3'd4; end 3'd4: begin wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end 3'd5: begin wishbone_interface_reader_source_source_payload_last_be <= 5'd16; end 3'd6: begin wishbone_interface_reader_source_source_payload_last_be <= 6'd32; end 3'd7: begin wishbone_interface_reader_source_source_payload_last_be <= 7'd64; end default: begin wishbone_interface_reader_source_source_payload_last_be <= 4'd8; end endcase end end assign wishbone_interface_reader_memory0_re = wishbone_interface_reader_read; assign wishbone_interface_reader_memory0_adr = wishbone_interface_reader_length[10:2]; assign wishbone_interface_reader_memory1_re = wishbone_interface_reader_read; assign wishbone_interface_reader_memory1_adr = wishbone_interface_reader_length[10:2]; always @(*) begin wishbone_interface_reader_rd_data <= 32'd0; case (wishbone_interface_reader_cmd_fifo_source_payload_slot) 1'd0: begin wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory0_dat_r; end 1'd1: begin wishbone_interface_reader_rd_data <= wishbone_interface_reader_memory1_dat_r; end endcase end assign wishbone_interface_reader_source_source_payload_data = wishbone_interface_reader_rd_data; assign wishbone_interface_reader_event00 = wishbone_interface_reader_eventsourcepulse_status; assign wishbone_interface_reader_event01 = wishbone_interface_reader_eventsourcepulse_pending; always @(*) begin wishbone_interface_reader_eventsourcepulse_clear <= 1'd0; if ((wishbone_interface_reader_pending_re & wishbone_interface_reader_pending_r)) begin wishbone_interface_reader_eventsourcepulse_clear <= 1'd1; end end assign wishbone_interface_reader_irq = (wishbone_interface_reader_pending_status & wishbone_interface_reader_enable_storage); assign wishbone_interface_reader_eventsourcepulse_status = 1'd0; assign wishbone_interface_reader_cmd_fifo_syncfifo_din = {wishbone_interface_reader_cmd_fifo_fifo_in_last, wishbone_interface_reader_cmd_fifo_fifo_in_first, wishbone_interface_reader_cmd_fifo_fifo_in_payload_length, wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot}; assign {wishbone_interface_reader_cmd_fifo_fifo_out_last, wishbone_interface_reader_cmd_fifo_fifo_out_first, wishbone_interface_reader_cmd_fifo_fifo_out_payload_length, wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot} = wishbone_interface_reader_cmd_fifo_syncfifo_dout; assign wishbone_interface_reader_cmd_fifo_sink_ready = wishbone_interface_reader_cmd_fifo_syncfifo_writable; assign wishbone_interface_reader_cmd_fifo_syncfifo_we = wishbone_interface_reader_cmd_fifo_sink_valid; assign wishbone_interface_reader_cmd_fifo_fifo_in_first = wishbone_interface_reader_cmd_fifo_sink_first; assign wishbone_interface_reader_cmd_fifo_fifo_in_last = wishbone_interface_reader_cmd_fifo_sink_last; assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_slot = wishbone_interface_reader_cmd_fifo_sink_payload_slot; assign wishbone_interface_reader_cmd_fifo_fifo_in_payload_length = wishbone_interface_reader_cmd_fifo_sink_payload_length; assign wishbone_interface_reader_cmd_fifo_source_valid = wishbone_interface_reader_cmd_fifo_syncfifo_readable; assign wishbone_interface_reader_cmd_fifo_source_first = wishbone_interface_reader_cmd_fifo_fifo_out_first; assign wishbone_interface_reader_cmd_fifo_source_last = wishbone_interface_reader_cmd_fifo_fifo_out_last; assign wishbone_interface_reader_cmd_fifo_source_payload_slot = wishbone_interface_reader_cmd_fifo_fifo_out_payload_slot; assign wishbone_interface_reader_cmd_fifo_source_payload_length = wishbone_interface_reader_cmd_fifo_fifo_out_payload_length; assign wishbone_interface_reader_cmd_fifo_syncfifo_re = wishbone_interface_reader_cmd_fifo_source_ready; always @(*) begin wishbone_interface_reader_cmd_fifo_wrport_adr <= 1'd0; if (wishbone_interface_reader_cmd_fifo_replace) begin wishbone_interface_reader_cmd_fifo_wrport_adr <= (wishbone_interface_reader_cmd_fifo_produce - 1'd1); end else begin wishbone_interface_reader_cmd_fifo_wrport_adr <= wishbone_interface_reader_cmd_fifo_produce; end end assign wishbone_interface_reader_cmd_fifo_wrport_dat_w = wishbone_interface_reader_cmd_fifo_syncfifo_din; assign wishbone_interface_reader_cmd_fifo_wrport_we = (wishbone_interface_reader_cmd_fifo_syncfifo_we & (wishbone_interface_reader_cmd_fifo_syncfifo_writable | wishbone_interface_reader_cmd_fifo_replace)); assign wishbone_interface_reader_cmd_fifo_do_read = (wishbone_interface_reader_cmd_fifo_syncfifo_readable & wishbone_interface_reader_cmd_fifo_syncfifo_re); assign wishbone_interface_reader_cmd_fifo_rdport_adr = wishbone_interface_reader_cmd_fifo_consume; assign wishbone_interface_reader_cmd_fifo_syncfifo_dout = wishbone_interface_reader_cmd_fifo_rdport_dat_r; assign wishbone_interface_reader_cmd_fifo_syncfifo_writable = (wishbone_interface_reader_cmd_fifo_level != 2'd2); assign wishbone_interface_reader_cmd_fifo_syncfifo_readable = (wishbone_interface_reader_cmd_fifo_level != 1'd0); always @(*) begin liteethmacsramreader_next_state <= 2'd0; wishbone_interface_reader_cmd_fifo_source_ready <= 1'd0; wishbone_interface_reader_eventsourcepulse_trigger <= 1'd0; wishbone_interface_reader_length_liteethmacsramreader_next_value <= 11'd0; wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd0; wishbone_interface_reader_read <= 1'd0; wishbone_interface_reader_source_source_last <= 1'd0; wishbone_interface_reader_source_source_valid <= 1'd0; liteethmacsramreader_next_state <= liteethmacsramreader_state; case (liteethmacsramreader_state) 1'd1: begin wishbone_interface_reader_source_source_valid <= 1'd1; wishbone_interface_reader_source_source_last <= (wishbone_interface_reader_length >= wishbone_interface_reader_cmd_fifo_source_payload_length); if (wishbone_interface_reader_source_source_ready) begin wishbone_interface_reader_read <= 1'd1; wishbone_interface_reader_length_liteethmacsramreader_next_value <= (wishbone_interface_reader_length + 3'd4); wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; if (wishbone_interface_reader_source_source_last) begin liteethmacsramreader_next_state <= 2'd2; end end end 2'd2: begin wishbone_interface_reader_length_liteethmacsramreader_next_value <= 1'd0; wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; wishbone_interface_reader_eventsourcepulse_trigger <= 1'd1; wishbone_interface_reader_cmd_fifo_source_ready <= 1'd1; liteethmacsramreader_next_state <= 1'd0; end default: begin if (wishbone_interface_reader_cmd_fifo_source_valid) begin wishbone_interface_reader_read <= 1'd1; wishbone_interface_reader_length_liteethmacsramreader_next_value <= 3'd4; wishbone_interface_reader_length_liteethmacsramreader_next_value_ce <= 1'd1; liteethmacsramreader_next_state <= 1'd1; end end endcase end assign wishbone_interface_ev_irq = (wishbone_interface_writer_irq | wishbone_interface_reader_irq); assign wishbone_interface_sram0_adr = wishbone_interface_interface0_adr[8:0]; assign wishbone_interface_interface0_dat_r = wishbone_interface_sram0_dat_r; assign wishbone_interface_sram1_adr = wishbone_interface_interface1_adr[8:0]; assign wishbone_interface_interface1_dat_r = wishbone_interface_sram1_dat_r; always @(*) begin wishbone_interface_decoder0_slave_sel <= 2'd0; wishbone_interface_decoder0_slave_sel[0] <= (wishbone_interface_bus_rx_adr[9] == 1'd0); wishbone_interface_decoder0_slave_sel[1] <= (wishbone_interface_bus_rx_adr[9] == 1'd1); end assign wishbone_interface_interface0_adr = wishbone_interface_bus_rx_adr; assign wishbone_interface_interface0_dat_w = wishbone_interface_bus_rx_dat_w; assign wishbone_interface_interface0_sel = wishbone_interface_bus_rx_sel; assign wishbone_interface_interface0_stb = wishbone_interface_bus_rx_stb; assign wishbone_interface_interface0_we = wishbone_interface_bus_rx_we; assign wishbone_interface_interface0_cti = wishbone_interface_bus_rx_cti; assign wishbone_interface_interface0_bte = wishbone_interface_bus_rx_bte; assign wishbone_interface_interface1_adr = wishbone_interface_bus_rx_adr; assign wishbone_interface_interface1_dat_w = wishbone_interface_bus_rx_dat_w; assign wishbone_interface_interface1_sel = wishbone_interface_bus_rx_sel; assign wishbone_interface_interface1_stb = wishbone_interface_bus_rx_stb; assign wishbone_interface_interface1_we = wishbone_interface_bus_rx_we; assign wishbone_interface_interface1_cti = wishbone_interface_bus_rx_cti; assign wishbone_interface_interface1_bte = wishbone_interface_bus_rx_bte; assign wishbone_interface_interface0_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[0]); assign wishbone_interface_interface1_cyc = (wishbone_interface_bus_rx_cyc & wishbone_interface_decoder0_slave_sel[1]); assign wishbone_interface_bus_rx_ack = (wishbone_interface_interface0_ack | wishbone_interface_interface1_ack); assign wishbone_interface_bus_rx_err = (wishbone_interface_interface0_err | wishbone_interface_interface1_err); assign wishbone_interface_bus_rx_dat_r = (({32{wishbone_interface_decoder0_slave_sel_r[0]}} & wishbone_interface_interface0_dat_r) | ({32{wishbone_interface_decoder0_slave_sel_r[1]}} & wishbone_interface_interface1_dat_r)); always @(*) begin wishbone_interface_sram2_we <= 4'd0; wishbone_interface_sram2_we[0] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[0]); wishbone_interface_sram2_we[1] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[1]); wishbone_interface_sram2_we[2] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[2]); wishbone_interface_sram2_we[3] <= (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & wishbone_interface_interface2_we) & wishbone_interface_interface2_sel[3]); end assign wishbone_interface_sram2_adr = wishbone_interface_interface2_adr[8:0]; assign wishbone_interface_interface2_dat_r = wishbone_interface_sram2_dat_r; assign wishbone_interface_sram2_dat_w = wishbone_interface_interface2_dat_w; always @(*) begin wishbone_interface_sram3_we <= 4'd0; wishbone_interface_sram3_we[0] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[0]); wishbone_interface_sram3_we[1] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[1]); wishbone_interface_sram3_we[2] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[2]); wishbone_interface_sram3_we[3] <= (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & wishbone_interface_interface3_we) & wishbone_interface_interface3_sel[3]); end assign wishbone_interface_sram3_adr = wishbone_interface_interface3_adr[8:0]; assign wishbone_interface_interface3_dat_r = wishbone_interface_sram3_dat_r; assign wishbone_interface_sram3_dat_w = wishbone_interface_interface3_dat_w; always @(*) begin wishbone_interface_decoder1_slave_sel <= 2'd0; wishbone_interface_decoder1_slave_sel[0] <= (wishbone_interface_bus_tx_adr[9] == 1'd0); wishbone_interface_decoder1_slave_sel[1] <= (wishbone_interface_bus_tx_adr[9] == 1'd1); end assign wishbone_interface_interface2_adr = wishbone_interface_bus_tx_adr; assign wishbone_interface_interface2_dat_w = wishbone_interface_bus_tx_dat_w; assign wishbone_interface_interface2_sel = wishbone_interface_bus_tx_sel; assign wishbone_interface_interface2_stb = wishbone_interface_bus_tx_stb; assign wishbone_interface_interface2_we = wishbone_interface_bus_tx_we; assign wishbone_interface_interface2_cti = wishbone_interface_bus_tx_cti; assign wishbone_interface_interface2_bte = wishbone_interface_bus_tx_bte; assign wishbone_interface_interface3_adr = wishbone_interface_bus_tx_adr; assign wishbone_interface_interface3_dat_w = wishbone_interface_bus_tx_dat_w; assign wishbone_interface_interface3_sel = wishbone_interface_bus_tx_sel; assign wishbone_interface_interface3_stb = wishbone_interface_bus_tx_stb; assign wishbone_interface_interface3_we = wishbone_interface_bus_tx_we; assign wishbone_interface_interface3_cti = wishbone_interface_bus_tx_cti; assign wishbone_interface_interface3_bte = wishbone_interface_bus_tx_bte; assign wishbone_interface_interface2_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[0]); assign wishbone_interface_interface3_cyc = (wishbone_interface_bus_tx_cyc & wishbone_interface_decoder1_slave_sel[1]); assign wishbone_interface_bus_tx_ack = (wishbone_interface_interface2_ack | wishbone_interface_interface3_ack); assign wishbone_interface_bus_tx_err = (wishbone_interface_interface2_err | wishbone_interface_interface3_err); assign wishbone_interface_bus_tx_dat_r = (({32{wishbone_interface_decoder1_slave_sel_r[0]}} & wishbone_interface_interface2_dat_r) | ({32{wishbone_interface_decoder1_slave_sel_r[1]}} & wishbone_interface_interface3_dat_r)); always @(*) begin interface0_ack <= 1'd0; interface0_dat_r <= 32'd0; interface1_adr <= 14'd0; interface1_dat_w <= 32'd0; interface1_re <= 1'd0; interface1_we <= 1'd0; wishbone2csr_next_state <= 1'd0; wishbone2csr_next_state <= wishbone2csr_state; case (wishbone2csr_state) 1'd1: begin interface0_ack <= 1'd1; interface0_dat_r <= interface1_dat_r; wishbone2csr_next_state <= 1'd0; end default: begin interface1_dat_w <= interface0_dat_w; if ((interface0_cyc & interface0_stb)) begin interface1_adr <= interface0_adr; interface1_re <= ((~interface0_we) & (interface0_sel != 1'd0)); interface1_we <= (interface0_we & (interface0_sel != 1'd0)); wishbone2csr_next_state <= 1'd1; end end endcase end assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; always @(*) begin csrbank0_reset0_re <= 1'd0; csrbank0_reset0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin csrbank0_reset0_re <= interface0_bank_bus_we; csrbank0_reset0_we <= interface0_bank_bus_re; end end assign csrbank0_scratch0_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_scratch0_re <= 1'd0; csrbank0_scratch0_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin csrbank0_scratch0_re <= interface0_bank_bus_we; csrbank0_scratch0_we <= interface0_bank_bus_re; end end assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w; always @(*) begin csrbank0_bus_errors_re <= 1'd0; csrbank0_bus_errors_we <= 1'd0; if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin csrbank0_bus_errors_re <= interface0_bank_bus_we; csrbank0_bus_errors_we <= interface0_bank_bus_re; end end always @(*) begin maccore_maccore_soc_rst <= 1'd0; if (maccore_maccore_reset_re) begin maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0]; end end assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1]; assign csrbank0_reset0_w = maccore_maccore_reset_storage; assign csrbank0_scratch0_w = maccore_maccore_scratch_storage; assign csrbank0_bus_errors_w = maccore_maccore_bus_errors_status; assign maccore_maccore_bus_errors_we = csrbank0_bus_errors_we; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 2'd2); assign csrbank1_sram_writer_slot_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_writer_slot_re <= 1'd0; csrbank1_sram_writer_slot_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin csrbank1_sram_writer_slot_re <= interface1_bank_bus_we; csrbank1_sram_writer_slot_we <= interface1_bank_bus_re; end end assign csrbank1_sram_writer_length_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin csrbank1_sram_writer_length_re <= 1'd0; csrbank1_sram_writer_length_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin csrbank1_sram_writer_length_re <= interface1_bank_bus_we; csrbank1_sram_writer_length_we <= interface1_bank_bus_re; end end assign csrbank1_sram_writer_errors_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_sram_writer_errors_re <= 1'd0; csrbank1_sram_writer_errors_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin csrbank1_sram_writer_errors_re <= interface1_bank_bus_we; csrbank1_sram_writer_errors_we <= interface1_bank_bus_re; end end assign csrbank1_sram_writer_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_writer_ev_status_re <= 1'd0; csrbank1_sram_writer_ev_status_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin csrbank1_sram_writer_ev_status_re <= interface1_bank_bus_we; csrbank1_sram_writer_ev_status_we <= interface1_bank_bus_re; end end assign csrbank1_sram_writer_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_writer_ev_pending_re <= 1'd0; csrbank1_sram_writer_ev_pending_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin csrbank1_sram_writer_ev_pending_re <= interface1_bank_bus_we; csrbank1_sram_writer_ev_pending_we <= interface1_bank_bus_re; end end assign csrbank1_sram_writer_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_writer_ev_enable0_re <= 1'd0; csrbank1_sram_writer_ev_enable0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin csrbank1_sram_writer_ev_enable0_re <= interface1_bank_bus_we; csrbank1_sram_writer_ev_enable0_we <= interface1_bank_bus_re; end end assign wishbone_interface_reader_start_r = interface1_bank_bus_dat_w[0]; always @(*) begin wishbone_interface_reader_start_re <= 1'd0; wishbone_interface_reader_start_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin wishbone_interface_reader_start_re <= interface1_bank_bus_we; wishbone_interface_reader_start_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_ready_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_reader_ready_re <= 1'd0; csrbank1_sram_reader_ready_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin csrbank1_sram_reader_ready_re <= interface1_bank_bus_we; csrbank1_sram_reader_ready_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_level_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin csrbank1_sram_reader_level_re <= 1'd0; csrbank1_sram_reader_level_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin csrbank1_sram_reader_level_re <= interface1_bank_bus_we; csrbank1_sram_reader_level_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_slot0_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_reader_slot0_re <= 1'd0; csrbank1_sram_reader_slot0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin csrbank1_sram_reader_slot0_re <= interface1_bank_bus_we; csrbank1_sram_reader_slot0_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_length0_r = interface1_bank_bus_dat_w[10:0]; always @(*) begin csrbank1_sram_reader_length0_re <= 1'd0; csrbank1_sram_reader_length0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin csrbank1_sram_reader_length0_re <= interface1_bank_bus_we; csrbank1_sram_reader_length0_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_ev_status_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_reader_ev_status_re <= 1'd0; csrbank1_sram_reader_ev_status_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin csrbank1_sram_reader_ev_status_re <= interface1_bank_bus_we; csrbank1_sram_reader_ev_status_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_ev_pending_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_reader_ev_pending_re <= 1'd0; csrbank1_sram_reader_ev_pending_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin csrbank1_sram_reader_ev_pending_re <= interface1_bank_bus_we; csrbank1_sram_reader_ev_pending_we <= interface1_bank_bus_re; end end assign csrbank1_sram_reader_ev_enable0_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_sram_reader_ev_enable0_re <= 1'd0; csrbank1_sram_reader_ev_enable0_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin csrbank1_sram_reader_ev_enable0_re <= interface1_bank_bus_we; csrbank1_sram_reader_ev_enable0_we <= interface1_bank_bus_re; end end assign csrbank1_preamble_crc_r = interface1_bank_bus_dat_w[0]; always @(*) begin csrbank1_preamble_crc_re <= 1'd0; csrbank1_preamble_crc_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin csrbank1_preamble_crc_re <= interface1_bank_bus_we; csrbank1_preamble_crc_we <= interface1_bank_bus_re; end end assign csrbank1_rx_datapath_preamble_errors_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_rx_datapath_preamble_errors_re <= 1'd0; csrbank1_rx_datapath_preamble_errors_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin csrbank1_rx_datapath_preamble_errors_re <= interface1_bank_bus_we; csrbank1_rx_datapath_preamble_errors_we <= interface1_bank_bus_re; end end assign csrbank1_rx_datapath_crc_errors_r = interface1_bank_bus_dat_w; always @(*) begin csrbank1_rx_datapath_crc_errors_re <= 1'd0; csrbank1_rx_datapath_crc_errors_we <= 1'd0; if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin csrbank1_rx_datapath_crc_errors_re <= interface1_bank_bus_we; csrbank1_rx_datapath_crc_errors_we <= interface1_bank_bus_re; end end assign csrbank1_sram_writer_slot_w = wishbone_interface_writer_slot_status; assign wishbone_interface_writer_slot_we = csrbank1_sram_writer_slot_we; assign csrbank1_sram_writer_length_w = wishbone_interface_writer_length_status; assign wishbone_interface_writer_length_we = csrbank1_sram_writer_length_we; assign csrbank1_sram_writer_errors_w = wishbone_interface_writer_errors_status; assign wishbone_interface_writer_errors_we = csrbank1_sram_writer_errors_we; assign wishbone_interface_writer_status_status = wishbone_interface_writer_available0; assign csrbank1_sram_writer_ev_status_w = wishbone_interface_writer_status_status; assign wishbone_interface_writer_status_we = csrbank1_sram_writer_ev_status_we; assign wishbone_interface_writer_pending_status = wishbone_interface_writer_available1; assign csrbank1_sram_writer_ev_pending_w = wishbone_interface_writer_pending_status; assign wishbone_interface_writer_pending_we = csrbank1_sram_writer_ev_pending_we; assign wishbone_interface_writer_available2 = wishbone_interface_writer_enable_storage; assign csrbank1_sram_writer_ev_enable0_w = wishbone_interface_writer_enable_storage; assign csrbank1_sram_reader_ready_w = wishbone_interface_reader_ready_status; assign wishbone_interface_reader_ready_we = csrbank1_sram_reader_ready_we; assign csrbank1_sram_reader_level_w = wishbone_interface_reader_level_status; assign wishbone_interface_reader_level_we = csrbank1_sram_reader_level_we; assign csrbank1_sram_reader_slot0_w = wishbone_interface_reader_slot_storage; assign csrbank1_sram_reader_length0_w = wishbone_interface_reader_length_storage; assign wishbone_interface_reader_status_status = wishbone_interface_reader_event00; assign csrbank1_sram_reader_ev_status_w = wishbone_interface_reader_status_status; assign wishbone_interface_reader_status_we = csrbank1_sram_reader_ev_status_we; assign wishbone_interface_reader_pending_status = wishbone_interface_reader_event01; assign csrbank1_sram_reader_ev_pending_w = wishbone_interface_reader_pending_status; assign wishbone_interface_reader_pending_we = csrbank1_sram_reader_ev_pending_we; assign wishbone_interface_reader_event02 = wishbone_interface_reader_enable_storage; assign csrbank1_sram_reader_ev_enable0_w = wishbone_interface_reader_enable_storage; assign csrbank1_preamble_crc_w = core_status; assign core_we = csrbank1_preamble_crc_we; assign csrbank1_rx_datapath_preamble_errors_w = core_preamble_errors_status; assign core_preamble_errors_we = csrbank1_rx_datapath_preamble_errors_we; assign csrbank1_rx_datapath_crc_errors_w = core_crc_errors_status; assign core_crc_errors_we = csrbank1_rx_datapath_crc_errors_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); assign csrbank2_mode_detection_mode_r = interface2_bank_bus_dat_w[0]; always @(*) begin csrbank2_mode_detection_mode_re <= 1'd0; csrbank2_mode_detection_mode_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin csrbank2_mode_detection_mode_re <= interface2_bank_bus_we; csrbank2_mode_detection_mode_we <= interface2_bank_bus_re; end end assign csrbank2_crg_reset0_r = interface2_bank_bus_dat_w[0]; always @(*) begin csrbank2_crg_reset0_re <= 1'd0; csrbank2_crg_reset0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin csrbank2_crg_reset0_re <= interface2_bank_bus_we; csrbank2_crg_reset0_we <= interface2_bank_bus_re; end end assign csrbank2_mdio_w0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin csrbank2_mdio_w0_re <= 1'd0; csrbank2_mdio_w0_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin csrbank2_mdio_w0_re <= interface2_bank_bus_we; csrbank2_mdio_w0_we <= interface2_bank_bus_re; end end assign csrbank2_mdio_r_r = interface2_bank_bus_dat_w[0]; always @(*) begin csrbank2_mdio_r_re <= 1'd0; csrbank2_mdio_r_we <= 1'd0; if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin csrbank2_mdio_r_re <= interface2_bank_bus_we; csrbank2_mdio_r_we <= interface2_bank_bus_re; end end assign csrbank2_mode_detection_mode_w = maccore_ethphy_mode_status; assign maccore_ethphy_mode_we = csrbank2_mode_detection_mode_we; assign csrbank2_crg_reset0_w = maccore_ethphy_reset_storage; assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0]; assign maccore_ethphy_oe = maccore_ethphy__w_storage[1]; assign maccore_ethphy_w = maccore_ethphy__w_storage[2]; assign csrbank2_mdio_w0_w = maccore_ethphy__w_storage; assign csrbank2_mdio_r_w = maccore_ethphy__r_status; assign maccore_ethphy__r_we = csrbank2_mdio_r_we; assign adr = interface1_adr; assign re = interface1_re; assign we = interface1_we; assign dat_w = interface1_dat_w; assign interface1_dat_r = dat_r; assign interface0_bank_bus_adr = adr; assign interface1_bank_bus_adr = adr; assign interface2_bank_bus_adr = adr; assign interface0_bank_bus_re = re; assign interface1_bank_bus_re = re; assign interface2_bank_bus_re = re; assign interface0_bank_bus_we = we; assign interface1_bank_bus_we = we; assign interface2_bank_bus_we = we; assign interface0_bank_bus_dat_w = dat_w; assign interface1_bank_bus_dat_w = dat_w; assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin self0 <= 30'd0; case (grant) default: begin self0 <= wb_bus_adr; end endcase end always @(*) begin self1 <= 32'd0; case (grant) default: begin self1 <= wb_bus_dat_w; end endcase end always @(*) begin self2 <= 4'd0; case (grant) default: begin self2 <= wb_bus_sel; end endcase end always @(*) begin self3 <= 1'd0; case (grant) default: begin self3 <= wb_bus_cyc; end endcase end always @(*) begin self4 <= 1'd0; case (grant) default: begin self4 <= wb_bus_stb; end endcase end always @(*) begin self5 <= 1'd0; case (grant) default: begin self5 <= wb_bus_we; end endcase end always @(*) begin self6 <= 3'd0; case (grant) default: begin self6 <= wb_bus_cti; end endcase end always @(*) begin self7 <= 2'd0; case (grant) default: begin self7 <= wb_bus_bte; end endcase end assign maccore_ethphy_toggle_o = xilinxmultiregimpl01; always @(*) begin maccore_ethphy__r_status <= 1'd0; maccore_ethphy__r_status <= maccore_ethphy_r; maccore_ethphy__r_status <= xilinxmultiregimpl11; end assign core_tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl21; assign core_tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl31; assign core_pulsesynchronizer0_toggle_o = xilinxmultiregimpl41; assign core_pulsesynchronizer1_toggle_o = xilinxmultiregimpl51; assign core_rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl61; assign core_rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl71; //------------------------------------------------------------------------------ // Synchronous Logic //------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin maccore_ethphy_eth_counter <= (maccore_ethphy_eth_counter + 1'd1); if (maccore_ethphy_i) begin maccore_ethphy_toggle_i <= (~maccore_ethphy_toggle_i); end maccore_ethphy_pads_d_rx_dv <= gmii_rx_dv; maccore_ethphy_pads_d_rx_data <= gmii_rx_data; maccore_ethphy_gmii_rx_dv_d <= maccore_ethphy_pads_d_rx_dv; maccore_ethphy_gmii_rx_source_valid <= maccore_ethphy_pads_d_rx_dv; maccore_ethphy_gmii_rx_source_payload_data <= maccore_ethphy_pads_d_rx_data; maccore_ethphy_mii_rx_reset <= (~maccore_ethphy_pads_d_rx_dv); maccore_ethphy_mii_rx_converter_sink_valid <= 1'd1; maccore_ethphy_mii_rx_converter_sink_payload_data <= maccore_ethphy_pads_d_rx_data; if (maccore_ethphy_mii_rx_converter_source_ready) begin maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; end if (maccore_ethphy_mii_rx_converter_load_part) begin if (((maccore_ethphy_mii_rx_converter_demux == 1'd1) | maccore_ethphy_mii_rx_converter_sink_last)) begin maccore_ethphy_mii_rx_converter_demux <= 1'd0; maccore_ethphy_mii_rx_converter_strobe_all <= 1'd1; end else begin maccore_ethphy_mii_rx_converter_demux <= (maccore_ethphy_mii_rx_converter_demux + 1'd1); end end if ((maccore_ethphy_mii_rx_converter_source_valid & maccore_ethphy_mii_rx_converter_source_ready)) begin if ((maccore_ethphy_mii_rx_converter_sink_valid & maccore_ethphy_mii_rx_converter_sink_ready)) begin maccore_ethphy_mii_rx_converter_source_first <= maccore_ethphy_mii_rx_converter_sink_first; maccore_ethphy_mii_rx_converter_source_last <= maccore_ethphy_mii_rx_converter_sink_last; end else begin maccore_ethphy_mii_rx_converter_source_first <= 1'd0; maccore_ethphy_mii_rx_converter_source_last <= 1'd0; end end else begin if ((maccore_ethphy_mii_rx_converter_sink_valid & maccore_ethphy_mii_rx_converter_sink_ready)) begin maccore_ethphy_mii_rx_converter_source_first <= (maccore_ethphy_mii_rx_converter_sink_first | maccore_ethphy_mii_rx_converter_source_first); maccore_ethphy_mii_rx_converter_source_last <= (maccore_ethphy_mii_rx_converter_sink_last | maccore_ethphy_mii_rx_converter_source_last); end end if (maccore_ethphy_mii_rx_converter_load_part) begin case (maccore_ethphy_mii_rx_converter_demux) 1'd0: begin maccore_ethphy_mii_rx_converter_source_payload_data[3:0] <= maccore_ethphy_mii_rx_converter_sink_payload_data; end 1'd1: begin maccore_ethphy_mii_rx_converter_source_payload_data[7:4] <= maccore_ethphy_mii_rx_converter_sink_payload_data; end endcase end if (maccore_ethphy_mii_rx_converter_load_part) begin maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= (maccore_ethphy_mii_rx_converter_demux + 1'd1); end if (maccore_ethphy_mii_rx_reset) begin maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; maccore_ethphy_mii_rx_converter_demux <= 1'd0; maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; end rxdatapath_liteethmacpreamblechecker_state <= rxdatapath_liteethmacpreamblechecker_next_state; if (core_pulsesynchronizer0_i) begin core_pulsesynchronizer0_toggle_i <= (~core_pulsesynchronizer0_toggle_i); end if (core_liteethmaccrc32checker_crc_ce) begin core_liteethmaccrc32checker_crc_reg <= core_liteethmaccrc32checker_crc_crc_next; end if (core_liteethmaccrc32checker_crc_reset) begin core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; end if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin if ((core_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin core_liteethmaccrc32checker_syncfifo_produce <= 1'd0; end else begin core_liteethmaccrc32checker_syncfifo_produce <= (core_liteethmaccrc32checker_syncfifo_produce + 1'd1); end end if (core_liteethmaccrc32checker_syncfifo_do_read) begin if ((core_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin core_liteethmaccrc32checker_syncfifo_consume <= 1'd0; end else begin core_liteethmaccrc32checker_syncfifo_consume <= (core_liteethmaccrc32checker_syncfifo_consume + 1'd1); end end if (((core_liteethmaccrc32checker_syncfifo_syncfifo_we & core_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~core_liteethmaccrc32checker_syncfifo_replace))) begin if ((~core_liteethmaccrc32checker_syncfifo_do_read)) begin core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level + 1'd1); end end else begin if (core_liteethmaccrc32checker_syncfifo_do_read) begin core_liteethmaccrc32checker_syncfifo_level <= (core_liteethmaccrc32checker_syncfifo_level - 1'd1); end end if (core_liteethmaccrc32checker_fifo_reset) begin core_liteethmaccrc32checker_syncfifo_level <= 3'd0; core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; end rxdatapath_bufferizeendpoints_state <= rxdatapath_bufferizeendpoints_next_state; if (core_liteethmaccrc32checker_last_be_next_value_ce0) begin core_liteethmaccrc32checker_last_be <= core_liteethmaccrc32checker_last_be_next_value0; end if (core_liteethmaccrc32checker_crc_error1_next_value_ce1) begin core_liteethmaccrc32checker_crc_error1 <= core_liteethmaccrc32checker_crc_error1_next_value1; end if (((~core_bufferizeendpoints_pipe_valid_source_valid) | core_bufferizeendpoints_pipe_valid_source_ready)) begin core_bufferizeendpoints_pipe_valid_source_valid <= core_bufferizeendpoints_pipe_valid_sink_valid; core_bufferizeendpoints_pipe_valid_source_first <= core_bufferizeendpoints_pipe_valid_sink_first; core_bufferizeendpoints_pipe_valid_source_last <= core_bufferizeendpoints_pipe_valid_sink_last; core_bufferizeendpoints_pipe_valid_source_payload_data <= core_bufferizeendpoints_pipe_valid_sink_payload_data; core_bufferizeendpoints_pipe_valid_source_payload_last_be <= core_bufferizeendpoints_pipe_valid_sink_payload_last_be; core_bufferizeendpoints_pipe_valid_source_payload_error <= core_bufferizeendpoints_pipe_valid_sink_payload_error; end if (core_pulsesynchronizer1_i) begin core_pulsesynchronizer1_toggle_i <= (~core_pulsesynchronizer1_toggle_i); end if (core_rx_converter_converter_source_ready) begin core_rx_converter_converter_strobe_all <= 1'd0; end if (core_rx_converter_converter_load_part) begin if (((core_rx_converter_converter_demux == 2'd3) | core_rx_converter_converter_sink_last)) begin core_rx_converter_converter_demux <= 1'd0; core_rx_converter_converter_strobe_all <= 1'd1; end else begin core_rx_converter_converter_demux <= (core_rx_converter_converter_demux + 1'd1); end end if ((core_rx_converter_converter_source_valid & core_rx_converter_converter_source_ready)) begin if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin core_rx_converter_converter_source_first <= core_rx_converter_converter_sink_first; core_rx_converter_converter_source_last <= core_rx_converter_converter_sink_last; end else begin core_rx_converter_converter_source_first <= 1'd0; core_rx_converter_converter_source_last <= 1'd0; end end else begin if ((core_rx_converter_converter_sink_valid & core_rx_converter_converter_sink_ready)) begin core_rx_converter_converter_source_first <= (core_rx_converter_converter_sink_first | core_rx_converter_converter_source_first); core_rx_converter_converter_source_last <= (core_rx_converter_converter_sink_last | core_rx_converter_converter_source_last); end end if (core_rx_converter_converter_load_part) begin case (core_rx_converter_converter_demux) 1'd0: begin core_rx_converter_converter_source_payload_data[9:0] <= core_rx_converter_converter_sink_payload_data; end 1'd1: begin core_rx_converter_converter_source_payload_data[19:10] <= core_rx_converter_converter_sink_payload_data; end 2'd2: begin core_rx_converter_converter_source_payload_data[29:20] <= core_rx_converter_converter_sink_payload_data; end 2'd3: begin core_rx_converter_converter_source_payload_data[39:30] <= core_rx_converter_converter_sink_payload_data; end endcase end if (core_rx_converter_converter_load_part) begin core_rx_converter_converter_source_payload_valid_token_count <= (core_rx_converter_converter_demux + 1'd1); end core_rx_cdc_cdc_graycounter0_q_binary <= core_rx_cdc_cdc_graycounter0_q_next_binary; core_rx_cdc_cdc_graycounter0_q <= core_rx_cdc_cdc_graycounter0_q_next; if (eth_rx_rst) begin maccore_ethphy_gmii_rx_source_valid <= 1'd0; maccore_ethphy_gmii_rx_source_payload_data <= 8'd0; maccore_ethphy_gmii_rx_dv_d <= 1'd0; maccore_ethphy_mii_rx_converter_sink_valid <= 1'd0; maccore_ethphy_mii_rx_converter_sink_payload_data <= 4'd0; maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; maccore_ethphy_mii_rx_converter_demux <= 1'd0; maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; maccore_ethphy_mii_rx_reset <= 1'd0; core_liteethmaccrc32checker_crc_reg <= 32'd4294967295; core_liteethmaccrc32checker_syncfifo_level <= 3'd0; core_liteethmaccrc32checker_syncfifo_produce <= 3'd0; core_liteethmaccrc32checker_syncfifo_consume <= 3'd0; core_liteethmaccrc32checker_last_be <= 1'd0; core_liteethmaccrc32checker_crc_error1 <= 1'd0; core_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; core_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; core_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; core_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; core_rx_converter_converter_source_payload_data <= 40'd0; core_rx_converter_converter_source_payload_valid_token_count <= 3'd0; core_rx_converter_converter_demux <= 2'd0; core_rx_converter_converter_strobe_all <= 1'd0; core_rx_cdc_cdc_graycounter0_q <= 6'd0; core_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; rxdatapath_liteethmacpreamblechecker_state <= 1'd0; rxdatapath_bufferizeendpoints_state <= 2'd0; end xilinxmultiregimpl70 <= core_rx_cdc_cdc_graycounter1_q; xilinxmultiregimpl71 <= xilinxmultiregimpl70; end always @(posedge eth_tx_clk) begin if ((maccore_ethphy_mode0 == 1'd1)) begin gmii_tx_en <= maccore_ethphy_mii_tx_pads_tx_en; gmii_tx_data <= maccore_ethphy_mii_tx_pads_tx_data; end else begin gmii_tx_en <= maccore_ethphy_gmii_tx_pads_tx_en; gmii_tx_data <= maccore_ethphy_gmii_tx_pads_tx_data; end maccore_ethphy_gmii_tx_pads_tx_er <= 1'd0; maccore_ethphy_gmii_tx_pads_tx_en <= maccore_ethphy_gmii_tx_sink_valid; maccore_ethphy_gmii_tx_pads_tx_data <= maccore_ethphy_gmii_tx_sink_payload_data; maccore_ethphy_gmii_tx_sink_ready <= 1'd1; maccore_ethphy_mii_tx_pads_tx_er <= 1'd0; maccore_ethphy_mii_tx_pads_tx_en <= maccore_ethphy_mii_tx_source_source_valid; maccore_ethphy_mii_tx_pads_tx_data <= maccore_ethphy_mii_tx_source_source_payload_data; if ((maccore_ethphy_mii_tx_converter_source_valid & maccore_ethphy_mii_tx_converter_source_ready)) begin if (maccore_ethphy_mii_tx_converter_last) begin maccore_ethphy_mii_tx_converter_mux <= 1'd0; end else begin maccore_ethphy_mii_tx_converter_mux <= (maccore_ethphy_mii_tx_converter_mux + 1'd1); end end core_tx_cdc_cdc_graycounter1_q_binary <= core_tx_cdc_cdc_graycounter1_q_next_binary; core_tx_cdc_cdc_graycounter1_q <= core_tx_cdc_cdc_graycounter1_q_next; if ((core_tx_converter_converter_source_valid & core_tx_converter_converter_source_ready)) begin if (core_tx_converter_converter_last) begin core_tx_converter_converter_mux <= 1'd0; end else begin core_tx_converter_converter_mux <= (core_tx_converter_converter_mux + 1'd1); end end txdatapath_liteethmactxlastbe_state <= txdatapath_liteethmactxlastbe_next_state; txdatapath_liteethmacpaddinginserter_state <= txdatapath_liteethmacpaddinginserter_next_state; if (core_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin core_tx_padding_counter <= core_tx_padding_counter_clockdomainsrenamer0_next_value; end if (core_tx_crc_is_ongoing0) begin core_tx_crc_cnt <= 2'd3; end else begin if ((core_tx_crc_is_ongoing1 & (~core_tx_crc_cnt_done))) begin core_tx_crc_cnt <= (core_tx_crc_cnt - core_tx_crc_source_ready); end end if (core_tx_crc_ce) begin core_tx_crc_reg <= core_tx_crc_crc_next; end if (core_tx_crc_reset) begin core_tx_crc_reg <= 32'd4294967295; end txdatapath_bufferizeendpoints_state <= txdatapath_bufferizeendpoints_next_state; if (core_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin core_tx_crc_crc_packet <= core_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; end if (core_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin core_tx_crc_last_be <= core_tx_crc_last_be_clockdomainsrenamer1_next_value1; end if (((~core_tx_crc_pipe_valid_source_valid) | core_tx_crc_pipe_valid_source_ready)) begin core_tx_crc_pipe_valid_source_valid <= core_tx_crc_pipe_valid_sink_valid; core_tx_crc_pipe_valid_source_first <= core_tx_crc_pipe_valid_sink_first; core_tx_crc_pipe_valid_source_last <= core_tx_crc_pipe_valid_sink_last; core_tx_crc_pipe_valid_source_payload_data <= core_tx_crc_pipe_valid_sink_payload_data; core_tx_crc_pipe_valid_source_payload_last_be <= core_tx_crc_pipe_valid_sink_payload_last_be; core_tx_crc_pipe_valid_source_payload_error <= core_tx_crc_pipe_valid_sink_payload_error; end txdatapath_liteethmacpreambleinserter_state <= txdatapath_liteethmacpreambleinserter_next_state; if (core_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin core_tx_preamble_count <= core_tx_preamble_count_clockdomainsrenamer2_next_value; end txdatapath_liteethmacgap_state <= txdatapath_liteethmacgap_next_state; if (core_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin core_tx_gap_counter <= core_tx_gap_counter_clockdomainsrenamer3_next_value; end if (eth_tx_rst) begin maccore_ethphy_gmii_tx_sink_ready <= 1'd0; maccore_ethphy_mii_tx_converter_mux <= 1'd0; core_tx_cdc_cdc_graycounter1_q <= 6'd0; core_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; core_tx_converter_converter_mux <= 2'd0; core_tx_padding_counter <= 16'd0; core_tx_crc_reg <= 32'd4294967295; core_tx_crc_cnt <= 2'd3; core_tx_crc_pipe_valid_source_valid <= 1'd0; core_tx_crc_pipe_valid_source_payload_data <= 8'd0; core_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; core_tx_crc_pipe_valid_source_payload_error <= 1'd0; txdatapath_liteethmactxlastbe_state <= 1'd0; txdatapath_liteethmacpaddinginserter_state <= 1'd0; txdatapath_bufferizeendpoints_state <= 2'd0; txdatapath_liteethmacpreambleinserter_state <= 2'd0; txdatapath_liteethmacgap_state <= 1'd0; end xilinxmultiregimpl20 <= core_tx_cdc_cdc_graycounter0_q; xilinxmultiregimpl21 <= xilinxmultiregimpl20; end always @(posedge por_clk) begin maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin slave_sel_r <= slave_sel; if (wait_1) begin if ((~done)) begin count <= (count - 1'd1); end end else begin count <= 20'd1000000; end if ((maccore_maccore_bus_errors != 32'd4294967295)) begin if (maccore_maccore_bus_error) begin maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1); end end if (maccore_ethphy_update_mode) begin maccore_ethphy_mode0 <= maccore_ethphy_mode1; end if (maccore_ethphy_sys_counter_reset) begin maccore_ethphy_sys_counter <= 1'd0; end else begin if (maccore_ethphy_sys_counter_ce) begin maccore_ethphy_sys_counter <= (maccore_ethphy_sys_counter + 1'd1); end end maccore_ethphy_toggle_o_r <= maccore_ethphy_toggle_o; liteethphygmiimii_state <= liteethphygmiimii_next_state; if (maccore_ethphy_counter_ce) begin maccore_ethphy_counter <= (maccore_ethphy_counter + 1'd1); end core_tx_cdc_cdc_graycounter0_q_binary <= core_tx_cdc_cdc_graycounter0_q_next_binary; core_tx_cdc_cdc_graycounter0_q <= core_tx_cdc_cdc_graycounter0_q_next; if (core_pulsesynchronizer0_o) begin core_preamble_errors_status <= (core_preamble_errors_status + 1'd1); end if (core_pulsesynchronizer1_o) begin core_crc_errors_status <= (core_crc_errors_status + 1'd1); end core_pulsesynchronizer0_toggle_o_r <= core_pulsesynchronizer0_toggle_o; core_pulsesynchronizer1_toggle_o_r <= core_pulsesynchronizer1_toggle_o; core_rx_cdc_cdc_graycounter1_q_binary <= core_rx_cdc_cdc_graycounter1_q_next_binary; core_rx_cdc_cdc_graycounter1_q <= core_rx_cdc_cdc_graycounter1_q_next; if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin wishbone_interface_writer_stat_fifo_produce <= (wishbone_interface_writer_stat_fifo_produce + 1'd1); end if (wishbone_interface_writer_stat_fifo_do_read) begin wishbone_interface_writer_stat_fifo_consume <= (wishbone_interface_writer_stat_fifo_consume + 1'd1); end if (((wishbone_interface_writer_stat_fifo_syncfifo_we & wishbone_interface_writer_stat_fifo_syncfifo_writable) & (~wishbone_interface_writer_stat_fifo_replace))) begin if ((~wishbone_interface_writer_stat_fifo_do_read)) begin wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level + 1'd1); end end else begin if (wishbone_interface_writer_stat_fifo_do_read) begin wishbone_interface_writer_stat_fifo_level <= (wishbone_interface_writer_stat_fifo_level - 1'd1); end end liteethmacsramwriter_state <= liteethmacsramwriter_next_state; if (wishbone_interface_writer_length_liteethmacsramwriter_t_next_value_ce) begin wishbone_interface_writer_length <= wishbone_interface_writer_length_liteethmacsramwriter_t_next_value; end if (wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value_ce) begin wishbone_interface_writer_errors_status <= wishbone_interface_writer_errors_status_liteethmacsramwriter_f_next_value; end if (wishbone_interface_writer_slot_liteethmacsramwriter_next_value_ce) begin wishbone_interface_writer_slot <= wishbone_interface_writer_slot_liteethmacsramwriter_next_value; end if (wishbone_interface_reader_eventsourcepulse_clear) begin wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; end if (wishbone_interface_reader_eventsourcepulse_trigger) begin wishbone_interface_reader_eventsourcepulse_pending <= 1'd1; end if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin wishbone_interface_reader_cmd_fifo_produce <= (wishbone_interface_reader_cmd_fifo_produce + 1'd1); end if (wishbone_interface_reader_cmd_fifo_do_read) begin wishbone_interface_reader_cmd_fifo_consume <= (wishbone_interface_reader_cmd_fifo_consume + 1'd1); end if (((wishbone_interface_reader_cmd_fifo_syncfifo_we & wishbone_interface_reader_cmd_fifo_syncfifo_writable) & (~wishbone_interface_reader_cmd_fifo_replace))) begin if ((~wishbone_interface_reader_cmd_fifo_do_read)) begin wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level + 1'd1); end end else begin if (wishbone_interface_reader_cmd_fifo_do_read) begin wishbone_interface_reader_cmd_fifo_level <= (wishbone_interface_reader_cmd_fifo_level - 1'd1); end end liteethmacsramreader_state <= liteethmacsramreader_next_state; if (wishbone_interface_reader_length_liteethmacsramreader_next_value_ce) begin wishbone_interface_reader_length <= wishbone_interface_reader_length_liteethmacsramreader_next_value; end wishbone_interface_interface0_ack <= 1'd0; if (((wishbone_interface_interface0_cyc & wishbone_interface_interface0_stb) & ((~wishbone_interface_interface0_ack) | wishbone_interface_sram0_adr_burst))) begin wishbone_interface_interface0_ack <= 1'd1; end wishbone_interface_interface1_ack <= 1'd0; if (((wishbone_interface_interface1_cyc & wishbone_interface_interface1_stb) & ((~wishbone_interface_interface1_ack) | wishbone_interface_sram1_adr_burst))) begin wishbone_interface_interface1_ack <= 1'd1; end wishbone_interface_decoder0_slave_sel_r <= wishbone_interface_decoder0_slave_sel; wishbone_interface_interface2_ack <= 1'd0; if (((wishbone_interface_interface2_cyc & wishbone_interface_interface2_stb) & ((~wishbone_interface_interface2_ack) | wishbone_interface_sram2_adr_burst))) begin wishbone_interface_interface2_ack <= 1'd1; end wishbone_interface_interface3_ack <= 1'd0; if (((wishbone_interface_interface3_cyc & wishbone_interface_interface3_stb) & ((~wishbone_interface_interface3_ack) | wishbone_interface_sram3_adr_burst))) begin wishbone_interface_interface3_ack <= 1'd1; end wishbone_interface_decoder1_slave_sel_r <= wishbone_interface_decoder1_slave_sel; wishbone2csr_state <= wishbone2csr_next_state; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin case (interface0_bank_bus_adr[8:0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_reset0_w; end 1'd1: begin interface0_bank_bus_dat_r <= csrbank0_scratch0_w; end 2'd2: begin interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; end endcase end if (csrbank0_reset0_re) begin maccore_maccore_reset_storage <= csrbank0_reset0_r; end maccore_maccore_reset_re <= csrbank0_reset0_re; if (csrbank0_scratch0_re) begin maccore_maccore_scratch_storage <= csrbank0_scratch0_r; end maccore_maccore_scratch_re <= csrbank0_scratch0_re; maccore_maccore_bus_errors_re <= csrbank0_bus_errors_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin case (interface1_bank_bus_adr[8:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_sram_writer_slot_w; end 1'd1: begin interface1_bank_bus_dat_r <= csrbank1_sram_writer_length_w; end 2'd2: begin interface1_bank_bus_dat_r <= csrbank1_sram_writer_errors_w; end 2'd3: begin interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_status_w; end 3'd4: begin interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_pending_w; end 3'd5: begin interface1_bank_bus_dat_r <= csrbank1_sram_writer_ev_enable0_w; end 3'd6: begin interface1_bank_bus_dat_r <= wishbone_interface_reader_start_w; end 3'd7: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_ready_w; end 4'd8: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_level_w; end 4'd9: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_slot0_w; end 4'd10: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_length0_w; end 4'd11: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_status_w; end 4'd12: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_pending_w; end 4'd13: begin interface1_bank_bus_dat_r <= csrbank1_sram_reader_ev_enable0_w; end 4'd14: begin interface1_bank_bus_dat_r <= csrbank1_preamble_crc_w; end 4'd15: begin interface1_bank_bus_dat_r <= csrbank1_rx_datapath_preamble_errors_w; end 5'd16: begin interface1_bank_bus_dat_r <= csrbank1_rx_datapath_crc_errors_w; end endcase end wishbone_interface_writer_slot_re <= csrbank1_sram_writer_slot_re; wishbone_interface_writer_length_re <= csrbank1_sram_writer_length_re; wishbone_interface_writer_errors_re <= csrbank1_sram_writer_errors_re; wishbone_interface_writer_status_re <= csrbank1_sram_writer_ev_status_re; if (csrbank1_sram_writer_ev_pending_re) begin wishbone_interface_writer_pending_r <= csrbank1_sram_writer_ev_pending_r; end wishbone_interface_writer_pending_re <= csrbank1_sram_writer_ev_pending_re; if (csrbank1_sram_writer_ev_enable0_re) begin wishbone_interface_writer_enable_storage <= csrbank1_sram_writer_ev_enable0_r; end wishbone_interface_writer_enable_re <= csrbank1_sram_writer_ev_enable0_re; wishbone_interface_reader_ready_re <= csrbank1_sram_reader_ready_re; wishbone_interface_reader_level_re <= csrbank1_sram_reader_level_re; if (csrbank1_sram_reader_slot0_re) begin wishbone_interface_reader_slot_storage <= csrbank1_sram_reader_slot0_r; end wishbone_interface_reader_slot_re <= csrbank1_sram_reader_slot0_re; if (csrbank1_sram_reader_length0_re) begin wishbone_interface_reader_length_storage <= csrbank1_sram_reader_length0_r; end wishbone_interface_reader_length_re <= csrbank1_sram_reader_length0_re; wishbone_interface_reader_status_re <= csrbank1_sram_reader_ev_status_re; if (csrbank1_sram_reader_ev_pending_re) begin wishbone_interface_reader_pending_r <= csrbank1_sram_reader_ev_pending_r; end wishbone_interface_reader_pending_re <= csrbank1_sram_reader_ev_pending_re; if (csrbank1_sram_reader_ev_enable0_re) begin wishbone_interface_reader_enable_storage <= csrbank1_sram_reader_ev_enable0_r; end wishbone_interface_reader_enable_re <= csrbank1_sram_reader_ev_enable0_re; core_re <= csrbank1_preamble_crc_re; core_preamble_errors_re <= csrbank1_rx_datapath_preamble_errors_re; core_crc_errors_re <= csrbank1_rx_datapath_crc_errors_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin case (interface2_bank_bus_adr[8:0]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_mode_detection_mode_w; end 1'd1: begin interface2_bank_bus_dat_r <= csrbank2_crg_reset0_w; end 2'd2: begin interface2_bank_bus_dat_r <= csrbank2_mdio_w0_w; end 2'd3: begin interface2_bank_bus_dat_r <= csrbank2_mdio_r_w; end endcase end maccore_ethphy_mode_re <= csrbank2_mode_detection_mode_re; if (csrbank2_crg_reset0_re) begin maccore_ethphy_reset_storage <= csrbank2_crg_reset0_r; end maccore_ethphy_reset_re <= csrbank2_crg_reset0_re; if (csrbank2_mdio_w0_re) begin maccore_ethphy__w_storage <= csrbank2_mdio_w0_r; end maccore_ethphy__w_re <= csrbank2_mdio_w0_re; maccore_ethphy__r_re <= csrbank2_mdio_r_re; if (sys_rst) begin maccore_maccore_reset_storage <= 2'd0; maccore_maccore_reset_re <= 1'd0; maccore_maccore_scratch_storage <= 32'd305419896; maccore_maccore_scratch_re <= 1'd0; maccore_maccore_bus_errors_re <= 1'd0; maccore_maccore_bus_errors <= 32'd0; maccore_ethphy_mode0 <= 1'd0; maccore_ethphy_mode_re <= 1'd0; maccore_ethphy_reset_storage <= 1'd0; maccore_ethphy_reset_re <= 1'd0; maccore_ethphy_counter <= 9'd0; maccore_ethphy__w_storage <= 3'd0; maccore_ethphy__w_re <= 1'd0; maccore_ethphy__r_re <= 1'd0; core_re <= 1'd0; core_tx_cdc_cdc_graycounter0_q <= 6'd0; core_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; core_preamble_errors_status <= 32'd0; core_preamble_errors_re <= 1'd0; core_crc_errors_status <= 32'd0; core_crc_errors_re <= 1'd0; core_rx_cdc_cdc_graycounter1_q <= 6'd0; core_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; wishbone_interface_writer_slot_re <= 1'd0; wishbone_interface_writer_length_re <= 1'd0; wishbone_interface_writer_errors_status <= 32'd0; wishbone_interface_writer_errors_re <= 1'd0; wishbone_interface_writer_status_re <= 1'd0; wishbone_interface_writer_pending_re <= 1'd0; wishbone_interface_writer_pending_r <= 1'd0; wishbone_interface_writer_enable_storage <= 1'd0; wishbone_interface_writer_enable_re <= 1'd0; wishbone_interface_writer_slot <= 1'd0; wishbone_interface_writer_length <= 11'd0; wishbone_interface_writer_stat_fifo_level <= 2'd0; wishbone_interface_writer_stat_fifo_produce <= 1'd0; wishbone_interface_writer_stat_fifo_consume <= 1'd0; wishbone_interface_reader_ready_re <= 1'd0; wishbone_interface_reader_level_re <= 1'd0; wishbone_interface_reader_slot_re <= 1'd0; wishbone_interface_reader_length_re <= 1'd0; wishbone_interface_reader_eventsourcepulse_pending <= 1'd0; wishbone_interface_reader_status_re <= 1'd0; wishbone_interface_reader_pending_re <= 1'd0; wishbone_interface_reader_pending_r <= 1'd0; wishbone_interface_reader_enable_storage <= 1'd0; wishbone_interface_reader_enable_re <= 1'd0; wishbone_interface_reader_length <= 11'd0; wishbone_interface_reader_cmd_fifo_level <= 2'd0; wishbone_interface_reader_cmd_fifo_produce <= 1'd0; wishbone_interface_reader_cmd_fifo_consume <= 1'd0; wishbone_interface_interface0_ack <= 1'd0; wishbone_interface_interface1_ack <= 1'd0; wishbone_interface_decoder0_slave_sel_r <= 2'd0; wishbone_interface_interface2_ack <= 1'd0; wishbone_interface_interface3_ack <= 1'd0; wishbone_interface_decoder1_slave_sel_r <= 2'd0; slave_sel_r <= 3'd0; count <= 20'd1000000; liteethphygmiimii_state <= 2'd0; liteethmacsramwriter_state <= 3'd0; liteethmacsramreader_state <= 2'd0; wishbone2csr_state <= 1'd0; end xilinxmultiregimpl00 <= maccore_ethphy_toggle_i; xilinxmultiregimpl01 <= xilinxmultiregimpl00; xilinxmultiregimpl10 <= maccore_ethphy_data_r; xilinxmultiregimpl11 <= xilinxmultiregimpl10; xilinxmultiregimpl30 <= core_tx_cdc_cdc_graycounter1_q; xilinxmultiregimpl31 <= xilinxmultiregimpl30; xilinxmultiregimpl40 <= core_pulsesynchronizer0_toggle_i; xilinxmultiregimpl41 <= xilinxmultiregimpl40; xilinxmultiregimpl50 <= core_pulsesynchronizer1_toggle_i; xilinxmultiregimpl51 <= xilinxmultiregimpl50; xilinxmultiregimpl60 <= core_rx_cdc_cdc_graycounter0_q; xilinxmultiregimpl61 <= xilinxmultiregimpl60; end //------------------------------------------------------------------------------ // Specialized Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Instance BUFG of BUFG Module. //------------------------------------------------------------------------------ BUFG BUFG( // Inputs. .I (gmii_clocks_rx), // Outputs. .O (eth_rx_clk) ); //------------------------------------------------------------------------------ // Instance BUFG_1 of BUFG Module. //------------------------------------------------------------------------------ BUFG BUFG_1( // Inputs. .I (maccore_ethphy_eth_tx_clk), // Outputs. .O (eth_tx_clk) ); assign gmii_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz; assign maccore_ethphy_data_r = gmii_mdio; //------------------------------------------------------------------------------ // Memory storage: 32-words x 42-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 // Port 1 | Read: Sync | Write: ---- | reg [41:0] storage[0:31]; reg [41:0] storage_dat0; reg [41:0] storage_dat1; always @(posedge sys_clk) begin if (core_tx_cdc_cdc_wrport_we) storage[core_tx_cdc_cdc_wrport_adr] <= core_tx_cdc_cdc_wrport_dat_w; storage_dat0 <= storage[core_tx_cdc_cdc_wrport_adr]; end always @(posedge eth_tx_clk) begin storage_dat1 <= storage[core_tx_cdc_cdc_rdport_adr]; end assign core_tx_cdc_cdc_wrport_dat_r = storage_dat0; assign core_tx_cdc_cdc_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ // Memory storage_1: 5-words x 12-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 // Port 1 | Read: Async | Write: ---- | reg [11:0] storage_1[0:4]; reg [11:0] storage_1_dat0; always @(posedge eth_rx_clk) begin if (core_liteethmaccrc32checker_syncfifo_wrport_we) storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr] <= core_liteethmaccrc32checker_syncfifo_wrport_dat_w; storage_1_dat0 <= storage_1[core_liteethmaccrc32checker_syncfifo_wrport_adr]; end always @(posedge eth_rx_clk) begin end assign core_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; assign core_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[core_liteethmaccrc32checker_syncfifo_rdport_adr]; //------------------------------------------------------------------------------ // Memory storage_2: 32-words x 42-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 // Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; reg [41:0] storage_2_dat0; reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin if (core_rx_cdc_cdc_wrport_we) storage_2[core_rx_cdc_cdc_wrport_adr] <= core_rx_cdc_cdc_wrport_dat_w; storage_2_dat0 <= storage_2[core_rx_cdc_cdc_wrport_adr]; end always @(posedge sys_clk) begin storage_2_dat1 <= storage_2[core_rx_cdc_cdc_rdport_adr]; end assign core_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; assign core_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; //------------------------------------------------------------------------------ // Memory storage_3: 2-words x 14-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 // Port 1 | Read: Async | Write: ---- | reg [13:0] storage_3[0:1]; reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin if (wishbone_interface_writer_stat_fifo_wrport_we) storage_3[wishbone_interface_writer_stat_fifo_wrport_adr] <= wishbone_interface_writer_stat_fifo_wrport_dat_w; storage_3_dat0 <= storage_3[wishbone_interface_writer_stat_fifo_wrport_adr]; end always @(posedge sys_clk) begin end assign wishbone_interface_writer_stat_fifo_wrport_dat_r = storage_3_dat0; assign wishbone_interface_writer_stat_fifo_rdport_dat_r = storage_3[wishbone_interface_writer_stat_fifo_rdport_adr]; //------------------------------------------------------------------------------ // Memory mem: 383-words x 32-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 // Port 1 | Read: Sync | Write: ---- | reg [31:0] mem[0:382]; reg [8:0] mem_adr0; reg [31:0] mem_dat1; always @(posedge sys_clk) begin if (wishbone_interface_writer_memory0_we) mem[wishbone_interface_writer_memory0_adr] <= wishbone_interface_writer_memory0_dat_w; mem_adr0 <= wishbone_interface_writer_memory0_adr; end always @(posedge sys_clk) begin mem_dat1 <= mem[wishbone_interface_sram0_adr]; end assign wishbone_interface_writer_memory0_dat_r = mem[mem_adr0]; assign wishbone_interface_sram0_dat_r = mem_dat1; //------------------------------------------------------------------------------ // Memory mem_1: 383-words x 32-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 // Port 1 | Read: Sync | Write: ---- | reg [31:0] mem_1[0:382]; reg [8:0] mem_1_adr0; reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin if (wishbone_interface_writer_memory1_we) mem_1[wishbone_interface_writer_memory1_adr] <= wishbone_interface_writer_memory1_dat_w; mem_1_adr0 <= wishbone_interface_writer_memory1_adr; end always @(posedge sys_clk) begin mem_1_dat1 <= mem_1[wishbone_interface_sram1_adr]; end assign wishbone_interface_writer_memory1_dat_r = mem_1[mem_1_adr0]; assign wishbone_interface_sram1_dat_r = mem_1_dat1; //------------------------------------------------------------------------------ // Memory storage_4: 2-words x 14-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 // Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin if (wishbone_interface_reader_cmd_fifo_wrport_we) storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr] <= wishbone_interface_reader_cmd_fifo_wrport_dat_w; storage_4_dat0 <= storage_4[wishbone_interface_reader_cmd_fifo_wrport_adr]; end always @(posedge sys_clk) begin end assign wishbone_interface_reader_cmd_fifo_wrport_dat_r = storage_4_dat0; assign wishbone_interface_reader_cmd_fifo_rdport_dat_r = storage_4[wishbone_interface_reader_cmd_fifo_rdport_adr]; //------------------------------------------------------------------------------ // Memory mem_2: 383-words x 32-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: ---- | // Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 reg [31:0] mem_2[0:382]; reg [31:0] mem_2_dat0; reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin if (wishbone_interface_reader_memory0_re) mem_2_dat0 <= mem_2[wishbone_interface_reader_memory0_adr]; end always @(posedge sys_clk) begin if (wishbone_interface_sram2_we[0]) mem_2[wishbone_interface_sram2_adr][7:0] <= wishbone_interface_sram2_dat_w[7:0]; if (wishbone_interface_sram2_we[1]) mem_2[wishbone_interface_sram2_adr][15:8] <= wishbone_interface_sram2_dat_w[15:8]; if (wishbone_interface_sram2_we[2]) mem_2[wishbone_interface_sram2_adr][23:16] <= wishbone_interface_sram2_dat_w[23:16]; if (wishbone_interface_sram2_we[3]) mem_2[wishbone_interface_sram2_adr][31:24] <= wishbone_interface_sram2_dat_w[31:24]; mem_2_adr1 <= wishbone_interface_sram2_adr; end assign wishbone_interface_reader_memory0_dat_r = mem_2_dat0; assign wishbone_interface_sram2_dat_r = mem_2[mem_2_adr1]; //------------------------------------------------------------------------------ // Memory mem_3: 383-words x 32-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: ---- | // Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 reg [31:0] mem_3[0:382]; reg [31:0] mem_3_dat0; reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin if (wishbone_interface_reader_memory1_re) mem_3_dat0 <= mem_3[wishbone_interface_reader_memory1_adr]; end always @(posedge sys_clk) begin if (wishbone_interface_sram3_we[0]) mem_3[wishbone_interface_sram3_adr][7:0] <= wishbone_interface_sram3_dat_w[7:0]; if (wishbone_interface_sram3_we[1]) mem_3[wishbone_interface_sram3_adr][15:8] <= wishbone_interface_sram3_dat_w[15:8]; if (wishbone_interface_sram3_we[2]) mem_3[wishbone_interface_sram3_adr][23:16] <= wishbone_interface_sram3_dat_w[23:16]; if (wishbone_interface_sram3_we[3]) mem_3[wishbone_interface_sram3_adr][31:24] <= wishbone_interface_sram3_dat_w[31:24]; mem_3_adr1 <= wishbone_interface_sram3_adr; end assign wishbone_interface_reader_memory1_dat_r = mem_3_dat0; assign wishbone_interface_sram3_dat_r = mem_3[mem_3_adr1]; //------------------------------------------------------------------------------ // Instance ODDR of ODDR Module. //------------------------------------------------------------------------------ ODDR #( // Parameters. .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR ( // Inputs. .C (eth_tx_clk), .CE (1'd1), .D1 (1'd1), .D2 ((maccore_ethphy_mode0 == 1'd1)), .R (1'd0), .S (1'd0), // Outputs. .Q (gmii_clocks_gtx) ); (* ars_ff1 = "true", async_reg = "true" *) //------------------------------------------------------------------------------ // Instance FDPE of FDPE Module. //------------------------------------------------------------------------------ FDPE #( // Parameters. .INIT (1'd1) ) FDPE ( // Inputs. .C (eth_tx_clk), .CE (1'd1), .D (1'd0), .PRE (maccore_ethphy_reset0), // Outputs. .Q (rst_meta0) ); (* ars_ff2 = "true", async_reg = "true" *) //------------------------------------------------------------------------------ // Instance FDPE_1 of FDPE Module. //------------------------------------------------------------------------------ FDPE #( // Parameters. .INIT (1'd1) ) FDPE_1 ( // Inputs. .C (eth_tx_clk), .CE (1'd1), .D (rst_meta0), .PRE (maccore_ethphy_reset0), // Outputs. .Q (eth_tx_rst) ); (* ars_ff1 = "true", async_reg = "true" *) //------------------------------------------------------------------------------ // Instance FDPE_2 of FDPE Module. //------------------------------------------------------------------------------ FDPE #( // Parameters. .INIT (1'd1) ) FDPE_2 ( // Inputs. .C (eth_rx_clk), .CE (1'd1), .D (1'd0), .PRE (maccore_ethphy_reset0), // Outputs. .Q (rst_meta1) ); (* ars_ff2 = "true", async_reg = "true" *) //------------------------------------------------------------------------------ // Instance FDPE_3 of FDPE Module. //------------------------------------------------------------------------------ FDPE #( // Parameters. .INIT (1'd1) ) FDPE_3 ( // Inputs. .C (eth_rx_clk), .CE (1'd1), .D (rst_meta1), .PRE (maccore_ethphy_reset0), // Outputs. .Q (eth_rx_rst) ); endmodule // ----------------------------------------------------------------------------- // Auto-Generated by LiteX on 2025-02-15 16:17:45. //------------------------------------------------------------------------------