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104 lines
2.5 KiB
VHDL
104 lines
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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entity zero_counter is
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port (
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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is_32bit : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity zero_counter;
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architecture behaviour of zero_counter is
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signal l32, r32 : std_ulogic;
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signal v32 : std_ulogic_vector(31 downto 0);
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signal v16 : std_ulogic_vector(15 downto 0);
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signal v8 : std_ulogic_vector(7 downto 0);
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signal v4 : std_ulogic_vector(3 downto 0);
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signal sel : std_ulogic_vector(5 downto 0);
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begin
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zerocounter0: process(all)
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begin
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l32 <= or (rs(63 downto 32));
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r32 <= or (rs(31 downto 0));
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if (l32 = '0' or is_32bit = '1') and r32 = '0' then
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-- operand is zero, return 32 for 32-bit, else 64
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result <= x"00000000000000" & '0' & not is_32bit & is_32bit & "00000";
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else
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if count_right = '0' then
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sel(5) <= l32 and (not is_32bit);
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else
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sel(5) <= (not r32) and (not is_32bit);
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end if;
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if sel(5) = '1' then
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v32 <= rs(63 downto 32);
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else
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v32 <= rs(31 downto 0);
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end if;
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if count_right = '0' then
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sel(4) <= or (v32(31 downto 16));
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else
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sel(4) <= not (or (v32(15 downto 0)));
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end if;
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if sel(4) = '1' then
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v16 <= v32(31 downto 16);
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else
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v16 <= v32(15 downto 0);
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end if;
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if count_right = '0' then
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sel(3) <= or (v16(15 downto 8));
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else
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sel(3) <= not (or (v16(7 downto 0)));
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end if;
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if sel(3) = '1' then
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v8 <= v16(15 downto 8);
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else
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v8 <= v16(7 downto 0);
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end if;
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if count_right = '0' then
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sel(2) <= or (v8(7 downto 4));
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else
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sel(2) <= not (or (v8(3 downto 0)));
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end if;
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if sel(2) = '1' then
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v4 <= v8(7 downto 4);
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else
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v4 <= v8(3 downto 0);
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end if;
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if count_right = '0' then
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if v4(3) = '1' then
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sel(1 downto 0) <= "11";
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elsif v4(2) = '1' then
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sel(1 downto 0) <= "10";
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elsif v4(1) = '1' then
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sel(1 downto 0) <= "01";
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else
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sel(1 downto 0) <= "00";
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end if;
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result <= x"00000000000000" & "00" & (not sel(5) and not is_32bit) & not sel(4 downto 0);
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else
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if v4(0) = '1' then
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sel(1 downto 0) <= "00";
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elsif v4(1) = '1' then
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sel(1 downto 0) <= "01";
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elsif v4(2) = '1' then
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sel(1 downto 0) <= "10";
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else
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sel(1 downto 0) <= "11";
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end if;
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result <= x"00000000000000" & "00" & sel;
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end if;
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end if;
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end process;
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end behaviour;
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