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125 lines
3.9 KiB
VHDL
125 lines
3.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.ppc_fx_insns.all;
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entity logical is
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port (
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rs : in std_ulogic_vector(63 downto 0);
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rb : in std_ulogic_vector(63 downto 0);
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op : in insn_type_t;
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invert_in : in std_ulogic;
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invert_out : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0);
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datalen : in std_logic_vector(3 downto 0)
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);
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end entity logical;
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architecture behaviour of logical is
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subtype twobit is unsigned(1 downto 0);
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type twobit32 is array(0 to 31) of twobit;
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signal pc2 : twobit32;
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subtype threebit is unsigned(2 downto 0);
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type threebit16 is array(0 to 15) of threebit;
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signal pc4 : threebit16;
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subtype fourbit is unsigned(3 downto 0);
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type fourbit8 is array(0 to 7) of fourbit;
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signal pc8 : fourbit8;
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subtype sixbit is unsigned(5 downto 0);
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type sixbit2 is array(0 to 1) of sixbit;
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signal pc32 : sixbit2;
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signal par0, par1 : std_ulogic;
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signal popcnt : std_ulogic_vector(63 downto 0);
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signal parity : std_ulogic_vector(63 downto 0);
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begin
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logical_0: process(all)
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variable rb_adj, tmp : std_ulogic_vector(63 downto 0);
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variable negative : std_ulogic;
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begin
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-- population counts
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for i in 0 to 31 loop
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pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
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end loop;
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for i in 0 to 15 loop
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pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
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end loop;
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for i in 0 to 7 loop
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pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
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end loop;
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for i in 0 to 1 loop
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pc32(i) <= ("00" & pc8(i * 4)) + ("00" & pc8(i * 4 + 1)) +
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("00" & pc8(i * 4 + 2)) + ("00" & pc8(i * 4 + 3));
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end loop;
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popcnt <= (others => '0');
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if datalen(3 downto 2) = "00" then
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-- popcntb
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for i in 0 to 7 loop
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popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8(i));
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end loop;
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elsif datalen(3) = '0' then
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-- popcntw
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for i in 0 to 1 loop
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popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
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end loop;
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else
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popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
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end if;
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-- parity calculations
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par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
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par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);
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parity <= (others => '0');
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if datalen(3) = '1' then
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parity(0) <= par0 xor par1;
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else
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parity(0) <= par0;
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parity(32) <= par1;
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end if;
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rb_adj := rb;
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if invert_in = '1' then
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rb_adj := not rb;
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end if;
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case op is
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when OP_AND =>
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tmp := rs and rb_adj;
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when OP_OR =>
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tmp := rs or rb_adj;
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when OP_XOR =>
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tmp := rs xor rb_adj;
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when OP_POPCNT =>
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tmp := popcnt;
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when OP_PRTY =>
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tmp := parity;
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when OP_CMPB =>
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tmp := ppc_cmpb(rs, rb);
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when others =>
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-- EXTS
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-- note datalen is a 1-hot encoding
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negative := (datalen(0) and rs(7)) or
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(datalen(1) and rs(15)) or
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(datalen(2) and rs(31));
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tmp := (others => negative);
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if datalen(2) = '1' then
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tmp(31 downto 16) := rs(31 downto 16);
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end if;
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if datalen(2) = '1' or datalen(1) = '1' then
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tmp(15 downto 8) := rs(15 downto 8);
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end if;
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tmp(7 downto 0) := rs(7 downto 0);
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end case;
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if invert_out = '1' then
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tmp := not tmp;
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end if;
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result <= tmp;
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end process;
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end behaviour;
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