From 6ae4978f0cf65222dcd5534617cb6c11ca237bbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Mon, 16 May 2022 17:52:30 +0200 Subject: [PATCH] pfv: expose CR as a flat 32-bit value. --- cores/microwatt/_wrapper.py | 43 ++---------------- cores/microwatt/microwatt_top.vhdl | 72 ++++-------------------------- power_fv/checks/cr.py | 44 +++++++++++------- power_fv/pfv.py | 12 ++--- 4 files changed, 45 insertions(+), 126 deletions(-) diff --git a/cores/microwatt/_wrapper.py b/cores/microwatt/_wrapper.py index 32098e5..2277770 100644 --- a/cores/microwatt/_wrapper.py +++ b/cores/microwatt/_wrapper.py @@ -121,45 +121,10 @@ class MicrowattWrapper(Elaboratable): ("o", "pfv_rt_w_stb", self.pfv.rt.w_stb), ("o", "pfv_rt_w_data", self.pfv.rt.w_data), - ("o", "pfv_cr0_r_stb", self.pfv.cr0.r_stb), - ("o", "pfv_cr0_r_data", self.pfv.cr0.r_data), - ("o", "pfv_cr0_w_stb", self.pfv.cr0.w_stb), - ("o", "pfv_cr0_w_data", self.pfv.cr0.w_data), - - ("o", "pfv_cr1_r_stb", self.pfv.cr1.r_stb), - ("o", "pfv_cr1_r_data", self.pfv.cr1.r_data), - ("o", "pfv_cr1_w_stb", self.pfv.cr1.w_stb), - ("o", "pfv_cr1_w_data", self.pfv.cr1.w_data), - - ("o", "pfv_cr2_r_stb", self.pfv.cr2.r_stb), - ("o", "pfv_cr2_r_data", self.pfv.cr2.r_data), - ("o", "pfv_cr2_w_stb", self.pfv.cr2.w_stb), - ("o", "pfv_cr2_w_data", self.pfv.cr2.w_data), - - ("o", "pfv_cr3_r_stb", self.pfv.cr3.r_stb), - ("o", "pfv_cr3_r_data", self.pfv.cr3.r_data), - ("o", "pfv_cr3_w_stb", self.pfv.cr3.w_stb), - ("o", "pfv_cr3_w_data", self.pfv.cr3.w_data), - - ("o", "pfv_cr4_r_stb", self.pfv.cr4.r_stb), - ("o", "pfv_cr4_r_data", self.pfv.cr4.r_data), - ("o", "pfv_cr4_w_stb", self.pfv.cr4.w_stb), - ("o", "pfv_cr4_w_data", self.pfv.cr4.w_data), - - ("o", "pfv_cr5_r_stb", self.pfv.cr5.r_stb), - ("o", "pfv_cr5_r_data", self.pfv.cr5.r_data), - ("o", "pfv_cr5_w_stb", self.pfv.cr5.w_stb), - ("o", "pfv_cr5_w_data", self.pfv.cr5.w_data), - - ("o", "pfv_cr6_r_stb", self.pfv.cr6.r_stb), - ("o", "pfv_cr6_r_data", self.pfv.cr6.r_data), - ("o", "pfv_cr6_w_stb", self.pfv.cr6.w_stb), - ("o", "pfv_cr6_w_data", self.pfv.cr6.w_data), - - ("o", "pfv_cr7_r_stb", self.pfv.cr7.r_stb), - ("o", "pfv_cr7_r_data", self.pfv.cr7.r_data), - ("o", "pfv_cr7_w_stb", self.pfv.cr7.w_stb), - ("o", "pfv_cr7_w_data", self.pfv.cr7.w_data), + ("o", "pfv_cr_r_stb", self.pfv.cr.r_stb), + ("o", "pfv_cr_r_data", self.pfv.cr.r_data), + ("o", "pfv_cr_w_stb", self.pfv.cr.w_stb), + ("o", "pfv_cr_w_data", self.pfv.cr.w_data), ("o", "pfv_lr_r_stb", self.pfv.lr.r_stb), ("o", "pfv_lr_r_data", self.pfv.lr.r_data), diff --git a/cores/microwatt/microwatt_top.vhdl b/cores/microwatt/microwatt_top.vhdl index db9b9a7..fad926f 100644 --- a/cores/microwatt/microwatt_top.vhdl +++ b/cores/microwatt/microwatt_top.vhdl @@ -59,38 +59,10 @@ entity toplevel is pfv_rt_w_stb : out std_ulogic; pfv_rt_w_data : out std_ulogic_vector(63 downto 0); - pfv_cr0_r_stb : out std_ulogic; - pfv_cr0_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr0_w_stb : out std_ulogic; - pfv_cr0_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr1_r_stb : out std_ulogic; - pfv_cr1_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr1_w_stb : out std_ulogic; - pfv_cr1_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr2_r_stb : out std_ulogic; - pfv_cr2_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr2_w_stb : out std_ulogic; - pfv_cr2_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr3_r_stb : out std_ulogic; - pfv_cr3_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr3_w_stb : out std_ulogic; - pfv_cr3_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr4_r_stb : out std_ulogic; - pfv_cr4_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr4_w_stb : out std_ulogic; - pfv_cr4_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr5_r_stb : out std_ulogic; - pfv_cr5_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr5_w_stb : out std_ulogic; - pfv_cr5_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr6_r_stb : out std_ulogic; - pfv_cr6_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr6_w_stb : out std_ulogic; - pfv_cr6_w_data : out std_ulogic_vector(3 downto 0); - pfv_cr7_r_stb : out std_ulogic; - pfv_cr7_r_data : out std_ulogic_vector(3 downto 0); - pfv_cr7_w_stb : out std_ulogic; - pfv_cr7_w_data : out std_ulogic_vector(3 downto 0); + pfv_cr_r_stb : out std_ulogic_vector( 7 downto 0); + pfv_cr_r_data : out std_ulogic_vector(31 downto 0); + pfv_cr_w_stb : out std_ulogic_vector( 7 downto 0); + pfv_cr_w_data : out std_ulogic_vector(31 downto 0); pfv_lr_r_stb : out std_ulogic; pfv_lr_r_data : out std_ulogic_vector(63 downto 0); @@ -179,38 +151,10 @@ begin pfv_rt_w_stb <= pfv.rt.w_stb; pfv_rt_w_data <= pfv.rt.w_data; - pfv_cr0_r_stb <= pfv.cr(0).r_stb; - pfv_cr0_r_data <= pfv.cr(0).r_data; - pfv_cr0_w_stb <= pfv.cr(0).w_stb; - pfv_cr0_w_data <= pfv.cr(0).w_data; - pfv_cr1_r_stb <= pfv.cr(1).r_stb; - pfv_cr1_r_data <= pfv.cr(1).r_data; - pfv_cr1_w_stb <= pfv.cr(1).w_stb; - pfv_cr1_w_data <= pfv.cr(1).w_data; - pfv_cr2_r_stb <= pfv.cr(2).r_stb; - pfv_cr2_r_data <= pfv.cr(2).r_data; - pfv_cr2_w_stb <= pfv.cr(2).w_stb; - pfv_cr2_w_data <= pfv.cr(2).w_data; - pfv_cr3_r_stb <= pfv.cr(3).r_stb; - pfv_cr3_r_data <= pfv.cr(3).r_data; - pfv_cr3_w_stb <= pfv.cr(3).w_stb; - pfv_cr3_w_data <= pfv.cr(3).w_data; - pfv_cr4_r_stb <= pfv.cr(4).r_stb; - pfv_cr4_r_data <= pfv.cr(4).r_data; - pfv_cr4_w_stb <= pfv.cr(4).w_stb; - pfv_cr4_w_data <= pfv.cr(4).w_data; - pfv_cr5_r_stb <= pfv.cr(5).r_stb; - pfv_cr5_r_data <= pfv.cr(5).r_data; - pfv_cr5_w_stb <= pfv.cr(5).w_stb; - pfv_cr5_w_data <= pfv.cr(5).w_data; - pfv_cr6_r_stb <= pfv.cr(6).r_stb; - pfv_cr6_r_data <= pfv.cr(6).r_data; - pfv_cr6_w_stb <= pfv.cr(6).w_stb; - pfv_cr6_w_data <= pfv.cr(6).w_data; - pfv_cr7_r_stb <= pfv.cr(7).r_stb; - pfv_cr7_r_data <= pfv.cr(7).r_data; - pfv_cr7_w_stb <= pfv.cr(7).w_stb; - pfv_cr7_w_data <= pfv.cr(7).w_data; + pfv_cr_r_stb <= pfv.cr.r_stb; + pfv_cr_r_data <= pfv.cr.r_data; + pfv_cr_w_stb <= pfv.cr.w_stb; + pfv_cr_w_data <= pfv.cr.w_data; pfv_lr_r_stb <= pfv.lr.r_stb; pfv_lr_r_data <= pfv.lr.r_data; diff --git a/power_fv/checks/cr.py b/power_fv/checks/cr.py index b9312ac..70ae907 100644 --- a/power_fv/checks/cr.py +++ b/power_fv/checks/cr.py @@ -22,36 +22,46 @@ class CRCheck(Elaboratable): spec_order = AnyConst(self.pfv.order.width) - cr = Array(Record([ - ("written", 1), - ("shadow", 4), - ], name=f"cr{i}") for i in range(8)) + cr_map = Array( + Record([ + ("pfv", [ + ("r_stb", 1), + ("r_data", 4), + ("w_stb", 1), + ("w_data", 4), + ]), + ("written", 1), + ("shadow", 4), + ], name=f"cr_{i}") for i in range(8) + ) cr_written_any = 0 - with m.If(self.pfv.stb & (self.pfv.order <= spec_order)): - for i, cr_field in enumerate(cr): - pfv_cr_field = getattr(self.pfv, f"cr{i}") + for i, cr_field in enumerate(cr_map): + m.d.comb += [ + cr_field.pfv.r_stb .eq(self.pfv.cr.r_stb[i]), + cr_field.pfv.r_data.eq(self.pfv.cr.r_data.word_select(i, 4)), + cr_field.pfv.w_stb .eq(self.pfv.cr.w_stb[i]), + cr_field.pfv.w_data.eq(self.pfv.cr.w_data.word_select(i, 4)), + ] + cr_written_any |= cr_field.written - with m.If(pfv_cr_field.w_stb): + with m.If(self.pfv.stb & (self.pfv.order <= spec_order)): + for cr_field in cr_map: + with m.If(cr_field.pfv.w_stb): m.d.sync += [ cr_field.written.eq(1), - cr_field.shadow .eq(pfv_cr_field.w_data), + cr_field.shadow .eq(cr_field.pfv.w_data), ] - cr_written_any |= cr_field.written - with m.If(self.post): m.d.sync += [ Assume(Past(self.pfv.stb)), Assume(Past(self.pfv.order) == spec_order), Assume(cr_written_any), ] - - for i, cr_field in enumerate(cr): - pfv_cr_field = getattr(self.pfv, f"cr{i}") - - with m.If(Past(pfv_cr_field.r_stb)): - m.d.sync += Assert(Past(pfv_cr_field.r_data) == Past(cr_field.shadow)) + for cr_field in cr_map: + with m.If(Past(cr_field.pfv.r_stb)): + m.d.sync += Assert(Past(cr_field.pfv.r_data) == Past(cr_field.shadow)) return m diff --git a/power_fv/pfv.py b/power_fv/pfv.py index 92c7a1d..466f273 100644 --- a/power_fv/pfv.py +++ b/power_fv/pfv.py @@ -58,12 +58,12 @@ class Interface(Record): # CR layout += [ - (f"cr{i}", [ - ("r_stb", 1), - ("r_data", 4), - ("w_stb", 1), - ("w_data", 4), - ]) for i in range(8) + ("cr", [ + ("r_stb", 8), + ("r_data", 32), + ("w_stb", 8), + ("w_data", 32), + ]), ] # SPRs