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445 lines
11 KiB
Python
445 lines
11 KiB
Python
2 years ago
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#!/usr/bin/python3
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# pyverilator
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# fixed internal sig parsing (cdata/wdata)
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# 1. this should be based on init setting AND should be done even w/o trace on!!!
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# in add_to_vcd_trace(self), time is bumped +5
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# 2. should count cycs
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# 3. add parm so clock can be set but NOT eval (for multiclock, only fastest evals)
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# 4. how to access mem[][]??
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# 5. not adding vectors to gtk - cuz 0:n?
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import os, sys
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import datetime
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from optparse import OptionParser
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from optparse import OptionGroup
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import random
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from random import randint
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from pysutils import *
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user = os.environ['USER']
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binPath = os.path.dirname(os.path.realpath(__file__))
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localPV = True
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if localPV:
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import os, sys
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sys.path.append(os.path.join(binPath, 'pyverilator'))
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import pyverilator
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####################################################################
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# Defaults
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rtl = ['src']
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model = 'sdr'
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stopOnFail = True
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verbose = False
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vcd = False
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seed = randint(1, int('8675309', 16))
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runCycs = 100
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#rangesRd = [(0,63), (0,63), (0,63), (0,63)]
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rangesRd = [(0,7), (0,7), (0,7), (0,7)]
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#rangesWr = [(0,63), (0,63)]
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rangesWr = [(0,7), (0,7)]
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####################################################################
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# Process command line
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usage = "Usage: %prog [options]"
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parser = OptionParser(usage)
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parser.add_option('-m', '--model', dest='model', help=f'sdr or ddr')
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parser.add_option('-s', '--seed', dest='seed', help=f'initialize seed to n')
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parser.add_option('-c', '--cycles', dest='runCycs', help=f'cycles to run, default={runCycs}')
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parser.add_option('-t', '--trace', dest='trace', action='store_true', help=f'create wave file')
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parser.add_option('-f', '--stopfail', dest='stopOnFail', action='store_true', help=f'stop on first fail')
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parser.add_option('-v', '--verbose', dest='verbose', action='store_true', help=f'noisy output')
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options, args = parser.parse_args()
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if options.model is not None:
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model = options.model
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if options.seed is not None:
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seed = int(options.seed)
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if options.runCycs is not None:
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runCycs = int(options.runCycs)
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if options.trace is not None:
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vcd = True
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if options.stopOnFail is not None:
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stopOnFail = True
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if options.verbose is not None:
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verbose = True
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####################################################################
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# Init
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sdr = False
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ddr = False
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ddr1x = False
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if model == 'sdr':
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top = 'test_ra_sdr.v'
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sdr = True
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elif model == 'ddr1x':
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top = 'test_ra_ddr_1x.v'
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ddr = True
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ddr1x = True
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else:
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top = 'test_ra_ddr.v'
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ddr = True
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errors = 0
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cyc = 0
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quiesceCyc = 5 # before end
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# build model
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sim = pyverilator.PyVerilator.build(top, verilog_path=rtl)
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print('io')
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print(sim.io)
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print()
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print('internals')
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# issue #8 - try local fix
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print(sim.internals)
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print()
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#print('ra')
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#print(sim.internals.ra)
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# array0,1,2 dont exist as submodules???
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#print()
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#
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#print('ra.add_clk')
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#print(sim.internals.ra.add_clk)
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#print()
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if vcd:
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sim.start_gtkwave(auto_tracing=False)
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#wtf vectors are failing
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# will make this load a savefile anyway someday
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# this doesn't actually restrict what's beign recorded anyway; still
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# can load saved netlist after sim
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#sim.send_to_gtkwave(sim.io)
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#for s in sim.io:
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# try:
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# sim.send_to_gtkwave(sim.io[s])
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# except:
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# print(f'*** failed {s}')
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####################################################################
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# Functions, Classes
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def getSimTime():
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return (sim.curr_time, cyc)
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msg(init=getSimTime)
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# sim-driven signals don't look like _q since they are set after the eval(clk=1) tick
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# would have to set after eval of rising edge but also not do a simtick
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def tick():
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sim.eval()
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if vcd:
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sim.add_to_vcd_trace()
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def run(n=1, cb=None):
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global cyc
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if sdr or ddr1x:
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for i in range(n):
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sim.io.clk = 0
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tick()
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sim.io.clk = 1
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tick()
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elif ddr:
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for i in range(n):
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sim.io.clk = 0
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sim.io.clk2x = 1
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tick()
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sim.io.clk2x = 0
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tick()
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sim.io.clk = 1
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sim.io.clk2x = 1
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tick()
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sim.io.clk2x = 0
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tick()
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cyc += 1
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if not vcd: # should be done by pyv!!!!
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sim.curr_time = cyc * 10
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if cb is not None:
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(cb)()
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def fail(t=None):
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global errors, stopOnFail
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msg('*** FAIL ***')
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errors += 1
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if t is not None:
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msg(t)
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class Memory:
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def __init__(self, locs, bits, init=0):
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self.mem = [init] * locs
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self.bits = bits
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def read(self, adr):
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return self.mem[adr]
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def readall(self):
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mem = []
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for i in range(len(self.mem)):
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mem.append(self.mem[i])
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return mem
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def write(self, adr, dat):
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self.mem[adr] = dat
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def __str__(self):
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t = ''
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for i in range(0,len(self.mem),4):
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t1 = f'[{i:02X}] {self.mem[i]:018X}'
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for j in range(i+1, i+4):
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t1 += f' [{j:02X}] {self.mem[j]:018X}'
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#t1 += f' {self.mem[j]:018X}\n'
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t += t1 + '\n'
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return t
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class Port:
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def __init__(self, id, type='r'):
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self.id = id
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self.type = type
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def read(self, adr):
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sim.io[f'rd_enb_{self.id}'] = 1
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sim.io[f'rd_adr_{self.id}'] = adr
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msg(f'Port={self.id} RD @{adr:02X}')
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def write(self, adr, dat):
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sim.io[f'wr_enb_{self.id}'] = 1
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sim.io[f'wr_adr_{self.id}'] = adr
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sim.io[f'wr_dat_{self.id}'] = dat
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msg(f'Port={self.id} WR @{adr:02X}={dat:02X}')
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def data(self):
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return int(sim.io[f'rd_dat_{self.id}'])
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def idle(self):
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if self.type == 'r':
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sim.io[f'rd_enb_{self.id}'] = 0
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sim.io[f'rd_adr_{self.id}'] = 0 # random
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else:
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sim.io[f'wr_enb_{self.id}'] = 0
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sim.io[f'wr_adr_{self.id}'] = 0 # random
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sim.io[f'wr_dat_{self.id}'] = 0 # random
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def printstate():
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mac = sim.internals.ra
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if sdr:
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msg(f'R0: {mac.rd_enb_0_q:01X} {mac.rd_adr_0_q:02X} {mac.rd_dat_0_q:018X} R1: {mac.rd_enb_1_q:01X} {mac.rd_adr_1_q:02X} {mac.rd_dat_1_q:018X}')
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msg(f'W0: {mac.wr_enb_0_q:01X} {mac.wr_adr_0_q:02X} {mac.wr_dat_0_q:018X}')
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else:
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msg(f'R0: {mac.rd_enb_0_q:01X} {mac.rd_adr_0_q:02X} {mac.rd_dat_0_q:018X} R1: {mac.rd_enb_1_q:01X} {mac.rd_adr_1_q:02X} {mac.rd_dat_1_q:018X} R2: {mac.rd_enb_2_q:01X} {mac.rd_adr_2_q:02X} {mac.rd_dat_2_q:018X} R3: {mac.rd_enb_3_q:01X} {mac.rd_adr_3_q:02X} {mac.rd_dat_3_q:018X}')
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msg(f'W0: {mac.wr_enb_0_q:01X} {mac.wr_adr_0_q:02X} {mac.wr_dat_0_q:018X} W1: {mac.wr_enb_1_q:01X} {mac.wr_adr_1_q:02X} {mac.wr_dat_1_q:018X}')
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def printfinal():
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print()
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print()
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print('Final State')
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print(f'Model : {top}')
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print()
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print(data)
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# should be checking actual mem[][] here, but can't access signals
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print()
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for i in range(len(portsRd)):
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print(f'Reads Port {i}: {reads[i]}')
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for i in range(len(portsWr)):
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print(f'Writes Port {i}: {writes[i]}')
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print()
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print(f'Seed: {seed:08X}')
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print(f'Cycles: {cyc}')
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print(f'Errors: {errors}')
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def check(port, adr, exp=None):
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if exp is None:
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exp = data.read(adr)
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act = portsRd[port].data()
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if act != exp:
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fail(f'* RD MISCOMPARE * port={port} adr={adr:02X} act={act:018X} exp={exp:018X}')
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return False
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elif verbose:
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msg(f'* RD COMPARE * port={port} adr={adr:02X} act={act:018X} exp={exp:018X}')
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return True
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####################################################################
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# Do something
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msg(f'Initializing seed to {hex(seed)}')
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random.seed(seed)
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data = Memory(64, 72)
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if sdr:
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portsRd = [Port(0, 'r'), Port(1, 'r')]
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portsWr = [Port(0, 'w')]
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else:
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portsRd = [Port(0, 'r'), Port(1, 'r'), Port(2, 'r'), Port(3, 'r')]
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portsWr = [Port(0, 'w'), Port(1, 'w')]
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# Array Cycle Timings
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#
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# write
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# | e/a/d | acc | valid |
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# * latched by wrapper (in)
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#
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#
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# read
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# | e/a | acc | valid |
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# * latched by wrapper (in)
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# * latched by wrapper (out)
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#
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# rd(a) = wr(a) (both enabled):
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# reset
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sim.io.reset = 1
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run(1)
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sim.io.reset = 0
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# idle
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for p in portsRd:
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p.idle()
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for p in portsWr:
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p.idle()
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run(10)
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# init array
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if sdr:
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for a in range(0, 64, 1):
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d0 = int(f'5555555555555555{a:02X}', 16)
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portsWr[0].write(a, d0)
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run(1, printstate)
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data.write(a, d0) # now visible for reads
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portsWr[0].idle()
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else:
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for a in range(0, 64, 2):
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d0 = int(f'5555555555555555{a:02X}', 16)
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portsWr[0].write(a, d0)
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d1 = int(f'5555555555555555{a+1:02X}', 16)
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portsWr[1].write(a+1, d1)
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run(1, printstate)
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data.write(a, d0) # now visible for reads
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data.write(a+1, d1) # now visible for reads
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portsWr[0].idle()
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portsWr[1].idle()
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# random cmds
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# writes: visible to all reads in cycle n+1,...
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# reads: check in cycle n+2 vs mem data in cycle n+1
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#
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# every cycle:
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# save data state
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# pick weighted read0, read1, read2, read3, write0, write1 (cmd freq, adr) and ensure no adr coll if req'd
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# schedule data change (write)
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# schedule checks (read)
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updates = []
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checks = []
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reads = [0, 0, 0, 0]
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writes = [0, 0]
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saveData = None
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quiesced = False
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quiesceCyc = cyc + runCycs - quiesceCyc
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#d = int('1000', 16)
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msg('Starting random loop.')
|
||
|
|
for c in range(runCycs):
|
||
|
|
|
||
|
|
ok = True
|
||
|
|
|
||
|
|
# check reads
|
||
|
|
checksNext = []
|
||
|
|
for i in range(len(checks)):
|
||
|
|
rd = checks[i]
|
||
|
|
if cyc == rd[0]:
|
||
|
|
ok = ok and check(rd[1], rd[2], saveData[rd[2]])
|
||
|
|
else:
|
||
|
|
checksNext.append(rd)
|
||
|
|
checks = checksNext
|
||
|
|
|
||
|
|
# do writes
|
||
|
|
updatesNext = [] # always only 1 cycle
|
||
|
|
for i in range(len(updates)):
|
||
|
|
wr = updates[i]
|
||
|
|
if cyc == wr[0]:
|
||
|
|
data.write(wr[2], wr[3])
|
||
|
|
else:
|
||
|
|
print('HUH? should always be this cycle!', cyc, updates)
|
||
|
|
quit()
|
||
|
|
updates = updatesNext
|
||
|
|
|
||
|
|
# save current data
|
||
|
|
saveData = data.readall()
|
||
|
|
|
||
|
|
# quiesce?
|
||
|
|
if cyc >= quiesceCyc:
|
||
|
|
if not quiesced:
|
||
|
|
msg('Quiescing...')
|
||
|
|
quiesced = True
|
||
|
|
|
||
|
|
# write coll will give w1 precedence - or make it avoid
|
||
|
|
aw = [None] * 2
|
||
|
|
for i in range(len(portsWr)):
|
||
|
|
portsWr[i].idle()
|
||
|
|
aw[i] = -1
|
||
|
|
if not quiesced and randint(1, 10) < 5:
|
||
|
|
r = rangesWr[i]
|
||
|
|
aw[i] = randint(r[0], r[1])
|
||
|
|
d = int(hexrandom(18), 16)
|
||
|
|
portsWr[i].write(aw[i], d)
|
||
|
|
updates.append((cyc+1, i, aw[i], d))
|
||
|
|
writes[i] += 1
|
||
|
|
|
||
|
|
for i in range(len(portsRd)):
|
||
|
|
portsRd[i].idle()
|
||
|
|
if not quiesced and randint(1, 10) < 5:
|
||
|
|
r = rangesRd[i]
|
||
|
|
ar = randint(r[0], r[1])
|
||
|
|
while ar == aw[0] or ar == aw[1]:
|
||
|
|
ar = randint(r[0], r[1])
|
||
|
|
portsRd[i].read(ar)
|
||
|
|
checks.append((cyc+2, i, ar))
|
||
|
|
reads[i] += 1
|
||
|
|
|
||
|
|
run(1, printstate)
|
||
|
|
if not ok and stopOnFail:
|
||
|
|
break
|
||
|
|
|
||
|
|
####################################################################
|
||
|
|
# Clean up
|
||
|
|
|
||
|
|
printfinal()
|
||
|
|
|
||
|
|
if ok and errors == 0:
|
||
|
|
print()
|
||
|
|
print('You has opulence.')
|
||
|
|
print()
|
||
|
|
else:
|
||
|
|
print()
|
||
|
|
print('You are worthless and weak!')
|
||
|
|
print()
|
||
|
|
|
||
|
|
print('Done.')
|