OpenPOWER Cores
Verilog 0 0

An experimental small core based on VexRiscv, written in Scala

Updated 3 months ago

Verilog 1 1

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 1 month ago

Verilog 1 1

A tiny Open POWER ISA softcore written in VHDL 2008

Updated 1 month ago

Python 1 0

Updated 3 weeks ago

F* 1 0

High-specific-bandwidth memory design

Updated 1 week ago

VHDL 2 1

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

Updated 4 months ago