VHDL 2 1

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

Updated 2 months ago

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

Updated 3 months ago

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 3 months ago

Verilog 1 1

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 1 month ago

Verilog 0 0

An experimental small core based on VexRiscv, written in Scala

Updated 1 month ago

The purpose of this design is to enable the AC922 to accept a DC-SCM v1.0 hardware management module. This enables AC922 as a development platform for DC-SCM development and test.

Updated 5 months ago

Updated 1 year ago

Updated 1 year ago

The Workgroup Charter Template

Updated 1 year ago

Updated 1 year ago

This repo houses or points to the gateware (FPGA image code) for the librebmc project

Updated 2 months ago

This is the main libreBMC repo that contains an overview of the project and useful links. Start here.

Updated 2 months ago

This is the main libreBMC repo that contains an overview of the project and useful links. Start here.

Updated 2 months ago

Updated 2 months ago

Updated 12 months ago

Updated 1 month ago

Meeting Minutes for the OPF Academic BoF

Updated 8 months ago

A tiny Open POWER ISA softcore written in VHDL 2008

Updated 1 day ago

A tiny Open POWER ISA softcore written in VHDL 2008

Updated 3 months ago