The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
Updated 12 months ago
The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
Updated 10 months ago
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
Updated 2 months ago
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
Updated 12 months ago
An experimental small core based on VexRiscv, written in Scala
Updated 9 months ago
The purpose of this design is to enable the AC922 to accept a DC-SCM v1.0 hardware management module. This enables AC922 as a development platform for DC-SCM development and test.
Updated 1 year ago
Updated 2 years ago
The Workgroup Charter Template
Updated 2 years ago
Updated 2 years ago
Updated 7 months ago
Curriculum material for teaching computer architecture with MIPS and POWER
Updated 5 months ago
Updated 2 years ago
A collection of scripts and meta data for managing the OPF Hub systems with IPMI via the OpenBMC.
Updated 7 months ago
This is the main libreBMC repo that contains an overview of the project and useful links. Start here.
Updated 8 months ago
This is the main libreBMC repo that contains an overview of the project and useful links. Start here.
Updated 10 months ago
This is the main libreBMC repo that contains an overview of the project and useful links. Start here.
Updated 8 months ago
Updated 2 years ago
Updated 10 months ago
Updated 2 years ago
Updated 2 weeks ago