Updated 7 months ago

Updated 5 months ago

The purpose of this design is to enable the AC922 to accept a DC-SCM v1.0 hardware management module. This enables AC922 as a development platform for DC-SCM development and test.

Updated 5 months ago

Updated 4 months ago

A test site for a high-specific-bandwidth memory design

Updated 2 months ago

The Workgroup Charter Template

Updated 2 months ago

An experimental small core based on VexRiscv, written in Scala

Updated 2 months ago

Verilog 0 0

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue

Updated 1 month ago

VHDL 0 0

The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers

Updated 1 month ago

Updated 3 weeks ago

Updated 3 weeks ago

Updated 3 weeks ago

Updated 2 weeks ago

Verilog 1 1

A test site for a high-specific-bandwidth memory design

Updated 2 weeks ago