From 2342edca684070dc0a08de3ded5a9fab54f16f16 Mon Sep 17 00:00:00 2001 From: Toshaan Bharvani Date: Fri, 7 May 2021 09:49:34 +0200 Subject: [PATCH] feedback from Lionel on cosmetic changes Signed-off-by: Toshaan Bharvani --- content.tex | 179 +++++++++++++++++++++++++++------------------------- 1 file changed, 93 insertions(+), 86 deletions(-) diff --git a/content.tex b/content.tex index 816937d..456ac08 100644 --- a/content.tex +++ b/content.tex @@ -2,43 +2,43 @@ \section{Workgroup name} -LibreBMC Special Integration Work Group (SIG) +LibreBMC \acrfull{SIG} \section{Definitions} -Reference the OpenPOWER Foundation IPR Policy and OpenPOWER WorkGroup Process for additional term definitions. +Reference the OpenPOWER Foundation \acrshort{IPR} Policy and OpenPOWER WorkGroup Process for additional term definitions. -\begin{itemize} +\begin{enumerate} \item ``Maintainer" is an Eligible or Non-Eligible participant of the workgroup that has been elected by Full Majority Vote to review and -approve changes to the LibreBMC code in the git repository(ies) created by this SIG. -\end{itemize} +approve changes to the LibreBMC code in the git repository(ies) created by this \acrshort{SIG}. +\end{enumerate} \section{Description} -The LibreBMC SIG is a project workgroup whose purpose is to create a reference design of an open source Baseboard Management Controller (BMC) compatible -with the Open Compute Project (OCP) Datacenter Secure Control Module (DC-SCM) specification, named ``LibreBMC".\par +The LibreBMC \acrshort{SIG} is a project workgroup whose purpose is to create a reference design of an open source \acrfull{BMC} compatible +with the \acrfull{OCP} \acrfull{DC-SCM} specification, named ``LibreBMC".\par -The goal of the SIG is advance the state of the open source hardware community through the design and implementation of LibreBMC. -The SIG will use many open source tools and components, including open POWER ISA processor soft core, -Register-Transfer-Level (RTL) for all required BMC interfaces and controls, design and synthesis tools, PDKs, DC-SCM board reference designs and -BMC software to design and implement LibreBMC in order to contribute to their growth and usability.\par +The goal of the \acrshort{SIG} is advance the state of the open source hardware community through the design and implementation of LibreBMC. +The SIG will use many open source tools and components, including open POWER \acrshort{ISA} processor soft core, \acrfull{RTL} +for all required \acrshort{BMC} interfaces and controls, design and synthesis tools, \acrfull{PDK}'s, \acrshort{DC-SCM} board reference designs and +\acrshort{BMC} software to design and implement LibreBMC in order to contribute to their growth and usability.\par -The purpose of LibreBMC is to be a fully open source BMC design which will enhance the security of server management control by utilizing open hardware -and software, and designed with fully open source tooling.\par +The purpose of LibreBMC is to be a fully open source \acrshort{BMC} design which will enhance the security of +server management control by utilizing open hardware and software, and designed with fully open source tooling.\par -The requirement of a POWER ISA core will drive the design and open release of a new or improved POWER soft-core. +The requirement of a POWER \acrshort{ISA} core will drive the design and open release of a new or improved POWER soft-core. \section{Scope} -The scope of the LibreBMC SIG is the creation of a functional BMC prototype. -The prototype will include a DC-SCM card design with a FPGA controller. -The FPGA image will consist of a POWER ISA core(s) that can run the OpenBMC stack (including LSB) and +The scope of the LibreBMC \acrshort{SIG} is the creation of a functional \acrshort{BMC} prototype. +The prototype will include a \acrshort{DC-SCM} card design with a \acrfull{FPGA} controller. +The \acrshort{FPGA} image will consist of a POWER \acrshort{ISA} core(s) that can run the OpenBMC stack (including \acrfull{LSB}) and manage the interface between system-management software and platform hardware. -The FPGA image will also have all controls and interfaces required of a typical BMC.\par +The \acrshort{FPGA} image will also have all controls and interfaces required of a typical \acrshort{BMC}.\par -LibreBMC will be compatible with the OCP DC-SCM specification. -Any changes to the OCP DC-SCM specification is outside the scope of this workgroup and will be handled through OCP.\par +LibreBMC will be compatible with the \acrshort{OCP} \acrshort{DC-SCM} specification. +Any changes to the \acrshort{OCP} \acrshort{DC-SCM} specification is outside the scope of this workgroup and will be handled through \acrshort{OCP}.\par LibreBMC should meet the requirements to manage a variety of server architectures, including but not limited to POWER, ARM, and x86 based systems. Any changes to system reference designs or specifications to use LibreBMC are outside the scope of this workgroup.\par @@ -48,7 +48,7 @@ Any modifications of these are outside the scope of the workgroup and will be ha \section{Similar Activities} -\begin{enumerate} +\begin{itemize} \item Accelerator Workgroup : may work with to define the requirements for open tooling needed to complete the implementation of LibreBMC components. \item @@ -62,44 +62,50 @@ OpenPOWER compliant systems that will run on LibreBMC. \item Development Platform Workgroup : defines the reference architecture of future OpenPower systems that may incorporate and use LibreBMC to manage the system. -\end{enumerate} +\end{itemize} \section{Users} -Any system vendor, datacenter, or cloud that plans to use a BMC, compatible with the OCP DC-SCM form factor to manage their system. -Any third-party hardware manufacturers that choose to build BMC's compatible with the DC-SCM specification. +\begin{itemize} +\item +Any system vendor, datacenter operator, or cloud provider that plans to use a \acrshort{BMC}, +compatible with the \acrshort{OCP} \acrshort{DC-SCM} form factor to manage their system. +\item +Any third-party hardware manufacturer that choose to build \acrshort{BMC}s compatible with the \acrshort{DC-SCM} specification. +\item Any monitoring / base software vendors. +\end{itemize} \section{Work Product} -\begin{enumerate} +\begin{itemize} \item -FPGA RTL for a POWER ISA soft-core +\acrshort{FPGA} \acrshort{RTL} for a POWER \acrshort{ISA} soft-core \item -FPGA RTL that includes the soft-core and all required interfaces and controls +\acrshort{FPGA} \acrshort{RTL} that includes the soft-core and all required interfaces and controls \item Working LibreBMC prototype \item Demonstration of LibreBMC managing a system -\end{enumerate} +\end{itemize} -The FPGA RTL and reference material will be open to the general public and maintained in a public git repository(ies). +The \acrshort{FPGA} \acrshort{RTL} and reference material will be open to the general public and maintained in a public git repository(ies). \section{Projects} -\begin{enumerate} +\begin{itemize} \item -Design an FPGA based POWER ISA soft-core capable of running OpenBMC that meets reasonable performance requirements +Design an \acrshort{FPGA} based POWER \acrshort{ISA} soft-core capable of running OpenBMC that meets reasonable performance requirements \item -Design and build an FPGA image for LibreBMC that contains one or more of the POWER ISA soft cores, along with the required interfaces and -controls, that is capable of managing a server. +Design and build an \acrshort{FPGA} image for LibreBMC that contains one or more of the POWER \acrshort{ISA} soft cores, +along with the required interfaces and controls, that is capable of managing a server. \item Create required material to properly document how to recreate and use the design. \item Build a prototype of LibreBMC. \item -Demonstrate the operability of LibreBMC containing the above mentioned FPGA image in a server. -\end{enumerate} +Demonstrate the operability of LibreBMC containing the above mentioned \acrshort{FPGA} image in a server. +\end{itemize} \section{Participation} @@ -125,59 +131,59 @@ Subsequent meetings will be held bi-weekly alternating between 5p CST Wednesday \section{Participants} -\begin{enumerate} +\begin{itemize} \item IBM - \begin{enumerate} + \begin{itemize} \item Paul Lecocq (lecocq@us.ibm.com) \item Paul Mackerras (pmac@au1.ibm.com) \item Steve Roberts (robers@us.ibm.com) - \end{enumerate} + \end{itemize} \item Google - \begin{enumerate} + \begin{itemize} \item Tim Ansel (tansell@google.com) - \end{enumerate} + \end{itemize} \item Antmicro - \begin{enumerate} + \begin{itemize} \item Michael Gielda (mgielda@antmicro.com) - \end{enumerate} + \end{itemize} \item Raptor Computing Systems - \begin{enumerate} + \begin{itemize} \item Timothy Pearson (tpearson@raptorengineering.com) - \end{enumerate} + \end{itemize} VanTosh - \begin{enumerate} + \begin{itemize} \item Toshaan Bharvani (toshaan@vantosh.com) - \end{enumerate} + \end{itemize} Yadro - \begin{enumerate} + \begin{itemize} \item Alexey Stepanov (a.stepanov@yadro.com) - \end{enumerate} -\end{enumerate} + \end{itemize} +\end{itemize} \section{Balloting Approval Requirements} While the WG aims to operate as a consensus based community from time to time a WG decision may require a vote to move a Project forward.\par Standard WG Process applies with the following specific requirements with respect to Maintainers : -\begin{enumerate} +\begin{itemize} \item Election of repository Maintainer(s) will be by Full Majority Vote. A Maintainer can be removed from their position as Maintainer by Full Majority Vote as well. \item The initial Maintainer(s) will be voted in prior to setting up the git repository for the project. -\end{enumerate} +\end{itemize} \section{Member Organization Support} @@ -185,14 +191,14 @@ Member organization support will be confirmed as part of the approval process. \section{Anticipated Contributions} -\begin{enumerate} +\begin{itemize} \item -Power ISA Core RTL +POWER \acrshort{ISA} Core \acrshort{RTL} \item -RTL created as part of the workgroup deliverable +\acrshort{RTL} created as part of the workgroup deliverable \item -OCP DC-SCM compatible board schematics -\end{enumerate} +\acrshort{OCP} \acrshort{DC-SCM} compatible board schematics +\end{itemize} \section{IPR, Confidentiality \& Licensing} @@ -231,31 +237,32 @@ The executed Contribution / Feedback License or Guest Participation Agreement mu As a default position, all Code that is, or is made part of, an OpenPOWER Deliverable shall be licensed out by OpenPOWER under one of the following licenses and shall at least be provided in source code form. -The selected license will include or be accompanied by a clarification that any necessary license rights for the Power ISA comes from -the Power ISA license and is not granted under the selected license for the OpenPOWER Deliverable. -\begin{enumerate} +The selected license will include or be accompanied by a clarification that any necessary license rights for the Power \acrshort{ISA} comes from +the POWER \acrshort{ISA} license and is not granted under the selected license for the OpenPOWER Deliverable. +\begin{itemize} \item Apache License, V2.0 with the condition that the patent license granted in Section 3 of the License, as applied to the ``Work", hereby includes implementations of the Work in physical form. \item a future open hardware license with WG, TSC, and Board approval. +\end{itemize} \subsection{Open Source Communities} This WG may accept Code from the following OS Communities under their respective licenses. -\begin{enumerate} +\begin{itemize} \item LiteX - \begin{enumerate} + \begin{itemize} \item https://github.com/enjoy-digital/litex \item 2-Clause BSD - \end{enumerate} + \end{itemize} \item Microwatt POWER ISA Core - \begin{enumerate} + \begin{itemize} \item https://github.com/antonblanchard/microwatt \item @@ -263,73 +270,73 @@ Microwatt POWER ISA Core \end{itemize} \item Antmicro DC-SCM board - \begin{enumerate} + \begin{itemize} \item https://github.com/antmicro/artix-dc-scm (ecp5-dc-scm) \item Apache license, Version 2.0 - \end{enumerate} -\end{enumerate} + \end{itemize} +\end{itemize} This WG may accept other OS Code under a Permissive License such as Apache License, v2.0, 2 or 3 clause BSD, MIT, ISC, -or other OS license approved by this WG, TSC and Board.\par +or other \acrshort{OS} license approved by this WG, TSC and Board.\par -This WG may contribute Code to the following OS Communities under either the respective OS Communities required license or an approved WG deliverable -license as defined in the above OS Licensing Mode.\par +This WG may contribute Code to the following \acrshort{OS} Communities under either the respective \acrshort{OS} Communities +required license or an approved WG deliverable license as defined in the above \acrshort{OS} Licensing Mode.\par -\begin{enumerate} +\begin{itemize} \item OpenBMC - \begin{enumerate} + \begin{itemize} \item https://github.com/openbmc - \ite, + \item Apache license, Version 2.0 - \end{enumerate} + \end{itemize} \item LiteX - \begin{enumerate} + \begin{itemize} \item https://github.com/enjoy-digital/litex \item 2-Clause BSD - \end{enumerate} + \end{itemize} Microwatt POWER ISA Core - \begin{enumerate} + \begin{itemize} \item https://github.com/antonblanchard/microwatt \item Apache License, Version 2.0 - \end{enumerate} + \end{itemize} Antmicro DC-SCM board - \begin{enumerate} + \begin{itemize} \item o https://github.com/antmicro/artix-dc-scm or ecp5-dc-scm \item Apache license, Version 2.0 - \end{enumerate} + \end{itemize} SymbiFlow - \begin{enumerate} + \begin{itemize} \item https://symbiflow.github.io/ \item ISC License - \end{enumerate} + \end{itemize} Yosys - \begin{enumerate} + \begin{itemize} \item http://www.clifford.at/yosys/ \item ISC License - \end{enumerate} + \end{itemize} Project X-Ray - \begin{enumerate} + \begin{itemize} \item https://github.com/SymbiFlow/prjxray \item ISC License - \end{enumerate} -\end{enumerate} + \end{itemize} +\end{itemize} This WG may accept or contribute Code from/to additional OS Communities with approval by the WG, TSC, and Board. Any code accepted from or contributed to approved OS Communities must be under a Permissive License such as