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New version [HERE](https://files.openpower.foundation/s/k5Hny649q3XHSqk)
# AGENDA
## Procedural update
* Todd to run the late call with the Australians
* Karol to run the Europe time call (this call)
## Getting hardware to people -- Update
There are 3 components: host system (AC922), Interposer board, DC-SCM Board.
* AC922
* 1 is in Rochester
* 1 is in Australia
* 1 is in Sunnyvale, USA @ Google
* 1 is in Seattle, USA @ Google
* Loaner from IBM Poland to Antmicro is in process
* Some snags remain and are being worked through
* No timeframe yet
* Further action on aquiring AC922s
* Antmicro is purchasing one and should have it soon
* Snags have been worked through and reports are it should arrive in 3 weeks
* VanTosh will also be purchasing at least one
*
* Interposer
* 6 pieces. Parts for 4 more are in Rochester
* Next step is to have them built
* Todd was unable to get into the office as planned due to Covid Restrictions
* Todd has permission for tomorrow and plans to deliver the parts to card build
* 2 are in Rochester
* 2 are in Australia
* Delivered
* 2 are at Antmicro
* Reports are these have been delivered.
* They have been delivered!
* DC-SCM board
* 4 boards, but only 3 have FPGAs
* Update is Google is providing some to Antmicro.
* 6 weeks out at least
* Also attempting to get some from China
* Plan to have 10 total when the FPGAs arrive.
* Need to be tested
* Update: Australia can get into the plant, so best may be to send 1 DC-SCM to Australia for bringup in parallel with the Antmicro bringup.
* Need general smoke test, RAM, ethernet test, GPIOs
* Once the FPGAs come, they will test and ship to Australia
* Since we are 3 weeks out on getting the AC922s to Antmicro, can we ship a smoke tested DC-SCM to IBM Australia ASAP? Karol to check.
* Need to start working on getting Lattice parts for the DC-SCM board. Michael will take the lead on this.
* PCBs sent in for production for lattice FPGA
* Still need memory and ethernet parts
* Marshall offered to help if there are issues getting FPGAs
* Lattice was interested in having a Crosslink-NX / Cerbra DC-SCM board designed.
*
## OCP Summit
* Todd to show the booth location and layout
* Want to have a "LibreBMC" setup for OCP Summit booth
* Plan to ship from Rochester. Need a DC-SCM card in Rochester.
* Cannot power the AC922 at the booth
* However, could we just power the DC-SCM card
* The booth has only 1 2ft pedestal
* Thinking just the AC922 hardware is what we will have.
* There will not be a screen to show the demo
* LibreBMC was approved for a 5 minute "lightening" presentation.
* Need to determine the key points to make and who will present
* In addition to the 5 minute live presentation, a 20-30 minute full presentation can be shown as a part of the virtual conference
* First Deadline for submission is Oct 11th
* Final Deadline is Oct 25th
* Want a demo to be videotaped for that virtual conference presentation.
* Antmicro will help to create the demo
* What to show on the demo
* BMCweb UI.
* Lots of sensors/etc could be shown.
* Presentation of LibreBMC to the OCP DC-SCM working group has been moved to the public meeting on the first week of October.
* Todd to create initial set of charts
* Still in progress
* Antmicro to update and co-present
* Todd to re-send the info regarding the meeting details
* Yacoub Oulad Daoud <yacoub@google.com> is chasing Tim about slides for "A fully open source (tooling, hardware RTL, software) BMC"
* AI(tansell@google.com): Send an introduction email.
* rosedahl@us.ibm.com
## Gateware
* We **need** to a "real" LiteX based SoC rather than a FuseSoC + LiteX generator based mismash.
* Example -- https://github.com/litex-hub/linux-on-litex-vexriscv
* Need someone to fill the repo and fix the issues.
* Any candidates?
* Requirements for gateware;
* Must support following hardware parts;
* Xilinx Artix 7 35T (current test board Arty A7-35T)
* Lattice ECP5 25T (current test board ????)
* [future] Lattice Crosslink NX (17k LUTs)
* Expectation is that the full multi-core (minimum 2, preferred 4) and all the peripherals fit into these small FPGAs without problems (IE place and route takes under 15 minutes).
* We know this can be done for RISC-V due to https://antmicro.com/blog/2020/05/multicore-vex-in-litex/
* > Taking only 70% of a 35 KLUT FPGA
* This is really about performance and fit.
* https://j.mp/fpgabmc-bench
* https://j.mp/softcpu-on-fpgas
## Software
### LiteEth upstreaming
* Joel 'shenki' Stanley upstreamed the LiteEth driver
* Mendy is looking at getting Joel more time to work on stuff in this area.
