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meetingminutes/2022/20220629.md

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title date attendees draft
Meeting Minutes 2022-06-29 2022-06-29
toddrosedahl,ibm
toshaanbharvani,vantosh
antonblanchard,ibm
michaelneuling,ibm
munirahmad,lattice
lukeleighton,libre-soc
konstantinous,vectorcampgr
andrey,libre-soc
cesar,libre-soc
jacob,libre-soc
timpearson,raptorengineering
paulmackerras,ibm
false

LibreBMC SIG Meeting

Meeting date: 29 June 2022 Access link: https://zoom.us/j/91597478078 Meeting ID: 91597478078

Call to Order

Anti-trust Reminder

This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundation’s Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: Antitrust Guidelines

Meeting Recording

Meeting is being recorded

AGENDA

Introduction

New folks this week?

New News

Any update?

Hardware Update

Bringup

  • AntMicro has all the HW it needs to do bring-up on the AC922.
    • However, they have very little time to spend on this
  • AntMicro will send a DC-SCM card to Toshaan
  • Todd will send an Interposer to Toshaan
  • I have not yet done this. Does it still make sense?
    • Yes, Toshaan still has time and resources available

OCP DC-SCM 2.0 Working Group -- Meets bi-weekly

Todd to run a call with Google, Munir from Lattice, and some other key players to discuss our common direction for the 3.0 standard. WIP.

  • DC-SCM 2.0 Has been submitted

Conferences

  • Todd Still working to set up various follow-ups
  • We need something new to showcase at OCP22 and SC22

Overall Goal Reminder: We want to boot an AC922 using an FPGA (not the AST2500 ASIC) on a DC-SCM card. We want to prove that the FPGA can boot a high power, modern server.

To do this, we need the following pieces:

  1. A DC-SCM card that has an FPGA on it to replace the AST2500 ASIC a. Antmicro built a few of these that use Xylinx A7s. They power on, but no bring-up has been done to show they will boot the system. b. Antmicro is building some that have ECP5’s on them, but they are still missing some parts
  2. An interposer that will plug into the DC-SCM card and the AC922. a. I have 6 of these built
  3. A Root of Trust bypass jumper a. Plans for these are available and they are easy to build
  4. A softcore (microwatt) running on the FPGA a. This works, but it needs to be better incorporated with Lite-x b. Can use libreSOC. Yes, we think so as Libre-SOC is a drop-in replacement (more or less) c. Can use Kestral
    • Raptor has PCI-e connected. ECP5 based cards booting up a blackbird.
    • Runs Zepher RTOS on microwatt. Does not run linux. https://www.zephyrproject.org/
    • Next step to add graphical output (framebuffer)
    • DC-SCM to SO-DIMM interposer card (possibility)
    • Raptor could make a DC-SCM card and interposer to boot a Kestrel from the DC-SCM card
  5. Full gateware in Lite-x for the target FPGA is needed such that the entire OpenBMC stack can run a. Some modules are done. Some not. I have the list.
  6. Full OpenBMC code running a. We currently power on our prototype with scripts. OpenBMC is not running. * OpenBMC runs YOCTO https://www.yoctoproject.org/

So far we did a prototype where we used the xilinx A7 FPGA on a custom breadboard and ran microwatt and a very stripped down FPGA. We proved it could boot the AC922, but again it was very low function. We need to have it fully functional to really prove it.

  • Getting to the overall goal above by OCP22 (Oct 18th) seems unachievable at the current pace

  • Other options:

    • Show the bringup of the real DC-SCM card (A7) on the AC922. Show it can boot, but use scripts as we did prior. OpenBMC not running. Very few gateware additions.
    • Pivot to the ECP5 using OpenBMC on the DC-SCM card.
      • Gateware is all there (per Raptor)
        • lite-x, n-migen, nextpnr-ecp5, yosys. all Libre-Licensed
      • Open-Source tooling is better
        • Usable with no legal issues
    • Do a simulation only -- better to use real hardware
      • Could have 2 FPGAs
      • 1 is the BMC
      • The other FPGA could be some sort of a representation of the system
        • Implement HB on it?
        • Run QEMU?
        • Some other simulation running?

Communication / Collaboration

  • Calendar invites are working now it seems.

    • Cal invites did not work. Todd/Toshaan to work offline on it.
    • Cal invites did not work again -- at least on outlook

  • Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.

  • I created new repos on git in order to be able to point people at the information they need to get started and help out

  • https://git.openpower.foundation/librebmc

Gateware

Update?

Simulation

  • Renode looks like a good option for a simulation environment for LibreBMC.
    • Todd to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. WIP

Soft Cores

  • OPF is funding an FPGA optimized POWER soft core
    • Target was "VexRISCV" resource usage and performance. **Todd to schedule a readout at a future meeting. Toshaan to check on when they could present

Toolchain

Updates?

Software

Updates?

FPGA Usage Barriers

  • List of opens (potential barriers) for using FPGAs as BMCs
    • Cost --
      • Projection is that will be cost competitive
      • Some things require an external chip
        • video driver, but could be added later
    • Soft Error Rates -- Munir to follow up
      • Hard fails roughly the same as an ASIC
      • Looks like Xilinx SER FIT is reasonable (<200).
      • And detectable and fixable with an image reload
      • Lattice to provide data on FIT rates and recovery design
        • Munir did send an email with info
    • Performance? 8X slower than an ASPEED?
      • Information from Lattice
        • much faster to BMC to boot. 2min for ASPEED. 5sec for FGPA
          • This is mostly a function of the BMC stack, the ASPEED vs FPGA, so potentially not Apples to Apples (ASPEED vs FPGA)
        • Lattice to provide some information on this performance comparisons to ASPEED
        • How long will it take the system to boot on the FPGA?
        • Opening up of LTPI is under consideration (MIT)
    • Image size * 85,000 latches ECP5 * New chips coming. See last week's minutes * How to optimize image space? * Currently microwatt fits easily in 85,000 latches * https://github.com/antonblanchard/microwatt * our CI results are here * https://github.com/antonblanchard/microwatt/actions/runs/2205354319 * https://github.com/antonblanchard/microwatt/blob/master/.github/workflows/test.yml#L70

Project Ideas -- Running list of areas where we could use help

Workgroup Collaboration Tools

Community Involvement

  • Options for not needing an AC922

    • FPGA on both sides (emulating the HPM)
      • Raptor has such a board that has an FPGA on both sides
    • Can just use QEMU and simulate the AC922 side

  • How do we generate more activity/interest

    • Engage Universities -- There are interested universities

    • Todd to start a list of universities and contacts New direction here. Todd/Toshaan to make an OPF page "Education Page" that points to these projects as well as the OpenPOWER curriculum being developed. Then we can all point our education contacts to that page. No need to list them here

    • Need clear work breakdown. We have this for some projects.

    • Need Mentors. True for Interns/MLH/etc, but many projects can be supported in the open

    • Offer badges/certificates

    • Offer Bounties

    • Major League Hacking Interships

      • Start end of May.
      • Need to sign up by end of March
      • Must have sponsors to guide students and hold office hours
      • We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors
      • To use MLH, We need BoD (Board of Directors) approval

  • Need work items clearly identified and easily understood

    • Documentation -- We need build instructions, readmes, etc

      • Need someone replicate the FPGA/OpenBMC load from scratch
        • Then document the process for others to follow so they can replicate the results
          • Build all pieces -- Core, peripherals, OpenBMC,etc
        • Toshaan to take a crack at this now

    • Need official OpenBMC project and a makefile, bitbake/etc

    • Need the project broken down into manageable pieces

  • It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.

    • I did see an offer of help for a logo. I will follow up later. TBD

Goals -- Need timelines on these -- WIP

  • Tasks defined and project broken down
  • Able to generate a bitstream for an FPGA using fully open source toolchain.
  • Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
  • Someone seriously starting to do a real (non-development) LibreBMC deployment.
  • Fully functional Gateware and OpenBMC code stack for AC922
  • Determine the performance/size

Next Meeting

{{< localdatetime date="2022-06-14" time="10:00" >}}