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71 lines
834 B
Markdown
71 lines
834 B
Markdown
3 years ago
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## Directory Structure
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```
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src/vhdl
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clib (low-level components)
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ibm (std_ulogic)
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support (power_logic subtype)
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tri (latches and arrays)
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work (macros)
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```
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```
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build
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a2x (project)
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ip_cache (empty until project built)
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ip_repo (empty until IP built/copied)
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ip_user (IP macros to be built)
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tcl (build scripts)
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xdc (constraints)
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```
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```
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fpga
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tcl
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```
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```
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doc
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core user guide, etc.
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```
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## Build Process
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### IP
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IP is created in ip_user and copied to ip_repo for use in top level bd.
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See build/ip_user/xxx/readme.md.
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Core:
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```
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a2x_axi
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```
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Simple card components:
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```
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a2x_axi_reg
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a2x_dbug
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a2x_reset
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```
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Help Vivado attach to VIO correctly:
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```
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reverserator_3
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reverserator_4
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reverserator_32
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reverserator_64
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```
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### Project
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See build/a2x/readme.md.
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1. create project
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2. synth/implement
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