From 3f6663020c85103a11cdb107104249892bcecb49 Mon Sep 17 00:00:00 2001
From: wtf <52765606+openpowerwtf@users.noreply.ggithub.com>
Date: Wed, 8 Sep 2021 08:21:16 -0500
Subject: [PATCH] init
---
.gitattributes | 2 +
LICENSE | 33 +
README.md | 70 +
readme.md | 69 +
rel/doc/A2O_UM.pdf | 37517 ++++++++++++++++++++++++++++++++++
rel/doc/PowerISA_V2.07B.pdf | Bin 0 -> 8605169 bytes
rel/doc/a2_build_video.md | 3 +
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create mode 100644 readme.md
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create mode 100644 rel/doc/a2_build_video.md
diff --git a/.gitattributes b/.gitattributes
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+# Help GitHub correctly report the project language
+*.v linguist-language=Verilog
diff --git a/LICENSE b/LICENSE
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+© IBM Corp. 2020
+Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
+repository except in compliance with the License as modified.
+You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+
+Modified Terms:
+
+ 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
+ the work of authorship in physical form.
+
+ 2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
+ from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
+ under the terms and conditions of the EULA.
+
+Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
+"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
+governing permissions and limitations under the License.
+
+Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
+ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
+ISA) here: https://openpowerfoundation.org.
+
+Brief explanation of modifications:
+
+Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
+it unambiguously permits a user to make and use the physical chip.
+
+Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
+and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
+licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received
+under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
+licenses for the specific Power ISA Core are granted under this modified Apache license.
+
diff --git a/README.md b/README.md
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+# A2O
+
+## The Project
+This is the release of the A2O POWER processor core RTL and associated FPGA implementation (using ADM-PCIE-9V3 FPGA).
+
+See [Project Info](rel/readme.md) for details.
+
+## The Core
+The [A2O core](rel/doc/A2O_UM.pdf) was created to optimize single-thread performance, and targeted 3+ GHz in 45nm technology.
+
+It is a 27 FO4 implementation, with an out-of-order pipeline supporting 1 or 2 threads. It fully supports Power ISA 2.07 using Book III-E.
+The core was also designed to support pluggable implementations of MMU and AXU logic macros.
+This includes elimination of the MMU and using ERAT-only mode for translation/protection.
+
+## The History
+
+The A2O design was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution
+(register renaming, reservation stations, completion buffer) and a store queue.
+
+The A2L2 external interface is largely the same for the two cores.
+
+## FPGA Implementation Notes
+
+1. There are lots of knobs available for tweaking generation parameters. Very little experimentation was done to test whether they work, or the effects on area, etc.
+2. Only single-thread generation has been done so far. The FPGA in use has very high utilization with one thread.
+3. A2I used clk_1x and clk_2x (for some of the special arrays), but A2O also uses clk_4x. This (and possibly along with the area congestion) led to changing the clk_1x to 50MHz to lessen timing pressure
+(both setup and hold misses).
+
+### Technology Scaling
+
+A comparison of the design in original technology and scaled to 7nm (SMT2, fixed-point, no MMU):
+
+| |Freq |Pwr |Freq Sort|Pwr Sort|Area |Vdd |
+|-----:|---------|-------|---------|--------|---------|-------|
+|45nm |2.30 GHz |1.49 W | | |4.90 mm2 |0.97 V |
+| 7nm |3.90 GHz |0.79 W |4.17 GHz |0.85 W |0.31 mm2 |1.1 V |
+| 7nm |3.75 GHz |0.63 W |4.03 GHz |0.67 W |0.31 mm2 |1.0 V |
+| 7nm |3.55 GHz |0.49 W |3.87 GHz |0.52 W |0.31 mm2 |0.9 V |
+| 7nm |3.07 GHz |0.32 W |3.60 GHz |0.38 W |0.31 mm2 |0.8 V |
+| 7nm |2.40 GHz |0.20 W |3.00 GHz |0.25 W |0.31 mm2 |0.7 V |
+
+These estimates are based on a semicustom design in representative foundry processes (IBM 45nm/Samsung 7nm).
+
+### Compliancy
+
+The A2O core is compliant to Power ISA 2.07 and will need updates to be compliant with either version 3.0c or 3.1.
+Power ISA 3.0c and 3.1 are the two Power ISA versions contributed to OpenPOWER Foundation by IBM. Changes will include:
+
+* radix translation
+* op updates, to eliminate noncompliant ones and add missing ones required for a given compliancy level
+* various 'mode' and other changes to meet the open specification targeted compliancy level (III-E needs to be changed to III)
+
+## Miscellaneous
+
+1. A2O was not released as a product; the documentation was derived from A2I but is *much* less complete than the A2I version.
+The documentation has been edited and updated where possible, but undoubtedly, there
+remain errors vis a vis the RTL (especially likely in implementation-specific SPRs).
+
+ Please use 'issues' to report errors.
+
+## Errata
+
+1. There is a problem that is being circumvented by setting LSUCR0.DFWD=1, AND limiting the store queue size (currently at 4). While it appears
+to be directly related to forwarding (L1 DC hit returns 0's instead of data), the store queue size also had to be limited.
+
+ Not debugged at this time; could be related to:
+ 1. bad generation parm
+ 2. bad edit for source updates related to compiling for Vivado
+ 3. ???
+
diff --git a/readme.md b/readme.md
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+## Directory Structure
+
+```
+src/verilog/trilib
+src/verilog/work
+src/vhdl
+```
+
+```
+build
+ bd (project)
+ ip_cache (empty until project built)
+ ip_repo (empty until IP built/copied)
+ ip_user (IP macros to be built)
+ tcl (build scripts)
+```
+
+```
+fpga
+ tcl
+```
+
+```
+doc
+ core user guide, etc.
+```
+
+
+## Build Process
+
+### IP
+
+IP is created in ip_user and copied to ip_repo for use in top level bd.
+
+See build/ip_user/xxx/readme.md.
+
+Core:
+
+```
+a2o_core
+```
+
+Core-AXI:
+```
+a2l2_axi
+```
+
+Simple card components:
+
+```
+a2o_axi_reg
+a2o_dbug
+```
+
+Help Vivado attach to VIO correctly:
+
+```
+reverserator_3
+reverserator_4
+reverserator_64
+```
+
+### Project
+
+See build/bd/readme.md.
+
+1. create project
+2. synth/implement
+
diff --git a/rel/doc/A2O_UM.pdf b/rel/doc/A2O_UM.pdf
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--- /dev/null
+++ b/rel/doc/A2O_UM.pdf
@@ -0,0 +1,37517 @@
+%PDF-1.4
%
+1 0 obj
<>>>
endobj
2 0 obj
<>stream
+
+
+
+
+ 2020-09-13T14:58:29-05:00
+ 2020-09-13T14:56:07Z
+ 2020-09-13T14:58:29-05:00
+ FrameMaker 2019
+ uuid:66b7fb7e-db9e-4dd0-81c5-f573b0904364
+ uuid:a02094a8-ca2b-4a70-883e-cb62957f0337
+ application/pdf
+
+
+ BillFlynn
+
+
+
+
+ A2.pdf
+
+
+ Adobe PDF Library 15.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endstream
endobj
14 0 obj
<>
endobj
15 0 obj
<>
endobj
16 0 obj
<>
endobj
3 0 obj
<>
endobj
20 0 obj
<>
endobj
21 0 obj
<>
endobj
22 0 obj
<>
endobj
23 0 obj
<>
endobj
24 0 obj
<>
endobj
25 0 obj
<>
endobj
51 0 obj
<>
endobj
52 0 obj
<>
endobj
53 0 obj
<>
endobj
54 0 obj
<>
endobj
55 0 obj
<>
endobj
56 0 obj
<>
endobj
82 0 obj
<>
endobj
83 0 obj
<>
endobj
84 0 obj
<>
endobj
85 0 obj
<>
endobj
86 0 obj
<>
endobj
87 0 obj
<>
endobj
88 0 obj
<>
endobj
119 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
120 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
121 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
122 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
123 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
124 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
125 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
126 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
127 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
128 0 obj
<>/ExtGState<>/Font<>/ProcSet[/PDF/Text]>>/TrimBox[0.0 0.0 612.0 792.0]/Type/Page>>
endobj
156 0 obj
[158 0 R]
endobj
157 0 obj
<>stream
+HW]E}_1vd B7^CnS]=A"jΩ5>.URU,#[O^>f]?^`~w?==\֧v JI_zy$=iU"}|4u]^gn;>]J
0r2krQiz~\|˛]7UǔUΆd\[uoj!oNoNurВS_n?o7!tBG֮_yԜ53i\njF~fB):&U.Bnz2G/%AofI(N^na<#='to
k"
LF7w#h:P; N(TNԝ9f\M+ɌscԶc5"mb;!M>Bj)uj'9<@˶(D|v]W!sNrӞK?5w#DjQ[>/:q]VNYU#щ"__?VfXc0qPv-VU¸deaV iƛj*%"huV,2/&WP_*MW
+
!f+"YCÜ{-r>x_Wabپh5ʃ ߢK|E.B
xMKG{gXm>(K`}=7_5q2 6XXmA
T