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336 lines
14 KiB
Verilog
336 lines
14 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Tri Array Wrapper
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module tri_128x16_1r1w_1(
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vdd,
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vcs,
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gnd,
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nclk,
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rd_act,
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wr_act,
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lcb_d_mode_dc,
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lcb_clkoff_dc_b,
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lcb_mpw1_dc_b,
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lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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func_scan_in,
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func_scan_out,
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lcb_sg_0,
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lcb_sl_thold_0_b,
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lcb_time_sl_thold_0,
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lcb_abst_sl_thold_0,
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lcb_ary_nsl_thold_0,
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lcb_repr_sl_thold_0,
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time_scan_in,
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time_scan_out,
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abst_scan_in,
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abst_scan_out,
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repr_scan_in,
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repr_scan_out,
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abist_di,
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abist_bw_odd,
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abist_bw_even,
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abist_wr_adr,
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wr_abst_act,
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abist_rd0_adr,
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rd0_abst_act,
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tc_lbist_ary_wrt_thru_dc,
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abist_ena_1,
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abist_g8t_rd0_comp_ena,
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abist_raw_dc_b,
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obs0_abist_cmp,
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lcb_bolt_sl_thold_0,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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bw,
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wr_adr,
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rd_adr,
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di,
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do
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);
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parameter addressable_ports = 128; // number of addressable register in this array
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parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
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parameter port_bitwidth = 16; // bitwidth of ports
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parameter ways = 1; // number of ways
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// POWER PINS
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inout vdd;
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inout vcs;
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inout gnd;
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input [0:`NCLK_WIDTH-1] nclk;
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input rd_act;
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input wr_act;
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// DC TEST PINS
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input lcb_d_mode_dc;
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input lcb_clkoff_dc_b;
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input [0:4] lcb_mpw1_dc_b;
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input lcb_mpw2_dc_b;
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input [0:4] lcb_delay_lclkr_dc;
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input ccflush_dc;
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input scan_dis_dc_b;
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input scan_diag_dc;
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input func_scan_in;
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output func_scan_out;
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input lcb_sg_0;
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input lcb_sl_thold_0_b;
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input lcb_time_sl_thold_0;
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input lcb_abst_sl_thold_0;
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input lcb_ary_nsl_thold_0;
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input lcb_repr_sl_thold_0;
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input time_scan_in;
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output time_scan_out;
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input abst_scan_in;
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output abst_scan_out;
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input repr_scan_in;
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output repr_scan_out;
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input [0:3] abist_di;
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input abist_bw_odd;
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input abist_bw_even;
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input [0:6] abist_wr_adr;
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input wr_abst_act;
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input [0:6] abist_rd0_adr;
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input rd0_abst_act;
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input tc_lbist_ary_wrt_thru_dc;
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input abist_ena_1;
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input abist_g8t_rd0_comp_ena;
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input abist_raw_dc_b;
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input [0:3] obs0_abist_cmp;
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// BOLT-ON
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input lcb_bolt_sl_thold_0;
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input pc_bo_enable_2; // general bolt-on enable
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input pc_bo_reset; // reset
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input pc_bo_unload; // unload sticky bits
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input pc_bo_repair; // execute sticky bit decode
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input pc_bo_shdata; // shift data for timing write and diag loop
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input pc_bo_select; // select for mask and hier writes
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output bo_pc_failout; // fail/no-fix reg
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output bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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input [0:15] bw;
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input [0:6] wr_adr;
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input [0:6] rd_adr;
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input [0:15] di;
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output [0:15] do;
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// tri_128x16_1r1w_1
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// Configuration Statement for NCsim
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//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;
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wire clk;
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wire clk2x;
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wire [0:8] b0addra;
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wire [0:8] b0addrb;
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wire wea;
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wire web;
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wire wren_a;
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// Latches
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reg reset_q;
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reg gate_fq;
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wire gate_d;
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wire [0:35] r_data_out_1_d;
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reg [0:35] r_data_out_1_fq;
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wire [0:35] w_data_in_0;
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wire [0:35] r_data_out_0_bram;
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wire [0:35] r_data_out_1_bram;
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wire toggle_d;
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reg toggle_q;
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wire toggle2x_d;
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reg toggle2x_q;
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(* analysis_not_referenced="true" *)
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wire unused;
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assign clk = nclk[0];
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assign clk2x = nclk[2];
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always @(posedge clk)
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begin: rlatch
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reset_q <= nclk[1];
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end
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//
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// NEW clk2x gate logic start
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//
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always @(posedge nclk[0])
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begin: tlatch
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if (reset_q == 1'b1)
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toggle_q <= 1'b1;
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else
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toggle_q <= toggle_d;
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end
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always @(posedge nclk[2])
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begin: flatch
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toggle2x_q <= toggle2x_d;
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gate_fq <= gate_d;
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r_data_out_1_fq <= r_data_out_1_d;
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end
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assign toggle_d = (~toggle_q);
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assign toggle2x_d = toggle_q;
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// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
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//gate_d <= toggle_q xor toggle2x_q;
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// if you want the first half do the following
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assign gate_d = (~(toggle_q ^ toggle2x_q));
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assign b0addra[2:8] = wr_adr;
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assign b0addrb[2:8] = rd_adr;
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// Unused Address Bits
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assign b0addra[0:1] = 2'b00;
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assign b0addrb[0:1] = 2'b00;
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// port a is a read-modify-write port
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assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 :
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1'b0;
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assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk
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assign web = 1'b0;
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assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] :
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r_data_out_0_bram[0];
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assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] :
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r_data_out_0_bram[1];
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assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] :
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r_data_out_0_bram[2];
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assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] :
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r_data_out_0_bram[3];
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assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] :
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r_data_out_0_bram[4];
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assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] :
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r_data_out_0_bram[5];
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assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] :
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r_data_out_0_bram[6];
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assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] :
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r_data_out_0_bram[7];
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assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
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r_data_out_0_bram[8];
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assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
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r_data_out_0_bram[9];
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assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] :
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r_data_out_0_bram[10];
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assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] :
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r_data_out_0_bram[11];
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assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] :
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r_data_out_0_bram[12];
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assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] :
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r_data_out_0_bram[13];
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assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
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r_data_out_0_bram[14];
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assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
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r_data_out_0_bram[15];
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assign w_data_in_0[16:35] = {20{1'b0}};
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assign r_data_out_1_d = r_data_out_1_bram;
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RAMB16_S36_S36
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#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
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bram0a(
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.CLKA(clk2x),
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.CLKB(clk2x),
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.SSRA(reset_q),
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.SSRB(reset_q),
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.ADDRA(b0addra),
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.ADDRB(b0addrb),
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.DIA(w_data_in_0[0:31]),
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.DIB({32{1'b0}}),
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.DOA(r_data_out_0_bram[0:31]),
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.DOB(r_data_out_1_bram[0:31]),
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.DOPA(r_data_out_0_bram[32:35]),
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.DOPB(r_data_out_1_bram[32:35]),
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.DIPA(w_data_in_0[32:35]),
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.DIPB(4'b0000),
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.ENA(1'b1),
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.ENB(1'b1),
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.WEA(wea),
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.WEB(web)
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);
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assign do = r_data_out_1_fq[0:15];
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assign func_scan_out = func_scan_in;
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assign time_scan_out = time_scan_in;
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assign abst_scan_out = abst_scan_in;
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assign repr_scan_out = repr_scan_in;
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assign bo_pc_failout = 1'b0;
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assign bo_pc_diagloop = 1'b0;
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assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
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lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
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abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
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tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
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lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
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pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]};
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endmodule
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