From 03f9d7a97e8bbec46b2cbd3386774295e48a8387 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Thu, 11 Jun 2020 14:57:30 +1000 Subject: [PATCH] tests/xics: Fix assumption that interrupts happen immediately Currently the test writes to the XICS and then checks that the expected interrupt has happened. This turns into a stbcix instruction followed immediately by a load from the variable that indicates whether an interrupt has happened. It is possible for it to take a few cycles for the store to reach the XICS and the interrupt request signal to come back to the core, particularly with improvements to the load/store unit and dcache. This therefore adds a delay between storing to the XICS and checking for the occurrence of an interrupt, so as to give the signals time to propagate. The delay loop does an arbitrary 10 iterations, and each iteration does two loads and one store to (cacheable) memory. Signed-off-by: Paul Mackerras --- tests/test_xics.bin | Bin 12384 -> 12384 bytes tests/xics/xics.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/tests/test_xics.bin b/tests/test_xics.bin index 6dd993ce0af3fd582dcb3d1914ca85dcf8b48a1b..327f98f64e2bb62ea1ca48f98456b1dae59799f6 100755 GIT binary patch literal 12384 zcmeHMeP~9}x?1N^Bop^0P9~4sBwE9SP_d8El z_Os$ND{N?x_u%Q?d+xdCoZs)n)4Qz-uwh4VU1x-yG;m~qBLf^6;K%?+1~@XnkpYejaAbia z3mjSC$O1rNF!tn3n?cQea++#bPs_36+eU(8)q43!N->)0Pk&s9G?MObp!KasKKNbYK{^nEt@br^K+|q)!1HQ^Iwes!yffG0x{j#AxQ?Nj1)xhm3#vQ3B(Jd|Ce8I+<_SsKMAZu)*WY{ciy) zQ7}#9X@3fsgm}91&`89)R$}-%>E1s`8^=+fhd#?rOBw5*hyHa-dkXEpmHqO!E%?^p zo8!0o-XVP>FRfPJN99=dvrX1dpdOaKAGP>m-@}$R`~IeEo8Q&oJ1Oq;ebMAQn08k9 z{*oNazW-cX;_h|SuS1_@zm>8w?)NNh_B}7#W#62yO57~#K+cge+`;^fq9ylAW$sm( zdtMJTpw(2Bx7D{i7|;7w^`a8vro1;W(Ch8 zC6hsywh$o-9OX5cpPjakk_q+!+(99_aBmC}*4INLDz7M!`u z{}rH~qNEydX`V2z1!k;|ajdFOH`kQF(b11ZUo#2+;PO7F7{R3HNehtL8~)jDPdsXLf$v_Q z5FT?4&0uf68)s}AHq)ZCE|>JN=H5%6d4&J}SiiZfi&*jeKAXasq2&8%yvIbmJO?s& zIggdkHsx5Yw(6y=&9%b=jN7#H33z#q@HvFfzCyg?FP}jay82V1&F#&YujPHM<)-Ls zq=#DheDqn)Kk~)78bf&jH{#(-F)-hw>%NCGmhSycOB?nwKCd0vp#ay7Wj#|lIvm;m z6+ES_9yPRkch9bYJ>Ljz+y2C^9(SY43Iluhk8*{jjVSw}#pUq+AK({$Fn-S{l=gH~ zw7*)>{u(u#5(N0%E^uFLS2>qz1 ziMne;knt4k&U*BH=VKwhze1;Pg^q^4U*&{2xI*XgB^@u!52DXi5MqdRx;eh1buZPfh_Sm# zcWiHLqAoMae_W~!eWt|Aag6D}EPN0{`C=a5kg~tBz_e$CmbUtI?Y0+qof{SKBm0t=r(!Y zQo?CMG{>KW%Dd3zarR|1U^8GdU^8GdU^8GdU^8GdU^8GdU^8GdU^8GdU^DQ)V?dW5 gjPR+_yw1qBENHS^xl0J6pDT6jlOLj~IekM&zO2#spjdc^ku7gA-g@pl< z)7Z7c`hiUOkV(Lxg^;vc1ZbPW2eejNI;YhT-G)@uQo$H0fqw9xO$wu|c1(BoJJ0vR z<0W+KG|7|jlV0w<=ltHe=l8qky?38O6l)?H44hdo*ehson-GJ6G3UVu4c)cFzs(sN z40LL-2$9}My#t)G@kNd!p+ZV!>6i9HMj}f&M zdhs9h`Qrk$DNvgNwJA`W0<|enn*y~drgMvNU+5Iu2wWPtG;nF)(!izRO8}c5bGpL7 zr-4s1miz4EG5gr2k*}Gme|v0Q15s^KqnZHPEc>nNFdw$$-(dOP;asP2kDPkQ z+|&EjTspbyIUk;r^Ks0LrNuabxZXrYO+crb-jiSH3a>2-cGz>f2eWLz@1 z5kse7=(A$f&J#oNXHG;$L)SmWhEw46vgfKdRP`ckF%SJg1Q(LuQ%*-#9?ZQNT|&b? zqLZr@(Xe4;hNG2q#8*d=dgf3r^+4Q)53&={gO^2AqsE4XG_bOL=1NqjsXm<=dvy|h z<6_uohhC3jPRU7&l@eKV;@Y5i+{^Vr##9i$2{mwx62#{4L92|sr%RAFOU$9viCa4D*6zY> zPuGI07xjE%rJcjWwph&Jl+?h=;i$B|0uJT#aEM4hb9+PeEgZH;o8oZ5hG|lM$ssQ0 z=ir=&L#r(obNE~SyV-B$a7o&ZfkVrubJyVw>1PhNRNunku(T--=WUo?<(C||?&hw8 z-cX17Md{)6W_RZ-b&Tt*bx8tOLas}1-_>he*6o1wvtGYfeT!aQ(x&tpwP9M7AG~*#$!8+!m+w8+ZIP{h z=Ue-4*kUr58#0!a%N1$+4Y;&Ib9E0YE)&wv_N?k#xEz%>#pQwx6H)%pvG$?t|9qUaP>N|nd#IhqH3WOwZnRze7g0%b)nffv6jCmom&?_mA3bw<)`4Fw2aHT*eU&N z|CQ=nwEUK|DJ=(VnAOV9S`O*pQ`75=)qszF-{)A1Ee7YFESa181!?;Lx%=kH{j~IR z?l)B5lKTN^Q@NkBVfHBh=ct38Pwrm_THfdP$6ob}n)~af0ipr{w_YqH~yU%l|`+FYR(coF@ zxVTw8$6mtTA$0x6(dVplVywxr`M$jzjNWkMdG~?i7U-w!m!v)PUUPJ*H3r5L%J;_= z(X8q-Z;VIfnEzMgB5yy%2ciaY;k+vGO*ZDNiG(&hZvHnipvBc4(%&y%(E$ChIcgE^`7 zFpnQwmh3aIkF9Ozx!+v%y194R>wOpcvW82o95J4dv2?oLSMv|C0qfGpx?SuJ){jcx znDZU%+kBbO%|Au?d(PxaudP}m_eC0Vx{7B2-#e$}HEM6PMUFM_#=;~1Ti%4k4%o1( z<@kNz3}_ZgzZR|g*rF9SHcA(BzYD&k*90of_eD)_Pi%Si5onRZv+jO+3a(9D*ArWp z)Nx%3d!+kedF}plEXRBv-?y0mJ1ZjihS-@Adkq(2q&5cU-Lv1}BJ)|y`8-t{amj0W z{?s>r@R_xt_6bXtza0%#Ma^#w-sc)Kzl-vooA(^9o2+4UAFsgyX#0`1{`h%?d49dV z8PC|CnEUk5h83nJ;Lwn`i)A2n?fQ|~hPr~gw(j1xYxmYV+jzBY{B?8O0jQ4N6Z{9q zQ@++V>_MsB_w2LWa=fo$$Nog#P1Q9zJT03#wlebDn_AotFVx|KM&_Ztu!%}SKCNnz zX4+5#wC3+ZJTCo=<9?gP_9(^%&Q93c&{9i<{srHQEfv&UhL038jvwt1{P+#PJUGs7 zoFlO5rX`QthyE{ZxFfLr)`DYY#&Mp7Z9iIivfM|$S4xkR9CZ#mj%k?NSJD3c3i5q8 zb>%OY%^Y~%k8oDs6yhwe4PP_tSYJ_R;vFMM_QR<%pAHwO)7e`>+(t`n6?KTmVIAET zOdWh9p9taNSQbo=#5BU(0nAHTAu=4NnR7hkI=tZJvU@UZuJAj07FN(YGuJ;~x>)9W z2yoVCKdx)c39$ryK3MnT(pGsV<~^*9u#Ci{IR+o|t?A<1Le%HoCXQpTfsI=}_*w&J zo6Xh%TPJMHj}OLe$2n+;SB-HP=QwQbXsN~2`k3~lsbw?RVrA~~JPyeFmU;M+;!#wf zs6bJHq5?$)iV74JC@N4?pr}AmfuaIM1&Rv%_X=#6KML^A7JS6zST?j@b@J{xf2+Tk PH_gZ&CI0%Qdm;Y<^ycm; diff --git a/tests/xics/xics.c b/tests/xics/xics.c index 2ff4c54..a2db3a5 100644 --- a/tests/xics/xics.c +++ b/tests/xics/xics.c @@ -9,6 +9,14 @@ #undef DEBUG //#define DEBUG 1 +void delay(void) +{ + static volatile int i; + + for (i = 0; i < 10; ++i) + ; +} + void print_number(unsigned int i) // only for i = 0-999 { unsigned int j, k, m; @@ -148,14 +156,17 @@ int xics_test_0(void) xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt // still masked, so shouldn't happen yet + delay(); assert(isrs_run == 0); // unmask IPI only xics_write8(XICS_XIRR, 0x40); + delay(); assert(isrs_run == ISR_IPI); // unmask UART xics_write8(XICS_XIRR, 0xc0); + delay(); assert(isrs_run == (ISR_IPI | ISR_UART)); // cleanup @@ -174,12 +185,14 @@ int xics_test_1(void) xics_write8(XICS_XIRR, 0xff); // allow all interrupts // should be none pending + delay(); assert(isrs_run == 0); // trigger both potato_uart_irq_en(); // cause 0x500 interrupt xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt + delay(); assert(isrs_run == (ISR_IPI | ISR_UART)); // cleanup @@ -208,9 +221,11 @@ int xics_test_2(void) // trigger an IPI xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt + delay(); assert(isrs_run == 0); mtmsrd(0x9000000000008003); // EE on + delay(); assert(isrs_run == ISR_IPI); // cleanup