From 80cf489e969fa49d455fa38a97177f64ba333b90 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Tue, 8 Dec 2020 19:18:34 +1100 Subject: [PATCH] Add LOG_LENGTH to top-generic.vhdl The other top level files allow LOG_LENGTH to be configured. Signed-off-by: Anton Blanchard --- fpga/top-generic.vhdl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl index 2ad0dd3..d5219ff 100644 --- a/fpga/top-generic.vhdl +++ b/fpga/top-generic.vhdl @@ -12,6 +12,7 @@ entity toplevel is CLK_INPUT : positive := 100000000; CLK_FREQUENCY : positive := 100000000; HAS_FPU : boolean := true; + LOG_LENGTH : natural := 512; DISABLE_FLATTEN_CORE : boolean := false; UART_IS_16550 : boolean := true ); @@ -70,6 +71,7 @@ begin SIM => false, CLK_FREQ => CLK_FREQUENCY, HAS_FPU => HAS_FPU, + LOG_LENGTH => LOG_LENGTH, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, UART0_IS_16550 => UART_IS_16550 )