diff --git a/writeback.vhdl b/writeback.vhdl
index 65da537..516e6ba 100644
--- a/writeback.vhdl
+++ b/writeback.vhdl
@@ -77,10 +77,10 @@ begin
     writeback_1: process(all)
         variable v    : reg_type;
         variable f    : WritebackToFetch1Type;
-	variable cf: std_ulogic_vector(3 downto 0);
+        variable cf: std_ulogic_vector(3 downto 0);
         variable zero : std_ulogic;
         variable sign : std_ulogic;
-	variable scf  : std_ulogic_vector(3 downto 0);
+        variable scf  : std_ulogic_vector(3 downto 0);
         variable vec  : integer range 0 to 16#fff#;
         variable srr1 : std_ulogic_vector(15 downto 0);
         variable intr : std_ulogic;
@@ -228,7 +228,7 @@ begin
             f.mode_32bit := e_in.redir_mode(0);
         end if;
 
-	f_out <= f;
+        f_out <= f;
         flush_out <= f_out.redirect;
 
         rin <= v;