From 12efb51bcc7024ba78175ad7cbfa23837ad2ac89 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 9 Aug 2021 13:49:25 +1000 Subject: [PATCH] liteeth: Update yaml config csr_data_width is no longer required. Add ntxslots and nrxslots parameters but set them to the default value. Signed-off-by: Anton Blanchard --- liteeth/gen-src/arty.yml | 3 ++- liteeth/gen-src/nexys-video.yml | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/liteeth/gen-src/arty.yml b/liteeth/gen-src/arty.yml index 7200a70..d092c0a 100644 --- a/liteeth/gen-src/arty.yml +++ b/liteeth/gen-src/arty.yml @@ -8,8 +8,9 @@ vendor: xilinx clk_freq: 100e6 core: wishbone endianness: little +ntxslots: 2 +nrxslots: 2 soc: mem_map: ethmac: 0x00010000 - csr_data_width: 32 diff --git a/liteeth/gen-src/nexys-video.yml b/liteeth/gen-src/nexys-video.yml index 38a207c..d7253ea 100644 --- a/liteeth/gen-src/nexys-video.yml +++ b/liteeth/gen-src/nexys-video.yml @@ -8,8 +8,9 @@ vendor: xilinx clk_freq: 125e6 core: wishbone endianness: little +ntxslots: 2 +nrxslots: 2 soc: mem_map: ethmac: 0x00010000 - csr_data_width: 32