From 3c2739e10af00199de3c206a18dbae07489c41c9 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 8 Jul 2020 16:13:27 +1000 Subject: [PATCH 1/4] spi: Send dummy clocks at boot When using an FPGA which routes the SPI clock via STARTUPE2 as is done on the Nexys Video (or optionally on Arty), the HW needs at least 3 beats of that clock to complete the switch from the internal config clock to the one we provide. This works around it by having the SPI controller send 8 dummy clocks at boot time with CS held high. Without this, flash identification will fail those boards Signed-off-by: Benjamin Herrenschmidt --- spi_flash_ctrl.vhdl | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/spi_flash_ctrl.vhdl b/spi_flash_ctrl.vhdl index bc41d08..095bc74 100644 --- a/spi_flash_ctrl.vhdl +++ b/spi_flash_ctrl.vhdl @@ -11,6 +11,9 @@ entity spi_flash_ctrl is DEF_CLK_DIV : natural := 2; -- Clock divider SCK = CLK/((CLK_DIV+1)*2) DEF_QUAD_READ : boolean := false; -- Use quad read with 8 clk dummy + -- Dummy clocks after boot + BOOT_CLOCKS : boolean := true; -- Send 8 dummy clocks after boot + -- Number of data lines (1=MISO/MOSI, otherwise 2 or 4) DATA_LINES : positive := 1 ); @@ -103,7 +106,7 @@ architecture rtl of spi_flash_ctrl is constant DEFAULT_CS_TIMEOUT : integer := 32; -- Automatic mode state - type auto_state_t is (AUTO_IDLE, AUTO_CS_ON, AUTO_CMD, + type auto_state_t is (AUTO_BOOT, AUTO_IDLE, AUTO_CS_ON, AUTO_CMD, AUTO_ADR0, AUTO_ADR1, AUTO_ADR2, AUTO_ADR3, AUTO_DUMMY, AUTO_DAT0, AUTO_DAT1, AUTO_DAT2, AUTO_DAT3, @@ -125,7 +128,7 @@ architecture rtl of spi_flash_ctrl is -- Automatic mode latches signal auto_data : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0'); signal auto_cnt : integer range 0 to 63 := 0; - signal auto_state : auto_state_t := AUTO_IDLE; + signal auto_state : auto_state_t := AUTO_BOOT; signal auto_last_addr : std_ulogic_vector(31 downto 0); begin @@ -176,7 +179,7 @@ begin -- in practice. -- if cmd_valid = '1' and cmd_ready = '1' then - pending_read <= '1'; + pending_read <= not wb_req.we; elsif bus_idle = '1' then pending_read <= '0'; end if; @@ -396,21 +399,29 @@ begin if rst = '1' or ctrl_reset = '1' then auto_cs <= '0'; auto_cnt_next <= 0; - auto_next <= AUTO_IDLE; + auto_next <= AUTO_BOOT; else -- Run counter if auto_cnt /= 0 then auto_cnt_next <= auto_cnt - 1; end if; - -- Automatic CS is set whenever state isn't IDLE or RECOVERY - if auto_state /= AUTO_IDLE and - auto_state /= AUTO_RECOVERY then + -- Automatic CS is set whenever state isn't IDLE or RECOVERY or BOOT + if auto_state /= AUTO_IDLE and + auto_state /= AUTO_RECOVERY and + auto_state /= AUTO_BOOT then auto_cs <= '1'; end if; -- State machine case auto_state is + when AUTO_BOOT => + if BOOT_CLOCKS then + auto_cmd_valid <= '1'; + if cmd_ready = '1' then + auto_next <= AUTO_IDLE; + end if; + end if; when AUTO_IDLE => -- Access to the memory map only when manual CS isn't set if wb_map_valid = '1' and ctrl_cs = '0' then @@ -599,3 +610,4 @@ begin end process; end architecture; + From 5449d842dd461b73bdaa855a8b49fcc60e3ee5eb Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 25 Jun 2020 14:05:03 +1000 Subject: [PATCH 2/4] nexys_video: Fix nexys-video build Signed-off-by: Benjamin Herrenschmidt --- fpga/top-nexys-video.vhdl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index ac760a1..3e559ba 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -20,7 +20,7 @@ entity toplevel is SPI_FLASH_OFFSET : integer := 10485760; SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_QUAD : boolean := true; - UART_IS_16550 : boolean := true; + UART_IS_16550 : boolean := true ); port( ext_clk : in std_ulogic; @@ -151,8 +151,8 @@ begin wb_dram_out => wb_dram_out, wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, - wb_ext_is_dram_csr => wb_dram_is_csr, - wb_ext_is_dram_init => wb_dram_is_init, + wb_ext_is_dram_csr => wb_ext_is_dram_csr, + wb_ext_is_dram_init => wb_ext_is_dram_init, alt_reset => core_alt_reset ); From a5fa92f71b9f78cd76e68fd201f9fc3a543bf861 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 26 Jun 2020 23:34:14 +1000 Subject: [PATCH 3/4] fpga: nexys-video: Wire up core_alt_reset It looks like we left it dangling Signed-off-by: Benjamin Herrenschmidt --- fpga/top-nexys-video.vhdl | 1 + 1 file changed, 1 insertion(+) diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 3e559ba..5395ff6 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -264,6 +264,7 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => soc_rst, + core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, From b0241d9f2de3dc23ed53903b296f30aee34bb5e4 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 8 Jul 2020 14:00:27 +1000 Subject: [PATCH 4/4] corefile/nexys_video: Parameter fixes This fixes up a few issues with parameters: Only arty has "has_uart1" since we haven't added plumbing for a second UART anywhere else. Also "uart_is_16550" was mixing on one of the nexys_video targets, and nexys_video toplevel was missing LOG_LENGTH. Signed-off-by: Benjamin Herrenschmidt --- fpga/top-nexys-video.vhdl | 2 ++ microwatt.core | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 5395ff6..15fa176 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -20,6 +20,7 @@ entity toplevel is SPI_FLASH_OFFSET : integer := 10485760; SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 2048; UART_IS_16550 : boolean := true ); port( @@ -128,6 +129,7 @@ begin SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, UART0_IS_16550 => UART_IS_16550 ) port map ( diff --git a/microwatt.core b/microwatt.core index 046020d..15786fe 100644 --- a/microwatt.core +++ b/microwatt.core @@ -118,7 +118,6 @@ targets: - disable_flatten_core - log_length=2048 - uart_is_16550 - - has_uart1 tools: vivado: {part : xc7a100tcsg324-1} toplevel : toplevel @@ -135,7 +134,6 @@ targets: - spi_flash_offset=10485760 - log_length=2048 - uart_is_16550 - - has_uart1 tools: vivado: {part : xc7a200tsbg484-1} toplevel : toplevel @@ -151,6 +149,7 @@ targets: - no_bram - spi_flash_offset=10485760 - log_length=2048 + - uart_is_16550 generate: [litedram_nexys_video] tools: vivado: {part : xc7a200tsbg484-1} @@ -240,7 +239,6 @@ targets: - disable_flatten_core - log_length=512 - uart_is_16550 - - has_uart1 tools: vivado: {part : xc7a35tcpg236-1} toplevel : toplevel