diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 4db6aab..6147d8f 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -80,14 +80,14 @@ set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdca # PMOD header JB (high-speed, no protection resisters) ################################################################################ -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_1 }]; -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_2 }]; -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_3 }]; -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_4 }]; -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_7 }]; -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_8 }]; -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_9 }]; -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_10 }]; +set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[1] }]; +set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[2] }]; +set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jb[3] }]; +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[6] }]; +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jb[7] }]; +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[7] }]; +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[9] }]; +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[10] }]; # connection to Digilent PmodSD on JB #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 SLEW FAST PULLUP TRUE } [get_ports { sdcard_data[3] }]; @@ -103,14 +103,14 @@ set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdca # PMOD header JC (high-speed, no protection resisters) ################################################################################ -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_1 }]; -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_2 }]; -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_3 }]; -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_4 }]; -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_7 }]; -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_8 }]; -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_9 }]; -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_10 }]; +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[1] }]; +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[2] }]; +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[3] }]; +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[4] }]; +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[7] }]; +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[8] }]; +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { pmod_jc[9] }]; +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc[10] }]; ################################################################################ # PMOD header JD (standard, 200 ohm protection resisters) @@ -135,8 +135,8 @@ set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_po set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[3] }]; set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[4] }]; set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[5] }]; -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[6] }]; -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[7] }]; +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[4] }]; +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb[8] }]; set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[8] }]; set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[9] }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 PULLDOWN TRUE } [get_ports { shield_io[10] }]; @@ -552,3 +552,4 @@ set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] + diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 7171be9..75d555d 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -17,6 +17,7 @@ entity toplevel is HAS_FPU : boolean := true; HAS_BTC : boolean := true; HAS_SHORT_MULT : boolean := false; + HAS_LPC : boolean := true; USE_LITEDRAM : boolean := false; NO_BRAM : boolean := false; DISABLE_FLATTEN_CORE : boolean := false; @@ -60,6 +61,10 @@ entity toplevel is -- GPIO shield_io : inout std_ulogic_vector(44 downto 0); + -- LPC + pmod_jb : inout std_ulogic_vector(10 downto 1); + pmod_jc : inout std_ulogic_vector(10 downto 1); + -- Ethernet eth_ref_clk : out std_ulogic; eth_clocks_tx : in std_ulogic; @@ -163,6 +168,18 @@ architecture behaviour of toplevel is signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0); signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0); + -- LPC + signal lpc_data_o : std_ulogic_vector(3 downto 0); + signal lpc_data_o_reg : std_ulogic_vector(3 downto 0); + signal lpc_data_oe : std_ulogic; + signal lpc_data_i : std_ulogic_vector(3 downto 0); + signal lpc_irq_o : std_ulogic; + signal lpc_irq_oe : std_ulogic; + signal lpc_irq_i : std_ulogic; + signal lpc_frame_n : std_ulogic; + signal lpc_reset_n : std_ulogic; + signal lpc_clock : std_ulogic; + -- Fixup various memory sizes based on generics function get_bram_size return natural is begin @@ -196,6 +213,7 @@ begin HAS_FPU => HAS_FPU, HAS_BTC => HAS_BTC, HAS_SHORT_MULT => HAS_SHORT_MULT, + HAS_LPC => HAS_LPC, HAS_DRAM => USE_LITEDRAM, DRAM_SIZE => 256 * 1024 * 1024, DRAM_INIT_SIZE => PAYLOAD_SIZE, @@ -238,6 +256,17 @@ begin gpio_out => gpio_out, gpio_dir => gpio_dir, + -- LPC + lpc_data_o => lpc_data_o, + lpc_data_oe => lpc_data_oe, + lpc_data_i => lpc_data_i, + lpc_frame_n => lpc_frame_n, + lpc_reset_n => lpc_reset_n, + lpc_clock => lpc_clock, + lpc_irq_o => lpc_irq_o, + lpc_irq_oe => lpc_irq_oe, + lpc_irq_i => lpc_irq_i, + -- External interrupts ext_irq_eth => ext_irq_eth, ext_irq_sdcard => ext_irq_sdcard, @@ -263,6 +292,35 @@ begin --uart_pmod_rts_n <= '0'; + -- LPC inout/bidir pins (assignments requested by paulus) + lpc_clock <= pmod_jb(1); + pmod_jb(2) <= '0'; + + lpc_data_i(0) <= pmod_jc(1); + lpc_data_i(1) <= pmod_jc(3); + lpc_data_i(2) <= pmod_jc(7); + lpc_data_i(3) <= pmod_jc(9); + lpc_data_o_reg <= lpc_data_o; + + pmod_jc(1) <= lpc_data_o_reg(0) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(2) <= '0'; + pmod_jc(3) <= lpc_data_o_reg(1) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(4) <= '0'; + pmod_jc(7) <= lpc_data_o_reg(2) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(8) <= '0'; + pmod_jc(9) <= lpc_data_o_reg(3) when lpc_data_oe = '1' and ext_rst_n = '1' else 'Z'; + pmod_jc(10) <= '0'; + + lpc_reset_n <= pmod_jb(3); + pmod_jb(4) <= 'Z'; -- actually comes out on 40-pin connector + lpc_frame_n <= pmod_jb(7); + pmod_jb(7) <= 'Z'; + pmod_jb(8) <= 'Z'; -- actually comes out on 40-pin connector + pmod_jb(9) <= lpc_irq_o when lpc_irq_oe = '1' and ext_rst_n = '1' else 'Z'; + lpc_irq_i <= pmod_jb(9); + pmod_jb(10) <= lpc_data_oe; + + -- SPI Flash -- -- Note: Unlike many other boards, the SPI flash on the Arty has @@ -699,8 +757,8 @@ begin gpio_in(3) <= shield_io(3); gpio_in(4) <= shield_io(4); gpio_in(5) <= shield_io(5); - gpio_in(6) <= shield_io(6); - gpio_in(7) <= shield_io(7); + gpio_in(6) <= shield_io(6); -- actually comes out on JB4 + gpio_in(7) <= shield_io(7); -- actually comes out on JB8 gpio_in(8) <= shield_io(8); gpio_in(9) <= shield_io(9); gpio_in(10) <= shield_io(10); diff --git a/hello_world/hello_world.bin b/hello_world/hello_world.bin index e4b14ca..d1bf303 100755 Binary files a/hello_world/hello_world.bin and b/hello_world/hello_world.bin differ diff --git a/hello_world/hello_world.elf b/hello_world/hello_world.elf index 5eeedc4..6be1ee4 100755 Binary files a/hello_world/hello_world.elf and b/hello_world/hello_world.elf differ diff --git a/lpc/lpc.v b/lpc/lpc.v new file mode 100644 index 0000000..727a58c --- /dev/null +++ b/lpc/lpc.v @@ -0,0 +1,13153 @@ +/* Generated by Yosys 0.10+12 (git sha1 4e70c3077, gcc 11.2.1 -fPIC -Os) */ + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0" *) +(* generator = "nMigen" *) +module \U$$0 (clk, lclkrst_clk, lclkrst_rst, w_data, w_rdy, w_en, r_data, r_rdy, r_en, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:341" *) + wire [2:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) + wire \$12 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:378" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) + wire \$16 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:379" *) + wire \$18 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:335" *) + wire [2:0] \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) + wire \$20 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:380" *) + wire \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:383" *) + wire [2:0] \$24 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:383" *) + wire [2:0] \$25 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:384" *) + wire [2:0] \$27 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:384" *) + wire [2:0] \$28 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) + wire \$30 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:394" *) + wire \$32 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:400" *) + wire \$34 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:335" *) + wire [2:0] \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:341" *) + wire [2:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:330" *) + wire \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:353" *) + reg [1:0] consume_cdc_consume_r_gry = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:353" *) + reg [1:0] \consume_cdc_consume_r_gry$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:354" *) + wire [1:0] consume_cdc_consume_w_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + wire [1:0] consume_dec_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + wire [1:0] consume_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + wire [1:0] consume_enc_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + wire [1:0] consume_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:339" *) + reg [1:0] consume_r_bin = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:339" *) + reg [1:0] \consume_r_bin$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:340" *) + wire [1:0] consume_r_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:362" *) + reg [1:0] consume_w_bin = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:362" *) + reg [1:0] \consume_w_bin$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:345" *) + wire [1:0] produce_cdc_produce_r_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:344" *) + reg [1:0] produce_cdc_produce_w_gry = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:344" *) + reg [1:0] \produce_cdc_produce_w_gry$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + wire [1:0] produce_dec_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + wire [1:0] produce_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + wire [1:0] produce_enc_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + wire [1:0] produce_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:368" *) + wire [1:0] produce_r_bin; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:333" *) + reg [1:0] produce_w_bin = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:333" *) + reg [1:0] \produce_w_bin$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:334" *) + wire [1:0] produce_w_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [63:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:375" *) + reg r_empty; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [1:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:311" *) + reg r_rst = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:311" *) + reg \r_rst$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:415" *) + wire rst_cdc_r_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + wire [1:0] rst_dec_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + wire [1:0] rst_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:388" *) + wire storage_r_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:388" *) + wire [63:0] storage_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:388" *) + wire storage_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:387" *) + wire storage_w_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:387" *) + wire [63:0] storage_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:387" *) + wire storage_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [63:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:374" *) + wire w_full; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + reg [1:0] w_level = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + reg [1:0] \w_level$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + reg [63:0] storage [1:0]; + initial begin + storage[0] = 64'h0000000000000000; + storage[1] = 64'h0000000000000000; + end + always @(posedge lclkrst_clk) begin + if (storage_w_en) + storage[storage_w_addr] <= storage_w_data; + end + reg [63:0] _0_; + always @(posedge clk) begin + _0_ <= storage[storage_r_addr]; + end + assign storage_r_data = _0_; + assign \$10 = consume_r_bin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:341" *) \$8 ; + assign \$12 = produce_cdc_produce_w_gry[1] != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) consume_cdc_consume_w_gry[1]; + assign \$14 = produce_cdc_produce_w_gry[0] != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:378" *) consume_cdc_consume_w_gry[0]; + assign \$16 = \$12 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) \$14 ; + assign \$22 = consume_cdc_consume_r_gry == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:380" *) produce_cdc_produce_r_gry; + assign \$25 = produce_w_bin - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:383" *) consume_w_bin; + assign \$28 = produce_r_bin - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:384" *) consume_r_bin; + assign \$30 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) w_en; + assign \$32 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:394" *) w_full; + assign \$34 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:400" *) r_empty; + assign \$3 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) w_en; + assign \$5 = produce_w_bin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:335" *) \$3 ; + assign \$8 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:330" *) r_en; + always @(posedge clk) + r_rst <= \r_rst$next ; + always @(posedge lclkrst_clk) + w_level <= \w_level$next ; + always @(posedge lclkrst_clk) + consume_w_bin <= \consume_w_bin$next ; + always @(posedge clk) + consume_cdc_consume_r_gry <= \consume_cdc_consume_r_gry$next ; + always @(posedge lclkrst_clk) + produce_cdc_produce_w_gry <= \produce_cdc_produce_w_gry$next ; + always @(posedge clk) + consume_r_bin <= \consume_r_bin$next ; + always @(posedge lclkrst_clk) + produce_w_bin <= \produce_w_bin$next ; + consume_cdc consume_cdc ( + .consume_r_gry(consume_cdc_consume_r_gry), + .consume_w_gry(consume_cdc_consume_w_gry), + .lclkrst_clk(lclkrst_clk), + .lclkrst_rst(lclkrst_rst) + ); + consume_dec consume_dec ( + .i(consume_dec_i), + .o(consume_dec_o) + ); + consume_enc consume_enc ( + .i(consume_enc_i), + .o(consume_enc_o) + ); + produce_cdc produce_cdc ( + .clk(clk), + .produce_r_gry(produce_cdc_produce_r_gry), + .produce_w_gry(produce_cdc_produce_w_gry), + .rst(rst) + ); + produce_dec produce_dec ( + .i(produce_dec_i), + .o(produce_dec_o) + ); + produce_enc produce_enc ( + .i(produce_enc_i), + .o(produce_enc_o) + ); + rst_cdc rst_cdc ( + .clk(clk), + .lclkrst_rst(lclkrst_rst), + .r_rst(rst_cdc_r_rst) + ); + rst_dec rst_dec ( + .i(rst_dec_i), + .o(rst_dec_o) + ); + always @* begin + if (\initial ) begin end + \produce_w_bin$next = produce_w_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclkrst_rst) + 1'h1: + \produce_w_bin$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + r_empty = \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + r_empty = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \w_level$next = \$25 [1:0]; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclkrst_rst) + 1'h1: + \w_level$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + \r_rst$next = 1'h1; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:431" */ + default: + \r_rst$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \consume_r_bin$next = consume_r_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + \consume_r_bin$next = rst_dec_o; + endcase + end + always @* begin + if (\initial ) begin end + \produce_cdc_produce_w_gry$next = produce_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclkrst_rst) + 1'h1: + \produce_cdc_produce_w_gry$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \consume_cdc_consume_r_gry$next = consume_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + \consume_cdc_consume_r_gry$next = produce_cdc_produce_r_gry; + endcase + end + always @* begin + if (\initial ) begin end + \consume_w_bin$next = consume_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclkrst_rst) + 1'h1: + \consume_w_bin$next = 2'h0; + endcase + end + assign \$2 = \$5 ; + assign \$7 = \$10 ; + assign \$24 = \$25 ; + assign \$27 = \$28 ; + assign rst_dec_i = produce_cdc_produce_r_gry; + assign r_rdy = \$34 ; + assign storage_r_en = 1'h1; + assign r_data = storage_r_data; + assign storage_r_addr = consume_r_nxt[0]; + assign w_rdy = \$32 ; + assign storage_w_en = \$30 ; + assign storage_w_data = w_data; + assign storage_w_addr = produce_w_bin[0]; + assign r_level = \$28 [1:0]; + assign w_full = \$20 ; + assign produce_r_bin = produce_dec_o; + assign produce_dec_i = produce_cdc_produce_r_gry; + assign consume_dec_i = consume_cdc_consume_w_gry; + assign consume_enc_i = consume_r_nxt; + assign produce_enc_i = produce_w_nxt; + assign consume_r_nxt = \$10 [1:0]; + assign produce_w_nxt = \$5 [1:0]; + assign \$18 = 1'h1; + assign \$20 = \$16 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1" *) +(* generator = "nMigen" *) +module \U$$1 (clk, lclkrst_clk, lclkrst_rst, w_rdy, w_data, w_en, r_en, r_data, r_rdy, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:341" *) + wire [2:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) + wire \$12 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:378" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) + wire \$16 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:379" *) + wire \$18 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:335" *) + wire [2:0] \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) + wire \$20 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:380" *) + wire \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:383" *) + wire [2:0] \$24 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:383" *) + wire [2:0] \$25 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:384" *) + wire [2:0] \$27 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:384" *) + wire [2:0] \$28 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) + wire \$30 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:394" *) + wire \$32 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:400" *) + wire \$34 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:335" *) + wire [2:0] \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:341" *) + wire [2:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:330" *) + wire \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:353" *) + reg [1:0] consume_cdc_consume_r_gry = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:353" *) + reg [1:0] \consume_cdc_consume_r_gry$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:354" *) + wire [1:0] consume_cdc_consume_w_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + wire [1:0] consume_dec_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + wire [1:0] consume_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + wire [1:0] consume_enc_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + wire [1:0] consume_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:339" *) + reg [1:0] consume_r_bin = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:339" *) + reg [1:0] \consume_r_bin$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:340" *) + wire [1:0] consume_r_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:362" *) + reg [1:0] consume_w_bin = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:362" *) + reg [1:0] \consume_w_bin$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:345" *) + wire [1:0] produce_cdc_produce_r_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:344" *) + reg [1:0] produce_cdc_produce_w_gry = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:344" *) + reg [1:0] \produce_cdc_produce_w_gry$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + wire [1:0] produce_dec_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + wire [1:0] produce_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + wire [1:0] produce_enc_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + wire [1:0] produce_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:368" *) + wire [1:0] produce_r_bin; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:333" *) + reg [1:0] produce_w_bin = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:333" *) + reg [1:0] \produce_w_bin$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:334" *) + wire [1:0] produce_w_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [32:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:375" *) + reg r_empty; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [1:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:311" *) + reg r_rst = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:311" *) + reg \r_rst$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:415" *) + wire rst_cdc_r_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + wire [1:0] rst_dec_i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + wire [1:0] rst_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:388" *) + wire storage_r_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:388" *) + wire [32:0] storage_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:388" *) + wire storage_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:387" *) + wire storage_w_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:387" *) + wire [32:0] storage_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:387" *) + wire storage_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [32:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:374" *) + wire w_full; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + reg [1:0] w_level = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + reg [1:0] \w_level$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + reg [32:0] storage [1:0]; + initial begin + storage[0] = 33'h000000000; + storage[1] = 33'h000000000; + end + always @(posedge clk) begin + if (storage_w_en) + storage[storage_w_addr] <= storage_w_data; + end + reg [32:0] _0_; + always @(posedge lclkrst_clk) begin + _0_ <= storage[storage_r_addr]; + end + assign storage_r_data = _0_; + assign \$10 = consume_r_bin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:341" *) \$8 ; + assign \$12 = produce_cdc_produce_w_gry[1] != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) consume_cdc_consume_w_gry[1]; + assign \$14 = produce_cdc_produce_w_gry[0] != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:378" *) consume_cdc_consume_w_gry[0]; + assign \$16 = \$12 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:377" *) \$14 ; + assign \$22 = consume_cdc_consume_r_gry == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:380" *) produce_cdc_produce_r_gry; + assign \$25 = produce_w_bin - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:383" *) consume_w_bin; + assign \$28 = produce_r_bin - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:384" *) consume_r_bin; + assign \$30 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) w_en; + assign \$32 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:394" *) w_full; + assign \$34 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:400" *) r_empty; + assign \$3 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:329" *) w_en; + assign \$5 = produce_w_bin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:335" *) \$3 ; + assign \$8 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:330" *) r_en; + always @(posedge lclkrst_clk) + r_rst <= \r_rst$next ; + always @(posedge clk) + w_level <= \w_level$next ; + always @(posedge clk) + consume_w_bin <= \consume_w_bin$next ; + always @(posedge lclkrst_clk) + consume_cdc_consume_r_gry <= \consume_cdc_consume_r_gry$next ; + always @(posedge clk) + produce_cdc_produce_w_gry <= \produce_cdc_produce_w_gry$next ; + always @(posedge lclkrst_clk) + consume_r_bin <= \consume_r_bin$next ; + always @(posedge clk) + produce_w_bin <= \produce_w_bin$next ; + \consume_cdc$8 consume_cdc ( + .clk(clk), + .consume_r_gry(consume_cdc_consume_r_gry), + .consume_w_gry(consume_cdc_consume_w_gry), + .rst(rst) + ); + \consume_dec$9 consume_dec ( + .i(consume_dec_i), + .o(consume_dec_o) + ); + \consume_enc$7 consume_enc ( + .i(consume_enc_i), + .o(consume_enc_o) + ); + \produce_cdc$6 produce_cdc ( + .lclkrst_clk(lclkrst_clk), + .lclkrst_rst(lclkrst_rst), + .produce_r_gry(produce_cdc_produce_r_gry), + .produce_w_gry(produce_cdc_produce_w_gry) + ); + \produce_dec$10 produce_dec ( + .i(produce_dec_i), + .o(produce_dec_o) + ); + \produce_enc$5 produce_enc ( + .i(produce_enc_i), + .o(produce_enc_o) + ); + \rst_cdc$11 rst_cdc ( + .lclkrst_clk(lclkrst_clk), + .r_rst(rst_cdc_r_rst), + .rst(rst) + ); + \rst_dec$12 rst_dec ( + .i(rst_dec_i), + .o(rst_dec_o) + ); + always @* begin + if (\initial ) begin end + \produce_w_bin$next = produce_w_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \produce_w_bin$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + r_empty = \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + r_empty = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \w_level$next = \$25 [1:0]; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \w_level$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + \r_rst$next = 1'h1; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:431" */ + default: + \r_rst$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclkrst_rst) + 1'h1: + \r_rst$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \consume_r_bin$next = consume_r_nxt; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + \consume_r_bin$next = rst_dec_o; + endcase + end + always @* begin + if (\initial ) begin end + \produce_cdc_produce_w_gry$next = produce_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \produce_cdc_produce_w_gry$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \consume_cdc_consume_r_gry$next = consume_enc_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" *) + casez (rst_cdc_r_rst) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:426" */ + 1'h1: + \consume_cdc_consume_r_gry$next = produce_cdc_produce_r_gry; + endcase + end + always @* begin + if (\initial ) begin end + \consume_w_bin$next = consume_dec_o; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \consume_w_bin$next = 2'h0; + endcase + end + assign \$2 = \$5 ; + assign \$7 = \$10 ; + assign \$24 = \$25 ; + assign \$27 = \$28 ; + assign rst_dec_i = produce_cdc_produce_r_gry; + assign r_rdy = \$34 ; + assign storage_r_en = 1'h1; + assign r_data = storage_r_data; + assign storage_r_addr = consume_r_nxt[0]; + assign w_rdy = \$32 ; + assign storage_w_en = \$30 ; + assign storage_w_data = w_data; + assign storage_w_addr = produce_w_bin[0]; + assign r_level = \$28 [1:0]; + assign w_full = \$20 ; + assign produce_r_bin = produce_dec_o; + assign produce_dec_i = produce_cdc_produce_r_gry; + assign consume_dec_i = consume_cdc_consume_w_gry; + assign consume_enc_i = consume_r_nxt; + assign produce_enc_i = produce_w_nxt; + assign consume_r_nxt = \$10 [1:0]; + assign produce_w_nxt = \$5 [1:0]; + assign \$18 = 1'h1; + assign \$20 = \$16 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.bmc_decode" *) +(* generator = "nMigen" *) +module bmc_decode(lpc_ctrl_wb__dat_w, lpc_ctrl_wb__dat_r, lpc_ctrl_wb__sel, lpc_ctrl_wb__cyc, lpc_ctrl_wb__stb, lpc_ctrl_wb__we, lpc_ctrl_wb__ack, _bus__adr, _bus__dat_w, _bus__dat_r, _bus__sel, _bus__cyc, _bus__stb, _bus__we, _bus__ack, wb_a__adr, wb_a__dat_w, wb_a__dat_r, wb_a__sel, wb_a__cyc, wb_a__stb, wb_a__we, wb_a__ack, bmc_wb__dat_w, bmc_wb__stb, bmc_wb__cyc, bmc_wb__we, bmc_wb__ack, bmc_wb__adr, bmc_wb__dat_r, lpc_ctrl_wb__adr); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [14:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) + wire \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) + wire \$12 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [14:0] \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [14:0] \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [14:0] \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [14:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [14:0] \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + output _bus__ack; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input [13:0] _bus__adr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__cyc; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + output [31:0] _bus__dat_r; + reg [31:0] _bus__dat_r; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input [31:0] _bus__dat_w; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input [3:0] _bus__sel; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input bmc_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output [2:0] bmc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output bmc_wb__cyc; + reg bmc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input [31:0] bmc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output [31:0] bmc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire [3:0] bmc_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output bmc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output bmc_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + input lpc_ctrl_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output [2:0] lpc_ctrl_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output lpc_ctrl_wb__cyc; + reg lpc_ctrl_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + input [31:0] lpc_ctrl_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output [31:0] lpc_ctrl_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output [3:0] lpc_ctrl_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output lpc_ctrl_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output lpc_ctrl_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input wb_a__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output [2:0] wb_a__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output wb_a__cyc; + reg wb_a__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input [31:0] wb_a__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output [31:0] wb_a__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output [3:0] wb_a__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output wb_a__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output wb_a__we; + assign \$12 = \$10 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) wb_a__ack; + assign \$14 = \$12 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) lpc_ctrl_wb__ack; + always @* begin + if (\initial ) begin end + bmc_wb__cyc = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00010000000???: + bmc_wb__cyc = _bus__cyc; + endcase + end + always @* begin + if (\initial ) begin end + _bus__dat_r = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00010000000???: + _bus__dat_r = bmc_wb__dat_r; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00000000000???: + _bus__dat_r = wb_a__dat_r; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00100000000???: + _bus__dat_r = lpc_ctrl_wb__dat_r; + endcase + end + always @* begin + if (\initial ) begin end + wb_a__cyc = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00010000000???: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00000000000???: + wb_a__cyc = _bus__cyc; + endcase + end + always @* begin + if (\initial ) begin end + lpc_ctrl_wb__cyc = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00010000000???: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00000000000???: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 14'b00100000000???: + lpc_ctrl_wb__cyc = _bus__cyc; + endcase + end + assign \$1 = \$2 ; + assign \$4 = \$5 ; + assign \$7 = \$8 ; + assign _bus__ack = \$14 ; + assign lpc_ctrl_wb__stb = _bus__stb; + assign lpc_ctrl_wb__we = _bus__we; + assign lpc_ctrl_wb__sel = _bus__sel; + assign lpc_ctrl_wb__dat_w = _bus__dat_w; + assign lpc_ctrl_wb__adr = \$8 [2:0]; + assign wb_a__stb = _bus__stb; + assign wb_a__we = _bus__we; + assign wb_a__sel = _bus__sel; + assign wb_a__dat_w = _bus__dat_w; + assign wb_a__adr = \$5 [2:0]; + assign bmc_wb__stb = _bus__stb; + assign bmc_wb__we = _bus__we; + assign bmc_wb__sel = _bus__sel; + assign bmc_wb__dat_w = _bus__dat_w; + assign bmc_wb__adr = \$2 [2:0]; + assign \$2 = { 1'h0, _bus__adr }; + assign \$5 = { 1'h0, _bus__adr }; + assign \$8 = { 1'h0, _bus__adr }; + assign \$10 = bmc_wb__ack; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc_ctrl.bridge" *) +(* generator = "nMigen" *) +module bridge(clk, wb__adr, wb__dat_w, wb__dat_r, wb__sel, wb__cyc, wb__stb, wb__we, wb__ack, csr__addr, csr__r_stb, csr__w_stb, csr__w_data, csr__r_data, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:81" *) + wire \$11 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + wire \$13 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + wire \$15 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + wire \$17 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:79" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:79" *) + wire \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + wire \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + wire \$9 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + output [1:0] csr__addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + input [31:0] csr__r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + output csr__r_stb; + reg csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + output [31:0] csr__w_data; + reg [31:0] csr__w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + output csr__w_stb; + reg csr__w_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:66" *) + reg cycle = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:66" *) + reg \cycle$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + output wb__ack; + reg wb__ack = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + reg \wb__ack$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + input [1:0] wb__adr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + input wb__cyc; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + output [31:0] wb__dat_r; + reg [31:0] wb__dat_r = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + reg [31:0] \wb__dat_r$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + input [31:0] wb__dat_w; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + input wb__sel; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + input wb__stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + input wb__we; + assign \$9 = wb__cyc & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) wb__stb; + assign \$11 = wb__sel & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:81" *) wb__we; + assign \$13 = wb__cyc & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) wb__stb; + assign \$15 = wb__cyc & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) wb__stb; + assign \$17 = wb__cyc & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) wb__stb; + assign \$1 = wb__cyc & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) wb__stb; + assign \$3 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:79" *) wb__we; + assign \$5 = wb__sel & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:79" *) \$3 ; + assign \$7 = wb__cyc & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) wb__stb; + always @(posedge clk) + wb__ack <= \wb__ack$next ; + always @(posedge clk) + wb__dat_r <= \wb__dat_r$next ; + always @(posedge clk) + cycle <= \cycle$next ; + always @* begin + if (\initial ) begin end + csr__r_stb = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + casez (\$1 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" */ + 1'h1: + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:70" *) + casez (cycle) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:75" */ + 1'h0: + csr__r_stb = \$5 ; + endcase + endcase + end + always @* begin + if (\initial ) begin end + csr__w_data = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + casez (\$7 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" */ + 1'h1: + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:70" *) + casez (cycle) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:75" */ + 1'h0: + csr__w_data = wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + csr__w_stb = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + casez (\$9 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" */ + 1'h1: + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:70" *) + casez (cycle) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:75" */ + 1'h0: + csr__w_stb = \$11 ; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \cycle$next = cycle; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + casez (\$13 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" */ + 1'h1: + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:70" *) + casez (cycle) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:75" */ + 1'h0: + \cycle$next = 1'h1; + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:88" *) + casez (wb__ack) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:88" */ + 1'h1: + \cycle$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \cycle$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wb__dat_r$next = wb__dat_r; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + casez (\$15 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:70" *) + casez (cycle) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:75" */ + 1'h0: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:84" */ + default: + \wb__dat_r$next = csr__r_data; + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \wb__dat_r$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \wb__ack$next = wb__ack; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" *) + casez (\$17 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:69" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:70" *) + casez (cycle) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:75" */ + 1'h0: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:84" */ + default: + \wb__ack$next = 1'h1; + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:88" *) + casez (wb__ack) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:88" */ + 1'h1: + \wb__ack$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \wb__ack$next = 1'h0; + endcase + end + assign csr__addr = wb__adr; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.consume_cdc" *) +(* generator = "nMigen" *) +module consume_cdc(lclkrst_rst, consume_r_gry, consume_w_gry, lclkrst_clk); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:353" *) + input [1:0] consume_r_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:354" *) + output [1:0] consume_w_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage0 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage0$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage1 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage1$next ; + always @(posedge lclkrst_clk) + stage1 <= stage0; + always @(posedge lclkrst_clk) + stage0 <= consume_r_gry; + assign consume_w_gry = stage1; + assign \stage1$next = stage0; + assign \stage0$next = consume_r_gry; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.consume_cdc" *) +(* generator = "nMigen" *) +module \consume_cdc$8 (clk, consume_r_gry, consume_w_gry, rst); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:353" *) + input [1:0] consume_r_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:354" *) + output [1:0] consume_w_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage0 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage0$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage1 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage1$next ; + always @(posedge clk) + stage1 <= stage0; + always @(posedge clk) + stage0 <= consume_r_gry; + assign consume_w_gry = stage1; + assign \stage1$next = stage0; + assign \stage0$next = consume_r_gry; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.consume_dec" *) +(* generator = "nMigen" *) +module consume_dec(o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + output [1:0] o; + assign \$1 = o[1] ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) i[0]; + assign o[0] = \$1 ; + assign o[1] = i[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.consume_dec" *) +(* generator = "nMigen" *) +module \consume_dec$9 (o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + output [1:0] o; + assign \$1 = o[1] ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) i[0]; + assign o[0] = \$1 ; + assign o[1] = i[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.consume_enc" *) +(* generator = "nMigen" *) +module consume_enc(o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) + wire [1:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + output [1:0] o; + assign \$1 = i ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) i[1]; + assign o = \$1 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.consume_enc" *) +(* generator = "nMigen" *) +module \consume_enc$7 (o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) + wire [1:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + output [1:0] o; + assign \$1 = i ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) i[1]; + assign o = \$1 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined.fifo_a" *) +(* generator = "nMigen" *) +module fifo_a(clk, w_data, w_rdy, w_en, r_data, r_rdy, r_en, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) + wire [11:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:225" *) + wire [11:0] level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [11:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + reg r_rdy = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + reg \r_rdy$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + wire [10:0] unbuffered_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] unbuffered_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire unbuffered_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire unbuffered_r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] unbuffered_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire unbuffered_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire unbuffered_w_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [11:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + assign \$1 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_rdy; + assign \$3 = \$1 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_en; + assign \$5 = unbuffered_r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) \$3 ; + assign \$7 = unbuffered_level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) r_rdy; + always @(posedge clk) + r_rdy <= \r_rdy$next ; + unbuffered unbuffered ( + .clk(clk), + .level(unbuffered_level), + .r_data(unbuffered_r_data), + .r_en(unbuffered_r_en), + .r_rdy(unbuffered_r_rdy), + .rst(rst), + .w_data(unbuffered_w_data), + .w_en(unbuffered_w_en), + .w_rdy(unbuffered_w_rdy) + ); + always @* begin + if (\initial ) begin end + \r_rdy$next = r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" *) + casez ({ r_en, unbuffered_r_en }) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" */ + 2'b?1: + \r_rdy$next = 1'h1; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:253" */ + 2'b1?: + \r_rdy$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_rdy$next = 1'h0; + endcase + end + assign r_level = level; + assign w_level = level; + assign level = \$7 ; + assign unbuffered_r_en = \$5 ; + assign r_data = unbuffered_r_data; + assign w_rdy = unbuffered_w_rdy; + assign unbuffered_w_en = w_en; + assign unbuffered_w_data = w_data; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined.fifo_b" *) +(* generator = "nMigen" *) +module fifo_b(clk, r_data, r_rdy, r_en, w_data, w_rdy, w_en, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) + wire [11:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:225" *) + wire [11:0] level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [11:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + reg r_rdy = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + reg \r_rdy$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + wire [10:0] unbuffered_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] unbuffered_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire unbuffered_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire unbuffered_r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] unbuffered_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire unbuffered_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire unbuffered_w_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [11:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + assign \$1 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_rdy; + assign \$3 = \$1 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_en; + assign \$5 = unbuffered_r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) \$3 ; + assign \$7 = unbuffered_level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) r_rdy; + always @(posedge clk) + r_rdy <= \r_rdy$next ; + \unbuffered$1 unbuffered ( + .clk(clk), + .level(unbuffered_level), + .r_data(unbuffered_r_data), + .r_en(unbuffered_r_en), + .r_rdy(unbuffered_r_rdy), + .rst(rst), + .w_data(unbuffered_w_data), + .w_en(unbuffered_w_en), + .w_rdy(unbuffered_w_rdy) + ); + always @* begin + if (\initial ) begin end + \r_rdy$next = r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" *) + casez ({ r_en, unbuffered_r_en }) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" */ + 2'b?1: + \r_rdy$next = 1'h1; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:253" */ + 2'b1?: + \r_rdy$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_rdy$next = 1'h0; + endcase + end + assign r_level = level; + assign w_level = level; + assign level = \$7 ; + assign unbuffered_r_en = \$5 ; + assign r_data = unbuffered_r_data; + assign w_rdy = unbuffered_w_rdy; + assign unbuffered_w_en = w_en; + assign unbuffered_w_data = w_data; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.ipmi_bt.from_bmc_fifo" *) +(* generator = "nMigen" *) +module from_bmc_fifo(clk, reset_from_bmc_fifo, w_data, w_en, r_en, r_rdy, r_data, w_rdy, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) + wire [6:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:225" *) + wire [6:0] level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [6:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + reg r_rdy = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + reg \r_rdy$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:51" *) + input reset_from_bmc_fifo; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + wire [5:0] unbuffered_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] unbuffered_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire unbuffered_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire unbuffered_r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] unbuffered_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire unbuffered_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire unbuffered_w_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [6:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + assign \$1 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_rdy; + assign \$3 = \$1 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_en; + assign \$5 = unbuffered_r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) \$3 ; + assign \$7 = unbuffered_level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) r_rdy; + always @(posedge clk) + r_rdy <= \r_rdy$next ; + \unbuffered$2 unbuffered ( + .clk(clk), + .level(unbuffered_level), + .r_data(unbuffered_r_data), + .r_en(unbuffered_r_en), + .r_rdy(unbuffered_r_rdy), + .reset_from_bmc_fifo(reset_from_bmc_fifo), + .rst(rst), + .w_data(unbuffered_w_data), + .w_en(unbuffered_w_en), + .w_rdy(unbuffered_w_rdy) + ); + always @* begin + if (\initial ) begin end + \r_rdy$next = r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" *) + casez ({ r_en, unbuffered_r_en }) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" */ + 2'b?1: + \r_rdy$next = 1'h1; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:253" */ + 2'b1?: + \r_rdy$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_bmc_fifo) + 1'h1: + \r_rdy$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_rdy$next = 1'h0; + endcase + end + assign r_level = level; + assign w_level = level; + assign level = \$7 ; + assign unbuffered_r_en = \$5 ; + assign r_data = unbuffered_r_data; + assign w_rdy = unbuffered_w_rdy; + assign unbuffered_w_en = w_en; + assign unbuffered_w_data = w_data; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.ipmi_bt.from_target_fifo" *) +(* generator = "nMigen" *) +module from_target_fifo(clk, reset_from_target_fifo, w_data, w_en, r_en, r_rdy, r_data, w_rdy, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$3 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) + wire \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) + wire [6:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:225" *) + wire [6:0] level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [6:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + reg r_rdy = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + reg \r_rdy$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:52" *) + input reset_from_target_fifo; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + wire [5:0] unbuffered_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] unbuffered_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire unbuffered_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire unbuffered_r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] unbuffered_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire unbuffered_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire unbuffered_w_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [6:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + assign \$1 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_rdy; + assign \$3 = \$1 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) r_en; + assign \$5 = unbuffered_r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:249" *) \$3 ; + assign \$7 = unbuffered_level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:257" *) r_rdy; + always @(posedge clk) + r_rdy <= \r_rdy$next ; + \unbuffered$3 unbuffered ( + .clk(clk), + .level(unbuffered_level), + .r_data(unbuffered_r_data), + .r_en(unbuffered_r_en), + .r_rdy(unbuffered_r_rdy), + .reset_from_target_fifo(reset_from_target_fifo), + .rst(rst), + .w_data(unbuffered_w_data), + .w_en(unbuffered_w_en), + .w_rdy(unbuffered_w_rdy) + ); + always @* begin + if (\initial ) begin end + \r_rdy$next = r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" *) + casez ({ r_en, unbuffered_r_en }) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:251" */ + 2'b?1: + \r_rdy$next = 1'h1; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:253" */ + 2'b1?: + \r_rdy$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_target_fifo) + 1'h1: + \r_rdy$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_rdy$next = 1'h0; + endcase + end + assign r_level = level; + assign w_level = level; + assign level = \$7 ; + assign unbuffered_r_en = \$5 ; + assign r_data = unbuffered_r_data; + assign w_rdy = unbuffered_w_rdy; + assign unbuffered_w_en = w_en; + assign unbuffered_w_data = w_data; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io" *) +(* generator = "nMigen" *) +module io(bmc_wb__dat_w, bmc_wb__sel, bmc_wb__cyc, bmc_wb__stb, bmc_wb__we, bmc_wb__dat_r, bmc_wb__ack, target_wb__adr, target_wb__dat_w, target_wb__sel, target_wb__cyc, target_wb__stb, target_wb__we, target_wb__dat_r, target_wb__ack, target_wb__err, lpc_ctrl_wb__adr, lpc_ctrl_wb__dat_w, lpc_ctrl_wb__dat_r, lpc_ctrl_wb__sel, lpc_ctrl_wb__cyc, lpc_ctrl_wb__stb, lpc_ctrl_wb__we, lpc_ctrl_wb__ack, bmc_vuart_irq, bmc_ipmi_irq, target_vuart_irq, target_ipmi_irq, rst, clk, bmc_wb__adr); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:77" *) + wire \$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:82" *) + wire \$11 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:78" *) + wire \$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:77" *) + wire \$5 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:82" *) + wire \$7 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:83" *) + wire \$9 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:76" *) + reg ack_expected = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:76" *) + reg \ack_expected$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire bmc_decode__bus__ack; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [13:0] bmc_decode__bus__adr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire bmc_decode__bus__cyc; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [31:0] bmc_decode__bus__dat_r; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [31:0] bmc_decode__bus__dat_w; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [3:0] bmc_decode__bus__sel; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire bmc_decode__bus__stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire bmc_decode__bus__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:23" *) + output bmc_ipmi_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:22" *) + output bmc_vuart_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + output bmc_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + input [13:0] bmc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + input bmc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + output [31:0] bmc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + input [31:0] bmc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + input [3:0] bmc_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + input bmc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + input bmc_wb__we; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:42" *) + wire ipmi_bt_bmc_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire ipmi_bt_bmc_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire [2:0] ipmi_bt_bmc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire ipmi_bt_bmc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire [31:0] ipmi_bt_bmc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire [31:0] ipmi_bt_bmc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire ipmi_bt_bmc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + wire ipmi_bt_bmc_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:45" *) + wire ipmi_bt_target_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire ipmi_bt_target_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire [1:0] ipmi_bt_target_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire ipmi_bt_target_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire [7:0] ipmi_bt_target_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire [7:0] ipmi_bt_target_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire ipmi_bt_target_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire ipmi_bt_target_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + input lpc_ctrl_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output [2:0] lpc_ctrl_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output lpc_ctrl_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + input [31:0] lpc_ctrl_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output [31:0] lpc_ctrl_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output [3:0] lpc_ctrl_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output lpc_ctrl_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + output lpc_ctrl_wb__we; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire target_decode__bus__ack; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [15:0] target_decode__bus__adr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire target_decode__bus__cyc; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [7:0] target_decode__bus__dat_r; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire [7:0] target_decode__bus__dat_w; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire target_decode__bus__err; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire target_decode__bus__sel; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire target_decode__bus__stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + wire target_decode__bus__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + reg target_decode_error_wb__err; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:29" *) + output target_ipmi_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:28" *) + output target_vuart_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + output target_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + input [15:0] target_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + input target_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + output [7:0] target_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + input [7:0] target_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + output target_wb__err; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + input target_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + input target_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + input target_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:23" *) + wire vuart_joined_irq_a; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:26" *) + wire vuart_joined_irq_b; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire vuart_joined_wb_a__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire [2:0] vuart_joined_wb_a__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire vuart_joined_wb_a__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire [31:0] vuart_joined_wb_a__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire [31:0] vuart_joined_wb_a__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire [3:0] vuart_joined_wb_a__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire vuart_joined_wb_a__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + wire vuart_joined_wb_a__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire vuart_joined_wb_b__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire [2:0] vuart_joined_wb_b__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire vuart_joined_wb_b__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire [7:0] vuart_joined_wb_b__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire [7:0] vuart_joined_wb_b__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire vuart_joined_wb_b__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire vuart_joined_wb_b__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + wire vuart_joined_wb_b__we; + assign \$9 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:83" *) vuart_joined_wb_b__ack; + assign \$11 = \$7 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:82" *) \$9 ; + assign \$1 = target_wb__sel & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:77" *) target_wb__cyc; + assign \$3 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:78" *) ack_expected; + assign \$5 = \$1 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:77" *) \$3 ; + assign \$7 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:82" *) ipmi_bt_target_wb__ack; + always @(posedge clk) + ack_expected <= \ack_expected$next ; + bmc_decode bmc_decode ( + ._bus__ack(bmc_decode__bus__ack), + ._bus__adr(bmc_decode__bus__adr), + ._bus__cyc(bmc_decode__bus__cyc), + ._bus__dat_r(bmc_decode__bus__dat_r), + ._bus__dat_w(bmc_decode__bus__dat_w), + ._bus__sel(bmc_decode__bus__sel), + ._bus__stb(bmc_decode__bus__stb), + ._bus__we(bmc_decode__bus__we), + .bmc_wb__ack(ipmi_bt_bmc_wb__ack), + .bmc_wb__adr(ipmi_bt_bmc_wb__adr), + .bmc_wb__cyc(ipmi_bt_bmc_wb__cyc), + .bmc_wb__dat_r(ipmi_bt_bmc_wb__dat_r), + .bmc_wb__dat_w(ipmi_bt_bmc_wb__dat_w), + .bmc_wb__stb(ipmi_bt_bmc_wb__stb), + .bmc_wb__we(ipmi_bt_bmc_wb__we), + .lpc_ctrl_wb__ack(lpc_ctrl_wb__ack), + .lpc_ctrl_wb__adr(lpc_ctrl_wb__adr), + .lpc_ctrl_wb__cyc(lpc_ctrl_wb__cyc), + .lpc_ctrl_wb__dat_r(lpc_ctrl_wb__dat_r), + .lpc_ctrl_wb__dat_w(lpc_ctrl_wb__dat_w), + .lpc_ctrl_wb__sel(lpc_ctrl_wb__sel), + .lpc_ctrl_wb__stb(lpc_ctrl_wb__stb), + .lpc_ctrl_wb__we(lpc_ctrl_wb__we), + .wb_a__ack(vuart_joined_wb_a__ack), + .wb_a__adr(vuart_joined_wb_a__adr), + .wb_a__cyc(vuart_joined_wb_a__cyc), + .wb_a__dat_r(vuart_joined_wb_a__dat_r), + .wb_a__dat_w(vuart_joined_wb_a__dat_w), + .wb_a__sel(vuart_joined_wb_a__sel), + .wb_a__stb(vuart_joined_wb_a__stb), + .wb_a__we(vuart_joined_wb_a__we) + ); + ipmi_bt ipmi_bt ( + .bmc_irq(ipmi_bt_bmc_irq), + .bmc_wb__ack(ipmi_bt_bmc_wb__ack), + .bmc_wb__adr(ipmi_bt_bmc_wb__adr), + .bmc_wb__cyc(ipmi_bt_bmc_wb__cyc), + .bmc_wb__dat_r(ipmi_bt_bmc_wb__dat_r), + .bmc_wb__dat_w(ipmi_bt_bmc_wb__dat_w), + .bmc_wb__stb(ipmi_bt_bmc_wb__stb), + .bmc_wb__we(ipmi_bt_bmc_wb__we), + .clk(clk), + .rst(rst), + .target_irq(ipmi_bt_target_irq), + .target_wb__ack(ipmi_bt_target_wb__ack), + .target_wb__adr(ipmi_bt_target_wb__adr), + .target_wb__cyc(ipmi_bt_target_wb__cyc), + .target_wb__dat_r(ipmi_bt_target_wb__dat_r), + .target_wb__dat_w(ipmi_bt_target_wb__dat_w), + .target_wb__stb(ipmi_bt_target_wb__stb), + .target_wb__we(ipmi_bt_target_wb__we) + ); + target_decode target_decode ( + ._bus__ack(target_decode__bus__ack), + ._bus__adr(target_decode__bus__adr), + ._bus__cyc(target_decode__bus__cyc), + ._bus__dat_r(target_decode__bus__dat_r), + ._bus__dat_w(target_decode__bus__dat_w), + ._bus__err(target_decode__bus__err), + ._bus__sel(target_decode__bus__sel), + ._bus__stb(target_decode__bus__stb), + ._bus__we(target_decode__bus__we), + .error_wb__err(target_decode_error_wb__err), + .target_wb__ack(ipmi_bt_target_wb__ack), + .target_wb__adr(ipmi_bt_target_wb__adr), + .target_wb__cyc(ipmi_bt_target_wb__cyc), + .target_wb__dat_r(ipmi_bt_target_wb__dat_r), + .target_wb__dat_w(ipmi_bt_target_wb__dat_w), + .target_wb__stb(ipmi_bt_target_wb__stb), + .target_wb__we(ipmi_bt_target_wb__we), + .wb_b__ack(vuart_joined_wb_b__ack), + .wb_b__adr(vuart_joined_wb_b__adr), + .wb_b__cyc(vuart_joined_wb_b__cyc), + .wb_b__dat_r(vuart_joined_wb_b__dat_r), + .wb_b__dat_w(vuart_joined_wb_b__dat_w), + .wb_b__sel(vuart_joined_wb_b__sel), + .wb_b__stb(vuart_joined_wb_b__stb), + .wb_b__we(vuart_joined_wb_b__we) + ); + vuart_joined vuart_joined ( + .clk(clk), + .irq_a(vuart_joined_irq_a), + .irq_b(vuart_joined_irq_b), + .rst(rst), + .wb_a__ack(vuart_joined_wb_a__ack), + .wb_a__adr(vuart_joined_wb_a__adr), + .wb_a__cyc(vuart_joined_wb_a__cyc), + .wb_a__dat_r(vuart_joined_wb_a__dat_r), + .wb_a__dat_w(vuart_joined_wb_a__dat_w), + .wb_a__sel(vuart_joined_wb_a__sel), + .wb_a__stb(vuart_joined_wb_a__stb), + .wb_a__we(vuart_joined_wb_a__we), + .wb_b__ack(vuart_joined_wb_b__ack), + .wb_b__adr(vuart_joined_wb_b__adr), + .wb_b__cyc(vuart_joined_wb_b__cyc), + .wb_b__dat_r(vuart_joined_wb_b__dat_r), + .wb_b__dat_w(vuart_joined_wb_b__dat_w), + .wb_b__sel(vuart_joined_wb_b__sel), + .wb_b__stb(vuart_joined_wb_b__stb), + .wb_b__we(vuart_joined_wb_b__we) + ); + always @* begin + if (\initial ) begin end + \ack_expected$next = \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ack_expected$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + target_decode_error_wb__err = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:81" *) + casez (ack_expected) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:81" */ + 1'h1: + target_decode_error_wb__err = \$11 ; + endcase + end + assign target_wb__err = target_decode__bus__err; + assign target_wb__ack = target_decode__bus__ack; + assign target_decode__bus__we = target_wb__we; + assign target_decode__bus__stb = target_wb__stb; + assign target_decode__bus__cyc = target_wb__cyc; + assign target_decode__bus__sel = target_wb__sel; + assign target_wb__dat_r = target_decode__bus__dat_r; + assign target_decode__bus__dat_w = target_wb__dat_w; + assign target_decode__bus__adr = target_wb__adr; + assign target_vuart_irq = vuart_joined_irq_b; + assign target_ipmi_irq = ipmi_bt_target_irq; + assign bmc_wb__ack = bmc_decode__bus__ack; + assign bmc_decode__bus__we = bmc_wb__we; + assign bmc_decode__bus__stb = bmc_wb__stb; + assign bmc_decode__bus__cyc = bmc_wb__cyc; + assign bmc_decode__bus__sel = bmc_wb__sel; + assign bmc_wb__dat_r = bmc_decode__bus__dat_r; + assign bmc_decode__bus__dat_w = bmc_wb__dat_w; + assign bmc_decode__bus__adr = bmc_wb__adr; + assign bmc_vuart_irq = vuart_joined_irq_a; + assign bmc_ipmi_irq = ipmi_bt_bmc_irq; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.ipmi_bt" *) +(* generator = "nMigen" *) +module ipmi_bt(target_wb__ack, target_irq, rst, clk, bmc_wb__dat_w, target_wb__dat_w, bmc_wb__stb, bmc_wb__cyc, bmc_wb__we, target_wb__stb, target_wb__cyc, target_wb__we, bmc_wb__ack, target_wb__adr, target_wb__dat_r, bmc_wb__adr, bmc_wb__dat_r, bmc_irq); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:76" *) + wire \$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:82" *) + wire \$11 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:82" *) + wire \$13 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:83" *) + wire \$15 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:83" *) + wire \$17 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:83" *) + wire \$19 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:130" *) + wire \$21 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:141" *) + wire [1:0] \$23 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:141" *) + wire [1:0] \$25 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:178" *) + wire \$27 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:180" *) + wire \$29 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:76" *) + wire \$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:213" *) + wire [7:0] \$31 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:266" *) + wire \$33 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:121" *) + wire [31:0] \$35 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:108" *) + wire [31:0] \$37 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:138" *) + wire [31:0] \$39 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:139" *) + wire [31:0] \$41 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:77" *) + wire \$5 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:77" *) + wire \$7 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:77" *) + wire \$9 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:118" *) + reg bmc_busy = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:118" *) + reg \bmc_busy$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:42" *) + output bmc_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:139" *) + reg [1:0] \bmc_irq$24 = 2'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:139" *) + reg [1:0] \bmc_irq$24$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:138" *) + reg [1:0] bmc_irq_en = 2'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:138" *) + reg [1:0] \bmc_irq_en$next ; + (* enum_base_type = "StateEnum" *) + (* enum_value_0 = "IDLE" *) + (* enum_value_1 = "ACK" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:87" *) + reg bmc_state = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:87" *) + reg \bmc_state$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:115" *) + reg bmc_to_target_attn = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:115" *) + reg \bmc_to_target_attn$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:128" *) + reg bmc_to_target_irq = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:128" *) + reg \bmc_to_target_irq$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:127" *) + reg bmc_to_target_irq_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:127" *) + reg \bmc_to_target_irq_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output bmc_wb__ack; + reg bmc_wb__ack = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + reg \bmc_wb__ack$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input [2:0] bmc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input bmc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + output [31:0] bmc_wb__dat_r; + reg [31:0] bmc_wb__dat_r = 32'd0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + reg [31:0] \bmc_wb__dat_r$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input [31:0] bmc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input bmc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:41" *) + input bmc_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:121" *) + wire [7:0] bt_ctrl; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] from_bmc_fifo_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + reg from_bmc_fifo_r_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + reg \from_bmc_fifo_r_en$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire from_bmc_fifo_r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:103" *) + reg [7:0] from_bmc_fifo_read_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:51" *) + reg from_bmc_fifo_reset_from_bmc_fifo = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:51" *) + reg \from_bmc_fifo_reset_from_bmc_fifo$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] from_bmc_fifo_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + reg from_bmc_fifo_w_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + reg \from_bmc_fifo_w_en$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire from_bmc_fifo_w_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] from_target_fifo_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + reg from_target_fifo_r_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + reg \from_target_fifo_r_en$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire from_target_fifo_r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:108" *) + reg [7:0] from_target_fifo_read_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:52" *) + reg from_target_fifo_reset_from_target_fifo = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:52" *) + reg \from_target_fifo_reset_from_target_fifo$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] from_target_fifo_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + reg from_target_fifo_w_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + reg \from_target_fifo_w_en$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire from_target_fifo_w_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:74" *) + wire is_bmc_read; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:73" *) + wire is_bmc_write; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:79" *) + wire is_target_read; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:80" *) + wire is_target_write; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:117" *) + reg platform_reserved = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:117" *) + reg \platform_reserved$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:116" *) + reg sms_attn = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:116" *) + reg \sms_attn$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:119" *) + reg target_busy = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:119" *) + reg \target_busy$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:45" *) + output target_irq; + (* enum_base_type = "StateEnum" *) + (* enum_value_0 = "IDLE" *) + (* enum_value_1 = "ACK" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:88" *) + reg target_state = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:88" *) + reg \target_state$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:114" *) + reg target_to_bmc_attn = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:114" *) + reg \target_to_bmc_attn$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output target_wb__ack; + reg target_wb__ack = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + reg \target_wb__ack$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input [1:0] target_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input target_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output [7:0] target_wb__dat_r; + reg [7:0] target_wb__dat_r = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + reg [7:0] \target_wb__dat_r$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input [7:0] target_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input target_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input target_wb__we; + assign \$9 = \$5 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:77" *) \$7 ; + assign \$11 = target_wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:82" *) target_wb__cyc; + assign \$13 = \$11 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:82" *) target_wb__we; + assign \$15 = target_wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:83" *) target_wb__cyc; + assign \$17 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:83" *) target_wb__we; + assign \$1 = bmc_wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:76" *) bmc_wb__cyc; + assign \$19 = \$15 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:83" *) \$17 ; + assign \$21 = bmc_to_target_irq_en & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:130" *) bmc_to_target_irq; + assign \$25 = bmc_irq_en & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:141" *) \bmc_irq$24 ; + assign \$27 = target_busy & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:178" *) bmc_irq_en[1]; + assign \$29 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:180" *) target_busy; + assign \$31 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:213" *) { bmc_to_target_irq, bmc_to_target_irq_en }; + assign \$33 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:266" *) bmc_busy; + assign \$35 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:121" *) bt_ctrl; + assign \$37 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:108" *) from_target_fifo_read_data; + assign \$3 = \$1 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:76" *) bmc_wb__we; + assign \$39 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:138" *) bmc_irq_en; + assign \$41 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:139" *) \bmc_irq$24 ; + assign \$5 = bmc_wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:77" *) bmc_wb__cyc; + assign \$7 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:77" *) bmc_wb__we; + always @(posedge clk) + bmc_wb__dat_r <= \bmc_wb__dat_r$next ; + always @(posedge clk) + bmc_state <= \bmc_state$next ; + always @(posedge clk) + bmc_irq_en <= \bmc_irq_en$next ; + always @(posedge clk) + bmc_busy <= \bmc_busy$next ; + always @(posedge clk) + target_wb__dat_r <= \target_wb__dat_r$next ; + always @(posedge clk) + target_state <= \target_state$next ; + always @(posedge clk) + bmc_to_target_irq <= \bmc_to_target_irq$next ; + always @(posedge clk) + bmc_to_target_irq_en <= \bmc_to_target_irq_en$next ; + always @(posedge clk) + target_busy <= \target_busy$next ; + always @(posedge clk) + platform_reserved <= \platform_reserved$next ; + always @(posedge clk) + sms_attn <= \sms_attn$next ; + always @(posedge clk) + bmc_to_target_attn <= \bmc_to_target_attn$next ; + always @(posedge clk) + target_to_bmc_attn <= \target_to_bmc_attn$next ; + always @(posedge clk) + \bmc_irq$24 <= \bmc_irq$24$next ; + always @(posedge clk) + target_wb__ack <= \target_wb__ack$next ; + always @(posedge clk) + bmc_wb__ack <= \bmc_wb__ack$next ; + always @(posedge clk) + from_target_fifo_r_en <= \from_target_fifo_r_en$next ; + always @(posedge clk) + from_target_fifo_w_en <= \from_target_fifo_w_en$next ; + always @(posedge clk) + from_bmc_fifo_r_en <= \from_bmc_fifo_r_en$next ; + always @(posedge clk) + from_bmc_fifo_w_en <= \from_bmc_fifo_w_en$next ; + always @(posedge clk) + from_target_fifo_reset_from_target_fifo <= \from_target_fifo_reset_from_target_fifo$next ; + always @(posedge clk) + from_bmc_fifo_reset_from_bmc_fifo <= \from_bmc_fifo_reset_from_bmc_fifo$next ; + from_bmc_fifo from_bmc_fifo ( + .clk(clk), + .r_data(from_bmc_fifo_r_data), + .r_en(from_bmc_fifo_r_en), + .r_rdy(from_bmc_fifo_r_rdy), + .reset_from_bmc_fifo(from_bmc_fifo_reset_from_bmc_fifo), + .rst(rst), + .w_data(from_bmc_fifo_w_data), + .w_en(from_bmc_fifo_w_en), + .w_rdy(from_bmc_fifo_w_rdy) + ); + from_target_fifo from_target_fifo ( + .clk(clk), + .r_data(from_target_fifo_r_data), + .r_en(from_target_fifo_r_en), + .r_rdy(from_target_fifo_r_rdy), + .reset_from_target_fifo(from_target_fifo_reset_from_target_fifo), + .rst(rst), + .w_data(from_target_fifo_w_data), + .w_en(from_target_fifo_w_en), + .w_rdy(from_target_fifo_w_rdy) + ); + always @* begin + if (\initial ) begin end + \from_bmc_fifo_reset_from_bmc_fifo$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:233" *) + casez (bmc_wb__dat_w[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:233" */ + 1'h1: + \from_bmc_fifo_reset_from_bmc_fifo$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \from_bmc_fifo_reset_from_bmc_fifo$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \from_target_fifo_reset_from_target_fifo$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:150" *) + casez (target_wb__dat_w[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:150" */ + 1'h1: + \from_target_fifo_reset_from_target_fifo$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \from_target_fifo_reset_from_target_fifo$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \from_target_fifo_w_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:184" */ + 2'h1: + \from_target_fifo_w_en$next = from_target_fifo_w_rdy; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \from_target_fifo_w_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \from_target_fifo_r_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" *) + casez (is_bmc_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:284" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:285" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:288" */ + 3'h5: + \from_target_fifo_r_en$next = from_target_fifo_r_rdy; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \from_target_fifo_r_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_wb__ack$next = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + \bmc_wb__ack$next = 1'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" *) + casez (is_bmc_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" */ + 1'h1: + \bmc_wb__ack$next = 1'h1; + endcase + end + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:305" */ + 1'h1: + \bmc_wb__ack$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \target_wb__ack$next = 1'h0; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + \target_wb__ack$next = 1'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" *) + casez (is_target_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" */ + 1'h1: + \target_wb__ack$next = 1'h1; + endcase + end + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:220" */ + 1'h1: + \target_wb__ack$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \target_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + from_bmc_fifo_read_data = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:105" *) + casez (from_bmc_fifo_r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:105" */ + 1'h1: + from_bmc_fifo_read_data = from_bmc_fifo_r_data; + endcase + end + always @* begin + if (\initial ) begin end + from_target_fifo_read_data = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:110" *) + casez (from_target_fifo_r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:110" */ + 1'h1: + from_target_fifo_read_data = from_target_fifo_r_data; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_irq$24$next = \bmc_irq$24 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:157" *) + casez (target_wb__dat_w[2]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:157" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:159" *) + casez (bmc_irq_en[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:159" */ + 1'h1: + \bmc_irq$24$next [0] = 1'h1; + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:176" *) + casez (target_wb__dat_w[6]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:176" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:178" *) + casez (\$27 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:178" */ + 1'h1: + \bmc_irq$24$next [1] = 1'h1; + endcase + endcase + end + endcase + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:268" */ + 3'h5: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:272" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:275" */ + 3'h1: + \bmc_irq$24$next = bmc_wb__dat_w[1:0]; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_irq$24$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \target_to_bmc_attn$next = target_to_bmc_attn; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:157" *) + casez (target_wb__dat_w[2]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:157" */ + 1'h1: + \target_to_bmc_attn$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:241" *) + casez (bmc_wb__dat_w[2]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:241" */ + 1'h1: + \target_to_bmc_attn$next = 1'h0; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \target_to_bmc_attn$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_to_target_attn$next = bmc_to_target_attn; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:164" *) + casez (target_wb__dat_w[3]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:164" */ + 1'h1: + \bmc_to_target_attn$next = 1'h0; + endcase + endcase + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:245" *) + casez (bmc_wb__dat_w[3]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:245" */ + 1'h1: + \bmc_to_target_attn$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_to_target_attn$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \sms_attn$next = sms_attn; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:168" *) + casez (target_wb__dat_w[4]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:168" */ + 1'h1: + \sms_attn$next = 1'h0; + endcase + endcase + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:252" *) + casez (bmc_wb__dat_w[4]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:252" */ + 1'h1: + \sms_attn$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \sms_attn$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \platform_reserved$next = platform_reserved; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:172" *) + casez (target_wb__dat_w[5]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:172" */ + 1'h1: + \platform_reserved$next = 1'h1; + endcase + endcase + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:259" *) + casez (bmc_wb__dat_w[5]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:259" */ + 1'h1: + \platform_reserved$next = 1'h0; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \platform_reserved$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \target_busy$next = target_busy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:176" *) + casez (target_wb__dat_w[6]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:176" */ + 1'h1: + \target_busy$next = \$29 ; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \target_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_to_target_irq_en$next = bmc_to_target_irq_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:184" */ + 2'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:188" */ + 2'h2: + \bmc_to_target_irq_en$next = target_wb__dat_w[0]; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_to_target_irq_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_to_target_irq$next = bmc_to_target_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:147" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:148" */ + 2'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:184" */ + 2'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:188" */ + 2'h2: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:193" *) + casez (target_wb__dat_w[1]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:193" */ + 1'h1: + \bmc_to_target_irq$next = 1'h0; + endcase + endcase + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:245" *) + casez (bmc_wb__dat_w[3]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:245" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:247" *) + casez (bmc_to_target_irq_en) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:247" */ + 1'h1: + \bmc_to_target_irq$next = 1'h1; + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:252" *) + casez (bmc_wb__dat_w[4]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:252" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:254" *) + casez (bmc_to_target_irq_en) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:254" */ + 1'h1: + \bmc_to_target_irq$next = 1'h1; + endcase + endcase + end + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_to_target_irq$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \target_state$next = target_state; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" *) + casez (is_target_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:146" */ + 1'h1: + \target_state$next = 1'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" *) + casez (is_target_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" */ + 1'h1: + \target_state$next = 1'h1; + endcase + end + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:220" */ + 1'h1: + \target_state$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \target_state$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \target_wb__dat_r$next = target_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" *) + casez (is_target_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:202" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:203" */ + 2'h0: + \target_wb__dat_r$next = bt_ctrl; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:206" */ + 2'h1: + \target_wb__dat_r$next = from_bmc_fifo_read_data; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:212" */ + 2'h2: + \target_wb__dat_r$next = \$31 ; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \target_wb__dat_r$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_busy$next = bmc_busy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:265" *) + casez (bmc_wb__dat_w[7]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:265" */ + 1'h1: + \bmc_busy$next = \$33 ; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_irq_en$next = bmc_irq_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:268" */ + 3'h5: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:272" */ + 3'h0: + \bmc_irq_en$next = bmc_wb__dat_w[1:0]; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_irq_en$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_state$next = bmc_state; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + \bmc_state$next = 1'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" *) + casez (is_bmc_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" */ + 1'h1: + \bmc_state$next = 1'h1; + endcase + end + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:305" */ + 1'h1: + \bmc_state$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_state$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \bmc_wb__dat_r$next = bmc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" *) + casez (is_bmc_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:283" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:284" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:285" */ + 3'h4: + \bmc_wb__dat_r$next = \$35 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:288" */ + 3'h5: + \bmc_wb__dat_r$next = \$37 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:294" */ + 3'h0: + \bmc_wb__dat_r$next = \$39 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:297" */ + 3'h1: + \bmc_wb__dat_r$next = \$41 ; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \bmc_wb__dat_r$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \from_bmc_fifo_w_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:227" *) + casez (bmc_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:228" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" *) + casez (is_bmc_write) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:229" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:230" *) + casez (bmc_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:231" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:268" */ + 3'h5: + \from_bmc_fifo_w_en$next = from_bmc_fifo_w_rdy; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \from_bmc_fifo_w_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \from_bmc_fifo_r_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:144" *) + casez (target_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:145" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" *) + casez (is_target_read) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:201" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:202" *) + casez (target_wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:203" */ + 2'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:206" */ + 2'h1: + \from_bmc_fifo_r_en$next = from_bmc_fifo_r_rdy; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \from_bmc_fifo_r_en$next = 1'h0; + endcase + end + assign \$23 = \$25 ; + assign bmc_irq = \$25 [0]; + assign target_irq = \$21 ; + assign bt_ctrl = { bmc_busy, target_busy, platform_reserved, sms_attn, bmc_to_target_attn, target_to_bmc_attn, 2'h0 }; + assign is_target_read = \$19 ; + assign is_target_write = \$13 ; + assign is_bmc_read = \$9 ; + assign is_bmc_write = \$3 ; + assign from_target_fifo_w_data = target_wb__dat_w; + assign from_bmc_fifo_w_data = bmc_wb__dat_w[7:0]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc" *) +(* generator = "nMigen" *) +module lpc(io_wb__dat_w, io_wb__sel, io_wb__cyc, io_wb__stb, io_wb__we, io_wb__dat_r, io_wb__ack, io_wb__err, fw_wb__adr, fw_wb__dat_w, fw_wb__dat_r, fw_wb__sel, fw_wb__cyc, fw_wb__stb, fw_wb__we, fw_wb__ack, lclk, lframe, lad_in, lad_out, lad_en, lreset, rst, clk, lclk_clk, lclk_rst, lclkrst_clk, lclkrst_rst, io_wb__adr); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + wire \$101 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + wire \$103 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + wire \$105 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:171" *) + wire \$107 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:173" *) + wire \$109 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + wire \$11 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire [31:0] \$111 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:175" *) + wire \$113 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:176" *) + wire \$115 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:178" *) + wire \$117 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:179" *) + wire \$119 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:181" *) + wire \$121 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:183" *) + wire \$123 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:185" *) + wire \$125 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:185" *) + wire \$127 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + wire \$13 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + wire \$15 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:128" *) + wire \$17 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + wire \$19 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + wire \$21 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + wire \$23 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:131" *) + wire \$25 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + wire \$27 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + wire \$29 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + wire \$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + wire \$31 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:132" *) + wire \$33 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" *) + wire \$35 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:142" *) + wire \$37 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:144" *) + wire [62:0] \$39 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:144" *) + wire [62:0] \$40 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" *) + wire \$42 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" *) + wire \$44 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:150" *) + wire [46:0] \$46 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:150" *) + wire [46:0] \$47 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" *) + wire \$49 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + wire \$5 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:153" *) + wire [62:0] \$51 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:153" *) + wire [62:0] \$52 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" *) + wire \$54 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:156" *) + wire [62:0] \$56 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:156" *) + wire [62:0] \$57 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:137" *) + wire \$59 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" *) + wire \$61 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:140" *) + wire \$63 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:142" *) + wire \$65 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" *) + wire \$67 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:146" *) + wire \$69 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + wire \$7 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" *) + wire \$71 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" *) + wire \$73 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" *) + wire \$75 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:157" *) + wire \$77 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + wire \$79 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + wire \$81 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + wire \$83 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:160" *) + wire \$85 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + wire \$87 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + wire \$89 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:164" *) + wire \$9 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + wire \$91 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:161" *) + wire \$93 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + wire \$95 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + wire \$97 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + wire \$99 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [63:0] \U$$0_r_data ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + reg \U$$0_r_en ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire \U$$0_r_rdy ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [63:0] \U$$0_w_data ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire \U$$0_w_en ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire \U$$0_w_rdy ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [32:0] \U$$1_r_data ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire \U$$1_r_en ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire \U$$1_r_rdy ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + reg [32:0] \U$$1_w_data ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire \U$$1_w_en ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire \U$$1_w_rdy ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + input fw_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + output [25:0] fw_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + output fw_wb__cyc; + reg fw_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + input [31:0] fw_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + output [31:0] fw_wb__dat_w; + reg [31:0] fw_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + output [3:0] fw_wb__sel; + reg [3:0] fw_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + output fw_wb__stb; + reg fw_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + output fw_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + input io_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + output [15:0] io_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + output io_wb__cyc; + reg io_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + input [7:0] io_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + output [7:0] io_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + input io_wb__err; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + output io_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + output io_wb__stb; + reg io_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + output io_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:54" *) + output lad_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:52" *) + input [3:0] lad_in; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:53" *) + output [3:0] lad_out; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:50" *) + input lclk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclk_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclk_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclkrst_rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:51" *) + input lframe; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:71" *) + wire [27:0] lpc_addr; + (* enum_base_type = "LPCCycletype" *) + (* enum_value_00 = "IORD" *) + (* enum_value_01 = "IOWR" *) + (* enum_value_10 = "FWRD" *) + (* enum_value_11 = "FWWR" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:73" *) + wire [1:0] lpc_cmd; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:72" *) + wire [31:0] lpc_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:85" *) + wire [31:0] \lpc_data$2 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:76" *) + wire lpc_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:88" *) + wire \lpc_en$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:86" *) + wire lpc_error; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:104" *) + wire lpc_lad_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:102" *) + wire [3:0] lpc_lad_in; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:103" *) + wire [3:0] lpc_lad_out; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:101" *) + wire lpc_lframe; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:105" *) + wire lpc_lreset; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:87" *) + wire lpc_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:77" *) + wire lpc_rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:74" *) + wire [1:0] lpc_size; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:55" *) + input lreset; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:75" *) + wire rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:79" *) + wire [27:0] wr_addr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:80" *) + wire [1:0] wr_cmd; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:78" *) + wire [31:0] wr_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:82" *) + wire wr_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:81" *) + wire [1:0] wr_size; + assign \$9 = io_wb__ack | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:164" *) io_wb__err; + assign \$99 = \$95 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) \$97 ; + assign \$101 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) 2'h2; + assign \$103 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) 2'h3; + assign \$105 = \$101 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) \$103 ; + assign \$107 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:171" *) wr_cmd; + assign \$109 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:173" *) 2'h2; + assign \$111 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) io_wb__dat_r; + assign \$113 = wr_size == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:175" *) 1'h1; + assign \$117 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:178" *) wr_size; + assign \$11 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) 2'h2; + assign \$119 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:179" *) 1'h1; + assign \$121 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:181" *) 2'h2; + assign \$123 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:183" *) 2'h3; + assign \$125 = io_wb__ack | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:185" *) fw_wb__ack; + assign \$127 = \$125 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:185" *) io_wb__err; + assign \$13 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) 2'h3; + assign \$15 = \$11 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) \$13 ; + assign \$17 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:128" *) 2'h1; + assign \$19 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) wr_cmd; + assign \$21 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) 2'h1; + assign \$23 = \$19 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) \$21 ; + assign \$25 = wr_rdy & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:131" *) \U$$1_w_rdy ; + assign \$27 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) wr_cmd; + assign \$29 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) 2'h1; + assign \$31 = \$27 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) \$29 ; + assign \$33 = wr_rdy & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:132" *) \U$$1_w_rdy ; + assign \$35 = wr_size == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" *) 1'h1; + assign \$3 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) wr_cmd; + assign \$42 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" *) wr_size; + assign \$44 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" *) 1'h1; + assign \$49 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" *) 2'h2; + assign \$54 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" *) 2'h3; + assign \$5 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) 2'h1; + assign \$59 = wr_size == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:137" *) 2'h3; + assign \$61 = wr_size == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" *) 1'h1; + assign \$63 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:140" *) wr_addr[1]; + assign \$67 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" *) wr_size; + assign \$69 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:146" *) wr_addr[1:0]; + assign \$71 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" *) 1'h1; + assign \$73 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" *) 2'h2; + assign \$75 = wr_addr[1:0] == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" *) 2'h3; + assign \$77 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:157" *) 2'h3; + assign \$7 = \$3 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) \$5 ; + assign \$79 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) 2'h2; + assign \$81 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) 2'h3; + assign \$83 = \$79 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) \$81 ; + assign \$85 = wr_rdy & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:160" *) \U$$1_w_rdy ; + assign \$87 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) 2'h2; + assign \$89 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) 2'h3; + assign \$91 = \$87 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) \$89 ; + assign \$93 = wr_rdy & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:161" *) \U$$1_w_rdy ; + assign \$95 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) wr_cmd; + assign \$97 = wr_cmd == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) 2'h1; + \U$$0 \U$$0 ( + .clk(clk), + .lclkrst_clk(lclkrst_clk), + .lclkrst_rst(lclkrst_rst), + .r_data(\U$$0_r_data ), + .r_en(\U$$0_r_en ), + .r_rdy(\U$$0_r_rdy ), + .rst(rst), + .w_data(\U$$0_w_data ), + .w_en(\U$$0_w_en ), + .w_rdy(\U$$0_w_rdy ) + ); + \U$$1 \U$$1 ( + .clk(clk), + .lclkrst_clk(lclkrst_clk), + .lclkrst_rst(lclkrst_rst), + .r_data(\U$$1_r_data ), + .r_en(\U$$1_r_en ), + .r_rdy(\U$$1_r_rdy ), + .rst(rst), + .w_data(\U$$1_w_data ), + .w_en(\U$$1_w_en ), + .w_rdy(\U$$1_w_rdy ) + ); + \lpc$4 lpc ( + .addr(lpc_addr), + .cmd(lpc_cmd), + .data(lpc_data), + .\data$2 (\lpc_data$2 ), + .en(lpc_en), + .\en$1 (\lpc_en$1 ), + .error(lpc_error), + .lad_en(lpc_lad_en), + .lad_in(lpc_lad_in), + .lad_out(lpc_lad_out), + .lclk_clk(lclk_clk), + .lclk_rst(lclk_rst), + .lframe(lpc_lframe), + .lreset(lpc_lreset), + .rdy(lpc_rdy), + .rst(lpc_rst), + .size(lpc_size) + ); + always @* begin + if (\initial ) begin end + \U$$0_r_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + casez (\$7 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" */ + 1'h1: + \U$$0_r_en = \$9 ; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + casez (\$15 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" */ + 1'h1: + \U$$0_r_en = fw_wb__ack; + endcase + end + always @* begin + if (\initial ) begin end + io_wb__cyc = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + casez (\$23 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" */ + 1'h1: + io_wb__cyc = \$25 ; + endcase + end + always @* begin + if (\initial ) begin end + io_wb__stb = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" *) + casez (\$31 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:129" */ + 1'h1: + io_wb__stb = \$33 ; + endcase + end + always @* begin + if (\initial ) begin end + fw_wb__dat_w = wr_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" *) + casez (\$35 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:142" *) + casez (\$37 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:142" */ + 1'h1: + fw_wb__dat_w = \$40 [31:0]; + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" *) + casez (\$42 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" */ + 1'h1: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" *) + casez (\$44 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" */ + 1'h1: + fw_wb__dat_w = \$47 [31:0]; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" *) + casez (\$49 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" */ + 1'h1: + fw_wb__dat_w = \$52 [31:0]; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" *) + casez (\$54 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" */ + 1'h1: + fw_wb__dat_w = \$57 [31:0]; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + fw_wb__sel = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:137" *) + casez (\$59 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:137" */ + 1'h1: + fw_wb__sel = 4'hf; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" *) + casez (\$61 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:139" */ + 1'h1: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:140" *) + casez (\$63 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:140" */ + 1'h1: + fw_wb__sel = 4'h3; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:142" *) + casez (\$65 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:142" */ + 1'h1: + fw_wb__sel = 4'hc; + endcase + end + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" *) + casez (\$67 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:145" */ + 1'h1: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:146" *) + casez (\$69 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:146" */ + 1'h1: + fw_wb__sel = 4'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" *) + casez (\$71 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:148" */ + 1'h1: + fw_wb__sel = 4'h2; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" *) + casez (\$73 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:151" */ + 1'h1: + fw_wb__sel = 4'h4; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" *) + casez (\$75 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:154" */ + 1'h1: + fw_wb__sel = 4'h8; + endcase + end + endcase + end + always @* begin + if (\initial ) begin end + fw_wb__cyc = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + casez (\$83 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" */ + 1'h1: + fw_wb__cyc = \$85 ; + endcase + end + always @* begin + if (\initial ) begin end + fw_wb__stb = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" *) + casez (\$91 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:158" */ + 1'h1: + fw_wb__stb = \$93 ; + endcase + end + always @* begin + if (\initial ) begin end + \U$$1_w_data = 33'h000000000; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" *) + casez (\$99 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:163" */ + 1'h1: + \U$$1_w_data [32] = io_wb__err; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" *) + casez (\$105 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:166" */ + 1'h1: + \U$$1_w_data [32] = 1'h0; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:171" *) + casez ({ \$109 , \$107 }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:171" */ + 2'b?1: + \U$$1_w_data [31:0] = \$111 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:173" */ + 2'b1?: + begin + \U$$1_w_data [31:0] = fw_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:175" *) + casez (\$113 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:175" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:176" *) + casez (\$115 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:176" */ + 1'h1: + \U$$1_w_data [15:0] = fw_wb__dat_r[31:16]; + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:178" *) + casez (\$117 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:178" */ + 1'h1: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:179" *) + casez (\$119 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:179" */ + 1'h1: + \U$$1_w_data [7:0] = fw_wb__dat_r[15:8]; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:181" *) + casez (\$121 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:181" */ + 1'h1: + \U$$1_w_data [7:0] = fw_wb__dat_r[23:16]; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:183" *) + casez (\$123 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:183" */ + 1'h1: + \U$$1_w_data [7:0] = fw_wb__dat_r[31:24]; + endcase + end + endcase + end + endcase + end + assign \$39 = \$40 ; + assign \$46 = \$47 ; + assign \$51 = \$52 ; + assign \$56 = \$57 ; + assign lpc_rdy = \U$$1_r_rdy ; + assign lpc_error = \U$$1_r_data [32]; + assign \lpc_data$2 = \U$$1_r_data [31:0]; + assign \U$$1_r_en = \lpc_en$1 ; + assign \U$$1_w_en = \$127 ; + assign fw_wb__we = \$77 ; + assign fw_wb__adr = wr_addr[27:2]; + assign io_wb__we = \$17 ; + assign io_wb__sel = 1'h1; + assign io_wb__dat_w = wr_data[7:0]; + assign io_wb__adr = wr_addr[15:0]; + assign wr_rdy = \U$$0_r_rdy ; + assign wr_size = \U$$0_r_data [63:62]; + assign wr_cmd = \U$$0_r_data [61:60]; + assign wr_addr = \U$$0_r_data [59:32]; + assign wr_data = \U$$0_r_data [31:0]; + assign \U$$0_w_en = lpc_en; + assign rdy = \U$$0_w_rdy ; + assign \U$$0_w_data [63:62] = lpc_size; + assign \U$$0_w_data [61:60] = lpc_cmd; + assign \U$$0_w_data [59:32] = lpc_addr; + assign \U$$0_w_data [31:0] = lpc_data; + assign lad_out = lpc_lad_out; + assign lad_en = lpc_lad_en; + assign lpc_lad_in = lad_in; + assign lpc_lreset = lreset; + assign lpc_lframe = lframe; + assign lclkrst_rst = lpc_rst; + assign lclkrst_clk = lclk; + assign lclk_rst = rst; + assign lclk_clk = lclk; + assign \$37 = wr_addr[1]; + assign \$40 = { 15'h0000, \U$$0_r_data [31:0], 16'h0000 }; + assign \$47 = { 7'h00, \U$$0_r_data [31:0], 8'h00 }; + assign \$52 = { 15'h0000, \U$$0_r_data [31:0], 16'h0000 }; + assign \$57 = { 7'h00, \U$$0_r_data [31:0], 24'h000000 }; + assign \$65 = wr_addr[1]; + assign \$115 = wr_addr[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.lpc" *) +(* generator = "nMigen" *) +module \lpc$4 (lclk_rst, rst, lframe, lreset, lad_in, lad_en, lad_out, data, addr, cmd, size, en, \en$1 , \data$2 , error, rdy, lclk_clk); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" *) + wire \$10 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + wire \$100 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + wire \$102 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + wire \$104 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" *) + wire \$12 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + wire \$14 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) + wire \$16 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:168" *) + wire \$18 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:170" *) + wire \$20 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:190" *) + wire \$22 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" *) + wire \$24 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:210" *) + wire \$26 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:225" *) + wire \$28 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" *) + wire \$30 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" *) + wire \$32 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:291" *) + wire \$34 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" *) + wire \$36 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" *) + wire \$38 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + wire \$40 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:157" *) + wire [3:0] \$42 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:157" *) + wire [3:0] \$43 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) + wire \$45 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:189" *) + wire [3:0] \$47 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:189" *) + wire [3:0] \$48 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" *) + wire \$50 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:210" *) + wire \$52 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:224" *) + wire [3:0] \$54 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:224" *) + wire [3:0] \$55 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:260" *) + wire [3:0] \$57 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:260" *) + wire [3:0] \$58 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:218" *) + wire \$6 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" *) + wire \$60 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:277" *) + wire [3:0] \$62 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:277" *) + wire [3:0] \$63 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" *) + wire \$65 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:290" *) + wire [3:0] \$67 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:290" *) + wire [3:0] \$68 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:312" *) + wire [3:0] \$70 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:312" *) + wire [3:0] \$71 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + wire \$73 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) + wire \$75 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:219" *) + wire \$77 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:285" *) + wire \$79 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:284" *) + wire \$8 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:240" *) + wire [31:0] \$81 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:243" *) + wire [31:0] \$83 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:269" *) + wire [31:0] \$85 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:271" *) + wire [31:0] \$87 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + wire \$89 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + wire \$91 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + wire \$93 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + wire \$95 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + wire \$98 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:71" *) + output [27:0] addr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:122" *) + reg [27:0] \addr$3 = 28'h0000000; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:122" *) + reg [27:0] \addr$3$next ; + (* enum_base_type = "LPCCycletype" *) + (* enum_value_00 = "IORD" *) + (* enum_value_01 = "IOWR" *) + (* enum_value_10 = "FWRD" *) + (* enum_value_11 = "FWWR" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:73" *) + output [1:0] cmd; + reg [1:0] cmd; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:121" *) + reg [2:0] cyclecount = 3'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:121" *) + reg [2:0] \cyclecount$next ; + (* enum_base_type = "LPCCycletype" *) + (* enum_value_00 = "IORD" *) + (* enum_value_01 = "IOWR" *) + (* enum_value_10 = "FWRD" *) + (* enum_value_11 = "FWWR" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:119" *) + reg [1:0] cycletype = 2'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:119" *) + reg [1:0] \cycletype$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:72" *) + output [31:0] data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:85" *) + input [31:0] \data$2 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:123" *) + reg [31:0] \data$4 = 32'd0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:123" *) + reg [31:0] \data$4$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:76" *) + output en; + reg en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:88" *) + output \en$1 ; + reg \en$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:86" *) + input error; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:104" *) + output lad_en; + reg lad_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:102" *) + input [3:0] lad_in; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:103" *) + output [3:0] lad_out; + reg [3:0] lad_out; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:108" *) + reg [3:0] lad_tri; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclk_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclk_rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:101" *) + input lframe; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:126" *) + reg lframesync = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:126" *) + reg \lframesync$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:105" *) + input lreset; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:87" *) + input rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:77" *) + output rst; + reg rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:89" *) + reg \rst$97 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:74" *) + output [1:0] size; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:124" *) + reg [1:0] \size$5 = 2'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:124" *) + reg [1:0] \size$5$next ; + (* enum_base_type = "LPCStates" *) + (* enum_value_0000 = "START" *) + (* enum_value_0001 = "CYCLETYPE" *) + (* enum_value_0010 = "IOADDR" *) + (* enum_value_0011 = "FWIDSEL" *) + (* enum_value_0100 = "FWADDR" *) + (* enum_value_0101 = "FWMSIZE" *) + (* enum_value_0110 = "RDTAR1" *) + (* enum_value_0111 = "RDSYNC" *) + (* enum_value_1000 = "RDDATA" *) + (* enum_value_1001 = "WRDATA" *) + (* enum_value_1010 = "WRTAR1" *) + (* enum_value_1011 = "WRSYNC" *) + (* enum_value_1100 = "TAR2" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:117" *) + reg [3:0] state = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:117" *) + reg [3:0] \state$next ; + (* enum_base_type = "LPCStates" *) + (* enum_value_0000 = "START" *) + (* enum_value_0001 = "CYCLETYPE" *) + (* enum_value_0010 = "IOADDR" *) + (* enum_value_0011 = "FWIDSEL" *) + (* enum_value_0100 = "FWADDR" *) + (* enum_value_0101 = "FWMSIZE" *) + (* enum_value_0110 = "RDTAR1" *) + (* enum_value_0111 = "RDSYNC" *) + (* enum_value_1000 = "RDDATA" *) + (* enum_value_1001 = "WRDATA" *) + (* enum_value_1010 = "WRTAR1" *) + (* enum_value_1011 = "WRSYNC" *) + (* enum_value_1100 = "TAR2" *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:118" *) + reg [3:0] statenext; + assign \$100 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) lframe; + assign \$102 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) lframesync; + assign \$104 = \$100 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) \$102 ; + assign \$10 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" *) cyclecount; + assign \$12 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" *) lreset; + assign \$14 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) lframe; + assign \$16 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) cyclecount; + assign \$18 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:168" *) cycletype; + assign \$20 = cycletype == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:170" *) 2'h1; + assign \$22 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:190" *) cyclecount; + assign \$24 = cycletype == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" *) 2'h2; + assign \$26 = cycletype == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:210" *) 2'h3; + assign \$28 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:225" *) cyclecount; + assign \$30 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" *) cyclecount; + assign \$32 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" *) cyclecount; + assign \$34 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:291" *) cyclecount; + assign \$36 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" *) cyclecount; + assign \$38 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" *) lreset; + assign \$40 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) lframe; + assign \$43 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:157" *) 1'h1; + assign \$45 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) cyclecount; + assign \$48 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:189" *) 1'h1; + assign \$50 = cycletype == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" *) 2'h2; + assign \$52 = cycletype == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:210" *) 2'h3; + assign \$55 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:224" *) 1'h1; + assign \$58 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:260" *) 1'h1; + assign \$60 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" *) cyclecount; + assign \$63 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:277" *) 1'h1; + assign \$65 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" *) cyclecount; + assign \$68 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:290" *) 1'h1; + assign \$6 = cyclecount == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:218" *) 1'h1; + assign \$71 = cyclecount - (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:312" *) 1'h1; + assign \$73 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) lframe; + assign \$75 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) cyclecount; + assign \$77 = ! (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:219" *) cycletype; + assign \$79 = cycletype == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:285" *) 2'h1; + assign \$81 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:240" *) { 1'h0, \data$2 [7:0] }; + assign \$83 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:243" *) { 1'h0, \data$2 [15:0] }; + assign \$85 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:269" *) { lad_in, \data$4 [7:4] }; + assign \$87 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:271" *) { lad_in, \data$4 [15:4] }; + assign \$8 = cyclecount == (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:284" *) 1'h1; + assign \$89 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) lframe; + assign \$91 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) lframe; + assign \$93 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) lframesync; + assign \$95 = \$91 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) \$93 ; + assign \$98 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) lframe; + always @(posedge lclk_clk) + lframesync <= \lframesync$next ; + always @(posedge lclk_clk) + \data$4 <= \data$4$next ; + always @(posedge lclk_clk) + \size$5 <= \size$5$next ; + always @(posedge lclk_clk) + \addr$3 <= \addr$3$next ; + always @(posedge lclk_clk) + cycletype <= \cycletype$next ; + always @(posedge lclk_clk) + cyclecount <= \cyclecount$next ; + always @(posedge lclk_clk) + state <= \state$next ; + always @* begin + if (\initial ) begin end + \addr$3$next = \addr$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + \addr$3$next = { \addr$3 [23:0], lad_in }; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + \addr$3$next = { \addr$3 [23:0], lad_in }; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \addr$3$next = 28'h0000000; + endcase + end + always @* begin + if (\initial ) begin end + \size$5$next = \size$5 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) + casez (\$75 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" */ + 1'h1: + \size$5$next = 2'h0; + endcase + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:194" *) + casez (lad_in) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:195" */ + 4'h0: + \size$5$next = 2'h0; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:198" */ + 4'h1: + \size$5$next = 2'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:201" */ + 4'h2: + \size$5$next = 2'h3; + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \size$5$next = 2'h0; + endcase + end + always @* begin + if (\initial ) begin end + cmd = 2'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:219" *) + casez (\$77 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:219" */ + 1'h1: + cmd = 2'h0; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:221" */ + default: + cmd = 2'h2; + endcase + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + /* empty */; + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:285" *) + casez (\$79 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:285" */ + 1'h1: + cmd = 2'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:287" */ + default: + cmd = 2'h3; + endcase + endcase + end + always @* begin + if (\initial ) begin end + lad_out = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + begin + lad_out = 4'h6; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" */ + 1'h1: + begin + lad_out = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:250" *) + casez (error) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:250" */ + 1'h1: + lad_out = 4'ha; + endcase + end + endcase + end + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + lad_out = \data$4 [3:0]; + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + /* empty */; + /* \nmigen.decoding = "WRSYNC/11" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:294" */ + 4'hb: + begin + lad_out = 4'h6; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" */ + 1'h1: + begin + lad_out = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:304" *) + casez (error) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:304" */ + 1'h1: + lad_out = 4'ha; + endcase + end + endcase + end + /* \nmigen.decoding = "TAR2/12" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:308" */ + 4'hc: + lad_out = 4'hf; + endcase + end + always @* begin + if (\initial ) begin end + \data$4$next = \data$4 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:237" *) + casez (\size$5 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:238" */ + 2'h0: + \data$4$next = \$81 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:241" */ + 2'h1: + \data$4$next = \$83 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:244" */ + 2'h3: + \data$4$next = \data$2 ; + endcase + endcase + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + \data$4$next = { \data$4 [3:0], \data$4 [31:4] }; + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:267" *) + casez (\size$5 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:268" */ + 2'h0: + \data$4$next = \$85 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:270" */ + 2'h1: + \data$4$next = \$87 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:272" */ + 2'h3: + \data$4$next = { lad_in, \data$4 [31:4] }; + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \data$4$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + rst = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + casez (\$95 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" */ + 1'h1: + rst = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \rst$97 = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" *) + casez (\$104 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:345" */ + 1'h1: + \rst$97 = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + \lframesync$next = lframe; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \lframesync$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:350" *) + casez (lad_en) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:350" */ + 1'h1: + lad_tri = lad_out; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:352" */ + default: + lad_tri = lad_in; + endcase + end + always @* begin + if (\initial ) begin end + en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + en = \$6 ; + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + /* empty */; + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + en = \$8 ; + endcase + end + always @* begin + if (\initial ) begin end + \en$1 = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + \en$1 = 1'h1; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + \en$1 = 1'h1; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" */ + 1'h1: + \en$1 = 1'h1; + endcase + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + /* empty */; + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + /* empty */; + /* \nmigen.decoding = "WRSYNC/11" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:294" */ + 4'hb: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" */ + 1'h1: + \en$1 = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \state$next = statenext; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \state$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + lad_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + /* empty */; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + lad_en = 1'h1; + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + lad_en = 1'h1; + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + /* empty */; + /* \nmigen.decoding = "WRSYNC/11" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:294" */ + 4'hb: + lad_en = 1'h1; + /* \nmigen.decoding = "TAR2/12" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:308" */ + 4'hc: + begin + lad_en = 1'h1; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" *) + casez (\$10 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" */ + 1'h1: + lad_en = 1'h0; + endcase + end + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" *) + casez (\$12 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" */ + 1'h1: + lad_en = 1'h0; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + casez (\$14 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" */ + 1'h1: + lad_en = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + statenext = state; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + begin + statenext = 4'h2; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:148" *) + casez (lad_in) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:149" */ + 4'b000?: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:151" */ + 4'b001?: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:153" */ + default: + statenext = 4'h0; + endcase + end + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) + casez (\$16 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:168" *) + casez ({ \$20 , \$18 }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:168" */ + 2'b?1: + statenext = 4'h6; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:170" */ + 2'b1?: + statenext = 4'h9; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:172" */ + default: + statenext = 4'h0; + endcase + endcase + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + statenext = 4'h4; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + begin + statenext = 4'h4; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:190" *) + casez (\$22 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:190" */ + 1'h1: + statenext = 4'h5; + endcase + end + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + begin + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:194" *) + casez (lad_in) + endcase + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" *) + casez ({ \$26 , \$24 }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" */ + 2'b?1: + statenext = 4'h6; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:210" */ + 2'b1?: + statenext = 4'h9; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:212" */ + default: + statenext = 4'h0; + endcase + end + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:225" *) + casez (\$28 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:225" */ + 1'h1: + statenext = 4'h7; + endcase + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" */ + 1'h1: + begin + statenext = 4'h8; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:237" *) + casez (\size$5 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:238" */ + 2'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:241" */ + 2'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:244" */ + 2'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:247" */ + default: + statenext = 4'h0; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:250" *) + casez (error) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:250" */ + 1'h1: + statenext = 4'h0; + endcase + end + endcase + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" *) + casez (\$30 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" */ + 1'h1: + statenext = 4'hc; + endcase + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + begin + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:267" *) + casez (\size$5 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:268" */ + 2'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:270" */ + 2'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:272" */ + 2'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:274" */ + default: + statenext = 4'h0; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" *) + casez (\$32 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" */ + 1'h1: + statenext = 4'ha; + endcase + end + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:291" *) + casez (\$34 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:291" */ + 1'h1: + statenext = 4'hb; + endcase + /* \nmigen.decoding = "WRSYNC/11" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:294" */ + 4'hb: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" */ + 1'h1: + begin + statenext = 4'hc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:304" *) + casez (error) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:304" */ + 1'h1: + statenext = 4'h0; + endcase + end + endcase + /* \nmigen.decoding = "TAR2/12" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:308" */ + 4'hc: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" *) + casez (\$36 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:313" */ + 1'h1: + statenext = 4'h0; + endcase + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:317" */ + default: + statenext = 4'h0; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" *) + casez (\$38 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:321" */ + 1'h1: + statenext = 4'h0; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + casez (\$40 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:329" *) + casez (lad_in) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:330" */ + 4'h0: + statenext = 4'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:332" */ + 4'hd: + statenext = 4'h3; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:335" */ + 4'he: + statenext = 4'h3; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:338" */ + default: + statenext = 4'h0; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \cyclecount$next = cyclecount; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + \cyclecount$next = 3'h3; + /* \nmigen.decoding = "IOADDR/2" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:156" */ + 4'h2: + begin + \cyclecount$next = \$43 [2:0]; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" *) + casez (\$45 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:165" */ + 1'h1: + \cyclecount$next = 3'h1; + endcase + end + /* \nmigen.decoding = "FWIDSEL/3" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:175" */ + 4'h3: + \cyclecount$next = 3'h6; + /* \nmigen.decoding = "FWADDR/4" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:180" */ + 4'h4: + \cyclecount$next = \$48 [2:0]; + /* \nmigen.decoding = "FWMSIZE/5" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:193" */ + 4'h5: + begin + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:194" *) + casez (lad_in) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:195" */ + 4'h0: + \cyclecount$next = 3'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:198" */ + 4'h1: + \cyclecount$next = 3'h3; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:201" */ + 4'h2: + \cyclecount$next = 3'h7; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" *) + casez ({ \$52 , \$50 }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:207" */ + 2'b?1: + \cyclecount$next = 3'h1; + endcase + end + /* \nmigen.decoding = "RDTAR1/6" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:216" */ + 4'h6: + \cyclecount$next = \$55 [2:0]; + /* \nmigen.decoding = "RDSYNC/7" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:228" */ + 4'h7: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:232" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:237" *) + casez (\size$5 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:238" */ + 2'h0: + \cyclecount$next = 3'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:241" */ + 2'h1: + \cyclecount$next = 3'h3; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:244" */ + 2'h3: + \cyclecount$next = 3'h7; + endcase + endcase + /* \nmigen.decoding = "RDDATA/8" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:255" */ + 4'h8: + begin + \cyclecount$next = \$58 [2:0]; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" *) + casez (\$60 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:261" */ + 1'h1: + \cyclecount$next = 3'h1; + endcase + end + /* \nmigen.decoding = "WRDATA/9" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:266" */ + 4'h9: + begin + \cyclecount$next = \$63 [2:0]; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" *) + casez (\$65 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:278" */ + 1'h1: + \cyclecount$next = 3'h1; + endcase + end + /* \nmigen.decoding = "WRTAR1/10" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:282" */ + 4'ha: + \cyclecount$next = \$68 [2:0]; + /* \nmigen.decoding = "WRSYNC/11" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:294" */ + 4'hb: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" *) + casez (rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:298" */ + 1'h1: + \cyclecount$next = 3'h1; + endcase + /* \nmigen.decoding = "TAR2/12" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:308" */ + 4'hc: + \cyclecount$next = \$71 [2:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \cyclecount$next = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + \cycletype$next = cycletype; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:139" *) + casez (state) + /* \nmigen.decoding = "CYCLETYPE/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:144" */ + 4'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:148" *) + casez (lad_in) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:149" */ + 4'b000?: + \cycletype$next = 2'h0; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:151" */ + 4'b001?: + \cycletype$next = 2'h1; + endcase + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" *) + casez (\$73 ) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:325" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:329" *) + casez (lad_in) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:330" */ + 4'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:332" */ + 4'hd: + \cycletype$next = 2'h2; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcfront.py:335" */ + 4'he: + \cycletype$next = 2'h3; + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (lclk_rst) + 1'h1: + \cycletype$next = 2'h0; + endcase + end + assign \$42 = \$43 ; + assign \$47 = \$48 ; + assign \$54 = \$55 ; + assign \$57 = \$58 ; + assign \$62 = \$63 ; + assign \$67 = \$68 ; + assign \$70 = \$71 ; + assign size = \size$5 ; + assign data = \data$4 ; + assign addr = \addr$3 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc_ctrl" *) +(* generator = "nMigen" *) +module lpc_ctrl(dma_wb__dat_w, dma_wb__sel, dma_wb__cyc, dma_wb__stb, dma_wb__we, dma_wb__dat_r, dma_wb__ack, lpc_wb__adr, lpc_wb__dat_w, lpc_wb__dat_r, lpc_wb__sel, lpc_wb__cyc, lpc_wb__stb, lpc_wb__we, lpc_wb__ack, io_wb__adr, io_wb__dat_w, io_wb__dat_r, io_wb__sel, io_wb__cyc, io_wb__stb, io_wb__we, io_wb__ack, rst, clk, dma_wb__adr); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire [29:0] \$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) + wire [31:0] \$10 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) + wire [31:0] \$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) + wire [31:0] \$4 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) + wire [31:0] \$6 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) + wire [31:0] \$8 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:29" *) + reg [31:0] base_lo = 32'd0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:29" *) + reg [31:0] \base_lo$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire bridge_wb__ack; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire [1:0] bridge_wb__adr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire bridge_wb__cyc; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire [31:0] bridge_wb__dat_r; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire [31:0] bridge_wb__dat_w; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire bridge_wb__sel; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire bridge_wb__stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/wishbone.py:47" *) + wire bridge_wb__we; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + input dma_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + output [29:0] dma_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + output dma_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + input [31:0] dma_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + output [31:0] dma_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + output [3:0] dma_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + output dma_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + output dma_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + output io_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + input [1:0] io_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + input io_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + output [31:0] io_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + input [31:0] io_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + input [3:0] io_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + input io_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + input io_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + output lpc_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + input [25:0] lpc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + input lpc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + output [31:0] lpc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + input [31:0] lpc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + input [3:0] lpc_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + input lpc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + input lpc_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:33" *) + reg [31:0] mask_lo = 32'd0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:33" *) + reg [31:0] \mask_lo$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + wire [31:0] mux_base_lo_csr__r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + wire [31:0] mux_base_lo_csr__w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + wire mux_base_lo_csr__w_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + wire [1:0] mux_csr__addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + wire [31:0] mux_csr__r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + wire mux_csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + wire [31:0] mux_csr__w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + wire mux_csr__w_stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + wire [31:0] mux_mask_lo_csr__r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + wire [31:0] mux_mask_lo_csr__w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + wire mux_mask_lo_csr__w_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + assign \$10 = \$6 | (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) \$8 ; + assign \$1 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) lpc_wb__adr; + assign \$6 = lpc_wb__adr & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:60" *) \$4 ; + always @(posedge clk) + mask_lo <= \mask_lo$next ; + always @(posedge clk) + base_lo <= \base_lo$next ; + bridge bridge ( + .clk(clk), + .csr__addr(mux_csr__addr), + .csr__r_data(mux_csr__r_data), + .csr__r_stb(mux_csr__r_stb), + .csr__w_data(mux_csr__w_data), + .csr__w_stb(mux_csr__w_stb), + .rst(rst), + .wb__ack(bridge_wb__ack), + .wb__adr(bridge_wb__adr), + .wb__cyc(bridge_wb__cyc), + .wb__dat_r(bridge_wb__dat_r), + .wb__dat_w(bridge_wb__dat_w), + .wb__sel(bridge_wb__sel), + .wb__stb(bridge_wb__stb), + .wb__we(bridge_wb__we) + ); + mux mux ( + .base_lo_csr__r_data(mux_base_lo_csr__r_data), + .base_lo_csr__w_data(mux_base_lo_csr__w_data), + .base_lo_csr__w_stb(mux_base_lo_csr__w_stb), + .clk(clk), + .csr__addr(mux_csr__addr), + .csr__r_data(mux_csr__r_data), + .csr__r_stb(mux_csr__r_stb), + .csr__w_data(mux_csr__w_data), + .csr__w_stb(mux_csr__w_stb), + .mask_lo_csr__r_data(mux_mask_lo_csr__r_data), + .mask_lo_csr__w_data(mux_mask_lo_csr__w_data), + .mask_lo_csr__w_stb(mux_mask_lo_csr__w_stb), + .rst(rst) + ); + always @* begin + if (\initial ) begin end + \base_lo$next = base_lo; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:52" *) + casez (mux_base_lo_csr__w_stb) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:52" */ + 1'h1: + \base_lo$next = mux_base_lo_csr__w_data; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_lo$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \mask_lo$next = mask_lo; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:54" *) + casez (mux_mask_lo_csr__w_stb) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:54" */ + 1'h1: + \mask_lo$next = mux_mask_lo_csr__w_data; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_lo$next = 32'd0; + endcase + end + assign \$3 = \$10 ; + assign lpc_wb__ack = dma_wb__ack; + assign dma_wb__we = lpc_wb__we; + assign dma_wb__stb = lpc_wb__stb; + assign dma_wb__cyc = lpc_wb__cyc; + assign dma_wb__sel = lpc_wb__sel; + assign lpc_wb__dat_r = dma_wb__dat_r; + assign dma_wb__dat_w = lpc_wb__dat_w; + assign dma_wb__adr = \$10 [29:0]; + assign mux_mask_lo_csr__r_data = mask_lo; + assign mux_base_lo_csr__r_data = base_lo; + assign io_wb__ack = bridge_wb__ack; + assign bridge_wb__we = io_wb__we; + assign bridge_wb__stb = io_wb__stb; + assign bridge_wb__cyc = io_wb__cyc; + assign bridge_wb__sel = io_wb__sel[0]; + assign io_wb__dat_r = bridge_wb__dat_r; + assign bridge_wb__dat_w = io_wb__dat_w; + assign bridge_wb__adr = io_wb__adr; + assign \$4 = { 2'h0, mask_lo[31:2] }; + assign \$8 = { 2'h0, base_lo[31:2] }; +endmodule + +(* \nmigen.hierarchy = "lpc_top" *) +(* top = 1 *) +(* generator = "nMigen" *) +module lpc_top(dat_w, dat_r, sel, cyc, stb, we, ack, dma_adr, dma_dat_w, dma_dat_r, dma_sel, dma_cyc, dma_stb, dma_we, dma_ack, lclk, lframe, lad_in, lad_out, lad_en, lreset, bmc_vuart_irq, bmc_ipmi_irq, target_vuart_irq, target_ipmi_irq, clk, rst, lclk_clk, lclk_rst, lclkrst_clk, lclkrst_rst, adr); + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:31" *) + wire [3:0] \$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:35" *) + output ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:28" *) + input [13:0] adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:57" *) + output bmc_ipmi_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:56" *) + output bmc_vuart_irq; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:32" *) + input cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:30" *) + output [31:0] dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:29" *) + input [31:0] dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:45" *) + input dma_ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:38" *) + output [29:0] dma_adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:42" *) + output dma_cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:40" *) + input [31:0] dma_dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:39" *) + output [31:0] dma_dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:41" *) + output [3:0] dma_sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:43" *) + output dma_stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:44" *) + output dma_we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:23" *) + wire io_bmc_ipmi_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:22" *) + wire io_bmc_vuart_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire io_bmc_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire [13:0] io_bmc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire io_bmc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire [31:0] io_bmc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire [31:0] io_bmc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire [3:0] io_bmc_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire io_bmc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:24" *) + wire io_bmc_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire io_lpc_ctrl_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire [2:0] io_lpc_ctrl_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire io_lpc_ctrl_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire [31:0] io_lpc_ctrl_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire [31:0] io_lpc_ctrl_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire [3:0] io_lpc_ctrl_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire io_lpc_ctrl_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:26" *) + wire io_lpc_ctrl_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:29" *) + wire io_target_ipmi_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:28" *) + wire io_target_vuart_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire io_target_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire [15:0] io_target_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire io_target_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire [7:0] io_target_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire [7:0] io_target_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire io_target_wb__err; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire io_target_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire io_target_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:30" *) + wire io_target_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:52" *) + output lad_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:50" *) + input [3:0] lad_in; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:51" *) + output [3:0] lad_out; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:48" *) + input lclk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclk_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclk_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + output lclkrst_rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:49" *) + input lframe; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire lpc_ctrl_dma_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire [29:0] lpc_ctrl_dma_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire lpc_ctrl_dma_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire [31:0] lpc_ctrl_dma_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire [31:0] lpc_ctrl_dma_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire [3:0] lpc_ctrl_dma_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire lpc_ctrl_dma_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:23" *) + wire lpc_ctrl_dma_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire lpc_ctrl_io_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire [1:0] lpc_ctrl_io_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire lpc_ctrl_io_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire [31:0] lpc_ctrl_io_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire [31:0] lpc_ctrl_io_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire [3:0] lpc_ctrl_io_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire lpc_ctrl_io_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:20" *) + wire lpc_ctrl_io_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire lpc_ctrl_lpc_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire [25:0] lpc_ctrl_lpc_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire lpc_ctrl_lpc_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire [31:0] lpc_ctrl_lpc_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire [31:0] lpc_ctrl_lpc_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire [3:0] lpc_ctrl_lpc_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire lpc_ctrl_lpc_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:22" *) + wire lpc_ctrl_lpc_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire lpc_fw_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire [25:0] lpc_fw_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire lpc_fw_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire [31:0] lpc_fw_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire [31:0] lpc_fw_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire [3:0] lpc_fw_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire lpc_fw_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:62" *) + wire lpc_fw_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire lpc_io_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire [15:0] lpc_io_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire lpc_io_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire [7:0] lpc_io_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire [7:0] lpc_io_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire lpc_io_wb__err; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire lpc_io_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire lpc_io_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:57" *) + wire lpc_io_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:54" *) + wire lpc_lad_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:52" *) + wire [3:0] lpc_lad_in; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:53" *) + wire [3:0] lpc_lad_out; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:50" *) + wire lpc_lclk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:51" *) + wire lpc_lframe; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc2wb.py:55" *) + wire lpc_lreset; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:53" *) + input lreset; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:31" *) + input sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:33" *) + input stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:60" *) + output target_ipmi_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:59" *) + output target_vuart_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:34" *) + input we; + assign \$1 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpcperipheral.py:31" *) sel; + io io ( + .bmc_ipmi_irq(io_bmc_ipmi_irq), + .bmc_vuart_irq(io_bmc_vuart_irq), + .bmc_wb__ack(io_bmc_wb__ack), + .bmc_wb__adr(io_bmc_wb__adr), + .bmc_wb__cyc(io_bmc_wb__cyc), + .bmc_wb__dat_r(io_bmc_wb__dat_r), + .bmc_wb__dat_w(io_bmc_wb__dat_w), + .bmc_wb__sel(io_bmc_wb__sel), + .bmc_wb__stb(io_bmc_wb__stb), + .bmc_wb__we(io_bmc_wb__we), + .clk(clk), + .lpc_ctrl_wb__ack(io_lpc_ctrl_wb__ack), + .lpc_ctrl_wb__adr(io_lpc_ctrl_wb__adr), + .lpc_ctrl_wb__cyc(io_lpc_ctrl_wb__cyc), + .lpc_ctrl_wb__dat_r(io_lpc_ctrl_wb__dat_r), + .lpc_ctrl_wb__dat_w(io_lpc_ctrl_wb__dat_w), + .lpc_ctrl_wb__sel(io_lpc_ctrl_wb__sel), + .lpc_ctrl_wb__stb(io_lpc_ctrl_wb__stb), + .lpc_ctrl_wb__we(io_lpc_ctrl_wb__we), + .rst(rst), + .target_ipmi_irq(io_target_ipmi_irq), + .target_vuart_irq(io_target_vuart_irq), + .target_wb__ack(io_target_wb__ack), + .target_wb__adr(io_target_wb__adr), + .target_wb__cyc(io_target_wb__cyc), + .target_wb__dat_r(io_target_wb__dat_r), + .target_wb__dat_w(io_target_wb__dat_w), + .target_wb__err(io_target_wb__err), + .target_wb__sel(io_target_wb__sel), + .target_wb__stb(io_target_wb__stb), + .target_wb__we(io_target_wb__we) + ); + lpc lpc ( + .clk(clk), + .fw_wb__ack(lpc_fw_wb__ack), + .fw_wb__adr(lpc_fw_wb__adr), + .fw_wb__cyc(lpc_fw_wb__cyc), + .fw_wb__dat_r(lpc_fw_wb__dat_r), + .fw_wb__dat_w(lpc_fw_wb__dat_w), + .fw_wb__sel(lpc_fw_wb__sel), + .fw_wb__stb(lpc_fw_wb__stb), + .fw_wb__we(lpc_fw_wb__we), + .io_wb__ack(lpc_io_wb__ack), + .io_wb__adr(lpc_io_wb__adr), + .io_wb__cyc(lpc_io_wb__cyc), + .io_wb__dat_r(lpc_io_wb__dat_r), + .io_wb__dat_w(lpc_io_wb__dat_w), + .io_wb__err(lpc_io_wb__err), + .io_wb__sel(lpc_io_wb__sel), + .io_wb__stb(lpc_io_wb__stb), + .io_wb__we(lpc_io_wb__we), + .lad_en(lpc_lad_en), + .lad_in(lpc_lad_in), + .lad_out(lpc_lad_out), + .lclk(lpc_lclk), + .lclk_clk(lclk_clk), + .lclk_rst(lclk_rst), + .lclkrst_clk(lclkrst_clk), + .lclkrst_rst(lclkrst_rst), + .lframe(lpc_lframe), + .lreset(lpc_lreset), + .rst(rst) + ); + lpc_ctrl lpc_ctrl ( + .clk(clk), + .dma_wb__ack(lpc_ctrl_dma_wb__ack), + .dma_wb__adr(lpc_ctrl_dma_wb__adr), + .dma_wb__cyc(lpc_ctrl_dma_wb__cyc), + .dma_wb__dat_r(lpc_ctrl_dma_wb__dat_r), + .dma_wb__dat_w(lpc_ctrl_dma_wb__dat_w), + .dma_wb__sel(lpc_ctrl_dma_wb__sel), + .dma_wb__stb(lpc_ctrl_dma_wb__stb), + .dma_wb__we(lpc_ctrl_dma_wb__we), + .io_wb__ack(lpc_ctrl_io_wb__ack), + .io_wb__adr(lpc_ctrl_io_wb__adr), + .io_wb__cyc(lpc_ctrl_io_wb__cyc), + .io_wb__dat_r(lpc_ctrl_io_wb__dat_r), + .io_wb__dat_w(lpc_ctrl_io_wb__dat_w), + .io_wb__sel(lpc_ctrl_io_wb__sel), + .io_wb__stb(lpc_ctrl_io_wb__stb), + .io_wb__we(lpc_ctrl_io_wb__we), + .lpc_wb__ack(lpc_ctrl_lpc_wb__ack), + .lpc_wb__adr(lpc_ctrl_lpc_wb__adr), + .lpc_wb__cyc(lpc_ctrl_lpc_wb__cyc), + .lpc_wb__dat_r(lpc_ctrl_lpc_wb__dat_r), + .lpc_wb__dat_w(lpc_ctrl_lpc_wb__dat_w), + .lpc_wb__sel(lpc_ctrl_lpc_wb__sel), + .lpc_wb__stb(lpc_ctrl_lpc_wb__stb), + .lpc_wb__we(lpc_ctrl_lpc_wb__we), + .rst(rst) + ); + assign target_ipmi_irq = io_target_ipmi_irq; + assign target_vuart_irq = io_target_vuart_irq; + assign bmc_ipmi_irq = io_bmc_ipmi_irq; + assign bmc_vuart_irq = io_bmc_vuart_irq; + assign lpc_lreset = lreset; + assign lad_en = lpc_lad_en; + assign lad_out = lpc_lad_out; + assign lpc_lad_in = lad_in; + assign lpc_lframe = lframe; + assign lpc_lclk = lclk; + assign io_lpc_ctrl_wb__ack = lpc_ctrl_io_wb__ack; + assign lpc_ctrl_io_wb__we = io_lpc_ctrl_wb__we; + assign lpc_ctrl_io_wb__stb = io_lpc_ctrl_wb__stb; + assign lpc_ctrl_io_wb__cyc = io_lpc_ctrl_wb__cyc; + assign lpc_ctrl_io_wb__sel = io_lpc_ctrl_wb__sel; + assign io_lpc_ctrl_wb__dat_r = lpc_ctrl_io_wb__dat_r; + assign lpc_ctrl_io_wb__dat_w = io_lpc_ctrl_wb__dat_w; + assign lpc_ctrl_io_wb__adr = io_lpc_ctrl_wb__adr[1:0]; + assign lpc_fw_wb__ack = lpc_ctrl_lpc_wb__ack; + assign lpc_ctrl_lpc_wb__we = lpc_fw_wb__we; + assign lpc_ctrl_lpc_wb__stb = lpc_fw_wb__stb; + assign lpc_ctrl_lpc_wb__cyc = lpc_fw_wb__cyc; + assign lpc_ctrl_lpc_wb__sel = lpc_fw_wb__sel; + assign lpc_fw_wb__dat_r = lpc_ctrl_lpc_wb__dat_r; + assign lpc_ctrl_lpc_wb__dat_w = lpc_fw_wb__dat_w; + assign lpc_ctrl_lpc_wb__adr = lpc_fw_wb__adr; + assign lpc_ctrl_dma_wb__ack = dma_ack; + assign lpc_ctrl_dma_wb__dat_r = dma_dat_r; + assign dma_we = lpc_ctrl_dma_wb__we; + assign dma_stb = lpc_ctrl_dma_wb__stb; + assign dma_cyc = lpc_ctrl_dma_wb__cyc; + assign dma_sel = lpc_ctrl_dma_wb__sel; + assign dma_dat_w = lpc_ctrl_dma_wb__dat_w; + assign dma_adr = lpc_ctrl_dma_wb__adr; + assign lpc_io_wb__err = io_target_wb__err; + assign lpc_io_wb__ack = io_target_wb__ack; + assign lpc_io_wb__dat_r = io_target_wb__dat_r; + assign io_target_wb__we = lpc_io_wb__we; + assign io_target_wb__stb = lpc_io_wb__stb; + assign io_target_wb__cyc = lpc_io_wb__cyc; + assign io_target_wb__sel = lpc_io_wb__sel; + assign io_target_wb__dat_w = lpc_io_wb__dat_w; + assign io_target_wb__adr = lpc_io_wb__adr; + assign ack = io_bmc_wb__ack; + assign dat_r = io_bmc_wb__dat_r; + assign io_bmc_wb__we = we; + assign io_bmc_wb__stb = stb; + assign io_bmc_wb__cyc = cyc; + assign io_bmc_wb__sel = \$1 ; + assign io_bmc_wb__dat_w = dat_w; + assign io_bmc_wb__adr = adr; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc_ctrl.mux" *) +(* generator = "nMigen" *) +module mux(clk, base_lo_csr__r_data, mask_lo_csr__r_data, base_lo_csr__w_stb, base_lo_csr__w_data, mask_lo_csr__w_stb, mask_lo_csr__w_data, csr__addr, csr__r_stb, csr__w_stb, csr__w_data, csr__r_data, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$11 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$13 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$15 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$17 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$19 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$21 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$23 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$25 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) + wire [31:0] \$27 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:293" *) + wire [1:0] \$8 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:31" *) + wire [31:0] base_hi_csr__r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:31" *) + reg base_hi_csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] base_hi_csr__shadow = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] \base_hi_csr__shadow$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg base_hi_csr__shadow_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg \base_hi_csr__shadow_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:31" *) + wire [31:0] base_hi_csr__w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:31" *) + reg base_hi_csr__w_stb = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:31" *) + reg \base_hi_csr__w_stb$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + input [31:0] base_lo_csr__r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + reg base_lo_csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] base_lo_csr__shadow = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] \base_lo_csr__shadow$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg base_lo_csr__shadow_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg \base_lo_csr__shadow_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + output [31:0] base_lo_csr__w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + output base_lo_csr__w_stb; + reg base_lo_csr__w_stb = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:28" *) + reg \base_lo_csr__w_stb$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + input [1:0] csr__addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + output [31:0] csr__r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + input csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + input [31:0] csr__w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:232" *) + input csr__w_stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:35" *) + wire [31:0] mask_hi_csr__r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:35" *) + reg mask_hi_csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] mask_hi_csr__shadow = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] \mask_hi_csr__shadow$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg mask_hi_csr__shadow_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg \mask_hi_csr__shadow_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:35" *) + wire [31:0] mask_hi_csr__w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:35" *) + reg mask_hi_csr__w_stb = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:35" *) + reg \mask_hi_csr__w_stb$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + input [31:0] mask_lo_csr__r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + reg mask_lo_csr__r_stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] mask_lo_csr__shadow = 32'd0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:269" *) + reg [31:0] \mask_lo_csr__shadow$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg mask_lo_csr__shadow_en = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:271" *) + reg \mask_lo_csr__shadow_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + output [31:0] mask_lo_csr__w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + output mask_lo_csr__w_stb; + reg mask_lo_csr__w_stb = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/lpc_ctrl.py:32" *) + reg \mask_lo_csr__w_stb$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + assign \$13 = base_lo_csr__shadow_en ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) base_lo_csr__shadow : 32'd0; + assign \$15 = 1'h0 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) \$13 ; + assign \$17 = base_hi_csr__shadow_en ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) base_hi_csr__shadow : 32'd0; + assign \$19 = \$15 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) \$17 ; + assign \$21 = mask_lo_csr__shadow_en ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) mask_lo_csr__shadow : 32'd0; + assign \$23 = \$19 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) \$21 ; + assign \$25 = mask_hi_csr__shadow_en ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) mask_hi_csr__shadow : 32'd0; + assign \$27 = \$23 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:287" *) \$25 ; + always @(posedge clk) + mask_lo_csr__w_stb <= \mask_lo_csr__w_stb$next ; + always @(posedge clk) + mask_lo_csr__shadow_en <= \mask_lo_csr__shadow_en$next ; + always @(posedge clk) + base_hi_csr__shadow <= \base_hi_csr__shadow$next ; + always @(posedge clk) + base_hi_csr__w_stb <= \base_hi_csr__w_stb$next ; + always @(posedge clk) + base_hi_csr__shadow_en <= \base_hi_csr__shadow_en$next ; + always @(posedge clk) + base_lo_csr__shadow <= \base_lo_csr__shadow$next ; + always @(posedge clk) + base_lo_csr__w_stb <= \base_lo_csr__w_stb$next ; + always @(posedge clk) + base_lo_csr__shadow_en <= \base_lo_csr__shadow_en$next ; + always @(posedge clk) + mask_hi_csr__shadow <= \mask_hi_csr__shadow$next ; + always @(posedge clk) + mask_hi_csr__w_stb <= \mask_hi_csr__w_stb$next ; + always @(posedge clk) + mask_hi_csr__shadow_en <= \mask_hi_csr__shadow_en$next ; + always @(posedge clk) + mask_lo_csr__shadow <= \mask_lo_csr__shadow$next ; + always @* begin + if (\initial ) begin end + \base_lo_csr__shadow_en$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h0: + \base_lo_csr__shadow_en$next = \$2 [0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_lo_csr__shadow_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \mask_lo_csr__shadow_en$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h2: + \mask_lo_csr__shadow_en$next = \$8 [0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_lo_csr__shadow_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \mask_lo_csr__w_stb$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h2: + \mask_lo_csr__w_stb$next = csr__w_stb; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_lo_csr__w_stb$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + mask_lo_csr__r_stb = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h2: + mask_lo_csr__r_stb = csr__r_stb; + endcase + end + always @* begin + if (\initial ) begin end + \mask_lo_csr__shadow$next = mask_lo_csr__shadow; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h2: + begin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" *) + casez (csr__r_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" */ + 1'h1: + \mask_lo_csr__shadow$next = mask_lo_csr__r_data; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" *) + casez (csr__w_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" */ + 1'h1: + \mask_lo_csr__shadow$next = csr__w_data; + endcase + end + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_lo_csr__shadow$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \mask_hi_csr__shadow_en$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h3: + \mask_hi_csr__shadow_en$next = \$11 [0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_hi_csr__shadow_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \mask_hi_csr__w_stb$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h3: + \mask_hi_csr__w_stb$next = csr__w_stb; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_hi_csr__w_stb$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + mask_hi_csr__r_stb = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h3: + mask_hi_csr__r_stb = csr__r_stb; + endcase + end + always @* begin + if (\initial ) begin end + \mask_hi_csr__shadow$next = mask_hi_csr__shadow; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h3: + begin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" *) + casez (csr__r_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" */ + 1'h1: + \mask_hi_csr__shadow$next = 32'd0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" *) + casez (csr__w_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" */ + 1'h1: + \mask_hi_csr__shadow$next = csr__w_data; + endcase + end + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mask_hi_csr__shadow$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \base_lo_csr__w_stb$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h0: + \base_lo_csr__w_stb$next = csr__w_stb; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_lo_csr__w_stb$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + base_lo_csr__r_stb = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h0: + base_lo_csr__r_stb = csr__r_stb; + endcase + end + always @* begin + if (\initial ) begin end + \base_lo_csr__shadow$next = base_lo_csr__shadow; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h0: + begin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" *) + casez (csr__r_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" */ + 1'h1: + \base_lo_csr__shadow$next = base_lo_csr__r_data; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" *) + casez (csr__w_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" */ + 1'h1: + \base_lo_csr__shadow$next = csr__w_data; + endcase + end + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_lo_csr__shadow$next = 32'd0; + endcase + end + always @* begin + if (\initial ) begin end + \base_hi_csr__shadow_en$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h1: + \base_hi_csr__shadow_en$next = \$5 [0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_hi_csr__shadow_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \base_hi_csr__w_stb$next = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h1: + \base_hi_csr__w_stb$next = csr__w_stb; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_hi_csr__w_stb$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + base_hi_csr__r_stb = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h1: + base_hi_csr__r_stb = csr__r_stb; + endcase + end + always @* begin + if (\initial ) begin end + \base_hi_csr__shadow$next = base_hi_csr__shadow; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:281" *) + casez (csr__addr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:285" */ + 2'h1: + begin + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" *) + casez (csr__r_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:290" */ + 1'h1: + \base_hi_csr__shadow$next = 32'd0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" *) + casez (csr__w_stb) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/csr/bus.py:300" */ + 1'h1: + \base_hi_csr__shadow$next = csr__w_data; + endcase + end + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \base_hi_csr__shadow$next = 32'd0; + endcase + end + assign \$1 = \$2 ; + assign \$4 = \$5 ; + assign \$7 = \$8 ; + assign \$10 = \$11 ; + assign base_hi_csr__r_data = 32'd0; + assign mask_hi_csr__r_data = 32'd0; + assign csr__r_data = \$27 ; + assign mask_hi_csr__w_data = mask_hi_csr__shadow; + assign mask_lo_csr__w_data = mask_lo_csr__shadow; + assign base_hi_csr__w_data = base_hi_csr__shadow; + assign base_lo_csr__w_data = base_lo_csr__shadow; + assign \$2 = { 1'h0, csr__r_stb }; + assign \$5 = { 1'h0, csr__r_stb }; + assign \$8 = { 1'h0, csr__r_stb }; + assign \$11 = { 1'h0, csr__r_stb }; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.produce_cdc" *) +(* generator = "nMigen" *) +module produce_cdc(clk, produce_w_gry, produce_r_gry, rst); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:345" *) + output [1:0] produce_r_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:344" *) + input [1:0] produce_w_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage0 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage0$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage1 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage1$next ; + always @(posedge clk) + stage1 <= stage0; + always @(posedge clk) + stage0 <= produce_w_gry; + assign produce_r_gry = stage1; + assign \stage1$next = stage0; + assign \stage0$next = produce_w_gry; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.produce_cdc" *) +(* generator = "nMigen" *) +module \produce_cdc$6 (lclkrst_rst, produce_w_gry, produce_r_gry, lclkrst_clk); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:345" *) + output [1:0] produce_r_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:344" *) + input [1:0] produce_w_gry; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage0 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage0$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + reg [1:0] stage1 = 2'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:88" *) + wire [1:0] \stage1$next ; + always @(posedge lclkrst_clk) + stage1 <= stage0; + always @(posedge lclkrst_clk) + stage0 <= produce_w_gry; + assign produce_r_gry = stage1; + assign \stage1$next = stage0; + assign \stage0$next = produce_w_gry; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.produce_dec" *) +(* generator = "nMigen" *) +module produce_dec(o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + output [1:0] o; + assign \$1 = o[1] ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) i[0]; + assign o[0] = \$1 ; + assign o[1] = i[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.produce_dec" *) +(* generator = "nMigen" *) +module \produce_dec$10 (o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + output [1:0] o; + assign \$1 = o[1] ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) i[0]; + assign o[0] = \$1 ; + assign o[1] = i[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.produce_enc" *) +(* generator = "nMigen" *) +module produce_enc(o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) + wire [1:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + output [1:0] o; + assign \$1 = i ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) i[1]; + assign o = \$1 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.produce_enc" *) +(* generator = "nMigen" *) +module \produce_enc$5 (o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) + wire [1:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:151" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:152" *) + output [1:0] o; + assign \$1 = i ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:156" *) i[1]; + assign o = \$1 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.rst_cdc" *) +(* generator = "nMigen" *) +module rst_cdc(lclkrst_rst, r_rst, clk); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:162" *) + wire async_ff_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:162" *) + wire async_ff_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:415" *) + output r_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg stage0 = 1'h1; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg \stage0$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg stage1 = 1'h1; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg \stage1$next ; + always @(posedge async_ff_clk, posedge async_ff_rst) + if (async_ff_rst) stage1 <= 1'h1; + else stage1 <= \stage1$next ; + always @(posedge async_ff_clk, posedge async_ff_rst) + if (async_ff_rst) stage0 <= 1'h1; + else stage0 <= \stage0$next ; + always @* begin + if (\initial ) begin end + \stage0$next = 1'h0; + end + always @* begin + if (\initial ) begin end + \stage1$next = stage0; + end + assign r_rst = stage1; + assign async_ff_clk = clk; + assign async_ff_rst = lclkrst_rst; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.rst_cdc" *) +(* generator = "nMigen" *) +module \rst_cdc$11 (lclkrst_clk, r_rst, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:162" *) + wire async_ff_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:162" *) + wire async_ff_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input lclkrst_clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:415" *) + output r_rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg stage0 = 1'h1; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg \stage0$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg stage1 = 1'h1; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/cdc.py:163" *) + reg \stage1$next ; + always @(posedge async_ff_clk, posedge async_ff_rst) + if (async_ff_rst) stage1 <= 1'h1; + else stage1 <= \stage1$next ; + always @(posedge async_ff_clk, posedge async_ff_rst) + if (async_ff_rst) stage0 <= 1'h1; + else stage0 <= \stage0$next ; + always @* begin + if (\initial ) begin end + \stage0$next = 1'h0; + end + always @* begin + if (\initial ) begin end + \stage1$next = stage0; + end + assign r_rst = stage1; + assign async_ff_clk = lclkrst_clk; + assign async_ff_rst = rst; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$0.rst_dec" *) +(* generator = "nMigen" *) +module rst_dec(o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + output [1:0] o; + assign \$1 = o[1] ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) i[0]; + assign o[0] = \$1 ; + assign o[1] = i[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.lpc.U$$1.rst_dec" *) +(* generator = "nMigen" *) +module \rst_dec$12 (o, i); + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) + wire \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:178" *) + input [1:0] i; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:179" *) + output [1:0] o; + assign \$1 = o[1] ^ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/coding.py:185" *) i[0]; + assign o[0] = \$1 ; + assign o[1] = i[1]; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.target_decode" *) +(* generator = "nMigen" *) +module target_decode(target_wb__ack, wb_b__ack, _bus__adr, _bus__dat_w, _bus__dat_r, _bus__sel, _bus__cyc, _bus__stb, _bus__we, _bus__ack, _bus__err, wb_b__adr, wb_b__dat_w, wb_b__dat_r, wb_b__sel, wb_b__cyc, wb_b__stb, wb_b__we, target_wb__dat_w, target_wb__stb, target_wb__cyc, target_wb__we, target_wb__adr, target_wb__dat_r, error_wb__err); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [16:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) + wire \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) + wire \$12 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:303" *) + wire \$16 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [16:0] \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [16:0] \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [16:0] \$5 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [16:0] \$7 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:282" *) + wire [16:0] \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + output _bus__ack; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input [15:0] _bus__adr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__cyc; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + output [7:0] _bus__dat_r; + reg [7:0] _bus__dat_r; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input [7:0] _bus__dat_w; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + output _bus__err; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__sel; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__stb; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:217" *) + input _bus__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire error_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire [1:0] error_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + reg error_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire [7:0] error_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire [7:0] error_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + input error_wb__err; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire error_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire error_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/io_space.py:32" *) + wire error_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input target_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output [1:0] target_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output target_wb__cyc; + reg target_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + input [7:0] target_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output [7:0] target_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + wire target_wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output target_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:44" *) + output target_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input wb_b__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output [2:0] wb_b__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output wb_b__cyc; + reg wb_b__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input [7:0] wb_b__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output [7:0] wb_b__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output wb_b__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output wb_b__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output wb_b__we; + assign \$12 = \$10 | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:301" *) wb_b__ack; + always @* begin + if (\initial ) begin end + target_wb__cyc = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b00000000111001??: + target_wb__cyc = _bus__cyc; + endcase + end + always @* begin + if (\initial ) begin end + _bus__dat_r = 8'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b00000000111001??: + _bus__dat_r = target_wb__dat_r; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b0000001111111???: + _bus__dat_r = wb_b__dat_r; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b00000000000000??: + _bus__dat_r = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + wb_b__cyc = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b00000000111001??: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b0000001111111???: + wb_b__cyc = _bus__cyc; + endcase + end + always @* begin + if (\initial ) begin end + error_wb__cyc = 1'h0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:277" *) + casez (_bus__adr) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b00000000111001??: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b0000001111111???: + /* empty */; + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen_soc-0.1.dev44+ge9f73e4-py3.9.egg/nmigen_soc/wishbone/bus.py:296" */ + 16'b00000000000000??: + error_wb__cyc = _bus__cyc; + endcase + end + assign \$1 = \$2 ; + assign \$4 = \$5 ; + assign \$7 = \$8 ; + assign error_wb__dat_r = 8'h00; + assign error_wb__ack = 1'h0; + assign _bus__err = \$16 ; + assign _bus__ack = \$14 ; + assign error_wb__stb = _bus__stb; + assign error_wb__we = _bus__we; + assign error_wb__sel = _bus__sel; + assign error_wb__dat_w = _bus__dat_w; + assign error_wb__adr = \$8 [1:0]; + assign wb_b__stb = _bus__stb; + assign wb_b__we = _bus__we; + assign wb_b__sel = _bus__sel; + assign wb_b__dat_w = _bus__dat_w; + assign wb_b__adr = \$5 [2:0]; + assign target_wb__stb = _bus__stb; + assign target_wb__we = _bus__we; + assign target_wb__sel = _bus__sel; + assign target_wb__dat_w = _bus__dat_w; + assign target_wb__adr = \$2 [1:0]; + assign \$2 = { 1'h0, _bus__adr }; + assign \$5 = { 1'h0, _bus__adr }; + assign \$8 = { 1'h0, _bus__adr }; + assign \$10 = target_wb__ack; + assign \$14 = \$12 ; + assign \$16 = error_wb__err; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined.fifo_a.unbuffered" *) +(* generator = "nMigen" *) +module unbuffered(clk, w_data, w_en, w_rdy, r_data, r_en, r_rdy, level, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$11 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$13 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$17 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$19 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) + wire \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$20 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$23 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$26 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$28 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$29 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$32 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [11:0] \$34 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [11:0] \$35 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$37 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$39 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) + wire \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$40 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$43 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [11:0] \$45 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [11:0] \$46 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) + wire \$6 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [10:0] consume = 11'h000; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [10:0] \consume$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + output [10:0] level; + reg [10:0] level = 11'h000; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + reg [10:0] \level$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [10:0] produce = 11'h000; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [10:0] \produce$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [10:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [10:0] storage_r_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [7:0] storage_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire storage_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [10:0] storage_w_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [7:0] storage_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire storage_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [10:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + reg [7:0] storage [2046:0]; + initial begin + storage[0] = 8'h00; + storage[1] = 8'h00; + storage[2] = 8'h00; + storage[3] = 8'h00; + storage[4] = 8'h00; + storage[5] = 8'h00; + storage[6] = 8'h00; + storage[7] = 8'h00; + storage[8] = 8'h00; + storage[9] = 8'h00; + storage[10] = 8'h00; + storage[11] = 8'h00; + storage[12] = 8'h00; + storage[13] = 8'h00; + storage[14] = 8'h00; + storage[15] = 8'h00; + storage[16] = 8'h00; + storage[17] = 8'h00; + storage[18] = 8'h00; + storage[19] = 8'h00; + storage[20] = 8'h00; + storage[21] = 8'h00; + storage[22] = 8'h00; + storage[23] = 8'h00; + storage[24] = 8'h00; + storage[25] = 8'h00; + storage[26] = 8'h00; + storage[27] = 8'h00; + storage[28] = 8'h00; + storage[29] = 8'h00; + storage[30] = 8'h00; + storage[31] = 8'h00; + storage[32] = 8'h00; + storage[33] = 8'h00; + storage[34] = 8'h00; + storage[35] = 8'h00; + storage[36] = 8'h00; + storage[37] = 8'h00; + storage[38] = 8'h00; + storage[39] = 8'h00; + storage[40] = 8'h00; + storage[41] = 8'h00; + storage[42] = 8'h00; + storage[43] = 8'h00; + storage[44] = 8'h00; + storage[45] = 8'h00; + storage[46] = 8'h00; + storage[47] = 8'h00; + storage[48] = 8'h00; + storage[49] = 8'h00; + storage[50] = 8'h00; + storage[51] = 8'h00; + storage[52] = 8'h00; + storage[53] = 8'h00; + storage[54] = 8'h00; + storage[55] = 8'h00; + storage[56] = 8'h00; + storage[57] = 8'h00; + storage[58] = 8'h00; + storage[59] = 8'h00; + storage[60] = 8'h00; + storage[61] = 8'h00; + storage[62] = 8'h00; + storage[63] = 8'h00; + storage[64] = 8'h00; + storage[65] = 8'h00; + storage[66] = 8'h00; + storage[67] = 8'h00; + storage[68] = 8'h00; + storage[69] = 8'h00; + storage[70] = 8'h00; + storage[71] = 8'h00; + storage[72] = 8'h00; + storage[73] = 8'h00; + storage[74] = 8'h00; + storage[75] = 8'h00; + storage[76] = 8'h00; + storage[77] = 8'h00; + storage[78] = 8'h00; + storage[79] = 8'h00; + storage[80] = 8'h00; + storage[81] = 8'h00; + storage[82] = 8'h00; + storage[83] = 8'h00; + storage[84] = 8'h00; + storage[85] = 8'h00; + storage[86] = 8'h00; + storage[87] = 8'h00; + storage[88] = 8'h00; + storage[89] = 8'h00; + storage[90] = 8'h00; + storage[91] = 8'h00; + storage[92] = 8'h00; + storage[93] = 8'h00; + storage[94] = 8'h00; + storage[95] = 8'h00; + storage[96] = 8'h00; + storage[97] = 8'h00; + storage[98] = 8'h00; + storage[99] = 8'h00; + storage[100] = 8'h00; + storage[101] = 8'h00; + storage[102] = 8'h00; + storage[103] = 8'h00; + storage[104] = 8'h00; + storage[105] = 8'h00; + storage[106] = 8'h00; + storage[107] = 8'h00; + storage[108] = 8'h00; + storage[109] = 8'h00; + storage[110] = 8'h00; + storage[111] = 8'h00; + storage[112] = 8'h00; + storage[113] = 8'h00; + storage[114] = 8'h00; + storage[115] = 8'h00; + storage[116] = 8'h00; + storage[117] = 8'h00; + storage[118] = 8'h00; + storage[119] = 8'h00; + storage[120] = 8'h00; + storage[121] = 8'h00; + storage[122] = 8'h00; + storage[123] = 8'h00; + storage[124] = 8'h00; + storage[125] = 8'h00; + storage[126] = 8'h00; + storage[127] = 8'h00; + storage[128] = 8'h00; + storage[129] = 8'h00; + storage[130] = 8'h00; + storage[131] = 8'h00; + storage[132] = 8'h00; + storage[133] = 8'h00; + storage[134] = 8'h00; + storage[135] = 8'h00; + storage[136] = 8'h00; + storage[137] = 8'h00; + storage[138] = 8'h00; + storage[139] = 8'h00; + storage[140] = 8'h00; + storage[141] = 8'h00; + storage[142] = 8'h00; + storage[143] = 8'h00; + storage[144] = 8'h00; + storage[145] = 8'h00; + storage[146] = 8'h00; + storage[147] = 8'h00; + storage[148] = 8'h00; + storage[149] = 8'h00; + storage[150] = 8'h00; + storage[151] = 8'h00; + storage[152] = 8'h00; + storage[153] = 8'h00; + storage[154] = 8'h00; + storage[155] = 8'h00; + storage[156] = 8'h00; + storage[157] = 8'h00; + storage[158] = 8'h00; + storage[159] = 8'h00; + storage[160] = 8'h00; + storage[161] = 8'h00; + storage[162] = 8'h00; + storage[163] = 8'h00; + storage[164] = 8'h00; + storage[165] = 8'h00; + storage[166] = 8'h00; + storage[167] = 8'h00; + storage[168] = 8'h00; + storage[169] = 8'h00; + storage[170] = 8'h00; + storage[171] = 8'h00; + storage[172] = 8'h00; + storage[173] = 8'h00; + storage[174] = 8'h00; + storage[175] = 8'h00; + storage[176] = 8'h00; + storage[177] = 8'h00; + storage[178] = 8'h00; + storage[179] = 8'h00; + storage[180] = 8'h00; + storage[181] = 8'h00; + storage[182] = 8'h00; + storage[183] = 8'h00; + storage[184] = 8'h00; + storage[185] = 8'h00; + storage[186] = 8'h00; + storage[187] = 8'h00; + storage[188] = 8'h00; + storage[189] = 8'h00; + storage[190] = 8'h00; + storage[191] = 8'h00; + storage[192] = 8'h00; + storage[193] = 8'h00; + storage[194] = 8'h00; + storage[195] = 8'h00; + storage[196] = 8'h00; + storage[197] = 8'h00; + storage[198] = 8'h00; + storage[199] = 8'h00; + storage[200] = 8'h00; + storage[201] = 8'h00; + storage[202] = 8'h00; + storage[203] = 8'h00; + storage[204] = 8'h00; + storage[205] = 8'h00; + storage[206] = 8'h00; + storage[207] = 8'h00; + storage[208] = 8'h00; + storage[209] = 8'h00; + storage[210] = 8'h00; + storage[211] = 8'h00; + storage[212] = 8'h00; + storage[213] = 8'h00; + storage[214] = 8'h00; + storage[215] = 8'h00; + storage[216] = 8'h00; + storage[217] = 8'h00; + storage[218] = 8'h00; + storage[219] = 8'h00; + storage[220] = 8'h00; + storage[221] = 8'h00; + storage[222] = 8'h00; + storage[223] = 8'h00; + storage[224] = 8'h00; + storage[225] = 8'h00; + storage[226] = 8'h00; + storage[227] = 8'h00; + storage[228] = 8'h00; + storage[229] = 8'h00; + storage[230] = 8'h00; + storage[231] = 8'h00; + storage[232] = 8'h00; + storage[233] = 8'h00; + storage[234] = 8'h00; + storage[235] = 8'h00; + storage[236] = 8'h00; + storage[237] = 8'h00; + storage[238] = 8'h00; + storage[239] = 8'h00; + storage[240] = 8'h00; + storage[241] = 8'h00; + storage[242] = 8'h00; + storage[243] = 8'h00; + storage[244] = 8'h00; + storage[245] = 8'h00; + storage[246] = 8'h00; + storage[247] = 8'h00; + storage[248] = 8'h00; + storage[249] = 8'h00; + storage[250] = 8'h00; + storage[251] = 8'h00; + storage[252] = 8'h00; + storage[253] = 8'h00; + storage[254] = 8'h00; + storage[255] = 8'h00; + storage[256] = 8'h00; + storage[257] = 8'h00; + storage[258] = 8'h00; + storage[259] = 8'h00; + storage[260] = 8'h00; + storage[261] = 8'h00; + storage[262] = 8'h00; + storage[263] = 8'h00; + storage[264] = 8'h00; + storage[265] = 8'h00; + storage[266] = 8'h00; + storage[267] = 8'h00; + storage[268] = 8'h00; + storage[269] = 8'h00; + storage[270] = 8'h00; + storage[271] = 8'h00; + storage[272] = 8'h00; + storage[273] = 8'h00; + storage[274] = 8'h00; + storage[275] = 8'h00; + storage[276] = 8'h00; + storage[277] = 8'h00; + storage[278] = 8'h00; + storage[279] = 8'h00; + storage[280] = 8'h00; + storage[281] = 8'h00; + storage[282] = 8'h00; + storage[283] = 8'h00; + storage[284] = 8'h00; + storage[285] = 8'h00; + storage[286] = 8'h00; + storage[287] = 8'h00; + storage[288] = 8'h00; + storage[289] = 8'h00; + storage[290] = 8'h00; + storage[291] = 8'h00; + storage[292] = 8'h00; + storage[293] = 8'h00; + storage[294] = 8'h00; + storage[295] = 8'h00; + storage[296] = 8'h00; + storage[297] = 8'h00; + storage[298] = 8'h00; + storage[299] = 8'h00; + storage[300] = 8'h00; + storage[301] = 8'h00; + storage[302] = 8'h00; + storage[303] = 8'h00; + storage[304] = 8'h00; + storage[305] = 8'h00; + storage[306] = 8'h00; + storage[307] = 8'h00; + storage[308] = 8'h00; + storage[309] = 8'h00; + storage[310] = 8'h00; + storage[311] = 8'h00; + storage[312] = 8'h00; + storage[313] = 8'h00; + storage[314] = 8'h00; + storage[315] = 8'h00; + storage[316] = 8'h00; + storage[317] = 8'h00; + storage[318] = 8'h00; + storage[319] = 8'h00; + storage[320] = 8'h00; + storage[321] = 8'h00; + storage[322] = 8'h00; + storage[323] = 8'h00; + storage[324] = 8'h00; + storage[325] = 8'h00; + storage[326] = 8'h00; + storage[327] = 8'h00; + storage[328] = 8'h00; + storage[329] = 8'h00; + storage[330] = 8'h00; + storage[331] = 8'h00; + storage[332] = 8'h00; + storage[333] = 8'h00; + storage[334] = 8'h00; + storage[335] = 8'h00; + storage[336] = 8'h00; + storage[337] = 8'h00; + storage[338] = 8'h00; + storage[339] = 8'h00; + storage[340] = 8'h00; + storage[341] = 8'h00; + storage[342] = 8'h00; + storage[343] = 8'h00; + storage[344] = 8'h00; + storage[345] = 8'h00; + storage[346] = 8'h00; + storage[347] = 8'h00; + storage[348] = 8'h00; + storage[349] = 8'h00; + storage[350] = 8'h00; + storage[351] = 8'h00; + storage[352] = 8'h00; + storage[353] = 8'h00; + storage[354] = 8'h00; + storage[355] = 8'h00; + storage[356] = 8'h00; + storage[357] = 8'h00; + storage[358] = 8'h00; + storage[359] = 8'h00; + storage[360] = 8'h00; + storage[361] = 8'h00; + storage[362] = 8'h00; + storage[363] = 8'h00; + storage[364] = 8'h00; + storage[365] = 8'h00; + storage[366] = 8'h00; + storage[367] = 8'h00; + storage[368] = 8'h00; + storage[369] = 8'h00; + storage[370] = 8'h00; + storage[371] = 8'h00; + storage[372] = 8'h00; + storage[373] = 8'h00; + storage[374] = 8'h00; + storage[375] = 8'h00; + storage[376] = 8'h00; + storage[377] = 8'h00; + storage[378] = 8'h00; + storage[379] = 8'h00; + storage[380] = 8'h00; + storage[381] = 8'h00; + storage[382] = 8'h00; + storage[383] = 8'h00; + storage[384] = 8'h00; + storage[385] = 8'h00; + storage[386] = 8'h00; + storage[387] = 8'h00; + storage[388] = 8'h00; + storage[389] = 8'h00; + storage[390] = 8'h00; + storage[391] = 8'h00; + storage[392] = 8'h00; + storage[393] = 8'h00; + storage[394] = 8'h00; + storage[395] = 8'h00; + storage[396] = 8'h00; + storage[397] = 8'h00; + storage[398] = 8'h00; + storage[399] = 8'h00; + storage[400] = 8'h00; + storage[401] = 8'h00; + storage[402] = 8'h00; + storage[403] = 8'h00; + storage[404] = 8'h00; + storage[405] = 8'h00; + storage[406] = 8'h00; + storage[407] = 8'h00; + storage[408] = 8'h00; + storage[409] = 8'h00; + storage[410] = 8'h00; + storage[411] = 8'h00; + storage[412] = 8'h00; + storage[413] = 8'h00; + storage[414] = 8'h00; + storage[415] = 8'h00; + storage[416] = 8'h00; + storage[417] = 8'h00; + storage[418] = 8'h00; + storage[419] = 8'h00; + storage[420] = 8'h00; + storage[421] = 8'h00; + storage[422] = 8'h00; + storage[423] = 8'h00; + storage[424] = 8'h00; + storage[425] = 8'h00; + storage[426] = 8'h00; + storage[427] = 8'h00; + storage[428] = 8'h00; + storage[429] = 8'h00; + storage[430] = 8'h00; + storage[431] = 8'h00; + storage[432] = 8'h00; + storage[433] = 8'h00; + storage[434] = 8'h00; + storage[435] = 8'h00; + storage[436] = 8'h00; + storage[437] = 8'h00; + storage[438] = 8'h00; + storage[439] = 8'h00; + storage[440] = 8'h00; + storage[441] = 8'h00; + storage[442] = 8'h00; + storage[443] = 8'h00; + storage[444] = 8'h00; + storage[445] = 8'h00; + storage[446] = 8'h00; + storage[447] = 8'h00; + storage[448] = 8'h00; + storage[449] = 8'h00; + storage[450] = 8'h00; + storage[451] = 8'h00; + storage[452] = 8'h00; + storage[453] = 8'h00; + storage[454] = 8'h00; + storage[455] = 8'h00; + storage[456] = 8'h00; + storage[457] = 8'h00; + storage[458] = 8'h00; + storage[459] = 8'h00; + storage[460] = 8'h00; + storage[461] = 8'h00; + storage[462] = 8'h00; + storage[463] = 8'h00; + storage[464] = 8'h00; + storage[465] = 8'h00; + storage[466] = 8'h00; + storage[467] = 8'h00; + storage[468] = 8'h00; + storage[469] = 8'h00; + storage[470] = 8'h00; + storage[471] = 8'h00; + storage[472] = 8'h00; + storage[473] = 8'h00; + storage[474] = 8'h00; + storage[475] = 8'h00; + storage[476] = 8'h00; + storage[477] = 8'h00; + storage[478] = 8'h00; + storage[479] = 8'h00; + storage[480] = 8'h00; + storage[481] = 8'h00; + storage[482] = 8'h00; + storage[483] = 8'h00; + storage[484] = 8'h00; + storage[485] = 8'h00; + storage[486] = 8'h00; + storage[487] = 8'h00; + storage[488] = 8'h00; + storage[489] = 8'h00; + storage[490] = 8'h00; + storage[491] = 8'h00; + storage[492] = 8'h00; + storage[493] = 8'h00; + storage[494] = 8'h00; + storage[495] = 8'h00; + storage[496] = 8'h00; + storage[497] = 8'h00; + storage[498] = 8'h00; + storage[499] = 8'h00; + storage[500] = 8'h00; + storage[501] = 8'h00; + storage[502] = 8'h00; + storage[503] = 8'h00; + storage[504] = 8'h00; + storage[505] = 8'h00; + storage[506] = 8'h00; + storage[507] = 8'h00; + storage[508] = 8'h00; + storage[509] = 8'h00; + storage[510] = 8'h00; + storage[511] = 8'h00; + storage[512] = 8'h00; + storage[513] = 8'h00; + storage[514] = 8'h00; + storage[515] = 8'h00; + storage[516] = 8'h00; + storage[517] = 8'h00; + storage[518] = 8'h00; + storage[519] = 8'h00; + storage[520] = 8'h00; + storage[521] = 8'h00; + storage[522] = 8'h00; + storage[523] = 8'h00; + storage[524] = 8'h00; + storage[525] = 8'h00; + storage[526] = 8'h00; + storage[527] = 8'h00; + storage[528] = 8'h00; + storage[529] = 8'h00; + storage[530] = 8'h00; + storage[531] = 8'h00; + storage[532] = 8'h00; + storage[533] = 8'h00; + storage[534] = 8'h00; + storage[535] = 8'h00; + storage[536] = 8'h00; + storage[537] = 8'h00; + storage[538] = 8'h00; + storage[539] = 8'h00; + storage[540] = 8'h00; + storage[541] = 8'h00; + storage[542] = 8'h00; + storage[543] = 8'h00; + storage[544] = 8'h00; + storage[545] = 8'h00; + storage[546] = 8'h00; + storage[547] = 8'h00; + storage[548] = 8'h00; + storage[549] = 8'h00; + storage[550] = 8'h00; + storage[551] = 8'h00; + storage[552] = 8'h00; + storage[553] = 8'h00; + storage[554] = 8'h00; + storage[555] = 8'h00; + storage[556] = 8'h00; + storage[557] = 8'h00; + storage[558] = 8'h00; + storage[559] = 8'h00; + storage[560] = 8'h00; + storage[561] = 8'h00; + storage[562] = 8'h00; + storage[563] = 8'h00; + storage[564] = 8'h00; + storage[565] = 8'h00; + storage[566] = 8'h00; + storage[567] = 8'h00; + storage[568] = 8'h00; + storage[569] = 8'h00; + storage[570] = 8'h00; + storage[571] = 8'h00; + storage[572] = 8'h00; + storage[573] = 8'h00; + storage[574] = 8'h00; + storage[575] = 8'h00; + storage[576] = 8'h00; + storage[577] = 8'h00; + storage[578] = 8'h00; + storage[579] = 8'h00; + storage[580] = 8'h00; + storage[581] = 8'h00; + storage[582] = 8'h00; + storage[583] = 8'h00; + storage[584] = 8'h00; + storage[585] = 8'h00; + storage[586] = 8'h00; + storage[587] = 8'h00; + storage[588] = 8'h00; + storage[589] = 8'h00; + storage[590] = 8'h00; + storage[591] = 8'h00; + storage[592] = 8'h00; + storage[593] = 8'h00; + storage[594] = 8'h00; + storage[595] = 8'h00; + storage[596] = 8'h00; + storage[597] = 8'h00; + storage[598] = 8'h00; + storage[599] = 8'h00; + storage[600] = 8'h00; + storage[601] = 8'h00; + storage[602] = 8'h00; + storage[603] = 8'h00; + storage[604] = 8'h00; + storage[605] = 8'h00; + storage[606] = 8'h00; + storage[607] = 8'h00; + storage[608] = 8'h00; + storage[609] = 8'h00; + storage[610] = 8'h00; + storage[611] = 8'h00; + storage[612] = 8'h00; + storage[613] = 8'h00; + storage[614] = 8'h00; + storage[615] = 8'h00; + storage[616] = 8'h00; + storage[617] = 8'h00; + storage[618] = 8'h00; + storage[619] = 8'h00; + storage[620] = 8'h00; + storage[621] = 8'h00; + storage[622] = 8'h00; + storage[623] = 8'h00; + storage[624] = 8'h00; + storage[625] = 8'h00; + storage[626] = 8'h00; + storage[627] = 8'h00; + storage[628] = 8'h00; + storage[629] = 8'h00; + storage[630] = 8'h00; + storage[631] = 8'h00; + storage[632] = 8'h00; + storage[633] = 8'h00; + storage[634] = 8'h00; + storage[635] = 8'h00; + storage[636] = 8'h00; + storage[637] = 8'h00; + storage[638] = 8'h00; + storage[639] = 8'h00; + storage[640] = 8'h00; + storage[641] = 8'h00; + storage[642] = 8'h00; + storage[643] = 8'h00; + storage[644] = 8'h00; + storage[645] = 8'h00; + storage[646] = 8'h00; + storage[647] = 8'h00; + storage[648] = 8'h00; + storage[649] = 8'h00; + storage[650] = 8'h00; + storage[651] = 8'h00; + storage[652] = 8'h00; + storage[653] = 8'h00; + storage[654] = 8'h00; + storage[655] = 8'h00; + storage[656] = 8'h00; + storage[657] = 8'h00; + storage[658] = 8'h00; + storage[659] = 8'h00; + storage[660] = 8'h00; + storage[661] = 8'h00; + storage[662] = 8'h00; + storage[663] = 8'h00; + storage[664] = 8'h00; + storage[665] = 8'h00; + storage[666] = 8'h00; + storage[667] = 8'h00; + storage[668] = 8'h00; + storage[669] = 8'h00; + storage[670] = 8'h00; + storage[671] = 8'h00; + storage[672] = 8'h00; + storage[673] = 8'h00; + storage[674] = 8'h00; + storage[675] = 8'h00; + storage[676] = 8'h00; + storage[677] = 8'h00; + storage[678] = 8'h00; + storage[679] = 8'h00; + storage[680] = 8'h00; + storage[681] = 8'h00; + storage[682] = 8'h00; + storage[683] = 8'h00; + storage[684] = 8'h00; + storage[685] = 8'h00; + storage[686] = 8'h00; + storage[687] = 8'h00; + storage[688] = 8'h00; + storage[689] = 8'h00; + storage[690] = 8'h00; + storage[691] = 8'h00; + storage[692] = 8'h00; + storage[693] = 8'h00; + storage[694] = 8'h00; + storage[695] = 8'h00; + storage[696] = 8'h00; + storage[697] = 8'h00; + storage[698] = 8'h00; + storage[699] = 8'h00; + storage[700] = 8'h00; + storage[701] = 8'h00; + storage[702] = 8'h00; + storage[703] = 8'h00; + storage[704] = 8'h00; + storage[705] = 8'h00; + storage[706] = 8'h00; + storage[707] = 8'h00; + storage[708] = 8'h00; + storage[709] = 8'h00; + storage[710] = 8'h00; + storage[711] = 8'h00; + storage[712] = 8'h00; + storage[713] = 8'h00; + storage[714] = 8'h00; + storage[715] = 8'h00; + storage[716] = 8'h00; + storage[717] = 8'h00; + storage[718] = 8'h00; + storage[719] = 8'h00; + storage[720] = 8'h00; + storage[721] = 8'h00; + storage[722] = 8'h00; + storage[723] = 8'h00; + storage[724] = 8'h00; + storage[725] = 8'h00; + storage[726] = 8'h00; + storage[727] = 8'h00; + storage[728] = 8'h00; + storage[729] = 8'h00; + storage[730] = 8'h00; + storage[731] = 8'h00; + storage[732] = 8'h00; + storage[733] = 8'h00; + storage[734] = 8'h00; + storage[735] = 8'h00; + storage[736] = 8'h00; + storage[737] = 8'h00; + storage[738] = 8'h00; + storage[739] = 8'h00; + storage[740] = 8'h00; + storage[741] = 8'h00; + storage[742] = 8'h00; + storage[743] = 8'h00; + storage[744] = 8'h00; + storage[745] = 8'h00; + storage[746] = 8'h00; + storage[747] = 8'h00; + storage[748] = 8'h00; + storage[749] = 8'h00; + storage[750] = 8'h00; + storage[751] = 8'h00; + storage[752] = 8'h00; + storage[753] = 8'h00; + storage[754] = 8'h00; + storage[755] = 8'h00; + storage[756] = 8'h00; + storage[757] = 8'h00; + storage[758] = 8'h00; + storage[759] = 8'h00; + storage[760] = 8'h00; + storage[761] = 8'h00; + storage[762] = 8'h00; + storage[763] = 8'h00; + storage[764] = 8'h00; + storage[765] = 8'h00; + storage[766] = 8'h00; + storage[767] = 8'h00; + storage[768] = 8'h00; + storage[769] = 8'h00; + storage[770] = 8'h00; + storage[771] = 8'h00; + storage[772] = 8'h00; + storage[773] = 8'h00; + storage[774] = 8'h00; + storage[775] = 8'h00; + storage[776] = 8'h00; + storage[777] = 8'h00; + storage[778] = 8'h00; + storage[779] = 8'h00; + storage[780] = 8'h00; + storage[781] = 8'h00; + storage[782] = 8'h00; + storage[783] = 8'h00; + storage[784] = 8'h00; + storage[785] = 8'h00; + storage[786] = 8'h00; + storage[787] = 8'h00; + storage[788] = 8'h00; + storage[789] = 8'h00; + storage[790] = 8'h00; + storage[791] = 8'h00; + storage[792] = 8'h00; + storage[793] = 8'h00; + storage[794] = 8'h00; + storage[795] = 8'h00; + storage[796] = 8'h00; + storage[797] = 8'h00; + storage[798] = 8'h00; + storage[799] = 8'h00; + storage[800] = 8'h00; + storage[801] = 8'h00; + storage[802] = 8'h00; + storage[803] = 8'h00; + storage[804] = 8'h00; + storage[805] = 8'h00; + storage[806] = 8'h00; + storage[807] = 8'h00; + storage[808] = 8'h00; + storage[809] = 8'h00; + storage[810] = 8'h00; + storage[811] = 8'h00; + storage[812] = 8'h00; + storage[813] = 8'h00; + storage[814] = 8'h00; + storage[815] = 8'h00; + storage[816] = 8'h00; + storage[817] = 8'h00; + storage[818] = 8'h00; + storage[819] = 8'h00; + storage[820] = 8'h00; + storage[821] = 8'h00; + storage[822] = 8'h00; + storage[823] = 8'h00; + storage[824] = 8'h00; + storage[825] = 8'h00; + storage[826] = 8'h00; + storage[827] = 8'h00; + storage[828] = 8'h00; + storage[829] = 8'h00; + storage[830] = 8'h00; + storage[831] = 8'h00; + storage[832] = 8'h00; + storage[833] = 8'h00; + storage[834] = 8'h00; + storage[835] = 8'h00; + storage[836] = 8'h00; + storage[837] = 8'h00; + storage[838] = 8'h00; + storage[839] = 8'h00; + storage[840] = 8'h00; + storage[841] = 8'h00; + storage[842] = 8'h00; + storage[843] = 8'h00; + storage[844] = 8'h00; + storage[845] = 8'h00; + storage[846] = 8'h00; + storage[847] = 8'h00; + storage[848] = 8'h00; + storage[849] = 8'h00; + storage[850] = 8'h00; + storage[851] = 8'h00; + storage[852] = 8'h00; + storage[853] = 8'h00; + storage[854] = 8'h00; + storage[855] = 8'h00; + storage[856] = 8'h00; + storage[857] = 8'h00; + storage[858] = 8'h00; + storage[859] = 8'h00; + storage[860] = 8'h00; + storage[861] = 8'h00; + storage[862] = 8'h00; + storage[863] = 8'h00; + storage[864] = 8'h00; + storage[865] = 8'h00; + storage[866] = 8'h00; + storage[867] = 8'h00; + storage[868] = 8'h00; + storage[869] = 8'h00; + storage[870] = 8'h00; + storage[871] = 8'h00; + storage[872] = 8'h00; + storage[873] = 8'h00; + storage[874] = 8'h00; + storage[875] = 8'h00; + storage[876] = 8'h00; + storage[877] = 8'h00; + storage[878] = 8'h00; + storage[879] = 8'h00; + storage[880] = 8'h00; + storage[881] = 8'h00; + storage[882] = 8'h00; + storage[883] = 8'h00; + storage[884] = 8'h00; + storage[885] = 8'h00; + storage[886] = 8'h00; + storage[887] = 8'h00; + storage[888] = 8'h00; + storage[889] = 8'h00; + storage[890] = 8'h00; + storage[891] = 8'h00; + storage[892] = 8'h00; + storage[893] = 8'h00; + storage[894] = 8'h00; + storage[895] = 8'h00; + storage[896] = 8'h00; + storage[897] = 8'h00; + storage[898] = 8'h00; + storage[899] = 8'h00; + storage[900] = 8'h00; + storage[901] = 8'h00; + storage[902] = 8'h00; + storage[903] = 8'h00; + storage[904] = 8'h00; + storage[905] = 8'h00; + storage[906] = 8'h00; + storage[907] = 8'h00; + storage[908] = 8'h00; + storage[909] = 8'h00; + storage[910] = 8'h00; + storage[911] = 8'h00; + storage[912] = 8'h00; + storage[913] = 8'h00; + storage[914] = 8'h00; + storage[915] = 8'h00; + storage[916] = 8'h00; + storage[917] = 8'h00; + storage[918] = 8'h00; + storage[919] = 8'h00; + storage[920] = 8'h00; + storage[921] = 8'h00; + storage[922] = 8'h00; + storage[923] = 8'h00; + storage[924] = 8'h00; + storage[925] = 8'h00; + storage[926] = 8'h00; + storage[927] = 8'h00; + storage[928] = 8'h00; + storage[929] = 8'h00; + storage[930] = 8'h00; + storage[931] = 8'h00; + storage[932] = 8'h00; + storage[933] = 8'h00; + storage[934] = 8'h00; + storage[935] = 8'h00; + storage[936] = 8'h00; + storage[937] = 8'h00; + storage[938] = 8'h00; + storage[939] = 8'h00; + storage[940] = 8'h00; + storage[941] = 8'h00; + storage[942] = 8'h00; + storage[943] = 8'h00; + storage[944] = 8'h00; + storage[945] = 8'h00; + storage[946] = 8'h00; + storage[947] = 8'h00; + storage[948] = 8'h00; + storage[949] = 8'h00; + storage[950] = 8'h00; + storage[951] = 8'h00; + storage[952] = 8'h00; + storage[953] = 8'h00; + storage[954] = 8'h00; + storage[955] = 8'h00; + storage[956] = 8'h00; + storage[957] = 8'h00; + storage[958] = 8'h00; + storage[959] = 8'h00; + storage[960] = 8'h00; + storage[961] = 8'h00; + storage[962] = 8'h00; + storage[963] = 8'h00; + storage[964] = 8'h00; + storage[965] = 8'h00; + storage[966] = 8'h00; + storage[967] = 8'h00; + storage[968] = 8'h00; + storage[969] = 8'h00; + storage[970] = 8'h00; + storage[971] = 8'h00; + storage[972] = 8'h00; + storage[973] = 8'h00; + storage[974] = 8'h00; + storage[975] = 8'h00; + storage[976] = 8'h00; + storage[977] = 8'h00; + storage[978] = 8'h00; + storage[979] = 8'h00; + storage[980] = 8'h00; + storage[981] = 8'h00; + storage[982] = 8'h00; + storage[983] = 8'h00; + storage[984] = 8'h00; + storage[985] = 8'h00; + storage[986] = 8'h00; + storage[987] = 8'h00; + storage[988] = 8'h00; + storage[989] = 8'h00; + storage[990] = 8'h00; + storage[991] = 8'h00; + storage[992] = 8'h00; + storage[993] = 8'h00; + storage[994] = 8'h00; + storage[995] = 8'h00; + storage[996] = 8'h00; + storage[997] = 8'h00; + storage[998] = 8'h00; + storage[999] = 8'h00; + storage[1000] = 8'h00; + storage[1001] = 8'h00; + storage[1002] = 8'h00; + storage[1003] = 8'h00; + storage[1004] = 8'h00; + storage[1005] = 8'h00; + storage[1006] = 8'h00; + storage[1007] = 8'h00; + storage[1008] = 8'h00; + storage[1009] = 8'h00; + storage[1010] = 8'h00; + storage[1011] = 8'h00; + storage[1012] = 8'h00; + storage[1013] = 8'h00; + storage[1014] = 8'h00; + storage[1015] = 8'h00; + storage[1016] = 8'h00; + storage[1017] = 8'h00; + storage[1018] = 8'h00; + storage[1019] = 8'h00; + storage[1020] = 8'h00; + storage[1021] = 8'h00; + storage[1022] = 8'h00; + storage[1023] = 8'h00; + storage[1024] = 8'h00; + storage[1025] = 8'h00; + storage[1026] = 8'h00; + storage[1027] = 8'h00; + storage[1028] = 8'h00; + storage[1029] = 8'h00; + storage[1030] = 8'h00; + storage[1031] = 8'h00; + storage[1032] = 8'h00; + storage[1033] = 8'h00; + storage[1034] = 8'h00; + storage[1035] = 8'h00; + storage[1036] = 8'h00; + storage[1037] = 8'h00; + storage[1038] = 8'h00; + storage[1039] = 8'h00; + storage[1040] = 8'h00; + storage[1041] = 8'h00; + storage[1042] = 8'h00; + storage[1043] = 8'h00; + storage[1044] = 8'h00; + storage[1045] = 8'h00; + storage[1046] = 8'h00; + storage[1047] = 8'h00; + storage[1048] = 8'h00; + storage[1049] = 8'h00; + storage[1050] = 8'h00; + storage[1051] = 8'h00; + storage[1052] = 8'h00; + storage[1053] = 8'h00; + storage[1054] = 8'h00; + storage[1055] = 8'h00; + storage[1056] = 8'h00; + storage[1057] = 8'h00; + storage[1058] = 8'h00; + storage[1059] = 8'h00; + storage[1060] = 8'h00; + storage[1061] = 8'h00; + storage[1062] = 8'h00; + storage[1063] = 8'h00; + storage[1064] = 8'h00; + storage[1065] = 8'h00; + storage[1066] = 8'h00; + storage[1067] = 8'h00; + storage[1068] = 8'h00; + storage[1069] = 8'h00; + storage[1070] = 8'h00; + storage[1071] = 8'h00; + storage[1072] = 8'h00; + storage[1073] = 8'h00; + storage[1074] = 8'h00; + storage[1075] = 8'h00; + storage[1076] = 8'h00; + storage[1077] = 8'h00; + storage[1078] = 8'h00; + storage[1079] = 8'h00; + storage[1080] = 8'h00; + storage[1081] = 8'h00; + storage[1082] = 8'h00; + storage[1083] = 8'h00; + storage[1084] = 8'h00; + storage[1085] = 8'h00; + storage[1086] = 8'h00; + storage[1087] = 8'h00; + storage[1088] = 8'h00; + storage[1089] = 8'h00; + storage[1090] = 8'h00; + storage[1091] = 8'h00; + storage[1092] = 8'h00; + storage[1093] = 8'h00; + storage[1094] = 8'h00; + storage[1095] = 8'h00; + storage[1096] = 8'h00; + storage[1097] = 8'h00; + storage[1098] = 8'h00; + storage[1099] = 8'h00; + storage[1100] = 8'h00; + storage[1101] = 8'h00; + storage[1102] = 8'h00; + storage[1103] = 8'h00; + storage[1104] = 8'h00; + storage[1105] = 8'h00; + storage[1106] = 8'h00; + storage[1107] = 8'h00; + storage[1108] = 8'h00; + storage[1109] = 8'h00; + storage[1110] = 8'h00; + storage[1111] = 8'h00; + storage[1112] = 8'h00; + storage[1113] = 8'h00; + storage[1114] = 8'h00; + storage[1115] = 8'h00; + storage[1116] = 8'h00; + storage[1117] = 8'h00; + storage[1118] = 8'h00; + storage[1119] = 8'h00; + storage[1120] = 8'h00; + storage[1121] = 8'h00; + storage[1122] = 8'h00; + storage[1123] = 8'h00; + storage[1124] = 8'h00; + storage[1125] = 8'h00; + storage[1126] = 8'h00; + storage[1127] = 8'h00; + storage[1128] = 8'h00; + storage[1129] = 8'h00; + storage[1130] = 8'h00; + storage[1131] = 8'h00; + storage[1132] = 8'h00; + storage[1133] = 8'h00; + storage[1134] = 8'h00; + storage[1135] = 8'h00; + storage[1136] = 8'h00; + storage[1137] = 8'h00; + storage[1138] = 8'h00; + storage[1139] = 8'h00; + storage[1140] = 8'h00; + storage[1141] = 8'h00; + storage[1142] = 8'h00; + storage[1143] = 8'h00; + storage[1144] = 8'h00; + storage[1145] = 8'h00; + storage[1146] = 8'h00; + storage[1147] = 8'h00; + storage[1148] = 8'h00; + storage[1149] = 8'h00; + storage[1150] = 8'h00; + storage[1151] = 8'h00; + storage[1152] = 8'h00; + storage[1153] = 8'h00; + storage[1154] = 8'h00; + storage[1155] = 8'h00; + storage[1156] = 8'h00; + storage[1157] = 8'h00; + storage[1158] = 8'h00; + storage[1159] = 8'h00; + storage[1160] = 8'h00; + storage[1161] = 8'h00; + storage[1162] = 8'h00; + storage[1163] = 8'h00; + storage[1164] = 8'h00; + storage[1165] = 8'h00; + storage[1166] = 8'h00; + storage[1167] = 8'h00; + storage[1168] = 8'h00; + storage[1169] = 8'h00; + storage[1170] = 8'h00; + storage[1171] = 8'h00; + storage[1172] = 8'h00; + storage[1173] = 8'h00; + storage[1174] = 8'h00; + storage[1175] = 8'h00; + storage[1176] = 8'h00; + storage[1177] = 8'h00; + storage[1178] = 8'h00; + storage[1179] = 8'h00; + storage[1180] = 8'h00; + storage[1181] = 8'h00; + storage[1182] = 8'h00; + storage[1183] = 8'h00; + storage[1184] = 8'h00; + storage[1185] = 8'h00; + storage[1186] = 8'h00; + storage[1187] = 8'h00; + storage[1188] = 8'h00; + storage[1189] = 8'h00; + storage[1190] = 8'h00; + storage[1191] = 8'h00; + storage[1192] = 8'h00; + storage[1193] = 8'h00; + storage[1194] = 8'h00; + storage[1195] = 8'h00; + storage[1196] = 8'h00; + storage[1197] = 8'h00; + storage[1198] = 8'h00; + storage[1199] = 8'h00; + storage[1200] = 8'h00; + storage[1201] = 8'h00; + storage[1202] = 8'h00; + storage[1203] = 8'h00; + storage[1204] = 8'h00; + storage[1205] = 8'h00; + storage[1206] = 8'h00; + storage[1207] = 8'h00; + storage[1208] = 8'h00; + storage[1209] = 8'h00; + storage[1210] = 8'h00; + storage[1211] = 8'h00; + storage[1212] = 8'h00; + storage[1213] = 8'h00; + storage[1214] = 8'h00; + storage[1215] = 8'h00; + storage[1216] = 8'h00; + storage[1217] = 8'h00; + storage[1218] = 8'h00; + storage[1219] = 8'h00; + storage[1220] = 8'h00; + storage[1221] = 8'h00; + storage[1222] = 8'h00; + storage[1223] = 8'h00; + storage[1224] = 8'h00; + storage[1225] = 8'h00; + storage[1226] = 8'h00; + storage[1227] = 8'h00; + storage[1228] = 8'h00; + storage[1229] = 8'h00; + storage[1230] = 8'h00; + storage[1231] = 8'h00; + storage[1232] = 8'h00; + storage[1233] = 8'h00; + storage[1234] = 8'h00; + storage[1235] = 8'h00; + storage[1236] = 8'h00; + storage[1237] = 8'h00; + storage[1238] = 8'h00; + storage[1239] = 8'h00; + storage[1240] = 8'h00; + storage[1241] = 8'h00; + storage[1242] = 8'h00; + storage[1243] = 8'h00; + storage[1244] = 8'h00; + storage[1245] = 8'h00; + storage[1246] = 8'h00; + storage[1247] = 8'h00; + storage[1248] = 8'h00; + storage[1249] = 8'h00; + storage[1250] = 8'h00; + storage[1251] = 8'h00; + storage[1252] = 8'h00; + storage[1253] = 8'h00; + storage[1254] = 8'h00; + storage[1255] = 8'h00; + storage[1256] = 8'h00; + storage[1257] = 8'h00; + storage[1258] = 8'h00; + storage[1259] = 8'h00; + storage[1260] = 8'h00; + storage[1261] = 8'h00; + storage[1262] = 8'h00; + storage[1263] = 8'h00; + storage[1264] = 8'h00; + storage[1265] = 8'h00; + storage[1266] = 8'h00; + storage[1267] = 8'h00; + storage[1268] = 8'h00; + storage[1269] = 8'h00; + storage[1270] = 8'h00; + storage[1271] = 8'h00; + storage[1272] = 8'h00; + storage[1273] = 8'h00; + storage[1274] = 8'h00; + storage[1275] = 8'h00; + storage[1276] = 8'h00; + storage[1277] = 8'h00; + storage[1278] = 8'h00; + storage[1279] = 8'h00; + storage[1280] = 8'h00; + storage[1281] = 8'h00; + storage[1282] = 8'h00; + storage[1283] = 8'h00; + storage[1284] = 8'h00; + storage[1285] = 8'h00; + storage[1286] = 8'h00; + storage[1287] = 8'h00; + storage[1288] = 8'h00; + storage[1289] = 8'h00; + storage[1290] = 8'h00; + storage[1291] = 8'h00; + storage[1292] = 8'h00; + storage[1293] = 8'h00; + storage[1294] = 8'h00; + storage[1295] = 8'h00; + storage[1296] = 8'h00; + storage[1297] = 8'h00; + storage[1298] = 8'h00; + storage[1299] = 8'h00; + storage[1300] = 8'h00; + storage[1301] = 8'h00; + storage[1302] = 8'h00; + storage[1303] = 8'h00; + storage[1304] = 8'h00; + storage[1305] = 8'h00; + storage[1306] = 8'h00; + storage[1307] = 8'h00; + storage[1308] = 8'h00; + storage[1309] = 8'h00; + storage[1310] = 8'h00; + storage[1311] = 8'h00; + storage[1312] = 8'h00; + storage[1313] = 8'h00; + storage[1314] = 8'h00; + storage[1315] = 8'h00; + storage[1316] = 8'h00; + storage[1317] = 8'h00; + storage[1318] = 8'h00; + storage[1319] = 8'h00; + storage[1320] = 8'h00; + storage[1321] = 8'h00; + storage[1322] = 8'h00; + storage[1323] = 8'h00; + storage[1324] = 8'h00; + storage[1325] = 8'h00; + storage[1326] = 8'h00; + storage[1327] = 8'h00; + storage[1328] = 8'h00; + storage[1329] = 8'h00; + storage[1330] = 8'h00; + storage[1331] = 8'h00; + storage[1332] = 8'h00; + storage[1333] = 8'h00; + storage[1334] = 8'h00; + storage[1335] = 8'h00; + storage[1336] = 8'h00; + storage[1337] = 8'h00; + storage[1338] = 8'h00; + storage[1339] = 8'h00; + storage[1340] = 8'h00; + storage[1341] = 8'h00; + storage[1342] = 8'h00; + storage[1343] = 8'h00; + storage[1344] = 8'h00; + storage[1345] = 8'h00; + storage[1346] = 8'h00; + storage[1347] = 8'h00; + storage[1348] = 8'h00; + storage[1349] = 8'h00; + storage[1350] = 8'h00; + storage[1351] = 8'h00; + storage[1352] = 8'h00; + storage[1353] = 8'h00; + storage[1354] = 8'h00; + storage[1355] = 8'h00; + storage[1356] = 8'h00; + storage[1357] = 8'h00; + storage[1358] = 8'h00; + storage[1359] = 8'h00; + storage[1360] = 8'h00; + storage[1361] = 8'h00; + storage[1362] = 8'h00; + storage[1363] = 8'h00; + storage[1364] = 8'h00; + storage[1365] = 8'h00; + storage[1366] = 8'h00; + storage[1367] = 8'h00; + storage[1368] = 8'h00; + storage[1369] = 8'h00; + storage[1370] = 8'h00; + storage[1371] = 8'h00; + storage[1372] = 8'h00; + storage[1373] = 8'h00; + storage[1374] = 8'h00; + storage[1375] = 8'h00; + storage[1376] = 8'h00; + storage[1377] = 8'h00; + storage[1378] = 8'h00; + storage[1379] = 8'h00; + storage[1380] = 8'h00; + storage[1381] = 8'h00; + storage[1382] = 8'h00; + storage[1383] = 8'h00; + storage[1384] = 8'h00; + storage[1385] = 8'h00; + storage[1386] = 8'h00; + storage[1387] = 8'h00; + storage[1388] = 8'h00; + storage[1389] = 8'h00; + storage[1390] = 8'h00; + storage[1391] = 8'h00; + storage[1392] = 8'h00; + storage[1393] = 8'h00; + storage[1394] = 8'h00; + storage[1395] = 8'h00; + storage[1396] = 8'h00; + storage[1397] = 8'h00; + storage[1398] = 8'h00; + storage[1399] = 8'h00; + storage[1400] = 8'h00; + storage[1401] = 8'h00; + storage[1402] = 8'h00; + storage[1403] = 8'h00; + storage[1404] = 8'h00; + storage[1405] = 8'h00; + storage[1406] = 8'h00; + storage[1407] = 8'h00; + storage[1408] = 8'h00; + storage[1409] = 8'h00; + storage[1410] = 8'h00; + storage[1411] = 8'h00; + storage[1412] = 8'h00; + storage[1413] = 8'h00; + storage[1414] = 8'h00; + storage[1415] = 8'h00; + storage[1416] = 8'h00; + storage[1417] = 8'h00; + storage[1418] = 8'h00; + storage[1419] = 8'h00; + storage[1420] = 8'h00; + storage[1421] = 8'h00; + storage[1422] = 8'h00; + storage[1423] = 8'h00; + storage[1424] = 8'h00; + storage[1425] = 8'h00; + storage[1426] = 8'h00; + storage[1427] = 8'h00; + storage[1428] = 8'h00; + storage[1429] = 8'h00; + storage[1430] = 8'h00; + storage[1431] = 8'h00; + storage[1432] = 8'h00; + storage[1433] = 8'h00; + storage[1434] = 8'h00; + storage[1435] = 8'h00; + storage[1436] = 8'h00; + storage[1437] = 8'h00; + storage[1438] = 8'h00; + storage[1439] = 8'h00; + storage[1440] = 8'h00; + storage[1441] = 8'h00; + storage[1442] = 8'h00; + storage[1443] = 8'h00; + storage[1444] = 8'h00; + storage[1445] = 8'h00; + storage[1446] = 8'h00; + storage[1447] = 8'h00; + storage[1448] = 8'h00; + storage[1449] = 8'h00; + storage[1450] = 8'h00; + storage[1451] = 8'h00; + storage[1452] = 8'h00; + storage[1453] = 8'h00; + storage[1454] = 8'h00; + storage[1455] = 8'h00; + storage[1456] = 8'h00; + storage[1457] = 8'h00; + storage[1458] = 8'h00; + storage[1459] = 8'h00; + storage[1460] = 8'h00; + storage[1461] = 8'h00; + storage[1462] = 8'h00; + storage[1463] = 8'h00; + storage[1464] = 8'h00; + storage[1465] = 8'h00; + storage[1466] = 8'h00; + storage[1467] = 8'h00; + storage[1468] = 8'h00; + storage[1469] = 8'h00; + storage[1470] = 8'h00; + storage[1471] = 8'h00; + storage[1472] = 8'h00; + storage[1473] = 8'h00; + storage[1474] = 8'h00; + storage[1475] = 8'h00; + storage[1476] = 8'h00; + storage[1477] = 8'h00; + storage[1478] = 8'h00; + storage[1479] = 8'h00; + storage[1480] = 8'h00; + storage[1481] = 8'h00; + storage[1482] = 8'h00; + storage[1483] = 8'h00; + storage[1484] = 8'h00; + storage[1485] = 8'h00; + storage[1486] = 8'h00; + storage[1487] = 8'h00; + storage[1488] = 8'h00; + storage[1489] = 8'h00; + storage[1490] = 8'h00; + storage[1491] = 8'h00; + storage[1492] = 8'h00; + storage[1493] = 8'h00; + storage[1494] = 8'h00; + storage[1495] = 8'h00; + storage[1496] = 8'h00; + storage[1497] = 8'h00; + storage[1498] = 8'h00; + storage[1499] = 8'h00; + storage[1500] = 8'h00; + storage[1501] = 8'h00; + storage[1502] = 8'h00; + storage[1503] = 8'h00; + storage[1504] = 8'h00; + storage[1505] = 8'h00; + storage[1506] = 8'h00; + storage[1507] = 8'h00; + storage[1508] = 8'h00; + storage[1509] = 8'h00; + storage[1510] = 8'h00; + storage[1511] = 8'h00; + storage[1512] = 8'h00; + storage[1513] = 8'h00; + storage[1514] = 8'h00; + storage[1515] = 8'h00; + storage[1516] = 8'h00; + storage[1517] = 8'h00; + storage[1518] = 8'h00; + storage[1519] = 8'h00; + storage[1520] = 8'h00; + storage[1521] = 8'h00; + storage[1522] = 8'h00; + storage[1523] = 8'h00; + storage[1524] = 8'h00; + storage[1525] = 8'h00; + storage[1526] = 8'h00; + storage[1527] = 8'h00; + storage[1528] = 8'h00; + storage[1529] = 8'h00; + storage[1530] = 8'h00; + storage[1531] = 8'h00; + storage[1532] = 8'h00; + storage[1533] = 8'h00; + storage[1534] = 8'h00; + storage[1535] = 8'h00; + storage[1536] = 8'h00; + storage[1537] = 8'h00; + storage[1538] = 8'h00; + storage[1539] = 8'h00; + storage[1540] = 8'h00; + storage[1541] = 8'h00; + storage[1542] = 8'h00; + storage[1543] = 8'h00; + storage[1544] = 8'h00; + storage[1545] = 8'h00; + storage[1546] = 8'h00; + storage[1547] = 8'h00; + storage[1548] = 8'h00; + storage[1549] = 8'h00; + storage[1550] = 8'h00; + storage[1551] = 8'h00; + storage[1552] = 8'h00; + storage[1553] = 8'h00; + storage[1554] = 8'h00; + storage[1555] = 8'h00; + storage[1556] = 8'h00; + storage[1557] = 8'h00; + storage[1558] = 8'h00; + storage[1559] = 8'h00; + storage[1560] = 8'h00; + storage[1561] = 8'h00; + storage[1562] = 8'h00; + storage[1563] = 8'h00; + storage[1564] = 8'h00; + storage[1565] = 8'h00; + storage[1566] = 8'h00; + storage[1567] = 8'h00; + storage[1568] = 8'h00; + storage[1569] = 8'h00; + storage[1570] = 8'h00; + storage[1571] = 8'h00; + storage[1572] = 8'h00; + storage[1573] = 8'h00; + storage[1574] = 8'h00; + storage[1575] = 8'h00; + storage[1576] = 8'h00; + storage[1577] = 8'h00; + storage[1578] = 8'h00; + storage[1579] = 8'h00; + storage[1580] = 8'h00; + storage[1581] = 8'h00; + storage[1582] = 8'h00; + storage[1583] = 8'h00; + storage[1584] = 8'h00; + storage[1585] = 8'h00; + storage[1586] = 8'h00; + storage[1587] = 8'h00; + storage[1588] = 8'h00; + storage[1589] = 8'h00; + storage[1590] = 8'h00; + storage[1591] = 8'h00; + storage[1592] = 8'h00; + storage[1593] = 8'h00; + storage[1594] = 8'h00; + storage[1595] = 8'h00; + storage[1596] = 8'h00; + storage[1597] = 8'h00; + storage[1598] = 8'h00; + storage[1599] = 8'h00; + storage[1600] = 8'h00; + storage[1601] = 8'h00; + storage[1602] = 8'h00; + storage[1603] = 8'h00; + storage[1604] = 8'h00; + storage[1605] = 8'h00; + storage[1606] = 8'h00; + storage[1607] = 8'h00; + storage[1608] = 8'h00; + storage[1609] = 8'h00; + storage[1610] = 8'h00; + storage[1611] = 8'h00; + storage[1612] = 8'h00; + storage[1613] = 8'h00; + storage[1614] = 8'h00; + storage[1615] = 8'h00; + storage[1616] = 8'h00; + storage[1617] = 8'h00; + storage[1618] = 8'h00; + storage[1619] = 8'h00; + storage[1620] = 8'h00; + storage[1621] = 8'h00; + storage[1622] = 8'h00; + storage[1623] = 8'h00; + storage[1624] = 8'h00; + storage[1625] = 8'h00; + storage[1626] = 8'h00; + storage[1627] = 8'h00; + storage[1628] = 8'h00; + storage[1629] = 8'h00; + storage[1630] = 8'h00; + storage[1631] = 8'h00; + storage[1632] = 8'h00; + storage[1633] = 8'h00; + storage[1634] = 8'h00; + storage[1635] = 8'h00; + storage[1636] = 8'h00; + storage[1637] = 8'h00; + storage[1638] = 8'h00; + storage[1639] = 8'h00; + storage[1640] = 8'h00; + storage[1641] = 8'h00; + storage[1642] = 8'h00; + storage[1643] = 8'h00; + storage[1644] = 8'h00; + storage[1645] = 8'h00; + storage[1646] = 8'h00; + storage[1647] = 8'h00; + storage[1648] = 8'h00; + storage[1649] = 8'h00; + storage[1650] = 8'h00; + storage[1651] = 8'h00; + storage[1652] = 8'h00; + storage[1653] = 8'h00; + storage[1654] = 8'h00; + storage[1655] = 8'h00; + storage[1656] = 8'h00; + storage[1657] = 8'h00; + storage[1658] = 8'h00; + storage[1659] = 8'h00; + storage[1660] = 8'h00; + storage[1661] = 8'h00; + storage[1662] = 8'h00; + storage[1663] = 8'h00; + storage[1664] = 8'h00; + storage[1665] = 8'h00; + storage[1666] = 8'h00; + storage[1667] = 8'h00; + storage[1668] = 8'h00; + storage[1669] = 8'h00; + storage[1670] = 8'h00; + storage[1671] = 8'h00; + storage[1672] = 8'h00; + storage[1673] = 8'h00; + storage[1674] = 8'h00; + storage[1675] = 8'h00; + storage[1676] = 8'h00; + storage[1677] = 8'h00; + storage[1678] = 8'h00; + storage[1679] = 8'h00; + storage[1680] = 8'h00; + storage[1681] = 8'h00; + storage[1682] = 8'h00; + storage[1683] = 8'h00; + storage[1684] = 8'h00; + storage[1685] = 8'h00; + storage[1686] = 8'h00; + storage[1687] = 8'h00; + storage[1688] = 8'h00; + storage[1689] = 8'h00; + storage[1690] = 8'h00; + storage[1691] = 8'h00; + storage[1692] = 8'h00; + storage[1693] = 8'h00; + storage[1694] = 8'h00; + storage[1695] = 8'h00; + storage[1696] = 8'h00; + storage[1697] = 8'h00; + storage[1698] = 8'h00; + storage[1699] = 8'h00; + storage[1700] = 8'h00; + storage[1701] = 8'h00; + storage[1702] = 8'h00; + storage[1703] = 8'h00; + storage[1704] = 8'h00; + storage[1705] = 8'h00; + storage[1706] = 8'h00; + storage[1707] = 8'h00; + storage[1708] = 8'h00; + storage[1709] = 8'h00; + storage[1710] = 8'h00; + storage[1711] = 8'h00; + storage[1712] = 8'h00; + storage[1713] = 8'h00; + storage[1714] = 8'h00; + storage[1715] = 8'h00; + storage[1716] = 8'h00; + storage[1717] = 8'h00; + storage[1718] = 8'h00; + storage[1719] = 8'h00; + storage[1720] = 8'h00; + storage[1721] = 8'h00; + storage[1722] = 8'h00; + storage[1723] = 8'h00; + storage[1724] = 8'h00; + storage[1725] = 8'h00; + storage[1726] = 8'h00; + storage[1727] = 8'h00; + storage[1728] = 8'h00; + storage[1729] = 8'h00; + storage[1730] = 8'h00; + storage[1731] = 8'h00; + storage[1732] = 8'h00; + storage[1733] = 8'h00; + storage[1734] = 8'h00; + storage[1735] = 8'h00; + storage[1736] = 8'h00; + storage[1737] = 8'h00; + storage[1738] = 8'h00; + storage[1739] = 8'h00; + storage[1740] = 8'h00; + storage[1741] = 8'h00; + storage[1742] = 8'h00; + storage[1743] = 8'h00; + storage[1744] = 8'h00; + storage[1745] = 8'h00; + storage[1746] = 8'h00; + storage[1747] = 8'h00; + storage[1748] = 8'h00; + storage[1749] = 8'h00; + storage[1750] = 8'h00; + storage[1751] = 8'h00; + storage[1752] = 8'h00; + storage[1753] = 8'h00; + storage[1754] = 8'h00; + storage[1755] = 8'h00; + storage[1756] = 8'h00; + storage[1757] = 8'h00; + storage[1758] = 8'h00; + storage[1759] = 8'h00; + storage[1760] = 8'h00; + storage[1761] = 8'h00; + storage[1762] = 8'h00; + storage[1763] = 8'h00; + storage[1764] = 8'h00; + storage[1765] = 8'h00; + storage[1766] = 8'h00; + storage[1767] = 8'h00; + storage[1768] = 8'h00; + storage[1769] = 8'h00; + storage[1770] = 8'h00; + storage[1771] = 8'h00; + storage[1772] = 8'h00; + storage[1773] = 8'h00; + storage[1774] = 8'h00; + storage[1775] = 8'h00; + storage[1776] = 8'h00; + storage[1777] = 8'h00; + storage[1778] = 8'h00; + storage[1779] = 8'h00; + storage[1780] = 8'h00; + storage[1781] = 8'h00; + storage[1782] = 8'h00; + storage[1783] = 8'h00; + storage[1784] = 8'h00; + storage[1785] = 8'h00; + storage[1786] = 8'h00; + storage[1787] = 8'h00; + storage[1788] = 8'h00; + storage[1789] = 8'h00; + storage[1790] = 8'h00; + storage[1791] = 8'h00; + storage[1792] = 8'h00; + storage[1793] = 8'h00; + storage[1794] = 8'h00; + storage[1795] = 8'h00; + storage[1796] = 8'h00; + storage[1797] = 8'h00; + storage[1798] = 8'h00; + storage[1799] = 8'h00; + storage[1800] = 8'h00; + storage[1801] = 8'h00; + storage[1802] = 8'h00; + storage[1803] = 8'h00; + storage[1804] = 8'h00; + storage[1805] = 8'h00; + storage[1806] = 8'h00; + storage[1807] = 8'h00; + storage[1808] = 8'h00; + storage[1809] = 8'h00; + storage[1810] = 8'h00; + storage[1811] = 8'h00; + storage[1812] = 8'h00; + storage[1813] = 8'h00; + storage[1814] = 8'h00; + storage[1815] = 8'h00; + storage[1816] = 8'h00; + storage[1817] = 8'h00; + storage[1818] = 8'h00; + storage[1819] = 8'h00; + storage[1820] = 8'h00; + storage[1821] = 8'h00; + storage[1822] = 8'h00; + storage[1823] = 8'h00; + storage[1824] = 8'h00; + storage[1825] = 8'h00; + storage[1826] = 8'h00; + storage[1827] = 8'h00; + storage[1828] = 8'h00; + storage[1829] = 8'h00; + storage[1830] = 8'h00; + storage[1831] = 8'h00; + storage[1832] = 8'h00; + storage[1833] = 8'h00; + storage[1834] = 8'h00; + storage[1835] = 8'h00; + storage[1836] = 8'h00; + storage[1837] = 8'h00; + storage[1838] = 8'h00; + storage[1839] = 8'h00; + storage[1840] = 8'h00; + storage[1841] = 8'h00; + storage[1842] = 8'h00; + storage[1843] = 8'h00; + storage[1844] = 8'h00; + storage[1845] = 8'h00; + storage[1846] = 8'h00; + storage[1847] = 8'h00; + storage[1848] = 8'h00; + storage[1849] = 8'h00; + storage[1850] = 8'h00; + storage[1851] = 8'h00; + storage[1852] = 8'h00; + storage[1853] = 8'h00; + storage[1854] = 8'h00; + storage[1855] = 8'h00; + storage[1856] = 8'h00; + storage[1857] = 8'h00; + storage[1858] = 8'h00; + storage[1859] = 8'h00; + storage[1860] = 8'h00; + storage[1861] = 8'h00; + storage[1862] = 8'h00; + storage[1863] = 8'h00; + storage[1864] = 8'h00; + storage[1865] = 8'h00; + storage[1866] = 8'h00; + storage[1867] = 8'h00; + storage[1868] = 8'h00; + storage[1869] = 8'h00; + storage[1870] = 8'h00; + storage[1871] = 8'h00; + storage[1872] = 8'h00; + storage[1873] = 8'h00; + storage[1874] = 8'h00; + storage[1875] = 8'h00; + storage[1876] = 8'h00; + storage[1877] = 8'h00; + storage[1878] = 8'h00; + storage[1879] = 8'h00; + storage[1880] = 8'h00; + storage[1881] = 8'h00; + storage[1882] = 8'h00; + storage[1883] = 8'h00; + storage[1884] = 8'h00; + storage[1885] = 8'h00; + storage[1886] = 8'h00; + storage[1887] = 8'h00; + storage[1888] = 8'h00; + storage[1889] = 8'h00; + storage[1890] = 8'h00; + storage[1891] = 8'h00; + storage[1892] = 8'h00; + storage[1893] = 8'h00; + storage[1894] = 8'h00; + storage[1895] = 8'h00; + storage[1896] = 8'h00; + storage[1897] = 8'h00; + storage[1898] = 8'h00; + storage[1899] = 8'h00; + storage[1900] = 8'h00; + storage[1901] = 8'h00; + storage[1902] = 8'h00; + storage[1903] = 8'h00; + storage[1904] = 8'h00; + storage[1905] = 8'h00; + storage[1906] = 8'h00; + storage[1907] = 8'h00; + storage[1908] = 8'h00; + storage[1909] = 8'h00; + storage[1910] = 8'h00; + storage[1911] = 8'h00; + storage[1912] = 8'h00; + storage[1913] = 8'h00; + storage[1914] = 8'h00; + storage[1915] = 8'h00; + storage[1916] = 8'h00; + storage[1917] = 8'h00; + storage[1918] = 8'h00; + storage[1919] = 8'h00; + storage[1920] = 8'h00; + storage[1921] = 8'h00; + storage[1922] = 8'h00; + storage[1923] = 8'h00; + storage[1924] = 8'h00; + storage[1925] = 8'h00; + storage[1926] = 8'h00; + storage[1927] = 8'h00; + storage[1928] = 8'h00; + storage[1929] = 8'h00; + storage[1930] = 8'h00; + storage[1931] = 8'h00; + storage[1932] = 8'h00; + storage[1933] = 8'h00; + storage[1934] = 8'h00; + storage[1935] = 8'h00; + storage[1936] = 8'h00; + storage[1937] = 8'h00; + storage[1938] = 8'h00; + storage[1939] = 8'h00; + storage[1940] = 8'h00; + storage[1941] = 8'h00; + storage[1942] = 8'h00; + storage[1943] = 8'h00; + storage[1944] = 8'h00; + storage[1945] = 8'h00; + storage[1946] = 8'h00; + storage[1947] = 8'h00; + storage[1948] = 8'h00; + storage[1949] = 8'h00; + storage[1950] = 8'h00; + storage[1951] = 8'h00; + storage[1952] = 8'h00; + storage[1953] = 8'h00; + storage[1954] = 8'h00; + storage[1955] = 8'h00; + storage[1956] = 8'h00; + storage[1957] = 8'h00; + storage[1958] = 8'h00; + storage[1959] = 8'h00; + storage[1960] = 8'h00; + storage[1961] = 8'h00; + storage[1962] = 8'h00; + storage[1963] = 8'h00; + storage[1964] = 8'h00; + storage[1965] = 8'h00; + storage[1966] = 8'h00; + storage[1967] = 8'h00; + storage[1968] = 8'h00; + storage[1969] = 8'h00; + storage[1970] = 8'h00; + storage[1971] = 8'h00; + storage[1972] = 8'h00; + storage[1973] = 8'h00; + storage[1974] = 8'h00; + storage[1975] = 8'h00; + storage[1976] = 8'h00; + storage[1977] = 8'h00; + storage[1978] = 8'h00; + storage[1979] = 8'h00; + storage[1980] = 8'h00; + storage[1981] = 8'h00; + storage[1982] = 8'h00; + storage[1983] = 8'h00; + storage[1984] = 8'h00; + storage[1985] = 8'h00; + storage[1986] = 8'h00; + storage[1987] = 8'h00; + storage[1988] = 8'h00; + storage[1989] = 8'h00; + storage[1990] = 8'h00; + storage[1991] = 8'h00; + storage[1992] = 8'h00; + storage[1993] = 8'h00; + storage[1994] = 8'h00; + storage[1995] = 8'h00; + storage[1996] = 8'h00; + storage[1997] = 8'h00; + storage[1998] = 8'h00; + storage[1999] = 8'h00; + storage[2000] = 8'h00; + storage[2001] = 8'h00; + storage[2002] = 8'h00; + storage[2003] = 8'h00; + storage[2004] = 8'h00; + storage[2005] = 8'h00; + storage[2006] = 8'h00; + storage[2007] = 8'h00; + storage[2008] = 8'h00; + storage[2009] = 8'h00; + storage[2010] = 8'h00; + storage[2011] = 8'h00; + storage[2012] = 8'h00; + storage[2013] = 8'h00; + storage[2014] = 8'h00; + storage[2015] = 8'h00; + storage[2016] = 8'h00; + storage[2017] = 8'h00; + storage[2018] = 8'h00; + storage[2019] = 8'h00; + storage[2020] = 8'h00; + storage[2021] = 8'h00; + storage[2022] = 8'h00; + storage[2023] = 8'h00; + storage[2024] = 8'h00; + storage[2025] = 8'h00; + storage[2026] = 8'h00; + storage[2027] = 8'h00; + storage[2028] = 8'h00; + storage[2029] = 8'h00; + storage[2030] = 8'h00; + storage[2031] = 8'h00; + storage[2032] = 8'h00; + storage[2033] = 8'h00; + storage[2034] = 8'h00; + storage[2035] = 8'h00; + storage[2036] = 8'h00; + storage[2037] = 8'h00; + storage[2038] = 8'h00; + storage[2039] = 8'h00; + storage[2040] = 8'h00; + storage[2041] = 8'h00; + storage[2042] = 8'h00; + storage[2043] = 8'h00; + storage[2044] = 8'h00; + storage[2045] = 8'h00; + storage[2046] = 8'h00; + end + always @(posedge clk) begin + if (storage_w_en) + storage[storage_w_addr] <= storage_w_data; + end + reg [7:0] _0_; + always @(posedge clk) begin + if (storage_r_en) begin + _0_ <= storage[storage_r_addr]; + end + end + assign storage_r_data = _0_; + assign \$11 = produce + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$14 = produce == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 11'h7fe; + assign \$13 = \$14 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 12'h000 : \$11 ; + assign \$17 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$20 = consume + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$23 = consume == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 11'h7fe; + assign \$22 = \$23 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 12'h000 : \$20 ; + assign \$26 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$2 = level != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) 11'h7ff; + assign \$29 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$28 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$29 ; + assign \$32 = \$26 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$28 ; + assign \$35 = level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) 1'h1; + assign \$37 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$40 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$39 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$40 ; + assign \$43 = \$37 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$39 ; + assign \$46 = level - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) 1'h1; + assign \$4 = | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) level; + assign \$6 = w_en & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) w_rdy; + assign \$8 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + always @(posedge clk) + level <= \level$next ; + always @(posedge clk) + consume <= \consume$next ; + always @(posedge clk) + produce <= \produce$next ; + always @* begin + if (\initial ) begin end + \consume$next = consume; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" *) + casez (\$17 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" */ + 1'h1: + \consume$next = \$22 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \consume$next = 11'h000; + endcase + end + always @* begin + if (\initial ) begin end + \level$next = level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + casez (\$32 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" */ + 1'h1: + \level$next = \$35 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + casez (\$43 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" */ + 1'h1: + \level$next = \$46 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \level$next = 11'h000; + endcase + end + always @* begin + if (\initial ) begin end + \produce$next = produce; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" *) + casez (\$8 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" */ + 1'h1: + \produce$next = \$13 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \produce$next = 11'h000; + endcase + end + assign \$10 = \$13 ; + assign \$19 = \$22 ; + assign \$34 = \$35 ; + assign \$45 = \$46 ; + assign storage_r_en = r_en; + assign r_data = storage_r_data; + assign storage_r_addr = consume; + assign storage_w_en = \$6 ; + assign storage_w_data = w_data; + assign storage_w_addr = produce; + assign r_level = level; + assign w_level = level; + assign r_rdy = \$4 ; + assign w_rdy = \$2 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined.fifo_b.unbuffered" *) +(* generator = "nMigen" *) +module \unbuffered$1 (clk, w_data, w_en, w_rdy, r_data, r_en, r_rdy, level, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$11 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$13 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$17 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$19 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) + wire \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$20 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [11:0] \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$23 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$26 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$28 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$29 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$32 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [11:0] \$34 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [11:0] \$35 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$37 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$39 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) + wire \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$40 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$43 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [11:0] \$45 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [11:0] \$46 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) + wire \$6 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [10:0] consume = 11'h000; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [10:0] \consume$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + output [10:0] level; + reg [10:0] level = 11'h000; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + reg [10:0] \level$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [10:0] produce = 11'h000; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [10:0] \produce$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [10:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [10:0] storage_r_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [7:0] storage_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire storage_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [10:0] storage_w_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [7:0] storage_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire storage_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [10:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + reg [7:0] storage [2046:0]; + initial begin + storage[0] = 8'h00; + storage[1] = 8'h00; + storage[2] = 8'h00; + storage[3] = 8'h00; + storage[4] = 8'h00; + storage[5] = 8'h00; + storage[6] = 8'h00; + storage[7] = 8'h00; + storage[8] = 8'h00; + storage[9] = 8'h00; + storage[10] = 8'h00; + storage[11] = 8'h00; + storage[12] = 8'h00; + storage[13] = 8'h00; + storage[14] = 8'h00; + storage[15] = 8'h00; + storage[16] = 8'h00; + storage[17] = 8'h00; + storage[18] = 8'h00; + storage[19] = 8'h00; + storage[20] = 8'h00; + storage[21] = 8'h00; + storage[22] = 8'h00; + storage[23] = 8'h00; + storage[24] = 8'h00; + storage[25] = 8'h00; + storage[26] = 8'h00; + storage[27] = 8'h00; + storage[28] = 8'h00; + storage[29] = 8'h00; + storage[30] = 8'h00; + storage[31] = 8'h00; + storage[32] = 8'h00; + storage[33] = 8'h00; + storage[34] = 8'h00; + storage[35] = 8'h00; + storage[36] = 8'h00; + storage[37] = 8'h00; + storage[38] = 8'h00; + storage[39] = 8'h00; + storage[40] = 8'h00; + storage[41] = 8'h00; + storage[42] = 8'h00; + storage[43] = 8'h00; + storage[44] = 8'h00; + storage[45] = 8'h00; + storage[46] = 8'h00; + storage[47] = 8'h00; + storage[48] = 8'h00; + storage[49] = 8'h00; + storage[50] = 8'h00; + storage[51] = 8'h00; + storage[52] = 8'h00; + storage[53] = 8'h00; + storage[54] = 8'h00; + storage[55] = 8'h00; + storage[56] = 8'h00; + storage[57] = 8'h00; + storage[58] = 8'h00; + storage[59] = 8'h00; + storage[60] = 8'h00; + storage[61] = 8'h00; + storage[62] = 8'h00; + storage[63] = 8'h00; + storage[64] = 8'h00; + storage[65] = 8'h00; + storage[66] = 8'h00; + storage[67] = 8'h00; + storage[68] = 8'h00; + storage[69] = 8'h00; + storage[70] = 8'h00; + storage[71] = 8'h00; + storage[72] = 8'h00; + storage[73] = 8'h00; + storage[74] = 8'h00; + storage[75] = 8'h00; + storage[76] = 8'h00; + storage[77] = 8'h00; + storage[78] = 8'h00; + storage[79] = 8'h00; + storage[80] = 8'h00; + storage[81] = 8'h00; + storage[82] = 8'h00; + storage[83] = 8'h00; + storage[84] = 8'h00; + storage[85] = 8'h00; + storage[86] = 8'h00; + storage[87] = 8'h00; + storage[88] = 8'h00; + storage[89] = 8'h00; + storage[90] = 8'h00; + storage[91] = 8'h00; + storage[92] = 8'h00; + storage[93] = 8'h00; + storage[94] = 8'h00; + storage[95] = 8'h00; + storage[96] = 8'h00; + storage[97] = 8'h00; + storage[98] = 8'h00; + storage[99] = 8'h00; + storage[100] = 8'h00; + storage[101] = 8'h00; + storage[102] = 8'h00; + storage[103] = 8'h00; + storage[104] = 8'h00; + storage[105] = 8'h00; + storage[106] = 8'h00; + storage[107] = 8'h00; + storage[108] = 8'h00; + storage[109] = 8'h00; + storage[110] = 8'h00; + storage[111] = 8'h00; + storage[112] = 8'h00; + storage[113] = 8'h00; + storage[114] = 8'h00; + storage[115] = 8'h00; + storage[116] = 8'h00; + storage[117] = 8'h00; + storage[118] = 8'h00; + storage[119] = 8'h00; + storage[120] = 8'h00; + storage[121] = 8'h00; + storage[122] = 8'h00; + storage[123] = 8'h00; + storage[124] = 8'h00; + storage[125] = 8'h00; + storage[126] = 8'h00; + storage[127] = 8'h00; + storage[128] = 8'h00; + storage[129] = 8'h00; + storage[130] = 8'h00; + storage[131] = 8'h00; + storage[132] = 8'h00; + storage[133] = 8'h00; + storage[134] = 8'h00; + storage[135] = 8'h00; + storage[136] = 8'h00; + storage[137] = 8'h00; + storage[138] = 8'h00; + storage[139] = 8'h00; + storage[140] = 8'h00; + storage[141] = 8'h00; + storage[142] = 8'h00; + storage[143] = 8'h00; + storage[144] = 8'h00; + storage[145] = 8'h00; + storage[146] = 8'h00; + storage[147] = 8'h00; + storage[148] = 8'h00; + storage[149] = 8'h00; + storage[150] = 8'h00; + storage[151] = 8'h00; + storage[152] = 8'h00; + storage[153] = 8'h00; + storage[154] = 8'h00; + storage[155] = 8'h00; + storage[156] = 8'h00; + storage[157] = 8'h00; + storage[158] = 8'h00; + storage[159] = 8'h00; + storage[160] = 8'h00; + storage[161] = 8'h00; + storage[162] = 8'h00; + storage[163] = 8'h00; + storage[164] = 8'h00; + storage[165] = 8'h00; + storage[166] = 8'h00; + storage[167] = 8'h00; + storage[168] = 8'h00; + storage[169] = 8'h00; + storage[170] = 8'h00; + storage[171] = 8'h00; + storage[172] = 8'h00; + storage[173] = 8'h00; + storage[174] = 8'h00; + storage[175] = 8'h00; + storage[176] = 8'h00; + storage[177] = 8'h00; + storage[178] = 8'h00; + storage[179] = 8'h00; + storage[180] = 8'h00; + storage[181] = 8'h00; + storage[182] = 8'h00; + storage[183] = 8'h00; + storage[184] = 8'h00; + storage[185] = 8'h00; + storage[186] = 8'h00; + storage[187] = 8'h00; + storage[188] = 8'h00; + storage[189] = 8'h00; + storage[190] = 8'h00; + storage[191] = 8'h00; + storage[192] = 8'h00; + storage[193] = 8'h00; + storage[194] = 8'h00; + storage[195] = 8'h00; + storage[196] = 8'h00; + storage[197] = 8'h00; + storage[198] = 8'h00; + storage[199] = 8'h00; + storage[200] = 8'h00; + storage[201] = 8'h00; + storage[202] = 8'h00; + storage[203] = 8'h00; + storage[204] = 8'h00; + storage[205] = 8'h00; + storage[206] = 8'h00; + storage[207] = 8'h00; + storage[208] = 8'h00; + storage[209] = 8'h00; + storage[210] = 8'h00; + storage[211] = 8'h00; + storage[212] = 8'h00; + storage[213] = 8'h00; + storage[214] = 8'h00; + storage[215] = 8'h00; + storage[216] = 8'h00; + storage[217] = 8'h00; + storage[218] = 8'h00; + storage[219] = 8'h00; + storage[220] = 8'h00; + storage[221] = 8'h00; + storage[222] = 8'h00; + storage[223] = 8'h00; + storage[224] = 8'h00; + storage[225] = 8'h00; + storage[226] = 8'h00; + storage[227] = 8'h00; + storage[228] = 8'h00; + storage[229] = 8'h00; + storage[230] = 8'h00; + storage[231] = 8'h00; + storage[232] = 8'h00; + storage[233] = 8'h00; + storage[234] = 8'h00; + storage[235] = 8'h00; + storage[236] = 8'h00; + storage[237] = 8'h00; + storage[238] = 8'h00; + storage[239] = 8'h00; + storage[240] = 8'h00; + storage[241] = 8'h00; + storage[242] = 8'h00; + storage[243] = 8'h00; + storage[244] = 8'h00; + storage[245] = 8'h00; + storage[246] = 8'h00; + storage[247] = 8'h00; + storage[248] = 8'h00; + storage[249] = 8'h00; + storage[250] = 8'h00; + storage[251] = 8'h00; + storage[252] = 8'h00; + storage[253] = 8'h00; + storage[254] = 8'h00; + storage[255] = 8'h00; + storage[256] = 8'h00; + storage[257] = 8'h00; + storage[258] = 8'h00; + storage[259] = 8'h00; + storage[260] = 8'h00; + storage[261] = 8'h00; + storage[262] = 8'h00; + storage[263] = 8'h00; + storage[264] = 8'h00; + storage[265] = 8'h00; + storage[266] = 8'h00; + storage[267] = 8'h00; + storage[268] = 8'h00; + storage[269] = 8'h00; + storage[270] = 8'h00; + storage[271] = 8'h00; + storage[272] = 8'h00; + storage[273] = 8'h00; + storage[274] = 8'h00; + storage[275] = 8'h00; + storage[276] = 8'h00; + storage[277] = 8'h00; + storage[278] = 8'h00; + storage[279] = 8'h00; + storage[280] = 8'h00; + storage[281] = 8'h00; + storage[282] = 8'h00; + storage[283] = 8'h00; + storage[284] = 8'h00; + storage[285] = 8'h00; + storage[286] = 8'h00; + storage[287] = 8'h00; + storage[288] = 8'h00; + storage[289] = 8'h00; + storage[290] = 8'h00; + storage[291] = 8'h00; + storage[292] = 8'h00; + storage[293] = 8'h00; + storage[294] = 8'h00; + storage[295] = 8'h00; + storage[296] = 8'h00; + storage[297] = 8'h00; + storage[298] = 8'h00; + storage[299] = 8'h00; + storage[300] = 8'h00; + storage[301] = 8'h00; + storage[302] = 8'h00; + storage[303] = 8'h00; + storage[304] = 8'h00; + storage[305] = 8'h00; + storage[306] = 8'h00; + storage[307] = 8'h00; + storage[308] = 8'h00; + storage[309] = 8'h00; + storage[310] = 8'h00; + storage[311] = 8'h00; + storage[312] = 8'h00; + storage[313] = 8'h00; + storage[314] = 8'h00; + storage[315] = 8'h00; + storage[316] = 8'h00; + storage[317] = 8'h00; + storage[318] = 8'h00; + storage[319] = 8'h00; + storage[320] = 8'h00; + storage[321] = 8'h00; + storage[322] = 8'h00; + storage[323] = 8'h00; + storage[324] = 8'h00; + storage[325] = 8'h00; + storage[326] = 8'h00; + storage[327] = 8'h00; + storage[328] = 8'h00; + storage[329] = 8'h00; + storage[330] = 8'h00; + storage[331] = 8'h00; + storage[332] = 8'h00; + storage[333] = 8'h00; + storage[334] = 8'h00; + storage[335] = 8'h00; + storage[336] = 8'h00; + storage[337] = 8'h00; + storage[338] = 8'h00; + storage[339] = 8'h00; + storage[340] = 8'h00; + storage[341] = 8'h00; + storage[342] = 8'h00; + storage[343] = 8'h00; + storage[344] = 8'h00; + storage[345] = 8'h00; + storage[346] = 8'h00; + storage[347] = 8'h00; + storage[348] = 8'h00; + storage[349] = 8'h00; + storage[350] = 8'h00; + storage[351] = 8'h00; + storage[352] = 8'h00; + storage[353] = 8'h00; + storage[354] = 8'h00; + storage[355] = 8'h00; + storage[356] = 8'h00; + storage[357] = 8'h00; + storage[358] = 8'h00; + storage[359] = 8'h00; + storage[360] = 8'h00; + storage[361] = 8'h00; + storage[362] = 8'h00; + storage[363] = 8'h00; + storage[364] = 8'h00; + storage[365] = 8'h00; + storage[366] = 8'h00; + storage[367] = 8'h00; + storage[368] = 8'h00; + storage[369] = 8'h00; + storage[370] = 8'h00; + storage[371] = 8'h00; + storage[372] = 8'h00; + storage[373] = 8'h00; + storage[374] = 8'h00; + storage[375] = 8'h00; + storage[376] = 8'h00; + storage[377] = 8'h00; + storage[378] = 8'h00; + storage[379] = 8'h00; + storage[380] = 8'h00; + storage[381] = 8'h00; + storage[382] = 8'h00; + storage[383] = 8'h00; + storage[384] = 8'h00; + storage[385] = 8'h00; + storage[386] = 8'h00; + storage[387] = 8'h00; + storage[388] = 8'h00; + storage[389] = 8'h00; + storage[390] = 8'h00; + storage[391] = 8'h00; + storage[392] = 8'h00; + storage[393] = 8'h00; + storage[394] = 8'h00; + storage[395] = 8'h00; + storage[396] = 8'h00; + storage[397] = 8'h00; + storage[398] = 8'h00; + storage[399] = 8'h00; + storage[400] = 8'h00; + storage[401] = 8'h00; + storage[402] = 8'h00; + storage[403] = 8'h00; + storage[404] = 8'h00; + storage[405] = 8'h00; + storage[406] = 8'h00; + storage[407] = 8'h00; + storage[408] = 8'h00; + storage[409] = 8'h00; + storage[410] = 8'h00; + storage[411] = 8'h00; + storage[412] = 8'h00; + storage[413] = 8'h00; + storage[414] = 8'h00; + storage[415] = 8'h00; + storage[416] = 8'h00; + storage[417] = 8'h00; + storage[418] = 8'h00; + storage[419] = 8'h00; + storage[420] = 8'h00; + storage[421] = 8'h00; + storage[422] = 8'h00; + storage[423] = 8'h00; + storage[424] = 8'h00; + storage[425] = 8'h00; + storage[426] = 8'h00; + storage[427] = 8'h00; + storage[428] = 8'h00; + storage[429] = 8'h00; + storage[430] = 8'h00; + storage[431] = 8'h00; + storage[432] = 8'h00; + storage[433] = 8'h00; + storage[434] = 8'h00; + storage[435] = 8'h00; + storage[436] = 8'h00; + storage[437] = 8'h00; + storage[438] = 8'h00; + storage[439] = 8'h00; + storage[440] = 8'h00; + storage[441] = 8'h00; + storage[442] = 8'h00; + storage[443] = 8'h00; + storage[444] = 8'h00; + storage[445] = 8'h00; + storage[446] = 8'h00; + storage[447] = 8'h00; + storage[448] = 8'h00; + storage[449] = 8'h00; + storage[450] = 8'h00; + storage[451] = 8'h00; + storage[452] = 8'h00; + storage[453] = 8'h00; + storage[454] = 8'h00; + storage[455] = 8'h00; + storage[456] = 8'h00; + storage[457] = 8'h00; + storage[458] = 8'h00; + storage[459] = 8'h00; + storage[460] = 8'h00; + storage[461] = 8'h00; + storage[462] = 8'h00; + storage[463] = 8'h00; + storage[464] = 8'h00; + storage[465] = 8'h00; + storage[466] = 8'h00; + storage[467] = 8'h00; + storage[468] = 8'h00; + storage[469] = 8'h00; + storage[470] = 8'h00; + storage[471] = 8'h00; + storage[472] = 8'h00; + storage[473] = 8'h00; + storage[474] = 8'h00; + storage[475] = 8'h00; + storage[476] = 8'h00; + storage[477] = 8'h00; + storage[478] = 8'h00; + storage[479] = 8'h00; + storage[480] = 8'h00; + storage[481] = 8'h00; + storage[482] = 8'h00; + storage[483] = 8'h00; + storage[484] = 8'h00; + storage[485] = 8'h00; + storage[486] = 8'h00; + storage[487] = 8'h00; + storage[488] = 8'h00; + storage[489] = 8'h00; + storage[490] = 8'h00; + storage[491] = 8'h00; + storage[492] = 8'h00; + storage[493] = 8'h00; + storage[494] = 8'h00; + storage[495] = 8'h00; + storage[496] = 8'h00; + storage[497] = 8'h00; + storage[498] = 8'h00; + storage[499] = 8'h00; + storage[500] = 8'h00; + storage[501] = 8'h00; + storage[502] = 8'h00; + storage[503] = 8'h00; + storage[504] = 8'h00; + storage[505] = 8'h00; + storage[506] = 8'h00; + storage[507] = 8'h00; + storage[508] = 8'h00; + storage[509] = 8'h00; + storage[510] = 8'h00; + storage[511] = 8'h00; + storage[512] = 8'h00; + storage[513] = 8'h00; + storage[514] = 8'h00; + storage[515] = 8'h00; + storage[516] = 8'h00; + storage[517] = 8'h00; + storage[518] = 8'h00; + storage[519] = 8'h00; + storage[520] = 8'h00; + storage[521] = 8'h00; + storage[522] = 8'h00; + storage[523] = 8'h00; + storage[524] = 8'h00; + storage[525] = 8'h00; + storage[526] = 8'h00; + storage[527] = 8'h00; + storage[528] = 8'h00; + storage[529] = 8'h00; + storage[530] = 8'h00; + storage[531] = 8'h00; + storage[532] = 8'h00; + storage[533] = 8'h00; + storage[534] = 8'h00; + storage[535] = 8'h00; + storage[536] = 8'h00; + storage[537] = 8'h00; + storage[538] = 8'h00; + storage[539] = 8'h00; + storage[540] = 8'h00; + storage[541] = 8'h00; + storage[542] = 8'h00; + storage[543] = 8'h00; + storage[544] = 8'h00; + storage[545] = 8'h00; + storage[546] = 8'h00; + storage[547] = 8'h00; + storage[548] = 8'h00; + storage[549] = 8'h00; + storage[550] = 8'h00; + storage[551] = 8'h00; + storage[552] = 8'h00; + storage[553] = 8'h00; + storage[554] = 8'h00; + storage[555] = 8'h00; + storage[556] = 8'h00; + storage[557] = 8'h00; + storage[558] = 8'h00; + storage[559] = 8'h00; + storage[560] = 8'h00; + storage[561] = 8'h00; + storage[562] = 8'h00; + storage[563] = 8'h00; + storage[564] = 8'h00; + storage[565] = 8'h00; + storage[566] = 8'h00; + storage[567] = 8'h00; + storage[568] = 8'h00; + storage[569] = 8'h00; + storage[570] = 8'h00; + storage[571] = 8'h00; + storage[572] = 8'h00; + storage[573] = 8'h00; + storage[574] = 8'h00; + storage[575] = 8'h00; + storage[576] = 8'h00; + storage[577] = 8'h00; + storage[578] = 8'h00; + storage[579] = 8'h00; + storage[580] = 8'h00; + storage[581] = 8'h00; + storage[582] = 8'h00; + storage[583] = 8'h00; + storage[584] = 8'h00; + storage[585] = 8'h00; + storage[586] = 8'h00; + storage[587] = 8'h00; + storage[588] = 8'h00; + storage[589] = 8'h00; + storage[590] = 8'h00; + storage[591] = 8'h00; + storage[592] = 8'h00; + storage[593] = 8'h00; + storage[594] = 8'h00; + storage[595] = 8'h00; + storage[596] = 8'h00; + storage[597] = 8'h00; + storage[598] = 8'h00; + storage[599] = 8'h00; + storage[600] = 8'h00; + storage[601] = 8'h00; + storage[602] = 8'h00; + storage[603] = 8'h00; + storage[604] = 8'h00; + storage[605] = 8'h00; + storage[606] = 8'h00; + storage[607] = 8'h00; + storage[608] = 8'h00; + storage[609] = 8'h00; + storage[610] = 8'h00; + storage[611] = 8'h00; + storage[612] = 8'h00; + storage[613] = 8'h00; + storage[614] = 8'h00; + storage[615] = 8'h00; + storage[616] = 8'h00; + storage[617] = 8'h00; + storage[618] = 8'h00; + storage[619] = 8'h00; + storage[620] = 8'h00; + storage[621] = 8'h00; + storage[622] = 8'h00; + storage[623] = 8'h00; + storage[624] = 8'h00; + storage[625] = 8'h00; + storage[626] = 8'h00; + storage[627] = 8'h00; + storage[628] = 8'h00; + storage[629] = 8'h00; + storage[630] = 8'h00; + storage[631] = 8'h00; + storage[632] = 8'h00; + storage[633] = 8'h00; + storage[634] = 8'h00; + storage[635] = 8'h00; + storage[636] = 8'h00; + storage[637] = 8'h00; + storage[638] = 8'h00; + storage[639] = 8'h00; + storage[640] = 8'h00; + storage[641] = 8'h00; + storage[642] = 8'h00; + storage[643] = 8'h00; + storage[644] = 8'h00; + storage[645] = 8'h00; + storage[646] = 8'h00; + storage[647] = 8'h00; + storage[648] = 8'h00; + storage[649] = 8'h00; + storage[650] = 8'h00; + storage[651] = 8'h00; + storage[652] = 8'h00; + storage[653] = 8'h00; + storage[654] = 8'h00; + storage[655] = 8'h00; + storage[656] = 8'h00; + storage[657] = 8'h00; + storage[658] = 8'h00; + storage[659] = 8'h00; + storage[660] = 8'h00; + storage[661] = 8'h00; + storage[662] = 8'h00; + storage[663] = 8'h00; + storage[664] = 8'h00; + storage[665] = 8'h00; + storage[666] = 8'h00; + storage[667] = 8'h00; + storage[668] = 8'h00; + storage[669] = 8'h00; + storage[670] = 8'h00; + storage[671] = 8'h00; + storage[672] = 8'h00; + storage[673] = 8'h00; + storage[674] = 8'h00; + storage[675] = 8'h00; + storage[676] = 8'h00; + storage[677] = 8'h00; + storage[678] = 8'h00; + storage[679] = 8'h00; + storage[680] = 8'h00; + storage[681] = 8'h00; + storage[682] = 8'h00; + storage[683] = 8'h00; + storage[684] = 8'h00; + storage[685] = 8'h00; + storage[686] = 8'h00; + storage[687] = 8'h00; + storage[688] = 8'h00; + storage[689] = 8'h00; + storage[690] = 8'h00; + storage[691] = 8'h00; + storage[692] = 8'h00; + storage[693] = 8'h00; + storage[694] = 8'h00; + storage[695] = 8'h00; + storage[696] = 8'h00; + storage[697] = 8'h00; + storage[698] = 8'h00; + storage[699] = 8'h00; + storage[700] = 8'h00; + storage[701] = 8'h00; + storage[702] = 8'h00; + storage[703] = 8'h00; + storage[704] = 8'h00; + storage[705] = 8'h00; + storage[706] = 8'h00; + storage[707] = 8'h00; + storage[708] = 8'h00; + storage[709] = 8'h00; + storage[710] = 8'h00; + storage[711] = 8'h00; + storage[712] = 8'h00; + storage[713] = 8'h00; + storage[714] = 8'h00; + storage[715] = 8'h00; + storage[716] = 8'h00; + storage[717] = 8'h00; + storage[718] = 8'h00; + storage[719] = 8'h00; + storage[720] = 8'h00; + storage[721] = 8'h00; + storage[722] = 8'h00; + storage[723] = 8'h00; + storage[724] = 8'h00; + storage[725] = 8'h00; + storage[726] = 8'h00; + storage[727] = 8'h00; + storage[728] = 8'h00; + storage[729] = 8'h00; + storage[730] = 8'h00; + storage[731] = 8'h00; + storage[732] = 8'h00; + storage[733] = 8'h00; + storage[734] = 8'h00; + storage[735] = 8'h00; + storage[736] = 8'h00; + storage[737] = 8'h00; + storage[738] = 8'h00; + storage[739] = 8'h00; + storage[740] = 8'h00; + storage[741] = 8'h00; + storage[742] = 8'h00; + storage[743] = 8'h00; + storage[744] = 8'h00; + storage[745] = 8'h00; + storage[746] = 8'h00; + storage[747] = 8'h00; + storage[748] = 8'h00; + storage[749] = 8'h00; + storage[750] = 8'h00; + storage[751] = 8'h00; + storage[752] = 8'h00; + storage[753] = 8'h00; + storage[754] = 8'h00; + storage[755] = 8'h00; + storage[756] = 8'h00; + storage[757] = 8'h00; + storage[758] = 8'h00; + storage[759] = 8'h00; + storage[760] = 8'h00; + storage[761] = 8'h00; + storage[762] = 8'h00; + storage[763] = 8'h00; + storage[764] = 8'h00; + storage[765] = 8'h00; + storage[766] = 8'h00; + storage[767] = 8'h00; + storage[768] = 8'h00; + storage[769] = 8'h00; + storage[770] = 8'h00; + storage[771] = 8'h00; + storage[772] = 8'h00; + storage[773] = 8'h00; + storage[774] = 8'h00; + storage[775] = 8'h00; + storage[776] = 8'h00; + storage[777] = 8'h00; + storage[778] = 8'h00; + storage[779] = 8'h00; + storage[780] = 8'h00; + storage[781] = 8'h00; + storage[782] = 8'h00; + storage[783] = 8'h00; + storage[784] = 8'h00; + storage[785] = 8'h00; + storage[786] = 8'h00; + storage[787] = 8'h00; + storage[788] = 8'h00; + storage[789] = 8'h00; + storage[790] = 8'h00; + storage[791] = 8'h00; + storage[792] = 8'h00; + storage[793] = 8'h00; + storage[794] = 8'h00; + storage[795] = 8'h00; + storage[796] = 8'h00; + storage[797] = 8'h00; + storage[798] = 8'h00; + storage[799] = 8'h00; + storage[800] = 8'h00; + storage[801] = 8'h00; + storage[802] = 8'h00; + storage[803] = 8'h00; + storage[804] = 8'h00; + storage[805] = 8'h00; + storage[806] = 8'h00; + storage[807] = 8'h00; + storage[808] = 8'h00; + storage[809] = 8'h00; + storage[810] = 8'h00; + storage[811] = 8'h00; + storage[812] = 8'h00; + storage[813] = 8'h00; + storage[814] = 8'h00; + storage[815] = 8'h00; + storage[816] = 8'h00; + storage[817] = 8'h00; + storage[818] = 8'h00; + storage[819] = 8'h00; + storage[820] = 8'h00; + storage[821] = 8'h00; + storage[822] = 8'h00; + storage[823] = 8'h00; + storage[824] = 8'h00; + storage[825] = 8'h00; + storage[826] = 8'h00; + storage[827] = 8'h00; + storage[828] = 8'h00; + storage[829] = 8'h00; + storage[830] = 8'h00; + storage[831] = 8'h00; + storage[832] = 8'h00; + storage[833] = 8'h00; + storage[834] = 8'h00; + storage[835] = 8'h00; + storage[836] = 8'h00; + storage[837] = 8'h00; + storage[838] = 8'h00; + storage[839] = 8'h00; + storage[840] = 8'h00; + storage[841] = 8'h00; + storage[842] = 8'h00; + storage[843] = 8'h00; + storage[844] = 8'h00; + storage[845] = 8'h00; + storage[846] = 8'h00; + storage[847] = 8'h00; + storage[848] = 8'h00; + storage[849] = 8'h00; + storage[850] = 8'h00; + storage[851] = 8'h00; + storage[852] = 8'h00; + storage[853] = 8'h00; + storage[854] = 8'h00; + storage[855] = 8'h00; + storage[856] = 8'h00; + storage[857] = 8'h00; + storage[858] = 8'h00; + storage[859] = 8'h00; + storage[860] = 8'h00; + storage[861] = 8'h00; + storage[862] = 8'h00; + storage[863] = 8'h00; + storage[864] = 8'h00; + storage[865] = 8'h00; + storage[866] = 8'h00; + storage[867] = 8'h00; + storage[868] = 8'h00; + storage[869] = 8'h00; + storage[870] = 8'h00; + storage[871] = 8'h00; + storage[872] = 8'h00; + storage[873] = 8'h00; + storage[874] = 8'h00; + storage[875] = 8'h00; + storage[876] = 8'h00; + storage[877] = 8'h00; + storage[878] = 8'h00; + storage[879] = 8'h00; + storage[880] = 8'h00; + storage[881] = 8'h00; + storage[882] = 8'h00; + storage[883] = 8'h00; + storage[884] = 8'h00; + storage[885] = 8'h00; + storage[886] = 8'h00; + storage[887] = 8'h00; + storage[888] = 8'h00; + storage[889] = 8'h00; + storage[890] = 8'h00; + storage[891] = 8'h00; + storage[892] = 8'h00; + storage[893] = 8'h00; + storage[894] = 8'h00; + storage[895] = 8'h00; + storage[896] = 8'h00; + storage[897] = 8'h00; + storage[898] = 8'h00; + storage[899] = 8'h00; + storage[900] = 8'h00; + storage[901] = 8'h00; + storage[902] = 8'h00; + storage[903] = 8'h00; + storage[904] = 8'h00; + storage[905] = 8'h00; + storage[906] = 8'h00; + storage[907] = 8'h00; + storage[908] = 8'h00; + storage[909] = 8'h00; + storage[910] = 8'h00; + storage[911] = 8'h00; + storage[912] = 8'h00; + storage[913] = 8'h00; + storage[914] = 8'h00; + storage[915] = 8'h00; + storage[916] = 8'h00; + storage[917] = 8'h00; + storage[918] = 8'h00; + storage[919] = 8'h00; + storage[920] = 8'h00; + storage[921] = 8'h00; + storage[922] = 8'h00; + storage[923] = 8'h00; + storage[924] = 8'h00; + storage[925] = 8'h00; + storage[926] = 8'h00; + storage[927] = 8'h00; + storage[928] = 8'h00; + storage[929] = 8'h00; + storage[930] = 8'h00; + storage[931] = 8'h00; + storage[932] = 8'h00; + storage[933] = 8'h00; + storage[934] = 8'h00; + storage[935] = 8'h00; + storage[936] = 8'h00; + storage[937] = 8'h00; + storage[938] = 8'h00; + storage[939] = 8'h00; + storage[940] = 8'h00; + storage[941] = 8'h00; + storage[942] = 8'h00; + storage[943] = 8'h00; + storage[944] = 8'h00; + storage[945] = 8'h00; + storage[946] = 8'h00; + storage[947] = 8'h00; + storage[948] = 8'h00; + storage[949] = 8'h00; + storage[950] = 8'h00; + storage[951] = 8'h00; + storage[952] = 8'h00; + storage[953] = 8'h00; + storage[954] = 8'h00; + storage[955] = 8'h00; + storage[956] = 8'h00; + storage[957] = 8'h00; + storage[958] = 8'h00; + storage[959] = 8'h00; + storage[960] = 8'h00; + storage[961] = 8'h00; + storage[962] = 8'h00; + storage[963] = 8'h00; + storage[964] = 8'h00; + storage[965] = 8'h00; + storage[966] = 8'h00; + storage[967] = 8'h00; + storage[968] = 8'h00; + storage[969] = 8'h00; + storage[970] = 8'h00; + storage[971] = 8'h00; + storage[972] = 8'h00; + storage[973] = 8'h00; + storage[974] = 8'h00; + storage[975] = 8'h00; + storage[976] = 8'h00; + storage[977] = 8'h00; + storage[978] = 8'h00; + storage[979] = 8'h00; + storage[980] = 8'h00; + storage[981] = 8'h00; + storage[982] = 8'h00; + storage[983] = 8'h00; + storage[984] = 8'h00; + storage[985] = 8'h00; + storage[986] = 8'h00; + storage[987] = 8'h00; + storage[988] = 8'h00; + storage[989] = 8'h00; + storage[990] = 8'h00; + storage[991] = 8'h00; + storage[992] = 8'h00; + storage[993] = 8'h00; + storage[994] = 8'h00; + storage[995] = 8'h00; + storage[996] = 8'h00; + storage[997] = 8'h00; + storage[998] = 8'h00; + storage[999] = 8'h00; + storage[1000] = 8'h00; + storage[1001] = 8'h00; + storage[1002] = 8'h00; + storage[1003] = 8'h00; + storage[1004] = 8'h00; + storage[1005] = 8'h00; + storage[1006] = 8'h00; + storage[1007] = 8'h00; + storage[1008] = 8'h00; + storage[1009] = 8'h00; + storage[1010] = 8'h00; + storage[1011] = 8'h00; + storage[1012] = 8'h00; + storage[1013] = 8'h00; + storage[1014] = 8'h00; + storage[1015] = 8'h00; + storage[1016] = 8'h00; + storage[1017] = 8'h00; + storage[1018] = 8'h00; + storage[1019] = 8'h00; + storage[1020] = 8'h00; + storage[1021] = 8'h00; + storage[1022] = 8'h00; + storage[1023] = 8'h00; + storage[1024] = 8'h00; + storage[1025] = 8'h00; + storage[1026] = 8'h00; + storage[1027] = 8'h00; + storage[1028] = 8'h00; + storage[1029] = 8'h00; + storage[1030] = 8'h00; + storage[1031] = 8'h00; + storage[1032] = 8'h00; + storage[1033] = 8'h00; + storage[1034] = 8'h00; + storage[1035] = 8'h00; + storage[1036] = 8'h00; + storage[1037] = 8'h00; + storage[1038] = 8'h00; + storage[1039] = 8'h00; + storage[1040] = 8'h00; + storage[1041] = 8'h00; + storage[1042] = 8'h00; + storage[1043] = 8'h00; + storage[1044] = 8'h00; + storage[1045] = 8'h00; + storage[1046] = 8'h00; + storage[1047] = 8'h00; + storage[1048] = 8'h00; + storage[1049] = 8'h00; + storage[1050] = 8'h00; + storage[1051] = 8'h00; + storage[1052] = 8'h00; + storage[1053] = 8'h00; + storage[1054] = 8'h00; + storage[1055] = 8'h00; + storage[1056] = 8'h00; + storage[1057] = 8'h00; + storage[1058] = 8'h00; + storage[1059] = 8'h00; + storage[1060] = 8'h00; + storage[1061] = 8'h00; + storage[1062] = 8'h00; + storage[1063] = 8'h00; + storage[1064] = 8'h00; + storage[1065] = 8'h00; + storage[1066] = 8'h00; + storage[1067] = 8'h00; + storage[1068] = 8'h00; + storage[1069] = 8'h00; + storage[1070] = 8'h00; + storage[1071] = 8'h00; + storage[1072] = 8'h00; + storage[1073] = 8'h00; + storage[1074] = 8'h00; + storage[1075] = 8'h00; + storage[1076] = 8'h00; + storage[1077] = 8'h00; + storage[1078] = 8'h00; + storage[1079] = 8'h00; + storage[1080] = 8'h00; + storage[1081] = 8'h00; + storage[1082] = 8'h00; + storage[1083] = 8'h00; + storage[1084] = 8'h00; + storage[1085] = 8'h00; + storage[1086] = 8'h00; + storage[1087] = 8'h00; + storage[1088] = 8'h00; + storage[1089] = 8'h00; + storage[1090] = 8'h00; + storage[1091] = 8'h00; + storage[1092] = 8'h00; + storage[1093] = 8'h00; + storage[1094] = 8'h00; + storage[1095] = 8'h00; + storage[1096] = 8'h00; + storage[1097] = 8'h00; + storage[1098] = 8'h00; + storage[1099] = 8'h00; + storage[1100] = 8'h00; + storage[1101] = 8'h00; + storage[1102] = 8'h00; + storage[1103] = 8'h00; + storage[1104] = 8'h00; + storage[1105] = 8'h00; + storage[1106] = 8'h00; + storage[1107] = 8'h00; + storage[1108] = 8'h00; + storage[1109] = 8'h00; + storage[1110] = 8'h00; + storage[1111] = 8'h00; + storage[1112] = 8'h00; + storage[1113] = 8'h00; + storage[1114] = 8'h00; + storage[1115] = 8'h00; + storage[1116] = 8'h00; + storage[1117] = 8'h00; + storage[1118] = 8'h00; + storage[1119] = 8'h00; + storage[1120] = 8'h00; + storage[1121] = 8'h00; + storage[1122] = 8'h00; + storage[1123] = 8'h00; + storage[1124] = 8'h00; + storage[1125] = 8'h00; + storage[1126] = 8'h00; + storage[1127] = 8'h00; + storage[1128] = 8'h00; + storage[1129] = 8'h00; + storage[1130] = 8'h00; + storage[1131] = 8'h00; + storage[1132] = 8'h00; + storage[1133] = 8'h00; + storage[1134] = 8'h00; + storage[1135] = 8'h00; + storage[1136] = 8'h00; + storage[1137] = 8'h00; + storage[1138] = 8'h00; + storage[1139] = 8'h00; + storage[1140] = 8'h00; + storage[1141] = 8'h00; + storage[1142] = 8'h00; + storage[1143] = 8'h00; + storage[1144] = 8'h00; + storage[1145] = 8'h00; + storage[1146] = 8'h00; + storage[1147] = 8'h00; + storage[1148] = 8'h00; + storage[1149] = 8'h00; + storage[1150] = 8'h00; + storage[1151] = 8'h00; + storage[1152] = 8'h00; + storage[1153] = 8'h00; + storage[1154] = 8'h00; + storage[1155] = 8'h00; + storage[1156] = 8'h00; + storage[1157] = 8'h00; + storage[1158] = 8'h00; + storage[1159] = 8'h00; + storage[1160] = 8'h00; + storage[1161] = 8'h00; + storage[1162] = 8'h00; + storage[1163] = 8'h00; + storage[1164] = 8'h00; + storage[1165] = 8'h00; + storage[1166] = 8'h00; + storage[1167] = 8'h00; + storage[1168] = 8'h00; + storage[1169] = 8'h00; + storage[1170] = 8'h00; + storage[1171] = 8'h00; + storage[1172] = 8'h00; + storage[1173] = 8'h00; + storage[1174] = 8'h00; + storage[1175] = 8'h00; + storage[1176] = 8'h00; + storage[1177] = 8'h00; + storage[1178] = 8'h00; + storage[1179] = 8'h00; + storage[1180] = 8'h00; + storage[1181] = 8'h00; + storage[1182] = 8'h00; + storage[1183] = 8'h00; + storage[1184] = 8'h00; + storage[1185] = 8'h00; + storage[1186] = 8'h00; + storage[1187] = 8'h00; + storage[1188] = 8'h00; + storage[1189] = 8'h00; + storage[1190] = 8'h00; + storage[1191] = 8'h00; + storage[1192] = 8'h00; + storage[1193] = 8'h00; + storage[1194] = 8'h00; + storage[1195] = 8'h00; + storage[1196] = 8'h00; + storage[1197] = 8'h00; + storage[1198] = 8'h00; + storage[1199] = 8'h00; + storage[1200] = 8'h00; + storage[1201] = 8'h00; + storage[1202] = 8'h00; + storage[1203] = 8'h00; + storage[1204] = 8'h00; + storage[1205] = 8'h00; + storage[1206] = 8'h00; + storage[1207] = 8'h00; + storage[1208] = 8'h00; + storage[1209] = 8'h00; + storage[1210] = 8'h00; + storage[1211] = 8'h00; + storage[1212] = 8'h00; + storage[1213] = 8'h00; + storage[1214] = 8'h00; + storage[1215] = 8'h00; + storage[1216] = 8'h00; + storage[1217] = 8'h00; + storage[1218] = 8'h00; + storage[1219] = 8'h00; + storage[1220] = 8'h00; + storage[1221] = 8'h00; + storage[1222] = 8'h00; + storage[1223] = 8'h00; + storage[1224] = 8'h00; + storage[1225] = 8'h00; + storage[1226] = 8'h00; + storage[1227] = 8'h00; + storage[1228] = 8'h00; + storage[1229] = 8'h00; + storage[1230] = 8'h00; + storage[1231] = 8'h00; + storage[1232] = 8'h00; + storage[1233] = 8'h00; + storage[1234] = 8'h00; + storage[1235] = 8'h00; + storage[1236] = 8'h00; + storage[1237] = 8'h00; + storage[1238] = 8'h00; + storage[1239] = 8'h00; + storage[1240] = 8'h00; + storage[1241] = 8'h00; + storage[1242] = 8'h00; + storage[1243] = 8'h00; + storage[1244] = 8'h00; + storage[1245] = 8'h00; + storage[1246] = 8'h00; + storage[1247] = 8'h00; + storage[1248] = 8'h00; + storage[1249] = 8'h00; + storage[1250] = 8'h00; + storage[1251] = 8'h00; + storage[1252] = 8'h00; + storage[1253] = 8'h00; + storage[1254] = 8'h00; + storage[1255] = 8'h00; + storage[1256] = 8'h00; + storage[1257] = 8'h00; + storage[1258] = 8'h00; + storage[1259] = 8'h00; + storage[1260] = 8'h00; + storage[1261] = 8'h00; + storage[1262] = 8'h00; + storage[1263] = 8'h00; + storage[1264] = 8'h00; + storage[1265] = 8'h00; + storage[1266] = 8'h00; + storage[1267] = 8'h00; + storage[1268] = 8'h00; + storage[1269] = 8'h00; + storage[1270] = 8'h00; + storage[1271] = 8'h00; + storage[1272] = 8'h00; + storage[1273] = 8'h00; + storage[1274] = 8'h00; + storage[1275] = 8'h00; + storage[1276] = 8'h00; + storage[1277] = 8'h00; + storage[1278] = 8'h00; + storage[1279] = 8'h00; + storage[1280] = 8'h00; + storage[1281] = 8'h00; + storage[1282] = 8'h00; + storage[1283] = 8'h00; + storage[1284] = 8'h00; + storage[1285] = 8'h00; + storage[1286] = 8'h00; + storage[1287] = 8'h00; + storage[1288] = 8'h00; + storage[1289] = 8'h00; + storage[1290] = 8'h00; + storage[1291] = 8'h00; + storage[1292] = 8'h00; + storage[1293] = 8'h00; + storage[1294] = 8'h00; + storage[1295] = 8'h00; + storage[1296] = 8'h00; + storage[1297] = 8'h00; + storage[1298] = 8'h00; + storage[1299] = 8'h00; + storage[1300] = 8'h00; + storage[1301] = 8'h00; + storage[1302] = 8'h00; + storage[1303] = 8'h00; + storage[1304] = 8'h00; + storage[1305] = 8'h00; + storage[1306] = 8'h00; + storage[1307] = 8'h00; + storage[1308] = 8'h00; + storage[1309] = 8'h00; + storage[1310] = 8'h00; + storage[1311] = 8'h00; + storage[1312] = 8'h00; + storage[1313] = 8'h00; + storage[1314] = 8'h00; + storage[1315] = 8'h00; + storage[1316] = 8'h00; + storage[1317] = 8'h00; + storage[1318] = 8'h00; + storage[1319] = 8'h00; + storage[1320] = 8'h00; + storage[1321] = 8'h00; + storage[1322] = 8'h00; + storage[1323] = 8'h00; + storage[1324] = 8'h00; + storage[1325] = 8'h00; + storage[1326] = 8'h00; + storage[1327] = 8'h00; + storage[1328] = 8'h00; + storage[1329] = 8'h00; + storage[1330] = 8'h00; + storage[1331] = 8'h00; + storage[1332] = 8'h00; + storage[1333] = 8'h00; + storage[1334] = 8'h00; + storage[1335] = 8'h00; + storage[1336] = 8'h00; + storage[1337] = 8'h00; + storage[1338] = 8'h00; + storage[1339] = 8'h00; + storage[1340] = 8'h00; + storage[1341] = 8'h00; + storage[1342] = 8'h00; + storage[1343] = 8'h00; + storage[1344] = 8'h00; + storage[1345] = 8'h00; + storage[1346] = 8'h00; + storage[1347] = 8'h00; + storage[1348] = 8'h00; + storage[1349] = 8'h00; + storage[1350] = 8'h00; + storage[1351] = 8'h00; + storage[1352] = 8'h00; + storage[1353] = 8'h00; + storage[1354] = 8'h00; + storage[1355] = 8'h00; + storage[1356] = 8'h00; + storage[1357] = 8'h00; + storage[1358] = 8'h00; + storage[1359] = 8'h00; + storage[1360] = 8'h00; + storage[1361] = 8'h00; + storage[1362] = 8'h00; + storage[1363] = 8'h00; + storage[1364] = 8'h00; + storage[1365] = 8'h00; + storage[1366] = 8'h00; + storage[1367] = 8'h00; + storage[1368] = 8'h00; + storage[1369] = 8'h00; + storage[1370] = 8'h00; + storage[1371] = 8'h00; + storage[1372] = 8'h00; + storage[1373] = 8'h00; + storage[1374] = 8'h00; + storage[1375] = 8'h00; + storage[1376] = 8'h00; + storage[1377] = 8'h00; + storage[1378] = 8'h00; + storage[1379] = 8'h00; + storage[1380] = 8'h00; + storage[1381] = 8'h00; + storage[1382] = 8'h00; + storage[1383] = 8'h00; + storage[1384] = 8'h00; + storage[1385] = 8'h00; + storage[1386] = 8'h00; + storage[1387] = 8'h00; + storage[1388] = 8'h00; + storage[1389] = 8'h00; + storage[1390] = 8'h00; + storage[1391] = 8'h00; + storage[1392] = 8'h00; + storage[1393] = 8'h00; + storage[1394] = 8'h00; + storage[1395] = 8'h00; + storage[1396] = 8'h00; + storage[1397] = 8'h00; + storage[1398] = 8'h00; + storage[1399] = 8'h00; + storage[1400] = 8'h00; + storage[1401] = 8'h00; + storage[1402] = 8'h00; + storage[1403] = 8'h00; + storage[1404] = 8'h00; + storage[1405] = 8'h00; + storage[1406] = 8'h00; + storage[1407] = 8'h00; + storage[1408] = 8'h00; + storage[1409] = 8'h00; + storage[1410] = 8'h00; + storage[1411] = 8'h00; + storage[1412] = 8'h00; + storage[1413] = 8'h00; + storage[1414] = 8'h00; + storage[1415] = 8'h00; + storage[1416] = 8'h00; + storage[1417] = 8'h00; + storage[1418] = 8'h00; + storage[1419] = 8'h00; + storage[1420] = 8'h00; + storage[1421] = 8'h00; + storage[1422] = 8'h00; + storage[1423] = 8'h00; + storage[1424] = 8'h00; + storage[1425] = 8'h00; + storage[1426] = 8'h00; + storage[1427] = 8'h00; + storage[1428] = 8'h00; + storage[1429] = 8'h00; + storage[1430] = 8'h00; + storage[1431] = 8'h00; + storage[1432] = 8'h00; + storage[1433] = 8'h00; + storage[1434] = 8'h00; + storage[1435] = 8'h00; + storage[1436] = 8'h00; + storage[1437] = 8'h00; + storage[1438] = 8'h00; + storage[1439] = 8'h00; + storage[1440] = 8'h00; + storage[1441] = 8'h00; + storage[1442] = 8'h00; + storage[1443] = 8'h00; + storage[1444] = 8'h00; + storage[1445] = 8'h00; + storage[1446] = 8'h00; + storage[1447] = 8'h00; + storage[1448] = 8'h00; + storage[1449] = 8'h00; + storage[1450] = 8'h00; + storage[1451] = 8'h00; + storage[1452] = 8'h00; + storage[1453] = 8'h00; + storage[1454] = 8'h00; + storage[1455] = 8'h00; + storage[1456] = 8'h00; + storage[1457] = 8'h00; + storage[1458] = 8'h00; + storage[1459] = 8'h00; + storage[1460] = 8'h00; + storage[1461] = 8'h00; + storage[1462] = 8'h00; + storage[1463] = 8'h00; + storage[1464] = 8'h00; + storage[1465] = 8'h00; + storage[1466] = 8'h00; + storage[1467] = 8'h00; + storage[1468] = 8'h00; + storage[1469] = 8'h00; + storage[1470] = 8'h00; + storage[1471] = 8'h00; + storage[1472] = 8'h00; + storage[1473] = 8'h00; + storage[1474] = 8'h00; + storage[1475] = 8'h00; + storage[1476] = 8'h00; + storage[1477] = 8'h00; + storage[1478] = 8'h00; + storage[1479] = 8'h00; + storage[1480] = 8'h00; + storage[1481] = 8'h00; + storage[1482] = 8'h00; + storage[1483] = 8'h00; + storage[1484] = 8'h00; + storage[1485] = 8'h00; + storage[1486] = 8'h00; + storage[1487] = 8'h00; + storage[1488] = 8'h00; + storage[1489] = 8'h00; + storage[1490] = 8'h00; + storage[1491] = 8'h00; + storage[1492] = 8'h00; + storage[1493] = 8'h00; + storage[1494] = 8'h00; + storage[1495] = 8'h00; + storage[1496] = 8'h00; + storage[1497] = 8'h00; + storage[1498] = 8'h00; + storage[1499] = 8'h00; + storage[1500] = 8'h00; + storage[1501] = 8'h00; + storage[1502] = 8'h00; + storage[1503] = 8'h00; + storage[1504] = 8'h00; + storage[1505] = 8'h00; + storage[1506] = 8'h00; + storage[1507] = 8'h00; + storage[1508] = 8'h00; + storage[1509] = 8'h00; + storage[1510] = 8'h00; + storage[1511] = 8'h00; + storage[1512] = 8'h00; + storage[1513] = 8'h00; + storage[1514] = 8'h00; + storage[1515] = 8'h00; + storage[1516] = 8'h00; + storage[1517] = 8'h00; + storage[1518] = 8'h00; + storage[1519] = 8'h00; + storage[1520] = 8'h00; + storage[1521] = 8'h00; + storage[1522] = 8'h00; + storage[1523] = 8'h00; + storage[1524] = 8'h00; + storage[1525] = 8'h00; + storage[1526] = 8'h00; + storage[1527] = 8'h00; + storage[1528] = 8'h00; + storage[1529] = 8'h00; + storage[1530] = 8'h00; + storage[1531] = 8'h00; + storage[1532] = 8'h00; + storage[1533] = 8'h00; + storage[1534] = 8'h00; + storage[1535] = 8'h00; + storage[1536] = 8'h00; + storage[1537] = 8'h00; + storage[1538] = 8'h00; + storage[1539] = 8'h00; + storage[1540] = 8'h00; + storage[1541] = 8'h00; + storage[1542] = 8'h00; + storage[1543] = 8'h00; + storage[1544] = 8'h00; + storage[1545] = 8'h00; + storage[1546] = 8'h00; + storage[1547] = 8'h00; + storage[1548] = 8'h00; + storage[1549] = 8'h00; + storage[1550] = 8'h00; + storage[1551] = 8'h00; + storage[1552] = 8'h00; + storage[1553] = 8'h00; + storage[1554] = 8'h00; + storage[1555] = 8'h00; + storage[1556] = 8'h00; + storage[1557] = 8'h00; + storage[1558] = 8'h00; + storage[1559] = 8'h00; + storage[1560] = 8'h00; + storage[1561] = 8'h00; + storage[1562] = 8'h00; + storage[1563] = 8'h00; + storage[1564] = 8'h00; + storage[1565] = 8'h00; + storage[1566] = 8'h00; + storage[1567] = 8'h00; + storage[1568] = 8'h00; + storage[1569] = 8'h00; + storage[1570] = 8'h00; + storage[1571] = 8'h00; + storage[1572] = 8'h00; + storage[1573] = 8'h00; + storage[1574] = 8'h00; + storage[1575] = 8'h00; + storage[1576] = 8'h00; + storage[1577] = 8'h00; + storage[1578] = 8'h00; + storage[1579] = 8'h00; + storage[1580] = 8'h00; + storage[1581] = 8'h00; + storage[1582] = 8'h00; + storage[1583] = 8'h00; + storage[1584] = 8'h00; + storage[1585] = 8'h00; + storage[1586] = 8'h00; + storage[1587] = 8'h00; + storage[1588] = 8'h00; + storage[1589] = 8'h00; + storage[1590] = 8'h00; + storage[1591] = 8'h00; + storage[1592] = 8'h00; + storage[1593] = 8'h00; + storage[1594] = 8'h00; + storage[1595] = 8'h00; + storage[1596] = 8'h00; + storage[1597] = 8'h00; + storage[1598] = 8'h00; + storage[1599] = 8'h00; + storage[1600] = 8'h00; + storage[1601] = 8'h00; + storage[1602] = 8'h00; + storage[1603] = 8'h00; + storage[1604] = 8'h00; + storage[1605] = 8'h00; + storage[1606] = 8'h00; + storage[1607] = 8'h00; + storage[1608] = 8'h00; + storage[1609] = 8'h00; + storage[1610] = 8'h00; + storage[1611] = 8'h00; + storage[1612] = 8'h00; + storage[1613] = 8'h00; + storage[1614] = 8'h00; + storage[1615] = 8'h00; + storage[1616] = 8'h00; + storage[1617] = 8'h00; + storage[1618] = 8'h00; + storage[1619] = 8'h00; + storage[1620] = 8'h00; + storage[1621] = 8'h00; + storage[1622] = 8'h00; + storage[1623] = 8'h00; + storage[1624] = 8'h00; + storage[1625] = 8'h00; + storage[1626] = 8'h00; + storage[1627] = 8'h00; + storage[1628] = 8'h00; + storage[1629] = 8'h00; + storage[1630] = 8'h00; + storage[1631] = 8'h00; + storage[1632] = 8'h00; + storage[1633] = 8'h00; + storage[1634] = 8'h00; + storage[1635] = 8'h00; + storage[1636] = 8'h00; + storage[1637] = 8'h00; + storage[1638] = 8'h00; + storage[1639] = 8'h00; + storage[1640] = 8'h00; + storage[1641] = 8'h00; + storage[1642] = 8'h00; + storage[1643] = 8'h00; + storage[1644] = 8'h00; + storage[1645] = 8'h00; + storage[1646] = 8'h00; + storage[1647] = 8'h00; + storage[1648] = 8'h00; + storage[1649] = 8'h00; + storage[1650] = 8'h00; + storage[1651] = 8'h00; + storage[1652] = 8'h00; + storage[1653] = 8'h00; + storage[1654] = 8'h00; + storage[1655] = 8'h00; + storage[1656] = 8'h00; + storage[1657] = 8'h00; + storage[1658] = 8'h00; + storage[1659] = 8'h00; + storage[1660] = 8'h00; + storage[1661] = 8'h00; + storage[1662] = 8'h00; + storage[1663] = 8'h00; + storage[1664] = 8'h00; + storage[1665] = 8'h00; + storage[1666] = 8'h00; + storage[1667] = 8'h00; + storage[1668] = 8'h00; + storage[1669] = 8'h00; + storage[1670] = 8'h00; + storage[1671] = 8'h00; + storage[1672] = 8'h00; + storage[1673] = 8'h00; + storage[1674] = 8'h00; + storage[1675] = 8'h00; + storage[1676] = 8'h00; + storage[1677] = 8'h00; + storage[1678] = 8'h00; + storage[1679] = 8'h00; + storage[1680] = 8'h00; + storage[1681] = 8'h00; + storage[1682] = 8'h00; + storage[1683] = 8'h00; + storage[1684] = 8'h00; + storage[1685] = 8'h00; + storage[1686] = 8'h00; + storage[1687] = 8'h00; + storage[1688] = 8'h00; + storage[1689] = 8'h00; + storage[1690] = 8'h00; + storage[1691] = 8'h00; + storage[1692] = 8'h00; + storage[1693] = 8'h00; + storage[1694] = 8'h00; + storage[1695] = 8'h00; + storage[1696] = 8'h00; + storage[1697] = 8'h00; + storage[1698] = 8'h00; + storage[1699] = 8'h00; + storage[1700] = 8'h00; + storage[1701] = 8'h00; + storage[1702] = 8'h00; + storage[1703] = 8'h00; + storage[1704] = 8'h00; + storage[1705] = 8'h00; + storage[1706] = 8'h00; + storage[1707] = 8'h00; + storage[1708] = 8'h00; + storage[1709] = 8'h00; + storage[1710] = 8'h00; + storage[1711] = 8'h00; + storage[1712] = 8'h00; + storage[1713] = 8'h00; + storage[1714] = 8'h00; + storage[1715] = 8'h00; + storage[1716] = 8'h00; + storage[1717] = 8'h00; + storage[1718] = 8'h00; + storage[1719] = 8'h00; + storage[1720] = 8'h00; + storage[1721] = 8'h00; + storage[1722] = 8'h00; + storage[1723] = 8'h00; + storage[1724] = 8'h00; + storage[1725] = 8'h00; + storage[1726] = 8'h00; + storage[1727] = 8'h00; + storage[1728] = 8'h00; + storage[1729] = 8'h00; + storage[1730] = 8'h00; + storage[1731] = 8'h00; + storage[1732] = 8'h00; + storage[1733] = 8'h00; + storage[1734] = 8'h00; + storage[1735] = 8'h00; + storage[1736] = 8'h00; + storage[1737] = 8'h00; + storage[1738] = 8'h00; + storage[1739] = 8'h00; + storage[1740] = 8'h00; + storage[1741] = 8'h00; + storage[1742] = 8'h00; + storage[1743] = 8'h00; + storage[1744] = 8'h00; + storage[1745] = 8'h00; + storage[1746] = 8'h00; + storage[1747] = 8'h00; + storage[1748] = 8'h00; + storage[1749] = 8'h00; + storage[1750] = 8'h00; + storage[1751] = 8'h00; + storage[1752] = 8'h00; + storage[1753] = 8'h00; + storage[1754] = 8'h00; + storage[1755] = 8'h00; + storage[1756] = 8'h00; + storage[1757] = 8'h00; + storage[1758] = 8'h00; + storage[1759] = 8'h00; + storage[1760] = 8'h00; + storage[1761] = 8'h00; + storage[1762] = 8'h00; + storage[1763] = 8'h00; + storage[1764] = 8'h00; + storage[1765] = 8'h00; + storage[1766] = 8'h00; + storage[1767] = 8'h00; + storage[1768] = 8'h00; + storage[1769] = 8'h00; + storage[1770] = 8'h00; + storage[1771] = 8'h00; + storage[1772] = 8'h00; + storage[1773] = 8'h00; + storage[1774] = 8'h00; + storage[1775] = 8'h00; + storage[1776] = 8'h00; + storage[1777] = 8'h00; + storage[1778] = 8'h00; + storage[1779] = 8'h00; + storage[1780] = 8'h00; + storage[1781] = 8'h00; + storage[1782] = 8'h00; + storage[1783] = 8'h00; + storage[1784] = 8'h00; + storage[1785] = 8'h00; + storage[1786] = 8'h00; + storage[1787] = 8'h00; + storage[1788] = 8'h00; + storage[1789] = 8'h00; + storage[1790] = 8'h00; + storage[1791] = 8'h00; + storage[1792] = 8'h00; + storage[1793] = 8'h00; + storage[1794] = 8'h00; + storage[1795] = 8'h00; + storage[1796] = 8'h00; + storage[1797] = 8'h00; + storage[1798] = 8'h00; + storage[1799] = 8'h00; + storage[1800] = 8'h00; + storage[1801] = 8'h00; + storage[1802] = 8'h00; + storage[1803] = 8'h00; + storage[1804] = 8'h00; + storage[1805] = 8'h00; + storage[1806] = 8'h00; + storage[1807] = 8'h00; + storage[1808] = 8'h00; + storage[1809] = 8'h00; + storage[1810] = 8'h00; + storage[1811] = 8'h00; + storage[1812] = 8'h00; + storage[1813] = 8'h00; + storage[1814] = 8'h00; + storage[1815] = 8'h00; + storage[1816] = 8'h00; + storage[1817] = 8'h00; + storage[1818] = 8'h00; + storage[1819] = 8'h00; + storage[1820] = 8'h00; + storage[1821] = 8'h00; + storage[1822] = 8'h00; + storage[1823] = 8'h00; + storage[1824] = 8'h00; + storage[1825] = 8'h00; + storage[1826] = 8'h00; + storage[1827] = 8'h00; + storage[1828] = 8'h00; + storage[1829] = 8'h00; + storage[1830] = 8'h00; + storage[1831] = 8'h00; + storage[1832] = 8'h00; + storage[1833] = 8'h00; + storage[1834] = 8'h00; + storage[1835] = 8'h00; + storage[1836] = 8'h00; + storage[1837] = 8'h00; + storage[1838] = 8'h00; + storage[1839] = 8'h00; + storage[1840] = 8'h00; + storage[1841] = 8'h00; + storage[1842] = 8'h00; + storage[1843] = 8'h00; + storage[1844] = 8'h00; + storage[1845] = 8'h00; + storage[1846] = 8'h00; + storage[1847] = 8'h00; + storage[1848] = 8'h00; + storage[1849] = 8'h00; + storage[1850] = 8'h00; + storage[1851] = 8'h00; + storage[1852] = 8'h00; + storage[1853] = 8'h00; + storage[1854] = 8'h00; + storage[1855] = 8'h00; + storage[1856] = 8'h00; + storage[1857] = 8'h00; + storage[1858] = 8'h00; + storage[1859] = 8'h00; + storage[1860] = 8'h00; + storage[1861] = 8'h00; + storage[1862] = 8'h00; + storage[1863] = 8'h00; + storage[1864] = 8'h00; + storage[1865] = 8'h00; + storage[1866] = 8'h00; + storage[1867] = 8'h00; + storage[1868] = 8'h00; + storage[1869] = 8'h00; + storage[1870] = 8'h00; + storage[1871] = 8'h00; + storage[1872] = 8'h00; + storage[1873] = 8'h00; + storage[1874] = 8'h00; + storage[1875] = 8'h00; + storage[1876] = 8'h00; + storage[1877] = 8'h00; + storage[1878] = 8'h00; + storage[1879] = 8'h00; + storage[1880] = 8'h00; + storage[1881] = 8'h00; + storage[1882] = 8'h00; + storage[1883] = 8'h00; + storage[1884] = 8'h00; + storage[1885] = 8'h00; + storage[1886] = 8'h00; + storage[1887] = 8'h00; + storage[1888] = 8'h00; + storage[1889] = 8'h00; + storage[1890] = 8'h00; + storage[1891] = 8'h00; + storage[1892] = 8'h00; + storage[1893] = 8'h00; + storage[1894] = 8'h00; + storage[1895] = 8'h00; + storage[1896] = 8'h00; + storage[1897] = 8'h00; + storage[1898] = 8'h00; + storage[1899] = 8'h00; + storage[1900] = 8'h00; + storage[1901] = 8'h00; + storage[1902] = 8'h00; + storage[1903] = 8'h00; + storage[1904] = 8'h00; + storage[1905] = 8'h00; + storage[1906] = 8'h00; + storage[1907] = 8'h00; + storage[1908] = 8'h00; + storage[1909] = 8'h00; + storage[1910] = 8'h00; + storage[1911] = 8'h00; + storage[1912] = 8'h00; + storage[1913] = 8'h00; + storage[1914] = 8'h00; + storage[1915] = 8'h00; + storage[1916] = 8'h00; + storage[1917] = 8'h00; + storage[1918] = 8'h00; + storage[1919] = 8'h00; + storage[1920] = 8'h00; + storage[1921] = 8'h00; + storage[1922] = 8'h00; + storage[1923] = 8'h00; + storage[1924] = 8'h00; + storage[1925] = 8'h00; + storage[1926] = 8'h00; + storage[1927] = 8'h00; + storage[1928] = 8'h00; + storage[1929] = 8'h00; + storage[1930] = 8'h00; + storage[1931] = 8'h00; + storage[1932] = 8'h00; + storage[1933] = 8'h00; + storage[1934] = 8'h00; + storage[1935] = 8'h00; + storage[1936] = 8'h00; + storage[1937] = 8'h00; + storage[1938] = 8'h00; + storage[1939] = 8'h00; + storage[1940] = 8'h00; + storage[1941] = 8'h00; + storage[1942] = 8'h00; + storage[1943] = 8'h00; + storage[1944] = 8'h00; + storage[1945] = 8'h00; + storage[1946] = 8'h00; + storage[1947] = 8'h00; + storage[1948] = 8'h00; + storage[1949] = 8'h00; + storage[1950] = 8'h00; + storage[1951] = 8'h00; + storage[1952] = 8'h00; + storage[1953] = 8'h00; + storage[1954] = 8'h00; + storage[1955] = 8'h00; + storage[1956] = 8'h00; + storage[1957] = 8'h00; + storage[1958] = 8'h00; + storage[1959] = 8'h00; + storage[1960] = 8'h00; + storage[1961] = 8'h00; + storage[1962] = 8'h00; + storage[1963] = 8'h00; + storage[1964] = 8'h00; + storage[1965] = 8'h00; + storage[1966] = 8'h00; + storage[1967] = 8'h00; + storage[1968] = 8'h00; + storage[1969] = 8'h00; + storage[1970] = 8'h00; + storage[1971] = 8'h00; + storage[1972] = 8'h00; + storage[1973] = 8'h00; + storage[1974] = 8'h00; + storage[1975] = 8'h00; + storage[1976] = 8'h00; + storage[1977] = 8'h00; + storage[1978] = 8'h00; + storage[1979] = 8'h00; + storage[1980] = 8'h00; + storage[1981] = 8'h00; + storage[1982] = 8'h00; + storage[1983] = 8'h00; + storage[1984] = 8'h00; + storage[1985] = 8'h00; + storage[1986] = 8'h00; + storage[1987] = 8'h00; + storage[1988] = 8'h00; + storage[1989] = 8'h00; + storage[1990] = 8'h00; + storage[1991] = 8'h00; + storage[1992] = 8'h00; + storage[1993] = 8'h00; + storage[1994] = 8'h00; + storage[1995] = 8'h00; + storage[1996] = 8'h00; + storage[1997] = 8'h00; + storage[1998] = 8'h00; + storage[1999] = 8'h00; + storage[2000] = 8'h00; + storage[2001] = 8'h00; + storage[2002] = 8'h00; + storage[2003] = 8'h00; + storage[2004] = 8'h00; + storage[2005] = 8'h00; + storage[2006] = 8'h00; + storage[2007] = 8'h00; + storage[2008] = 8'h00; + storage[2009] = 8'h00; + storage[2010] = 8'h00; + storage[2011] = 8'h00; + storage[2012] = 8'h00; + storage[2013] = 8'h00; + storage[2014] = 8'h00; + storage[2015] = 8'h00; + storage[2016] = 8'h00; + storage[2017] = 8'h00; + storage[2018] = 8'h00; + storage[2019] = 8'h00; + storage[2020] = 8'h00; + storage[2021] = 8'h00; + storage[2022] = 8'h00; + storage[2023] = 8'h00; + storage[2024] = 8'h00; + storage[2025] = 8'h00; + storage[2026] = 8'h00; + storage[2027] = 8'h00; + storage[2028] = 8'h00; + storage[2029] = 8'h00; + storage[2030] = 8'h00; + storage[2031] = 8'h00; + storage[2032] = 8'h00; + storage[2033] = 8'h00; + storage[2034] = 8'h00; + storage[2035] = 8'h00; + storage[2036] = 8'h00; + storage[2037] = 8'h00; + storage[2038] = 8'h00; + storage[2039] = 8'h00; + storage[2040] = 8'h00; + storage[2041] = 8'h00; + storage[2042] = 8'h00; + storage[2043] = 8'h00; + storage[2044] = 8'h00; + storage[2045] = 8'h00; + storage[2046] = 8'h00; + end + always @(posedge clk) begin + if (storage_w_en) + storage[storage_w_addr] <= storage_w_data; + end + reg [7:0] _0_; + always @(posedge clk) begin + if (storage_r_en) begin + _0_ <= storage[storage_r_addr]; + end + end + assign storage_r_data = _0_; + assign \$11 = produce + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$14 = produce == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 11'h7fe; + assign \$13 = \$14 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 12'h000 : \$11 ; + assign \$17 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$20 = consume + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$23 = consume == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 11'h7fe; + assign \$22 = \$23 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 12'h000 : \$20 ; + assign \$26 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$2 = level != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) 11'h7ff; + assign \$29 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$28 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$29 ; + assign \$32 = \$26 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$28 ; + assign \$35 = level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) 1'h1; + assign \$37 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$40 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$39 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$40 ; + assign \$43 = \$37 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$39 ; + assign \$46 = level - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) 1'h1; + assign \$4 = | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) level; + assign \$6 = w_en & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) w_rdy; + assign \$8 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + always @(posedge clk) + level <= \level$next ; + always @(posedge clk) + consume <= \consume$next ; + always @(posedge clk) + produce <= \produce$next ; + always @* begin + if (\initial ) begin end + \consume$next = consume; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" *) + casez (\$17 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" */ + 1'h1: + \consume$next = \$22 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \consume$next = 11'h000; + endcase + end + always @* begin + if (\initial ) begin end + \level$next = level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + casez (\$32 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" */ + 1'h1: + \level$next = \$35 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + casez (\$43 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" */ + 1'h1: + \level$next = \$46 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \level$next = 11'h000; + endcase + end + always @* begin + if (\initial ) begin end + \produce$next = produce; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" *) + casez (\$8 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" */ + 1'h1: + \produce$next = \$13 [10:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \produce$next = 11'h000; + endcase + end + assign \$10 = \$13 ; + assign \$19 = \$22 ; + assign \$34 = \$35 ; + assign \$45 = \$46 ; + assign storage_r_en = r_en; + assign r_data = storage_r_data; + assign storage_r_addr = consume; + assign storage_w_en = \$6 ; + assign storage_w_data = w_data; + assign storage_w_addr = produce; + assign r_level = level; + assign w_level = level; + assign r_rdy = \$4 ; + assign w_rdy = \$2 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.ipmi_bt.from_bmc_fifo.unbuffered" *) +(* generator = "nMigen" *) +module \unbuffered$2 (clk, reset_from_bmc_fifo, w_data, w_en, w_rdy, r_data, r_en, r_rdy, level, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$11 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$13 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$17 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$19 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) + wire \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$20 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$23 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$26 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$28 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$29 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$32 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [6:0] \$34 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [6:0] \$35 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$37 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$39 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) + wire \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$40 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$43 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [6:0] \$45 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [6:0] \$46 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) + wire \$6 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [5:0] consume = 6'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [5:0] \consume$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + output [5:0] level; + reg [5:0] level = 6'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + reg [5:0] \level$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [5:0] produce = 6'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [5:0] \produce$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [5:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:51" *) + input reset_from_bmc_fifo; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [5:0] storage_r_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [7:0] storage_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire storage_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [5:0] storage_w_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [7:0] storage_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire storage_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [5:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + reg [7:0] storage [62:0]; + initial begin + storage[0] = 8'h00; + storage[1] = 8'h00; + storage[2] = 8'h00; + storage[3] = 8'h00; + storage[4] = 8'h00; + storage[5] = 8'h00; + storage[6] = 8'h00; + storage[7] = 8'h00; + storage[8] = 8'h00; + storage[9] = 8'h00; + storage[10] = 8'h00; + storage[11] = 8'h00; + storage[12] = 8'h00; + storage[13] = 8'h00; + storage[14] = 8'h00; + storage[15] = 8'h00; + storage[16] = 8'h00; + storage[17] = 8'h00; + storage[18] = 8'h00; + storage[19] = 8'h00; + storage[20] = 8'h00; + storage[21] = 8'h00; + storage[22] = 8'h00; + storage[23] = 8'h00; + storage[24] = 8'h00; + storage[25] = 8'h00; + storage[26] = 8'h00; + storage[27] = 8'h00; + storage[28] = 8'h00; + storage[29] = 8'h00; + storage[30] = 8'h00; + storage[31] = 8'h00; + storage[32] = 8'h00; + storage[33] = 8'h00; + storage[34] = 8'h00; + storage[35] = 8'h00; + storage[36] = 8'h00; + storage[37] = 8'h00; + storage[38] = 8'h00; + storage[39] = 8'h00; + storage[40] = 8'h00; + storage[41] = 8'h00; + storage[42] = 8'h00; + storage[43] = 8'h00; + storage[44] = 8'h00; + storage[45] = 8'h00; + storage[46] = 8'h00; + storage[47] = 8'h00; + storage[48] = 8'h00; + storage[49] = 8'h00; + storage[50] = 8'h00; + storage[51] = 8'h00; + storage[52] = 8'h00; + storage[53] = 8'h00; + storage[54] = 8'h00; + storage[55] = 8'h00; + storage[56] = 8'h00; + storage[57] = 8'h00; + storage[58] = 8'h00; + storage[59] = 8'h00; + storage[60] = 8'h00; + storage[61] = 8'h00; + storage[62] = 8'h00; + end + always @(posedge clk) begin + if (storage_w_en) + storage[storage_w_addr] <= storage_w_data; + end + reg [7:0] _0_; + always @(posedge clk) begin + if (storage_r_en) begin + _0_ <= storage[storage_r_addr]; + end + end + assign storage_r_data = _0_; + assign \$11 = produce + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$14 = produce == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 6'h3e; + assign \$13 = \$14 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 7'h00 : \$11 ; + assign \$17 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$20 = consume + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$23 = consume == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 6'h3e; + assign \$22 = \$23 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 7'h00 : \$20 ; + assign \$26 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$2 = level != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) 6'h3f; + assign \$29 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$28 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$29 ; + assign \$32 = \$26 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$28 ; + assign \$35 = level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) 1'h1; + assign \$37 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$40 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$39 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$40 ; + assign \$43 = \$37 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$39 ; + assign \$46 = level - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) 1'h1; + assign \$4 = | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) level; + assign \$6 = w_en & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) w_rdy; + assign \$8 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + always @(posedge clk) + level <= \level$next ; + always @(posedge clk) + consume <= \consume$next ; + always @(posedge clk) + produce <= \produce$next ; + always @* begin + if (\initial ) begin end + \consume$next = consume; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" *) + casez (\$17 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" */ + 1'h1: + \consume$next = \$22 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_bmc_fifo) + 1'h1: + \consume$next = 6'h00; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \consume$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \level$next = level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + casez (\$32 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" */ + 1'h1: + \level$next = \$35 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + casez (\$43 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" */ + 1'h1: + \level$next = \$46 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_bmc_fifo) + 1'h1: + \level$next = 6'h00; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \level$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \produce$next = produce; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" *) + casez (\$8 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" */ + 1'h1: + \produce$next = \$13 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_bmc_fifo) + 1'h1: + \produce$next = 6'h00; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \produce$next = 6'h00; + endcase + end + assign \$10 = \$13 ; + assign \$19 = \$22 ; + assign \$34 = \$35 ; + assign \$45 = \$46 ; + assign storage_r_en = r_en; + assign r_data = storage_r_data; + assign storage_r_addr = consume; + assign storage_w_en = \$6 ; + assign storage_w_data = w_data; + assign storage_w_addr = produce; + assign r_level = level; + assign w_level = level; + assign r_rdy = \$4 ; + assign w_rdy = \$2 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.ipmi_bt.from_target_fifo.unbuffered" *) +(* generator = "nMigen" *) +module \unbuffered$3 (clk, reset_from_target_fifo, w_data, w_en, w_rdy, r_data, r_en, r_rdy, level, rst); + reg \initial = 0; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$10 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$11 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$13 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$14 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$17 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$19 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) + wire \$2 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$20 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire [6:0] \$22 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) + wire \$23 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$26 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$28 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$29 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + wire \$32 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [6:0] \$34 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) + wire [6:0] \$35 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) + wire \$37 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$39 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) + wire \$4 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$40 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + wire \$43 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [6:0] \$45 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) + wire [6:0] \$46 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) + wire \$6 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) + wire \$8 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [5:0] consume = 6'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:147" *) + reg [5:0] \consume$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + output [5:0] level; + reg [5:0] level = 6'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:121" *) + reg [5:0] \level$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [5:0] produce = 6'h00; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:146" *) + reg [5:0] \produce$next ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + output [7:0] r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + input r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:86" *) + wire [5:0] r_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + output r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/ipmi_bt.py:52" *) + input reset_from_target_fifo; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [5:0] storage_r_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire [7:0] storage_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:144" *) + wire storage_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [5:0] storage_w_addr; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire [7:0] storage_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:143" *) + wire storage_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + input [7:0] w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + input w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:81" *) + wire [5:0] w_level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + output w_rdy; + reg [7:0] storage [62:0]; + initial begin + storage[0] = 8'h00; + storage[1] = 8'h00; + storage[2] = 8'h00; + storage[3] = 8'h00; + storage[4] = 8'h00; + storage[5] = 8'h00; + storage[6] = 8'h00; + storage[7] = 8'h00; + storage[8] = 8'h00; + storage[9] = 8'h00; + storage[10] = 8'h00; + storage[11] = 8'h00; + storage[12] = 8'h00; + storage[13] = 8'h00; + storage[14] = 8'h00; + storage[15] = 8'h00; + storage[16] = 8'h00; + storage[17] = 8'h00; + storage[18] = 8'h00; + storage[19] = 8'h00; + storage[20] = 8'h00; + storage[21] = 8'h00; + storage[22] = 8'h00; + storage[23] = 8'h00; + storage[24] = 8'h00; + storage[25] = 8'h00; + storage[26] = 8'h00; + storage[27] = 8'h00; + storage[28] = 8'h00; + storage[29] = 8'h00; + storage[30] = 8'h00; + storage[31] = 8'h00; + storage[32] = 8'h00; + storage[33] = 8'h00; + storage[34] = 8'h00; + storage[35] = 8'h00; + storage[36] = 8'h00; + storage[37] = 8'h00; + storage[38] = 8'h00; + storage[39] = 8'h00; + storage[40] = 8'h00; + storage[41] = 8'h00; + storage[42] = 8'h00; + storage[43] = 8'h00; + storage[44] = 8'h00; + storage[45] = 8'h00; + storage[46] = 8'h00; + storage[47] = 8'h00; + storage[48] = 8'h00; + storage[49] = 8'h00; + storage[50] = 8'h00; + storage[51] = 8'h00; + storage[52] = 8'h00; + storage[53] = 8'h00; + storage[54] = 8'h00; + storage[55] = 8'h00; + storage[56] = 8'h00; + storage[57] = 8'h00; + storage[58] = 8'h00; + storage[59] = 8'h00; + storage[60] = 8'h00; + storage[61] = 8'h00; + storage[62] = 8'h00; + end + always @(posedge clk) begin + if (storage_w_en) + storage[storage_w_addr] <= storage_w_data; + end + reg [7:0] _0_; + always @(posedge clk) begin + if (storage_r_en) begin + _0_ <= storage[storage_r_addr]; + end + end + assign storage_r_data = _0_; + assign \$11 = produce + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$14 = produce == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 6'h3e; + assign \$13 = \$14 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 7'h00 : \$11 ; + assign \$17 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$20 = consume + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 1'h1; + assign \$23 = consume == (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 6'h3e; + assign \$22 = \$23 ? (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:93" *) 7'h00 : \$20 ; + assign \$26 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$2 = level != (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:133" *) 6'h3f; + assign \$29 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$28 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$29 ; + assign \$32 = \$26 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) \$28 ; + assign \$35 = level + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:167" *) 1'h1; + assign \$37 = r_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:139" *) r_en; + assign \$40 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + assign \$39 = ~ (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$40 ; + assign \$43 = \$37 & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) \$39 ; + assign \$46 = level - (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:169" *) 1'h1; + assign \$4 = | (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:134" *) level; + assign \$6 = w_en & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:152" *) w_rdy; + assign \$8 = w_rdy & (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:140" *) w_en; + always @(posedge clk) + level <= \level$next ; + always @(posedge clk) + consume <= \consume$next ; + always @(posedge clk) + produce <= \produce$next ; + always @* begin + if (\initial ) begin end + \consume$next = consume; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" *) + casez (\$17 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:163" */ + 1'h1: + \consume$next = \$22 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_target_fifo) + 1'h1: + \consume$next = 6'h00; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \consume$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \level$next = level; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" *) + casez (\$32 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:166" */ + 1'h1: + \level$next = \$35 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" *) + casez (\$43 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:168" */ + 1'h1: + \level$next = \$46 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_target_fifo) + 1'h1: + \level$next = 6'h00; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \level$next = 6'h00; + endcase + end + always @* begin + if (\initial ) begin end + \produce$next = produce; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" *) + casez (\$8 ) + /* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:154" */ + 1'h1: + \produce$next = \$13 [5:0]; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:262" *) + casez (reset_from_target_fifo) + 1'h1: + \produce$next = 6'h00; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \produce$next = 6'h00; + endcase + end + assign \$10 = \$13 ; + assign \$19 = \$22 ; + assign \$34 = \$35 ; + assign \$45 = \$46 ; + assign storage_r_en = r_en; + assign r_data = storage_r_data; + assign storage_r_addr = consume; + assign storage_w_en = \$6 ; + assign storage_w_data = w_data; + assign storage_w_addr = produce; + assign r_level = level; + assign w_level = level; + assign r_rdy = \$4 ; + assign w_rdy = \$2 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined.vuart_a" *) +(* generator = "nMigen" *) +module vuart_a(clk, w_data, w_rdy, w_en, r_data, r_rdy, r_en, irq, wb__adr, wb__dat_w, wb__dat_r, wb__cyc, wb__stb, wb__we, wb__ack, rst); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) + wire \$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) + wire [7:0] \$11 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:60" *) + wire [7:0] \$13 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) + wire [7:0] \$15 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) + wire \$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) + wire \$5 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) + wire \$7 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) + wire \$9 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:85" *) + wire dlab; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:74" *) + reg [7:0] dll = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:74" *) + reg [7:0] \dll$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:75" *) + reg [7:0] dlm = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:75" *) + reg [7:0] \dlm$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:63" *) + reg [7:0] fcr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:63" *) + reg [7:0] \fcr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + reg fsm_state = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + reg \fsm_state$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) + reg [3:0] ier = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) + reg [3:0] \ier$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:60" *) + reg [3:0] iir; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:48" *) + output irq; + reg irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:79" *) + wire is_read; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:78" *) + wire is_write; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:64" *) + reg [7:0] lcr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:64" *) + reg [7:0] \lcr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) + reg [4:0] mcr = 5'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) + reg [4:0] \mcr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:72" *) + reg [7:0] msr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:72" *) + reg [7:0] \msr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:44" *) + input [7:0] r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:46" *) + output r_en; + reg r_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:46" *) + reg \r_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:45" *) + input r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:89" *) + reg [7:0] read_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:73" *) + reg [7:0] scr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:73" *) + reg [7:0] \scr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:39" *) + output [7:0] w_data; + reg [7:0] w_data = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:39" *) + reg [7:0] \w_data$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:41" *) + output w_en; + reg w_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:41" *) + reg \w_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:40" *) + input w_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + output wb__ack; + reg wb__ack = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + reg \wb__ack$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input [2:0] wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + output [7:0] wb__dat_r; + reg [7:0] wb__dat_r = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + reg [7:0] \wb__dat_r$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input [7:0] wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input wb__we; + assign \$9 = \$5 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) \$7 ; + assign \$11 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) ier; + assign \$13 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:60" *) iir; + assign \$15 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) mcr; + assign \$1 = wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) wb__cyc; + assign \$3 = \$1 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) wb__we; + assign \$5 = wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) wb__cyc; + assign \$7 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) wb__we; + always @(posedge clk) + msr <= \msr$next ; + always @(posedge clk) + mcr <= \mcr$next ; + always @(posedge clk) + lcr <= \lcr$next ; + always @(posedge clk) + fcr <= \fcr$next ; + always @(posedge clk) + ier <= \ier$next ; + always @(posedge clk) + dlm <= \dlm$next ; + always @(posedge clk) + w_data <= \w_data$next ; + always @(posedge clk) + dll <= \dll$next ; + always @(posedge clk) + w_en <= \w_en$next ; + always @(posedge clk) + r_en <= \r_en$next ; + always @(posedge clk) + wb__dat_r <= \wb__dat_r$next ; + always @(posedge clk) + fsm_state <= \fsm_state$next ; + always @(posedge clk) + wb__ack <= \wb__ack$next ; + always @(posedge clk) + scr <= \scr$next ; + always @* begin + if (\initial ) begin end + \dlm$next = dlm; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" */ + 1'h1: + \dlm$next = wb__dat_w; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dlm$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \ier$next = ier; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:143" */ + default: + \ier$next = wb__dat_w[3:0]; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ier$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fcr$next = fcr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + \fcr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fcr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \lcr$next = lcr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + \lcr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \lcr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \mcr$next = mcr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:152" */ + 3'h4: + \mcr$next = wb__dat_w[4:0]; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mcr$next = 5'h00; + endcase + end + always @* begin + if (\initial ) begin end + \msr$next = msr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:152" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:155" */ + 3'h6: + \msr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \msr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \scr$next = scr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:152" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:155" */ + 3'h6: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:158" */ + 3'h7: + \scr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \scr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \wb__ack$next = wb__ack; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + \wb__ack$next = 1'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + \wb__ack$next = 1'h1; + endcase + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:211" */ + 1'h1: + \wb__ack$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$next = fsm_state; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + \fsm_state$next = 1'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + \fsm_state$next = 1'h1; + endcase + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:211" */ + 1'h1: + \fsm_state$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fsm_state$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wb__dat_r$next = wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:166" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:167" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" */ + 1'h1: + \wb__dat_r$next = dll; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:170" */ + default: + \wb__dat_r$next = read_data; + endcase + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:175" */ + 3'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:176" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:176" */ + 1'h1: + \wb__dat_r$next = dlm; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:178" */ + default: + \wb__dat_r$next = \$11 ; + endcase + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:181" */ + 3'h2: + \wb__dat_r$next = \$13 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:184" */ + 3'h3: + \wb__dat_r$next = lcr; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:187" */ + 3'h4: + \wb__dat_r$next = \$15 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:190" */ + 3'h5: + begin + { \wb__dat_r$next [7], \wb__dat_r$next [4:2] } = 4'h0; + \wb__dat_r$next [0] = r_rdy; + \wb__dat_r$next [1] = 1'h0; + \wb__dat_r$next [5] = 1'h1; + \wb__dat_r$next [6] = 1'h1; + end + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:202" */ + 3'h6: + \wb__dat_r$next = msr; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:205" */ + 3'h7: + \wb__dat_r$next = scr; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \wb__dat_r$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + read_data = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:91" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:91" */ + 1'h1: + read_data = r_data; + endcase + end + always @* begin + if (\initial ) begin end + \r_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:166" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:167" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:170" */ + default: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:172" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:172" */ + 1'h1: + \r_en$next = 1'h1; + endcase + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \w_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:135" */ + default: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:137" *) + casez (w_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:137" */ + 1'h1: + \w_en$next = 1'h1; + endcase + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \w_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + irq = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" *) + casez (ier[1]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" */ + 1'h1: + irq = 1'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" *) + casez (ier[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" */ + 1'h1: + irq = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + iir = 4'h1; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" *) + casez (ier[1]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" */ + 1'h1: + iir = 4'h2; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" *) + casez (ier[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" */ + 1'h1: + iir = 4'h4; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dll$next = dll; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" */ + 1'h1: + \dll$next = wb__dat_w; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dll$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \w_data$next = w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:135" */ + default: + \w_data$next = wb__dat_w; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \w_data$next = 8'h00; + endcase + end + assign dlab = lcr[7]; + assign is_read = \$9 ; + assign is_write = \$3 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined.vuart_b" *) +(* generator = "nMigen" *) +module vuart_b(clk, w_data, w_rdy, w_en, r_data, r_rdy, r_en, irq, wb__adr, wb__dat_w, wb__dat_r, wb__cyc, wb__stb, wb__we, wb__ack, rst); + reg \initial = 0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) + wire \$1 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) + wire [7:0] \$11 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:60" *) + wire [7:0] \$13 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) + wire [7:0] \$15 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) + wire \$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) + wire \$5 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) + wire \$7 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) + wire \$9 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:85" *) + wire dlab; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:74" *) + reg [7:0] dll = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:74" *) + reg [7:0] \dll$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:75" *) + reg [7:0] dlm = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:75" *) + reg [7:0] \dlm$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:63" *) + reg [7:0] fcr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:63" *) + reg [7:0] \fcr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + reg fsm_state = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + reg \fsm_state$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) + reg [3:0] ier = 4'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) + reg [3:0] \ier$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:60" *) + reg [3:0] iir; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:48" *) + output irq; + reg irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:79" *) + wire is_read; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:78" *) + wire is_write; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:64" *) + reg [7:0] lcr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:64" *) + reg [7:0] \lcr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) + reg [4:0] mcr = 5'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) + reg [4:0] \mcr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:72" *) + reg [7:0] msr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:72" *) + reg [7:0] \msr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:44" *) + input [7:0] r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:46" *) + output r_en; + reg r_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:46" *) + reg \r_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:45" *) + input r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:89" *) + reg [7:0] read_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:73" *) + reg [7:0] scr = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:73" *) + reg [7:0] \scr$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:39" *) + output [7:0] w_data; + reg [7:0] w_data = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:39" *) + reg [7:0] \w_data$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:41" *) + output w_en; + reg w_en = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:41" *) + reg \w_en$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:40" *) + input w_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + output wb__ack; + reg wb__ack = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + reg \wb__ack$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input [2:0] wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + output [7:0] wb__dat_r; + reg [7:0] wb__dat_r = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + reg [7:0] \wb__dat_r$next ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input [7:0] wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + input wb__we; + assign \$9 = \$5 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) \$7 ; + assign \$11 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:57" *) ier; + assign \$13 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:60" *) iir; + assign \$15 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:65" *) mcr; + assign \$1 = wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) wb__cyc; + assign \$3 = \$1 & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:81" *) wb__we; + assign \$5 = wb__stb & (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) wb__cyc; + assign \$7 = ~ (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:82" *) wb__we; + always @(posedge clk) + wb__dat_r <= \wb__dat_r$next ; + always @(posedge clk) + fsm_state <= \fsm_state$next ; + always @(posedge clk) + wb__ack <= \wb__ack$next ; + always @(posedge clk) + scr <= \scr$next ; + always @(posedge clk) + msr <= \msr$next ; + always @(posedge clk) + mcr <= \mcr$next ; + always @(posedge clk) + lcr <= \lcr$next ; + always @(posedge clk) + fcr <= \fcr$next ; + always @(posedge clk) + ier <= \ier$next ; + always @(posedge clk) + dlm <= \dlm$next ; + always @(posedge clk) + w_data <= \w_data$next ; + always @(posedge clk) + dll <= \dll$next ; + always @(posedge clk) + w_en <= \w_en$next ; + always @(posedge clk) + r_en <= \r_en$next ; + always @* begin + if (\initial ) begin end + \dlm$next = dlm; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" */ + 1'h1: + \dlm$next = wb__dat_w; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dlm$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \ier$next = ier; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:141" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:143" */ + default: + \ier$next = wb__dat_w[3:0]; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \ier$next = 4'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fcr$next = fcr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + \fcr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fcr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \lcr$next = lcr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + \lcr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \lcr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \mcr$next = mcr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:152" */ + 3'h4: + \mcr$next = wb__dat_w[4:0]; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \mcr$next = 5'h00; + endcase + end + always @* begin + if (\initial ) begin end + \msr$next = msr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:152" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:155" */ + 3'h6: + \msr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \msr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \scr$next = scr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:140" */ + 3'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:146" */ + 3'h2: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:149" */ + 3'h3: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:152" */ + 3'h4: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:155" */ + 3'h6: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:158" */ + 3'h7: + \scr$next = wb__dat_w; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \scr$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \wb__ack$next = wb__ack; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + \wb__ack$next = 1'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + \wb__ack$next = 1'h1; + endcase + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:211" */ + 1'h1: + \wb__ack$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$next = fsm_state; + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + \fsm_state$next = 1'h1; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + \fsm_state$next = 1'h1; + endcase + /* \nmigen.decoding = "ACK/1" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:211" */ + 1'h1: + \fsm_state$next = 1'h0; + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \fsm_state$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \wb__dat_r$next = wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:166" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:167" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" */ + 1'h1: + \wb__dat_r$next = dll; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:170" */ + default: + \wb__dat_r$next = read_data; + endcase + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:175" */ + 3'h1: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:176" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:176" */ + 1'h1: + \wb__dat_r$next = dlm; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:178" */ + default: + \wb__dat_r$next = \$11 ; + endcase + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:181" */ + 3'h2: + \wb__dat_r$next = \$13 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:184" */ + 3'h3: + \wb__dat_r$next = lcr; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:187" */ + 3'h4: + \wb__dat_r$next = \$15 ; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:190" */ + 3'h5: + begin + { \wb__dat_r$next [7], \wb__dat_r$next [4:2] } = 4'h0; + \wb__dat_r$next [0] = r_rdy; + \wb__dat_r$next [1] = 1'h0; + \wb__dat_r$next [5] = 1'h1; + \wb__dat_r$next [6] = 1'h1; + end + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:202" */ + 3'h6: + \wb__dat_r$next = msr; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:205" */ + 3'h7: + \wb__dat_r$next = scr; + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \wb__dat_r$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + read_data = 8'h00; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:91" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:91" */ + 1'h1: + read_data = r_data; + endcase + end + always @* begin + if (\initial ) begin end + \r_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:165" */ + 2'b1?: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:166" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:167" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:168" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:170" */ + default: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:172" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:172" */ + 1'h1: + \r_en$next = 1'h1; + endcase + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \r_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \w_en$next = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:135" */ + default: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:137" *) + casez (w_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:137" */ + 1'h1: + \w_en$next = 1'h1; + endcase + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \w_en$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + irq = 1'h0; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" *) + casez (ier[1]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" */ + 1'h1: + irq = 1'h1; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" *) + casez (ier[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" */ + 1'h1: + irq = 1'h1; + endcase + endcase + end + always @* begin + if (\initial ) begin end + iir = 4'h1; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" *) + casez (ier[1]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:111" */ + 1'h1: + iir = 4'h2; + endcase + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" *) + casez (ier[0]) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:119" */ + 1'h1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" *) + casez (r_rdy) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:121" */ + 1'h1: + iir = 4'h4; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \dll$next = dll; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" */ + 1'h1: + \dll$next = wb__dat_w; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \dll$next = 8'h00; + endcase + end + always @* begin + if (\initial ) begin end + \w_data$next = w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:127" *) + casez (fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:128" */ + 1'h0: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" *) + casez ({ is_read, is_write }) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:130" */ + 2'b?1: + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:131" *) + casez (wb__adr) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:132" */ + 3'h0: + (* full_case = 32'd1 *) + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" *) + casez (dlab) + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:133" */ + 1'h1: + /* empty */; + /* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:135" */ + default: + \w_data$next = wb__dat_w; + endcase + endcase + endcase + endcase + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \w_data$next = 8'h00; + endcase + end + assign dlab = lcr[7]; + assign is_read = \$9 ; + assign is_write = \$3 ; +endmodule + +(* \nmigen.hierarchy = "lpc_top.io.vuart_joined" *) +(* generator = "nMigen" *) +module vuart_joined(wb_b__ack, irq_b, rst, clk, wb_a__adr, wb_a__dat_w, wb_a__dat_r, wb_a__sel, wb_a__cyc, wb_a__stb, wb_a__we, wb_a__ack, wb_b__adr, wb_b__dat_w, wb_b__dat_r, wb_b__sel, wb_b__cyc, wb_b__stb, wb_b__we, irq_a); + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [31:0] \$1 ; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input clk; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] fifo_a_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire fifo_a_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire fifo_a_r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] fifo_a_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire fifo_a_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire fifo_a_w_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:83" *) + wire [7:0] fifo_b_r_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:85" *) + wire fifo_b_r_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:84" *) + wire fifo_b_r_rdy; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:78" *) + wire [7:0] fifo_b_w_data; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:80" *) + wire fifo_b_w_en; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/lib/fifo.py:79" *) + wire fifo_b_w_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:23" *) + output irq_a; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:26" *) + output irq_b; + (* src = "/home/anton/.local/lib/python3.9/site-packages/nmigen-0.3.dev265+g11914a1-py3.9.egg/nmigen/hdl/ir.py:524" *) + input rst; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:48" *) + wire vuart_a_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:44" *) + wire [7:0] vuart_a_r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:46" *) + wire vuart_a_r_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:45" *) + wire vuart_a_r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:39" *) + wire [7:0] vuart_a_w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:41" *) + wire vuart_a_w_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:40" *) + wire vuart_a_w_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_a_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [2:0] vuart_a_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_a_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [7:0] vuart_a_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [7:0] vuart_a_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_a_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_a_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:48" *) + wire vuart_b_irq; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:44" *) + wire [7:0] vuart_b_r_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:46" *) + wire vuart_b_r_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:45" *) + wire vuart_b_r_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:39" *) + wire [7:0] vuart_b_w_data; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:41" *) + wire vuart_b_w_en; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:40" *) + wire vuart_b_w_rdy; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_b_wb__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [2:0] vuart_b_wb__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_b_wb__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [7:0] vuart_b_wb__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire [7:0] vuart_b_wb__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_b_wb__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire vuart_b_wb__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire wb__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) + wire \wb__sel$3 ; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output wb_a__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input [2:0] wb_a__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input wb_a__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + output [31:0] wb_a__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input [31:0] wb_a__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input [3:0] wb_a__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input wb_a__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:24" *) + input wb_a__we; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output wb_b__ack; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input [2:0] wb_b__adr; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input wb_b__cyc; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + output [7:0] wb_b__dat_r; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input [7:0] wb_b__dat_w; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input wb_b__sel; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input wb_b__stb; + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart_joined.py:27" *) + input wb_b__we; + assign \$1 = + (* src = "/home/anton/source/lpcperipheral/lpcperipheral/vuart.py:51" *) vuart_a_wb__dat_r; + fifo_a fifo_a ( + .clk(clk), + .r_data(fifo_a_r_data), + .r_en(fifo_a_r_en), + .r_rdy(fifo_a_r_rdy), + .rst(rst), + .w_data(fifo_a_w_data), + .w_en(fifo_a_w_en), + .w_rdy(fifo_a_w_rdy) + ); + fifo_b fifo_b ( + .clk(clk), + .r_data(fifo_b_r_data), + .r_en(fifo_b_r_en), + .r_rdy(fifo_b_r_rdy), + .rst(rst), + .w_data(fifo_b_w_data), + .w_en(fifo_b_w_en), + .w_rdy(fifo_b_w_rdy) + ); + vuart_a vuart_a ( + .clk(clk), + .irq(vuart_a_irq), + .r_data(vuart_a_r_data), + .r_en(vuart_a_r_en), + .r_rdy(vuart_a_r_rdy), + .rst(rst), + .w_data(vuart_a_w_data), + .w_en(vuart_a_w_en), + .w_rdy(vuart_a_w_rdy), + .wb__ack(vuart_a_wb__ack), + .wb__adr(vuart_a_wb__adr), + .wb__cyc(vuart_a_wb__cyc), + .wb__dat_r(vuart_a_wb__dat_r), + .wb__dat_w(vuart_a_wb__dat_w), + .wb__stb(vuart_a_wb__stb), + .wb__we(vuart_a_wb__we) + ); + vuart_b vuart_b ( + .clk(clk), + .irq(vuart_b_irq), + .r_data(vuart_b_r_data), + .r_en(vuart_b_r_en), + .r_rdy(vuart_b_r_rdy), + .rst(rst), + .w_data(vuart_b_w_data), + .w_en(vuart_b_w_en), + .w_rdy(vuart_b_w_rdy), + .wb__ack(vuart_b_wb__ack), + .wb__adr(vuart_b_wb__adr), + .wb__cyc(vuart_b_wb__cyc), + .wb__dat_r(vuart_b_wb__dat_r), + .wb__dat_w(vuart_b_wb__dat_w), + .wb__stb(vuart_b_wb__stb), + .wb__we(vuart_b_wb__we) + ); + assign wb_b__ack = vuart_b_wb__ack; + assign vuart_b_wb__we = wb_b__we; + assign vuart_b_wb__stb = wb_b__stb; + assign vuart_b_wb__cyc = wb_b__cyc; + assign \wb__sel$3 = wb_b__sel; + assign wb_b__dat_r = vuart_b_wb__dat_r; + assign vuart_b_wb__dat_w = wb_b__dat_w; + assign vuart_b_wb__adr = wb_b__adr; + assign wb_a__ack = vuart_a_wb__ack; + assign vuart_a_wb__we = wb_a__we; + assign vuart_a_wb__stb = wb_a__stb; + assign vuart_a_wb__cyc = wb_a__cyc; + assign wb__sel = wb_a__sel[0]; + assign wb_a__dat_r = \$1 ; + assign vuart_a_wb__dat_w = wb_a__dat_w[7:0]; + assign vuart_a_wb__adr = wb_a__adr; + assign irq_b = vuart_b_irq; + assign irq_a = vuart_a_irq; + assign fifo_a_r_en = vuart_b_r_en; + assign vuart_b_r_rdy = fifo_a_r_rdy; + assign vuart_b_r_data = fifo_a_r_data; + assign fifo_b_w_en = vuart_b_w_en; + assign vuart_b_w_rdy = fifo_b_w_rdy; + assign fifo_b_w_data = vuart_b_w_data; + assign fifo_b_r_en = vuart_a_r_en; + assign vuart_a_r_rdy = fifo_b_r_rdy; + assign vuart_a_r_data = fifo_b_r_data; + assign fifo_a_w_en = vuart_a_w_en; + assign vuart_a_w_rdy = fifo_a_w_rdy; + assign fifo_a_w_data = vuart_a_w_data; +endmodule diff --git a/microwatt.core b/microwatt.core index f463d90..0b562be 100644 --- a/microwatt.core +++ b/microwatt.core @@ -50,6 +50,7 @@ filesets: - sync_fifo.vhdl - spi_rxtx.vhdl - spi_flash_ctrl.vhdl + - lpc/lpc.v : {file_type : verilogSource} file_type : vhdlSource-2008 fpga: @@ -339,6 +340,7 @@ targets: - has_fpu - has_btc - has_short_mult + - has_lpc generate: [litedram_arty, liteeth_arty, litesdcard_arty] tools: vivado: {part : xc7a100ticsg324-1L} @@ -504,6 +506,12 @@ parameters: paramtype : generic default : false + has_lpc: + datatype : bool + description : Include an LPC slave in the SOC + paramtype : generic + default : false + disable_flatten_core: datatype : bool description : Prevent Vivado from flattening the main core components diff --git a/soc.vhdl b/soc.vhdl index b23336c..20e9af1 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -26,6 +26,7 @@ use work.wishbone_types.all; -- 0xc0006000: SPI Flash controller -- 0xc0007000: GPIO controller -- 0xc8nnnnnn: External IO bus +-- 0xcb000000: LPC slave (same addr as Kestral) -- 0xf0000000: Flash "ROM" mapping -- 0xff000000: DRAM init code (if any) or flash ROM (**) @@ -50,6 +51,8 @@ use work.wishbone_types.all; -- 2 : UART1 -- 3 : SD card -- 4 : GPIO +-- 5 : LPC UART +-- 6 : LPC IPMI entity soc is generic ( @@ -60,6 +63,7 @@ entity soc is HAS_FPU : boolean := true; HAS_BTC : boolean := true; HAS_SHORT_MULT : boolean := false; + HAS_LPC : boolean := false; DISABLE_FLATTEN_CORE : boolean := false; HAS_DRAM : boolean := false; DRAM_SIZE : integer := 0; @@ -129,6 +133,17 @@ entity soc is gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); + -- LPC signals + lpc_data_o : out std_ulogic_vector(3 downto 0); + lpc_data_oe : out std_ulogic; + lpc_data_i : in std_ulogic_vector(3 downto 0) := (others => '1'); + lpc_frame_n : in std_ulogic := '1'; + lpc_reset_n : in std_ulogic := '1'; + lpc_clock : in std_ulogic := '1'; + lpc_irq_o : out std_ulogic; + lpc_irq_oe : out std_ulogic; + lpc_irq_i : in std_ulogic := '0'; + -- DRAM controller signals alt_reset : in std_ulogic := '0' ); @@ -146,7 +161,7 @@ architecture behaviour of soc is -- Arbiter array (ghdl doesnt' support assigning the array -- elements in the entity instantiation) - constant NUM_WB_MASTERS : positive := 4; + constant NUM_WB_MASTERS : positive := 5; signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1); signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1); @@ -187,6 +202,26 @@ architecture behaviour of soc is signal wb_spiflash_is_reg : std_ulogic; signal wb_spiflash_is_map : std_ulogic; + -- LPC Flash controller signals: + signal wb_lpc_in : wb_io_master_out; + signal wb_lpc_out : wb_io_slave_out; + signal lpc_vuart_irq : std_ulogic; + signal lpc_ipmi_irq : std_ulogic; + + -- LPC master wb + signal lpc_master_wb_cyc : std_ulogic; + signal lpc_master_wb_stb : std_ulogic; + signal lpc_master_wb_err : std_ulogic; + signal lpc_master_wb_addr : std_ulogic_vector(29 downto 0); + + signal wb_lpc_dma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_lpc_dma_in : wb_io_slave_out; + signal wb_lpc_dma_nr : wb_io_master_out; + signal wb_lpc_dma_ir : wb_io_slave_out; + + -- for conversion from non-pipelined wishbone to pipelined + signal wb_lpc_dma_stb_sent : std_ulogic; + -- XICS signals: signal wb_xics_icp_in : wb_io_master_out; signal wb_xics_icp_out : wb_io_slave_out; @@ -225,6 +260,7 @@ architecture behaviour of soc is signal rst_core : std_ulogic := '1'; signal rst_uart : std_ulogic := '1'; signal rst_xics : std_ulogic := '1'; + signal rst_lpc : std_ulogic := '1'; signal rst_spi : std_ulogic := '1'; signal rst_gpio : std_ulogic := '1'; signal rst_bram : std_ulogic := '1'; @@ -243,6 +279,7 @@ architecture behaviour of soc is SLAVE_IO_SPI_FLASH_MAP, SLAVE_IO_GPIO, SLAVE_IO_EXTERNAL, + SLAVE_IO_LPC, SLAVE_IO_NONE); signal slave_io_dbg : slave_io_type; @@ -312,6 +349,7 @@ begin rst_spi <= rst; rst_xics <= rst; rst_gpio <= rst; + rst_lpc <= rst; rst_bram <= rst; rst_dtm <= rst; rst_wbar <= rst; @@ -360,11 +398,13 @@ begin wb_masters_out <= (0 => wishbone_dcore_out, 1 => wishbone_icore_out, 2 => wishbone_widen_data(wishbone_dma_out), - 3 => wishbone_debug_out); + 3 => wishbone_widen_data(wb_lpc_dma_out), + 4 => wishbone_debug_out); wishbone_dcore_in <= wb_masters_in(0); wishbone_icore_in <= wb_masters_in(1); wishbone_dma_in <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr); - wishbone_debug_in <= wb_masters_in(3); + wb_lpc_dma_in <= wishbone_narrow_data(wb_masters_in(3), wb_lpc_dma_out.adr); + wishbone_debug_in <= wb_masters_in(4); wishbone_arbiter_0: entity work.wishbone_arbiter generic map( NUM_MASTERS => NUM_WB_MASTERS @@ -616,6 +656,8 @@ begin slave_io := SLAVE_IO_UART1; elsif std_match(match, x"C8---") then slave_io := SLAVE_IO_EXTERNAL; + elsif std_match(match, x"CB---") then + slave_io := SLAVE_IO_LPC; elsif std_match(match, x"C0004") then slave_io := SLAVE_IO_ICP; elsif std_match(match, x"C0005") then @@ -636,6 +678,8 @@ begin wb_spiflash_is_map <= '0'; wb_gpio_in <= wb_sio_out; wb_gpio_in.cyc <= '0'; + wb_lpc_in <= wb_sio_out; + wb_lpc_in.cyc <= '0'; -- Only give xics 8 bits of wb addr (for now...) wb_xics_icp_in <= wb_sio_out; @@ -693,6 +737,9 @@ begin wb_sio_in <= wb_ext_io_out; end if; + when SLAVE_IO_LPC => + wb_lpc_in.cyc <= wb_sio_out.cyc; + wb_sio_in <= wb_lpc_out; when SLAVE_IO_SYSCON => wb_syscon_in.cyc <= wb_sio_out.cyc; wb_sio_in <= wb_syscon_out; @@ -892,6 +939,115 @@ begin wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack; end generate; + lpc_gen: if HAS_LPC generate + component lpc_top port ( + clk : in std_ulogic; + rst : in std_ulogic; + + lclk : in std_ulogic; + lframe : in std_ulogic; + lreset : in std_ulogic; + lad_en : out std_ulogic; + lad_out : out std_ulogic_vector(3 downto 0); + lad_in : in std_ulogic_vector(3 downto 0); + + adr : in std_ulogic_vector(13 downto 0); + dat_w : in std_ulogic_vector(31 downto 0); + dat_r : out std_ulogic_vector(31 downto 0); + ack : out std_ulogic; + cyc : in std_ulogic; + sel : in std_ulogic; + stb : in std_ulogic; + we : in std_ulogic; + + dma_adr : out std_ulogic_vector(29 downto 0); + dma_dat_w : out std_ulogic_vector(31 downto 0); + dma_dat_r : in std_ulogic_vector(31 downto 0); + dma_ack : in std_ulogic; + dma_cyc : out std_ulogic; + dma_sel : out std_ulogic_vector(3 downto 0); + dma_stb : out std_ulogic; + dma_we : out std_ulogic; + + bmc_ipmi_irq : out std_ulogic; + bmc_vuart_irq : out std_ulogic; + target_ipmi_irq : out std_ulogic; + target_vuart_irq : out std_ulogic + ); + end component; + begin + lpc0: lpc_top + port map( + rst => rst_lpc, + clk => system_clk, + + adr => wb_lpc_in.adr(13 downto 0), + dat_w => wb_lpc_in.dat(31 downto 0), + dat_r => wb_lpc_out.dat(31 downto 0), + ack => wb_lpc_out.ack, + cyc => wb_lpc_in.cyc, + sel => wb_lpc_in.sel(0), + stb => wb_lpc_in.stb, + we => wb_lpc_in.we, + + dma_adr => wb_lpc_dma_nr.adr(29 downto 0), + dma_dat_w => wb_lpc_dma_nr.dat(31 downto 0), + dma_dat_r => wb_lpc_dma_ir.dat(31 downto 0), + dma_sel => wb_lpc_dma_nr.sel, + dma_cyc => wb_lpc_dma_nr.cyc, + dma_stb => wb_lpc_dma_nr.stb, + dma_ack => wb_lpc_dma_ir.ack, + dma_we => wb_lpc_dma_nr.we, + + lclk => lpc_clock, + lframe => lpc_frame_n, + lreset => lpc_reset_n, + lad_out => lpc_data_o, + lad_in => lpc_data_i, + lad_en => lpc_data_oe, + + bmc_ipmi_irq => lpc_ipmi_irq, + bmc_vuart_irq => lpc_vuart_irq + ); + lpc_master_wb_err <= '0'; + lpc_irq_o <= '0'; + lpc_irq_oe <= '0'; + -- FIXME hook up irqs + + wb_lpc_out.stall <= not wb_lpc_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_lpc_dma_out <= wb_lpc_dma_nr; + if wb_lpc_dma_stb_sent = '1' or + (wb_lpc_dma_out.stb = '1' and wb_lpc_dma_in.stall = '0') then + wb_lpc_dma_out.stb <= '0'; + end if; + if wb_lpc_dma_nr.cyc = '0' or wb_lpc_dma_ir.ack = '1' then + wb_lpc_dma_stb_sent <= '0'; + elsif wb_lpc_dma_in.stall = '0' then + wb_lpc_dma_stb_sent <= wb_lpc_dma_nr.stb; + end if; + wb_lpc_dma_ir <= wb_lpc_dma_in; + end if; + end process; + + end generate; + + no_lpc_gen: if not HAS_LPC generate + lpc_data_o <= (others => '0'); + lpc_data_oe <= '0'; + lpc_irq_o <= '0'; + lpc_irq_oe <= '0'; + + wb_lpc_out.dat <= (others => '1'); + wb_lpc_out.ack <= wb_lpc_in.cyc and wb_lpc_in.stb; + wb_lpc_out.stall <= wb_lpc_in.cyc and not wb_lpc_out.ack; + end generate; + xics_icp: entity work.xics_icp port map( clk => system_clk, @@ -942,6 +1098,8 @@ begin int_level_in(2) <= uart1_irq; int_level_in(3) <= ext_irq_sdcard; int_level_in(4) <= gpio_intr; + int_level_in(5) <= lpc_vuart_irq; + int_level_in(6) <= lpc_ipmi_irq; end process; -- BRAM Memory slave